1. General description
The PCF8562 is a periphera l device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 32 segments. The PCF8562
is compatible with most microcontrollers and communicates via the two-line bidirectional
I2C-bus. Communication ove rheads are minimized by a display RAM with
auto-incremented addressing, by hardware subaddressing and by display memory
switching (static and duplex drive mo des).
2. Features and benefits
AEC-Q100 compliant (PCF8562TT/S400/2) for automotive applications
Single chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Internal LCD bias generation with voltage-follower buffers
32 segment dr ive s:
Up to sixteen 7-segment numeric characters
Up to eight 14-segment alphanumeric characters
Any graphics of up to 128 elements
32 4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent suppl ies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
From 2.5 V for low-threshold LCDs
Up to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs
Low power consum pt ion
400 kHz I2C-bu s in te rface
No external components required
Manufactured in silicon gate CMOS process
PCF8562
Universal LCD driver for low multiplex rates
Rev. 6 — 16 June 2011 Product data sheet
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.
PCF8562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 16 June 2011 2 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
3. Ordering information
[1] Not to be used for new designs. Replacement part is PCF85162T/1 for industrial applications.
[2] Not to be used for new designs. Replacement part is PCA85162T/Q900/1 for automotive applications.
4. Marking
Table 1. Ordering information
Type number Package
Name Description Version
PCF8562TT/2[1] TSSOP48 plastic thin shrink small outline package; 48 leads;
body width 6.1 mm SOT362-1
PCF8562TT/S400/2[2] TSSOP48 plastic thin shrink small outline package; 48 leads;
body width 6.1 mm SOT362-1
Table 2. Marking codes
Type number Marking code
PCF8562TT/2 PCF8562TT
PCF8562TT/S400/2 PCF8562TT/S400
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Product data sheet Rev. 6 — 16 June 2011 3 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
5. Block diagram
Fig 1. Block diagram of PCF8562
001aac262
LCD
VOLTAGE
SELECTOR
CLOCK SELECT
AND TIMING BLINKER
TIMEBASE
OSCILLATOR
INPUT
FILTERS I
2
C-BUS
CONTROLLER
POWER-ON
RESET
CLK
SYNC
OSC
SCL
SDA
SA0
BACKPLANE
OUTPUTS
DISPLAY
CONTROLLER
BP0
22
21
20
13
12
15
V
DD
14
11
10
19 16 17 18
23 24 25
BP2 BP1 BP3
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
OUTPUT BANK SELECT
AND BLINK CONTROL
26 to 48,
1 to 9
S0 to S31
A0 A1 A2
PCF8562
LCD BIAS
GENERATOR
V
SS
V
LCD
COMMAND
DECODER WRITE DATA
CONTROL
DISPLAY
RAM
40 × 4-BIT
DATA POINTER AND
AUTO INCREMENT
SUBADDRESS
COUNTER
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Product data sheet Rev. 6 — 16 June 2011 4 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
Top view. For mechanical details, see Figure 22.
Fig 2. Pinning diagram for TSSOP48 (PCF8562TT)
PCF8562TT
S23 S22
S24 S21
S25 S20
S26 S19
S27 S18
S28 S17
S29 S16
S30 S15
S31 S14
SDA S13
SCL S12
SYNC S11
CLK S10
VDD S9
OSC S8
A0 S7
A1 S6
A2 S5
SA0 S4
VSS S3
VLCD S2
BP0 S1
BP2 S0
BP1 BP3
001aac263
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
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Product data sheet Rev. 6 — 16 June 2011 5 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
6.2 Pin description
Table 3. Pin description
Symbol Pin Type Description
SDA 10 input/output I2C-bus se rial data line
SCL 11 input I2C-bus serial clock
SYNC 12 input/output cascade synchronization
CLK 13 input/output clock line
VDD 14 supply supply voltage
OSC 15 input internal oscil lator enable
A0 to A2 16 to 18 input subaddress inputs
SA0 19 input I2C-bus address input
VSS 20 supply ground supply voltage
VLCD 21 supply LCD supply voltage
BP0 to BP3 22 to 25 output LCD backplane outputs
S0 to S22,
S23 to S31 26 to 48,
1 to 9 output LCD segment outputs
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Product data sheet Rev. 6 — 16 June 2011 6 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7. Functional description
The PCF8562 is a versatile perip heral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It
can directly drive any static or multiplexed LCD containing u p to four backplane s and up to
32 segments.
The possible display configurations of the PCF8562 depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 4. All
of these configurations can be implemented in the typical system shown in Figure 4.
Fig 3. Example of displays suitable for PCF8562
Table 4. Selection of possible display configurations
Number of
Backplanes Icons Digits/Characters Dot matrix/
Elements
7-segment 14-segment
4 128 16 8 128 dots (4 32)
39612696dots (3 32)
2648464dots (2 32)
1324232dots (132)
7-segment with dot 14-segment with dot and accent
013aaa312
dot matrix
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Product data sheet Rev. 6 — 16 June 2011 7 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCF8562. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated intern ally.
The only other connections required to complete the system are to the po we r su pp lies
(VDD, VSS, and VLCD) and the LCD panel chosen for the application.
7.1 Power-On Reset (POR)
At power-on the PCF8562 resets to the following starting conditions:
•All backplane and segment outputs are set to VLCD
•The selected drive mode is: 1:4 multiplex with 1⁄3 bias
•Blinking is switched off
•Input and output bank selectors are reset
•The I2C-bus interface is initialized
•The data pointer and the subaddress counter are cleared (set to logic 0)
•Display is disabled
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltage s are obtained fr om an internal volt age divider con sisting of
three impedances connected in series between VLCD and VSS. The center impedance is
bypassed by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode
configuration is selected. The LCD voltage can be temperature compensated externally,
using the supply to pin VLCD.
7.3 LCD voltage selector
The LCD voltage selector coord ina te s th e mult iplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltag e selector is controlled by the
mode-set command from the command decode r. The biasing configurations that apply to
the preferred modes of o per ation , to gether with the bia sing chara cteristics as function s of
VLCD and the resulting discrimination ratios (D) are given in Table 5.
The resistance of the power lines must be kept to a minimum.
Fig 4. Typical system configuration
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
t
r
2C
b
SDA
SCL
OSC
32 segment drives
4 backplanes
LCD PANEL
(up to 128
elements)
PCF8562
A0
16
15
11
10 14 21
17 18 19 20
A1 A2 SA0
V
DD
V
SS
V
SS
V
DD
V
LCD
001aac264
R ≤
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Product data sheet Rev. 6 — 16 June 2011 8 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
Discrimination is a term which is defined as the ratio of the on and off RMS volt age across
a segment. It can be thought of as a measurement of contrast.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold volt age (Vth(off)) , typically when the LCD exhibit s approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD >3V
th(off).
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by , where the values for a are
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
(1)
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
(3)
Table 5. Biasing characteristics
LCD drive
mode Number of: LCD bias
configuration
Backplanes Levels
static 1 2 static 0 1
1:2 multiplex 2 3 1⁄20.354 0.791 2.236
1:2 multiplex 2 4 1⁄30.333 0.745 2.236
1:3 multiplex 3 4 1⁄30.333 0.638 1.915
1:4 multiplex 4 4 1⁄30.333 0.577 1.732
Voff RMS
VLCD
-------------------------
Von RMS
VLCD
------------------------
DVon RMS
Voff RMS
-------------------------=
1
1a+
-------------
Von RMS a22a n++
n1a+
2
------------------------------
VLCD
=
Voff RMS a22a–n+
n1a+
2
------------------------------
VLCD
=
DVon RMS
Voff RMS
-----------------------a22a n++
a22a–n+
---------------------------==
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Product data sheet Rev. 6 — 16 June 2011 9 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄2bias is and the discrimination for a n LCD drive mode of 1:4 multiplex with
1⁄2bias is .
The advanta ge of these LCD drive modes is a reduction of the LCD full scale volt age VLCD
as follows:
•1:3 multiplex (1⁄2 bias):
•1:4 multiplex (1⁄2 bias):
These compare with when 1⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are depende nt on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relat ive tran sm ission (at Vth(on)), see
Figure 5. For a good contrast performance, the following rules should be followed:
(4)
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and ar e affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
3 1.732=
21
3
---------- 1.528=
VLCD 6V
off RMS
2.449Voff RMS
==
VLCD 43
3
----------------------2.309Voff RMS
==
VLCD 3Voff RMS
=
Von RMS
Vth on
Voff RMS
Vth off
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Product data sheet Rev. 6 — 16 June 2011 10 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
Fig 5. Electro- optical characteristic: relative transmission curve of the liquid
VRMS [V]
100 %
90 %
10 %
OFF
SEGMENT
GREY
SEGMENT
ON
SEGMENT
Vth(off) Vth(on)
Relative Transmission
013aaa494
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Product data sheet Rev. 6 — 16 June 2011 11 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Figure 6.
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = V(Sn + 1)(t) VBP0(t).
Voff(RMS) = 0 V.
Fig 6. St atic drive mode waveforms
013aaa207
V
SS
V
LCD
V
SS
V
LCD
V
SS
V
LCD
V
LCD
−V
LCD
−V
LCD
V
LCD
state 1 0 V
BP0
Sn
Sn+1
state 2 0 V
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 1
(on) state 2
(off)
T
fr
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Product data sheet Rev. 6 — 16 June 2011 12 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backpla ne s ar e pr ov ide d in the LCD , the 1:2 multiple x mo d e ap plie s. The
PCF8562 allows the us e of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 7 and
Figure 8.
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.354VLCD.
Fig 7. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
013aaa208
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 2
state 1
VSS
VLCD
VLCD/2
VSS
VSS
VLCD
VLCD
VSS
VLCD
VLCD
VLCD
0 V
0 V
VLCD/2
VLCD/2
VLCD/2
−VLCD
−VLCD
−VLCD/2
−VLCD/2
Sn
Sn+1
Tfr
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Product data sheet Rev. 6 — 16 June 2011 13 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 8. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
013aaa209
state 1
BP0
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
−VLCD
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
Sn
Sn+1
Tfr
VSS
VLCD
2VLCD/3
VLCD/3
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Product data sheet Rev. 6 — 16 June 2011 14 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 9.
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 9. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
013aaa210
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
(a) Waveforms at driver.
BP2
Sn
Sn+1
Sn+2
Tfr
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
VSS
VLCD
2VLCD/3
VLCD/3
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Product data sheet Rev. 6 — 16 June 2011 15 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 10.
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
013aaa211
state 1
BP0
(b) Resultant waveforms
at LCD segment.
LCD segments
state 2
BP1
state 1
state 2
BP2
(a) Waveforms at driver.
BP3
Sn
Sn+1
Sn+2
Sn+3
Tfr
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
0 V
VLCD
2VLCD/3
−2VLCD/3
VLCD/3
−VLCD/3
−VLCD
VSS
VLCD
2VLCD/3
VLCD/3
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Product data sheet Rev. 6 — 16 June 2011 16 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clock
The internal lo gic of the PCF8562 a nd it s LCD drive signals are timed either by its internal
oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC
to pin VSS.
7.5.2 External clock
Pin CLK is enabled as an exter na l clock input by connecting pin O SC to VDD.
The LCD frame signal frequency is determined by the clock frequency (fclk).
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The PCF8562 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock fr equency from either
the internal or an external clock: .
7.7 Display register
The display register holds the display data while the corresponding multip lex signals are
generated.
7.8 Segment outputs
The LCD drive section includes 32 segment outputs S0 to S31 which should be
connected dir ec tly to the LC D. Th e segm e nt output signals are generated in accordance
with the multiplexed backplane signals and with data r esiding in the display latch. When
less than 32 segment outputs are required, the unused segment outputs should be left
open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outp uts can be left open-c ircu it.
•In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these
two adjacent outputs can be tied together to give enhanced drive capabilities.
•In the 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 carry the
same signals and may also be paired to increase the drive capa bilities.
•In the static drive mode the same signal is carried by all four backplane outputs and
they can be connected in parallel for very high drive requirements.
ffr fclk
24
-------
=
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Product data sheet Rev. 6 — 16 June 2011 17 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.10 Display RAM
The display RAM is a static 32 4-b it RAM which stores LCD dat a. The re is a one-to-one
correspond e nce between
•the bits in the RAM bitmap and the LCD elements
•the RAM columns and the se gm e nt outpu ts
•the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a log ic 0 indicates the off-state.
The display RAM bit map Figure 11 shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 31 which correspond with the
segment outputs S0 to S31. In multiplexed LCD applications the segment data of the first,
second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1,
BP2, and BP3 respectively.
When display dat a is transmitted to the PCF8562, the displa y bytes received are stored in
the display RAM in accordance with the selected LCD drive mode. The dat a is stored as it
arrives and depending on the current multiplex drive mode the bits are stored singularly , in
pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment
numeric display showing all drive modes is given in Figure 12; the RAM filling organization
depicted applies equally to other LCD types.
The display RAM bit map shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Fig 11. Display RAM bit map
0
0
1
2
3
1 2 3 4 27 28 29 30 31
display RAM addresses/segment outputs (S)
columns
display RAM rows/
backplane outputs
(BP)
rows
001aac265
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
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Product data sheet Rev. 6 — 16 June 2011 18 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
x = data bit unchanged.
Fig 12. Relationship between LCD layout, drive mode, display RAM filli ng order and display data transmitted over the I2C-bus
001aaj646
acbDPfegd
MSB LSB
bDPcadgfe
MSB LSB
abfgecdDP
MSB LSB
cbafgedDP
MSB LSB
drive mode
static
1:2
multiplex
1:3
multiplex
1:4
multiplex
LCD segments LCD backplanes display RAM filling order transmitted display byte
BP0
BP0
BP1
BP0
BP1 BP2
BP1
BP2
BP3
BP0
n
c
x
x
x
0
1
2
3
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
rows
display RAM
rows/backplane
outputs (BP)
byte1
columns
display RAM address/segment outputs (s)
n
a
b
x
x
0
1
2
3
f
g
x
x
e
c
x
x
d
DP
x
x
n + 1 n + 2 n + 3
byte1 byte2
rows
display RAM
rows/backplane
outputs (BP)
columns
display RAM address/segment outputs (s)
n
b
DP
c
x
0
1
2
3
a
d
g
x
f
e
x
x
n + 1 n + 2
byte1 byte2 byte3
rows
display RAM
rows/backplane
outputs (BP)
columns
display RAM address/segment outputs (s)
n + 1
n
a
c
b
DP
0
1
2
3
f
e
g
d
byte1 byte2 byte3 byte4 byte5
rows
display RAM
rows/backplane
outputs (BP)
columns
display RAM address/segment outputs (s)
Sn+2
Sn+3
Sn+1
Sn
DP
a
fb
g
ec
d
Sn+2
Sn+1
Sn+7
Sn
Sn+3
Sn+5
Sn+6
Sn+4
DP
a
fb
g
ec
d
Sn
Sn+1
Sn+2
DP
a
fb
g
ec
d
Sn+1
Sn
DP
a
fb
g
ec
d
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Product data sheet Rev. 6 — 16 June 2011 19 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
The following applies to Figure 12:
•In static drive mode the eight transmitted data bits are placed in row 0 as one byte.
•In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
•In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchang ed. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be t aken to avoid overwriting adjacent dat a because always fu ll bytes are
transmitted (see Section 7.10.3).
•In 1:4 multiplex drive mode , the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
7.10.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 12). Following this command,
an arriving data byte is stored at the display RAM address ind icated by the data pointer.
The filling order is shown in Figure 12.
After each byte is stored, the conten t of the da ta pointer is autom atically incremented by a
value dependent on the selected LCD drive mode:
•In static drive mode by eight
•In 1:2 multiplex drive mode by four
•In 1:3 multiplex drive mode by three
•In 1:4 multiplex drive mode by two
If an I2C-bus dat a access is terminated early then the st ate of the data poin ter is unknown.
The data pointer should be re-written prior to further RAM accesses.
7.10.2 Subaddress counter
The storage of display data is determined by the content of the subaddress counter.
Storage is allowed to t ake place only when the content of the subaddress counter
matches with the hardware subaddress applied to A0, A1, and A2. The subaddress
counter value is defined by the device-select command (see Table 13). If the content of
the subaddress counter and the hardware subaddress do not match then data storage is
inhibited but the data pointer is incremented as if data storage had taken place. The
subaddress counter is also incremented when the dat a pointer overflows.
The hardware subadd ress must not be changed while the device is being accesse d on the
I2C-bus interface.
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Universal LCD driver for low multiplex rates
7.10.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 6 (see Figure 12 as
well).
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 7.
In the case described in Table 7 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
•In the first write to the RAM, bits a7 to a0 are written.
•In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
•In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be consider ed in the module
layout process as well as in the driver software design.
7.10.4 Output bank selector
The output bank selector (see Table 14) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
•In 1:4 multiplex mode, all RAM addresses of ro w 0 are selected, these are followed b y
the content of row 1, 2, and then 3
•In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
Table 6. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0123456789:
0a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 :
1a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 :
2a5 a2 - b5 b2 - c5 c2 - d5 :
3----------:
Table 7. Entire RAM filling by re writing in 1:3 mult iplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0123456789:
0a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 :
1a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 :
2a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 :
3----------:
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Product data sheet Rev. 6 — 16 June 2011 21 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
•In 1:2 multiplex mode, rows 0 and 1 ar e se lect ed
•In static mode, row 0 is selected
The PCF8562 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. In the static drive mode, the bank-select command may request the content of
row 2 to be selected for display instead of the content of row 0. In the 1:2 multiplex mode,
the content of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
7.10.5 Input bank selector
The input bank sele cto r loads disp lay da ta into the dis pla y RAM in accordance with the
selected LCD drive configuration.
The bank-select command (see Table 14) can be used to load display data in row 2 in
static drive mode or in rows 2 and 3 in 1:2 mode. The input bank selector functions are
independent of the output bank selector.
7.11 Blinking
The display blinking capabilities of the PCF8562 are very versatile. The whole display can
blink at frequencies selected by the blink-select co mmand (see Table 15). The blink
frequencies are fractions of the clock frequency. The ratio between the clock and blink
frequencies depends on the blink mode selected (see Table 8).
An additional feature is for an arbitrary select ion of LCD eleme nts to blink. This applies to
the static and 1:2 multiplex drive mode s an d ca n be imple m en te d without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at th e blink frequency. This mode can
also be specified by the blink-sele ct command.
In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, group s of
LCD elements can blink by selectively changing the display RAM data at fixe d time
intervals.
[1] Blink modes 1, 2, and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz, and 2 Hz correspond to an
oscillator frequency (fclk) of 1536 Hz (see Section 12).
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 11).
Table 8. Blin king frequencies[1]
Blink mode Normal operating mode ra tio Nominal blink frequency
off - blinking off
12 Hz
21 Hz
3 0.5 Hz
fclk
768
----------
fclk
1536
-------------
fclk
3072
-------------
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Product data sheet Rev. 6 — 16 June 2011 22 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.12 Command decoder
The command decoder identifies command bytes that arr ive on the I2C-bus. The
commands available to the PCF8562 are defined in Table 9.
[1] Not used.
All available commands carry a continuation bit C in their most significant bit position as
shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to
arrive will also r epresent a command. If this bit is reset, it indicates that the command byte
is the last in the transfer. Further bytes will be regarded as display data (see Table 10).
Table 9. Definition of PCF8562 commands
Command Operation code Reference
Bit 76543210
mode-set C 1 0 -[1] E B M[1:0] Table 11
load-data-pointer C 0 0 P[4:0] Table 12
device-select C1100A[2:0] Table 13
bank-select C 1 1 1 1 0 I O Table 14
blink-select C 1 1 1 0 AB BF[1:0] Table 15
Table 10. C bit description
Bit Symbol Value Description
7C continue bit
0 last control byte in the transfer; next byte will be regarded
as display data
1 control bytes continue; next byte will be a command too
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NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
[1] The possibility to disable the display allows implementation of blinking under external control.
[2] Not applicable for static drive mode.
Table 11. M ode-set command bit description
Bit Symbol Value Description
7C0, 1see Table 10
6, 5 - 10 fixed value
4 - - unused
3E display status
0 disabled (blank)[1]
1 enabled
2B LCD bias configuration[2]
01⁄3 bias
11⁄2 bias
1 to 0 M[1:0] LCD drive mode selection
01 static; BP0
10 1:2 multiplex; BP0, BP1
11 1:3 multiplex; BP0, BP1, BP2
00 1:4 multiplex; BP0, BP1, BP2, BP3
Table 12. Load-data-pointer command bit description
Bit Symbol Value Description
7C0, 1see Table 10
6, 5 - 00 fixed value
4 to 0 P[4:0] 00000 to
11111 5 bit binary value, 0 to 31; transferred to the data pointer to
define one of 32 display RAM addresses
Table 13. Device-select command bit description
Bit Symbol Value Description
7C0, 1see Table 10
6 to 3 - 1100 fixed value
2 to 0 A[2:0] 000 to 111 3 bit binary value, 0 to 7; transferred to the subaddress
counter to define one of eight hardware subaddresses
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Product data sheet Rev. 6 — 16 June 2011 24 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.13 Display controller
The display controller executes the commands identified by the command decoder. It
contains the device’s status registers and coordinates their effects. The display controller
is also responsible for loading display dat a into the display RAM in the correct filling order.
Table 14. Bank-select command bit description
Bit Symbol Value Description
Static 1:2 multiplex[1]
7 C 0, 1 see Table 10
6 to 2 - 11110 fixed value
1I input bank selection; storage of arriving display data
0 RAM bit 0 RAM bits 0 and 1
1 RAM bit 2 RAM bits 2 and 3
0O output bank selec t io n; retrieval of LCD display data
0 RAM bit 0 RAM bits 0 and 1
1 RAM bit 2 RAM bits 2 and 3
Table 15. Blink-select command bit description
Bit Symbol Value Description
7C0, 1see Table 10
6 to 3 - 1110 fixed value
2AB blink mode selection
0 normal bl i n king[1]
1 alternate RAM bank blinking[2]
1 to 0 BF[1:0] blink frequency selection
00 off
01 1
10 2
11 3
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Product data sheet Rev. 6 — 16 June 2011 25 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
8. Characteristics of the I2C-bus
The I2C-bus is for bidirection al, two-line communication between dif ferent ICs or modules.
The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data b it is transferred durin g each clock pulse . The data on th e SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 13).
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the dat a line while the clock is HIGH is defined as the ST AR T
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 14).
8.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the ma ste r ar e th e sla ves (see Figure 15).
Fig 13. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 14. Definitio n of START and STOP condi tion s
mbc622
SDA
SCL P
STOP condition
SDA
SCL
S
START condition
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Product data sheet Rev. 6 — 16 June 2011 26 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
8.4 Acknowledge
The number of data bytes transf er re d be tween the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followe d by an acknowledge
cycle.
•A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
•A master receiver must generate an acknowledge after th e reception of each byte that
has been cloc ke d ou t of th e slave transmitte r.
•The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
•A master receiver must signal an end of dat a to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is illustrated in Figure 16.
Fig 15. System configuration
mga807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig 16. Acknowledgement of the I2C-bus
mbc602
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
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Product data sheet Rev. 6 — 16 June 2011 27 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
8.5 I2C-bus controller
The PCF8562 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8562 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8562.
The least significant bit of the slave address that a PCF8562 will respond to is defined by
the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to
a read acces s.
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus ma ster which is followed by one of two possible PCF8562
slave addresses available. All PCF8562s whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is
ignored by all PCF8562s whose SA0 inputs are set to the alternative level.
After an acknowledgement, one or more command bytes follow, that define the status of
each addressed PCF8562.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C, (see Figure 18). The command bytes are also acknowledged by all addressed
PCF8562s on the bu s.
Fig 17. I2C-bus protocol
Fig 18. Format of co mman d by te
S
A
0
S011100 0AC COMMAND A P
ADISPLAY DATA
slave address R/W acknowledge acknowledge
1 byte
update data pointers
n ≥ 1 byte(s) n ≥ 0 byte(s)
001aac266
msa833
REST OF OPCODE
C
MSB LSB
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Product data sheet Rev. 6 — 16 June 2011 28 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically
updated.
An acknowledgement, after each byte, is asserted only by the PCF8562s that are
addressed via addr ess lines A0, A1 and A2. After the last display byte, the I2C-bus master
asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus
access.
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Product data sheet Rev. 6 — 16 June 2011 29 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
9. Internal circuitry
Fig 19. Device protection circuits
SA0
VDD VDD
VSS VSS
VLCD
VSS
SDA
001aac269
VSS
SCL
VSS
CLK
VDD
VSS
OSC
VDD
VSS
SYNC
VDD
VSS
A0, A1, A2
VDD
VSS
BP0, BP1,
BP2, BP3
VLCD
VSS
S0 to S31
VLCD
VSS
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Product data sheet Rev. 6 — 16 June 2011 30 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
10. Limiting values
[1] Pass level; Human Body Model (HBM), according to Ref. 6 “JESD22-A114”.
[2] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.
[3] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.
[4] Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).
[5] According to the NXP store and transport requirements (see Ref. 11 “NX3-00092”) the devices have to be
stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products
deviant conditions are described in that document.
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed togeth er.
Table 16. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +6.5 V
VLCD LCD supply voltage 0.5 +7.5 V
VIinput voltage on each of the pins CLK,
SDA, SCL, SYNC, SA0,
OSC, A0 to A2
0.5 +6.5 V
VOoutput voltage on each of the pins S0 to
S31, BP0 to BP3 0.5 +7.5 V
IIinput current 10 +10 mA
IOoutput current 10 +10 mA
IDD supply current 50 +50 mA
IDD(LCD) LCD supply current 50 +50 mA
ISS ground supply current 50 +50 mA
Ptot total power dissipation - 400 mW
Pooutput power - 100 mW
Vesd electrostatic discharge
voltage HBM [1] -5000 V
MM [2] -200 V
CDM [3] -1500 V
Ilu latch-up current [4] - 300 mA
Tstg storage temperature [5] 65 +150 C
Tamb ambient temperature operating device 40 +85 C
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Product data sheet Rev. 6 — 16 June 2011 31 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
11. Static characteristics
[1] VLCD > 3 V for 1⁄3 bias.
[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-b u s inactive.
[3] The I2C-bus interface of PCF8562 is 5 V tolerant.
[4] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 16 (see Figure 19
as well).
[5] Propagation delay of driver between clock (CLK) and LCD driving signals.
[6] Periodically sampled, not 100 % tested.
[7] Outputs measured one at a time.
Table 17 . Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 1.8 - 5.5 V
VLCD LCD supply voltage [1] 2.5 - 6.5 V
IDD supply current fclk(ext) = 1536 Hz [2] -820A
IDD(LCD) LCD supply current fclk(ext) = 1536 Hz [2] -2460A
Logic[3]
VP(POR) power-on reset supply voltage 1.0 1.3 1.6 V
VIL LOW-level input voltage on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
VSS -0.3V
DD V
VIH HIGH-level input voltage on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
[4][5] 0.7VDD -V
DD V
IOL LOW-level output current output sink current;
VOL = 0.4 V; VDD =5V
on pins CLK and SYNC 1- - mA
on pin SDA 3 - - mA
IOH(CLK) HIGH-level output current on pin CLK output source current;
VOH =4.6V; V
DD =5V 1- - mA
ILleakage current VI=V
DD or VSS;
on pins CLK, SCL, SDA,
A0 to A2 and SA0
1- +1A
IL(OSC) leakage current on pin OSC VI=V
DD 1- +1A
CIinput capacitance [6] --7pF
LCD outputs
VOoutput voltage variation on pins BP0 to BP3 and
S0 to S31 100 - +100 mV
ROoutput resistance VLCD = 5 V [7]
on pins BP0 to BP3 - 1.5 - k
on pins S0 to S31 - 6.0 - k
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Product data sheet Rev. 6 — 16 June 2011 32 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
[1] Typical output duty factor: 50 % measured at the CLK output pin.
[2] Not tested in production.
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
Table 18. Dynam ic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Clock
fclk(int) internal clock frequency [1] 1440 1850 2640 Hz
fclk(ext) external clock frequency 960 - 2640 Hz
tclk(H) HIGH-level clock time 60 - - s
tclk(L) LOW-level clock time 60 - - s
Synchronization
tPD(SYNC_N) SYNC propagation delay - 30 - ns
tSYNC_NL SYNC LOW time 1 - - s
tPD(drv) driver propagation delay VLCD = 5 V [2] --30s
I2C-bus[3]
Pin SCL
fSCL SCL clock frequency - - 400 kHz
tLOW LOW period of the SCL clock 1.3 - - s
tHIGH HIGH period of the SCL clock 0.6 - - s
Pin SDA
tSU;DAT data set-up time 100 - - ns
tHD;DAT data hold ti me 0 - - ns
Pins SCL and SDA
tBUF bus free time between a STOP and
START condition 1.3 - - s
tSU;STO set-up time for STOP condition 0.6 - - s
tHD;STA hold time (repeated) START condition 0.6 - - s
tSU;STA set-up time for a repeated START
condition 0.6 - - s
trrise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 s
fSCL < 125 kHz - - 1.0 s
tffall time of both SDA and SCL signals - - 0.3 s
Cbcapacitive load for each bus line - - 400 pF
tw(spike) spike pulse width on the I2C-bus--50ns
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Product data sheet Rev. 6 — 16 June 2011 33 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
Fig 20. Driver timing waveforms
Fig 21. I2C-bus timing waveforms
013aaa493
0.7V
DD
0.3V
DD
0.7V
DD
0.3V
DD
SYNC
CLK
0.5 V
0.5 V
t
PD(drv)
t
PD(SYNC_N)
BP0 to BP3,
and S0 to S31
t
PD(SYNC_N)
t
SYNC_NL
(V
DD
= 5 V)
1/f
clk
t
clk(L)
t
clk(H)
SDA
mga728
SDA
SCL
tSU;STA tSU;STO
tHD;STA
tBUF tLOW
tHD;DAT tHIGH
tr
tf
tSU;DAT
PCF8562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 16 June 2011 34 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
13. Application information
13.1 Multiple chip operation
For large display co nfigurations or for more segments (> 128 elements) to drive please
refer to the PCF8576D device.
The contact re sistance between the SYNC inp ut/output on each cascaded device must be
controlled. If the resistance is too high, the device will not be able to synchronize properly;
this is particularly applicable to chip-on-glass applications. The maximum SYNC contact
resistance allowed for the number of devices in cascade is given in Table 19.
14. Test information
14.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
Table 19. SYNC contact resistance
Number of devices Maximum contact resist ance
2 6000
3to5 2200
6to10 1200
10 to 16 700
PCF8562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 16 June 2011 35 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
15. Package outline
Fig 22. Package outline SOT362-1 (TSSOP48)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
PCF8562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 16 June 2011 36 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent
standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
W ave soldering is a joining te chnology in which the joints are m ade by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solde r lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperatur e profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orie ntation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering ve rsus SnPb soldering
PCF8562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 16 June 2011 37 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
17.3 Wave soldering
Key characteristics in wave soldering are:
•Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are :
•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 23) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) an d cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on p ackage thickness and volume and is classified in accordance with
Table 20 and 21
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 23.
Table 20. SnPb eutectic process (from J-STD-0 20C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 21. Lead-free pr ocess (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
PCF8562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 16 June 2011 38 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
For further informa tion on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Abbreviations
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
Table 22. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
CDM Charged-Device Model
HBM Human Body Model
ITO Indium Tin Oxide
LCD Liquid Crystal Display
LSB Least Significant Bit
MM Machine Model
MSB Most Significant Bit
MSL Moisture Sensitivity Level
PCB Printed Ci rcu i t Boa rd
RAM Random Access Memory
RMS Root Mean Square
SCL Serial Clock Line
SDA Serial Data line
SMD Surface Mount Device
PCF8562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 16 June 2011 39 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
19. References
[1] AN10365 — Surface mount reflow soldering description
[2] AN10853 — ESD and EMC sensitivity of IC
[3] IEC 60134 — Rating syst ems for electronic tubes and valves and analogous
semiconductor devices
[4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[5] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[6] JESD22-A114 — Elec trostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[8] JESD22-C10 1 — Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[9] JESD78 — IC Latch-Up Test
[10] JESD625-A — Requirements for Handling Electrosta tic-Discharge-Sensitive
(ESDS) Devices
[11] NX3-00092 — NXP store and transport requirements
[12] SNV-FA-01-02 — Marking Formats Integrated Circuits
[13] UM10204 — I2C-bus specification and user manual
PCF8562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 16 June 2011 40 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
20. Revision history
Table 23. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCF8562 v.6 20110 616 Product data sheet - PCF8562_5
Modifications: •Added design-in and replacemen t part information
•Added Section 7.10.3
PCF8562_5 20100519 Product data sheet - PCF8562_4
PCF8562_4 20090318 Product data sheet - PCF8562_3
PCF8562_3 20081202 Product data sheet - PCF8562_2
PCF8562_2 20070122 Product data sheet - PCF8562_1
PCF8562_1 20050801 Product data sheet - -
PCF8562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 16 June 2011 41 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
21. Legal information
21.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semicondu ctors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use i n automotive
applications. The product is not designed, authorized or warranted to be
suitable for use in medica l, military, aircraft, space or life support equipment,
nor in applications where failure or malf unction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo m er(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter m s and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property right s.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product develop ment.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contain s t he product specification.
PCF8562 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 16 June 2011 42 of 43
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
21.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
I2C-bus — logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 June 2011
Document identifier: PCF8562
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
23. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 6
7.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 7
7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7
7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7
7.3.1 Electro-optical performance . . . . . . . . . . . . . . . 9
7.4 LCD drive mode waveforms. . . . . . . . . . . . . . 11
7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 11
7.4.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 12
7.4.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 14
7.4.4 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 15
7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.5.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.5.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 16
7.6 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.7 Display register. . . . . . . . . . . . . . . . . . . . . . . . 16
7.8 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16
7.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 16
7.10 Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.10.1 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.10.2 Subaddress cou nter . . . . . . . . . . . . . . . . . . . . 19
7.10.3 RAM writing in 1:3 multiplex drive mode. . . . . 20
7.10.4 Output bank selector . . . . . . . . . . . . . . . . . . . 20
7.10.5 Input bank selector. . . . . . . . . . . . . . . . . . . . . 21
7.11 Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.12 Command decoder. . . . . . . . . . . . . . . . . . . . . 22
7.13 Display controller . . . . . . . . . . . . . . . . . . . . . . 24
8 Charac teristics of the I2C-bus . . . . . . . . . . . . 25
8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.2 START and STOP conditions . . . . . . . . . . . . . 25
8.3 System configuration . . . . . . . . . . . . . . . . . . . 25
8.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.5 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 27
8.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.7 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 27
9 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 29
10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 30
11 Static characteristics. . . . . . . . . . . . . . . . . . . . 31
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 32
13 Application information . . . . . . . . . . . . . . . . . 34
13.1 Multiple chip operation. . . . . . . . . . . . . . . . . . 34
14 Test information . . . . . . . . . . . . . . . . . . . . . . . 34
14.1 Quality information. . . . . . . . . . . . . . . . . . . . . 34
15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 35
16 Handling information . . . . . . . . . . . . . . . . . . . 36
17 Soldering of SMD packages. . . . . . . . . . . . . . 36
17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 36
17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 36
17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 37
17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 37
18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38
19 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
20 Revision history . . . . . . . . . . . . . . . . . . . . . . . 40
21 Legal information . . . . . . . . . . . . . . . . . . . . . . 41
21.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 41
21.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41
21.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42
22 Contact information . . . . . . . . . . . . . . . . . . . . 42
23 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
