SERIAL PRESENCE DETECT PC133 SODIMM PC133 Unbuffered SDRAM SODIMM(144pin) SPD Specification Rev. 1.2 March. 2000 Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM * Revision History [Revision 0.0] Oct. 11, 1999 Jedec based PC133 SODIMM SPD Published. [Revision 0.1] Dec. 27, 1999 Add 64Mb D-Die based Module SPD. [Revision 1.0] Jan. 24, 2000 Change SPD reference to Intel 1.2B version. Changed SPD revision code(byte62) from 02h based to 12h. [Revision 1.1] Feb. 10, 2000 Typo correction. [Revision 1.2] March. 10, 2000 Add 128Mb C-die/256Mb B-die based Module SPD. * SPD Spec List M464S0424CT1-L75/C75 M464S0424DT1-L75/C75 M464S0824CT1-L75/C75 M464S0824DT1-L75/C75 M464S0924BT1-L75/C75 M464S0924CT1-L75/C75 M464S1724BT1-L75/C75 M464S1724CT1-L75/C75 M464S1654AT1-L75/C75 M464S1654BT1-L75/C75 M464S3254AT1-L75/C75 M464S3254BT1-L75/C75 Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S0424CT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 4MX64 *Composition : 4MX16 *4 *Used component part # : K4S641632C-TL75/TC75 *# of rows in module : 1 row *# of banks in component : 4 banks *Feature : 1,000 mil height & double sided component *Refresh : 4K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 54h 2 11 DIMM configuraion type Non parity 00h 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 12 0Ch 1 8 08h 1 1 Row 01h 15.625us, support self refresh 80h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 1 Row of 32MB 08h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 Function described Function Supported Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM Configuration) 75 Manufacturer part # (Data bits) 76 77 Intel 1.2B 12h - 9Bh Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 0 30h 80 ...... Manufacturer part # (Module depth) 4 34h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 2 32h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) C 43h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 1 31h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Week) 94 L C 4Ch Note 43h 7 37h 5 35h Blank 20h 1 31h C-die (4th Gen.) 43h - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 Reserved - 64h 6 Reserved Detailed PC100 Information 8Dh 6 Undefined - 5 126 127 128+ Unused storage locations Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S0424DT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 4MX64 *Composition : 4MX16 *4 *Used component part # : K4S641632D-TL75/TC75 *# of rows in module : 1 row *# of banks in component : 4 banks *Feature : 1,000 mil height & double sided component *Refresh : 4K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 54h 2 11 DIMM configuraion type Non parity 00h 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 12 0Ch 1 8 08h 1 1 Row 01h 15.625us, support self refresh 80h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 1 Row of 32MB 08h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 Function described Function Supported Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM Configuration) 75 Manufacturer part # (Data bits) 76 77 Intel 1.2B 12h - 9Bh Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 0 30h 80 ...... Manufacturer part # (Module depth) 4 34h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 2 32h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) D 44h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 1 31h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Week) 94 L C 4Ch Note 43h 7 37h 5 35h Blank 20h 1 31h D-die (5th Gen.) 44h - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 Reserved - 64h 6 Reserved Detailed PC100 Information 8Dh 6 Undefined - 5 126 127 128+ Unused storage locations Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S0824CT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 8MX64 *Composition : 4MX16 *8 *Used component part # : K4S641632C-TL75/TC75 *# of rows in module : 2 rows *# of banks in component : 4 banks *Feature : 1,250 mil height & double sided component *Refresh : 4K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 54h 2 11 DIMM configuraion type Non parity 00h 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 12 0Ch 1 8 08h 1 2 Rows 02h 15.625us, support self refresh 80h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 2 Rows of 32MB 08h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 Function described Function Supported Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM Configuration) 75 Manufacturer part # (Data bits) 76 77 Intel 1.2B 12h - 9Ch Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 0 30h 80 ...... Manufacturer part # (Module depth) 8 38h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 2 32h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) C 43h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 1 31h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Week) 94 L C 4Ch Note 43h 7 37h 5 35h Blank 20h 1 31h C-die (4th Gen.) 43h - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 Reserved - 64h 6 Reserved Detailed PC100 Information CDh 6 Undefined - 5 126 127 128+ Unused storage locations Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S0824DT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 8MX64 *Composition : 4MX16 *8 *Used component part # : K4S641632D-TL75/TC75 *# of rows in module : 2 rows *# of banks in component : 4 banks *Feature : 1,250 mil height & double sided component *Refresh : 4K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 54h 2 11 DIMM configuraion type Non parity 00h 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 12 0Ch 1 8 08h 1 2 Rows 02h 15.625us, support self refresh 80h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 2 Rows of 32MB 08h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 Function described Function Supported Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM Configuration) 75 Manufacturer part # (Data bits) 76 77 Intel 1.2B 12h - 9Ch Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 0 30h 80 ...... Manufacturer part # (Module depth) 8 38h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 2 32h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) D 44h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 1 31h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Week) 94 L C 4Ch Note 43h 7 37h 5 35h Blank 20h 1 31h D-die (5th Gen.) 44h - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 Reserved - 64h 6 Reserved Detailed PC100 Information CDh 6 Undefined - 5 126 127 128+ Unused storage locations Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S0924BT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 8Mx64 *Composition : 8Mx16 *4 *Used component part # : K4S281632B-TL75/TC75 *# of rows in module : 1 row *# of banks in component : 4 banks *Feature : 1,000 mil height & double sided component *Refresh : 4K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 54h 2 11 DIMM configuraion type Non parity 00h 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 12 0Ch 1 9 09h 1 1 Row 01h 15.625us, support self refresh 80h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 1 Row of 64MB 10h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 36~61 Function described Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 Function Supported ...... Manufacturer JEDEC ID code Intel 1.2B 12h - A4h Samsung CEh Samsung 00h Onyang Korea 01h Manufacturer part # (Memory module) M 4Dh Manufacturer part # (DIMM Configuration) 4 34h Blank 20h 72 Manufacturing location 73 74 75 Manufacturer part # (Data bits) 76 ...... Manufacturer part # (Data bits) 6 36h 77 ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 0 30h 80 ...... Manufacturer part # (Module depth) 9 39h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 2 32h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) B 42h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 86 Manufacturer part # (Hyphen) 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 1 31h "-" 2Dh L C 7 4Ch Note 43h 37h 5 35h Blank 20h 1 31h 92 ...... Manufacturer revision code (For component) B-die (3rd Gen.) 42h 93 Manufacturing date (Week) - - 3 94 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~12 Manufacturer specific data (may be used in future) Undefined - 5 126 Reserved - 64h 6 127 Reserved Detailed PC100 Information 8Dh 6 128+ Unused storage locations Undefined - 5 Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung's own purpose. 6. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S0924CT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 8Mx64 *Composition : 8Mx16 *4 *Used component part # : K4S281632C-TL75/TC75 *# of rows in module : 1 row *# of banks in component : 4 banks *Feature : 1,000 mil height & double sided component *Refresh : 4K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 54h 2 11 DIMM configuraion type Non parity 00h 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 12 0Ch 1 9 09h 1 1 Row 01h 15.625us, support self refresh 80h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 1 Row of 64MB 10h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 36~61 Function described Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 Function Supported ...... Manufacturer JEDEC ID code Intel 1.2B 12h - A4h Samsung CEh Samsung 00h Onyang Korea 01h Manufacturer part # (Memory module) M 4Dh Manufacturer part # (DIMM Configuration) 4 34h Blank 20h 72 Manufacturing location 73 74 75 Manufacturer part # (Data bits) 76 ...... Manufacturer part # (Data bits) 6 36h 77 ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 0 30h 80 ...... Manufacturer part # (Module depth) 9 39h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 2 32h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) C 43h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 86 Manufacturer part # (Hyphen) 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 1 31h "-" 2Dh L C 7 4Ch Note 43h 37h 5 35h Blank 20h 1 31h 92 ...... Manufacturer revision code (For component) C-die (4th Gen.) 43h 93 Manufacturing date (Week) - - 3 94 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~12 Manufacturer specific data (may be used in future) Undefined - 5 126 Reserved - 64h 6 127 Reserved Detailed PC100 Information 8Dh 6 128+ Unused storage locations Undefined - 5 Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung's own purpose. 6. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S1724BT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 16MX64 *Composition : 8MX16 *8 *Used component part # : K4S281632B-TL75/TC75 *# of rows in module : 2 rows *# of banks in component : 4 banks *Feature : 1,250 mil height & double sided component *Refresh : 4K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 54h 2 11 DIMM configuraion type Non parity 00h 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 12 0Ch 1 9 09h 1 2 Rows 02h 15.625us, support self refresh 80h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 2 Rows of 64MB 10h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 Function described Function Supported Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM Configuration) 75 Manufacturer part # (Data bits) 76 77 Intel 1.2B 12h - A5h Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 1 31h 80 ...... Manufacturer part # (Module depth) 7 37h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 2 32h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) B 42h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 1 31h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Week) 94 L C 4Ch Note 43h 7 37h 5 35h Blank 20h 1 31h B-die (3rd Gen.) 42h - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 Reserved - 64h 6 Reserved Detailed PC100 Information CDh 6 Undefined - 5 126 127 128+ Unused storage locations Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung's own purpose. 6. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S1724CT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 16MX64 *Composition : 8MX16 *8 *Used component part # : K4S281632C-TL75/TC75 *# of rows in module : 2 rows *# of banks in component : 4 banks *Feature : 1,250 mil height & double sided component *Refresh : 4K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 54h 2 11 DIMM configuraion type Non parity 00h 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 12 0Ch 1 9 09h 1 2 Rows 02h 15.625us, support self refresh 80h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 2 Rows of 64MB 10h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 Function described Function Supported Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM Configuration) 75 Manufacturer part # (Data bits) 76 77 Intel 1.2B 12h - A5h Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 1 31h 80 ...... Manufacturer part # (Module depth) 7 37h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 2 32h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) C 43h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 1 31h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Week) 94 L C 4Ch Note 43h 7 37h 5 35h Blank 20h 1 31h C-die (4th Gen.) 43h - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 Reserved - 64h 6 Reserved Detailed PC100 Information CDh 6 Undefined - 5 126 127 128+ Unused storage locations Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung's own purpose. 6. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S1654AT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 16MX64 *Composition : 16MX16 *4 *Used component part # : K4S561632A-TL75/TC75 *# of rows in module : 1 row *# of banks in component : 4 banks *Feature : 1,000 mil height & double sided component *Refresh : 8K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 2 11 DIMM configuraion type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 13 0Dh 1 9 09h 1 1 Row 01h 5.4ns 54h Non parity 00h 7.8us, support self refresh self 82h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 1 Row of 128MB 20h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 Function described Function Supported Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM Configuration) 75 Manufacturer part # (Data bits) 76 77 Intel 1.2B 12h - B7h Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 1 31h 80 ...... Manufacturer part # (Module depth) 6 36h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 5 35h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) A 41h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 1 31h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Week) 94 L C 4Ch Note 43h 7 37h 5 35h Blank 20h 1 31h A-die (2nd Gen.) 41h - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 Reserved - 64h 6 Reserved Detailed PC100 Information 8Dh 6 Undefined - 5 126 127 128+ Unused storage locations Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung's own purpose. 6. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S1654BT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 16MX64 *Composition : 16MX16 *4 *Used component part # : K4S561632B-TL75/TC75 *# of rows in module : 1 row *# of banks in component : 4 banks *Feature : 1,000 mil height & double sided component *Refresh : 8K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 2 11 DIMM configuraion type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 13 0Dh 1 9 09h 1 1 Row 01h 5.4ns 54h Non parity 00h 7.8us, support self refresh self 82h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 1 Row of 128MB 20h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 Function described Function Supported Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM Configuration) 75 Manufacturer part # (Data bits) 76 77 Intel 1.2B 12h - B7h Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 1 31h 80 ...... Manufacturer part # (Module depth) 6 36h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 5 35h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) B 42h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 1 31h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Week) 94 L C 4Ch Note 43h 7 37h 5 35h Blank 20h 1 31h B-die (3rd Gen.) 42h - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 Reserved - 64h 6 Reserved Detailed PC100 Information 8Dh 6 Undefined - 5 126 127 128+ Unused storage locations Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung's own purpose. 6. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S3254AT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 32MX64 *Composition : 16MX16 *8 *Used component part # : K4S561632A-TL75/TC75 *# of rows in module : 2 rows *# of banks in component : 4 banks *Feature : 1,250 mil height & double sided component *Refresh : 8K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 2 11 DIMM configuraion type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 13 0Dh 1 9 09h 1 2 Rows 02h 5.4ns 54h Non parity 00h 7.8us, support self refresh self 82h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 2 Rows of 128MB 20h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 Function described Function Supported Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM Configuration) 75 Manufacturer part # (Data bits) 76 77 Intel 1.2B 12h - B8h Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 3 33h 80 ...... Manufacturer part # (Module depth) 2 32h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 5 35h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) A 41h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 1 31h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Week) 94 L C 4Ch Note 43h 7 37h 5 35h Blank 20h 1 31h A-die (2nd Gen.) 41h - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 Reserved - 64h 6 Reserved Detailed PC100 Information CDh 6 Undefined - 5 126 127 128+ Unused storage locations Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung's own purpose. 6. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM M464S3254BT1-L75/C75(Intel SPD 1.2B ver. based) *Organization : 32MX64 *Composition : 16MX16 *8 *Used component part # : K4S561632B-TL75/TC75 *# of rows in module : 2 rows *# of banks in component : 4 banks *Feature : 1,250 mil height & double sided component *Refresh : 8K/64ms *Contents : Byte # Function described Function Supported Hex value -75 -75 128bytes 80h 256bytes (2K-bit) 08h Note 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly LVTTL 01h 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 75h 2 10 SDRAM access time from clock @CAS latency of 3 2 11 DIMM configuraion type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock dealy for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 13 0Dh 1 9 09h 1 2 Rows 02h 5.4ns 54h Non parity 00h 7.8us, support self refresh self 82h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 3 04h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & redundant addressing 00h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 - 00h 2 24 SDRAM access time @CAS latency of 2 - 00h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 20ns 14h 28 Minimum row active to row active delay (tRRD) 15ns 0Fh 29 Minimum RAS to CAS delay (=tRCD) 20ns 14h 30 Minimum activate precharge time (=tRAS) 45ns 2Dh 31 Module Row density 2 Rows of 128MB 20h 32 Command and Address signal input setup time 1.5ns 15h 33 Command and Address signal input hold time 0.8ns 08h 34 Data signal input setup time 1.5ns 15h Rev. 1.2 March. 2000 SERIAL PRESENCE DETECT PC133 SODIMM SERIAL PRESENCE DETECT INFORMATION Byte # 35 Function described Function Supported Hex value -75 -75 0.8ns 08h - 00h Data signal input hold time 36~61 Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 ...... Manufacturer JEDEC ID code 72 Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM Configuration) 75 Manufacturer part # (Data bits) 76 77 Intel 1.2B 12h - B8h Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 4 34h Blank 20h ...... Manufacturer part # (Data bits) 6 36h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 3 33h 80 ...... Manufacturer part # (Module depth) 2 32h 81 Manufacturer part # (Refresh, #of banks in Comp. & Inter- 5 35h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) B 42h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 1 31h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 89 Manufacturer part # (Minimum cycle time) 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Week) 94 L C 4Ch Note 43h 7 37h 5 35h Blank 20h 1 31h B-die (3rd Gen.) 42h - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 Reserved - 64h 6 Reserved Detailed PC100 Information CDh 6 Undefined - 5 126 127 128+ Unused storage locations Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsungs own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung's own purpose. 6. These values apply to PC100 applications only, per Intel PC66/PC100 SPD standards. Rev. 1.2 March. 2000