74AHC30; 74AHCT30 8-input NAND gate Rev. 4 -- 22 July 2015 Product data sheet 1. General description The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC30; 74AHCT30 provides an 8-input NAND function. 2. Features and benefits Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: For 74AHC30: CMOS level For 74AHCT30: TTL level ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number 74AHC30D Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm SOT762-1 40 C to +125 C XQFN12 SOT1174-1 74AHCT30D 74AHC30PW 74AHCT30PW 74AHC30BQ 74AHCT30BQ 74AHC30GU12 plastic, extremely thin quad flat package; no leads; 12 terminals; body 1.70 2.00 0.50 mm 74AHC30; 74AHCT30 Nexperia 8-input NAND gate 4. Marking Table 2. Marking codes Type number Marking 74AHC30D 74AHC30D 74AHCT30D 74AHCT30D 74AHC30PW AHC30 74AHCT30PW AHCT30 74AHC30BQ AHC30 74AHCT30BQ AHT30 74AHC30GU12 A3[1] [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram $ % & ' ( ) * + < PQD PQD Pin numbers are shown for SO14, TSSOP14 and DHVQFN14 packages only Fig 1. Logic symbol Pin numbers are shown for SO14, TSSOP14 and DHVQFN14 packages only Fig 2. IEC logic symbol $ % & ' < ( PQD ) * + Fig 3. Logic diagram 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 2 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate 6. Pinning information 6.1 Pinning $ WHUPLQDO LQGH[DUHD $+& $+&7 9&& $+& $+&7 % QF $ 9&& & + % QF ' * & + * ( ' ( QF ) ) QF *1' < *1' QF *1' < QF DDN 7UDQVSDUHQWWRSYLHZ DDL (1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad, however if it is soldered the solder land should remain floating or be connected to GND Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 WHUPLQDO LQGH[DUHD $ 9&& $+& QF + & * ' < ( ) *1' % DDD 7UDQVSDUHQWWRSYLHZ Fig 6. Pin configuration XQFN12 (SOT1174-1) 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 3 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate 6.2 Pin description Table 3. Symbol A Pin description Pin Description SO14, TSSOP14 and DHVQFN14 XQFN12 1 1 data input B 2 2 data input C 3 3 data input D 4 4 data input E 5 5 data input F 6 7 data input GND 7 6 ground (0 V) Y 8 8 data output n.c. 9 - not connected n.c. 10 - not connected G 11 9 data input H 12 10 data input n.c. 13 11 not connected VCC 14 12 supply voltage 7. Functional description Table 4. Function table[1] Input Output A B C D E F G H Y L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don't care. 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 4 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7.0 V VI input voltage 0.5 +7.0 V IIK input clamping current VI < 0.5 V [1] 20 - mA IOK output clamping current VO <0.5 V or VO > VCC + 0.5 V [1] 20 +20 mA IO output current VO =0.5 V to (VCC + 0.5 V) 25 +25 mA ICC supply current - +75 mA IGND ground current 75 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 500 mW - 250 mW Tamb = 40 C to +125 C [2] SO14, TSSOP14 and DHVQFN14 XQFN12 [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 packages: above 70 C, the value of Ptot derates linearly at 8 mW/K. For TSSOP14 packages: above 60 C, the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN14 packages: above 60 C, the value of Ptot derates linearly at 4.5 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate 74AHC_AHCT30 Product data sheet Conditions 74AHC30 74AHCT30 Unit Min Typ Max Min Typ Max 2.0 5.0 5.5 4.5 5.0 5.5 V 0 - 5.5 0 - 5.5 V 0 - VCC 0 - VCC V 40 +25 +125 40 +25 +125 C VCC = 3.3 V 0.3 V - - 100 - - - ns/V VCC = 5.0 V 0.5 V - - 20 - - 20 ns/V All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 5 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V 74AHC30 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 50 A; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = 50 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = 8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 A; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 A II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 A CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - - pF 74AHC_AHCT30 Product data sheet VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = VCC or GND All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 6 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate Table 7. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74AHCT30 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.80 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 A IO = 8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 A ICC additional per input pin; supply current VI = VCC 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - - pF VI = VCC or GND 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 C Conditions Min Typ[1] 40 C to +85 C Max 40 C to +125 C Unit Min Max Min Max 74AHC30 tpd propagation delay A, B, C, D, E, F, G, H to Y; see Figure 7 and 8 [2] VCC = 3.0 V to 3.6 V CL = 15 pF - 5.0 9.5 1.0 11.0 1.0 12.0 ns CL = 50 pF - 6.7 12.0 1.0 14.5 1.0 15.5 ns - 3.6 6.5 1.0 7.5 1.0 8.0 ns - 4.9 8.0 1.0 9.5 1.0 10.5 ns - 10 - - - - - pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power fi = 1 MHz; dissipation VI = GND to VCC capacitance 74AHC_AHCT30 Product data sheet [3] All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 7 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 C Conditions Min Typ[1] 40 C to +85 C Max 40 C to +125 C Unit Min Max Min Max 74AHCT30; VCC = 4.5 V to 5.5 V propagation delay tpd A, B, C, D, E, F, G, H to Y; see Figure 7 and 8 [2] CL = 15 pF CL = 50 pF [3] power fi = 1 MHz; dissipation VI = GND to VCC capacitance CPD - 3.3 6.5 1.0 7.5 1.0 8.0 ns - 4.7 8.5 1.0 9.5 1.0 10.5 ns - 12 - - - - - pF [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of the outputs. 12. Waveforms 9, $%&' ()*+ LQSXW *1' 90 W3+/ W3/+ 92+ 90 <RXWSXW PQD 92/ Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Input to output propagation delays Table 9. Measurement points Type Input Output VM VM 74AHC30 0.5 VCC 0.5 VCC 74AHCT30 1.5 V 0.5 VCC 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 8 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate 9, QHJDWLYH SXOVH W: 90 90 *1' WI 9, WI SRVLWLYH SXOVH *1' WU WU 90 90 W: 9&& * 9, 92 '87 57 &/ DDK Test data is given in Table 10. Definitions for test circuit: RT = termination resistance should be equal to the output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 8. Test circuit for measuring switching times Table 10. Test data Type Input Load Test VI tr, tf CL 74AHC30 VCC 3.0 ns 15 pF, 50 pF tPLH, tPHL 74AHCT30 3.0 V 3.0 ns 15 pF, 50 pF tPLH, tPHL 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 9 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate 13. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ = 4 $ $ $ $ SLQLQGH[ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP LQFKHV R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG Fig 9. 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7( Package outline SOT108-1 (SO14) 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 10 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ = 4 $ SLQLQGH[ $ $ $ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7( 02 Fig 10. Package outline SOT402-1 (TSSOP14) 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 11 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate '+94)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP % ' 627 $ $ $ ( F GHWDLO; WHUPLQDO LQGH[DUHD WHUPLQDO LQGH[DUHD & H H Y Z E & $ % & \ \ & / (K H N 'K ; N PP VFDOH 'LPHQVLRQV PPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PD[ QRP PLQ PP $ $ E F ' 'K ( (K H H N / Y Z \ \ 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 2XWOLQH YHUVLRQ 627 5HIHUHQFHV ,(& -('(& -(,7$ VRWBSR (XURSHDQ SURMHFWLRQ ,VVXHGDWH 02 Fig 11. Package outline SOT762-1 (DHVQFN14) 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 12 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate ;4)1SODVWLFH[WUHPHO\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 ; % ' $ WHUPLQDO LQGH[DUHD $ ( $ $ GHWDLO; & & $ % & Y Z E \ & \ H H WHUPLQDO LQGH[DUHD / / PP VFDOH 'LPHQVLRQV 8QLW $ PD[ QRP PLQ PP $ $ E ' ( H H / / Y Z \ \ 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 627 02 VRWBSR (XURSHDQ SURMHFWLRQ ,VVXHGDWH Fig 12. Package outline SOT1174-1 (XQFN12) 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 13 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT30 v.4 20150722 Product data sheet - 74AHC_AHCT30 v.3 - 74AHC_AHCT30 v.2 Modifications: 74AHC_AHCT30 v.3 Modifications: * Added type number 74AHC30GU12. 20090626 * * * Product data sheet Section 3: DHVQFN14 package added. Section 8: derating values added for DHVQFN14 package. Section 13: outline drawing added for DHVQFN14 package. 74AHC_AHCT30 v.2 20080530 Product data sheet - 74AHC_AHCT30 v.1 74AHC_AHCT30 v.1 19991130 Product specification - - 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 14 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes -- Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74AHC_AHCT30 Product data sheet Suitability for use -- Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the Nexperia product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). Nexperia does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 15 of 17 74AHC30; 74AHCT30 Nexperia 8-input NAND gate Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74AHC_AHCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 22 July 2015 (c) Nexperia B.V. 2017. All rights reserved 16 of 17 Nexperia 74AHC30; 74AHCT30 8-input NAND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 (c) General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 22 July 2015