INFINEON Tec hnologies 1 8.00
HYS 64/72V16300/32220GU
SDRAM-Modules
3.3 V 16M × 64/72-Bit 1 Bank SDRAM Module
3.3 V 32M × 64/72-Bit 2 Bank SDRAM Module
168-Pin Unbuffered DIMM Modules
The HYS 64(72)V16300GU and HYS 64(72)V32220GU are industry-standard 168-pin 8-byte Dual
In-line Memory Modules (DIMMs) which are organized as 16M ×64, 16M ×72 in 1 bank and
32M ×64 and 32M ×72 in two banks of high-speed memory arrays designed with 128Mbit
Synchronous DRAMs (SDRAMs) for non-parity and ECC ap plications. The DIMMs use -7 speed
sorted 16M ×8 SDRAM devices in TSOP54 packages to me et the PC133- 222 requi rements, -7.5
speed sorted for PC133-333 and use -8 components for the standard PC100-222 applications.
Decou pling capacito rs are mounted on the PC bo ard. T he PC board design is in accor dance with
INTEL’s PC SDRAM Rev. 1.0 Module Specification. The DIMMs have Serial Presence Detect,
implemented with a serial E 2PROM using the two-pin I2C protocol. The first 128 bytes are util ized by
the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 168-
pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with
1.25“ (31.75 mm) height.
• 168-Pin unbuffered 8-Byte Dual-In-Line
SDRAM Modules for PC main memory
applications
• PC100-222, PC133-333 and PC133-222
versions
• 1 bank 16M ×64, 16M ×72 and 2 bank
32M ×64, 32M ×72 organzation
• Optimized for byte-write non-parity (x64) or
ECC (x72) applications
• JEDEC standard Synchronous DRAMs
(SDRAM)
• Fully PC board layout compatible to INTEL’s
Rev. 1.0 Module Specification
• SDRAM Performance:
• Programmed Latencies:
• Single +3.3 V(±0.3 V) Power Supply
• Programmable CAS Latency, Burst Length,
and Wrap Sequence
(Sequential and Interleave)
• Auto-Refresh (CBR) and Self-Refresh
• Decoupling capacitors mounted on substrate
• All inputs and outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 16M ×8 SDRAMs in TSOPII-54
packages with 4096 re fresh cycles every
64 ms
• 133.35 mm ×31.75 mm ×4,00 mm card size
with gold-contact pads
(JEDEC MO-161-BA)
-7 /-7.5 -8 Unit
PC133 PC100
fCK Max. Clock
Frequency 133 100 MHz
tAC Clock Acce s s
Time 5.4 6 ns
Product Speed CL tRCD tRP
-7 PC133-222 2 2 2
-7.5 PC133-333 3 3 3
-8 PC100-222 2 2 2
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 2 8.00
Note: All part numbers end with a place code, designating the die revision. Consult factory for
current revision. Example: HYS 64V16300GU-8-C2, indicates that Rev.C2 dies are used for
SDRAM components.
Ordering Information
Type Code Package Descriptions Module
Height
128 MByte DIMMs
HYS 64V16300GU-7-C2 PC133-222-520 L-DIM-168-33 133 Mhz 16M ×64
1 bank SDRAM module 1.25“
HYS 64V16300GU-7.5-C2 PC133-333-520 L-DIM-168-33 133 Mhz 16M ×64
1 bank SDRAM module 1.25“
HYS 64V16300GU-8-C2 PC100-222-620 L-DIM-168-33 100 MHz 16M ×64
1 bank SDRAM module 1.25“
HYS 72V16300GU-7-C2 PC133-222-520 L-DIM-168-33 133 Mhz 16M ×72
1 bank SDRAM module 1.25“
HYS 72V16300GU-7.5-C2 PC133-333-520 L-DIM-168-33 133 Mhz 16M ×72
1 bank SDRAM module 1.25“
HYS 72V16300GU-8-C2 PC100-222-620 L-DIM-168-33 100 MHz 16M ×72
1 bank SDRAM module 1.25“
256 MByte DIMMs
HYS 64V32220GU-7-C2 PC133-222-520 L-DIM-168-30 133 MHz 32M ×64
2 bank SDRAM module 1.25“
HYS 64V32220GU-7.5-C2 PC133-333-520 L-DIM-168-30 133 MHz 32M ×64
2 bank SDRAM module 1.25“
HYS 64V32220GU-8-C2 PC100-222-620 L-DIM-168-30 100 MHz 32M ×64
2 bank SDRAM module 1.25“
HYS 72V32220GU-7-C2 PC133-222-520 L-DIM-168-30 133 Mhz 32M ×72
2 bank SDRAM module 1.25“
HYS 72V32220GU-7.5-C2 PC133-333-520 L-DIM-168-30 133 Mhz 32M ×72
2 bank SDRAM module 1.25“
HYS 72V32220GU-8-C2 PC100-222-620 L-DIM-168-30 100 Mhz 32M ×72
2 bank SDRAM module 1.25“
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 3 8.00
Pin Definitions and Functions
A0-A11 Address Inputs WE Read/Write Input VSS Ground
BA0, BA1 Bank Selects CKE0, CKE1 Clock Enabl e SCL Clock for SPD
DQ0 - DQ63 Data Input/Output CLK0 - CLK3 Clock Input SDA Serial Data Out
CB0-CB7 Check Bits
(x72 modules only) DQMB0 - DQMB7 Data Mask N.C. No Connection
RAS Row Address Strobe CS0 - CS3 Chip Select ––
CAS Column Address
Strobe VDD P owe r (+3.3 V) ––
Address Format
Part Number Rows Columns Bank Select Refresh Period Interval
16M ×64 HYS 64V16300GU 12 10 2 4k 64 ms 15,6 µs
16M ×72 HYS 72V16300GU 12 10 2 4k 64 ms 15,6 µs
32M ×64 HYS 64V32220GU 12 10 2 4k 64 ms 15,6 µs
32M ×72 HYS 72V32220GU 12 10 2 4k 64 ms 15,6 µs
Pin Configuration
PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol
1VSS 43 VSS 85 VSS 127 VSS
2 DQ0 44 DU 86 DQ32 128 CKE0
3 DQ1 45 CS2 87 DQ33 129 CS3
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6VDD 48 DU 90 VDD 132 N.C.
7DQ4 49
VDD 91 DQ36 133 VDD
8 DQ5 50 N.C. 92 DQ37 134 N.C.
9 DQ6 51 N.C. 93 DQ38 135 N.C.
10 DQ7 52 N.C. (CB2 ) 94 DQ39 136 CB6
11 DQ8 53 N.C. (CB3 ) 95 DQ40 137 CB7
12 VSS 54 VSS 96 VSS 138 VSS
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 4 8.00
Note: Pin names in parentheses are for the x72 ECC versions; example: Pin 106 = (CB5).
17 DQ13 59 VDD 101 DQ45 143 VDD
18 VDD 60 DQ20 102 VDD 144 DQ52
19 DQ14 61 N.C. 103 DQ46 145 N.C.
20 DQ15 62 DU 104 DQ47 146 DU
21 N.C. (CB0) 63 CKE1 105 N.C. (CB4) 147 N.C.
22 N.C. (CB1) 64 VSS 106 N.C. (CB5) 148 VSS
23 VSS 65 DQ21 107 VSS 149 DQ53
24 N.C. 66 DQ22 108 N.C. 150 DQ54
25 N.C. 67 DQ23 109 N.C. 151 DQ55
26 VDD 68 VSS 110 VDD 152 VSS
27 WE 69 DQ24 111 CAS 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 CS0 72 DQ27 114 CS1 156 DQ59
31 DU 73 VDD 115 RAS 157 VDD
32 VSS 74 DQ28 116 VSS 158 DQ60
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 VSS 120 A7 162 VSS
37 A8 79 CLK2 121 A9 163 CLK3
38 A10 80 N.C. 122 BA0 164 N.C.
39 BA1 81 WP 123 A11 165 SA0
40 VDD 82 SDA 124 VDD 166 SA1
41 VDD 83 SCL 125 CLK1 167 SA2
42 CLK0 84 VDD 126 N.C. 168 VDD
Pin Configuration (cont’d)
PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 5 8.00
Block Diagram for 16M ×64/72 SDRAM DIMM Modules (HYS 64/72V16300GU)
DQ0-DQ7
DQM WE
D0
CS0
WE
DQ(7:0)
DQMB0 DQ0-DQ7
DQ(39:32)
DQMB4 DQM
D4
DQ0-DQ7DQ(15:8)
DQMB1 DQM
D1
CS
DQ0-DQ7DQ(47:40)
DQMB5 DQM
D5
DQ0-DQ7CB(7:0) DQM
CS
D8
DQ0-DQ7
DQ0-DQ7
DQ(31:24)
DQMB3
DQ(23:16)
DQMB2
DQM
DQM
CS2
CS
CS
CS
D3
D2
DQMB7
DQ(63:56)
DQMB6
DQ(55:48)
CS
D7
D6
DQ0-DQ7
DQM
DQ0-DQ7
DQM
A0-A11, BA0, BA1 D0-D7, (D8)
CC
V
SS
VC0-C15, (C16, C17)D0-D7, (D8)
RAS D0-D7, (D8)
D0-D7, (D8)CAS Cl ock Wiring
16 M x 64 16 M x 72
CLK0
4 SD RA M + 3.3 pF 5 SDR AM
TerminationTermination
CLK1
4 SD RA M + 3.3 pF4 S DR AM + 3.3 pF
CLK2
CLK3
47 k
SCLSCL
2
SA0
SA1
SA2
E PROM (25 6 word x 8 B it)
SA1
SA0
SA2 SDA
WP
Ω
CS CS WE
WE
WE
WECS
WE
WE WE
WE
D0-D7, (D8)
CKE0 D0-D7, (D8)
Termination Termination
Note: D8 is only used in the x72 ECC version and
all re sistor values are 10 Ohm except
otherwise not ed.
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 6 8.00
Block Diagram for 32M ×64/72 SDRAM DIMM Modules (HYS 64/72V32220GU)
BL01
DQ0-DQ7
DQM
CS
D0 DQ0-DQ7
DQM
D8
CS
CS0
CS1
DQ(7:0)
DQMB0 DQ0-DQ7DQ(39:32)
DQMB4 DQM CS
D4
CS
DQ0-DQ7
DQM
D12
DQ0-DQ7DQ(15:8)
DQMB1 DQM CS
D1
CS
DQ0-DQ7
DQM
D9 DQ0-DQ7DQ(47:40)
DQMB5 DQM CSCS
D5
DQM
DQ0-DQ7
D13
DQ0-DQ7CB(7:0) DQM CSCS
D16
DQM
DQ0-DQ7
D17
DQ0-DQ7
DQ0-DQ7
DQ(31:24)
DQMB3
DQ(23:16)
DQMB2
DQM
DQM
CS3
CS2
CS CSCS CS
CSCS
D3 DQ0-DQ7
DQM
D2
DQM
DQ0-DQ7
DQMB7
DQ(63:56)
D11
DQMB6
DQ(55:48)
D10
CS
D7
D6
DQ0-DQ7
DQM
DQ0-DQ7
DQM
CS
DQ0-DQ7
DQM
D15
DQM
DQ0-DQ7
D14
A0-A11, BA0, BA1 D 0-D15, (D16, D17)
DD
V
SS
VC0-C31, (C32...C 35)
D0-D15, (D16, D17)
D0-D7, (D8)
RAS, CAS , WE D0-D15, (D16, D17)
D0-D7, (D16)CKE0
D9-D15, (D17)CKE1
DD
V
10 k
Ω
Clock Wiring
32 M x 64 32 M x 72
CLK0 4 SDRAM + 3 .3 pF 5 SDRAM
5 SDRAM4 SDRAM + 3 .3 pFCLK1 4 SDRAM + 3.3 pF4 SDRAM + 3 .3 pFCLK2 4 SDRAM + 3 .3 pFCLK3 4 SDRAM + 3.3 pF
47 k
SCLSCL
2
SA0
SA1
SA2
E PROM (256 Word x 8 Bit)
SA1
SA0
SA2 SDA
WP
Ω
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 except otherwise noted.
Ω
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 7 8.00
DC Characteristics
TA= 0 to 70 °C; VSS =0V; VDD,VDDQ =3.3V±0.3 V
Parameter Symbol Limit Values Unit
min. max.
Input High Voltage VIH2.0 VDD +0.3 V
Input Low Voltage VIL –0.5 0.8 V
Output High Voltage (IOUT =–4.0 mA) VOH 2.4 –V
Output Low Voltage (IOUT =4.0 mA) VOL –0.4 V
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) –40 40 µA
Output Leakage Current
(DQ is disabled, 0 V < VOUT <VDD)IO(L) –40 40 µA
Capacitance
TA = 0 to 70 °C; VDD =3.3V±0.3 V, f=1MHz
Parameter Symbol Limit Values Unit
max.
16M×64 max.
16M×72 max.
32M×64 max.
32M×72
Input Capacitance
(A0 to A11, BA0, BA1, RAS, CAS, WE)CI1 65 72 105 144 pF
Input Capacitance (CS0 - CS3) CCS 32 40 35 43 pF
Input Capacitance (CLK0 - CLK3) CCLK 38 40 42 45 pF
Input Capacitance (CKE0 , CKE1) CCKE 65 72 65 72 pF
Input Capacitance (DQMB0 - DQMB7) CI4 13 13 20 20 pF
Input/Output Capacitance
(DQ 0 - DQ63, CB 0 - CB7) CIO 10 10 17 17 pF
Input Capacitance (SCL, S A0-2) CSC 888 8 pF
Input/Output Capacitance CSD 888 8 pF
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 8 8.00
Operating Currents per SDRAM Component 1)
TA= 0 to 70 oC, VDD = 3.3 V ±0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter Test
Condition Symbol -7 /7.5 -8 Unit Note
max.
Opera ting Current
tRC =tRCMIN., tCK =tCKMIN.
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
–ICC1 160 150 mA 1)
Precharge Standby Current
in Power Down Mode
CS =VIH (min.), CKE ≤VIL(MAX)
tCK =min. ICC2P 1.5 1.5 mA 1)
Precharge S tand-by Current
in Non-Power Down Mode
CS =VIH (MIN.), CKE ≥VIH(MIN)
tCK =min. ICC2N 40 35 mA 1)
No Operating Current
tCK = m in., CS =VIH(MIN),
active state (max. 4 banks)
CKE ≥VIH(MIN.) ICC3N 50 45 mA 1)
CKE ≤VIL(MAX.) ICC3P 10 10 mA 1)
Burst Operating Current
tCK =min.,
Read command cycling
–ICC4 100 90 mA 1), 2)
Auto-Refresh Current
tCK =min.,
Auto-Refresh command cycling
–ICC5 230 210 mA 1)
Self-Refresh Current
Self-Refresh Mode, CKE = 0.2 V –ICC6 1.5 1.5 mA 1)
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 9 8.00
AC Characteristics 3), 4)
TA= 0 to 70 °C; VSS =0V; VDD =3.3V±0.3 V, tT=1ns
Parameter Symbol Limit Values Unit Note
-7
PC133-222 -7.5
PC133-333 -8
PC100-222
min. max. min. max. min. max.
Clock and Access Time
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK 7.5
7.5 –
–7.5
10 –
–10
10 –
–ns
ns
–
System Frequency
CAS Latency = 3
CAS Latency = 2
fCK –
–133
133 –
–133
100 –
–100
100 MHz
MHz
–
Cl o ck Ac c e ss Tim e
CAS Latency = 3
CAS Latency = 2
tAC –
–5.4
5.4 –
–5.4
6–
–6
6ns
ns
4), 5)
Clock High Pulse Width tCH 2.5 –2.5 –3–ns 6)
Clock Low Pulse Width tCL 2.5 –2.5 –3–ns 6)
Setup & Hold P arame ter s
Input Setup Time tIS 1.5 –1.5 –2–ns 7)
Input Hold Time tIH 0.8 –0.8 –1–ns 7)
Power Down Mode Entry
Time tSB –1–1–1CLK
8)
Power Down Mode Exit
Setup Time tPDE 1–1–1–CLK 9)
Mode Register Setup Time tRSC 2–2–2–CLK
Transition Time (rise and fall) tT1–1–1–ns –
Common Parameters
RAS to CAS Delay tRCD 15 –20 –20 –ns –
Precharge Time tRP 15 –20 –20 –ns –
Active Command Period tRAS 42 100k 45 100k 50 100k ns –
Cycle Time tRC 60 –67.5 –70 –ns –
Bank-to-Bank Delay Time tRRD 15 –15 –16 –ns –
CAS to CAS Delay T ime
(same bank) tCCD 1–1–1–CLK –
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 10 8.00
Refresh Cycle
Refres h Period (4096 cycles) tREF –64 –64 –64 ms
Se lf-Refresh Exit Time tSREX 1–1–1–CLK 10)
Re ad Cycle
Da ta Out Hold Time tOH 3–3–3–ns 4)
Data Out to Low Impedance tLZ 0–0–0–ns –
Data Out to High Impedanc e tHZ 373738ns
11
DQM Data Out Disable
Latency tDQZ –3–2–2CLK–
Write Cycle
Data Input to Precharge
(write recovery) tWR 2–2–2–CLK –
DQM Write Mask Latency tDQW 0–0–0–CLK –
AC Characteristics (cont’d) 3), 4)
TA= 0 to 70 °C; VSS =0V; VDD =3.3V±0.3 V, tT=1ns
Parameter Symbol Limit Values Unit Note
-7
PC133-222 -7.5
PC133-333 -8
PC100-222
min. max. min. max. min. max.
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SDRAM-Modules
INFINEON Tec hnologies 11 8.00
Notes
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 and
7.5 modules and at 100 Mhz for -8 modules. Input signals are changed once during tCK, except
for ICC6 and for standby currents when tCK = infinity. All values are shown per memory
component.
2. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 assumed and the VDDQ current is excluded.
3. All AC characteristics are shown on SDRAM component level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT= 1 ns with the AC output load circuit show. Specifi ed tAC and tOH pa rameter s ar e measured
with a 50 pF only, without any res is tive termination and w ith a in put signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
5. If clock rising time is longer than 1 ns, a time (tT/2 –0.5) ns must be added to this parameter.
6. Rated at 1.4 V
7. If tT is longer than 1 ns, a time (tT–1) ns has to be added to this parameter.
8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)
commands must be given to “wake-up” the device.
9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied
after the Self Refresh Exit command is registered.
11.This is referenced to the time at which the output achieves the open circuit condition, not to
output voltage levels.
A Serial Presence Detect storage device—E2PROM—is assembled onto the module. Information about the
module configuratio n, speed, etc. is w ritten into the E2PROM device during module production using a Serial
Presence Detect protocol (I2C synchronous 2-wire bus).
SPT03404
CLOCK 2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT 1.4 V
t
LZ
AC
t t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
50 pF
I/O
Measurement conditions for
tAC and tOH
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 12 8.00
SPD-Tab le for PC133-222 Modules:
Byte# Description SPD Entry
Value Hex
16Mx64
-7 16Mx72
-7 32Mx64
-7 32Mx72
-7
0 Num ber of SPD bytes 128 80
1 Total bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Num ber of Row Addresses
(without BS bits ) 12 0C
4 Num ber of Column Addres-
ses 10 0A
5 Number of DIMM Banks 1 / 2 01 02
6 Module Data Width 64 / 72 40 48 40 48
7 Module Data Width (cont’d) 0 00
8 Module Interf ace Level s LVTTL 01
9 SDRAM Cycle Time at CL=3 7.5 ns 75
10 SDRAM Access time from
Clock at CL=3 5.4 ns 54
11 Dimm Config none / ECC 00 0 2 00 0 2
12 Refresh Rate/Type Self-Refresh,
15.6ms 80
13 S D R A M w i d t h , P r im a r y x 8 0 8
14 Error Checking SDRAM data
width n/a / x8 00 08 00 0 8
15 Minimum clock delay for
back-t o-back r andom column
address
tccd = 1 CLK 01
16 Burst Length support ed 1, 2, 4 & 8 0F
17 Number of SDRAM banks 4 04
18 Supported CAS Latencies CAS latency = 2
& 3 06
19 CS Latencies CS latency = 0 01
20 WE Latencies Write latency = 0 01
21 SDRAM DIMM modul e
attributes non buff ered/non
reg. 00
22 SDRAM Device Attributes
:General Vcc tol +/- 10% 0E
23 Min. Clock Cycle Time at
CAS Latency = 2 7.5 ns 75
24 Max. data access time from
Clock for CL=2 5.4 ns 54
25 Mi nimum Clock Cycle Time
at CL = 1 not supported FF
26 Maxi mu m Dat a Acc ess Tim e
from Clock at CL=1 not supported FF
27 Minimum Row Precharge
Time 15 ns 0F
28 Minimum Ro w Active to Row
Active delay tRRD 14 ns 0E
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Byte# Description SPD Entry
Value Hex
16Mx64
-7 16Mx72
-7 32Mx64
-7 32Mx72
-7
29 Minimum RAS to CAS delay
tRCD 15 ns 0F
30 Minimum RAS pulse width
tRAS 42 ns 2A
31 Module Bank Density (per
bank) 128 MByte 20
32 SDRAM input setup time 1.5 ns 15
33 SDRAM input hold ti me 0. 8 ns 08
34 SDRAM data input hold time 1.5 ns 15
35 SDRAM data input setup
time 0.8 ns 08
62-61 Superset information (may be
used in future) FF
62 SPD Revision Re visi on 1.2 12
63 Checksum for bytes 0 - 62 CE E0 tbd tbd
64-
125 Manufacturers infor m ation XX XX XX X X
126 F requency Specificati on 64
127 Support Details AF FF
128+ Unused storage locations FF
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SPD-Tab le for PC133-333 Modules:
Byte# Description SPD Entry
Value Hex
16Mx64
-7.5 16Mx72
-7.5 32Mx64
-7.5 32Mx72
-7.5
0 Num ber of SPD bytes 128 80
1 Total bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Num ber of Row Addresses
(without BS bits ) 12 0C
4 Num ber of Column Addres-
ses 10 0A
5 Number of DIMM Banks 1 / 2 01 02
6 Module Data Width 64 / 72 40 48 40 48
7 Module Data Width (cont’d) 0 00
8 Module Interf ace Level s LVTTL 01
9 SDRAM Cycle Time at CL=3 7.5 ns 75
10 SDRAM Access time from
Clock at CL=3 5.4 ns 54
11 Dimm Config none / ECC 00 0 2 00 0 2
12 Refresh Rate/Type Self-Refresh,
15.6ms 80
13 S D R A M w i d t h , P r im a r y x 8 0 8
14 Error Checking SDRAM data
width n/a / x8 00 08 00 0 8
15 Minimum clock delay for
back-t o-back r andom column
address
tccd = 1 CLK 01
16 Burst Length support ed 1, 2, 4 & 8 0F
17 Number of SDRAM banks 4 04
18 Supported CAS Latencies CAS latency = 2
& 3 06
19 CS Latencies CS latency = 0 01
20 WE Latencies Write latency = 0 01
21 SDRAM DIMM modul e
attributes non buff ered/non
reg. 00
22 SDRAM Device Attributes
:General Vcc tol +/- 10% 0E
23 Min. Clock Cycle Time at
CAS Latency = 2 10.0 ns A0
24 Max. data access time from
Clock for CL=2 6.0 n s 60
25 Mi nimum Clock Cycle Time
at CL = 1 not supported FF
26 Maxi mu m Dat a Acc ess Tim e
from Clock at CL=1 not supported FF
27 Minimum Row Precharge
Time 20 ns 14
28 Minimum Ro w Active to Row
Active delay tRRD 15 ns 0F
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 15 8.00
Byte# Description SPD Entry
Value Hex
16Mx64
-7.5 16Mx72
-7.5 32Mx64
-7.5 32Mx72
-7.5
29 Minimum RAS to CAS delay
tRCD 20 ns 14
30 Minimum RAS pulse width
tRAS 45 ns 2D
31 Module Bank Density (per
bank) 128 MByte 20
32 SDRAM input setup time 1.5 ns 15
33 SDRAM input hold ti me 0. 8 ns 08
34 SDRAM data input hold time 1.5 ns 15
35 SDRAM data input setup
time 0.8 ns 08
62-61 Superset information (may be
used in future) FF
62 SPD Revision Re visi on 1.2 12
63 Checksum for bytes 0 - 62 13 25 14 26
64-
125 Manufacturers infor m ation XX XX XX X X
126 F requency Specificati on 64
127 Support Details AF FF
128+ Unused storage locations FF
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 16 8.00
SPD-Table for PC100 Modules:
Byte# Description SPD Entry
Value Hex
16Mx64
-8 16Mx72
-8 32Mx64
-8 32Mx72
-8
0 Num ber of SPD bytes 128 80
1 Total bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Num ber of Row Addresses
(without BS bits ) 12 0C
4 Num ber of Column Addres-
ses 10 0A
5 Number of DIMM Banks 1 / 2 01 02
6 Module Data Width 64 / 72 40 48 40 48
7 Module Data Width (cont’d) 0 00
8 Module Interf ace Level s LVTTL 01
9 SDRAM Cycle Time at CL=3 10.0 ns A0
10 SDRAM Access time from
Clock at CL=3 6.0 ns 60
11 Dimm Config none / ECC 00 0 2 00 0 2
12 Refresh Rate/Type Self-Refresh,
15.6ms 80
13 S D R A M w i d t h , P r im a r y x 8 0 8
14 Error Checking SDRAM data
width n/a / x8 00 08 00 0 8
15 Minimum clock delay for
back-t o-back r andom column
address
tccd = 1 CLK 01
16 Burst Length support ed 1, 2, 4 & 8 0F
17 Number of SDRAM banks 4 04
18 Supported CAS Latencies CAS latency = 2
& 3 06
19 CS Latencies CS latency = 0 01
20 WE Latencies Write latency = 0 01
21 SDRAM DIMM modul e
attributes non buff ered/non
reg. 00
22 SDRAM Device Attributes
:General Vcc tol +/- 10% 0E
23 Min. Clock Cycle Time at
CAS Latency = 2 10.0 ns A0
24 Max. data access time from
Clock for CL=2 6.0 n s 60
25 Mi nimum Clock Cycle Time
at CL = 1 not supported FF
26 Maxi mu m Dat a Acc ess Tim e
from Clock at CL=1 not supported FF
27 Minimum Row Precharge
Time 20 ns 14
28 Minimum Ro w Active to Row
Active delay tRRD 16 ns 10
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 17 8.00
Byte# Description SPD Entry
Value Hex
16Mx64
-8 16Mx72
-8 32Mx64
-8 32Mx72
-8
29 Minimum RAS to CAS delay
tRCD 20 ns 14
30 Minimum RAS pulse width
tRAS 45 ns 2D
31 Module Bank Density (per
bank) 128 MByte 20
32 SDRAM input setup time 2 ns 20
33 SDRAM input hold ti me 1 ns 10
34 SDRAM data input hold time 2 ns 20
35 SDRAM data input setup
time 1 ns 10
62-61 Superset information (may be
used in future) FF
62 SPD Revision Re visi on 1.2 12
63 Checksum for bytes 0 - 62 71 83 72 84
64-
125 Manufacturers infor m ation XX XX XX X X
126 F requency Specificati on 100 MHz 64
127 Support Details AF FF
128+ Unused storage locations FF
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 18 8.00
Package Outlines
L-DIM-168-30 (JEDEC MO-161-BA)
SDRAM DIMM Module Package
HYS 64/72V32220GU
Note: All tolerances according to JEDEC s tandard
L-DIM-168-30
133.35
10 11
36.35 6.35
4140
42.18
84
127.35
3
1.27
85 94 95 124 125 168
2
17.78 4
3min.
4 max .
31.75
D e ta i l of Cont ac ts
min.2.54
1
1.27
1
1.27 91 x 1.27 = 115.57
3.125
0.2
3
*) on ECC modules only
*)
*)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Informatio n”.Dimensions in mm
HYS 64/72V16300/32220GU
SDRAM-Modules
INFINEON Tec hnologies 19 8.00
L-DIM-168-33 (JEDEC MO-161-BA)
SDRAM DIMM Module Package
HYS 64/72V16300GU
Note: All tol erances according to JEDEC standard
L-DIM-168-33
133.35
10 11
36.35 6.35
4140
42.18
84
127.35
3
1.27
85 94 95 124 125 168
2
17.78 4
3min.
3 max.
31.75
Detail of Cont acts
min.2.54
1
1.27
1
1.27 91 x 1. 27 = 115.57
3.125
0.2
3
*) on ECC modules only
*)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Informatio n”.Dimensions in mm
