PIC18LF44J10-I/PT - MICROCHIP TECHNOLOGY

PIC18F45J10 Family

Data Sheet

28/40/44-Pin High-Performance,

RISC Microcontrollers

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Note the following details of the code protection feature on Microch ip devices:

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intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

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PIC18F45J10 FAMILY

S pecial Microcontroller Features:

• Operating Voltage Range: 2.0V to 3.6V

• 5.5V Tolerant Input (digital pins only)

• On-Chip 2.5V Regulator

• 4x Phase Lock Loop (PLL) available for Crystal

and Internal Oscillators

• Self-Programmable under Software Control

• Low-Power, High-Speed CMOS Flash Technology

• C Compiler Optimized Architecture:

- Optional extended instruction set designed to

optimize re-entrant code

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Single-Supply In-Circuit Serial Programming™

(ICSP™) via Two Pins

• In-Circuit Debug (ICD) with Three Breakpoints via

Two Pins

• Power-Managed modes with Clock Switching:

- Run: CPU on, peripherals on

- Idle: CPU off, peripherals on

- Sleep: CPU off, peripherals off

Flexible Oscil lator Struc ture:

• Two Crystal modes, up to 40 MHz

• Two External Clock modes, up to 40 MHz

• Internal 31 kHz Oscillator

• Secondary Oscillator using Timer1 @ 32 kHz

• Two-Speed Oscillator Start-up

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock

stops

Peripheral Highl ight s:

• High-Current Sink/Source 25 mA/25 mA

(PORTB and PORTC)

• Three Programmable External Interrupts

• Four Input Change Interrupts

• One Capture/Compare/PWM (CCP) module

• One Enhanced Capture/Compare/PWM (ECCP)

module:

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-shutdown and auto-restart

• Two Master Synchronous Serial Port (MSSP)

modules supporting 3-Wire SPI (all 4 modes) and

I2C™ Master and Slave modes

• One Enhanced Addressable USART module:

- Supports RS-485, RS-232 and LIN/J2602

- Auto-wake-up on Start bit

- Auto-Baud Detect (ABD)

• 10-Bit, up to 13-Channel Analog-to-Digital

Converter module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep

- Self-calibration feature

• Dual Analog Comparators with Input Multiplexing

Device

Program Memory SRAM Data

Memory

(bytes) I/O 10-Bit

A/D (ch)

CCP/

ECCP

(PWM)

MSSP

EUSART

Comparators

Timers

8/16-Bit

Flash

(bytes) # Single-Word

Instructions SPI Master

I2C™

PIC18F24J10 16K 8192 1024 21 10 2/0 1 Y Y 1 2 1/2

PIC18F25J10 32K 16384 1024 21 10 2/0 1 Y Y 1 2 1/2

PIC18F44J10 16K 8192 1024 32 13 1/1 2 Y Y 1 2 1/2

PIC18F45J10 32K 16384 1024 32 13 1/1 2 Y Y 1 2 1/2

28/40/44-Pin High-Per forman ce, RISC Microcontroll ers

PIC18F45J10 FAMILY

Pin Diagrams

PIC18F24J10

14 15

MCLR

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

VDDCORE/VCAP

RA5/AN4/SS1/C2OUT

VSS

OSC1/CLKI

OSC2/CLKO

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2*

RC2/CCP1

RC3/SCK1/SCL1

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/T0CKI/C1OUT

RB4/KBI0/AN11

RB3/AN9/CCP2*

RB2/INT2/AN8

RB1/INT1/AN10

RB0/INT0/FLT0/AN12

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO1

RC4/SDI1/SDA1

28-Pin SPDIP, SOIC, SSOP (300 MIL)

PIC18F25J10

* Pin feature is dependent on device configuration.

28-Pin QFN

PIC18F24J10

RC0/T1OSO/T1CKI

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/T0CKI/C1OUT

RB4/KBI0/AN11

RB3/AN9/CCP2*

RB2/INT2/AN8

RB1/INT1/AN10

RB0/INT0/FLT0/AN12

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO1

RC4/SDI1/SDA1

MCLR

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

VDDCORE/VCAP

RA5/AN4/SS1/C2OUT

VSS

OSC1/CLKI

OSC2/CLKO

RC1/T1OSI/CCP2*

RC2/CCP1

RC3/SCK1/SCL1

PIC18F25J10

* Pin feature is dependent on device configuration.

10 11

12 13 14

232425262728

= Pins are up to 5.5V tolerant

PIC18F45J10 FAMILY

Pin Diagrams (Continued)

44-Pin QFN(1)

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/T0CKI/C1OUT

RB4/KBI0/AN11

RB3/AN9/CCP2*

RB2/INT2/AN8

RB1/INT1/AN10

RB0/INT0/FLT0/AN12

VDD

VSS

RD7/PSP7/P1D

RD6/PSP6/P1C

RD5/PSP5/P1B

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5/SDO1

RC4/SDI1/SDA1

RD3/PSP3/SS2

RD2/PSP2/SDO2

MCLR

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

VDDCORE/VCAP

RA5/AN4/SS1/C2OUT

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

VDD

VSS

OSC1/CLKI

OSC2/CLKO

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2*

RC2/CCP1/P1A

RC3/SCK1/SCL1

RD0/PSP0/SCK2/SCL2

RD1/PSP1/SDI2/SDA2

PIC18F44J10

40-Pin PDIP (600 MIL)

PIC18F45J10

* Pin feature is dependent on device configuration.

Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.

PIC18F44J10

MCLR

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/T0CKI/C1OUT

RB4/KBI0/AN11

RC6/TX/CK

RC5/SDO1

RC4/SDI1/SDA1

RD3/PSP3/SS2

RD2/PSP2/SDO2

RD1/PSP1/SDI2/SDA2

RD0/PSP0/SCK2/SCL2

RC3/SCK1/SCL1

RC2/CCP1/P1A

RC1/T1OSI/CCP2*

RC0/T1OSO/T1CKI

OSC2/CLKO

OSC1/CLKI

VSS

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4/SS1/C2OUT

VDDCORE/VCAP

RC7/RX/DT

RD4/PSP4

RD5/PSP5/P1B

RD6/PSP6/P1C

VSS

VDD

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

RB3/AN9/CCP2*

RD7/PSP7/P1D 5

4VSS

VDD

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF-

RA1/AN1

RA0/AN0

PIC18F45J10

= Pins are up to 5.5V tolerant

PIC18F45J10 FAMILY

Pin Diagrams (Continued)

PIC18F44J10

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF-

RA1/AN1

RA0/AN0

MCLR

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/T0CKI/C1OUT

RB4/KBI0/AN11

RC6/TX/CK

RC5/SDO1

RC4/SDI1/SDA1

RD3/PSP3/SS2

RD2/PSP2/SDO2

RD1/PSP1/SDI2/SDA2

RD0/PSP0/SCK2/SCL2

RC3/SCK1/SCL1

RC2/CCP1/P1A

RC1/T1OSI/CCP2*

RC0/T1OSO/T1CKI

OSC2/CLKO

OSC1/CLKI

VSS

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4/SS1/C2OUT

VDDCORE/VCAP

RC7/RX/DT

RD4/PSP4

RD5/PSP5/P1B

RD6/PSP6/P1C

VSS

VDD

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

RB3/AN9/CCP2*

44-Pin TQFP

RD7/PSP7/P1D 5

PIC18F45J10

* Pin feature is dependent on device configuration.

= Pins are up to 5.5V tolerant

PIC18F45J10 FAMILY

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 23

3.0 Oscillator Configurations ............................................................................................................................................................ 27

4.0 Power-Managed Modes ............................................................................................................................................................. 35

5.0 Reset .......................................................................................................................................................................................... 41

6.0 Memory Organization ................................................................................................................................................................. 51

7.0 Flash Program Memory.............................................................................................................................................................. 71

8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 81

9.0 Interrupts .................................................................................................................................................................................... 83

10.0 I/O Ports ..................................................................................................................................................................................... 97

11.0 Timer0 Module ......................................................................................................................................................................... 115

12.0 Timer1 Module ......................................................................................................................................................................... 119

13.0 Timer2 Module ......................................................................................................................................................................... 125

14.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 127

15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 135

16.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 149

17.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 193

18.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 215

19.0 Comparator Module.................................................................................................................................................................. 225

20.0 Comparator Voltage Reference Module................................................................................................................................... 231

21.0 Special Features of the CPU.................................................................................................................................................... 235

22.0 Instruction Set Summary.......................................................................................................................................................... 249

23.0 Development Support............................................................................................................................................................... 299

24.0 Electrical Characteristics.......................................................................................................................................................... 303

25.0 Packaging Information.............................................................................................................................................................. 337

Appendix A: Revision History............................................................................................................................................................. 349

Appendix B: Migration Between High-End Device Families............................................................................................................... 350

Index .................................................................................................................................................................................................. 353

The Microchip Web Site..................................................................................................................................................................... 363

Customer Change Notification Service .............................................................................................................................................. 363

Customer Support .............................................................................................................................................................................. 363

Reader Response .............................................................................................................................................................................. 364

PIC18F45J10 family Product Identification System ........................................................................................................................... 365

PIC18F45J10 FAMILY

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PIC18F45J10 FAMILY

1.0 DEVICE OVERVIEW

This document contains device specific information for

the following devices:

This family offers the advantages of all PIC18

microcontrollers – namely, high computational perfor-

mance at an economical price. The PIC18F45J10 family

introduces design enhancements that make these micro-

controllers a logical choice for many high-performance,

power sensitive applications.

1.1 Core Features

1.1.1 LOW POWER

All of the devices in the PIC18F45J10 family

incorporate a range of features that can significantly

reduce power consumption during operation. Key

items include:

•Alternate Run Modes: By clocking the controller

from the Timer1 source or the internal oscillator

block, power consumption during code execution

can be reduced by as much as 90%.

•Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still

active. In these states, power consumption can be

reduced even further, to as little as 4% of normal

operation requirements.

•On-the-Fly Mode Switching: The power-

managed modes are invoked by user code during

operation, allowing the user to incorporate

power-saving ideas into their application’s software

design.

•Low Consumption in Key Modules: The

power requirements for both Timer1 and the

Watchdog Timer are minimized. See

Section 24.0 “Electrical Characteristics”

for values.

1.1.2 MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

All of the devices in the PIC18F45J10 family offer three

different oscillator options. These include:

• Two Crystal modes, using crystals or ceramic

resonators

• Two External Clock modes

• INTRC source (approximately 31 kHz)

Besides its availability as a clock source, the internal

oscillator block provides a stable reference source that

gives the family additional features for robust

operation:

•Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a refer-

ence signal provided by the internal oscillator. If a

clock failure occurs, the controller is switched to

the internal oscillator block, allowing for continued

low-speed operation or a safe application

shutdown.

•Two-Speed S tart-up: This option allows the

internal oscillator to serve as the clock source

from Power-on Reset, or wake-up from Sleep

mode, until the primary clock source is available.

• PIC18F24J10 • PIC18LF24J10

• PIC18F25J10 • PIC18LF25J10

• PIC18F44J10 • PIC18LF44J10

• PIC18F45J10 • PIC18LF45J10

PIC18F45J10 FAMILY

1.2 Other Special Features

• Communications: The PIC18F45J10 family

incorporates a range of serial communication

peripherals, including 1 independent Enhanced

USART and 2 Master SSP modules capable of

both SPI and I2C (Master and Slave) modes of

operation. Also, one of the general purpose I/O

ports can be reconfigured as an 8-bit Parallel

Slave Port for direct processor-to-processor

communications.

•Self-Programmability: These devices can write

to their own program memory spaces under

internal software control. By using a bootloader

routine, it becomes possible to create an

application that can update itself in the field.

•Extended Instruction Set: The PIC18F45J10

family introduces an optional extension to the

PIC18 instruction set, which adds 8 new instruc-

tions and an Indexed Addressing mode. This

extension, enabled as a device configuration

option, has been specifically designed to optimize

re-entrant application code originally developed in

high-level languages, such as C.

•Enhanced CCP module: In PWM mode, this

module provides 1, 2 or 4 modulated outputs for

controlling half-bridge and full-bridge drivers.

Other features include Auto-Shutdown, for

disabling PWM outputs on interrupt or other select

conditions and Auto-Restart, to reactivate outputs

once the condition has cleared.

•Enhanced Addressable USART: This serial

communication module is capable of standard

RS-232 operation and provides support for the

LIN/J2602 protocol. Other enhancements include

automatic baud rate detection and a 16-bit Baud

Rate Generator for improved resolution.

•10-bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without waiting for a sampling period and

thus, reduce code overhead.

•Extended Watchdog Timer (WDT): This

enhanced version incorporates a 16-bit prescaler,

allowing an extended time-out range that is stable

across operating voltage and temperature. See

Section 24.0 “Electrical Characteristics” for

time-out periods.

1.3 Details on Indi vidual Family

Members

Devices in the PIC18F45J10 family are available in

28-pin and 40/44-pin packages. Block diagrams for the

two groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in five

ways:

1. Flash program memory (16 Kbytes for

PIC18F24J10/44J10 devices and 32 Kbytes for

PIC18F25J10/45J10).

2. A/D channels (10 for 28-pin devices, 13 for

40/44-pin devices).

3. I/O ports (3 bidirectional ports on 28-pin devices,

5 bidirectional ports on 40/44-pin devices).

4. CCP and Enhanced CCP implementation

(28-pin devices have 2 standard CCP mod-

ules, 40/44-pin devices have one standard CCP

module and one ECCP module).

5. Parallel Slave Port (present only on 40/44-pin

devices).

6. One MSSP module for PIC18F24J10/25J10

devices and 2 MSSP modules for

PIC18F44J10/45J10 devices

7. Parts designated with an “F” part number (i.e.,

PIC18F25J10) have a minimum VDD of 2.7 volts,

whereas parts designated with an “LF” part

number (i.e., PIC18LF25J10) can operate

between 2.0-3.6 volts on VDD; however,

VDDCORE should never exceed VDD.

All of the other features for devices in this family are

identical. These are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2 and

Table 1-3.

The PIC18F45J10 family of devices provides an on-chip

voltage regulator to supply the correct voltage levels to

the core. Parts designated with an “F” part number (such

as PIC18F25J10) have the voltage regulator enabled.

These parts can run from 2.7-3.6 volts on VDD but should

have the VDDCORE pin connected to VSS through a low-

ESR capacitor. Parts designated with an “LF” part

number (such as PIC18LF24J10) do not enable the

voltage regulator. An external supply of 2.0-2.7 Volts has

to be supplied to the VDDCORE pin while 2.0-3.6 Volts

can be supplied to VDD (VDDCORE should never exceed

VDD). See Section 21.3 “On-Chip Voltage Regulator”

for more details about the internal voltage regulator.

PIC18F45J10 FAMILY

TABLE 1-1: DEVICE FEATURES

Features PIC18F24J10 PIC18F25J10 PIC18F44J10 PIC18F45J10

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz

Program Memory (Bytes) 16384 32768 16384 32768

Program Memory

(Instructions)

8192 16384 8192 16384

Data Memory (Bytes) 1024 1024 1024 1024

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E

Timers 3 3 3 3

Capture/Compare/PWM Modules 2 2 1 1

Enhanced

Capture/Compare/PWM Modules

0011

Serial Communications MSSP,

Enhanced USART

MSSP,

Enhanced USART

MSSP,

Enhanced USART

MSSP,

Enhanced USART

Parallel Communications (PSP) No No Yes Yes

10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels

Resets (and Delays) POR, BOR(1),

RESET Instruction,

Stack Full, Stack

Underflow (PWRT,

OST),

MCLR, WDT

POR, BOR(1),

RESET Instruction,

Stack Full, Stack

Underflow (PWRT,

OST),

MCLR, WDT

POR, BOR(1),

RESET Instruction,

Stack Full, Stack

Underflow (PWRT,

OST),

MCLR, WDT

POR, BOR(1),

RESET Instruction,

Stack Full, Stack

Underflow (PWRT,

OST),

MCLR, WDT

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions;

83 with Extended

Instruction Set enabled

75 Instructions;

83 with Extended

Instruction Set enabled

75 Instructions;

83 with Extended

Instruction Set enabled

75 Instructions;

83 with Extended

Instruction Set enabled

Packages 28-pin SPDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

28-pin SPDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

40-pin PDIP

44-pin QFN

44-pin TQFP

40-pin PDIP

44-pin QFN

44-pin TQFP

Note 1: BOR is not available in PIC18LF2XJ10/4XJ10 devices.

PIC18F45J10 FAMILY

FIGURE 1-1: PIC18F 24 J10 /25 J1 0 (2 8- PI N) BL OCK DIA GRA M

Instruction

Decode and

Control

PORTA

PORTB

PORTC

RA5/AN4/SS1/C2OUT

RB0/INT0/FLT0/AN12

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2(1)

RC2/CCP1

RC3/SCK1/SCL1

RC4/SDI1/SDA1

RC5/SDO1

RC6/TX/CK

RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/INT1/AN10

Data Latch

Data Memory

(1 Kbyte)

Address Latch

Data Address<12>

Access

BSR FSR0

FSR1

FSR2

inc/dec

logic

Address

412 4

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

BITOP

ALU<8>

Address Latch

Program Memory

(16/32 Kbytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

RB2/INT2/AN8

RB3/AN9/CCP2(1)

PCLATU

PCU

Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.

2: Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.

RB4/KBI0/AN11

RB5/KBI1/T0CKI/C1OUT

RB6/KBI2/PGC

RB7/KBI3/PGD

EUSARTComparator MSSP

10-Bit

ADC

Timer2Timer1Timer0

CCP2CCP1

Instruct ion Bus <16>

STKPTR Bank

State Machine

Control Signals

Decode

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out(2)

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

Block

INTRC

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

BOR(2)

OSC1

OSC2

VDD,VSS

MCLR

T1OSI

T1OSO

VDDCORE

PIC18F45J10 FAMILY

FIGURE 1-2: PIC18F44J10/45J10 (40/44-PIN) BLOCK DIAGRAM

Instruction

Decode and

Control

Data Latch

Data Memory

(3.9 Kbytes)

Address Latch

Data Address<12>

Access

BSR FSR0

FSR1

FSR2

inc/dec

logic

Address

412 4

PCH PCL

PCLATH

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

BITOP

ALU<8>

Address Latch

Program Memory

(16/32 Kbytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

ROM Latch

PCLATU

PCU

PORTE

RE2/CS/AN7

RE0/RD/AN5

RE1/WR/AN6

Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.

2: Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.

Instruction Bus <16>

STKPTR Bank

State Machine

Control Signals

Decode

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

OSC1

OSC2

VDD,

Brown-out(2)

Reset

Internal

Oscillator

Fail-Safe

Clock Monitor

Precision

Reference

Band Gap

VSS

MCLR

Block

INTRC

Oscillator

Single-Supply

Programming

In-Circuit

Debugger

T1OSI

T1OSO

PORTA

PORTB

PORTC

RA5/AN4/SS1/C2OUT

RB0/INT0/FLT0/AN12

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2(1)

RC2/CCP1/P1A

RC3/SCK1/SCL1

RC4/SDI1/SDA1

RC5/SDO1

RC6/TX/CK

RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-/CVREF

RA1/AN1

RA0/AN0

RB1/INT1/AN10

RB2/INT2/AN8

RB3/AN9/CCP2(1)

RB4/KBI0/AN11

RB5/KBI1/T0CKI/C1OUT

RB6/KBI2/PGC

RB7/KBI3/PGD

EUSARTComparator MSSP

10-Bit

ADC

Timer2Timer1Timer0

CCP2ECCP1

BOR(2)

PORTD

RD0/PSP0/SCK2/SCL2

RD1/PSP1/SDI2/SDA2

RD2/PSP2/SDO2

RD3/PSP3/SS2

RD4/PSP4

RD5/PSP5/P1B

RD6/PSP6/P1C

RD7/PSP7/P1D

VDDCORE

PIC18F45J10 FAMILY

TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS

Pin Name

Pin N um b e r Pin

Type Buffer

Type Description

SPDIP,

SOIC,

SSOP QFN

MCLR

126

IST

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low

Reset to the device.

OSC1/CLKI

OSC1

CLKI

—

CMOS

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

External clock source input. Always associated with pin

function OSC1. See related OSC2/CLKO pins.

OSC2/CLKO

OSC2

CLKO

10 7

—

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

In EC mode, OSC2 pin outputs CLKO which has 1/4 the

frequency of OSC1 and denotes the instruction cycle rate.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F45J10 FAMILY

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

227

I/O

TTL

Analog

Digital I/O.

Analog Input 0.

RA1/AN1

RA1

AN1

328

I/O

TTL

Analog

Digital I/O.

Analog Input 1.

RA2/AN2/VREF-/CVREF

RA2

AN2

VREF-

CVREF

I/O

TTL

Analog

Digital I/O.

Analog Input 2.

A/D reference voltage (low) input.

Comparator reference voltage output.

RA3/AN3/VREF+

RA3

AN3

VREF+

I/O

TTL

Analog

Digital I/O.

Analog Input 3.

A/D reference voltage (high) input.

RA5/AN4/SS1/C2OUT

RA5

AN4

SS1

C2OUT

I/O

TTL

Analog

TTL

—

Digital I/O.

Analog Input 4.

SPI slave select input.

Comparator 2 output.

TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin N um b e r Pin

Type Buffer

Type Description

SPDIP,

SOIC,

SSOP QFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F45J10 FAMILY

PORTB is a bidirectional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.

RB0/INT0/FLT0/AN12

RB0

INT0

FLT0

AN12

21 18

I/O

TTL

Analog

Digital I/O.

External Interrupt 0.

PWM Fault input for CCP1.

Analog input 12.

RB1/INT1/AN10

RB1

INT1

AN10

22 19

I/O

TTL

Analog

Digital I/O.

External Interrupt 1.

Analog input 10.

RB2/INT2/AN8

RB2

INT2

AN8

23 20

I/O

TTL

Analog

Digital I/O.

External Interrupt 2.

Analog input 8.

RB3/AN9/CCP2

RB3

AN9

CCP2(1)

24 21

I/O

TTL

Analog

Digital I/O.

Analog Input 9.

Capture 2 input/Compare 2 output/PWM2 output.

RB4/KBI0/AN11

RB4

KBI0

AN11

25 22

I/O

TTL

Analog

Digital I/O.

Interrupt-on-change pin.

Analog Input 11.

RB5/KBI1/T0CKI/

C1OUT

RB5

KBI1

T0CKI

C1OUT

26 23

I/O

TTL

—

Digital I/O.

Interrupt-on-change pin.

Timer0 external clock input.

Comparator 1 output.

RB6/KBI2/PGC

RB6

KBI2

PGC

27 24

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP™ programming clock pin.

RB7/KBI3/PGD

RB7

KBI3

PGD

28 25

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming data pin.

TABLE 1-2 : PI C18F24 J10 /25J 10 PINO UT I/O DES CRIPT IONS (CO NTINUED)

Pin Name

Pin N um b e r Pin

Type Buffer

Type Description

SPDIP,

SOIC,

SSOP QFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F45J10 FAMILY

PORTC is a bidirectional I/O port.

RC0/T1OSO/T1CKI

RC0

T1OSO

T1CKI

11 8

I/O

—

Digital I/O.

Timer1 oscillator output.

Timer1 external clock input.

RC1/T1OSI/CCP2

RC1

T1OSI

CCP2(2)

12 9

I/O

Analog

Digital I/O.

Timer1 oscillator input.

Capture 2 input/Compare 2 output/PWM2 output.

RC2/CCP1

RC2

CCP1

13 10

I/O

Digital I/O.

Capture 1 input/Compare 1 output/PWM1 output.

RC3/SCK1/SCL1

RC3

SCK1

SCL1

14 11

I/O

Digital I/O.

Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I2C™ mode.

RC4/SDI1/SDA1

RC4

SDI1

SDA1

15 12

I/O

Digital I/O.

SPI data in.

I2C data I/O.

RC5/SDO1

RC5

SDO1

16 13

I/O

—

Digital I/O.

SPI data out.

RC6/TX/CK

RC6

17 14

I/O

—

Digital I/O.

EUSART asynchronous transmit.

EUSART synchronous clock (see related RX/DT).

RC7/RX/DT

RC7

18 15

I/O

Digital I/O.

EUSART asynchronous receive.

EUSART synchronous data (see related TX/CK).

VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.

VDD 20 17 P — Positive supply for logic and I/O pins.

VDDCORE/VCAP

VDDCORE

VCAP

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin N um b e r Pin

Type Buffer

Type Description

SPDIP,

SOIC,

SSOP QFN

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F45J10 FAMILY

TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

MCLR

11818

IST

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low

Reset to the device.

OSC1/CLKI

OSC1

CLKI

13 32 30

—

CMOS

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

External clock source input. Always associated with

pin function OSC1. See related OSC2/CLKO pins.

OSC2/CLKO

OSC2

CLKO

14 33 31

—

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal

or resonator in Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO which

has 1/4 the frequency of OSC1 and denotes

the instruction cycle rate.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F45J10 FAMILY

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

21919

I/O

TTL

Analog

Digital I/O.

Analog Input 0.

RA1/AN1

RA1

AN1

32020

I/O

TTL

Analog

Digital I/O.

Analog Input 1.

RA2/AN2/VREF-/CVREF

RA2

AN2

VREF-

CVREF

42121

I/O

TTL

Analog

Digital I/O.

Analog Input 2.

A/D reference voltage (low) input.

Comparator reference voltage output.

RA3/AN3/VREF+

RA3

AN3

VREF+

52222

I/O

TTL

Analog

Digital I/O.

Analog Input 3.

A/D reference voltage (high) input.

RA5/AN4/SS1/C2OUT

RA5

AN4

SS1

C2OUT

72424

I/O

TTL

Analog

TTL

—

Digital I/O.

Analog Input 4.

SPI slave select input.

Comparator 2 output.

TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F45J10 FAMILY

PORTB is a bidirectional I/O port. PORTB can be

software programmed for internal weak pull-ups on

all inputs.

RB0/INT0/FLT0/AN12

RB0

INT0

FLT0

AN12

33 9 8

I/O

TTL

Analog

Digital I/O.

External Interrupt 0.

PWM Fault input for Enhanced CCP1.

Analog input 12.

RB1/INT1/AN10

RB1

INT1

AN10

34 10 9

I/O

TTL

Analog

Digital I/O.

External Interrupt 1.

Analog input 10.

RB2/INT2/AN8

RB2

INT2

AN8

35 11 10

I/O

TTL

Analog

Digital I/O.

External Interrupt 2.

Analog input 8.

RB3/AN9/CCP2

RB3

AN9

CCP2(1)

36 12 11

I/O

TTL

Analog

Digital I/O.

Analog Input 9.

Capture 2 input/Compare 2 output/PWM2 output.

RB4/KBI0/AN11

RB4

KBI0

AN11

37 14 14

I/O

TTL

Analog

Digital I/O.

Interrupt-on-change pin.

Analog Input 11.

RB5/KBI1/C1OUT

RB5

KBI1

C1OUT

38 15 15

I/O

TTL

—

Digital I/O.

Interrupt-on-change pin.

Comparator 1 output.

RB6/KBI2/PGC

RB6

KBI2

PGC

39 16 16

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP™ programming

clock pin.

RB7/KBI3/PGD

RB7

KBI3

PGD

40 17 17

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming

data pin.

TABLE 1-3 : PI C18F44 J10 /45J 10 PINO UT I/O DES CRIPT IONS (CO NTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F45J10 FAMILY

PORTC is a bidirectional I/O port.

RC0/T1OSO/T1CKI

RC0

T1OSO

T1CKI

15 34 32

I/O

—

Digital I/O.

Timer1 oscillator output.

Timer1 external clock input.

RC1/T1OSI/CCP2

RC1

T1OSI

CCP2(2)

16 35 35

I/O

CMOS

Digital I/O.

Timer1 oscillator input.

Capture 2 input/Compare 2 output/PWM2 output.

RC2/CCP1/P1A

RC2

CCP1

P1A

17 36 36

I/O

—

Digital I/O.

Capture 1 input/Compare 1 output/PWM1 output.

Enhanced CCP1 output.

RC3/SCK1/SCL1

RC3

SCK1

SCL1

18 37 37

I/O

Digital I/O.

Synchronous serial clock input/output for

SPI mode.

Synchronous serial clock input/output for

I2C™ mode.

RC4/SDI1/SDA1

RC4

SDI1

SDA1

23 42 42

I/O

Digital I/O.

SPI data in.

I2C data I/O.

RC5/SDO1

RC5

SDO1

24 43 43

I/O

—

Digital I/O.

SPI data out.

RC6/TX/CK

RC6

25 44 44

I/O

—

Digital I/O.

EUSART asynchronous transmit.

EUSART synchronous clock (see related RX/DT).

RC7/RX/DT

RC7

26 1 1

I/O

Digital I/O.

EUSART asynchronous receive.

EUSART synchronous data (see related TX/CK).

TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F45J10 FAMILY

PORTD is a bidirectional I/O port or a Parallel Slave

Port (PSP) for interfacing to a microprocessor port.

These pins have TTL input buffers when PSP module

is enabled.

RD0/PSP0/SCK2/

SCL2

RD0

PSP0

SCK2

SCL2

19 38 38

I/O

TTL

Digital I/O.

Parallel Slave Port data.

Synchronous serial clock input/output for

SPI mode.

Synchronous serial clock input/output for

I2C™ mode.

RD1/PSP1/SDI2/SDA2

RD1

PSP1

SDI2

SDA2

20 39 39

I/O

TTL

Digital I/O.

Parallel Slave Port data.

SPI data in.

I2C data I/O.

RD2/PSP2/SDO2

RD2

PSP2

SDO2

21 40 40

I/O

TTL

—

Digital I/O.

Parallel Slave Port data.

SPI data out.

RD3/PSP3/SS2

RD3

PSP3

SS2

22 41 41

I/O

TTL

Digital I/O.

Parallel Slave Port data.

SPI slave select input.

RD4/PSP4

RD4

PSP4

27 2 2

I/O

TTL

Digital I/O.

Parallel Slave Port data.

RD5/PSP5/P1B

RD5

PSP5

P1B

28 3 3

I/O

TTL

—

Digital I/O.

Parallel Slave Port data.

Enhanced CCP1 output.

RD6/PSP6/P1C

RD6

PSP6

P1C

29 4 4

I/O

TTL

—

Digital I/O.

Parallel Slave Port data.

Enhanced CCP1 output.

RD7/PSP7/P1D

RD7

PSP7

P1D

30 5 5

I/O

TTL

—

Digital I/O.

Parallel Slave Port data.

Enhanced CCP1 output.

TABLE 1-3 : PI C18F44 J10 /45J 10 PINO UT I/O DES CRIPT IONS (CO NTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F45J10 FAMILY

PORTE is a bidirectional I/O port.

RE0/RD/AN5

RE0

AN5

82525

I/O

TTL

Analog

Digital I/O.

Read control for Parallel Slave Port

(see also WR and CS pins).

Analog input 5.

RE1/WR/AN6

RE1

AN6

92626

I/O

TTL

Analog

Digital I/O.

Write control for Parallel Slave Port

(see CS and RD pins).

Analog input 6.

RE2/CS/AN7

RE2

AN7

10 27 27

I/O

TTL

Analog

Digital I/O.

Chip Select control for Parallel Slave Port

(see related RD and WR pins).

Analog input 7.

VSS 12, 31 6, 30,

6, 29 P — Ground reference for logic and I/O pins.

VDD 11, 32 7, 8,

28, 29

7, 28 P — Positive supply for logic and I/O pins.

VDDCORE/VCAP

VDDCORE

VCAP

62323

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

NC — 13 12, 13,

33, 34

— — No connect.

TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Number Pin

Type Buffer

Type Description

PDIP QFN TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

2.0 GUIDELINES FOR GETTING

STARTED WITH PIC18FJ

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC18F45J10 family family of

8-bit microcontrollers requires attention to a minimal

set of device pin connections before proceeding with

development.

The following pins must always be connected:

•All V

DD and VSS pins

(see Section 2.2 “Power Supply Pins”)

•All AV

DD and AVSS pins, regardless of whether or

not the analog device features are used

(see Section 2.2 “Power Supply Pins”)

•M

CLR pin

(see Section 2.3 “Master Clear (MCLR) Pin”)

• ENVREG (if implemented) and VCAP/VDDCORE pins

(see Section 2.4 “Voltage Regulator Pins

(VCAP/VDDCORE)”)

These pins must also be connected if they are being

used in the end application:

• PGC/PGD pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

• OSCI and OSCO pins when an external oscillator

source is used

(see Section 2.6 “External Oscillator Pins”)

Additionally, the following pins may be required:

•V

REF+/VREF- pins used when external voltage

reference for analog modules is implemented

The minimum mandatory connections are shown in

Figure 2-1.

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTIONS

Note: The AVDD and AVSS pins must always be

connected, regardless of whether any of

the analog modules are being used.

PIC18FXXJXX

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

VDD

MCLR

VCAP/VDDCORE

R2 ENVREG

(1)

C2(2)

C3(2)

C4(2)

C5(2)

C6(2)

Key (all values are recommendations):

C1 through C6: 0.1 μF, 20V ceramic

C7: 10 μF, 6.3V or greater, tantalum or ceramic

R1: 10 kΩ

R2: 100Ω to 470Ω

Note 1: See Secti on 2.4 “Voltage Regulator Pins

(VCAP/VDDCORE)” for explanation of

ENVREG pin connections.

2: The example shown is for a PIC18FJ device

with five VDD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;

adjust the number of decoupling capacitors

appropriately.

(1)

PIC18F45J10 FAMILY

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS, is required.

Consider the following criteria when using decoupling

capacitors:

•Value and type of capacitor: A 0.1 μF (100 nF),

10-20V capacitor is recommended. The capacitor

should be a low-ESR device with a resonance

frequency in the range of 200 MHz and higher.

Ceramic capacitors are recommended.

•Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater

than 0.25 inch (6 mm).

•Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of

tens of MHz), add a second ceramic type capaci-

tor in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 μF to 0.001 μF. Place this

second capacitor next to each primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible

(e.g., 0.1 μF in parallel with 0.001 μF).

•Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to

a minimum, thereby reducing PCB trace

inductance.

2.2.2 TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits including microcontrollers to

supply a local power source. The value of the tank

capacitor should be determined based on the trace

resistance that connects the power supply source to

the device and the maximum current drawn by the

device in the application. In other words, select the tank

capacitor so that it meets the acceptable voltage sag at

the device. Typical values range from 4.7 μF to 47 μF.

2.3 Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions: device Reset, and device programming

and debugging. If programming and debugging are

not required in the end application, a direct

connection to VDD may be all that is required. The

addition of other components, to help increase the

application’s resistance to spurious Resets from

voltage sags, may be beneficial. A typical

configuration is shown in Figure 2-1. Other circuit

designs may be implemented depending on the

application’s requirements.

During programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R1 and C1 will need to be adjusted based on the

application and PCB requirements. For example, it is

recommended that the capacitor, C1, be isolated

from the MCLR pin during programming and

debugging operations by using a jumper (Figure 2-2).

The jumper is replaced for normal run-time

operations.

Any components associated with the MCLR pin

should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

Note 1: R1 ≤10 kΩ is recommended. A suggested

starting value is 10 kΩ. Ensure that the

MCLR pin VIH and VIL specifications are met.

2: R2 ≤470Ω will limit any current flowing into

MCLR from the external capacitor, C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

VDD

MCLR

PIC18FXXJXX

PIC18F45J10 FAMILY

2.4 Voltage Regulator Pins

(VCAP/VDDCORE)

When the regulator is enabled (F devices), a low-ESR

(<5Ω) capacitor is required on the VCAP/VDDCORE pin to

stabilize the voltage regulator output voltage. The

VCAP/VDDCORE pin must not be connected to VDD and

must use a capacitor (10 μF typical) connected to

ground. The type can be ceramic or tantalum. A suitable

example is the Murata GRM21BF50J106ZE01 (10 μF,

6.3V) or equivalent. Designers may use Figure 2-3 to

evaluate ESR equivalence of candidate devices.

It is recommended that the trace length not exceed

0.25 inch (6 mm). Refer to Section 24.0 “Electrical

Characteristics” for additional information.

When the regulator is disabled (LF devices), the

VCAP/VDDCORE pin must be tied to a voltage supply at

the VDDCORE level. Refer to Section 24.0 “Electrical

Characteristics” for information on VDD and

VDDCORE.

FIGURE 2-3: FREQUENCY vs. ESR

PERFORMANCE FOR

SUGGESTED VCAP

2.5 ICSP Pins

The PGC and PGD pins are used for In-Circuit Serial

Programming (ICSP) and debugging purposes. It is

recommended to keep the trace length between the

ICSP connector and the ICSP pins on the device as

short as possible. If the ICSP connector is expected to

experience an ESD event, a series resistor is recom-

mended, with the value in the range of a few tens of

ohms, not to exceed 100Ω.

Pull-up resistors, series diodes and capacitors on the

PGC and PGD pins are not recommended as they will

interfere with the programmer/debugger com-

munications to the device. If such discrete components

are an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective device

Flash programming specification for information on

capacitive loading limits and pin input voltage high (VIH)

and input low (VIL) requirements.

For device emulation, ensure that the “Communication

Channel Select” (i.e., PGC/PGD pins) programmed

into the device matches the physical connections for

the ICSP to the MPLAB® ICD 2, MPLAB ICD 3 or

REAL ICE™ emulator.

For more information on the ICD 2, ICD 3 and REAL ICE

emulator connection requirements, refer to the following

documents that are available on the Microchip web site.

•“MPLAB® ICD 2 In-Circuit Debugger User’s

Guide” (DS51331)

•“Using MPLAB® ICD 2” (poster) (DS51265)

•“MPLAB® ICD 2 Design Advisory” (DS51566)

•“Using MPLAB® ICD 3” (poster) (DS51765)

•“MPLAB® ICD 3 Design Advisory” (DS51764)

•“MPLAB® REAL ICE™ I n-Circui t Emula tor Us er’s

Guide” (DS51616)

•“Using M PLAB® REAL ICE™ In- Circuit Em ulator”

(poster) (DS51749)

0.1

0.01

0.001 0.01 0.1 1 10 100 1000 10,000

Frequency (MHz)

ESR (Ω)

Note: Data for Murata GRM21BF50J106ZE01 shown.

Measurements at 25°C, 0V DC bias.

PIC18F45J10 FAMILY

2.6 External Oscillator Pins

Many microcontrollers have options for at least two

oscillators: a high-frequency primary oscillator and a

low-frequency secondary oscillator (refer to

Section 3.0 “Oscillator Configurations” for details).

The oscillator circuit should be placed on the same

side of the board as the device. Place the oscillator

circuit close to the respective oscillator pins with no

more than 0.5 inch (12 mm) between the circuit

components and the pins. The load capacitors should

be placed next to the oscillator itself, on the same side

of the board.

Use a grounded copper pour around the oscillator

circuit to isolate it from surrounding circuits. The

grounded copper pour should be routed directly to the

MCU ground. Do not run any signal traces or power

traces inside the ground pour. Also, if using a

two-sided board, avoid any traces on the other side of

the board where the crystal is placed. A suggested

layout is shown in Figure 2-4.

For additional information and design guidance on

oscillator circuits, please refer to these Microchip

Application Notes, available at the corporate web site

(www.microchip.com):

•AN826, “Crystal Oscillator Ba sics and Crystal

Selection for rfPIC™ and PICmicro® Devices”

•AN849, “Basic PICmicro® Oscillator Design”

• AN943, “Practical PICmicro® Oscillator Analysis

and Design”

•AN949, “Ma king Your Oscillator Work ”

FIGURE 2-4: SUGGESTED PLACEMENT

OF THE OSCILLATOR

CIRCUIT

2.7 Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic low state. Alternatively, connect a 1 kΩ

to 10 kΩ resistor to VSS on unused pins and drive the

output to logic low.

Main Oscillator

Guard Ring

Guard Trace

Secondary

Oscillator

PIC18F45J10 FAMILY

3.0 OSCILLATOR

CONFIGURATIONS

3.1 Oscillator Types

The PIC18F45J10 family of devices can be operated in

five different oscillator modes:

1. HS High-Speed Crystal/Resonator

2. HSPLL High-Speed Crystal/Resonator

with Software PLL Control

3. EC External Clock with FOSC/4 Output

4. ECPLL External Clock with Software PLL

Control

5. INTRC Internal 31 kHz Oscillator

Four of these are selected by the user by programming

the FOSC<2:0> Configuration bits. The fifth mode

(INTRC) may be invoked under software control; it can

also be configured as the default mode on device

Resets.

3.2 Crystal Oscillator/Ceramic

Resonators (HS Modes)

In HS or HSPLL Oscillator modes, a crystal or ceramic

resonator is connected to the OSC1 and OSC2 pins to

establish oscillation. Figure 3-1 shows the pin

connections.

The oscillator design requires the use of a parallel cut

crystal.

FIGURE 3-1: CRYSTAL/CERAMIC

RESONATOR OPERATION

(HS OR HSPLL

CONFIGURATION)

T ABLE 3-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

Note: Use of a series cut crystal may give a fre-

quency out of the crystal manufacturer’s

specifications.

Typical Capacitor Values Used:

Mode Freq. OSC1 OSC2

HS 8.0 MHz

16.0 MHz

27 pF

22 pF

27 pF

22 pF

Capacitor values are for design guidance only.

These capacitors were tested with the resonators

listed below for basic start-up and operation. These

values are not optimi zed.

Different capacitor values may be required to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes following Table 3-2 for additional

information.

Reson ators U sed :

4.0 MHz

8.0 MHz

16.0 MHz

Note 1: See Table 3-1 and Table 3-2 for initial values of

C1 and C2.

2: A series resistor (RS) may be required for AT

strip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

Logic

PIC18F45J10

RS(2)

Internal

PIC18F45J10 FAMILY

TABLE 3-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

3.3 External Clock Input (EC Modes)

The EC and ECPLL Oscillator modes require an exter-

nal clock source to be connected to the OSC1 pin.

There is no oscillator start-up time required after a

Power-on Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 3-2 shows the pin connections for the EC

Oscillator mode.

FIGURE 3-2: EXTERNAL CLOCK

INPUT OPERATION

(EC CONFIGURATION)

An external clock source may also be connected to the

OSC1 pin in the HS mode, as shown in Figure 3-3. In

this configuration, the divide-by-4 output on OSC2 is

not available.

FIGURE 3-3: EXTERNAL CLOCK INPUT

OPERATION (HS OSC

CONFIGURATION)

Osc Type Crystal

Freq.

Typical Cap acitor V alu es

Tested:

C1 C2

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listed

below for basic start-up and operation. These values

are not optimized.

Different capacitor values may be required to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

See the notes following this table for additional

information.

Crystals Used:

4 MHz

8 MHz

20 MHz

Note 1: Higher capacitance increases the stability

of oscillator but also increases the

start-up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

3: Rs may be required to avoid overdriving

crystals with low drive level specification.

4: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

OSC1/CLKI

OSC2/CLKO

FOSC/4

Clock from

Ext. System PIC18F45J10

OSC1

OSC2

Open

Clock from

Ext. System PIC18F45J10

(HS Mode)

PIC18F45J10 FAMILY

3.4 PLL Freque ncy Multi plier

A Phase Locked Loop (PLL) circuit is provided as an

option for users who want to use a lower frequency

oscillator circuit, or to clock the device up to its highest

rated frequency from a crystal oscillator. This may be

useful for customers who are concerned with EMI due

to high-frequency crystals, or users who require higher

clock speeds from an internal oscillator. For these

reasons, the HSPLL and ECPLL modes are available.

The HSPLL and ECPLL modes provide the ability to

selectively run the device at 4 times the external oscil-

lating source to produce frequencies up to 40 MHz.

The PLL is enabled by setting the PLLEN bit in the

OSCTUNE register (Register 3-1).

FIGURE 3-4: PLL BLOCK DIAGRAM

MUX

VCO

Loop

Filter

OSC2

OSC1

PLL Enable (OSCTUNE)

FIN

FOUT

SYSCLK

Phase

Comparator

HSPLL or ECPLL (CONFIG2L)

÷4

HS or EC

Mode

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

—PLLEN

(1) — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 PLLEN: Frequency Multiplier PLL Enable bit(1)

1 = PLL enabled

0 = PLL disabled

bit 5-0 Unimplemented: Read as ‘0’

Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and reads

as ‘0’.

PIC18F45J10 FAMILY

3.5 Internal Oscillator Block

The PIC18F45J10 family of devices includes an inter-

nal oscillator source (INTRC) which provides a nominal

31 kHz output. The INTRC is enabled on device

power-up and clocks the device during its configuration

cycle until it enters operating mode. INTRC is also

enabled if it is selected as the device clock source or if

any of the following are enabled:

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in

Section 21.0 “Special Features of the CPU”.

The INTRC can also be optionally configured as the

default clock source on device start-up by setting the

FOSC2 Configuration bit. This is discussed in

Section 3.6.1 “Oscillator Control Register”.

3.6 Clock Sources and

Oscillator Switching

The PIC18F45J10 family includes a feature that allows

the device clock source to be switched from the main

oscillator to an alternate clock source. PIC18F45J10

family devices offer two alternate clock sources. When

an alternate clock source is enabled, the various

power-managed operating modes are available.

Essentially, there are three clock sources for these

devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator

The primary oscillators include the External Crystal

and Resonator modes and the External Clock modes.

The particular mode is defined by the FOSC<2:0>

Configuration bits. The details of these modes are

covered earlier in this chapter.

The secondary oscillato rs are those external sources

not connected to the OSC1 or OSC2 pins. These

sources may continue to operate even after the

controller is placed in a power-managed mode.

PIC18F45J10 family devices offer the Timer1 oscillator

as a secondary oscillator. This oscillator, in all

power-managed modes, is often the time base for

functions such as a Real-Time Clock (RTC).

Most often, a 32.768 kHz watch crystal is connected

between the RC0/T1OSO/T13CKI and RC1/T1OSI

pins. Loading capacitors are also connected from each

pin to ground.

The Timer1 oscillator is discussed in greater detail in

Section 12.3 “Timer1 Oscillator”.

In addition to being a primary clock source, the internal

oscillator is available as a power-managed mode

clock source. The INTRC source is also used as the

clock source for several special features, such as the

WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F45J10 family devices

are shown in Figure 3-5. See Section 21.0 “Special

Features of the CPU” for Configuration register

details.

FIGURE 3-5: PIC18F45 J10 FAMILY CLOCK DIAGRAM

PIC18F45J10 Family

4 x PLL

FOSC<2:0>

T1OSCEN

Enable

Oscillator

T1OSO

T1OSI

Clock Source Option

for Other Modules

OSC1

OSC2

Sleep HSPLL, ECPLL

HS, EC

T1OSC

CPU

Peripherals

IDLEN

MUX

INTRC

Source

WDT, PWRT, FSCM

Internal Oscillator

Clock

Control

OSCCON<1:0>

and Two-Speed Start-up

Primary Oscillator

Secondary Oscillator

PIC18F45J10 FAMILY

3.6.1 OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 3-2) controls several

aspects of the device clock’s operation, both in

full-power operation and in power-managed modes.

The System Clock Select bits, SCS<1:0>, select the

clock source. The available clock sources are the

primary clock (defined by the FOSC<2:0> Configura-

tion bits), the secondary clock (Timer1 oscillator) and

the internal oscillator. The clock source changes after

one or more of the bits are written to, following a brief

clock transition interval.

The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)

bits indicate which clock source is currently providing

the device clock. The OSTS bit indicates that the

Oscillator Start-up Timer (OST) has timed out and the

primary clock is providing the device clock in primary

clock modes. The T1RUN bit indicates when the

Timer1 oscillator is providing the device clock in sec-

ondary clock modes. In power-managed modes, only

one of these bits will be set at any time. If neither of

these bits is set, the INTRC is providing the clock, or

the internal oscillator has just started and is not yet

stable.

The IDLEN bit determines if the device goes into Sleep

mode or one of the Idle modes when the SLEEP

instruction is executed.

The use of the flag and control bits in the OSCCON

“Power-M ana ged Modes”.

3.6.1.1 System Clock Selection and the

FOSC2 Configuration Bit

The SCS bits are cleared on all forms of Reset. In the

device’s default configuration, this means the primary

oscillator defined by FOSC<1:0> (that is, one of the HC

or EC modes) is used as the primary clock source on

device Resets.

The default clock configuration on Reset can be changed

with the FOSC2 Configuration bit. The effect of this bit is

to set the clock source selected when SCS<1:0> = 00.

When FOSC2 = 1 (default), the oscillator source

defined by FOSC<1:0> is selected whenever

SCS<1:0> = 00. When FOSC2 = 0, the INTRC oscillator

is selected whenever SCS<1:0> = 00. Because the SCS

bits are cleared on Reset, the FOSC2 setting also

changes the default oscillator mode on Reset.

Regardless of the setting of FOSC2, INTRC will always

be enabled on device power-up. It will serve as the

clock source until the device has loaded its configura-

tion values from memory. It is at this point that the

FOSC Configuration bits are read and the oscillator

selection of operational mode is made.

Note that either the primary clock or the internal

oscillator will have two bit setting options, at any given

time, depending on the setting of FOSC2.

3.6.2 OSCILLATOR TRANSITIONS

PIC18F45J10 family devices contain circuitry to

prevent clock “glitches” when switching between clock

sources. A short pause in the device clock occurs dur-

ing the clock switch. The length of this pause is the sum

of two cycles of the old clock source and three to four

cycles of the new clock source. This formula assumes

that the new clock source is stable.

Clock transitions are discussed in greater detail in

Section 4.1.2 “Entering Power-Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The

Timer1 oscillator is enabled by setting the

T1OSCEN bit in the Timer1 Control regis-

ter (T1CON<3>). If the Timer1 oscillator is

not enabled, then any attempt to select a

secondary clock source when executing a

SLEEP instruction will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before

executing the SLEEP instruction or a very

long delay may occur while the Timer1

oscillator starts.

PIC18F45J10 FAMILY

3.7 Effects of Power-Managed Modes

on the Various Clock Sources

When PRI_IDLE mode is selected, the designated pri-

mary oscillator continues to run without interruption.

For all other power-managed modes, the oscillator

using the OSC1 pin is disabled. The OSC1 pin (and

OSC2 pin if used by the oscillator) will stop oscillating.

In secondary clock modes (SEC_RUN and

SEC_IDLE), the Timer1 oscillator is operating and

providing the device clock. The Timer1 oscillator may

also run in all power-managed modes if required to

clock Timer1 or Timer3.

In RC_RUN and RC_IDLE modes, the internal oscilla-

tor provides the device clock source. The 31 kHz

INTRC output can be used directly to provide the clock

and may be enabled to support various special

features, regardless of the power-managed mode (see

Section 21.2 “Watchdog Timer (WDT)” through

Section 21.5 “Fail-Safe Clock Monitor” for more

information on WDT, Fail-Safe Clock Monitor and

Two-Speed Start-up).

If the Sleep mode is selected, all clock sources are

stopped. Since all the transistor switching currents

have been stopped, Sleep mode achieves the lowest

current consumption of the device (only leakage

currents).

Enabling any on-chip feature that will operate during

Sleep will increase the current consumed during Sleep.

The INTRC is required to support WDT operation. The

Timer1 oscillator may be operating to support a

real-time clock. Other features may be operating that

do not require a device clock source (i.e., MSSP slave,

PSP, INTx pins and others). Peripherals that may add

significant current consumption are listed in

Section 24.2 “DC Characteristics: Power-Down and

Supply Current”.

R/W-0 U-0 U-0 U-0 R-q(1) U-0 R/W-0 R/W-0

IDLEN — — —OSTS— SCS1 SCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters an Idle mode on SLEEP instruction

0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 Unimplemented: Read as ‘0’

bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)

1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running

0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready

bit 2 Unimplemented: Read as ‘0’

bit 1-0 SCS<1:0>: System Clock Select bits(4)

11 = Internal oscillator

10 = Primary oscillator

01 = Timer1 oscillator

When FOSC2 = 1:

00 = Primary oscillator

When FOSC2 = 0:

00 = Internal oscillator

Note 1: The Reset value is ‘0’ when HS mode and Two-Speed Start-up are both enabled; otherwise, it is ‘1’.

PIC18F45J10 FAMILY

3.8 Power-up Delays

Power-up delays are controlled by two timers, so that

no external Reset circuitry is required for most applica-

tions. The delays ensure that the device is kept in

Reset until the device power supply is stable under nor-

mal circumstances and the primary clock is operating

and stable. For additional information on power-up

delays, see Section 5.6 “Power-up Timer (PWRT)”.

The first timer is the Power-up Timer (PWRT), which

provides a fixed delay on power-up (parameter 33,

Table 24-10). It is always enabled.

The second timer is the Oscillator Start-up Timer

(OST), intended to keep the chip in Reset until the

crystal oscillator is stable (HS modes). The OST does

this by counting 1024 oscillator cycles before allowing

the oscillator to clock the device.

There is a delay of interval, TCSD (parameter 38,

Table 24-10), following POR, while the controller

becomes ready to execute instructions.

TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode OSC1 Pin OSC2 Pin

EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output)

HS, HSPLL Feedback inverter disabled at quiescent

voltage level

Feedback inverter disabled at quiescent

voltage level

Note: See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

4.0 POWER-MANAGED MODES

The PIC18F45J10 family devices provide the ability to

manage power consumption by simply managing clock-

ing to the CPU and the peripherals. In general, a lower

clock frequency and a reduction in the number of circuits

being clocked constitutes lower consumed power. For

the sake of managing power in an application, there are

three primary modes of operation:

• Run mode

• Idle mode

• Sleep mode

These modes define which portions of the device are

clocked and at what speed. The Run and Idle modes

may use any of the three available clock sources

(primary, secondary or internal oscillator block); the

Sleep mode does not use a clock source.

The power-managed modes include several

power-saving features offered on previous PIC®

microcontrollers. One is the clock switching feature,

offered in other PIC18 devices, allowing the controller

to use the Timer1 oscillator in place of the primary

oscillator. Also included is the Sleep mode, offered by

all PIC microcontrollers, where all device clocks are

stopped.

4.1 Selecting Power-Managed Modes

Selecting a power-managed mode requires two

decisions: if the CPU is to be clocked or not and which

clock source is to be used. The IDLEN bit

(OSCCON<7>) controls CPU clocking, while the

SCS<1:0> bits (OSCCON<1:0>) select the clock

source. The individual modes, bit settings, clock

sources and affected modules are summarized in

Table 4-1.

4.1.1 CLOCK SOURCES

The SCS<1:0> bits allow the selection of one of three

clock sources for power-managed modes. They are:

• the primary clock, as defined by the FOSC<1:0>

Configuration bits

• the secondary clock (Timer1 oscillator)

• the internal oscillator

4.1.2 ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another

begins by loading the OSCCON register. The

SCS<1:0> bits select the clock source and determine

which Run or Idle mode is to be used. Changing these

bits causes an immediate switch to the new clock

source, assuming that it is running. The switch may

also be subject to clock transition delays. These are

discussed in Section 4.1.3 “Clock Transitions and

Status Indicators” and subsequent sections.

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEP instruction. The

actual mode that results depends on the status of the

IDLEN bit.

Depending on the current mode and the mode being

switched to, a change to a power-managed mode does

not always require setting all of these bits. Many

transitions may be done by changing the oscillator

select bits, or changing the IDLEN bit, prior to issuing a

SLEEP instruction. If the IDLEN bit is already

configured correctly, it may only be necessary to

perform a SLEEP instruction to switch to the desired

mode.

TABLE 4-1: POWER-MANAGED MODES

Mode OSCCON bits Module Clocking Available Clock and Oscillator Source

IDLEN<7>(1) SCS<1:0> CPU Peripherals

Sleep 0N/A Off Off None – All clocks are disabled

PRI_RUN N/A 10 Clocked Clocked Primary – HS, EC;

this is the normal full-power execution mode

SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator

RC_RUN N/A 11 Clocked Clocked Internal Oscillator

PRI_IDLE 110Off Clocked Primary – HS, EC

SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator

RC_IDLE 111Off Clocked Internal Oscillator

Note 1: IDLEN reflects its value when the SLEEP instruction is executed.

PIC18F45J10 FAMILY

4.1.3 CLOCK TRANSITIONS AND STATUS

INDICATORS

The length of the transition between clock sources is

the sum of two cycles of the old clock source and three

to four cycles of the new clock source. This formula

assumes that the new clock source is stable.

Two bits indicate the current clock source and its

status: OSTS (OSCCON<3>) and T1RUN

(T1CON<6>). In general, only one of these bits will be

set while in a given power-managed mode. When the

OSTS bit is set, the primary clock is providing the

device clock. When the T1RUN bit is set, the Timer1

oscillator is providing the clock. If neither of these bits

is set, INTRC is clocking the device.

4.1.4 MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the

SLEEP instruction is determined by the setting of the

IDLEN bit at the time the instruction is executed. If

another SLEEP instruction is executed, the device will

enter the power-managed mode specified by IDLEN at

that time. If IDLEN has changed, the device will enter the

new power-managed mode specified by the new setting.

4.2 Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock source.

4.2.1 PRI_RUN MODE

The PRI_RUN mode is the normal, full-power execu-

tion mode of the microcontroller. This is also the default

mode upon a device Reset unless Two-Speed Start-up

is enabled (see Section 21.4 “Two-Speed Start-up”

for details). In this mode, the OSTS bit is set. (see

Section 3.6.1 “Oscillator Control Register”).

4.2.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the

“clock switching” feature offered in other PIC18

devices. In this mode, the CPU and peripherals are

clocked from the Timer1 oscillator. This gives users the

option of lower power consumption while still using a

high-accuracy clock source.

SEC_RUN mode is entered by setting the SCS<1:0>

bits to ‘01’. The device clock source is switched to the

Timer1 oscillator (see Figure 4-1), the primary

oscillator is shut down, the T1RUN bit (T1CON<6>) is

set and the OSTS bit is cleared.

On transitions from SEC_RUN mode to PRI_RUN

mode, the peripherals and CPU continue to be clocked

from the Timer1 oscillator while the primary clock is

started. When the primary clock becomes ready, a

clock switch back to the primary clock occurs (see

Figure 4-2). When the clock switch is complete, the

T1RUN bit is cleared, the OSTS bit is set and the

primary clock is providing the clock. The IDLEN and

SCS bits are not affected by the wake-up; the Timer1

oscillator continues to run.

FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

Note: Executing a SLEEP instruction does not

necessarily place the device into Sleep

mode. It acts as the trigger to place the

controller into either Sleep mode or one of

the Idle modes, depending on the setting

of the IDLEN bit.

Note: The Timer1 oscillator should already be

running prior to entering SEC_RUN mode.

If the T1OSCEN bit is not set when the

SCS<1:0> bits are set to ‘01’, entry to

SEC_RUN mode will not occur. If the

Timer1 oscillator is enabled, but not yet

running, device clocks will be delayed until

the oscillator has started. In such situa-

tions, initial oscillator operation is far from

stable and unpredictable operation may

result.

Q4Q3Q2

OSC1

Peripheral

Program

T1OSI

Counter

Clock

CPU

Clock

PC + 2PC

123

n-1

Clock Transition

Q4Q3Q2 Q1 Q3Q2

PC + 4

PIC18F45J10 FAMILY

4.2.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator; the primary clock is

shut down. This mode provides the best power conser-

vation of all the Run modes, while still executing code.

It works well for user applications which are not highly

timing-sensitive or do not require high-speed clocks at

all times.

This mode is entered by setting SCS<1:0> to ‘11’.

When the clock source is switched to the INTRC (see

Figure 4-2), the primary oscillator is shut down and the

OSTS bit is cleared.

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the INTRC

while the primary clock is started. When the primary

clock becomes ready, a clock switch to the primary

clock occurs (see Figure 4-3). When the clock switch is

complete, the OSTS bit is set and the primary clock is

providing the device clock. The IDLEN and SCS bits

are not affected by the switch. The INTRC source will

continue to run if either the WDT or the Fail-Safe Clock

Monitor is enabled.

FIGURE 4-2: TRANSITION TIMING TO RC_RUN MODE

FIGURE 4-3: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q4Q3Q2

OSC1

Peripheral

Program

INTRC

Counter

Clock

CPU

Clock

PC + 2PC

123 n-1n

Clock Transition

Q4Q3Q2 Q1 Q3Q2

PC + 4

Q1 Q3 Q4

OSC1

Peripheral

Program PC

INTRC

PC + 4

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC. These intervals are not shown to scale.

SCS<1:0> bits Changed OSTS bit Set

TOST(1)

PIC18F45J10 FAMILY

4.3 Sleep Mode

The power-managed Sleep mode is identical to the

legacy Sleep mode offered in all other PIC micro-

controllers. It is entered by clearing the IDLEN bit (the

default state on device Reset) and executing the

SLEEP instruction. This shuts down the selected

oscillator (Figure 4-4). All clock source status bits are

cleared.

Entering the Sleep mode from any other mode does not

require a clock switch. This is because no clocks are

needed once the controller has entered Sleep. If the

WDT is selected, the INTRC source will continue to

operate. If the Timer1 oscillator is enabled, it will also

continue to run.

When a wake event occurs in Sleep mode (by interrupt,

Reset or WDT time-out), the device will not be clocked

until the clock source selected by the SCS<1:0> bits

becomes ready (see Figure 4-5), or it will be clocked

from the internal oscillator if either the Two-Speed

Start-up or the Fail-Safe Clock Monitor are enabled

(see Se ction 21.0 “S pecial Features o f the CPU”). In

either case, the OSTS bit is set when the primary clock

is providing the device clocks. The IDLEN and SCS bits

are not affected by the wake-up.

4.4 Idle Modes

The Idle modes allow the controller’s CPU to be

selectively shut down while the peripherals continue to

operate. Selecting a particular Idle mode allows users

to further manage power consumption.

If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is

executed, the peripherals will be clocked from the clock

source selected using the SCS<1:0> bits; however, the

CPU will not be clocked. The clock source status bits are

not affected. Setting IDLEN and executing a SLEEP

instruction provides a quick method of switching from a

given Run mode to its corresponding Idle mode.

If the WDT is selected, the INTRC source will continue

to operate. If the Timer1 oscillator is enabled, it will also

continue to run.

Since the CPU is not executing instructions, the only

exits from any of the Idle modes are by interrupt, WDT

time-out or a Reset. When a wake event occurs, CPU

execution is delayed by an interval of TCSD

(parameter 38, Table 24-10) while it becomes ready to

execute code. When the CPU begins executing code,

it resumes with the same clock source for the current

Idle mode. For example, when waking from RC_IDLE

mode, the internal oscillator block will clock the CPU

and peripherals (in other words, RC_RUN mode). The

IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT

time-out will result in a WDT wake-up to the Run mode

currently specified by the SCS<1:0> bits.

FIGURE 4-4: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

FIGURE 4-5: TRANSITION TIMING FOR WAKE FROM SLEEP

Q4Q3Q2

OSC1

Peripheral

Sleep

Program

Q1Q1

Counter

Clock

CPU

Clock

PC + 2PC

Q3 Q4 Q1 Q2

OSC1

Peripheral

Program PC

Q3 Q4

CPU Clock

Q1 Q2 Q3 Q4 Q1 Q2

Clock

Counter PC + 6

PC + 4

Q1 Q2 Q3 Q4

Wake Event

Note1: TOST = 1024 TOSC. These intervals are not shown to scale.

TOST(1)

OSTS bit Set

PC + 2

PIC18F45J10 FAMILY

4.4.1 PRI_IDLE MODE

This mode is unique among the three low-power Idle

modes, in that it does not disable the primary device

clock. For timing-sensitive applications, this allows for

the fastest resumption of device operation with its more

accurate primary clock source, since the clock source

does not have to “warm up” or transition from another

oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing a SLEEP instruc-

tion. If the device is in another Run mode, set IDLEN

first, then set the SCS<1:0> bits to ‘10’ and execute

SLEEP. Although the CPU is disabled, the peripherals

continue to be clocked from the primary clock source

specified by the FOSC0 Configuration bit. The OSTS

bit remains set (see Figure 4-6).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval, TCSD, is

required between the wake event and when code

execution starts. This is required to allow the CPU to

become ready to execute instructions. After the

wake-up, the OSTS bit remains set. The IDLEN and

SCS bits are not affected by the wake-up (see

Figure 4-7).

4.4.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the Timer1

oscillator. This mode is entered from SEC_RUN by set-

ting the IDLEN bit and executing a SLEEP instruction. If

the device is in another Run mode, set IDLEN first, then

set SCS<1:0> to ‘01’ and execute SLEEP. When the

clock source is switched to the Timer1 oscillator, the

primary oscillator is shut-down, the OSTS bit is cleared

and the T1RUN bit is set.

When a wake event occurs, the peripherals continue to

be clocked from the Timer1 oscillator. After an interval

of TCSD following the wake event, the CPU begins exe-

cuting code being clocked by the Timer1 oscillator. The

IDLEN and SCS bits are not affected by the wake-up;

the Timer1 oscillator continues to run (see Figure 4-7).

FIGURE 4-6: TRANSITION TIMING FOR ENTRY TO IDLE MODE

FIGURE 4-7: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.

If the T1OSCEN bit is not set when the

SLEEP instruction is executed, the SLEEP

instruction will be ignored and entry to

SEC_IDLE mode will not occur. If the

Timer1 oscillator is enabled, but not yet

running, peripheral clocks will be delayed

until the oscillator has started. In such

situations, initial oscillator operation is far

from stable and unpredictable operation

may result.

Peripheral

Program PC PC + 2

OSC1

Q3 Q4 Q1

CPU Clock

Clock

Counter

OSC1

Peripheral

Program PC

CPU Clock

Q1 Q3 Q4

Clock

Counter

Wake Event

TCSD

PIC18F45J10 FAMILY

4.4.3 RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled but the periph-

erals continue to be clocked from the internal oscillator.

This mode allows for controllable power conservation

during Idle periods.

From RC_RUN, this mode is entered by setting the

IDLEN bit and executing a SLEEP instruction. If the

device is in another Run mode, first set IDLEN, then

clear the SCS bits and execute SLEEP. When the clock

source is switched to the INTRC, the primary oscillator

is shut down and the OSTS bit is cleared.

When a wake event occurs, the peripherals continue to

be clocked from the INTRC. After a delay of TCSD

following the wake event, the CPU begins executing

code being clocked by the INTRC. The IDLEN and

SCS bits are not affected by the wake-up. The INTRC

source will continue to run if either the WDT or the

Fail-Safe Clock Monitor is enabled.

4.5 Exiting Idle and Sleep Modes

An exit from Sleep mode, or any of the Idle modes, is

triggered by an interrupt, a Reset or a WDT time-out.

This section discusses the triggers that cause exits

from power-managed modes. The clocking subsystem

actions are discussed in each of the power-managed

modes sections (see Section 4.2 “Run Modes”,

Section 4.3 “Sleep Mode” and Section 4.4 “Idle

Modes”).

4.5.1 EXIT BY INTERRUPT

Any of the available interrupt sources can cause the

device to exit from an Idle mode, or the Sleep mode, to

a Run mode. To enable this functionality, an interrupt

source must be enabled by setting its enable bit in one

of the INTCON or PIE registers. The exit sequence is

initiated when the corresponding interrupt flag bit is set.

On all exits from Idle or Sleep modes by interrupt, code

execution branches to the interrupt vector if the

GIE/GIEH bit (INTCON<7>) is set. Otherwise, code

execution continues or resumes without branching

(see Section 9.0 “Interrupts”).

A fixed delay of interval, TCSD, following the wake event

is required when leaving Sleep and Idle modes. This

delay is required for the CPU to prepare for execution.

Instruction execution resumes on the first clock cycle

following this delay.

4.5.2 EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending

on which power-managed mode the device is in when

the time-out occurs.

If the device is not executing code (all Idle modes and

Sleep mode), the time-out will result in an exit from the

power-managed mode (see Section 4.2 “Run

Modes” and Section 4.3 “Sleep Mode ”). If the device

is executing code (all Run modes), the time-out will

result in a WDT Reset (see Section 21.2 “Watchdog

Timer (WDT)”).

The WDT timer and postscaler are cleared by one of

the following events:

• executing a SLEEP or CLRWDT instruction

• the loss of a currently selected clock source (if the

Fail-Safe Clock Monitor is enabled)

4.5.3 EXIT BY RESET

Exiting an Idle or Sleep mode by Reset automatically

forces the device to run from the INTRC.

4.5.4 EXIT WITHOUT AN OSCILLATOR

START-UP DELAY

Certain exits from power-managed modes do not

invoke the OST at all. There are two cases:

• PRI_IDLE mode where the primary clock source

is not stopped; and

• the primary clock source is the EC mode.

In these instances, the primary clock source either

does not require an oscillator start-up delay, since it is

already running (PRI_IDLE), or normally does not

require an oscillator start-up delay (EC). However, a

fixed delay of interval, T

CSD, following the wake event

is still required when leaving Sleep and Idle modes to

allow the CPU to prepare for execution. Instruction

execution resumes on the first clock cycle following this

delay.

PIC18F45J10 FAMILY

5.0 RESET

The PIC18F45J10 family of devices differentiate

between various kinds of Reset:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during power-managed modes

d) Watchdog Timer (WDT) Reset (during

execution)

e) Configuration Mismatch (CM)

f) Brown-out Reset (BOR)

g) RESET Instruction

h) Stack Full Reset

i) Stack Underflow Reset

This section discusses Resets generated by MCLR,

POR and BOR and covers the operation of the various

start-up timers. Stack Reset events are covered in

Section 6.1.4.4 “Stack Full and Underflow Resets”.

WDT Resets are covered in Section 21.2 “Watchdog

Timer (WDT)”.

A simplified block diagram of the on-chip Reset circuit

is shown in Figure 5-1.

5.1 RCON Register

Device Reset events are tracked through the RCON

indicate that a specific Reset event has occurred. In

most cases, these bits can only be set by the event and

must be cleared by the application after the event. The

state of these flag bits, taken together, can be read to

indicate the type of Reset that just occurred. This is

described in more detail in Section 5.7 “Reset State

of Registers”.

The RCON register also has a control bit for setting

interrupt priority (IPEN). Interrupt priority is discussed

in Section 9.0 “Interrupts”.

FIGURE 5-1: SIMPLI FIED B LOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR

VDD

WDT

Time-out

VDD Rise

Detect

PWRT

INTRC

POR Pulse

Chip_Reset

Brown-out

Reset(1)

RESET Instruction

Stack

Pointer

Stack Full/Underflow Reset

Sleep

( )_IDLE

32 μs

Note 1: The Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.

PWRT

11-Bit Ripple Counter

66 ms

Configuration Word Mismatch

PIC18F45J10 FAMILY

R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0

IPEN —CMRI TO PD POR BOR(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 Unimplemented: Read as ‘0’

bit 5 CM: Configuration Mismatch Flag bit

1 = A Configuration Mismatch Reset has not occurred

0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration

Mismatch Reset occurs)

bit 4 RI: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)

0 = The RESET instruction was executed causing a device Reset (must be set in software after a

Brown-out Reset occurs)

bit 3 TO: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 2 PD: Power-Down Detection Flag bit

1 = Set by power-up or by the CLRWDT instruction

0 = Set by execution of the SLEEP instruction

bit 1 POR: Power-on Reset Status bit

1 = A Power-on Reset has not occurred (set by firmware only)

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit(1)

1 = A Brown-out Reset has not occurred (set by firmware only)

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: BOR is not available on PIC18LF2XJ10/4XJ10 devices.

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent

Power-on Resets may be detected.

2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 5.4.1 “Detecting

BOR” for more information.

3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to

‘1’ by software immediately after a Power-on Reset).

PIC18F45J10 FAMILY

5.2 Mast er Clear (MCLR)

The MCLR pin provides a method for triggering a hard

external Reset of the device. A Reset is generated by

holding the pin low. PIC18 extended microcontroller

devices have a noise filter in the MCLR Reset path

which detects and ignores small pulses.

The MCLR pin is not driven low by any internal Resets,

including the WDT.

5.3 Power-on Reset (POR)

A Power-on Reset condition is generated on-chip

whenever VDD rises above a certain threshold. This

allows the device to start in the initialized state when

VDD is adequate for operation.

To take advantage of the POR circuitry, tie the MCLR

pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will

eliminate external RC components usually needed to

create a Power-on Reset delay. A minimum rise rate for

VDD is specified (parameter D004). For a slow rise

time, see Figure 5-2.

When the device starts normal operation (i.e., exits the

Reset condition), device operating parameters

(voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

Power-on Reset events are captured by the POR bit

(RCON<1>). The state of the bit is set to ‘0’ whenever

a Power-on Reset occurs; it does not change for any

other Reset event. POR is not reset to ‘1’ by any

hardware event. To capture multiple events, the user

manually resets the bit to ‘1’ in software following any

Power-on Reset.

5.4 Brown-out Reset (BOR)

(PIC18F2XJ10/4XJ10 Devices Only)

The PIC18F45J10 family of devices incorporates a

simple BOR function when the internal regulator is

enabled (ENVREG pin is tied to VDD). Any drop of VDD

below VBOR (parameter D005) for greater than time

TBOR (parameter 35) will reset the device. A Reset may

or may not occur if VDD falls below VBOR for less than

TBOR. The chip will remain in Brown-out Reset until

VDD rises above VBOR.

Once a BOR has occurred, the Power-up Timer will

keep the chip in Reset for TPWRT (parameter 33). If

VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be initialized. Once VDD

rises above VBOR, the Power-up Timer will execute the

additional time delay.

FIGURE 5-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

5.4.1 DETECTING BOR

The BOR bit always resets to ‘0’ on any Brown-out

Reset or Power-on Reset event. This makes it difficult

to determine if a Brown-out Reset event has occurred

just by reading the state of BOR alone. A more reliable

method is to simultaneously check the state of both

POR and BOR. This assumes that the POR bit is reset

to ‘1’ in software immediately after any Power-on Reset

event. If BOR is ‘0’ while POR is ‘1’, it can be reliably

assumed that a Brown-out Reset event has occurred.

In devices designated with an “LF” part number (such

as PIC18LF25J10), Brown-out Reset functionality is

disabled. In this case, the BOR bit cannot be used to

determine a Brown-out Reset event. The BOR bit is still

cleared by a Power-on Reset event.

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3: R1 ≥ 1 kΩ will limit any current flowing into

MCLR from external capacitor C, in the event

of MCLR pin breakdown, due to Electrostatic

Discharge (ESD) or Electrical Overstress

(EOS).

VDD

MCLR

PIC18F45J10

VDD

PIC18F45J10 FAMILY

5.5 Configuration Mismatch (CM)

The Configuration Mismatch (CM) Reset is designed to

detect and attempt to recover from random, memory

corrupting events. These include Electrostatic Discharge

(ESD) events, which can cause widespread, single-bit

changes throughout the device and result in catastrophic

failure.

In PIC18FXXJ Flash devices, the device Configuration

registers (located in the configuration memory space)

are continuously monitored during operation by

comparing their values to complimentary shadow reg-

isters. If a mismatch is detected between the two sets

of registers, a CM Reset automatically occurs. These

events are captured by the CM bit (RCON<5>). The

state of the bit is set to ‘0’ whenever a CM event occurs;

it does not change for any other Reset event.

A CM Reset behaves similarly to a Master Clear Reset,

RESET instruction, WDT time-out or Stack Event

Resets. As with all hard and power Reset events, the

device Configuration Words are reloaded from the

Flash Configuration Words in program memory as the

device restarts.

5.6 Power-up Timer (PWRT)

PIC18F45J10 family devices incorporate an on-chip

Power-up Timer (PWRT) to help regulate the Power-on

Reset process. The PWRT is always enabled. The

main function is to ensure that the device voltage is

stable before code is executed.

The Power-up Timer (PWRT) of the PIC18F45J10

family devices is an 11-bit counter which uses the

INTRC source as the clock input. This yields an

approximate time interval of 2048 x 32 μs=65.6ms.

While the PWRT is counting, the device is held in

Reset.

The power-up time delay depends on the INTRC clock

and will vary from chip to chip due to temperature and

process variation. See DC parameter 33 for details.

5.6.1 TIME-OUT SEQUENCE

If enabled, the PWRT time-out is invoked after the POR

pulse has cleared. The total time-out will vary based on

the status of the PWRT. Figure 5-3, Figure 5-4,

Figure 5-5 and Figure 5-6 all depict time-out

sequences on power-up with the Power-up Timer

enabled.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the PWRT will expire. Bringing

MCLR high will begin execution immediately

(Figure 5-5). This is useful for testing purposes, or to

synchronize more than one PIC18F device operating in

parallel.

FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

TPWRT

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

PIC18F45J10 FAMILY

FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, V DD RISE > TPWRT)

TPWRT

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

TPWRT

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

0V 1V

3.3V

TPWRT

PIC18F45J10 FAMILY

5.7 Reset State of Registers

Most registers are unaffected by a Reset. Their status

is unknown on POR and unchanged by all other

Resets. The other registers are forced to a “Reset

state” depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal

operation. Status bits from the RCON register (CM, RI,

TO, PD, POR and BOR) are set or cleared differently in

different Reset situations, as indicated in Table 5-1.

These bits are used in software to determine the nature

of the Reset.

Table 5-2 describes the Reset states for all of the

Special Function Registers. These are categorized by

Power-on and Brown-out Resets, Master Clear and

WDT Resets and WDT wake-ups.

TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Condition Program

Counter(1) RCON Register STKPTR Register

CM RI TO PD POR BOR(2) STKFUL STKUNF

Power-on Reset 0000h 111100 0 0

RESET instruction 0000h u0uuuu u u

Brown-out Reset 0000h 1111u0 u u

Configuration Mismatch Reset 0000h 0uuuuu u u

MCLR Reset during

power-managed Run modes

0000h uu1uuu u u

MCLR Reset during

power-managed Idle modes

and Sleep mode

0000h uu10uu u u

MCLR Reset during full-power

execution

0000h uuuuuu u u

Stack Full Reset (STVREN = 1) 0000h uuuuuu 1 u

Stack Underflow Reset

(STVREN = 1)

0000h uuuuuu u 1

Stack Underflow Error (not an

actual Reset, STVREN = 0)

0000h uuuuuu u 1

WDT time-out during full-power

or power-managed Run modes

0000h uu0uuu u u

WDT time-out during

power-managed Idle or Sleep

modes

PC + 2 uu00uu u u

Interrupt exit from

power-managed modes

PC + 2 uuu0uu u u

Legend: u = unchanged

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

2: BOR is not available on PIC18LF2XJ10/4XJ10 devices.

PIC18F45J10 FAMILY

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Brown-out Reset

MCLR Re sets,

WDT Reset,

RESET Instruction,

Stack Resets,

CM Resets

Wake-up via WDT

or Interrupt

TOSU PIC18F2XJ10 PIC18F4XJ10 ---0 0000 ---0 0000 ---0 uuuu(1)

TOSH PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu(1)

TOSL PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu(1)

STKPTR PIC18F2XJ10 PIC18F4XJ10 00-0 0000 uu-0 0000 uu-u uuuu(1)

PCLATU PIC18F2XJ10 PIC18F4XJ10 ---0 0000 ---0 0000 ---u uuuu

PCLATH PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

PCL PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 PC + 2(2)

TBLPTRU PIC18F2XJ10 PIC18F4XJ10 --00 0000 --00 0000 --uu uuuu

TBLPTRH PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

TBLPTRL PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

TABLAT PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

PRODH PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

PRODL PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

INTCON PIC18F2XJ10 PIC18F4XJ10 0000 000x 0000 000u uuuu uuuu(3)

INTCON2 PIC18F2XJ10 PIC18F4XJ10 1111 -1-1 1111 -1-1 uuuu -u-u(3)

INTCON3 PIC18F2XJ10 PIC18F4XJ10 11-0 0-00 11-0 0-00 uu-u u-uu(3)

INDF0 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

POSTINC0 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

POSTDEC0 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

PREINC0 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

PLUSW0 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

FSR0H PIC18F2XJ10 PIC18F4XJ10 ---- xxxx ---- uuuu ---- uuuu

FSR0L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

WREG PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

INDF1 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

POSTINC1 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

POSTDEC1 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

PREINC1 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

PLUSW1 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

FSR1H PIC18F2XJ10 PIC18F4XJ10 ---- xxxx ---- uuuu ---- uuuu

FSR1L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

BSR PIC18F2XJ10 PIC18F4XJ10 ---- 0000 ---- 0000 ---- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

PIC18F45J10 FAMILY

INDF2 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

POSTINC2 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

POSTDEC2 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

PREINC2 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

PLUSW2 PIC18F2XJ10 PIC18F4XJ10 N/A N/A N/A

FSR2H PIC18F2XJ10 PIC18F4XJ10 ---- xxxx ---- uuuu ---- uuuu

FSR2L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

STATUS PIC18F2XJ10 PIC18F4XJ10 ---x xxxx ---u uuuu ---u uuuu

TMR0H PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

TMR0L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

T0CON PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu

OSCCON PIC18F2XJ10 PIC18F4XJ10 0--- q-00 0--- q-00 u--- q-uu

WDTCON PIC18F2XJ10 PIC18F4XJ10 ---- ---0 ---- ---0 ---- ---u

RCON(4) PIC18F2XJ10 PIC18F4XJ10 0-11 11q0 0-qq qquu u-uu qquu

TMR1H PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

T1CON PIC18F2XJ10 PIC18F4XJ10 0000 0000 u0uu uuuu uuuu uuuu

TMR2 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

PR2 PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 1111 1111

T2CON PIC18F2XJ10 PIC18F4XJ10 -000 0000 -000 0000 -uuu uuuu

SSP1BUF PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

SSP1ADD PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

SSP1STAT PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

SSP1CON1 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

SSP1CON2 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

ADRESH PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

ADRESL PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 PIC18F2XJ10 PIC18F4XJ10 0-00 0000 0-00 0000 u-uu uuuu

ADCON1 PIC18F2XJ10 PIC18F4XJ10 --00 0qqq --00 0qqq --uu uqqq

ADCON2 PIC18F2XJ10 PIC18F4XJ10 0-00 0000 0-00 0000 u-uu uuuu

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Re sets,

WDT Reset,

RESET Instruction,

Stack Resets,

CM Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

PIC18F45J10 FAMILY

CCPR1H PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

CCPR2H PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2L PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

CCP2CON PIC18F2XJ10 PIC18F4XJ10 --00 0000 --00 0000 --uu uuuu

BAUDCON PIC18F2XJ10 PIC18F4XJ10 01-0 0-00 01-0 0-00 uu-u u-uu

ECCP1DEL PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

ECCP1AS PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

CVRCON PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

CMCON PIC18F2XJ10 PIC18F4XJ10 0000 0111 0000 0111 uuuu uuuu

SPBRGH PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

SPBRG PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

RCREG PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

TXREG PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

TXSTA PIC18F2XJ10 PIC18F4XJ10 0000 0010 0000 0010 uuuu uuuu

RCSTA PIC18F2XJ10 PIC18F4XJ10 0000 000x 0000 000x uuuu uuuu

EECON2 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

EECON1 PIC18F2XJ10 PIC18F4XJ10 ---0 x00- ---0 x00- ---u uuu-

IPR3 PIC18F2XJ10 PIC18F4XJ10 11-- ---- 11-- ---- uu-- ----

PIR3 PIC18F2XJ10 PIC18F4XJ10 00-- ---- 00-- ---- uu-- ----(3)

PIE3 PIC18F2XJ10 PIC18F4XJ10 00-- ---- 00-- ---- uu-- ----

IPR2 PIC18F2XJ10 PIC18F4XJ10 11-- 1--1 11-- 1--1 uu-- u--u

PIR2 PIC18F2XJ10 PIC18F4XJ10 00-- 0--0 00-- 0--0 uu-- u--u(3)

PIE2 PIC18F2XJ10 PIC18F4XJ10 00-- 0--0 00-- 0--0 uu-- u--u

IPR1 PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu

PIR1 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu(3)

PIE1 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Re sets,

WDT Reset,

RESET Instruction,

Stack Resets,

CM Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

PIC18F45J10 FAMILY

TRISE PIC18F2XJ10 PIC18F4XJ10 0000 -111 1111 -111 uuuu -uuu

TRISD PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu

TRISC PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu

TRISB PIC18F2XJ10 PIC18F4XJ10 1111 1111 1111 1111 uuuu uuuu

TRISA PIC18F2XJ10 PIC18F4XJ10 --1- 1111 --1- 1111 --u- uuuu

SSP2BUF PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

LATE PIC18F2XJ10 PIC18F4XJ10 ---- -xxx ---- -uuu ---- -uuu

LATD PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

LATC PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

LATB PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

LATA PIC18F2XJ10 PIC18F4XJ10 --xx xxxx --uu uuuu --uu uuuu

SSP2ADD PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

SSP2STAT PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

SSP2CON1 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

SSP2CON2 PIC18F2XJ10 PIC18F4XJ10 0000 0000 0000 0000 uuuu uuuu

PORTE PIC18F2XJ10 PIC18F4XJ10 ---- -xxx ---- -uuu ---- -uuu

PORTD PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

PORTC PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

PORTB PIC18F2XJ10 PIC18F4XJ10 xxxx xxxx uuuu uuuu uuuu uuuu

PORTA PIC18F2XJ10 PIC18F4XJ10 --0- 0000 --0- 0000 --u- uuuu

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset

MCLR Re sets,

WDT Reset,

RESET Instruction,

Stack Resets,

CM Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

PIC18F45J10 FAMILY

6.0 MEMORY ORGANIZATION

There are two types of memory in PIC18 Enhanced

microcontroller devices:

• Program Memory

• Data RAM

As Harvard architecture devices, the data and program

memories use separate busses; this allows for

concurrent access of the two memory spaces.

Additional detailed information on the operation of the

Flash program memory is provided in Section 7.0

“Flash Program Memory”.

6.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program

counter, which is capable of addressing a 2-Mbyte

program memory space. Accessing a location between

the upper boundary of the physically implemented

memory and the 2-Mbyte address will return all ‘0’s (a

NOP instruction).

The PIC18F24J10 and PIC18F44J10 each have

16 Kbytes of Flash memory and can store up to

8,192 single-word instructions. The PIC18F25J10 and

PIC18F45J10 each have 32 Kbytes of Flash memory

and can store up to 16,384 single-word instructions.

PIC18 devices have two interrupt vectors. The Reset

vector address is at 0000h and the interrupt vector

addresses are at 0008h and 0018h.

The program memory map for the PIC18F45J10 family

devices is shown in Figure 6-1.

FIGURE 6-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F45J10 FAMILY DEVICES

PC<20:0>

Stack Level 1

•

Stack Level 31

Reset Vector

Low-Priority Interrupt Vector

•

CALL,RCALL,RETURN

RETFIE,RETLW

0000h

0018h

On-Chip

Program Memory

High-Priority Interrupt Vector 0008h

User Memory Space

1FFFFFh

4000h

Read ‘0’

200000h

PIC18FX4J10

PIC18FX5J10

8000h

On-Chip

Program Memory

Read ‘0’

3FF7h

7FF7h

PIC18F45J10 FAMILY

6.1.1 HARD MEMORY VECTORS

All PIC18 devices have a total of three hard-coded

return vectors in their program memory space. The

Reset vector address is the default value to which the

program counter returns on all device Resets; it is

located at 0000h.

PIC18 devices also have two interrupt vector

addresses for the handling of high-priority and low-

priority interrupts. The high-priority interrupt vector is

located at 0008h and the low-priority interrupt vector is

at 0018h. Their locations in relation to the program

memory map are shown in Figure 6-2.

FIGURE 6-2: HARD VECTOR AND

CONFIGURATION WORD

LOCATIONS FOR

PIC18F45J10 FAMILY

DEVICES

6.1.2 FLASH CONFIGURATION WORDS

Because PIC18F45J10 family devices do not have

persistent configuration memory, the top four words of

on-chip program memory are reserved for configuration

information. On Reset, the configuration information is

copied into the Configuration registers.

The Configuration Words are stored in their program

memory location in numerical order, starting with the

lower byte of CONFIG1 at the lowest address and end-

ing with the upper byte of CONFIG4. For these devices,

only Configuration Words, CONFIG1 through

CONFIG3, are used; CONFIG4 is reserved. The actual

addresses of the Flash Configuration Word for devices

in the PIC18F45J10 family are shown in Table 6-1.

Their location in the memory map is shown with the

other memory vectors in Figure 6-2.

Additional details on the device Configuration Words

are provided in Secti on 21.1 “Configuration Bits”.

TABLE 6-1: FLASH CONFIGURATION

WORD FOR PIC18F45J10

FAMILY DEVICES

Reset Vector

Low-Priority Interrupt Vector

0000h

0018h

On-Chip

Program Memory

High-Priority Interrupt Vector 0008h

1FFFFFh

(Top of Memory)

(Top of Memory-7)

Flash Configuration Words

Read ‘0’

Legend: (Top of Memory) represents upper boundary

of on-chip program memory space (see

Figure 6-1 for device-specific values).

Shaded area represents unimplemented

memory. Areas are not shown to scale.

Device Program

Memory

(Kbytes)

Configuration

Word

Addresses

PIC18F24J10 16 3FF8h to 3FFFh

PIC18F44J10

PIC18F25J10 32 7FF8h to 7FFFh

PIC18F45J10

PIC18F45J10 FAMILY

6.1.3 PROGRAM COUNTER

The Program Counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21 bits wide

and is contained in three separate 8-bit registers. The

low byte, known as the PCL register, is both readable

and writable. The high byte, or PCH register, contains

the PC<15:8> bits; it is not directly readable or writable.

Updates to the PCH register are performed through the

PCLATH register. The upper byte is called PCU. This

directly readable or writable. Updates to the PCU

The contents of PCLATH and PCLATU are transferred

to the program counter by any operation that writes

PCL. Similarly, the upper two bytes of the program

counter are transferred to PCLATH and PCLATU by an

operation that reads PCL. This is useful for computed

offsets to the PC (see Section 6.1.6.1 “Computed

GOTO”).

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the Least Significant bit of PCL is fixed to

a value of ‘0’. The PC increments by 2 to address

sequential instructions in the program memory.

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

6.1.4 RETURN ADDRESS STACK

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC is

pushed onto the stack when a CALL or RCALL instruc-

tion is executed or an interrupt is Acknowledged. The

PC value is pulled off the stack on a RETURN, RETLW

or RETFIE instruction. PCLATU and PCLATH are not

affected by any of the RETURN or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a

5-bit Stack Pointer, STKPTR. The stack space is not

part of either program or data space. The Stack Pointer

is readable and writable and the address on the top of

the stack is readable and writable through the top-of-

stack Special Function Registers. Data can also be

pushed to, or popped from the stack, using these

registers.

A CALL type instruction causes a push onto the stack;

the Stack Pointer is first incremented and the location

pointed to by the Stack Pointer is written with the

contents of the PC (already pointing to the instruction

following the CALL). A RETURN type instruction causes

a pop from the stack; the contents of the location

pointed to by the STKPTR are transferred to the PC

and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all

Resets. There is no RAM associated with the location

corresponding to a Stack Pointer value of ‘00000’; this

is only a Reset value. Status bits indicate if the stack is

full or has overflowed or has underflowed.

6.1.4.1 Top-of-Stack Access

Only the top of the return address stack (TOS) is

readable and writable. A set of three registers,

TOSU:TOSH:TOSL, hold the contents of the stack loca-

tion pointed to by the STKPTR register (Figure 6-3). This

allows users to implement a software stack if necessary.

After a CALL, RCALL or interrupt, the software can read

the pushed value by reading the TOSU:TOSH:TOSL

registers. These values can be placed on a user-defined

software stack. At return time, the software can return

these values to TOSU:TOSH:TOSL and do a return.

The user must disable the global interrupt enable bits

while accessing the stack to prevent inadvertent stack

corruption.

FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

00011

001A34h

11111

11110

11101

00010

00001

00000

00010

Return Address Stack<20:0>

To p - o f - St a c k

000D58h

TOSLTOSHTOSU

34h1Ah00h

STKPTR<4:0>

Top-of-Stack Regis ters S tack Pointer

PIC18F45J10 FAMILY

6.1.4.2 Return Stack Pointer (STKPTR)

The STKPTR register (Register 6-1) contains the Stack

Pointer value, the STKFUL (Stack Overflow) status bit

and the STKUNF (Stack Underflow) status bits. The

value of the Stack Pointer can be 0 through 31. The

Stack Pointer increments before values are pushed

onto the stack and decrements after values are popped

off the stack. On Reset, the Stack Pointer value will be

zero. The user may read and write the Stack Pointer

value. This feature can be used by a Real-Time

Operating System (RTOS) for return stack

maintenance.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit is cleared by software or by a

POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack Over-

flow Reset Enable) Configuration bit. (Refer to

Section 21.1 “Configura tion Bits” for a description of

the device Configuration bits.) If STVREN is set

(default), the 31st push will push the (PC + 2) value

onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the Stack

Pointer will be set to zero.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the Stack Pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and the STKPTR will remain at 31.

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and sets the STKUNF bit, while the Stack

Pointer remains at zero. The STKUNF bit will remain

set until cleared by software or until a POR occurs.

6.1.4.3 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the

ability to push values onto the stack and pull values off

the stack without disturbing normal program execution

is a desirable feature. The PIC18 instruction set

includes two instructions, PUSH and POP, that permit

the TOS to be manipulated under software control.

TOSU, TOSH and TOSL can be modified to place data

or a return address on the stack.

The PUSH instruction places the current PC value onto

the stack. This increments the Stack Pointer and loads

the current PC value onto the stack.

The POP instruction discards the current TOS by decre-

menting the Stack Pointer. The previous value pushed

onto the stack then becomes the TOS value.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken. This is

not the same as a Reset, as the contents

of the SFRs are not affected.

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 STKFUL: Stack Full Flag bit(1)

1 = Stack became full or overflowed

0 = Stack has not become full or overflowed

bit 6 STKUNF: Stack Underflow Flag bit(1)

1 = Stack underflow occurred

0 = Stack underflow did not occur

bit 5 Unimplemented: Read as ‘0’

bit 4-0 SP<4:0>: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

PIC18F45J10 FAMILY

6.1.4.4 Stack Full and Underflow Resets

Device Resets on stack overflow and stack underflow

conditions are enabled by setting the STVREN bit in

Configuration Register 4L. When STVREN is set, a full

or underflow will set the appropriate STKFUL or

STKUNF bit and then cause a device Reset. When

STVREN is cleared, a full or underflow condition will set

the appropriate STKFUL or STKUNF bit but not cause

a device Reset. The STKFUL or STKUNF bits are

cleared by the user software or a Power-on Reset.

6.1.5 FAST REGISTER STACK

A Fast Register Stack is provided for the STATUS,

WREG and BSR registers, to provide a “fast return”

option for interrupts. The stack for each register is only

one level deep and is neither readable nor writable. It is

loaded with the current value of the corresponding

interrupt sources will push values into the stack regis-

ters. The values in the registers are then loaded back

into their associated registers if the RETFIE, FAST

instruction is used to return from the interrupt.

If both low and high-priority interrupts are enabled, the

stack registers cannot be used reliably to return from

low-priority interrupts. If a high-priority interrupt occurs

while servicing a low-priority interrupt, the stack regis-

ter values stored by the low-priority interrupt will be

overwritten. In these cases, users must save the key

registers in software during a low-priority interrupt.

If interrupt priority is not used, all interrupts may use the

Fast Register Stack for returns from interrupt. If no

interrupts are used, the Fast Register Stack can be

used to restore the STATUS, WREG and BSR registers

at the end of a subroutine call. To use the Fast Register

Stack for a subroutine call, a CALL label,FAST

instruction must be executed to save the STATUS,

WREG and BSR registers to the Fast Register Stack. A

RETURN,FAST instruction is then executed to restore

these registers from the Fast Register Stack.

Example 6-1 shows a source code example that uses

the Fast Register Stack during a subroutine call and

return.

EXAMPLE 6-1: FAST REGISTER STACK

CODE EXAMPLE

6.1.6 LOOK-UP TABLES IN PROGRAM

MEMORY

There may be programming situations that require the

creation of data structures, or look-up tables, in

program memory. For PIC18 devices, look-up tables

can be implemented in two ways:

• Computed GOTO

• Table Reads

6.1.6.1 Computed GOTO

A computed GOTO is accomplished by adding an offset

to the program counter. An example is shown in

Example 6-2.

A look-up table can be formed with an ADDWF PCL

instruction and a group of RETLW nn instructions. The

W register is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCL instruction. The next

instruction executed will be one of the RETLW nn

instructions that returns the value ‘nn’ to the calling

function.

The offset value (in WREG) specifies the number of

bytes that the program counter should advance and

should be multiples of 2 (LSb = 0).

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

EXAMPLE 6-2: COMPUTED GOTO USING

AN OFFSET VALUE

6.1.6.2 Table Reads and Table Writes

A better method of storing data in program memory

allows two bytes of data to be stored in each instruction

location.

Look-up table data may be stored two bytes per pro-

gram word by using table reads and writes. The Table

Pointer (TBLPTR) register specifies the byte address

and the Table Latch (TABLAT) register contains the

data that is read from or written to program memory.

Data is transferred to or from program memory one

byte at a time.

Table read and table write operations are discussed

further in Section 7.1 “Table Reads and Table

Writes”.

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

•

SUB1 •

•

RETURN, FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

MOVF OFFSET, W

CALL TABLE

ORG nn00h

TABLE ADDWF PCL

RETLW nnh

PIC18F45J10 FAMILY

6.2 PIC18 Instruction Cycle

6.2.1 CLOCKING SCHEME

The microcontroller clock input, whether from an

internal or external source, is internally divided by four

to generate four non-overlapping quadrature clocks

(Q1, Q2, Q3 and Q4). Internally, the program counter is

incremented on every Q1; the instruction is fetched

from the program memory and latched into the instruc-

tion register during Q4. The instruction is decoded and

executed during the following Q1 through Q4. The

clocks and instruction execution flow are shown in

Figure 6-4.

6.2.2 INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles: Q1

through Q4. The instruction fetch and execute are

pipelined in such a manner that a fetch takes one

instruction cycle, while the decode and execute take

another instruction cycle. However, due to the pipe-

lining, each instruction effectively executes in one

cycle. If an instruction causes the program counter to

change (e.g., GOTO), then two cycles are required to

complete the instruction (Example 6-3).

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 6-4: CLOCK/INSTRUCTION CYCLE

EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKO

(RC mode)

PC PC + 2 PC + 4

Fetch INST (PC)

Execute INST (PC – 2)

Fetch INST (PC + 2)

Execute INST (PC)

Fetch INST (PC + 4)

Execute INST (PC + 2)

Internal

Phase

Clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. BRA SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

PIC18F45J10 FAMILY

6.2.3 INSTRUCTIONS IN PROGRAM

MEMORY

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSB = 0). To maintain alignment

with instruction boundaries, the PC increments in steps

of 2 and the LSB will always read ‘0’ (see Section 6.1.3

“Program Counter”).

Figure 6-5 shows an example of how instruction words

are stored in the program memory.

The CALL and GOTO instructions have the absolute pro-

gram memory address embedded into the instruction.

Since instructions are always stored on word boundar-

ies, the data contained in the instruction is a word

address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 6-5 shows how the

instruction, GOTO 0006h, is encoded in the program

memory. Program branch instructions, which encode a

relative address offset, operate in the same manner. The

offset value stored in a branch instruction represents the

number of single-word instructions that the PC will be

offset by. Section 22.0 “Instruction Set Summary”

provides further details of the instruction set.

FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY

6.2.4 TWO-WORD INSTRUCTIONS

The standard PIC18 instruction set has four two-word

instructions: CALL, MOVFF, GOTO and LSFR. In all

cases, the second word of the instructions always has

‘1111’ as its four Most Significant bits; the other 12 bits

are literal data, usually a data memory address.

The use of ‘1111’ in the 4 MSbs of an instruction spec-

ifies a special form of NOP. If the instruction is executed

in proper sequence – immediately after the first word –

the data in the second word is accessed and used by

the instruction sequence. If the first word is skipped for

some reason and the second word is executed by itself,

a NOP is executed instead. This is necessary for cases

when the two-word instruction is preceded by a condi-

tional instruction that changes the PC. Example 6-4

shows how this works.

EXAMPLE 6-4: TWO-WORD INSTRUCTIONS

Word Address

LSB = 1LSB = 0↓

Program Memory

Byte Locations →

000000h

000002h

000004h

000006h

Instruction 1: MOVLW 055h 0Fh 55h 000008h

Instruction 2: GOTO 0006h EFh 03h 00000Ah

F0h 00h 00000Ch

Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh

F4h 56h 000010h

000012h

000014h

Note: See Section 6.6 “PIC18 Instruction

Execution and the Extended Instruc-

tion Set” for information on two-word

instructions in the extended instruction set.

CASE 1:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word

1111 0100 0101 0110 ; Execute this word as a NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110 ; 2nd word of instruction

0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18F45J10 FAMILY

6.3 Data Memory Organization

The data memory in PIC18 devices is implemented as

static RAM. Each register in the data memory has a

12-bit address, allowing up to 4096 bytes of data

memory. The memory space is divided into as many as

16 banks that contain 256 bytes each; PIC18F45J10

family devices implement all 16 banks. Figure 6-6

shows the data memory organization for the

PIC18F45J10 family devices.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratchpad operations in the user’s

application. Any read of an unimplemented location will

read as ‘0’s.

The instruction set and architecture allow operations

across all banks. The entire data memory may be

accessed by Direct, Indirect or Indexed Addressing

modes. Addressing modes are discussed later in this

subsection.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle, PIC18

devices implement an Access Bank. This is a 256-byte

memory space that provides fast access to SFRs and

the lower portion of GPR Bank 0 without using the

BSR. Section 6.3.2 “Access Bank” provides a

detailed description of the Access RAM.

6.3.1 BANK SELECT REGISTER (BSR)

Large areas of data memory require an efficient

addressing scheme to make rapid access to any

address possible. Ideally, this means that an entire

address does not need to be provided for each read or

write operation. For PIC18 devices, this is accom-

plished with a RAM banking scheme. This divides the

memory space into 16 contiguous banks of 256 bytes.

Depending on the instruction, each location can be

addressed directly by its full 12-bit address, or an 8-bit

low-order address and a 4-bit Bank Pointer.

Most instructions in the PIC18 instruction set make use

of the Bank Pointer, known as the Bank Select Register

(BSR). This SFR holds the 4 Most Significant bits of a

location’s address; the instruction itself includes the

8 Least Significant bits. Only the four lower bits of the

BSR are implemented (BSR<3:0>). The upper four bits

are unused; they will always read ‘0’ and cannot be

written to. The BSR can be loaded directly by using the

MOVLB instruction.

The value of the BSR indicates the bank in data

memory. The 8 bits in the instruction show the location

in the bank and can be thought of as an offset from the

bank’s lower boundary. The relationship between the

BSR’s value and the bank division in data memory is

shown in Figure 6-7.

Since up to 16 registers may share the same low-order

address, the user must always be careful to ensure that

the proper bank is selected before performing a data

read or write. For example, writing what should be

program data to an 8-bit address of F9h while the BSR

is 0Fh will end up resetting the program counter.

While any bank can be selected, only those banks that

are actually implemented can be read or written to.

Writes to unimplemented banks are ignored, while

reads from unimplemented banks will return ‘0’s. Even

so, the STATUS register will still be affected as if the

operation was successful. The data memory map in

Figure 6-6 indicates which banks are implemented.

In the core PIC18 instruction set, only the MOVFF

instruction fully specifies the 12-bit address of the

source and target registers. This instruction ignores the

BSR completely when it executes. All other instructions

include only the low-order address as an operand and

must use either the BSR or the Access Bank to locate

their target registers.

Note: The operation of some aspects of data

memory are changed when the PIC18

extended instruction set is enabled. See

Section 6.5 “Data Memory and the

Extended Instruction Set” for more

information.

PIC18F45J10 FAMILY

FIGURE 6-6: DATA MEMORY MAP FOR PIC18F45J10 FAMILY DEVICES

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

080h

07Fh

F80h

FFFh

00h

7Fh

80h

FFh

Access B ank

When ‘a’ = 0:

The BSR is ignored and the

Access Bank is used.

The first 128 bytes are

general purpose RAM

(from Bank 0).

The second 128 bytes are

Special Function Registers

(from Bank 15).

When ‘a’ = 1:

The BSR specifies the Bank

used by the instruction.

F7Fh

F00h

EFFh

1FFh

100h

0FFh

000h

Access RAM

FFh

00h

FFh

00h

FFh

00h

GPR

SFR

Access RAM High

Access RAM Low

Bank 2

= 0110

= 0010

(SFRs)

2FFh

200h

3FFh

300h

4FFh

400h

5FFh

500h

6FFh

600h

7FFh

700h

8FFh

800h

9FFh

900h

AFFh

A00h

BFFh

B00h

CFFh

C00h

DFFh

D00h

E00h

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPR

FFh

00h

= 0011

= 0100

= 0101

= 0111

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

= 1110

Unused

Read 00h

Unused

GPR

PIC18F45J10 FAMILY

FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

6.3.2 ACCESS BANK

While the use of the BSR with an embedded 8-bit

address allows users to address the entire range of

data memory, it also means that the user must always

ensure that the correct bank is selected. Otherwise,

data may be read from or written to the wrong location.

This can be disastrous if a GPR is the intended target

of an operation but an SFR is written to instead.

Verifying and/or changing the BSR for each read or

write to data memory can become very inefficient.

To streamline access for the most commonly used data

memory locations, the data memory is configured with

an Access Bank, which allows users to access a

mapped block of memory without specifying a BSR.

The Access Bank consists of the first 128 bytes of

memory (00h-7Fh) in Bank 0 and the last 128 bytes of

memory (80h-FFh) in Block 15. The lower half is known

as the “Access RAM” and is composed of GPRs. This

upper half is also where the device’s SFRs are

mapped. These two areas are mapped contiguously in

the Access Bank and can be addressed in a linear

fashion by an 8-bit address (Figure 6-6).

The Access Bank is used by core PIC18 instructions

that include the Access RAM bit (the ‘a’ parameter in

the instruction). When ‘a’ is equal to ‘1’, the instruction

uses the BSR and the 8-bit address included in the

opcode for the data memory address. When ‘a’ is ‘0’,

however, the instruction is forced to use the Access

Bank address map; the current value of the BSR is

ignored entirely.

Using this “forced” addressing allows the instruction to

operate on a data address in a single cycle without

updating the BSR first. For 8-bit addresses of 80h and

above, this means that users can evaluate and operate

on SFRs more efficiently. The Access RAM below 80h

is a good place for data values that the user might need

to access rapidly, such as immediate computational

results or common program variables. Access RAM

also allows for faster and more code efficient context

saving and switching of variables.

The mapping of the Access Bank is slightly different

when the extended instruction set is enabled (XINST

Configuration bit = 1). This is discussed in more detail

in Section 6.5.3 “Mapping the Access Bank in

Indexed Literal Offset Mode”.

6.3.3 GENERAL PURPOSE REGISTER

FILE

PIC18 devices may have banked memory in the GPR

area. This is data RAM which is available for use by all

instructions. GPRs start at the bottom of Bank 0

(address 000h) and grow upwards towards the bottom of

the SFR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other Resets.

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data Memory

Bank Select(2)

From Opcode(2)

0000

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

Bank 3

through

Bank 13

0011 11111111

BSR(1)

PIC18F45J10 FAMILY

6.3.4 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implemented as static RAM. SFRs start at the top of

data memory (FFFh) and extend downward to occupy

the top half of Bank 15 (F80h to FFFh). A list of these

registers is given in Table 6-2 and Table 6-3.

The SFRs can be classified into two sets: those

associated with the “core” device functionality (ALU,

Resets and interrupts) and those related to the periph-

eral functions. The Reset and Interrupt registers are

described in their respective chapters, while the ALU’s

STATUS register is described later in this section.

Registers related to the operation of a peripheral feature

are described in the chapter for that peripheral.

The SFRs are typically distributed among the

peripherals whose functions they control. Unused SFR

locations are unimplemented and read as ‘0’s.

TABLE 6-2: SPECIAL FUNCTION REGISTER MAP FOR PIC18F4 5J10 FAMILY DEVICES

Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1

FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1

FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1

FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2)

FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh —(2)

FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —(2)

FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2)

FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2)

FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL(3) F97h —(2)

FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(3) F96h TRISE(3)

FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3)

FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC

FF3h PRODL FD3h OSCCON FB3h —(2) F93h TRISB

FF2h INTCON FD2h —(2) FB2h —(2) F92h TRISA

FF1h INTCON2 FD1h WDTCON FB1h —(2) F91h —(2)

FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2)

FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2)

FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh SSP2BUF

FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3)

FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3)

FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC

FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB

FE9h FSR0L FC9h SSP1BUF FA9h —(2) F89h LATA

FE8h WREG FC8h SSP1ADD FA8h —(2) F88h SSP2ADD(3)

FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2(1) F87h SSP2STAT(3)

FE6h POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h SSP2CON1(3)

FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h SSP2CON2(3)

FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE(3)

FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD(3)

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.

3: This register is not available in 28-pin devices.

PIC18F45J10 FAMILY

TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Details

on page:

TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 47, 53

TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 47, 53

TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 47, 53

STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 47, 54

PCLATU — — — Holding Register for PC<20:16> ---0 0000 47, 53

PCLATH Holding Register for PC<15:8> 0000 0000 47, 53

PCL PC Low Byte (PC<7:0>) 0000 0000 47, 53

TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 47, 74

TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 47, 74

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 47, 74

TABLAT Program Memory Table Latch 0000 0000 47, 74

PRODH Product Register High Byte xxxx xxxx 47, 81

PRODL Product Register Low Byte xxxx xxxx 47, 81

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 47, 85

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 47, 86

INTCON3 INT2IP INT1IP —INT2IEINT1IE— INT2IF INT1IF 11-0 0-00 47, 87

INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 47, 67

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 47, 67

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 47, 67

PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 47, 67

PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –

value of FSR0 offset by W

N/A 47, 67

FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 47, 67

FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 47, 67

WREG Working Register xxxx xxxx 47

INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 47, 67

POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 47, 67

POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 47, 67

PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 47, 67

PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –

value of FSR1 offset by W

N/A 47, 67

FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 47, 67

FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 47, 67

BSR — — — — Bank Select Register ---- 0000 47, 58

INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 48, 67

POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 48, 67

POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 48, 67

PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 48, 67

PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –

value of FSR2 offset by W

N/A 48, 67

FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 48, 67

FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 48, 67

STATUS — — —NOVZDCC---x xxxx 48, 65

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition

Note 1: See Section 5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.

2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

3: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address

Masking” for details.

PIC18F45J10 FAMILY

TMR0H Timer0 Register High Byte 0000 0000 48, 117

TMR0L Timer0 Register Low Byte xxxx xxxx 48, 117

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 48, 115

OSCCON IDLEN — — —OSTS— SCS1 SCS0 0--- q-00 32, 48

WDTCON ———————SWDTEN--- ---0 48, 242

RCON IPEN —CMRI TO PD POR BOR(1) 0-11 11q0 42, 46, 94

TMR1H Timer1 Register High Byte xxxx xxxx 48, 124

TMR1L Timer1 Register Low Byte xxxx xxxx 48, 124

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 48, 119

TMR2 Timer2 Register 0000 0000 48, 126

PR2 Timer2 Period Register 1111 1111 48, 126

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 48, 125

SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 48, 158

SSP1ADD MSSP1 Address Register in I2C™ Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode. 0000 0000 48, 159

SSP1STAT SMP CKE D/A PSR/WUA BF 0000 0000 48, 150,

160

SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 48, 151,

161

SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 48, 162

GCEN ACKSTAT ADMSK5(3) ADMSK4(3) ADMSK3(3) ADMSK2(3) ADMSK1(3) SEN 0000 0000 48, 163

ADRESH A/D Result Register High Byte xxxx xxxx 48, 223

ADRESL A/D Result Register Low Byte xxxx xxxx 48, 223

ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0-00 0000 48, 218

ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 48, 218

ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 48, 218

CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 49, 128

CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 49, 128

CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 49, 128,

CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 49, 128

CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 49, 128

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 49, 128

BAUDCON ABDOVF RCIDL —SCKPBRG16— WUE ABDEN 01-0 0-00 49, 196

ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 0000 0000 49, 144

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 0000 0000 49, 146

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 49, 232

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 49, 226

TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Details

on page:

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition

Note 1: See Section 5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.

2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

3: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address

Masking” for details.

PIC18F45J10 FAMILY

SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 49, 198

SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 49, 198

RCREG EUSART Receive Register 0000 0000 49, 205

TXREG EUSART Transmit Register xxxx xxxx 49, 203

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 49, 196

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 49, 195

EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 49, 72

EECON1 — — — FREE WRERR WREN WR —---0 x00- 49, 74

IPR3 SSP2IP BCL2IP ——————11-- ---- 49, 94

PIR3 SSP2IF BCL2IF ——————00-- ---- 49, 90

PIE3 SSP2IE BCL2IE ——————00-- ---- 49, 92

IPR2 OSCFIP CMIP ——BCL1IP—— CCP2IP 11-- 1--1 49, 93

PIR2 OSCFIF CMIF ——BCL1IF—— CCP2IF 00-- 0--0 49, 89

PIE2 OSCFIE CMIE ——BCL1IE—— CCP2IE 00-- 0--0 49, 91

IPR1 PSPIP(2) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 49, 92

PIR1 PSPIF(2) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 49, 88

PIE1 PSPIE(2) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 49, 91

TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 50, 112

TRISD(2) PORTD Data Direction Control Register 1111 1111 50, 107

TRISC PORTC Data Direction Control Register 1111 1111 50, 104

TRISB PORTB Data Direction Control Register 1111 1111 50, 101

TRISA —— TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 --1- 1111 50, 98

SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 50, 158

LATE(2) — — — — — PORTE Data Latch Register

(Read and Write to Data Latch)

---- -xxx 50, 110

LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 50, 107

LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 50, 104

LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 50, 101

LATA —— PORTA Data Latch Register (Read and Write to Data Latch) --xx xxxx 50, 98

SSP2ADD MSSP2 Address Register in I2C™ Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode. 0000 0000 50, 158

SSP2STAT SMP CKE D/A PSR/WUA BF 0000 0000 50, 150,

160

SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50, 151,

161

SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 50, 164

GCEN ACKSTAT ADMSK5(3) ADMSK4(3) ADMSK3(3) ADMSK2(3) ADMSK1(3) SEN 0000 0000 48, 163

PORTE(2) — — — — —RE2

(2) RE1(2) RE0(2) ---- -xxx 50, 110

PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 50, 107

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 50, 104

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 50, 101

PORTA ——RA5— RA3 RA2 RA1 RA0 --0- 0000 50, 98

TABLE 6-3: REGISTER FILE SUMMARY (PIC18F24J10/25J10/44J10/45J10) (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Details

on page:

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition

Note 1: See Section 5.4 “Brown-out Reset (BOR) (PIC18F2XJ10/4XJ10 Devices Only)”.

2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

3: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 16.4.3.2 “Address

Masking” for details.

PIC18F45J10 FAMILY

6.3.5 STATUS REGISTER

The STATUS register, shown in Register 6-2, contains

the arithmetic status of the ALU. As with any other SFR,

it can be the operand for any instruction.

If the STATUS register is the destination for an instruc-

tion that affects the Z, DC, C, OV or N bits, the results

of the instruction are not written; instead, the STATUS

performed. Therefore, the result of an instruction with

the STATUS register as its destination may be different

than intended. As an example, CLRF STATUS will set

the Z bit and leave the remaining Status bits

unchanged (‘000u u1uu’).

It is recommended that only BCF, BSF, SWAPF, MOVFF

and MOVWF instructions are used to alter the STATUS

C, DC, OV or N bits in the STATUS register.

For other instructions that do not affect Status bits, see

the instruction set summaries in Table 22-2 and

Table 22-3.

Note: The C and DC bits operate as the borrow

and digit borrow bits, respectively, in

subtraction.

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOVZDC

(1) C(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative

(ALU MSB = 1).

1 = Result was negative

0 = Result was positive

bit 3 OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude

which causes the sign bit (bit 7) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow bit(1)

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(2)

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.

2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the

source register.

PIC18F45J10 FAMILY

6.4 Data Addressing Modes

While the program memory can be addressed in only

one way – through the program counter – information

in the data memory space can be addressed in several

ways. For most instructions, the addressing mode is

fixed. Other instructions may use up to three modes,

depending on which operands are used and whether or

not the extended instruction set is enabled.

The addressing modes are:

• Inherent

• Literal

•Direct

•Indirect

An additional addressing mode, Indexed Literal Offset,

is available when the extended instruction set is

enabled (XINST Configuration bit = 1). Its operation is

discussed in greater detail in Section 6.5.1 “Indexed

Addressing with Literal Offset”.

6.4.1 INHERENT AND LITERAL

ADDRESSING

Many PIC18 control instructions do not need any

argument at all; they either perform an operation that

globally affects the device or they operate implicitly on

one register. This addressing mode is known as Inherent

Addressing. Examples include SLEEP, RESET and DAW.

Other instructions work in a similar way but require an

additional explicit argument in the opcode. This is

known as Literal Addressing mode because they

require some literal value as an argument. Examples

include ADDLW and MOVLW, which respectively, add or

move a literal value to the W register. Other examples

include CALL and GOTO, which include a 20-bit

program memory address.

6.4.2 DIRECT ADDRESSING

Direct Addressing specifies all or part of the source

and/or destination address of the operation within the

opcode itself. The options are specified by the

arguments accompanying the instruction.

In the core PIC18 instruction set, bit-oriented and byte-

oriented instructions use some version of Direct

Addressing by default. All of these instructions include

some 8-bit literal address as their Least Significant

Byte. This address specifies either a register address in

one of the banks of data RAM (Sectio n 6.3.3 “Gener al

Purpose Register File”) or a location in the Access

Bank (Section 6.3.2 “Access Bank”) as the data

source for the instruction.

The Access RAM bit ‘a’ determines how the address is

interpreted. When ‘a’ is ‘1’, the contents of the BSR

(Section 6.3.1 “Bank Select Register (BSR)”) are

used with the address to determine the complete 12-bit

address of the register. When ‘a’ is ‘0’, the address is

interpreted as being a register in the Access Bank.

Addressing that uses the Access RAM is sometimes

also known as Direct Forced Addressing mode.

A few instructions, such as MOVFF, include the entire

12-bit address (either source or destination) in their

opcodes. In these cases, the BSR is ignored entirely.

The destination of the operation’s results is determined

by the destination bit ‘d’. When ‘d’ is ‘1’, the results are

stored back in the source register, overwriting its origi-

nal contents. When ‘d’ is ‘0’, the results are stored in

the W register. Instructions without the ‘d’ argument

have a destination that is implicit in the instruction; their

destination is either the target register being operated

on or the W register.

6.4.3 INDIRECT ADDRESSING

Indirect Addressing allows the user to access a location

in data memory without giving a fixed address in the

instruction. This is done by using File Select Registers

(FSRs) as pointers to the locations to be read or written

to. Since the FSRs are themselves located in RAM as

Special Function Registers, they can also be directly

manipulated under program control. This makes FSRs

very useful in implementing data structures, such as

tables and arrays in data memory.

The registers for Indirect Addressing are also

implemented with Indirect File Operands (INDFs) that

permit automatic manipulation of the pointer value with

auto-incrementing, auto-decrementing or offsetting

with another value. This allows for efficient code, using

loops, such as the example of clearing an entire RAM

bank in Example 6-5.

EXAMPLE 6-5: HOW TO CLEAR RAM

(BANK 1) USING

INDIRECT ADDRESSING

Note: The execution of some instructions in the

core PIC18 instruction set are changed

when the PIC18 extended instruction set is

enabled. See Section 6.5 “Data Memory

and the Extended Instruction Set” for

more information.

LFSR FSR0, 100h ;

NEXT CLRF POSTINC0 ; Clear INDF

; register then

; inc pointer

BTFSS FSR0H, 1 ; All done with

; Bank1?

BRA NEXT ; NO, clear next

CONTINUE ; YES, continue

PIC18F45J10 FAMILY

6.4.3.1 FSR Registers and the INDF

Operand

At the core of Indirect Addressing are three sets of reg-

isters: FSR0, FSR1 and FSR2. Each represents a pair

of 8-bit registers, FSRnH and FSRnL. The four upper

bits of the FSRnH register are not used, so each FSR

pair holds a 12-bit value. This represents a value that

can address the entire range of the data memory in a

linear fashion. The FSR register pairs, then, serve as

pointers to data memory locations.

Indirect Addressing is accomplished with a set of

Indirect File Operands, INDF0 through INDF2. These

can be thought of as “virtual” registers; they are

mapped in the SFR space but are not physically imple-

mented. Reading or writing to a particular INDF register

actually accesses its corresponding FSR register pair.

A read from INDF1, for example, reads the data at the

address indicated by FSR1H:FSR1L. Instructions that

use the INDF registers as operands actually use the

contents of their corresponding FSR as a pointer to the

instruction’s target. The INDF operand is just a

convenient way of using the pointer.

Because Indirect Addressing uses a full 12-bit address,

data RAM banking is not necessary. Thus, the current

contents of the BSR and the Access RAM bit have no

effect on determining the target address.

6.4.3.2 FSR Registers and POSTINC,

POSTDEC, PREINC and PLUSW

In addition to the INDF operand, each FSR register pair

also has four additional indirect operands. Like INDF,

these are “virtual” registers that cannot be indirectly

read or written to. Accessing these registers actually

accesses the associated FSR register pair, but also

performs a specific action on it stored value. They are:

• POSTDEC: accesses the FSR value, then

automatically decrements it by 1 afterwards

• POSTINC: accesses the FSR value, then

automatically increments it by 1 afterwards

• PREINC: increments the FSR value by 1, then

uses it in the operation

• PLUSW: adds the signed value of the W register

(range of -127 to 128) to that of the FSR and uses

the new value in the operation.

In this context, accessing an INDF register uses the

value in the FSR registers without changing them. Sim-

ilarly, accessing a PLUSW register gives the FSR value

offset by that in the W register; neither value is actually

changed in the operation. Accessing the other virtual

registers changes the value of the FSR registers.

Operations on the FSRs with POSTDEC, POSTINC

and PREINC affect the entire register pair; that is, roll-

overs of the FSRnL register, from FFh to 00h, carry

over to the FSRnH register. On the other hand, results

of these operations do not change the value of any

flags in the STATUS register (e.g., Z, N, OV, etc.).

FIGURE 6-8: INDIRECT ADDRES SING

FSR1H:FSR1L

Data Memory

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

Bank 3

through

Bank 13

ADDWF, INDF1, 1

Using an instruction with one of the

Indirect Addressing registers as the

operand....

...uses the 12-bit address stored in

the FSR pair associated with that

...to determine the data memory

location to be used in that operation.

In this case, the FSR1 pair contains

ECCh. This means the contents of

location ECCh will be added to that

of the W register and stored back in

ECCh.

xxxx1110 11001100

PIC18F45J10 FAMILY

The PLUSW register can be used to implement a form

of Indexed Addressing in the data memory space. By

manipulating the value in the W register, users can

reach addresses that are fixed offsets from pointer

addresses. In some applications, this can be used to

implement some powerful program control structure,

such as software stacks, inside of data memory.

6.4.3.3 Operations by FSRs on FSRs

Indirect Addressing operations that target other FSRs

or virtual registers represent special cases. For

example, using an FSR to point to one of the virtual

registers will not result in successful operations. As a

specific case, assume that FSR0H:FSR0L contains

FE7h, the address of INDF1. Attempts to read the

value of the INDF1 using INDF0 as an operand will

return 00h. Attempts to write to INDF1 using INDF0 as

the operand will result in a NOP.

On the other hand, using the virtual registers to write to

an FSR pair may not occur as planned. In these cases,

the value will be written to the FSR pair but without any

incrementing or decrementing. Thus, writing to INDF2

or POSTDEC2 will write the same value to the

FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the

SFR space, they can be manipulated through all direct

operations. Users should proceed cautiously when

working on these registers, particularly if their code

uses indirect addressing.

Similarly, operations by Indirect Addressing are gener-

ally permitted on all other SFRs. Users should exercise

the appropriate caution that they do not inadvertently

change settings that might affect the operation of the

device.

6.5 Data Memory and the Extended

Instruction Set

Enabling the PIC18 extended instruction set (XINST

Configuration bit = 1) significantly changes certain

aspects of data memory and its addressing. Specifi-

cally, the use of the Access Bank for many of the core

PIC18 instructions is different; this is due to the

introduction of a new addressing mode for the data

memory space.

What does not change is just as important. The size of

the data memory space is unchanged, as well as its

linear addressing. The SFR map remains the same.

Core PIC18 instructions can still operate in both Direct

and Indirect Addressing mode; inherent and literal

instructions do not change at all. Indirect addressing

with FSR0 and FSR1 also remains unchanged.

6.5.1 INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes

the behavior of Indirect Addressing using the FSR2

conditions, instructions that use the Access Bank – that

is, most bit-oriented and byte-oriented instructions –

can invoke a form of Indexed Addressing using an

offset specified in the instruction. This special address-

ing mode is known as Indexed Addressing with Literal

Offset, or Indexed Literal Offset mode.

When using the extended instruction set, this

addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0) and

• The file address argument is less than or equal to

5Fh.

Under these conditions, the file address of the instruc-

tion is not interpreted as the lower byte of an address

(used with the BSR in direct addressing), or as an 8-bit

address in the Access Bank. Instead, the value is

interpreted as an offset value to an Address Pointer,

specified by FSR2. The offset and the contents of

FSR2 are added to obtain the target address of the

operation.

6.5.2 INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use Direct

Addressing are potentially affected by the Indexed

Literal Offset Addressing mode. This includes all

byte-oriented and bit-oriented instructions, or almost

one-half of the standard PIC18 instruction set.

Instructions that only use Inherent or Literal Addressing

modes are unaffected.

Additionally, byte-oriented and bit-oriented instructions

are not affected if they do not use the Access Bank

(Access RAM bit is ‘1’), or include a file address of 60h

or above. Instructions meeting these criteria will

continue to execute as before. A comparison of the

different possible addressing modes when the

extended instruction set is enabled in shown in

Figure 6-9.

Those who desire to use byte-oriented or bit-oriented

instructions in the Indexed Literal Offset mode should

note the changes to assembler syntax for this mode.

This is described in more detail in Section 22.2.1

“Extended Instruction Syntax”.

PIC18F45J10 FAMILY

FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND

BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

Exampl e Inst ruc tion : ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

When ‘a’ = 0 and f ≥ 60h:

The instruction executes in

Direct Forced mode. ‘f’ is inter-

preted as a location in the

Access RAM between 060h

and 0FFh. This is the same as

locations 060h to 07Fh

(Bank 0) and F80h to FFFh

(Bank 15) of data memory.

Locations below 60h are not

available in this addressing

mode.

When ‘a’ = 0 and f ≤ 5Fh:

The instruction executes in

Indexed Literal Offset mode. ‘f’

is interpreted as an offset to the

address value in FSR2. The

two are added together to

obtain the address of the target

address can be anywhere in

the data memory space.

Note that in this mode, the

correct syntax is now:

ADDWF [k], d

where ‘k’ is the same as ‘f’.

When ‘a’ = 1 (all values of f):

The instruction executes in

Direct mode (also known as

Direct Long mode). ‘f’ is inter-

preted as a location in one of

the 16 banks of the data

memory space. The bank is

designated by the Bank Select

can be in any implemented

bank in the data memory

space.

000h

060h

100h

F00h

F80h

FFFh

Valid Range

00h

60h

80h

FFh

Data Memory

Access RAM

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

000h

080h

100h

F00h

F80h

FFFh Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

FSR2H FSR2L

ffffffff001001da

000h

080h

100h

F00h

F80h

FFFh Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

for ‘f’

BSR

00000000

080h

PIC18F45J10 FAMILY

6.5.3 MAPPING THE ACCESS BANK IN

INDEXED LITERAL OFFSET MODE

The use of Indexed Literal Offset Addressing mode

effectively changes how the first 96 locations of Access

RAM (00h to 5Fh) are mapped. Rather than containing

just the contents of the bottom half of Bank 0, this mode

maps the contents from Bank 0 and a user-defined

“window” that can be located anywhere in the data

memory space. The value of FSR2 establishes the

lower boundary of the addresses mapped into the

window, while the upper boundary is defined by FSR2

plus 95 (5Fh). Addresses in the Access RAM above

5Fh are mapped as previously described (see

Section 6.3.2 “Access Bank”). An example of Access

Bank remapping in this addressing mode is shown in

Figure 6-10.

Remapping of the Access Bank applies only to opera-

tions using the Indexed Literal Offset mode. Operations

that use the BSR (Access RAM bit is ‘1’) will continue

to use Direct Addressing as before.

6.6 PIC18 Instruction Execution and

the Extended Instruction Set

Enabling the extended instruction set adds eight

additional commands to the existing PIC18 instruction

set. These instructions are executed as described in

Section 22.2 “Extended Instruction Set”.

FIGURE 6-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET

ADDRESSING

Data Memory

000h

100h

200h

F80h

F00h

FFFh

Bank 1

Bank 15

Bank 2

through

Bank 14

SFRs

05Fh

ADDWF f, d, a

FSR2H:FSR2L = 120h

Locations in the region

from the FSR2 Pointer

(120h) to the pointer plus

05Fh (17Fh) are mapped

to the bottom of the

Access RAM (000h-05Fh).

Locations in Bank 0 from

060h to 07Fh are mapped,

as usual, to the middle half

of the Access Bank.

Special Function Registers

at F80h through FFFh are

mapped to 80h through

FFh, as usual.

Bank 0 addresses below

5Fh can still be addressed

by using the BSR.

Access Bank

00h

80h

FFh

7Fh

Bank 0

SFRs

Bank 1 “Window”

Bank 0

Window

Example Situation :

07Fh

120h

17Fh

5Fh

Bank 1

PIC18F45J10 FAMILY

7.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and

erasable during normal operation over the entire VDD

range.

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 64 bytes at a time. Program memory is

erased in blocks of 1024 bytes at a time. A Bulk Erase

operation may not be issued from user code.

Writing or erasing program memory will cease

instruction fetches until the operation is complete. The

program memory cannot be accessed during the write

or erase; therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

7.1 Table Reads and Table Writes

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the

data RAM space is 8 bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Table read operations retrieve data from program

memory and place it into the data RAM space.

Figure 7-1 shows the operation of a table read with

program memory and data RAM.

Table write operations store data from the data memory

space into holding registers in program memory. The

procedure to write the contents of the holding registers

into program memory is detailed in Section 7.5 “W riting

to Flash Program Memory”. Figure 7-2 shows the

operation of a table write with program memory and data

RAM.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word aligned. Therefore, a table block can

start and end at any byte address. If a table write is being

used to write executable code into program memory,

program instructions will need to be word-aligned.

FIGURE 7-1: TABLE READ OPERATION

Table Pointer(1)

Table Latch (8-bit)

Program Memory

TBLPTRH TBLPTRL

TABLAT

TBLPTRU

Instruction: TBLRD*

Note 1: Table Pointer register points to a byte in program memory.

Program Memory

(TBLPTR)

PIC18F45J10 FAMILY

FIGURE 7-2: TABLE WRITE OPERATION

7.2 Control Registers

Several control registers are used in conjunction with

the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

7.2.1 EECON1 AND EECON2 REGISTERS

The EECON1 register (Register 7-1) is the control

not a physical register; it is used exclusively in the

memory write and erase sequences. Reading

EECON2 will read all ‘0’s.

The FREE bit, when set, will allow a program memory

erase operation. When FREE is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only writes are enabled.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set in hardware when the WR bit is set and cleared

when the internal programming timer expires and the

write operation is complete.

The WR control bit initiates write operations. The bit

cannot be cleared, only set, in software; it is cleared in

hardware at the completion of the write operation.

Table Pointer(1) Table Latch (8-bit)

TBLPTRH TBLPTRL TABLAT

Program Memory

(TBLPTR)

TBLPTRU

Instruction: TBLWT*

Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by

TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in

Sect ion 7.5 “W riting to Flas h Program Memory ”.

Holding Registers

Program Memory

Note: During normal operation, the WRERR is

read as ‘1’. This can indicate that a write

operation was prematurely terminated by

a Reset, or a write operation was

attempted improperly.

PIC18F45J10 FAMILY

U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 U-0

— — — FREE WRERR WREN WR —

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit S = Settable bit (cannot be cleared in software)

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 FREE: Flash Row Erase Enable bit

1 = Performs an erase operation on the next WR command (cleared by completion of erase operation)

0 = Perform write only

bit 3 WRERR: Flash Program Error Flag bit

1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation, or an improper write attempt)

0 = The write operation completed

bit 2 WREN: Flash Program Write Enable bit

1 = Allows write cycles to Flash program

0 = Inhibits write cycles to Flash program

bit 1 WR: Write Control bit

1 = Initiates a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.)

0 = Write cycle is complete

bit 0 Unimplemented: Read as ‘0’

PIC18F45J10 FAMILY

7.2.2 TABLAT – TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch register is used to

hold 8-bit data during data transfers between program

memory and data RAM.

7.2.3 TBLPTR – TABLE POINTER

The Table Pointer (TBLPTR) register addresses a byte

within the program memory. The TBLPTR is comprised

of three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low-order

21 bits allow the device to address up to 2 Mbytes of

program memory space. The 22nd bit allows access to

the device ID, the user ID and the Configuration bits.

The Table Pointer register, TBLPTR, is used by the

TBLRD and TBLWT instructions. These instructions can

update the TBLPTR in one of four ways based on the

table operation. These operations are shown in

Table 7-1. These operations on the TBLPTR only affect

the low-order 21 bits.

7.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRD is executed, all 22 bits of the TBLPTR

determine which byte is read from program memory

into TABLAT.

When a TBLWT is executed, the six LSbs of the Table

Pointer register (TBLPTR<5:0>) determine which of

the 64 program memory holding registers is written to.

When the timed write to program memory begins (via

the WR bit), the 16 MSbs of the TBLPTR

(TBLPTR<20:6>) determine which program memory

block of 64 bytes is written to. For more detail, see

Section 7.5 “Writing to Flash Program Memory”.

When an erase of program memory is executed, the

7 MSbs of the Table Pointer register (TBLPTR<20:10>)

point to the 1024-byte block that will be erased. The

Least Significant bits (TBLPTR<9:0>) are ignored.

Figure 7-3 describes the relevant boundaries of

TBLPTR based on Flash program memory operations.

TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

Example Operation on Table Pointer

TBLRD*

TBLWT* TBLPTR is not modified

TBLRD*+

TBLWT*+ TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*- TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+* TBLPTR is incremented before the read/write

21 16 15 87 0

Table Write Table Write

Table Read – TBLPTR<21:0>

TBLPTRL

TBLPTRH

TBLPTRU

TBLPTR<5:0>TBLPTR<20:6>

Table Erase

TBLPTR<20:10>

PIC18F45J10 FAMILY

7.3 Reading the Flash Program

Memory

The TBLRD instruction is used to retrieve data from

program memory and places it into data RAM. Table

reads from program memory are performed one byte at

a time.

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next table read operation.

The internal program memory is typically organized by

words. The Least Significant bit of the address selects

between the high and low bytes of the word. Figure 7-4

shows the interface between the internal program

memory and the TABLAT.

FIGURE 7-4: READ S FROM FLASH PROGRAM MEMORY

EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD

(Even Byte Address)

Program Memory

(Odd Byte Address)

TBLRD TABLAT

TBLPTR = xxxxx1

FETCH

Instruction Register

(IR) Read Register

TBLPTR = xxxxx0

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the word

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

READ_WORD TBLRD*+ ; read into TABLAT and increment

MOVF TABLAT, W ; get data

MOVWF WORD_EVEN

TBLRD*+ ; read into TABLAT and increment

MOVF TABLAT, W ; get data

MOVWF WORD_ODD

PIC18F45J10 FAMILY

7.4 Erasing Flash Program Memory

The minimum erase block is 1024 bytes. Only through

the use of an external programmer, or through ICSP

control, can larger blocks of program memory be Bulk

Erased. Word Erase in the Flash array is not supported.

When initiating an erase sequence from the micro-

controller itself, a block of 1024 bytes of program

memory is erased. The Most Significant 7 bits of the

TBLPTR<21:10> point to the block being erased.

TBLPTR<9:0> are ignored.

The EECON1 register commands the erase operation.

The WREN bit must be set to enable write operations.

The FREE bit is set to select an erase operation.

For protection, the write initiate sequence for EECON2

must be used.

A long write is necessary for erasing the internal Flash.

Instruction execution is halted while in a long write

cycle. The long write will be terminated by the internal

programming timer.

7.4.1 FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory location is:

1. Load Table Pointer register with address of the

block being erased.

2. Set the WREN and FREE bits (EECON1<2,4>)

to enable the erase operation.

3. Disable interrupts.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the erase cycle.

7. The CPU will stall for duration of the erase for

TIE (see parameter D133B).

8. Re-enable interrupts.

EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY BLOCK

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

ERASE_ROW BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable Erase operation

BCF INTCON, GIE ; disable interrupts

Required MOVLW 55h

Sequence MOVWF EECON2 ; write 55h

MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

PIC18F45J10 FAMILY

7.5 Writing to Flash Program Memory

The minimum programming block is 32 words or

64 bytes. Word or byte programming is not supported.

Table writes are used internally to load the holding

registers needed to program the Flash memory. There

are 64 holding registers used by the table writes for

programming.

Since the Table Latch (TABLAT) is only a single byte, the

TBLWT instruction may need to be executed 64 times for

each programming operation. All of the table write

operations will essentially be short writes because only

the holding registers are written. At the end of updating

the 64 holding registers, the EECON1 register must be

written to in order to start the programming operation

with a long write.

The long write is necessary for programming the inter-

nal Flash. Instruction execution is halted while in a long

write cycle. The long write will be terminated by the

internal programming timer.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device.

FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY

7.5.1 FLASH PROGRAM MEMORY WRITE

SEQUENCE

The sequence of events for programming an internal

program memory location should be:

1. If the section of program memory to be written to

has been programmed previously, then the

memory will need to be erased before the write

occurs (see Section 7.4.1 “Flash Program

Memory Erase Sequence”).

2. Write the 64 bytes into the holding registers with

auto-increment.

3. Set the EECON1 register for the write operation:

• set WREN to enable byte writes.

4. Disable interrupts.

5. Write 55h to EECON2.

6. Write 0AAh to EECON2.

7. Set the WR bit. This will begin the write cycle.

8. The CPU will stall for duration of the write (about

2 ms using internal timer).

9. Re-enable interrupts.

10. Verify the memory (table read).

An example of the required code is shown in

Example 7-3.

Note: Unlike previous devices, the PIC18F45J10

family of devices does not reset the holding

registers after a write occurs. The holding

registers must be cleared or overwritten

before a programming sequence.

In order to maintain the endurance of the

cells, each Flash byte should not be

programmed more then twice between

erase operations. Either a Bulk or Row

Erase of the target row is required before

attempting to modify the contents a third

time.

TABLAT

TBLPTR = xxxx3FTBLPTR = xxxxx1TBLPTR = xxxxx0

Write Register

TBLPTR = xxxxx2

Program Memory

Holding Register Holding Register Holding Register Holding Register

88 8 8

Note: Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the 64 bytes in

the holding register.

PIC18F45J10 FAMILY

EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

ERASE_BLOCK BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable Erase operation

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

MOVWF EECON2 ; write 55h

MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

MOVLW D'16'

MOVWF WRITE_COUNTER ; Need to write 16 blocks of 64 to write

; one erase block of 1024

RESTART_BUFFER MOVLW D'64'

MOVWF COUNTER

MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

FILL_BUFFER ... ; read the new data from I2C, SPI,

; PSP, USART, etc.

WRITE_BUFFER MOVLW D’64' ; number of bytes in holding register

MOVWF COUNTER

WRITE_BYTE_TO_HREGSMOVFF POSTINC0, WREG ; get low byte of buffer data

MOVWF TABLAT ; present data to table latch

TBLWT+* ; write data, perform a short write

; to internal TBLWT holding register.

DECFSZ COUNTER ; loop until buffers are full

BRA WRITE_BYTE_TO_HREGS

PROGRAM_MEMORY BSF EECON1, WREN ; enable write to memory

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

Required MOVWF EECON2 ; write 55h

Sequence MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start program (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

BCF EECON1, WREN ; disable write to memory

DECFSZ WRITE_COUNTER ; done with one write cycle

BRA RESTART_BUFFER ; if not done replacing the erase block

PIC18F45J10 FAMILY

7.5.2 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

7.5.3 UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. If the write operation is interrupted

by a MCLR Reset or a WDT Time-out Reset during

normal operation, the user can check the WRERR bit

and rewrite the location(s) as needed.

7.5.4 PROTECTION AGAINST

SPURIOUS WRITES

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 21.0 “Special Features of the

CPU” for more detail.

7.6 Flash Program Operation During

Code Protection

See Section 21.6 “Program Verification and Code

Protection” for details on code protection of Flash

program memory.

TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values on

page

TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 47

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 47

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 47

TABLAT Program Memory Table Latch 47

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

EECON2 EEPROM Control Register 2 (not a physical register) 49

EECON1 — — — FREE WRERR WREN WR —49

IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 49

PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 49

PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

8.0 8 x 8 HARDWARE MULTIPLIER

8.1 Introduction

All PIC18 devices include an 8 x 8 hardware multiplier

as part of the ALU. The multiplier performs an unsigned

operation and yields a 16-bit result that is stored in the

product register pair, PRODH:PRODL. The multiplier’s

operation does not affect any flags in the STATUS

Making multiplication a hardware operation allows it to

be completed in a single instruction cycle. This has the

advantages of higher computational throughput and

reduced code size for multiplication algorithms and

allows the PIC18 devices to be used in many applica-

tions previously reserved for digital signal processors.

A comparison of various hardware and software

multiply operations, along with the savings in memory

and execution time, is shown in Table 8-1.

8.2 Operation

Example 8-1 shows the instruction sequence for an 8 x 8

unsigned multiplication. Only one instruction is required

when one of the arguments is already loaded in the

WREG register.

Example 8-2 shows the sequence to do an 8 x 8 signed

multiplication. To account for the sign bits of the

arguments, each argument’s Most Significant bit (MSb)

is tested and the appropriate subtractions are done.

EXAMPLE 8- 1: 8 x 8 UNSIGNE D

MULTIP LY ROU TI N E

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

MOVF ARG1, W ;

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

MOVF ARG1, W

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

BTFSC ARG2, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG1

MOVF ARG2, W

BTFSC ARG1, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

Routine Multiply Method Program

Memory

(Words)

Cycles

(Max)

Time

@ 40 MHz @ 10 MHz @ 4 MHz

8 x 8 unsigned Without hardware multiply 13 69 6.9 μs27.6 μs69 μs

Hardware multiply 1 1 100 ns 400 ns 1 μs

8 x 8 signed Without hardware multiply 33 91 9.1 μs36.4 μs91 μs

Hardware multiply 6 6 600 ns 2.4 μs6 μs

16 x 16 unsigned Without hardware multiply 21 242 24.2 μs96.8 μs242 μs

Hardware multiply 28 28 2.8 μs 11.2 μs28 μs

16 x 16 signed Without hardware multiply 52 254 25.4 μs 102.6 μs254 μs

Hardware multiply 35 40 4.0 μs16.0 μs40 μs

PIC18F45J10 FAMILY

Example 8-3 shows the sequence to do a 16 x 16

unsigned multiplication. Equation 8-1 shows the

algorithm that is used. The 32-bit result is stored in four

registers (RES3:RES0).

EQUATION 8-1: 16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8- 3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

Example 8-4 shows the sequence to do a 16 x 16

signed multiply. Equation 8-2 shows the algorithm

used. The 32-bit result is stored in four registers

(RES3:RES0). To account for the sign bits of the

arguments, the MSb for each argument pair is tested

and the appropriate subtractions are done.

EQUATION 8-2: 16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8-4: 16 x 16 SIGNED

MU LTIPLY ROUTINE

RES3:RES0 = ARG1 H:ARG1L • ARG 2H:ARG2L

= (ARG1H • ARG2H • 216) +

(ARG1H • ARG2L • 28) +

(ARG1L • ARG2H • 28) +

(ARG1L • ARG2L)

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

; MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

; MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

; MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 216) +

(ARG1H • ARG2L • 28) +

(ARG1L • ARG2H • 28) +

(ARG1L • ARG2L) +

(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +

(-1 • ARG1H<7> • ARG2H:ARG2L • 216)

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

; MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

; MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

; MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?

BRA SIGN_ARG1 ; no, check ARG1

MOVF ARG1L, W ;

SUBWF RES2 ;

MOVF ARG1H, W ;

SUBWFB RES3

;

SIGN_ARG1

BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWF RES2 ;

MOVF ARG2H, W ;

SUBWFB RES3

;

CONT_CODE

PIC18F45J10 FAMILY

9.0 INTERRUPTS

Members of the PIC18F45J10 family of devices have

multiple interrupt sources and an interrupt priority

feature that allows most interrupt sources to be

assigned a high-priority level or a low-priority level. The

high-priority interrupt vector is at 0008h and the

low-priority interrupt vector is at 0018h. High-priority

interrupt events will interrupt any low-priority interrupts

that may be in progress.

There are thirteen registers which are used to control

interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2, PIR3

• PIE1, PIE2, PIE3

• IPR1, IPR2, IPR3

It is recommended that the Microchip header files

supplied with MPLAB® IDE be used for the symbolic bit

names in these registers. This allows the

assembler/compiler to automatically take care of the

placement of these bits within the specified register.

In general, interrupt sources have three bits to control

their operation. They are:

•Flag bit to indicate that an interrupt event

occurred

•Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

•Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts

globally. Setting the GIEH bit (INTCON<7>) enables all

interrupts that have the priority bit set (high priority).

Setting the GIEL bit (INTCON<6>) enables all

interrupts that have the priority bit cleared (low priority).

When the interrupt flag, enable bit and appropriate

global interrupt enable bit are set, the interrupt will

vector immediately to address 0008h or 0018h,

depending on the priority bit setting. Individual

interrupts can be disabled through their corresponding

enable bits.

When the IPEN bit is cleared (default state), the

interrupt priority feature is disabled and interrupts are

compatible with PIC® mid-range devices. In

Compatibility mode, the interrupt priority bits for each

source have no effect. INTCON<6> is the PEIE bit

which enables/disables all peripheral interrupt sources.

INTCON<7> is the GIE bit which enables/disables all

interrupt sources. All interrupts branch to address

0008h in Compatibility mode.

When an interrupt is responded to, the global interrupt

enable bit is cleared to disable further interrupts. If the

IPEN bit is cleared, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High-priority interrupt sources can interrupt a

low-priority interrupt. Low-priority interrupts are not

processed while high-priority interrupts are in progress.

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address (0008h

or 0018h). Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bits must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIE bit (GIEH or GIEL

if priority levels are used) which re-enables interrupts.

For external interrupt events, such as the INTx pins or

the PORTB input change interrupt, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set regardless of the

status of their corresponding enable bit or the GIE bit.

Note: Do not use the MOVFF instruction to modify

any of the interrupt control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

PIC18F45J10 FAMILY

FIGURE 9-1: PIC18F24J10/25J10/44J10/45J10 INTERRUPT LOGIC

TMR0IE

GIE/GIEH

PEIE/GIEL

Wake-up if in

Interrupt to CPU

Vector to Location

0008h

INT2IF

INT2IE

INT2IP

INT1IF

INT1IE

INT1IP

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

IPEN

TMR0IF

TMR0IP

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

PEIE/GIEL

Interrupt to CPU

Vector to Location

IPEN

0018h

PIR1<7:0>

PIE1<7:0>

IPR1<7:0>

High-Priority Interrupt Generation

Low-Priority Interrupt Generation

Idle or Sleep modes

GIE/GIEH

PIR2<7:6, 3, 0>

PIE2<7:6, 3, 0>

IPR2<7:6, 3, 0>

PIR3<7:6>

PIE3<7:6>

IPR3<7:6>

PIR1<7:0>

PIE1<7:0>

IPR1<7:0>

PIR2<7:6, 3, 0>

PIE2<7:6, 3, 0>

IPR2<7:6, 3, 0>

PIR3<7:6>

PIE3<7:6>

IPR3<7:6>

IPEN

PIC18F45J10 FAMILY

9.1 INTCON Registers

The INTCON registers are readable and writable

registers which contain various enable, priority and flag

bits.

Note: Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

interrupt enable bit. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

This feature allows for software polling.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked interrupts

0 = Disables all interrupts

When IPEN = 1:

1 = Enables all high-priority interrupts

0 = Disables all interrupts

bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

When IPEN = 1:

1 = Enables all low-priority peripheral interrupts

0 = Disables all low-priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt

0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt

0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software)

0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit(1)

1 = At least one of the RB<7:4> pins changed state (must be cleared in software)

0 = None of the RB<7:4> pins have changed state

Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and

allow the bit to be cleared.

PIC18F45J10 FAMILY

R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1

RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 3 Unimplemented: Read as ‘0’

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

1 =High priority

0 = Low priority

bit 1 Unimplemented: Read as ‘0’

bit 0 RBIP: RB Port Change Interrupt Priority bit

1 =High priority

0 = Low priority

Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding

enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F45J10 FAMILY

R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

INT2IP INT1IP —INT2IE INT1IE —INT2IF INT1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 =High priority

0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 =High priority

0 = Low priority

bit 5 Unimplemented: Read as ‘0’

bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt

0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt

0 = Disables the INT1 external interrupt

bit 2 Unimplemented: Read as ‘0’

bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared in software)

0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software)

0 = The INT1 external interrupt did not occur

Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding

enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F45J10 FAMILY

9.2 PIR Registers

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are three Peripheral Interrupt

Request (Flag) registers (PIR1, PIR2, PIR3).

Note 1: Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE (INTCON<7>).

2: User software should ensure the

appropriate interrupt flag bits are cleared

prior to enabling an interrupt and after

servicing that interrupt.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write has occurred

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete

bit 5 RCIF: EUSART Receive Interrupt Flag bit

1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)

0 = The EUSART receive buffer is empty

bit 4 TXIF: EUSART Transmit Interrupt Flag bit

1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)

0 = The EUSART transmit buffer is full

bit 3 SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 2 CCP1IF: ECCP1/CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

Note 1: This bit is not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

OSCFIF CMIF ——BCLIF—— CCP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0 = Device clock operating

bit 6 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

bit 5-4 Unimplemented: Read as ‘0’

bit 3 BCLIF: Bus Collision Interrupt Flag bit (MSSP1 module)

1 = A bus collision occurred (must be cleared in software)

0 = No bus collision occurred

bit 2-1 Unimplemented: Read as ‘0’

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

SSP2IF BCL2IF — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 6 BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module)

1 = A bus collision occurred (must be cleared in software)

0 = No bus collision occurred

bit 5-0 Unimplemented: Read as ‘0’

PIC18F45J10 FAMILY

9.3 PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Enable registers (PIE1, PIE2, PIE3). When

IPEN = 0, the PEIE bit must be set to enable any of

these peripheral interrupts.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5 RCIE: EUSART Receive Interrupt Enable bit

1 = Enables the EUSART receive interrupt

0 = Disables the EUSART receive interrupt

bit 4 TXIE: EUSART Transmit Interrupt Enable bit

1 = Enables the EUSART transmit interrupt

0 = Disables the EUSART transmit interrupt

bit 3 SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit

1 = Enables the MSSP interrupt

0 = Disables the MSSP interrupt

bit 2 CCP1IE: ECCP1/CCP1 Interrupt Enable bit

1 = Enables the ECCP1/CCP1 interrupt

0 = Disables the ECCP1/CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Note 1: This bit is not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0

OSCFIE CMIE ——BCL1IE—— CCP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 6 CMIE: Comparator Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 5-4 Unimplemented: Read as ‘0’

bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)

1 = Enabled

0 = Disabled

bit 2-1 Unimplemented: Read as ‘0’

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enabled

0 = Disabled

R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

SSP2IE BCL2IE — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)

1 = Enabled

0 = Disabled

bit 5-0 Unimplemented: Read as ‘0’

PIC18F45J10 FAMILY

9.4 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Priority registers (IPR1, IPR2, IPR3). Using

the priority bits requires that the Interrupt Priority

Enable (IPEN) bit be set.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)

1 =High priority

0 = Low priority

bit 6 ADIP: A/D Converter Interrupt Priority bit

1 =High priority

0 = Low priority

bit 5 RCIP: EUSART Receive Interrupt Priority bit

1 =High priority

0 = Low priority

bit 4 TXIP: EUSART Transmit Interrupt Priority bit

1 =High priority

0 = Low priority

bit 3 SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit

1 =High priority

0 = Low priority

bit 2 CCP1IP: ECCP1/CCP1 Interrupt Priority bit

1 =High priority

0 = Low priority

bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1 =High priority

0 = Low priority

bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit

1 =High priority

0 = Low priority

Note 1: This bit is not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

R/W-1 R/W-1 U-0 U-0 R/W-1 U-0 U-0 R/W-0

OSCFIP CMIP ——BCL1IP—— CCP2IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit

1 =High priority

0 = Low priority

bit 6 CMIP: Comparator Interrupt Priority bit

1 =High priority

0 = Low priority

bit 5-4 Unimplemented: Read as ‘0’

bit 3 BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)

1 =High priority

0 = Low priority

bit 2-1 Unimplemented: Read as ‘0’

bit 0 CCP2IP: CCP2 Interrupt Priority bit

1 =High priority

0 = Low priority

R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0

SSP2IP BCL2IP — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit

1 =High priority

0 = Low priority

bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)

1 =High priority

0 = Low priority

bit 5-0 Unimplemented: Read as ‘0’

PIC18F45J10 FAMILY

9.5 RCON Register

The RCON register contains bits used to determine the

cause of the last Reset or wake-up from Idle or Sleep

modes. RCON also contains the bit that enables

interrupt priorities (IPEN).

R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0

IPEN —CMRI TO PD POR BOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 Unimplemented: Read as ‘0’

bit 5 CM: Configuration Mismatch Flag bit

For details of bit operation, see Register 5-1.

bit 4 RI: RESET Instruction Flag bit

For details of bit operation, see Register 5-1.

bit 3 TO: Watchdog Timer Time-out Flag bit

For details of bit operation, see Register 5-1.

bit 2 PD: Power-Down Detection Flag bit

For details of bit operation, see Register 5-1.

bit 1 POR: Power-on Reset Status bit

For details of bit operation, see Register 5-1.

bit 0 BOR: Brown-out Reset Status bit

For details of bit operation, see Register 5-1.

PIC18F45J10 FAMILY

9.6 INTx Pin Interrupts

External interrupts on the RB0/INT0, RB1/INT1 and

RB2/INT2 pins are edge-triggered. If the corresponding

INTEDGx bit in the INTCON2 register is set (= 1), the

interrupt is triggered by a rising edge; if the bit is clear,

the trigger is on the falling edge. When a valid edge

appears on the RBx/INTx pin, the corresponding flag

bit, INTxIF, is set. This interrupt can be disabled by

clearing the corresponding enable bit, INTxIE. Flag bit,

INTxIF, must be cleared in software in the Interrupt

Service Routine before re-enabling the interrupt.

All external interrupts (INT0, INT1 and INT2) can

wake-up the processor from the power-managed

modes if bit INTxIE was set prior to going into the

power-managed modes. If the Global Interrupt Enable

bit, GIE, is set, the processor will branch to the interrupt

vector following wake-up.

Interrupt priority for INT1 and INT2 is determined by the

value contained in the interrupt priority bits, INT1IP

(INTCON3<6>) and INT2IP (INTCON3<7>). There is

no priority bit associated with INT0. It is always a

high-priority interrupt source.

9.7 TMR0 Interrupt

In 8-bit mode (which is the default), an overflow in the

TMR0 register (FFh →00h) will set flag bit, TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L register

pair (FFFFh →0000h) will set TMR0IF. The interrupt

can be enabled/disabled by setting/clearing enable bit,

TMR0IE (INTCON<5>). Interrupt priority for Timer0 is

determined by the value contained in the interrupt prior-

ity bit, TMR0IP (INTCON2<2>). See Section 11.0

“Timer0 Module” for further details on the Timer0

module.

9.8 PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

9.9 Context Saving During Interrupts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the Fast Return Stack. If a fast

return from interrupt is not used (see Section 6.3

“Data Memory Organization”), the user may need to

save the WREG, STATUS and BSR registers on entry

to the Interrupt Service Routine. Depending on the

user’s application, other registers may also need to be

saved. Example 9-1 saves and restores the WREG,

STATUS and BSR registers during an Interrupt Service

Routine.

EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF W_TEMP ; W_TEMP is in virtual bank

MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere

MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere

;

; USER ISR CODE

;

MOVFF BSR_TEMP, BSR ; Restore BSR

MOVF W_TEMP, W ; Restore WREG

MOVFF STATUS_TEMP, STATUS ; Restore STATUS

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

10.0 I/O PORTS

Depending on the device selected and features

enabled, there are up to five ports available. Some pins

of the I/O ports are multiplexed with an alternate

function from the peripheral features on the device. In

general, when a peripheral is enabled, that pin may not

be used as a general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRIS register (Data Direction register)

• PORT register (reads the levels on the pins of the

device)

• LAT register (Data Latch register)

The Data Latch (LAT register) is useful for read-modify-

write operations on the value that the I/O pins are

driving.

A simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 10-1.

FIGURE 10-1: GENERIC I/O PORT

OPERATION

10.1 I/O Port Pin Capabilities

When developing an application, the capabilities of the

port pins must be considered. Outputs on some pins

have higher output drive strength than others. Similarly,

some pins can tolerate higher than VDD input levels.

10.1.1 PIN OUTPUT DRIVE

The output pin drive strengths vary for groups of pins

intended to meet the needs for a variety of applications.

PORTB and PORTC are designed to drive higher

loads, such as LEDs. All other ports are designed for

small loads, typically indication only. Table 10-1 sum-

marizes the output capabilities. Refer to Section 24.0

“Electri cal Characte ristics” for more details.

TABLE 10-1: OUTPUT DRIVE LEVELS

10.1.2 INPUT PINS AND VOLTAGE

CONSIDERATIONS

The voltage tolerance of pins used as device inputs is

dependent on the pin’s input function. Pins that are used

as digital only inputs are able to handle DC voltages up

to 5.5V; a level typical for digital logic circuits. In contrast,

pins that also have analog input functions of any kind

can only tolerate voltages up to VDD. Voltage excursions

beyond VDD on these pins should be avoided. Table 10-

2 summarizes the input capabilities. Refer to

Section 24.0 “Electrical Characteristics” for more

details.

TABLE 10-2: INPUT VOLTAGE LEVELS

Data

Bus

WR LAT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Input

Buffer

I/O pin

RD LAT

or PORT

Port Drive Description

PORTA

Minimum Intended for indication. PORTD

PORTE

PORTB High Suitable for direct LED drive

levels.

PORTC

Port or Pin Tolerated

Input Description

PORTA<5:0>

VDD Only VDD input levels

tolerated.

PORTB<5:0>

PORTC<1:0>

PORTE<2:0>

PORTB<7:6>

5.5V

Tolerates input levels

above VDD, useful for

most standard logic.

PORTC<7:2>

PORTD<7:0>

PIC18F45J10 FAMILY

10.1.3 INTERFACING TO A 5V SYSTEM

Though the VDDMAX of the PIC18F45J10 family is 3.6V,

these devices are still capable of interfacing with 5V

systems, even if the VIH of the target system is above

3.6V. This is accomplished by adding a pull-up resistor

to the port pin (Figure 10-2), clearing the LAT bit for that

pin and manipulating the corresponding TRIS bit

(Figure 10-1) to either allow the line to be pulled high or

to drive the pin low. Only port pins that are tolerant of

voltages up to 5.5V can be used for this type of

interface (refer to Section 10.1.2 “Input Pins and

Volta ge Considerations”).

FIGURE 10-2: +5V SYSTEM HARDWARE

INTERFACE

EXAMPLE 10-1: COMMUNICATING WITH

THE +5V SYSTEM

10.2 PORTA, TRISA and LATA Registers

PORTA is a 5-bit wide, bidirectional port. The corre-

sponding Data Direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORTA pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISA bit (= 0) will

make the corresponding PORTA pin an output (i.e., put

the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the

pins, whereas writing to it, will write to the port latch.

The Data Latch (LATA) register is also memory mapped.

Read-modify-write operations on the LATA register read

and write the latched output value for PORTA.

The other PORTA pins are multiplexed with analog

inputs, the analog VREF+ and VREF- inputs and the com-

parator voltage reference output. The operation of pins

RA<3:0> and RA5 as A/D converter inputs is selected

by clearing or setting the control bits in the ADCON1

Pins RA0 and RA3 may also be used as comparator

inputs and RA5 may be used as the C2 comparator

output by setting the appropriate bits in the CMCON

necessary to turn off the comparators.

All PORTA pins have TTL input levels and full CMOS

output drivers.

The TRISA register controls the direction of the PORTA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

EXAMPLE 10-2: INITIA LI ZING PORTA

RD7

+5V Device

PIC18F45J10 +5V

BCF LATD, 7 ; set up LAT register so

; changing TRIS bit will

; drive line low

BCF TRISD, 7 ; send a 0 to the 5V system

BCF TRISD, 7 ; send a 1 to the 5V system

Note: On a Power-on Reset, RA5 and RA<3:0>

are configured as analog inputs and read

as ‘0’.

CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches

CLRF LATA ; Alternate method

; to clear output

; data latches

MOVLW 07h ; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVWF 07h ; Configure comparators

MOVWF CMCON ; for digital input

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISA ; Set RA<3:0> as inputs

; RA<5:4> as outputs

PIC18F45J10 FAMILY

TABLE 10-3: PORTA I/O SUMMARY

Pin Function TRIS

Setting I/O I/O

Type Description

RA0/AN0 RA0 0O DIG LATA<0> data output; not affected by analog input.

1I TTL PORTA<0> data input; disabled when analog input enabled.

AN0 1I ANA A/D Input Channel 0 and Comparator C1- input. Default input

configuration on POR; does not affect digital output.

RA1/AN1 RA1 0O DIG LATA<1> data output; not affected by analog input.

1I TTL PORTA<1> data input; disabled when analog input enabled.

AN1 1I ANA A/D Input Channel 1 and Comparator C2- input. Default input

configuration on POR; does not affect digital output.

RA2/AN2/

VREF-/CVREF

RA2 0O DIG LATA<2> data output; not affected by analog input. Disabled when

CVREF output enabled.

1I TTL PORTA<2> data input. Disabled when analog functions enabled;

disabled when CVREF output enabled.

AN2 1I ANA A/D Input Channel 2 and Comparator C2+ input. Default input

configuration on POR; not affected by analog output.

VREF-1I ANA A/D and comparator voltage reference low input.

CVREF xO ANA Comparator voltage reference output. Enabling this feature disables

digital I/O.

RA3/AN3/VREF+RA30O DIG LATA<3> data output; not affected by analog input.

1I TTL PORTA<3> data input; disabled when analog input enabled.

AN3 1I ANA A/D Input Channel 3 and Comparator C1+ input. Default input

configuration on POR.

VREF+1I ANA A/D and comparator voltage reference high input.

RA5/AN4/SS1/

C2OUT

RA5 0O DIG LATA<5> data output; not affected by analog input.

1I TTL PORTA<5> data input; disabled when analog input enabled.

AN4 1I ANA A/D Input Channel 4. Default configuration on POR.

SS11I TTL Slave select input for MSSP1 (MSSP1 module).

C2OUT 0O DIG Comparator 2 output; takes priority over port data.

OSC2/CLKO OSC2 xO ANA Main oscillator feedback output connection (HS mode).

CLKO xO DIG System cycle clock output (FOSC/4) in RC and EC Oscillator modes.

OSC1/CLKI OSC1 xI ANA Main oscillator input connection.

CLKI xI ANA Main clock input connection.

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

PIC18F45J10 FAMILY

TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTA ——RA5— RA3 RA2 RA1 RA0 50

LATA —— PORTA Data Latch Register (Read and Write to Data Latch) 50

TRISA —— TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 49

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.

PIC18F45J10 FAMILY

10.3 PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bidirectional port. The corre-

sponding Data Direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISB bit (= 0)

will make the corresponding PORTB pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

PORTB.

EXAMPLE 10- 3: INITIALIZING PORTB

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit, RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

Four of the PORTB pins (RB<7:4>) have an interrupt-

on-change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB<7:4> pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB<7:4>)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB<7:4>

are ORed together to generate the RB Port Change

Interrupt with Flag bit, RBIF (INTCON<0>).

This interrupt can wake the device from Sleep mode or

any of the Idle modes. The user, in the Interrupt Service

Routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB (except with the

MOVFF (ANY), PORTB instruction).

b) Clear flag bit, RBIF.

A mismatch condition will continue to set flag bit, RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit, RBIF, to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

RB3 can be configured by the Configuration bit,

CCP2MX, as the alternate peripheral pin for the CCP2

module (CCP2MX = 0).

The RB5 pin is multiplexed with the Timer0 module

clock input and one of the comparator outputs to

become the RB5/KBI1/T0CKI/C1OUT pin.

Note: On a Power-on Reset, RB<4:0> are

configured as analog inputs by default and

read as ‘0’; RB<7:5> are configured as

digital inputs.

CLRF PORTB ; Initialize PORTB by

; clearing output

; data latches

CLRF LATB ; Alternate method

; to clear output

; data latches

MOVLW 0Fh ; Set RB<4:0> as

MOVWF ADCON1 ; digital I/O pins

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

PIC18F45J10 FAMILY

TABLE 10-5: PORTB I/O SUMMARY

Pin Function TRIS

Setting I/O I/O

Type Description

RB0/INT0/FLT0/

AN12

RB0 0O DIG LATB<0> data output; not affected by analog input.

1I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

INT0 1I ST External Interrupt 0 input.

FLT0 1I ST PWM Fault input (ECCP1/CCP1 module); enabled in

software.

AN12 1I ANA A/D Input Channel 12.(1)

RB1/INT1/AN10 RB1 0O DIG LATB<1> data output; not affected by analog input.

1I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

INT1 1I ST External Interrupt 1 input.

AN10 1I ANA A/D Input Channel 10.(1)

RB2/INT2/AN8 RB2 0O DIG LATB<2> data output; not affected by analog input.

1I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

INT2 1I ST External Interrupt 2 input.

AN8 1I ANA A/D Input Channel 8.(1)

RB3/AN9/CCP2 RB3 0O DIG LATB<3> data output; not affected by analog input.

1I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

AN9 1I ANA A/D Input Channel 9.(1)

CCP2(2) 0O DIG CCP2 compare and PWM output.

1I ST CCP2 capture input

RB4/KBI0/AN11 RB4 0O DIG LATB<4> data output; not affected by analog input.

1I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.(1)

KBI0 1I TTL Interrupt-on-change pin.

AN11 1I ANA A/D Input Channel 11.(1)

RB5/KBI1/T0CKI/

C1OUT

RB5 0O DIG LATB<5> data output.

1I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.

KBI1 1I TTL Interrupt-on-change pin.

T0CKI 1I ST Timer0 clock input.

C1OUT 0O DIG Comparator 1 output; takes priority over port data.

RB6/KBI2/PGC RB6 0O DIG LATB<6> data output.

1I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.

KBI2 1I TTL Interrupt-on-change pin.

PGC xI ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(3)

RB7/KBI3/PGD RB7 0O DIG LATB<7> data output.

1I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.

KBI3 1I TTL Interrupt-on-change pin.

PGD xO DIG Serial execution data output for ICSP and ICD operation.(3)

xI ST Serial execution data input for ICSP and ICD operation.(3)

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: Pins are configured as analog inputs by default.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.

3: All other pin functions are disabled when ICSP™ or ICD are enabled.

PIC18F45J10 FAMILY

TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 50

LATB PORTB Data Latch Register (Read and Write to Data Latch) 50

TRISB PORTB Data Direction Control Register 50

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP47

INTCON3 INT2IP INT1IP —INT2IEINT1IE— INT2IF INT1IF 47

ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.

PIC18F45J10 FAMILY

10.4 PORTC, TRISC and LATC

Registers

PORTC is an 8-bit wide, bidirectional port. The corre-

sponding Data Direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISC bit (= 0)

will make the corresponding PORTC pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATC) is also memory

mapped. Read-modify-write operations on the LATC

PORTC.

PORTC is multiplexed with several peripheral functions

(Table 10-7). The pins have Schmitt Trigger input

buffers. RC1 is normally configured by Configuration

bit, CCP2MX, as the default peripheral pin of the CCP2

module (default/erased state, CCP2MX = 1).

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an output,

while other peripherals override the TRIS bit to make a

pin an input. The user should refer to the corresponding

peripheral section for additional information.

The contents of the TRISC register are affected by

peripheral overrides. Reading TRISC always returns

the current contents, even though a peripheral device

may be overriding one or more of the pins.

EXAMPLE 10-4: INITIALIZING PORTC

Note: On a Power-on Reset, these pins are

configured as digital inputs.

CLRF PORTC ; Initialize PORTC by

; clearing output

; data latches

CLRF LATC ; Alternate method

; to clear output

; data latches

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISC ; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

PIC18F45J10 FAMILY

TABLE 10-7: PORTC I/O SUMMARY

Pin Function TRIS

Setting I/O I/O

Type Description

RC0/T1OSO/

T1CKI

RC0 0O DIG LATC<0> data output.

1I ST PORTC<0> data input.

T1OSO xO ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled.

Disables digital I/O.

T1CKI 1I ST Timer1 counter input.

RC1/T1OSI/CCP2 RC1 0O DIG LATC<1> data output.

1I ST PORTC<1> data input.

T1OSI xI ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.

Disables digital I/O.

CCP2(1) 0O DIG CCP2 compare and PWM output; takes priority over port data.

1I ST CCP2 capture input.

RC2/CCP1/P1A RC2 0O DIG LATC<2> data output.

1I ST PORTC<2> data input.

CCP1 0O DIG ECCP1/CCP1 compare or PWM output; takes priority over port data.

1I ST ECCP1/CCP1 capture input.

P1A(2) 0O DIG ECCP1 Enhanced PWM output, channel A. May be configured for

tri-state during Enhanced PWM shutdown events. Takes priority over

port data.

RC3/SCK1/SCL1 RC3 0O DIG LATC<3> data output.

1I ST PORTC<3> data input.

SCK1 0O DIG SPI clock output (MSSP1 module); takes priority over port data.

1I ST SPI clock input (MSSP1 module).

SCL1 0ODIGI

2C™ clock output (MSSP1 module); takes priority over port data.

1II

2C/SMB I2C clock input (MSSP1 module); input type depends on module setting.

RC4/SDI1/SDA1 RC4 0O DIG LATC<4> data output.

1I ST PORTC<4> data input.

SDI1 1I ST SPI data input (MSSP1 module).

SDA1 1ODIGI

2C data output (MSSP1 module); takes priority over port data.

1II

2C/SMB I2C data input (MSSP1 module); input type depends on module setting.

RC5/SDO1 RC5 0O DIG LATC<5> data output.

1I ST PORTC<5> data input.

SDO1 0O DIG SPI data output (MSSP1 module); takes priority over port data.

RC6/TX/CK RC6 0O DIG LATC<6> data output.

1I ST PORTC<6> data input.

TX 1O DIG Asynchronous serial transmit data output (EUSART module);

takes priority over port data. User must configure as output.

CK 1O DIG Synchronous serial clock output (EUSART module); takes priority

over port data.

1I ST Synchronous serial clock input (EUSART module).

RC7/RX/DT RC7 0O DIG LATC<7> data output.

1I ST PORTC<7> data input.

RX 1I ST Asynchronous serial receive data input (EUSART module).

DT 1O DIG Synchronous serial data output (EUSART module); takes priority over

port data.

1I ST Synchronous serial data input (EUSART module). User must

configure as an input.

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

I2C™/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3.

2: Enhanced PWM output is available only on PIC18F44J10/45J10 devices.

PIC18F45J10 FAMILY

TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 50

LATC PORTC Data Latch Register (Read and Write to Data Latch) 50

TRISC PORTC Data Direction Control Register 50

PIC18F45J10 FAMILY

10.5 PORTD, TRISD and LATD

Registers

PORTD is an 8-bit wide, bidirectional port. The corre-

sponding Data Direction register is TRISD. Setting a

TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISD bit (= 0)

will make the corresponding PORTD pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

PORTD.

All pins on PORTD are implemented with Schmitt Trigger

input buffers. Each pin is individually configurable as an

input or output.

Three of the PORTD pins are multiplexed with outputs

P1B, P1C and P1D of the Enhanced CCP module. The

operation of these additional PWM output pins is

covered in greater detail in Section 15.0 “Enhanced

Capture/Compare/PWM (ECCP) Module”.

PORTD can also be configured as an 8-bit wide micro-

processor port (Parallel Slave Port) by setting control

bit, PSPMODE (TRISE<4>). In this mode, the input

buffers are TTL. See Section 10.7 “Parallel Slave

Port” for additional information on the Parallel Slave

Port (PSP).

EXAMPLE 10-5: INITIALIZING PORTD

Note: PORTD is only available in 40/44-pin

devices.

Note: On a Power-on Reset, these pins are

configured as digital inputs.

Note: When the Enhanced PWM mode is used

with either dual or quad outputs, the PSP

functions of PORTD are automatically

disabled.

CLRF PORTD ; Initialize PORTD by

; clearing output

; data latches

CLRF LATD ; Alternate method

; to clear output

; data latches

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISD ; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

PIC18F45J10 FAMILY

TABLE 10-9: PORTD I/O SUMMARY

Pin Function TRIS

Setting I/O I/O

Type Description

RD0/PSP0/SCK2/

SCL2

RD0 0O DIG LATD<0> data output.

1I ST PORTD<0> data input.

PSP0 xO DIG PSP read data output (LATD<0>); takes priority over port data.

xI TTL PSP write data input.

SCK2 0O DIG SPI clock output (MSSP2 module); takes priority over port data.

1I ST SPI clock input (MSSP2 module).

SCL2 0ODIGI

2C™ clock output (MSSP2 module); takes priority over port data.

1II

2C/SMB I2C clock input (MSSP2 module); input type depends on module setting.

RD1/PSP1/SDI2/

SDA2

RD1 0O DIG LATD<1> data output.

1I ST PORTD<1> data input.

PSP1 xO DIG PSP read data output (LATD<1>); takes priority over port data.

xI TTL PSP write data input.

SDI2 1I ST SPI data input (MSSP2 module).

SDA2 1ODIGI

2C data output (MSSP2 module); takes priority over port data.

1II

2C/SMB I2C data input (MSSP2 module); input type depends on module setting.

RD2/PSP2/SDO2 RD2 0O DIG LATD<2> data output.

1I ST PORTD<2> data input.

PSP2 xO DIG PSP read data output (LATD<2>); takes priority over port data.

xI TTL PSP write data input.

SDO2 0O DIG SPI data output (MSSP2 module); takes priority over port data.

RD3/PSP3/SS2 RD3 0O DIG LATD<3> data output.

1I ST PORTD<3> data input.

PSP3 xO DIG PSP read data output (LATD<3>); takes priority over port data.

xI TTL PSP write data input.

SS2 1I TTL Slave select input for MSSP2 (MSSP2 module).

RD4/PSP4 RD4 0O DIG LATD<4> data output.

1I ST PORTD<4> data input.

PSP4 xO DIG PSP read data output (LATD<4>); takes priority over port data.

xI TTL PSP write data input.

RD5/PSP5/P1B RD5 0O DIG LATD<5> data output.

1I ST PORTD<5> data input.

PSP5 xO DIG PSP read data output (LATD<5>); takes priority over port data.

xI TTL PSP write data input.

P1B 0O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP

data. May be configured for tri-state during Enhanced PWM shutdown events.

RD6/PSP6/P1C RD6 0O DIG LATD<6> data output.

1I ST PORTD<6> data input.

PSP6 xO DIG PSP read data output (LATD<6>); takes priority over port data.

xI TTL PSP write data input.

P1C 0O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP

data. May be configured for tri-state during Enhanced PWM shutdown events.

RD7/PSP7/P1D RD7 0O DIG LATD<7> data output.

1I ST PORTD<7> data input.

PSP7 xO DIG PSP read data output (LATD<7>); takes priority over port data.

xI TTL PSP write data input.

P1D 0O DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP

data. May be configured for tri-state during Enhanced PWM shutdown events.

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C™/SMB = I2C/SMBus input buffer;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

PIC18F45J10 FAMILY

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 50

LATD(1) PORTD Data Latch Register (Read and Write to Data Latch) 50

TRISD(1) PORTD Data Direction Control Register 50

TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 50

CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.

Note 1: These registers and/or bits are not available in 28-pin devices.

PIC18F45J10 FAMILY

10.6 PORTE, TRISE and LATE

Registers

Depending on the particular PIC18F45J10 family

device selected, PORTE is implemented in two

different ways.

For 40/44-pin devices, PORTE is a 4-bit wide port.

Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/

AN7) are individually configurable as inputs or outputs.

These pins have Schmitt Trigger input buffers. When

selected as analog inputs, these pins will read as ‘0’s.

The corresponding Data Direction register is TRISE.

Setting a TRISE bit (= 1) will make the corresponding

PORTE pin an input (i.e., put the corresponding output

driver in a high-impedance mode). Clearing a TRISE bit

(= 0) will make the corresponding PORTE pin an output

(i.e., put the contents of the output latch on the selected

pin).

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

The upper four bits of the TRISE register also control

the operation of the Parallel Slave Port. Their operation

is explained in Register 10-1.

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

PORTE.

EXAMPLE 10-6: INITIALIZING PORTE

Note: PORTE is only available in 40/44-pin

devices.

Note: On a Power-on Reset, RE<2:0> are

configured as analog inputs.

CLRF PORTE ; Initialize PORTE by

; clearing output

; data latches

CLRF LATE ; Alternate method

; to clear output

; data latches

MOVLW 0Ah ; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVLW 03h ; Value used to

; initialize data

; direction

MOVWF TRISE ; Set RE<0> as inputs

; RE<1> as outputs

; RE<2> as inputs

PIC18F45J10 FAMILY

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1

IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IBF: Input Buffer Full Status bit

1 = A word has been received and is waiting to be read by the CPU

0 = No word has been received

bit 6 OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word

0 = The output buffer has been read

bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in software)

0 = No overflow occurred

bit 4 PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel Slave Port mode

0 = General Purpose I/O mode

bit 3 Unimplemented: Read as ‘0’

bit 2 TRISE2: RE2 Direction Control bit

1 = Input

0 = Output

bit 1 TRISE1: RE1 Direction Control bit

1 = Input

0 = Output

bit 0 TRISE0: RE0 Direction Control bit

1 = Input

0 = Output

PIC18F45J10 FAMILY

TABLE 10-11: PORTE I/O SUMMARY

TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Pin Function TRIS

Setting I/O I/O

Type Description

RE0/RD/AN5 RE0 0O DIG LATE<0> data output; not affected by analog input.

1I ST PORTE<0> data input; disabled when analog input enabled.

RD 1I TTL PSP read enable input (PSP enabled).

AN5 1I ANA A/D Input Channel 5; default input configuration on POR.

RE1/WR/AN6 RE1 0O DIG LATE<1> data output; not affected by analog input.

1I ST PORTE<1> data input; disabled when analog input enabled.

WR 1I TTL PSP write enable input (PSP enabled).

AN6 1I ANA A/D Input Channel 6; default input configuration on POR.

RE2/CS/AN7 RE2 0O DIG LATE<2> data output; not affected by analog input.

1I ST PORTE<2> data input; disabled when analog input enabled.

CS 1I TTL PSP write enable input (PSP enabled).

AN7 1I ANA A/D Input Channel 7; default input configuration on POR.

Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTE(1) — — — — — RE2 RE1 RE0 50

LATE(1) — — — — — PORTE Data Latch Register

(Read and Write to Data Latch)

TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 50

ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.

Note 1: These registers are not available in 28-pin devices.

PIC18F45J10 FAMILY

10.7 Parallel Slave Port

In addition to its function as a general I/O port, PORTD

can also operate as an 8-bit wide Parallel Slave Port

(PSP) or microprocessor port. PSP operation is

controlled by the 4 upper bits of the TRISE register

(Register 10-1). Setting control bit, PSPMODE

(TRISE<4>), enables PSP operation as long as the

Enhanced CCP module is not operating in Dual Output

or Quad Output PWM mode. In Slave mode, the port is

asynchronously readable and writable by the external

world.

The PSP can directly interface to an 8-bit micro-

processor data bus. The external microprocessor can

read or write the PORTD latch as an 8-bit latch. Setting

the control bit, PSPMODE, enables the PORTE I/O

pins to become control inputs for the microprocessor

port. When set, port pin RE0 is the RD input, RE1 is the

WR input and RE2 is the CS (Chip Select) input. For

this functionality, the corresponding data direction bits

of the TRISE register (TRISE<2:0>) must be config-

ured as inputs (set). The A/D port configuration bits,

PFCG<3:0> (ADCON1<3:0>), must also be set to a

value in the range of ‘1010’ through ‘1111’.

A write to the PSP occurs when both the CS and WR

lines are first detected low and ends when either are

detected high. The PSPIF and IBF flag bits are both set

when the write ends.

A read from the PSP occurs when both the CS and RD

lines are first detected low. The data in PORTD is read

out and the OBF bit is clear. If the user writes new data

to PORTD to set OBF, the data is immediately read out;

however, the OBF bit is not set.

When either the CS or RD lines are detected high, the

PORTD pins return to the input state and the PSPIF bit

is set. User applications should wait for PSPIF to be set

before servicing the PSP; when this happens, the IBF

and OBF bits can be polled and the appropriate action

taken.

The timing for the control signals in Write and Read

modes is shown in Figure 10-4 and Figure 10-5,

respectively.

FIGURE 10-3: PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE PORT)

Note: The Parallel Slave Port is only available in

40/44-pin devices.

Data Bus

WR LATD RDx pin

RD PORTD

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1<7>)

Read

Chip Select

Write

TTL

WR PORTD

RD LATD

Data Latch

Note: I/O pins have diode protection to VDD and VSS.

PORTE Pins

PIC18F45J10 FAMILY

FIGURE 10-4: PARALLEL SLAVE PORT WRITE WAVEFORMS

FIGURE 10-5: PARALLEL SLAVE PORT READ WAVEFORMS

TABLE 10-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 50

LATD(1) PORTD Data Latch Register (Read and Write to Data Latch) 50

TRISD(1) PORTD Data Direction Control Register 50

PORTE(1) — — — — — RE2 RE1 RE0 50

LATE(1) — — — — — PORTE Data Latch Register

(Read and Write to Data Latch)

TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 50

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.

Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

OBF

PSPIF

PORTD<7:0>

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

PSPIF

OBF

PORTD<7:0>

PIC18F45J10 FAMILY

11.0 T IMER0 MODULE

The Timer0 module incorporates the following features:

• Software selectable operation as a timer or

counter in both 8-bit or 16-bit modes

• Readable and writable registers

• Dedicated 8-bit, software programmable

prescaler

• Selectable clock source (internal or external)

• Edge select for external clock

• Interrupt-on-overflow

The T0CON register (Register 11-1) controls all

aspects of the module’s operation, including the

prescale selection. It is both readable and writable.

A simplified block diagram of the Timer0 module in 8-bit

mode is shown in Figure 11-1. Figure 11-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0

0 = Stops Timer0

bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit

1 = Timer0 is configured as an 8-bit timer/counter

0 = Timer0 is configured as a 16-bit timer/counter

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKO)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Timer0 Prescaler Assignment bit

1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.

0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits

111 = 1:256 Prescale value

110 = 1:128 Prescale value

101 = 1:64 Prescale value

100 = 1:32 Prescale value

011 = 1:16 Prescale value

010 = 1:8 Prescale value

001 = 1:4 Prescale value

000 = 1:2 Prescale value

PIC18F45J10 FAMILY

11.1 Timer0 Operation

Timer0 can operate as either a timer or a counter; the

mode is selected with the T0CS bit (T0CON<5>). In

Timer mode (T0CS = 0), the module increments on

every clock by default unless a different prescaler value

is selected (see Section 11.3 “Prescaler”). If the

TMR0 register is written to, the increment is inhibited

for the following two instruction cycles. The user can

work around this by writing an adjusted value to the

TMR0 register.

The Counter mode is selected by setting the T0CS bit

(= 1). In this mode, Timer0 increments either on every

rising or falling edge of pin RB5/T0CKI. The increment-

ing edge is determined by the Timer0 Source Edge

Select bit, T0SE (T0CON<4>); clearing this bit selects

the rising edge. Restrictions on the external clock input

are discussed below.

An external clock source can be used to drive Timer0;

however, it must meet certain requirements to ensure

that the external clock can be synchronized with the

internal phase clock (T

OSC). There is a delay between

synchronization and the onset of incrementing the

timer/counter.

11.2 Timer0 Reads and Wri tes in

16-Bit Mode

TMR0H is not the actual high byte of Timer0 in 16-bit

mode. It is actually a buffered version of the real high

byte of Timer0 which is not directly readable nor

writable (refer to Figure 11-2). TMR0H is updated with

the contents of the high byte of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

Timer0 without having to verify that the read of the high

and low byte were valid, due to a rollover between

successive reads of the high and low byte.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register. The high

byte is updated with the contents of TMR0H when a

write occurs to TMR0L. This allows all 16 bits of Timer0

to be updated at once.

FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)

FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks

TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS<2:0>

Set

TMR0IF

on Overflow

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI pin

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

Clocks TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS<2:0>

Set

TMR0IF

on Overflow

TMR0

TMR0H

High Byte

Read TMR0L

Write TMR0L

PIC18F45J10 FAMILY

11.3 Prescaler

An 8-bit counter is available as a prescaler for the Timer0

module. The prescaler is not directly readable or writable.

Its value is set by the PSA and T0PS<2:0> bits

(T0CON<3:0>) which determine the prescaler

assignment and prescale ratio.

Clearing the PSA bit assigns the prescaler to the

Timer0 module. When it is assigned, prescale values

from 1:2 through 1:256 in power-of-2 increments are

selectable.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0, MOVWF

TMR0, BSF TMR0, etc.) clear the prescaler count.

11.3.1 SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control and can be changed “on-the-fly” during program

execution.

11.4 Timer0 Int e rr u p t

The TMR0 interrupt is generated when the TMR0

from FFFFh to 0000h in 16-bit mode. This overflow sets

the TMR0IF flag bit. The interrupt can be masked by

clearing the TMR0IE bit (INTCON<5>). Before

re-enabling the interrupt, the TMR0IF bit must be

cleared in software by the Interrupt Service Routine.

Since Timer0 is shut down in Sleep mode, the TMR0

interrupt cannot awaken the processor from Sleep.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler

count but will not change the prescaler

assignment.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on pag e

TMR0L Timer0 Register Low Byte 48

TMR0H Timer0 Register High Byte 48

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 48

TRISA — — TRISA5 —TRISA3 TRISA2 TRISA1 TRISA0 50

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

12.0 T IMER1 MODULE

The Timer1 timer/counter module incorporates these

features:

• Software selectable operation as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR1H

and TMR1L)

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt-on-overflow

• Reset on CCP Special Event Trigger

• Device clock status flag (T1RUN)

A simplified block diagram of the Timer1 module is

shown in Figure 12-1. A block diagram of the module’s

operation in Read/Write mode is shown in Figure 12-2.

The module incorporates its own low-power oscillator

to provide an additional clocking option. The Timer1

oscillator can also be used as a low-power clock source

for the microcontroller in power-managed operation.

Timer1 can also be used to provide Real-Time Clock

(RTC) functionality to applications with only a minimal

addition of external components and code overhead.

Timer1 is controlled through the T1CON Control

Oscillator Enable bit (T1OSCEN). Timer1 can be

enabled or disabled by setting or clearing control bit,

TMR1ON (T1CON<0>).

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 T1RUN T1CKPS1 T1CKPS0

T1OSCEN

T1SYNC TMR1CS TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of TImer1 in one 16-bit operation

0 = Enables register read/write of Timer1 in two 8-bit operations

bit 6 T1RUN: Timer1 System Clock Status bit

1 = Device clock is derived from Timer1 oscillator

0 = Device clock is derived from another source

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: Timer1 Oscillator Enable bit

1 = Timer1 oscillator is enabled

0 = Timer1 oscillator is shut off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 =Stops Timer1

PIC18F45J10 FAMILY

12.1 Timer1 Operation

Timer1 can operate in one of these modes:

•Timer

• Synchronous Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>). When TMR1CS is cleared

(= 0), Timer1 increments on every internal instruction

cycle (FOSC/4). When the bit is set, Timer1 increments

on every rising edge of the Timer1 external clock input

or the Timer1 oscillator, if enabled.

When Timer1 is enabled, the RC1/T1OSI and

RC0/T1OSO/T1CKI pins become inputs. This means

the values of TRISC<1:0> are ignored and the pins are

read as ‘0’.

FIGURE 12-1: TIMER1 BLOCK DIAGRAM

T1SYNC

TMR1CS

T1CKPS<1:0>

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

On/Off

Prescaler

1, 2, 4, 8

Synchronize

Detect

T1OSO/T1CKI

T1OSI

TMR1ON

TMR1L

Set

TMR1IF

on Overflow

TMR1

High Byte

Clear TMR1

(CCP Special Event Trigger)

Timer1 Oscillator

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

On/Off

Timer1

Timer1 Clock Input

PIC18F45J10 FAMILY

FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

12.2 Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit

(T1CON<7>) is set, the address for TMR1H is mapped

to a buffer register for the high byte of Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 High Byte Buffer register. This

provides the user with the ability to accurately read all

16 bits of Timer1 without having to determine whether a

read of the high byte, followed by a read of the low byte,

has become invalid due to a rollover between reads.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. The Timer1 high

byte is updated with the contents of TMR1H when a

write occurs to TMR1L. This allows a user to write all

16 bits to both the high and low bytes of Timer1 at once.

The high byte of Timer1 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer1 High Byte Buffer register.

Writes to TMR1H do not clear the Timer1 prescaler.

The prescaler is only cleared on writes to TMR1L.

12.3 Timer1 Oscillator

An on-chip crystal oscillator circuit is incorporated

between pins T1OSI (input) and T1OSO (amplifier

output). It is enabled by setting the Timer1 Oscillator

Enable bit, T1OSCEN (T1CON<3>). The oscillator is a

low-power circuit rated for 32 kHz crystals. It will continue

to run during all power-managed modes. The circuit for a

typical oscillator is shown in Figure 12-3. Table 12-1

shows the capacitor selection for the Timer1 oscillator.

The user must provide a software time delay to ensure

proper start-up of the Timer1 oscillator.

FIGURE 12-3: EXTERNAL

COMPONENTS FOR THE

TIMER1 OSCILLATOR

T1SYNC

TMR1CS

T1CKPS<1:0>

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronize

Detect

T1OSO/T1CKI

T1OSI

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

TMR1L

Internal Data Bus

Set

TMR1IF

on Overflow

TMR1

TMR1H

High Byte

Read TMR1L

Write TMR1L

TMR1ON

Clear TMR1

(CCP Special Event Trigger)

Timer1 Oscillator

On/Off

Timer1

Timer1 Clock Input

Note: See the Notes with Table 12-1 for additional

information about capacitor selection.

XTAL

PIC18F45J10

T1OSI

T1OSO

32.768 kHz

27 pF

PIC18F45J10 FAMILY

TABLE 12-1: CAPACITOR SELECTION FOR

THE TIMER OSCILLATOR(2,3,4)

12.3.1 USING TIMER1 AS A

CLOCK SOURCE

The Timer1 oscillator is also available as a clock source

in power-managed modes. By setting the clock select

bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device

switches to SEC_RUN mode; both the CPU and

peripherals are clocked from the Timer1 oscillator. If the

IDLEN bit (OSCCON<7>) is cleared and a SLEEP

instruction is executed, the device enters SEC_IDLE

mode. Additional details are available in Section 4.0

“Power-M ana ged Modes”.

Whenever the Timer1 oscillator is providing the clock

source, the Timer1 system clock status flag, T1RUN

(T1CON<6>), is set. This can be used to determine the

controller’s current clocking mode. It can also indicate

the clock source being currently used by the Fail-Safe

Clock Monitor. If the Clock Monitor is enabled and the

Timer1 oscillator fails while providing the clock, polling

the T1RUN bit will indicate whether the clock is being

provided by the Timer1 oscillator or another source.

12.3.2 TIMER1 OSCILLATOR LAYOUT

CONSIDERATIONS

The Timer1 oscillator circuit draws very little power

during operation. Due to the low-power nature of the

oscillator, it may also be sensitive to rapidly changing

signals in close proximity.

The oscillator circuit, shown in Figure 12-3, should be

located as close as possible to the microcontroller.

There should be no circuits passing within the oscillator

circuit boundaries other than VSS or VDD.

If a high-speed circuit must be located near the oscilla-

tor (such as the CCP1 pin in Output Compare or PWM

mode, or the primary oscillator using the OSC2 pin), a

grounded guard ring around the oscillator circuit, as

shown in Figure 12-4, may be helpful when used on a

single-sided PCB or in addition to a ground plane.

FIGURE 12-4: OSCILLATOR CIRCUIT

WITH GROUNDED

GUARD RING

12.4 Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

Timer1 interrupt, if enabled, is generated on overflow

which is latched in interrupt flag bit, TMR1IF

(PIR1<0>). This interrupt can be enabled or disabled

by setting or clearing the Timer1 Interrupt Enable bit,

TMR1IE (PIE1<0>).

Oscillator

Type Freq. C1 C2

LP 32 kHz 27 pF(1) 27 pF(1)

Note 1: Microchip suggests these values as a

starting point in validating the oscillator

circuit.

2: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

4: Capacitor values are for design guidance

only.

VDD

OSC1

VSS

OSC2

RC0

RC1

RC2

Note: Not drawn to scale.

PIC18F45J10 FAMILY

12.5 Resetting Ti mer1 Using the

ECCP/CCP Special Event Trigger

If ECCP1/CCP1 or CCP2 is configured to generate

a Special Event Trigger in Compare mode

(CCPxM<3:0> = 1011), this signal will reset Timer1.

The trigger from CCP2 will also start an A/D conversion

if the A/D module is enabled (see Section 15.2.1

“Special Event Trigger” for more information).

The module must be configured as either a timer or a

synchronous counter to take advantage of this feature.

When used this way, the CCPRH:CCPRL register pair

effectively becomes a period register for Timer1.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

Special Event Trigger, the write operation will take

precedence.

12.6 Using T imer1 as a Real-Time Clock

Adding an external LP oscillator to Timer1 (such as the

one described in Section 12.3 “Timer1 Oscillator”

above) gives users the option to include RTC function-

ality to their applications. This is accomplished with an

inexpensive watch crystal to provide an accurate time

base and several lines of application code to calculate

the time. When operating in Sleep mode and using a

battery or supercapacitor as a power source, it can

completely eliminate the need for a separate RTC

device and battery backup.

The application code routine, RTCisr, shown in

Example 12-1, demonstrates a simple method to

increment a counter at one-second intervals using an

Interrupt Service Routine. Incrementing the TMR1

the routine which increments the seconds counter by

one. Additional counters for minutes and hours are

incremented as the previous counter overflows.

Since the register pair is 16 bits wide, counting up to

overflow the register directly from a 32.768 kHz clock

would take 2 seconds. To force the overflow at the

required one-second intervals, it is necessary to

preload it. The simplest method is to set the MSb of

TMR1H with a BSF instruction. Note that the TMR1L

introduce cumulative error over many cycles.

For this method to be accurate, Timer1 must operate in

Asynchronous mode and the Timer1 overflow interrupt

must be enabled (PIE1<0> = 1) as shown in the

routine, RTCinit. The Timer1 oscillator must also be

enabled and running at all times.

Note: The Special Event Triggers from the

ECCP1/CCPx module will not set the

TMR1IF interrupt flag bit (PIR1<0>).

PIC18F45J10 FAMILY

EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

RTCinit MOVLW 80h ; Preload TMR1 register pair

MOVWF TMR1H ; for 1 second overflow

CLRF TMR1L

MOVLW b’00001111’ ; Configure for external clock,

MOVWF T1CON ; Asynchronous operation, external oscillator

CLRF secs ; Initialize timekeeping registers

CLRF mins ;

MOVLW .12

MOVWF hours

BSF PIE1, TMR1IE ; Enable Timer1 interrupt

RETURN

RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow

BCF PIR1, TMR1IF ; Clear interrupt flag

INCF secs, F ; Increment seconds

MOVLW .59 ; 60 seconds elapsed?

CPFSGT secs

RETURN ; No, done

CLRF secs ; Clear seconds

INCF mins, F ; Increment minutes

MOVLW .59 ; 60 minutes elapsed?

CPFSGT mins

RETURN ; No, done

CLRF mins ; clear minutes

INCF hours, F ; Increment hours

MOVLW .23 ; 24 hours elapsed?

CPFSGT hours

RETURN ; No, done

CLRF hours ; Reset hours

RETURN ; Done

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

TMR1L Timer1 Register Low Byte 48

TMR1H Timer1 Register High Byte 48

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 48

Legend: Shaded cells are not used by the Timer1 module.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

13.0 T IMER2 MODULE

The Timer2 timer module incorporates the following

features:

• 8-bit Timer and Period registers (TMR2 and PR2,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler

(1:1, 1:4 and 1:16)

• Software programmable postscaler

(1:1 through 1:16)

• Interrupt on TMR2 to PR2 match

• Optional use as the shift clock for the

MSSP module

The module is controlled through the T2CON register

(Register 13-1) which enables or disables the timer and

configures the prescaler and postscaler. Timer2 can be

shut off by clearing control bit, TMR2ON (T2CON<2>),

to minimize power consumption.

A simplified block diagram of the module is shown in

Figure 13-1.

13.1 Timer2 Operation

In normal operation, TMR2 is incremented from 00h on

each clock (FOSC/4). A 4-bit counter/prescaler on the

clock input gives direct input, divide-by-4 and divide-by-16

prescale options; these are selected by the prescaler con-

trol bits, T2CKPS<1:>0 (T2CON<1:0>). The value of

TMR2 is compared to that of the Period register, PR2, on

each clock cycle. When the two values match, the

comparator generates a match signal as the timer output.

This signal also resets the value of TMR2 to 00h on the

next cycle and drives the output counter/postscaler (see

Section 13.2 “Timer2 Interrupt”).

The TMR2 and PR2 registers are both directly readable

and writable. The TMR2 register is cleared on any

device Reset, while the PR2 register initializes at FFh.

Both the prescaler and postscaler counters are cleared

on the following events:

• a write to the TMR2 register

• a write to the T2CON register

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

•

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

PIC18F45J10 FAMILY

13.2 Timer2 Interrupt

Timer2 can also generate an optional device interrupt.

The Timer2 output signal (TMR2 to PR2 match) pro-

vides the input for the 4-bit output counter/postscaler.

This counter generates the TMR2 match interrupt flag

which is latched in TMR2IF (PIR1<1>). The interrupt is

enabled by setting the TMR2 Match Interrupt Enable

bit, TMR2IE (PIE1<1>).

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, T2OUTPS<3:0> (T2CON<6:3>).

13.3 Timer2 Output

The unscaled output of TMR2 is available primarily to

the CCP modules, where it is used as a time base for

operations in PWM mode.

Timer2 can be optionally used as the shift clock source

for the MSSP module operating in SPI mode.

Additional information is provided in Section 16.0

“Master Synchronous Serial Port (MSSP) Module”.

FIGURE 13-1: TIMER2 BLOCK DIAGRAM

TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on pag e

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

TMR2 Timer2 Register 48

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 48

PR2 Timer2 Period Register 48

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

Comparator

TMR2 Output

TMR2

Postscaler

Prescaler PR2

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

T2OUTPS<3:0>

T2CKPS<1:0>

Set TMR2IF

Internal Data Bus

Reset

TMR2/PR2

(to PWM or MSSP)

Match

PIC18F45J10 FAMILY

14.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

PIC18F45J10 family devices all have two CCP

(Capture/Compare/PWM) modules. Each module

contains a 16-bit register which can operate as a 16-bit

Capture register, a 16-bit Compare register or a PWM

Master/Slave Duty Cycle register.

In 28-pin devices, the two standard CCP modules

(CCP1 and CCP2) operate as described in this chapter.

In 40/44-pin devices, CCP1 is implemented as an

Enhanced CCP module (ECCP1) with standard Capture

and Compare modes and Enhanced PWM modes. The

Enhanced CCP implementation is discussed in

Section 15.0 “Enhanced Capture/Compare/PWM

(ECCP) Module”.

The Capture and Compare operations described in this

chapter apply to all standard and Enhanced CCP

modules.

Note: Throughout this section and Section 15.0

“Enhanced Capture/Comp are/PWM (ECCP)

Module”, references to the register and bit

names for CCP modules are referred to gener-

ically by the use of ‘x’ or ‘y’ in place of the

specific module number. Thus, “CCPxCON”

might refer to the control register for CCP1,

CCP2 or ECCP1. “CCPxCON” is used

throughout these sections to refer to the

module control register regardless of whether

the CCP module is a standard or Enhanced

implementation.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DCxB<9:2>)

of the duty cycle are found in CCPRxL.

bit 3-0 CCPxM<3:0>: CCPx Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCPx module)

0001 = Reserved

0010 = Compare mode, toggle output on match (CCPxIF bit is set)

0011 = Reserved

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high

(CCPxIF bit is set)

1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low

(CCPxIF bit is set)

1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set,

CCPx pin reflects I/O state)

1011 = Compare mode: trigger special event, reset timer, start A/D conversion on

CCPx match (CCPxIF bit is set)

11xx =PWM mode

PIC18F45J10 FAMILY

14.1 CCP Module Configuration

Each Capture/Compare/PWM module is associated

with a control register (generically, CCPxCON) and a

data register (CCPRx). The data register, in turn, is

comprised of two 8-bit registers: CCPRxL (low byte)

and CCPRxH (high byte). All registers are both

readable and writable.

14.1.1 CCP MODULES AND TIMER

RESOURCES

The CCP modules utilize Timers 1 or 2, depending on

the mode selected. Timer1 is available to modules in

Capture or Compare modes, while Timer2 is available

for modules in PWM mode.

TABLE 14-1: ECCP/CCP MODE – TIMER

RESOURCE

Both modules may be active at any given time and may

share the same timer resource if they are configured to

operate in the same mode (Capture/Compare or PWM)

at the same time. The interactions between the two

modules are summarized in Figure 14-1 and

Figure 14-2. In Timer1 in Asynchronous Counter mode,

the capture operation will not work.

14.1.2 CCP2 PIN ASSIGNMENT

The pin assignment for CCP2 (Capture input, Compare

and PWM output) can change, based on device config-

uration. The CCP2MX Configuration bit determines

which pin CCP2 is multiplexed to. By default, it is

assigned to RC1 (CCP2MX = 1). If the Configuration bit

is cleared, CCP2 is multiplexed with RB3.

Changing the pin assignment of CCP2 does not auto-

matically change any requirements for configuring the

port pin. Users must always verify that the appropriate

TRIS register is configured correctly for CCP2

operation regardless of where it is located.

TABLE 14-2: INTERACTIONS BETWEEN ECCP1/CCP1 AND CCP2 FOR TIMER RESOURCES

ECCP/CCP Mode Timer Resource

Capture

Compare

PWM

Timer1

Timer2

CCP1 Mode CCP2 Mode Interaction

Capture Capture Each module uses TMR1 as the time base.

Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1. Automatic A/D

conversions on the trigger event can also be done. Operation of ECCP1/CCP1 will be

affected.

Compare Capture ECCP1/CCP1 can be configured for the Special Event Trigger to reset TMR1. Operation

of CCP2 will be affected.

Compare Compare Either module can be configured for the Special Event Trigger to reset TMR1. Automatic

A/D conversions on the CCP2 trigger event can be done.

Capture PWM(1) None

Compare PWM(1) None

PWM(1) Capture None

PWM(1) Compare None

PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).

Note 1: Includes standard and Enhanced PWM operation.

PIC18F45J10 FAMILY

14.2 Capture Mode

In Capture mode, the CCPRxH:CCPRxL register pair

captures the 16-bit value of the TMR1 register when an

event occurs on the corresponding CCPx pin. An event

is defined as one of the following:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge

The event is selected by the mode select bits,

CCPxM<3:0> (CCPxCON<3:0>). When a capture is

made, the interrupt request flag bit, CCPxIF, is set; it

must be cleared in software. If another capture occurs

before the value in register CCPRx is read, the old

captured value is overwritten by the new captured value.

14.2.1 CCP PIN CONFIGURATION

In Capture mode, the appropriate CCPx pin should be

configured as an input by setting the corresponding

TRIS direction bit.

14.2.2 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit clear to avoid false inter-

rupts. The interrupt flag bit, CCPxIF, should also be

cleared following any such change in operating mode.

14.2.3 CCP PRESCALER

There are four prescaler settings in Capture mode; they

are specified as part of the operating mode selected by

the mode select bits (CCPxM<3:0>). Whenever the

CCP module is turned off or Capture mode is disabled,

the prescaler counter is cleared. This means that any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared; therefore, the first capture may be from

a non-zero prescaler. Example 14-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 14-1: CHANGING BETWEE N

CAPTURE PRESCALERS

(CCP2 SHOWN)

FIGURE 14-1: CAPTURE MODE OPERAT ION BLOCK DIAGRAM

Note: If RB3/CCP2 or RC1/CCP2 is configured

as an output, a write to the port can cause

a capture condition.

CLRF CCP2CON ; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF CCP2CON ; Load CCP2CON with

; this value

CCPR1H CCPR1L

TMR1H TMR1L

Set CCP1IF

Q1:Q4

CCP1CON<3:0>

CCP1 pin

Prescaler

÷ 1, 4, 16

and

Edge Detect

CCPR2H CCPR2L

TMR1H TMR1L

Set CCP2IF

CCP2CON<3:0>

CCP2 pin

Prescaler

÷ 1, 4, 16

and

Edge Detect

PIC18F45J10 FAMILY

14.3 Compare Mode

In Compare mode, the 16-bit CCPRx register value is

constantly compared against the TMR1 register value.

When a match occurs, the CCPx pin can be:

• driven high

• driven low

• toggled (high-to-low or low-to-high)

• remain unchanged (that is, reflects the state of the

I/O latch)

The action on the pin is based on the value of the mode

select bits (CCPxM<3:0>). At the same time, the inter-

rupt flag bit, CCPxIF, is set.

14.3.1 CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

14.3.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

14.3.3 SOFTWARE INTERRUPT MODE

When the Generate Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the corresponding CCPx pin is

not affected. Only a CCP interrupt is generated, if

enabled and the CCPxIE bit is set.

14.3.4 SPECIAL EVENT TRIGGER

Both CCP modules are equipped with a Special Event

Trigger. This is an internal hardware signal generated

in Compare mode to trigger actions by other modules.

The Special Event Trigger is enabled by selecting

the Compare Special Event Trigger mode

(CCPxM<3:0> = 1011).

For either CCP module, the Special Event Trigger resets

the Timer register pair for whichever timer resource is

currently assigned as the module’s time base. This

allows the CCPRx registers to serve as a Programmable

Period register for either timer.

The Special Event Trigger for CCP2 can also start an

A/D conversion. In order to do this, the A/D converter

must already be enabled.

FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM

Note: Clearing the CCP2CON register will force

the RB3 or RC1 compare output latch

(depending on device configuration) to the

default low level. This is not the PORTB or

PORTC I/O data latch.

CCPR1H CCPR1L

TMR1H TMR1L

Comparator Q

Output

Logic

Special Event Trigger

Set CCP1IF

CCP1 pin

TRIS

CCP1CON<3:0>

Output Enable

CCPR2H CCPR2L

Comparator

Set CCP2IF

Compare

(Timer1 Reset)

Output

Logic

Special Event Trigger

CCP2 pin

TRIS

CCP2CON<3:0>

Output Enable

(Timer1 Reset, A/D Trigger)

Match

Compare

Match

PIC18F45J10 FAMILY

TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

RCON IPEN —CM RI TO PD POR BOR 46

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

PIR2 OSCFIF CMIF — — BCL1IF —— CCP2IF 49

PIE2 OSCFIE CMIE — — BCL1IE —— CCP2IE 49

IPR2 OSCFIP CMIP — — BCL1IP —— CCP2IP 49

TRISB PORTB Data Direction Control Register 50

TRISC PORTC Data Direction Control Register 50

TMR1L Timer1 Register Low Byte 48

TMR1H Timer1 Register High Byte 48

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 48

CCPR1L Capture/Compare/PWM Register 1 Low Byte 49

CCPR1H Capture/Compare/PWM Register 1 High Byte 49

CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49

CCPR2L Capture/Compare/PWM Register 2 Low Byte 49

CCPR2H Capture/Compare/PWM Register 2 High Byte 49

CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

14.4 PWM Mode

In Pulse-Width Modulation (PWM) mode, the CCPx pin

produces up to a 10-bit resolution PWM output. Since

the CCP2 pin is multiplexed with a PORTB or PORTC

data latch, the appropriate TRIS bit must be cleared to

make the CCP2 pin an output.

Figure 14-3 shows a simplified block diagram of the

CCP module in PWM mode.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 14.4.4

“Setup for PWM Operation”.

FIGURE 14-3: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 14-4) has a time base (period)

and a time that the output stays high (duty cycle).

The frequency of the PWM is the inverse of the

period (1/period).

FIGURE 14-4: PWM OUTPUT

14.4.1 PWM PERIOD

The PWM period is specified by writing to the PR2

following formula:

EQUATION 14-1:

PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

•TMR2 is cleared

• The CCPx pin is set (exception: if PWM duty

cycle = 0%, the CCPx pin will not be set)

• The PWM duty cycle is latched from CCPRxL into

CCPRxH

14.4.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPRxL register and to the CCPxCON<5:4> bits. Up

to 10-bit resolution is available. The CCPRxL contains

the eight MSbs and the CCPxCON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPRxL:CCPxCON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

EQUATION 14-2:

CCPRxL and CCPxCON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPRxH until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPRxH is a read-only register.

Note: Clearing the CCP2CON register will force

the RB3 or RC1 output latch (depending on

device configuration) to the default low

level. This is not the PORTB or PORTC I/O

data latch.

CCPRxL

CCPRxH (Slave)

Comparator

TMR2

PR2

(Note 1)

Duty Cycle Registers CCPxCON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

Note 1: The 8-bit TMR2 value is concatenated with the 2-bit

internal Q clock, or 2 bits of the prescaler, to create the

10-bit time base.

CCPx Output

Corresponding

TRIS bit

Comparator

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

Note: The Timer2 postscalers (see Section 13.0

“Timer2 Module”) are not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •

TOSC • (TMR2 Prescale Value)

PIC18F45J10 FAMILY

The CCPRxH register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

When the CCPRxH and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCPx pin is cleared.

The maximum PWM resolution (bits) for a given PWM

frequency is given by the equation:

EQUATION 14-3:

TABLE 14-4: EXAMPLE PWM FREQUEN CIES AND RESOLUTIONS A T 40 MHz

14.4.3 PWM AUTO-SHUTDOWN

(CCP1 ONLY)

The PWM auto-shutdown features of the Enhanced CCP

module are also available to CCP1 in 28-pin devices. The

operation of this feature is discussed in detail in

Section 15.4.7 “E nhanc ed PWM Auto- Shut dow n”.

Auto-shutdown features are not available for CCP2.

14.4.4 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2

2. Set the PWM duty cycle by writing to the

CCPRxL register and CCPxCON<5:4> bits.

3. Make the CCPx pin an output by clearing the

appropriate TRIS bit.

4. Set the TMR2 prescale value, then enable

Timer2 by writing to T2CON.

5. Configure the CCPx module for PWM operation.

Note: If the PWM duty cycle value is longer than

the PWM period, the CCP2 pin will not be

cleared.

FOSC

FPWM

---------------

⎝⎠

⎛⎞

log

2()log

----------------------------- bit s=

PWM Resolution (max)

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)1641111

PR2 Value FFh FFh FFh 3Fh 1Fh 17h

Maximum Resolution (bits) 10 10 10 8 7 6.58

PIC18F45J10 FAMILY

TABLE 14-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on p ag e

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

RCON IPEN —CM RI TO PD POR BOR 46

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

TRISB PORTB Data Direction Control Register 50

TRISC PORTC Data Direction Control Register 50

TMR2 Timer2 Register 48

PR2 Timer2 Period Register 48

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 48

CCPR1L Capture/Compare/PWM Register 1 Low Byte 49

CCPR1H Capture/Compare/PWM Register 1 High Byte 49

CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49

CCPR2L Capture/Compare/PWM Register 2 Low Byte 49

CCPR2H Capture/Compare/PWM Register 2 High Byte 49

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 49

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 49

ECCP1DEL PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

15.0 ENHANCED CAPTURE/

COMPARE/PWM (ECCP)

MODULE

In PIC18F44J10/45J10 devices, ECCP1 is

implemented as a standard CCP module with

Enhanced PWM capabilities. These include the

provisions for 2 or 4 output channels, user-selectable

polarity, dead-band control and automatic shutdown

and restart. The Enhanced features are discussed in

detail in Section 15.4 “Enhanced PWM Mode”.

Capture, Compare and single output PWM functions of

the ECCP module are the same as described for the

standard CCP module.

The control register for the Enhanced CCP module is

shown in Register 15-1. It differs from the CCP1CON

Most Significant bits are implemented to control PWM

functionality.

Note: The ECCP module is implemented only in

40/44-pin devices.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:

xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins

If CCP1M<3:2> = 11:

00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins

01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive

10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins

11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive

bit 5-4 DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found

in CCPR1L.

bit 3-0 CCP1M<3:0>: CCP1 Module Mode Select bits

0000 = Capture/Compare/PWM off (resets ECCP module)

0001 = Reserved

0010 = Compare mode, toggle output on match

0011 = Capture mode

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)

1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)

1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state

1011 = Compare mode, trigger special event (ECCP resets TMR1, sets CCP1IF bit)

1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low

PIC18F45J10 FAMILY

In addition to the expanded range of modes available

through the CCP1CON register and ECCP1AS

associated with Enhanced PWM operation and

auto-shutdown features. It is:

• ECCP1DEL (PWM Dead-Band Delay)

15.1 ECCP Outputs and Configuration

The Enhanced CCP module may have up to four PWM

outputs, depending on the selected operating mode.

These outputs, designated P1A through P1D, are

multiplexed with I/O pins on PORTC and PORTD. The

outputs that are active depend on the ECCP operating

mode selected. The pin assignments are summarized

in Table 15-1.

To configure the I/O pins as PWM outputs, the proper

PWM mode must be selected by setting the P1M<1:0>

and CCP1M<3:0> bits. The appropriate TRISC and

TRISD direction bits for the port pins must also be set

as outputs.

15.1.1 ECCP MODULES AND TIMER

RESOURCES

Like the standard CCP modules, the ECCP module can

utilize Timers 1 or 2, depending on the mode selected.

Timer1 is available for modules in Capture or Compare

modes, while Timer2 is available for modules in PWM

mode. Interactions between the standard and

Enhanced CCP modules are identical to those

described for standard CCP modules. Additional

details on timer resources are provided in

Section 14.1.1 “CCP Modules and Timer

Resources”.

15.2 Capture and Compare Modes

Except for the operation of the Special Event Trigger

discussed below, the Capture and Compare modes of

the ECCP module are identical in operation to that of

CCP2. These are discussed in detail in Section 14.2

“Capture Mode” and Section 14.3 “Compare

Mode”. No changes are required when moving

between 28-pin and 40/44-pin devices.

15.2.1 SPECIAL EVENT TRIGGER

The Special Event Trigger output of ECCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

15.3 Standard PWM Mode

When configured in Single Output mode, the ECCP

module functions identically to the standard CCP

module in PWM mode, as described in Section 14.4

“PWM Mode”. This is also sometimes referred to as

“Compatible CCP” mode, as in Table 15-1.

TABLE 15-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES

Note: When setting up single output PWM

operations, users are free to use either of

the processes described in Section 14.4.4

“Setup for PWM Operation” or

Section 15.4.9 “Setup for PWM Opera-

tion”. The latter is more generic and will

work for either single or multi-output PWM.

ECCP Mode CCP1CON

Configuration RC2 RD5 RD6 RD7

All 40/44-pin Devices:

Compatible CCP 00xx 11xx CCP1 RD5/PSP5 RD6/PSP6 RD7/PSP7

Dual PWM 10xx 11xx P1A P1B RD6/PSP6 RD7/PSP7

Quad PWM x1xx 11xx P1A P1B P1C P1D

Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.

PIC18F45J10 FAMILY

15.4 Enhanced PWM Mode

The Enhanced PWM mode provides additional PWM

output options for a broader range of control applica-

tions. The module is a backward compatible version of

the standard CCP module and offers up to four outputs,

designated P1A through P1D. Users are also able to

select the polarity of the signal (either active-high or

active-low). The module’s output mode and polarity are

configured by setting the P1M<1:0> and CCP1M<3:0>

bits of the CCP1CON register.

Figure 15-1 shows a simplified block diagram of PWM

operation. All control registers are double-buffered and

are loaded at the beginning of a new PWM cycle (the

period boundary when Timer2 resets) in order to

prevent glitches on any of the outputs. The exception is

the PWM Dead-Band Delay register, ECCP1DEL,

which is loaded at either the duty cycle boundary or the

period boundary (whichever comes first). Because of

the buffering, the module waits until the assigned timer

resets instead of starting immediately. This means that

Enhanced PWM waveforms do not exactly match the

standard PWM waveforms, but are instead offset by

one full instruction cycle (4 TOSC).

As before, the user must manually configure the

appropriate TRIS bits for output.

15.4.1 PWM PERIOD

The PWM period is specified by writing to the PR2

following equation.

EQUATION 15-1:

PWM frequency is defined as 1/[PWM period]. When

TMR2 is equal to PR2, the following three events occur

on the next increment cycle:

•TMR2 is cleared

• The CCP1 pin is set (if PWM duty cycle = 0%, the

CCP1 pin will not be set)

• The PWM duty cycle is copied from CCPR1L into

CCPR1H

FIGURE 15-1: SIMP LIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE

Note: The Timer2 postscaler (see Section 13.0

“Timer2 Module”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers CCP1CON<5:4>

Clear Timer,

set CCP1 pin and

latch D.C.

Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit

time base.

TRISx<x>

CCP1/P1A

TRISx<x>

P1B

TRISx<x>

P1D

Output

Controller

P1M1<1:0>

CCP1M<3:0>

ECCP1DEL

CCP1/P1A

P1B

P1C

P1D

P1C

PIC18F45J10 FAMILY

15.4.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L register

contains the eight MSbs and the CCP1CON<5:4>

contains the two LSbs. This 10-bit value is represented

by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is

calculated by the following equation:

EQUATION 15-2:

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not copied into

CCPR1H until a match between PR2 and TMR2 occurs

(i.e., the period is complete). In PWM mode, CCPR1H

is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM opera-

tion. When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or two bits

of the TMR2 prescaler, the CCP1 pin is cleared. The

maximum PWM resolution (bits) for a given PWM

frequency is given by the following equation:

EQUATION 15-3:

15.4.3 PWM OUTPUT CONFIGURATIONS

The P1M<1:0> bits in the CCP1CON register allow one

of four configurations:

• Single Output

• Half-Bridge Output

• Full-Bridge Output, Forward mode

• Full-Bridge Output, Reverse mode

The Single Output mode is the standard PWM mode

discussed in Section 15.4 “Enhanced PWM Mode”.

The Half-Bridge and Full-Bridge Output modes are

covered in detail in the sections that follow.

The general relationship of the outputs in all

configurations is summarized in Figure 15-2.

TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 Prescale Value)

()

PWM Resolution (max) =

FOSC

FPWM

log

log(2) bits

Note: If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)1641111

PR2 Value FFh FFh FFh 3Fh 1Fh 17h

Maximum Resolution (bits) 10 10 10 8 7 6.58

PIC18F45J10 FAMILY

FIGURE 15-2: PW M OUTPUT RELATIONSHI PS (ACTIVE-HIGH STATE)

FIGURE 15-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

Period

SIGNAL PR2 + 1

CCP1CON

<7:6>

P1A Modulated

P1B Modulated

P1A Active

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

P1D Inactive

Duty

Cycle

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay(1) Delay(1)

Period

SIGNAL PR2 + 1

CCP1CON

<7:6>

P1A Modulated

P1B Modulated

P1A Active

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

P1D Inactive

Duty

Cycle

(Single Output)

(Half-Bridge)

(Full-Bridge,

Forward)

(Full-Bridge,

Reverse)

Delay(1) Delay(1)

Relationships:

• Period = 4 * T

OSC * (PR2 + 1) * (TMR2 Prescale Value)

• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

• Delay = 4 * TOSC * (ECCP1DEL<6:0>)

Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 15.4.6 “Programmable

Dead-Band Delay”).

PIC18F45J10 FAMILY

15.4.4 HALF-BRIDGE MODE

In the Half-Bridge Output mode, two pins are used as

outputs to drive push-pull loads. The PWM output signal

is output on the P1A pin, while the complementary PWM

output signal is output on the P1B pin (Figure 15-4). This

mode can be used for half-bridge applications, as shown

in Figure 15-5, or for full-bridge applications where four

power switches are being modulated with two PWM

signals.

In Half-Bridge Output mode, the programmable dead-

band delay can be used to prevent shoot-through

current in half-bridge power devices. The value of bits,

PDC<6:0>, sets the number of instruction cycles before

the output is driven active. If the value is greater than

the duty cycle, the corresponding output remains

inactive during the entire cycle. See Section 15.4.6

“Programmable Dead-Band Delay” for more details

of the dead-band delay operations.

Since the P1A and P1B outputs are multiplexed with

the PORTC<2> and PORTD<5> data latches, the

TRISC<2> and TRISD<5> bits must be cleared to

configure P1A and P1B as outputs.

FIGURE 15-4: HALF-BRIDGE PWM

OUTPUT

FIGURE 15-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS

Period

Duty Cycle

(1)

P1A(2)

P1B(2)

td = Dead-Band Delay

Period

(1) (1)

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

PIC18F4XJ10

P1A

P1B

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

PIC18F4XJ10

P1A

P1B

St andard Half-Bridge Circuit (“Push-Pull”)

Half-B r i dge Output Driv ing a Full-Bridge Circuit

PIC18F45J10 FAMILY

15.4.5 FULL-BRIDGE MODE

In Full-Bridge Output mode, four pins are used as

outputs; however, only two outputs are active at a time.

In the Forward mode, pin P1A is continuously active

and pin P1D is modulated. In the Reverse mode, pin

P1C is continuously active and pin P1B is modulated.

These are illustrated in Figure 15-6.

P1A, P1B, P1C and P1D outputs are multiplexed with

the PORTC<2> and PORTD<7:5> data latches. The

TRISC<2> and TRISD<7:5> bits must be cleared to

make the P1A, P1B, P1C and P1D pins outputs.

FIGURE 15-6: FULL-BRIDGE PWM OUTPUT

Period

Duty Cycle

P1A(2)

P1B(2)

P1C(2)

P1D(2)

Forwar d Mode

(1)

Period

Duty Cycle

P1A(2)

P1C(2)

P1D(2)

P1B(2)

Reverse Mode

(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.

Note 2: Output signal is shown as active-high.

PIC18F45J10 FAMILY

FIGURE 15-7: EX AMP LE OF FULL-BRIDGE APPLICA TION

15.4.5.1 Direction Change in Full-Bridge Mode

In the Full-Bridge Output mode, the P1M1 bit in the

CCP1CON register allows the user to control the

forward/reverse direction. When the application firm-

ware changes this direction control bit, the module will

assume the new direction on the next PWM cycle.

Just before the end of the current PWM period, the

modulated outputs (P1B and P1D) are placed in their

inactive state, while the unmodulated outputs (P1A and

P1C) are switched to drive in the opposite direction.

This occurs in the time interval, 4 T

OSC * (Timer2

Prescale Value), before the next PWM period begins.

The Timer2 prescaler will be either 1, 4 or 16, depend-

ing on the value of the T2CKPS<1:0> bits

(T2CON<1:0>). During the interval from the switch of

the unmodulated outputs to the beginning of the next

period, the modulated outputs (P1B and P1D) remain

inactive. This relationship is shown in Figure 15-8.

Note that in the Full-Bridge Output mode, the ECCP1

module does not provide any dead-band delay. In

general, since only one output is modulated at all times,

dead-band delay is not required. However, there is a

situation where a dead-band delay might be required.

This situation occurs when both of the following

conditions are true:

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn-off time of the power switch, including

the power device and driver circuit, is greater

than the turn-on time.

Figure 15-9 shows an example where the PWM

direction changes from forward to reverse at a near

100% duty cycle. At time t1, the outputs P1A and P1D

become inactive while output P1C becomes active. In

this example, since the turn-off time of the power

devices is longer than the turn-on time, a shoot-through

current may flow through power devices, QC and QD

(see Figure 15-7), for the duration of ‘t’. The same

phenomenon will occur to power devices, QA and QB,

for PWM direction change from reverse to forward.

If changing PWM direction at high duty cycle is required

for an application, one of the following requirements

must be met:

1. Reduce PWM for a PWM period before

changing directions.

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

P1A

P1C

FET

Driver

FET

Driver

V+

V-

Load

FET

Driver

FET

Driver

P1B

P1D

QB QD

PIC18F4XJ10

PIC18F45J10 FAMILY

FIGURE 15-8: PWM DIRECTION CHANGE

FIGURE 15-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Period(1)

SIGNAL

Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.

2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals

of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals

are inactive at this time.

Period

(Note 2)

P1A (Active-High)

P1B (Active-High)

P1C (Active-High)

P1D (Active-High)

Forward Period Reverse Period

P1A(1)

tON(2)

tOFF(3)

t = tOFF – tON(2,3)

P1B(1)

P1C(1)

P1D(1)

External Switch D(1)

Potential

Shoot-Through

Current(1)

Note 1: All signals are shown as active-high.

2: tON is the turn-on delay of power switch QC and its driver.

3: tOFF is the turn-off delay of power switch QD and its driver.

External Switch C(1)

PIC18F45J10 FAMILY

15.4.6 PROGRAMMABLE DEAD-BAND

DELAY

In half-bridge applications, where all power switches

are modulated at the PWM frequency at all times, the

power switches normally require more time to turn off

than to turn on. If both the upper and lower power

switches are switched at the same time (one turned on

and the other turned off), both switches may be on for

a short period of time until one switch completely turns

off. During this brief interval, a very high current (shoot-

through current) may flow through both power

switches, shorting the bridge supply. To avoid this

potentially destructive shoot-through current from

flowing during switching, turning on either of the power

switches is normally delayed to allow the other switch

to completely turn off.

In the Half-Bridge Output mode, a digitally programmable

dead-band delay is available to avoid shoot-through

current from destroying the bridge power switches. The

delay occurs at the signal transition from the nonactive

state to the active state. See Figure 15-4 for an

illustration. Bits PDC<6:0> of the ECCP1DEL register

(Register 15-2) set the delay period in terms of microcon-

troller instruction cycles (TCY or 4 TOSC). These bits are

not available in 28-pin devices as the standard CCP

module does not support half-bridge operation.

15.4.7 ENHANCED PWM AUTO-SHUTDOWN

When the ECCP1 is programmed for any of the

Enhanced PWM modes, the active output pins may be

configured for auto-shutdown. Auto-shutdown immedi-

ately places the Enhanced PWM output pins into a

defined shutdown state when a shutdown event occurs.

A shutdown event can be caused by either of the

comparator modules, a low level on the Fault input pin

(FLT0) or any combination of these three sources. The

comparators may be used to monitor a voltage input

proportional to a current being monitored in the bridge

circuit. If the voltage exceeds a threshold, the

comparator switches state and triggers a shutdown.

Alternatively, a low digital signal on FLT0 can also trigger

a shutdown. The auto-shutdown feature can be disabled

by not selecting any auto-shutdown sources. The auto-

shutdown sources to be used are selected using the

ECCPAS<2:0> bits (bits<6:4> of the ECCP1AS

When a shutdown occurs, the output pins are

asynchronously placed in their shutdown states,

specified by the PSSAC<1:0> and PSSBD<1:0> bits

(ECCPAS<3:0>). Each pin pair (P1A/P1C and P1B/

P1D) may be set to drive high, drive low or be tri-stated

(not driving). The ECCPASE bit (ECCP1AS<7>) is also

set to hold the Enhanced PWM outputs in their

shutdown states.

The ECCPASE bit is set by hardware when a shutdown

event occurs. If automatic restarts are not enabled, the

ECCPASE bit is cleared by firmware when the cause of

the shutdown clears. If automatic restarts are enabled,

the ECCPASE bit is automatically cleared when the

cause of the auto-shutdown has cleared.

If the ECCPASE bit is set when a PWM period begins,

the PWM outputs remain in their shutdown state for that

entire PWM period. When the ECCPASE bit is cleared,

the PWM outputs will return to normal operation at the

beginning of the next PWM period.

Note: Programmable dead-band delay is not

implemented in 28-pin devices with

standard CCP modules.

Note: Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PRSEN: PWM Restart Enable bit

1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away;

the PWM restarts automatically

0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM

bit 6-0 PDC<6:0>: PWM Delay Count bits(1)

Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM

signal to transition to active.

Note 1: Reserved on 28-pin devices; maintain these bits clear.

PIC18F45J10 FAMILY

CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit

1 = A shutdown event has occurred; ECCP outputs are in shutdown state

0 = ECCP outputs are operating

bit 6-4 ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits

111 = FLT0, Comparator 1 or Comparator 2

110 = FLT0 or Comparator 2

101 = FLT0 or Comparator 1

100 =FLT0

011 = Either Comparator 1 or 2

010 = Comparator 2 output

001 = Comparator 1 output

000 = Auto-shutdown is disabled

bit 3-2 PSSAC<1:0>: Pins A and C Shutdown State Control bits

1x = Pins A and C are tri-state (40/44-pin devices); PWM output is tri-state (28-pin devices)

01 = Drive Pins A and C to ‘1’

00 = Drive Pins A and C to ‘0’

bit 1-0 PSSBD<1:0>: Pins B and D Shutdown State Control bits(1)

1x = Pins B and D tri-state

01 = Drive Pins B and D to ‘1’

00 = Drive Pins B and D to ‘0’

Note 1: Reserved on 28-pin devices; maintain these bits clear.

PIC18F45J10 FAMILY

15.4.7.1 Auto-Shutdown and Automatic

Restart

The auto-shutdown feature can be configured to allow

automatic restarts of the module following a shutdown

event. This is enabled by setting the PRSEN bit of the

ECCP1DEL register (ECCP1DEL<7>).

In Shutdown mode with PRSEN = 1 (Figure 15-10), the

ECCPASE bit will remain set for as long as the cause

of the shutdown continues. When the shutdown condi-

tion clears, the ECCPASE bit is cleared. If PRSEN = 0

(Figure 15-11), once a shutdown condition occurs, the

ECCPASE bit will remain set until it is cleared by firm-

ware. Once ECCPASE is cleared, the Enhanced PWM

will resume at the beginning of the next PWM period.

Independent of the PRSEN bit setting, if the auto-

shutdown source is one of the comparators, the

shutdown condition is a level. The ECCPASE bit

cannot be cleared as long as the cause of the shutdown

persists.

The Auto-Shutdown mode can be forced by writing a ‘1’

to the ECCPASE bit.

15.4.8 START-UP CONSIDERATIONS

When the ECCP module is used in the PWM mode, the

application hardware must use the proper external pull-

up and/or pull-down resistors on the PWM output pins.

When the microcontroller is released from Reset, all of

the I/O pins are in the high-impedance state. The

external circuits must keep the power switch devices in

the OFF state until the microcontroller drives the I/O

pins with the proper signal levels, or activates the PWM

output(s).

The CCP1M<1:0> bits (CCP1CON<1:0>) allow the

user to choose whether the PWM output signals are

active-high or active-low for each pair of PWM output

pins (P1A/P1C and P1B/P1D). The PWM output

polarities must be selected before the PWM pins are

configured as outputs. Changing the polarity configura-

tion while the PWM pins are configured as outputs is

not recommended, since it may result in damage to the

application circuits.

The P1A, P1B, P1C and P1D output latches may not be

in the proper states when the PWM module is initialized.

Enabling the PWM pins for output at the same time as

the ECCP module may cause damage to the applica-

tion circuit. The ECCP module must be enabled in the

proper output mode and complete a full PWM cycle

before configuring the PWM pins as outputs. The com-

pletion of a full PWM cycle is indicated by the TMR2IF

bit being set as the second PWM period begins.

FIGURE 15-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)

FIGURE 15-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)

Note: Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

Shutdown

PWM

ECCPASE bit

Activity

Event

Shutdown

Event Occurs

Shutdown

Event Clears

PWM

Resumes

Normal PWM

Start of

PWM Period

Shutdown

PWM

ECCPASE bit

Activity

Event

Shutdown

Event Occurs

Shutdown

Event Clears

PWM

Resumes

Normal PWM

Start of

PWM Period

ECCPASE

Cleared by

Firmware

PWM Period

PIC18F45J10 FAMILY

15.4.9 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the ECCP module for PWM operation:

1. Configure the PWM pins, P1A and P1B (and

P1C and P1D, if used), as inputs by setting the

corresponding TRIS bits.

2. Set the PWM period by loading the PR2 register.

3. If auto-shutdown is required:

• Disable auto-shutdown (ECCPASE = 0)

• Configure source (FLT0, Comparator 1 or

Comparator 2)

• Wait for non-shutdown condition

4. Configure the ECCP module for the desired

PWM mode and configuration by loading the

CCP1CON register with the appropriate values:

• Select one of the available output

configurations and direction with the

P1M<1:0> bits.

• Select the polarities of the PWM output

signals with the CCP1M<3:0> bits.

5. Set the PWM duty cycle by loading the CCPR1L

6. For Half-Bridge Output mode, set the dead-

band delay by loading ECCP1DEL<6:0> with

the appropriate value.

7. If auto-shutdown operation is required, load the

ECCP1AS register:

• Select the auto-shutdown sources using the

ECCPAS<2:0> bits.

• Select the shutdown states of the PWM

output pins using the PSSAC<1:0> and

PSSBD<1:0> bits.

• Set the ECCPASE bit (ECCP1AS<7>).

• Configure the comparators using the CMCON

• Configure the comparator inputs as analog

inputs.

8. If auto-restart operation is required, set the

PRSEN bit (ECCP1DEL<7>).

9. Configure and start TMR2:

• Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit (PIR1<1>).

• Set the TMR2 prescale value by loading the

T2CKPS bits (T2CON<1:0>).

• Enable Timer2 by setting the TMR2ON bit

(T2CON<2>).

10. Enable PWM outputs after a new PWM cycle

has started:

• Wait until TMRx overflows (TMRxIF bit is set).

• Enable the CCP1/P1A, P1B, P1C and/or P1D

pin outputs by clearing the respective TRIS bits.

• Clear the ECCPASE bit (ECCP1AS<7>).

15.4.10 OPERATION IN POWER-MANAGED

MODES

In Sleep mode, all clock sources are disabled. Timer2

will not increment and the state of the module will not

change. If the CCP1 pin is driving a value, it will con-

tinue to drive that value. When the device wakes up, it

will continue from this state. If Two-Speed Start-ups are

enabled, the initial start-up frequency from INTOSC

and the postscaler may not be stable immediately.

In PRI_IDLE mode, the primary clock will continue to

clock the ECCP module without change. In all other

power-managed modes, the selected power-managed

mode clock will clock Timer2. Other power-managed

mode clocks will most likely be different than the

primary clock frequency.

15.4.10.1 Operation with Fail-Safe

Clock Monitor

If the Fail-Safe Clock Monitor is enabled, a clock failure

will force the device into the power-managed RC_RUN

mode and the OSCFIF bit (PIR2<7>) will be set. The

ECCP will then be clocked from the internal oscillator

clock source, which may have a different clock

frequency than the primary clock.

See the previous section for additional details.

15.4.11 EFFECTS OF A RESET

Both Power-on Reset and subsequent Resets will force

all ports to Input mode and the CCP registers to their

Reset states.

This forces the Enhanced CCP module to reset to a

state compatible with the standard CCP module.

PIC18F45J10 FAMILY

TABLE 15-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

RCON IPEN —CM RI TO PD POR BOR 46

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 49

PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 49

IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 49

TRISB PORTB Data Direction Control Register 50

TRISC PORTC Data Direction Control Register 50

TRISD(1) PORTD Data Direction Control Register 50

TMR1L Timer1 Register Low Byte 48

TMR1H Timer1 Register High Byte 48

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 48

TMR2 Timer2 Register 48

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 48

PR2 Timer2 Period Register 48

CCPR1L Capture/Compare/PWM Register 1 Low Byte 49

CCPR1H Capture/Compare/PWM Register 1 High Byte 49

CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 49

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 49

ECCP1DEL PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.

Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

16.0 MASTER SYNCHRONOUS

SERIAL PORT (MS SP)

MODULE

16.1 Master SSP (MSSP) Module

Overview

The Master Synchronous Serial Port (MSSP) module is

a serial interface, useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers,

display drivers, A/D converters, etc. The MSSP module

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C™)

- Full Master mode

- Slave mode (with general address call)

The I2C interface supports the following modes in

hardware:

•Master mode

• Multi-Master mode

• Slave mode

PIC18F24J10/25J10 (28-pin) devices have one MSSP

module designated as MSSP1. PIC18F44J10/45J10

(40/44-pin) devices have two MSSP modules,

designated as MSSP1 and MSSP2. Each module

operates independently of the other.

16.2 Control Registers

Each MSSP module has three associated control

registers. These include a status register (SSPxSTAT)

and two control registers (SSPxCON1 and SSPxCON2).

The use of these registers and their individual configura-

tion bits differ significantly depending on whether the

MSSP module is operated in SPI or I2C mode.

Additional details are provided under the individual

sections.

16.3 SPI Mode

The SPI mode allows 8 bits of data to be synchronously

transmitted and received simultaneously. All four

modes of SPI are supported. To accomplish

communication, typically three pins are used:

• Serial Data Out (SDOx) – RC5/SDO1 or

RD2/PSP2/SDO2

• Serial Data In (SDIx) – RC4/SDI1/SDA1 or

RD1/PSP1/SDI2/SDA2

• Serial Clock (SCKx) – RC3/SCK1/SCL1 or

RD0/PSP0/SCK2/SCL2

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SSx) – RA5/AN4/SS1/C2OUT or

RD3/PSP3/SS2

Figure 16-1 shows the block diagram of the MSSP

module when operating in SPI mode.

FIGURE 16-1: MSSP BLOCK DIAGRAM

(SPI MODE)

Note: Throughout this section, generic refer-

ences to an MSSP module in any of its

operating modes may be interpreted as

being equally applicable to MSSP1 or

MSSP2. Register names and module I/O

signals use the generic designator ‘x’ to

indicate the use of a numeral to distinguish

a particular module, when required.

Control bit names are not individuated.

Note: Disabling the MSSP module by clearing

the SSPEN (SSPxCON1<5>) bit may not

reset the module. It is recommended to

clear the SSPxSTAT, SSPxCON1 and

SSPxCON2 registers and select the mode

prior to setting the SSPEN bit to enable

the MSSP module.

Note: In devices with more than one MSSP

module, it is very important to pay close

attention to SSPxCON register names.

SSP1CON1 and SSP1CON2 control

different operational aspects of the same

module, while SSP1CON1 and

SSP2CON1 control the same features for

two different modules.

Read Write

Internal

Data Bus

SSPxSR reg

SSPM<3:0>

bit 0 Shift

Clock

SSx Control

Enable

Clock Select

TMR2 Output

TOSC

Prescaler

4, 16, 64

Edge

Select

Data to TX/RX in SSPxSR

TRIS bit

SMP:CKE

SDOx

SSPxBUF reg

SDIx

SSx

SCKx

Note: Only port I/O names are used in this diagram for the sake

of brevity. Refer to the text for a full list of multiplexed

functions.

Edge Select

( )

PIC18F45J10 FAMILY

16.3.1 REGISTERS

Each MSSP module has four registers for SPI mode

operation. These are:

• MSSP Control Register 1 (SSPxCON1)

• MSSP Status Register (SSPxSTAT)

• Serial Receive/Transmit Buffer Register

(SSPxBUF)

• MSSP Shift Register (SSPxSR) – Not directly

accessible

SSPxCON1 and SSPxSTAT are the control and status

registers in SPI mode operation. The SSPxCON1

the SSPxSTAT are read-only. The upper two bits of the

SSPxSTAT are read/write.

SSPxSR is the shift register used for shifting data in or

out. SSPxBUF is the buffer register to which data

bytes are written to or read from.

In receive operations, SSPxSR and SSPxBUF

together create a double-buffered receiver. When

SSPxSR receives a complete byte, it is transferred to

SSPxBUF and the SSPxIF interrupt is set.

During transmission, the SSPxBUF is not

double-buffered. A write to SSPxBUF will write to both

SSPxBUF and SSPxSR.

REGIST ER 16-1: SSPxSTAT: MSSP x STATUS REGISTER (SPI MODE )

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE(1) D/A PSR/WUA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Sample bit

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

bit 6 CKE: SPI Clock Select bit(1)

1 = Transmit occurs on transition from active to Idle clock state

0 = Transmit occurs on transition from Idle to active clock state

bit 5 D/A: Data/Address bit

Used in I2C mode only.

bit 4 P: Stop bit

Used in I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared.

bit 3 S: Start bit

Used in I2C mode only.

bit 2 R/W: Read/Write Information bit

Used in I2C mode only.

bit 1 UA: Update Address bit

Used in I2C mode only.

bit 0 BF: Buffer Full Status bit (Receive mode only)

1 = Receive complete, SSPxBUF is full

0 = Receive not complete, SSPxBUF is empty

Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>).

PIC18F45J10 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit(1)

SPI Slave mode:

1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of

overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read

the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in

software).

0 = No overflow

bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2)

1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: Clock Polarity Select bit

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3)

0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin

0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled

0011 = SPI Master mode, clock = TMR2 output/2

0010 = SPI Master mode, clock = FOSC/64

0001 = SPI Master mode, clock = FOSC/16

0000 = SPI Master mode, clock = FOSC/4

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by

writing to the SSPxBUF register.

2: When enabled, these pins must be properly configured as input or output.

3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.

PIC18F45J10 FAMILY

16.3.2 OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCKx is the clock output)

• Slave mode (SCKx is the clock input)

• Clock Polarity (Idle state of SCKx)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCKx)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

Each MSSP consists of a transmit/receive shift register

(SSPxSR) and a buffer register (SSPxBUF). The

SSPxSR shifts the data in and out of the device, MSb

first. The SSPxBUF holds the data that was written to the

SSPxSR until the received data is ready. Once the 8 bits

of data have been received, that byte is moved to the

SSPxBUF register. Then, the Buffer Full detect bit, BF

(SSPxSTAT<0>), and the interrupt flag bit, SSPxIF, are

set. This double-buffering of the received data

(SSPxBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

SSPxBUF register during transmission/reception of data

will be ignored and the Write Collision detect bit, WCOL

(SSPxCON1<7>), will be set. User software must clear

the WCOL bit so that it can be determined if the following

write(s) to the SSPxBUF register completed

successfully.

When the application software is expecting to receive

valid data, the SSPxBUF should be read before the next

byte of data to transfer is written to the SSPxBUF. The

Buffer Full bit, BF (SSPxSTAT<0>), indicates when

SSPxBUF has been loaded with the received data

(transmission is complete). When the SSPxBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the MSSP interrupt

is used to determine when the transmission/reception

has completed. The SSPxBUF must be read and/or

written. If the interrupt method is not going to be used,

then software polling can be done to ensure that a write

collision does not occur. Example 16-1 shows the

loading of the SSP1BUF (SSP1SR) for data

transmission.

The SSPxSR is not directly readable or writable and

can only be accessed by addressing the SSPxBUF

the various status conditions.

EXAMPLE 16-1: LOADING THE SSP1BUF (SSP1SR ) REGISTER

LOOP BTFSS SSP1STAT, BF ;Has data been received (transmit complete)?

BRA LOOP ;No

MOVF SSP1BUF, W ;WREG reg = contents of SSP1BUF

MOVWF RXDATA ;Save in user RAM, if data is meaningful

MOVF TXDATA, W ;W reg = contents of TXDATA

MOVWF SSP1BUF ;New data to xmit

PIC18F45J10 FAMILY

16.3.3 ENABLING SPI I/O

To enable the serial port, MSSP Enable bit, SSPEN

(SSPxCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, reinitialize the

SSPxCON registers and then set the SSPEN bit. This

configures the SDIx, SDOx, SCKx and SSx pins as

serial port pins. For the pins to behave as the serial port

function, some must have their data direction bits (in

the TRIS register) appropriately programmed as

follows:

• SDIx is automatically controlled by the SPI module

• SDOx must have TRISC<5> (or TRISD<2>) bit

cleared

• SCKx (Master mode) must have TRISC<3> (or

TRISD<0>) bit cleared

• SCKx (Slave mode) must have TRISC<3> (or

TRISD<0>) bit set

•SS

x must have TRISA<5> (or TRISD<3>) bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

16.3.4 TYPICAL CONNECTION

Figure 16-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCKx signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge and latched on the opposite edge

of the clock. Both processors should be programmed to

the same Clock Polarity (CKP), then both controllers

would send and receive data at the same time.

Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• Master sends data – Slave sends dummy data

• Master sends data – Slave sends data

• Master sends dummy data – Slave sends data

FIGURE 16-2: SP I MAST E R/S LAVE CONNECTION

Serial Input Buffer

(SSPxBUF)

Shift Register

(SSPxSR)

MSb LSb

SDOx

SDIx

PROCESSOR 1

SCKx

SPI Master SSPM<3:0> = 00xxb

Serial Input Buffer

(SSPxBUF)

Shift Register

(SSPxSR)

LSb

MSb

SDIx

SDOx

PROCESSOR 2

SCKx

SPI Slave SSPM<3:0> = 010xb

Serial Clock

PIC18F45J10 FAMILY

16.3.5 MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCKx. The master determines

when the slave (Processor 2, Figure 16-2) will

broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPxBUF register is written to. If the SPI

is only going to receive, the SDOx output could be dis-

abled (programmed as an input). The SSPxSR register

will continue to shift in the signal present on the SDIx

pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPxBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

The clock polarity is selected by appropriately

programming the CKP bit (SSPxCON1<4>). This then,

would give waveforms for SPI communication as

shown in Figure 16-3, Figure 16-5 and Figure 16-6,

where the MSB is transmitted first. In Master mode, the

SPI clock rate (bit rate) is user-programmable to be one

of the following:

•F

OSC/4 (or TCY)

•FOSC/16 (or 4 • TCY)

•F

OSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 16-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDOx data is valid before

there is a clock edge on SCKx. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPxBUF is loaded with the received

data is shown.

FIGURE 16-3: SPI MODE WAVEFORM (MASTER MODE)

SCKx

(CKP = 0

SCKx

(CKP = 1

SCKx

(CKP = 0

SCKx

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDIx

bit 7 bit 0

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7

SDIx

SSPxIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPxBUF

SSPxSR to

SSPxBUF

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)

Next Q4 Cycle

after Q2↓

bit 0

PIC18F45J10 FAMILY

16.3.6 SLAVE MODE

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCKx. When the

last bit is latched, the SSPxIF interrupt flag bit is set.

Before enabling the module in SPI Slave mode, the

clock line must match the proper Idle state. The clock

line can be observed by reading the SCKx pin. The Idle

state is determined by the CKP bit (SSPxCON1<4>).

While in Slave mode, the external clock is supplied by

the external clock source on the SCKx pin. This

external clock must meet the minimum high and low

times as specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from Sleep.

16.3.7 SLAVE SELECT

SYNCHRONIZATION

The SSx pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SSx pin control

enabled (SSPxCON1<3:0> = 04h). When the SSx pin

is low, transmission and reception are enabled and the

SDOx pin is driven. When the SSx pin goes high, the

SDOx pin is no longer driven, even if in the middle of a

transmitted byte and becomes a floating output.

External pull-up/pull-down resistors may be desirable

depending on the application.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SSx pin to

a high level or clearing the SSPEN bit.

To emulate two-wire communication, the SDOx pin can

be connected to the SDIx pin. When the SPI needs to

operate as a receiver, the SDOx pin can be configured

as an input. This disables transmissions from the

SDOx. The SDIx can always be left as an input (SDIx

function) since it cannot create a bus conflict.

FIGURE 16-4: SLAV E SYNCHRONIZATION WAVEFORM

Note 1: When the SPI is in Slave mode with SSx pin

control enabled (SSPxCON1<3:0> = 0100),

the SPI module will reset if the SSx pin is set

to VDD.

2: If the SPI is used in Slave mode with CKE

set, then the SSx pin control must be

enabled.

SCKx

(CKP = 1

SCKx

(CKP = 0

Input

Sample

SDIx

bit 7

SDOx bit 7 bit 6 bit 7

SSPxIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPxBUF

SSPxSR to

SSPxBUF

SSx

Flag

bit 0

bit 7

bit 0

Next Q4 Cycle

after Q2

↓

PIC18F45J10 FAMILY

FIGURE 16-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 16-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SCKx

(CKP = 1

SCKx

(CKP = 0

Input

Sample

SDIx

bit 7

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPxIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPxBUF

SSPxSR to

SSPxBUF

SSx

Flag

Optional

Next Q4 Cycle

after Q2↓

bit 0

SCKx

(CKP = 1

SCKx

(CKP = 0

Input

Sample

SDIx

bit 7 bit 0

SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPxIF

Interrupt

(SMP = 0)

CKE = 1)

(SMP = 0)

Write to

SSPxBUF

SSPxSR to

SSPxBUF

SSx

Flag

Not Optional

Next Q4 Cycle

after Q2↓

PIC18F45J10 FAMILY

16.3.8 OPERATION IN POWER-MANAGED

MODES

In SPI Master mode, module clocks may be operating

at a different speed than when in Full-Power mode; in

the case of Sleep mode, all clocks are halted.

In Idle modes, a clock is provided to the peripherals.

That clock should be from the primary clock source, the

secondary clock (Timer1 oscillator at 32.768 kHz) or

the INTOSC source. See Sec tion 3.6 “Clock Source s

and Oscillator Switching” for additional information.

In most cases, the speed that the master clocks SPI

data is not important; however, this should be

evaluated for each system.

If MSSP interrupts are enabled, they can wake the con-

troller from Sleep mode, or one of the Idle modes, when

the master completes sending data. If an exit from

Sleep or Idle mode is not desired, MSSP interrupts

should be disabled.

If the Sleep mode is selected, all module clocks are

halted and the transmission/reception will remain in

that state until the devices wakes. After the device

returns to Run mode, the module will resume

transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

allows the device to be placed in any power-managed

mode and data to be shifted into the SPI

Transmit/Receive Shift register. When all 8 bits have

been received, the MSSP interrupt flag bit will be set

and if enabled, will wake the device.

16.3.9 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

16.3.10 BUS MODE COMPATIBILITY

Table 16-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 16-1: SPI BUS MODES

There is also an SMP bit which controls when the data

is sampled.

16.3.11 SPI CLOCK SPEED AND MODULE

INTERACTIONS

Because MSSP1 and MSSP2 are independent

modules, they can operate simultaneously at different

data rates. Setting the SSPM<3:0> bits of the

SSPxCON1 register determines the rate for the

corresponding module.

An exception is when both modules use Timer2 as a

time base in Master mode. In this instance, any

changes to the Timer2 operation will affect both MSSP

modules equally. If different bit rates are required for

each module, the user should select one of the other

three time base options for one of the modules.

Standard SPI Mode

Terminology

Control Bits State

CKP CKE

0, 0 0 1

0, 1 0 0

1, 0 1 1

1, 1 1 0

PIC18F45J10 FAMILY

TABLE 16-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

PIR3 SSP2IF BCL2IF ——————49

PIE3 SSP2IE BCL2IE ——————49

IPR3 SSP2IP BCL2IP ——————49

TRISA —— TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 50

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 50

SSP1BUF MSSP1 Receive Buffer/Transmit Register 48

SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 48

SSP1STAT SMP CKE D/A P S R/W UA BF 48

SSP2BUF MSSP2 Receive Buffer/Transmit Register 50

SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50

SSP2STAT SMP CKE D/A P S R/W UA BF 50

Legend: Shaded cells are not used by the MSSP module in SPI mode.

Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

16.4 I2C Mode

The MSSP module in I2C mode fully implements all

master and slave functions (including general call

support) and provides interrupts on Start and Stop bits

in hardware to determine a free bus (multi-master

function). The MSSP module implements the standard

mode specifications, as well as 7-bit and 10-bit

addressing.

Two pins are used for data transfer:

• Serial clock (SCLx) – RC3/SCK1/SCL1 or

RD6/SCK2/SCL2

• Serial data (SDAx) – RC4/SDI1/SDA1 or

RD5/SDI2/SDA2

The user must configure these pins as inputs by setting

the associated TRIS bits.

FIGURE 16-7: MSSP BLOCK DIAGRAM

(I2C™ MODE)

16.4.1 REGISTERS

The MSSP module has six registers for I2C operation.

These are:

• MSSP Control Register 1 (SSPxCON1)

• MSSP Control Register 2 (SSPxCON2)

• MSSP Status Register (SSPxSTAT)

• Serial Receive/Transmit Buffer Register

(SSPxBUF)

• MSSP Shift Register (SSPxSR) – Not directly

accessible

• MSSP Address Register (SSPxADD)

SSPxCON1, SSPxCON2 and SSPxSTAT are the

control and status registers in I2C mode operation. The

SSPxCON1 and SSPxCON2 registers are readable

and writable. The lower 6 bits of the SSPxSTAT are

read-only. The upper two bits of the SSPxSTAT are

read/write.

Many of the bits in SSPxCON2 assume different

functions, depending on whether the module is operat-

ing in Master or Slave mode; bits<5:2> also assume

different names in Slave mode. The different aspects of

SSPxCON2 are shown in Register 16-5 (for Master

mode) and Register 16-6 (Slave mode).

SSPxSR is the shift register used for shifting data in or

out. SSPxBUF is the buffer register to which data bytes

are written to or read from.

SSPxADD register holds the slave device address

when the MSSP is configured in I2C Slave mode. When

the MSSP is configured in Master mode, the lower

seven bits of SSPxADD act as the Baud Rate

Generator reload value.

In receive operations, SSPxSR and SSPxBUF together

create a double-buffered receiver. When SSPxSR

receives a complete byte, it is transferred to SSPxBUF

and the SSPxIF interrupt is set.

During transmission, the SSPxBUF is not

double-buffered. A write to SSPxBUF will write to both

SSPxBUF and SSPxSR.

Read Write

SSPxSR reg

Match Detect

SSPxADD reg

SSPxBUF reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPxSTAT reg)

Shift

Clock

MSb LSb

Note: Only port I/O names are used in this diagram for

the sake of brevity. Refer to the text for a full list of

multiplexed functions.

SCLx

SDAx

Start and

Stop bit Detect

Address Mask

Note: Disabling the MSSP module by clearing

the SSPEN (SSPxCON1<5>) bit may not

reset the module. It is recommended to

clear the SSPxSTAT, SSPxCON1 and

SSPxCON2 registers and select the mode

prior to setting the SSPEN bit to enable

the MSSP module.

PIC18F45J10 FAMILY

REGIST ER 16-3: SSPxSTAT: MSSP x STATUS REGISTER (I 2C™ MODE)

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R0 R-0

SMP CKE D/A P(1) S(1) R/W UA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Slew Rate Control bit

In Master or Slave mode:

1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for High-Speed mode (400 kHz)

bit 6 CKE: SMBus Select bit

In Master or Slave mode:

1 = Enable SMBus specific inputs

0 = Disable SMBus specific inputs

bit 5 D/A: Data/Address bit

In Master mode:

Reserved.

In Slave mode:

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit(1)

1 = Indicates that a Stop bit has been detected last

0 = Stop bit was not detected last

bit 3 S: Start bit(1)

1 = Indicates that a Start bit has been detected last

0 = Start bit was not detected last

bit 2 R/W: Read/Write Information bit (I2C mode only)

In Slave mode:(2)

1 = Read

0 = Write

In Master mode:(3)

1 = Transmit is in progress

0 = Transmit is not in progress

bit 1 UA: Update Address bit (10-Bit Slave mode only)

1 = Indicates that the user needs to update the address in the SSPxADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

In Transmit mode:

1 = SSPxBUF is full

0 = SSPxBUF is empty

In Receive mode:

1 = SSPxBUF is full (does not include the ACK and Stop bits)

0 = SSPxBUF is empty (does not include the ACK and Stop bits)

Note 1: This bit is cleared on Reset and when SSPEN is cleared.

2: This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit or not ACK bit.

3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.

PIC18F45J10 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN(1) CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

In Master Transmit mode:

1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a

transmission to be started (must be cleared in software)

0 = No collision

In Slave Transmit mode:

1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0 = No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit.

bit 6 SSPOV: Receive Overflow Indicator bit

In Receive mode:

1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in

software)

0 = No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mode.

bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1)

1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: SCK Release Control bit

In Slave mode:

1 = Release clock

0 = Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode.

bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits

1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1011 = I2C Firmware Controlled Master mode (slave Idle)

1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1))

0111 = I2C Slave mode, 10-bit address

0110 = I2C Slave mode, 7-bit address

Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.

Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs.

PIC18F45J10 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Enable bit

Unused in Master mode.

bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1 = Acknowledge was not received from slave

0 = Acknowledge was received from slave

bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1)

1 = Not Acknowledge

0 = Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit(2)

1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.

Automatically cleared by hardware.

0 = Acknowledge sequence Idle

bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2)

1 = Enables Receive mode for I2C

0 = Receive Idle

bit 2 PEN: Stop Condition Enable bit(2)

1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.

0 = Stop condition Idle

bit 1 RSEN: Repeated Start Condition Enable bit(2)

1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.

0 = Repeated Start condition Idle

bit 0 SEN: Start Condition Enable bit(2)

1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.

0 = Start condition Idle

Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written

(or writes to the SSPxBUF are disabled).

PIC18F45J10 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Enable bit

1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR

0 = General call address disabled

bit 6 ACKSTAT: Acknowledge Status bit

Unused in Slave mode.

bit 5-2 ADMSK<5:2>: Slave Address Mask Select bits

1 = Masking of corresponding bits of SSPxADD enabled

0 = Masking of corresponding bits of SSPxADD disabled

bit 1 ADMSK1: Slave Address Least Significant bit(s) Mask Select bit

In 7-Bit Addressing mode:

1 = Masking of SSPxADD<1> only enabled

0 = Masking of SSPxADD<1> only disabled

In 10-Bit Addressing mode:

1 = Masking of SSPxADD<1:0> enabled

0 = Masking of SSPxADD<1:0> disabled

bit 0 SEN: Stretch Enable bit(1)

1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0 = Clock stretching is disabled

Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or

writes to the SSPxBUF are disabled).

PIC18F45J10 FAMILY

16.4.2 OPERATION

The MSSP module functions are enabled by setting the

MSSP Enable bit, SSPEN (SSPxCON1<5>).

The SSPxCON1 register allows control of the I2C

operation. Four mode selection bits

(SSPxCON1<3:0>) allow one of the following I2C

modes to be selected:

•I

2C Master mode,

clock = (FOSC/4) x (SSPxADD + 1)

•I

2C Slave mode (7-bit address)

•I

2C Slave mode (10-bit address)

•I

2C Slave mode (7-bit address) with Start and

Stop bit interrupts enabled

•I

2C Slave mode (10-bit address) with Start and

Stop bit interrupts enabled

•I

2C Firmware Controlled Master mode,

slave is Idle

Selection of any I2C mode, with the SSPEN bit set,

forces the SCLx and SDAx pins to be open-drain,

provided these pins are programmed to inputs by

setting the appropriate TRISC or TRISD bits. To ensure

proper operation of the module, pull-up resistors must

be provided externally to the SCLx and SDAx pins.

16.4.3 SLAVE MODE

In Slave mode, the SCLx and SDAx pins must be

configured as inputs (TRISC<4:3> set). The MSSP

module will override the input state with the output data

when required (slave-transmitter).

The I2C Slave mode hardware will always generate an

interrupt on an exact address match. In addition,

address masking will also allow the hardware to gener-

ate an interrupt for more than one address (up to 31 in

7-bit addressing and up to 63 in 10-bit addressing).

Through the mode select bits, the user can also choose

to interrupt on Start and Stop bits.

When an address is matched, or the data transfer after

an address match is received, the hardware auto-

matically will generate the Acknowledge (ACK) pulse

and load the SSPxBUF register with the received value

currently in the SSPxSR register.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

• The Buffer Full bit, BF (SSPxSTAT<0>), was set

before the transfer was received.

• The MSSP Overflow bit, SSPOV

(SSPxCON1<6>), was set before the transfer was

received.

In this case, the SSPxSR register value is not loaded

into the SSPxBUF, but the SSPxIF bit is set. The BF bit

is cleared by reading the SSPxBUF register, while the

SSPOV bit is cleared through software.

The SCLx clock input must have a minimum high and

low for proper operation. The high and low times of the

I2C specification, as well as the requirement of the

MSSP module, are shown in timing parameter 100 and

parameter 101.

16.4.3.1 Addressing

Once the MSSP module has been enabled, it waits for

a Start condition to occur. Following the Start condition,

the 8 bits are shifted into the SSPxSR register. All

incoming bits are sampled with the rising edge of the

clock (SCLx) line. The value of register SSPxSR<7:1>

is compared to the value of the SSPxADD register. The

address is compared on the falling edge of the eighth

clock (SCLx) pulse. If the addresses match and the BF

and SSPOV bits are clear, the following events occur:

1. The SSPxSR register value is loaded into the

SSPxBUF register.

2. The Buffer Full bit, BF, is set.

3. An ACK pulse is generated.

4. The MSSP Interrupt Flag bit, SSPxIF, is set (and

interrupt is generated, if enabled) on the falling

edge of the ninth SCLx pulse.

In 10-Bit Addressing mode, two address bytes need to

be received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPxSTAT<2>) must specify a write

so the slave device will receive the second address byte.

For a 10-bit address, the first byte would equal ‘11110

A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the

address. The sequence of events for 10-Bit Addressing

mode is as follows, with steps 7 through 9 for the

slave-transmitter:

1. Receive first (high) byte of address (bits,

SSPxIF, BF and UA (SSPxSTAT<1>), are set).

2. Update the SSPxADD register with second (low)

byte of address (clears bit, UA, and releases the

SCLx line).

3. Read the SSPxBUF register (clears bit, BF) and

clear flag bit, SSPxIF.

4. Receive second (low) byte of address (bits,

SSPxIF, BF and UA, are set).

5. Update the SSPxADD register with the first

(high) byte of address. If match releases SCLx

line, this will clear bit, UA.

6. Read the SSPxBUF register (clears bit, BF) and

clear flag bit, SSPxIF.

7. Receive Repeated Start condition.

8. Receive first (high) byte of address (bits,

SSPxIF and BF, are set).

9. Read the SSPxBUF register (clears bit, BF) and

clear flag bit, SSPxIF.

PIC18F45J10 FAMILY

16.4.3.2 Address Masking

Masking an address bit causes that bit to become a

“don’t care”. When one address bit is masked, two

addresses will be Acknowledged and cause an

interrupt. It is possible to mask more than one address

bit at a time, which makes it possible to Acknowledge

up to 31 addresses in 7-Bit Addressing mode and up to

63 addresses in 10-Bit Addressing mode (see

Example 16-2).

The I2C Slave behaves the same way, whether

address masking is used or not. However, when

address masking is used, the I2C slave can

Acknowledge multiple addresses and cause interrupts.

When this occurs, it is necessary to determine which

address caused the interrupt by checking SSPxBUF.

In 7-Bit Addressing mode, Address Mask bits,

ADMSK<5:1> (SSPxCON2<5:1>), mask the

corresponding address bits in the SSPxADD register. For

any ADMSK bits that are set (ADMSK<n> = 1), the cor-

responding address bit is ignored (SSPxADD<n> = x).

For the module to issue an address Acknowledge, it is

sufficient to match only on addresses that do not have an

active address mask.

In 10-Bit Addressing mode, ADMSK<5:2> bits mask

the corresponding address bits in the SSPxADD regis-

ter. In addition, ADMSK1 simultaneously masks the two

LSbs of the address (SSPxADD<1:0>). For any

ADMSK bits that are active (ADMSK<n> = 1), the cor-

responding address bit is ignored (SSPxADD<n> = x).

Also note that although in 10-Bit Addressing mode, the

upper address bits reuse part of the SSPxADD register

bits, the address mask bits do not interact with those

bits. They only affect the lower address bits.

EXAMPLE 16-2: ADDRESS MASKING EXAMP LES

Note 1: ADMSK1 masks the two Least Significant

bits of the address.

2: The two Most Significant bits of the

address are not affected by address

masking.

7-Bit Addressing:

SSPxADD<7:1>= A0h (1010000) (SSPxADD<0> is assumed to be ‘0’)

ADMSK<5:1> = 00111

Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh

10-Bit Addressing:

SSPxADD<7:0>= A0h (10100000) (the two MSbs of the address are ignored in this example, since they are

not affected by masking)

ADMSK<5:1> = 00111

Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh

PIC18F45J10 FAMILY

16.4.3.3 Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPxSTAT

the SSPxBUF register and the SDAx line is held low

(ACK).

When the address byte overflow condition exists, then

the no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit, BF (SSPxSTAT<0>),

is set, or bit, SSPOV (SSPxCON1<6>), is set.

An MSSP interrupt is generated for each data transfer

byte. The interrupt flag bit, SSPxIF, must be cleared in

software. The SSPxSTAT register is used to determine

the status of the byte.

If SEN is enabled (SSPxCON2<0> = 1), SCKx/SCLx

(RC3 or RD0) will be held low (clock stretch) following

each data transfer. The clock must be released by

setting bit, CKP (SSPxCON1<4>). See Section 16.4.4

“Clock Stretching” for more details.

16.4.3.4 Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPxSTAT register is set. The received address is

loaded into the SSPxBUF register. The ACK pulse will

be sent on the ninth bit and pin RC3 or RD6 is held low,

regardless of SEN (see Section 16.4.4 “Clock

Stretching” for more details). By stretching the clock,

the master will be unable to assert another clock pulse

until the slave is done preparing the transmit data. The

transmit data must be loaded into the SSPxBUF regis-

ter which also loads the SSPxSR register. Then pin

RC3 or RD0 should be enabled by setting bit, CKP

(SSPxCON1<4>). The eight data bits are shifted out on

the falling edge of the SCLx input. This ensures that the

SDAx signal is valid during the SCLx high time

(Figure 16-9).

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCLx input pulse. If the

SDAx line is high (not ACK), then the data transfer is

complete. In this case, when the ACK is latched by the

slave, the slave logic is reset (resets SSPxSTAT

of the Start bit. If the SDAx line was low (ACK), the next

transmit data must be loaded into the SSPxBUF regis-

ter. Again, pin RC3 or RD0 must be enabled by setting

bit CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPxIF bit must be cleared in software and

the SSPxSTAT register is used to determine the status

of the byte. The SSPxIF bit is set on the falling edge of

the ninth clock pulse.

PIC18F45J10 FAMILY

FIGURE 16-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING)

SDAx

SCLx

SSPxIF (PIR1<3> or PIR3<7>)

BF (SSPxSTAT<0>)

SSPOV (SSPxCON1<6>)

S1 234 567 89 1 2 34 5 67 89 1 2345 7 89 P

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPxBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPxBUF is

still full. ACK is not sent.

CKP

(CKP does not reset to ‘0’ when SEN = 0)

PIC18F45J10 FAMILY

FIGURE 16-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING)

SDAx

SCLx

BF (SSPxSTAT<0>)

A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9

SSPxBUF is written in software

Cleared in software

Data in

sampled

ACK

Transmitting Data

R/W = 0

ACK

Receiving Address

A7 D7

D6 D5 D4 D3 D2 D1 D0

2 3 4 5 6 7 8 9

SSPxBUF is written in software

Cleared in software

From SSPxIF ISR

Transmitting Data

CKP (SSPxCON<4>)

ACK

CKP is set in software CKP is set in software

SCLx held low

while CPU

responds to SSPxIF

SSPxIF (PIR1<3> or PIR3<7>)

From SSPxIF ISR

Clear by reading

PIC18F45J10 FAMILY

FIGURE 16-10 : I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING)

SDAx

SCLx

SSPxIF (PIR1<3> or PIR3<7>)

BF (SSPxSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6A5 A4A3A2A1A0 D7 D6D5D4D3 D1D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Receive Second Byte of Address

Cleared by hardware

when SSPxADD is updated

with low byte of address

UA (SSPxSTAT<1>)

Clock is held low until

update of SSPxADD has

taken place

UA is set indicating that

the SSPxADD needs to be

updated

UA is set indicating that

SSPxADD needs to be

updated

Cleared by hardware when

SSPxADD is updated with high

byte of address

SSPxBUF is written with

contents of SSPxSR

Dummy read of SSPxBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPxCON1<6>)

SSPOV is set

because SSPxBUF is

still full. ACK is not sent.

(CKP does not reset to ‘0’ when SEN = 0)

Clock is held low until

update of SSPxADD has

taken place

PIC18F45J10 FAMILY

FIGURE 16-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING)

SDAx

SCLx

SSPxIF (PIR1<3> or PIR3<7>)

BF (SSPxSTAT<0>)

S1234 5 6789 12345678 9 12345 7 89 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 1 1 1 1 0 A8

R/W = 1

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Bus master

terminates

transfer

Receive Second Byte of Address

Cleared by hardware when

SSPxADD is updated with low

byte of address

UA (SSPxSTAT<1>)

Clock is held low until

update of SSPxADD has

taken place

UA is set indicating that

the SSPxADD needs to be

updated

UA is set indicating that

SSPxADD needs to be

updated

Cleared by hardware when

SSPxADD is updated with high

byte of address.

SSPxBUF is written with

contents of SSPxSR

Dummy read of SSPxBUF

to clear BF flag

Receive First Byte of Address

12345 789

D7 D6 D5 D4 D3 D1

ACK

Transmitting Data Byte

Dummy read of SSPxBUF

to clear BF flag

Cleared in software

Write of SSPxBUF

initiates transmit

Cleared in software

Completion of

clears BF flag

CKP (SSPxCON1<4>)

CKP is set in software

CKP is automatically cleared in hardware, holding SCLx low

Clock is held low until

update of SSPxADD has

taken place

data transmission

Clock is held low until

CKP is set to ‘1’

third address sequence

BF flag is clear

at the end of the

PIC18F45J10 FAMILY

16.4.4 CLOCK STRETCHING

Both 7-Bit and 10-Bit Slave modes implement

automatic clock stretching during a transmit sequence.

The SEN bit (SSPxCON2<0>) allows clock stretching

to be enabled during receives. Setting SEN will cause

the SCLx pin to be held low at the end of each data

receive sequence.

16.4.4.1 Clock Stretching for 7-Bit Slave

Receive Mode (SEN = 1)

In 7-Bit Slave Receive mode, on the falling edge of the

ninth clock at the end of the ACK sequence, if the BF

bit is set, the CKP bit in the SSPxCON1 register is

automatically cleared, forcing the SCLx output to be

held low. The CKP being cleared to ‘0’ will assert the

SCLx line low. The CKP bit must be set in the user’s

ISR before reception is allowed to continue. By holding

the SCLx line low, the user has time to service the ISR

and read the contents of the SSPxBUF before the

master device can initiate another receive sequence.

This will prevent buffer overruns from occurring (see

Figure 16-13).

16.4.4.2 Clock Stretching for 10-Bit Slave

Receive Mode (SEN = 1)

In 10-Bit Slave Receive mode during the address

sequence, clock stretching automatically takes place

but CKP is not cleared. During this time, if the UA bit is

set after the ninth clock, clock stretching is initiated.

The UA bit is set after receiving the upper byte of the

10-bit address and following the receive of the second

byte of the 10-bit address with the R/W bit cleared to

‘0’. The release of the clock line occurs upon updating

SSPxADD. Clock stretching will occur on each data

receive sequence as described in 7-bit mode.

16.4.4.3 Clock Stretching for 7-Bit Slave

Transmit Mode

The 7-Bit Slave Transmit mode implements clock

stretching by clearing the CKP bit after the falling edge

of the ninth clock, if the BF bit is clear. This occurs

regardless of the state of the SEN bit.

The user’s ISR must set the CKP bit before transmis-

sion is allowed to continue. By holding the SCLx line

low, the user has time to service the ISR and load the

contents of the SSPxBUF before the master device

can initiate another transmit sequence (see

Figure 16-9).

16.4.4.4 Clock Stretching for 10-Bit Slave

Transmit Mode

In 10-Bit Slave Transmit mode, clock stretching is con-

trolled during the first two address sequences by the

state of the UA bit, just as it is in 10-bit Slave Receive

mode. The first two addresses are followed by a third

address sequence which contains the high-order bits

of the 10-bit address and the R/W bit set to ‘1’. After

the third address sequence is performed, the UA bit is

not set, the module is now configured in Transmit

mode and clock stretching is controlled by the BF flag

as in 7-Bit Slave Transmit mode (see Figure 16-11).

Note 1: If the user reads the contents of the

SSPxBUF before the falling edge of the

ninth clock, thus clearing the BF bit, the

CKP bit will not be cleared and clock

stretching will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit. The

user should be careful to clear the BF bit

in the ISR before the next receive

sequence in order to prevent an overflow

condition.

Note: If the user polls the UA bit and clears it by

updating the SSPxADD register before the

falling edge of the ninth clock occurs and if

the user hasn’t cleared the BF bit by read-

ing the SSPxBUF register before that time,

then the CKP bit will still NOT be asserted

low. Clock stretching on the basis of the

state of the BF bit only occurs during a

data sequence, not an address sequence.

Note 1: If the user loads the contents of

SSPxBUF, setting the BF bit before the

falling edge of the ninth clock, the CKP bit

will not be cleared and clock stretching

will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit.

PIC18F45J10 FAMILY

16.4.4.5 Clock Synchronization and

the CKP bit

When the CKP bit is cleared, the SCLx output is forced

to ‘0’. However, clearing the CKP bit will not assert the

SCLx output low until the SCLx output is already sam-

pled low. Therefore, the CKP bit will not assert the

SCLx line until an external I2C master device has

already asserted the SCLx line. The SCLx output will

remain low until the CKP bit is set and all other

devices on the I2C bus have deasserted SCLx. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCLx (see

Figure 16-12).

FIGURE 16-12: CLOCK SYNCHRONIZATION TIMING

SDAx

SCLx

DX – 1DX

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPxCON

CKP

Master Device

Deasserts Clock

Master Device

Asserts Clock

PIC18F45J10 FAMILY

FIGURE 16-13 : I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESSING)

SDAx

SCLx

SSPxIF (PIR1<3> or PIR3<7>)

BF (SSPxSTAT<0>)

SSPOV (SSPxCON1<6>)

S1 234 567 89 1 2345 67 89 1 23 45 7 89 P

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPxBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPxBUF is

still full. ACK is not sent.

CKP

written

to ‘1’ in

If BF is cleared

prior to the falling

edge of the 9th clock,

CKP will not be reset

to ‘0’ and no clock

stretching will occur

software

Clock is held low until

CKP is set to ‘1’

Clock is not held low

because buffer full bit is

clear prior to falling edge

of 9th clock

Clock is not held low

because ACK =

BF is set after falling

edge of the 9th clock,

CKP is reset to ‘0’ and

clock stretching occurs

PIC18F45J10 FAMILY

FIGURE 16-14 : I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING)

SDAx

SCLx

SSPxIF (PIR1<3> or PIR3<7>)

BF (SSPxSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1 A0 D7D6D5D4D3 D1D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Receive Second Byte of Address

Cleared by hardware when

SSPxADD is updated with low

byte of address after falling edge

UA (SSPxSTAT<1>)

Clock is held low until

update of SSPxADD has

taken place

UA is set indicating that

the SSPxADD needs to be

updated

UA is set indicating that

SSPxADD needs to be

updated

Cleared by hardware when

SSPxADD is updated with high

byte of address after falling edge

SSPxBUF is written with

contents of SSPxSR

Dummy read of SSPxBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPxCON1<6>)

CKP written to

‘

’

Note: An update of the SSPxADD register before the

falling edge of the ninth clock will have no effect

on UA and UA will remain set.

Note: An update of the SSPxADD

edge of the ninth clock will

have no effect on UA and

UA will remain set.

in software

Clock is held low until

update of SSPxADD has

taken place

of ninth clock

SSPOV is set

because SSPxBUF is

still full. ACK is not sent.

Dummy read of SSPxBUF

to clear BF flag

Clock is held low until

CKP is set to

‘

’

Clock is not held low

because ACK =

PIC18F45J10 FAMILY

16.4.5 GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I2C bus is such that

the first byte after the Start condition usually

determines which device will be the slave addressed by

the master. The exception is the general call address

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all ‘0’s with R/W = 0.

The general call address is recognized when the

General Call Enable bit, GCEN, is enabled

(SSPxCON2<7> set). Following a Start bit detect, 8 bits

are shifted into the SSPxSR and the address is

compared against the SSPxADD. It is also compared to

the general call address and fixed in hardware.

If the general call address matches, the SSPxSR is

transferred to the SSPxBUF, the BF flag bit is set

(eighth bit) and on the falling edge of the ninth bit (ACK

bit), the SSPxIF interrupt flag bit is set.

When the interrupt is serviced, the source for the

interrupt can be checked by reading the contents of the

SSPxBUF. The value can be used to determine if the

address was device-specific or a general call address.

In 10-bit mode, the SSPxADD is required to be updated

for the second half of the address to match and the UA

bit is set (SSPxSTAT<1>). If the general call address is

sampled when the GCEN bit is set, while the slave is

configured in 10-Bit Addressing mode, then the second

half of the address is not necessary, the UA bit will not

be set and the slave will begin receiving data after the

Acknowledge (Figure 16-15).

FIGURE 16-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESSING MODE)

SDAx

SCLx

SSPxIF

BF (SSPxSTAT<0>)

SSPOV (SSPxCON1<6>)

Cleared in software

SSPxBUF is read

R/W = 0

ACK

General Call Address

Address is compared to General Call Address

GCEN (SSPxCON2<7>)

Receiving Data ACK

123456789123456789

D7 D6 D5 D4 D3 D2 D1 D0

after ACK, set interrupt

‘0’

‘1’

PIC18F45J10 FAMILY

16.4.6 MASTER MODE

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPxCON1 and by setting

the SSPEN bit. In Master mode, the SCLx and SDAx

lines are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared

from a Reset or when the MSSP module is disabled.

Control of the I2C bus may be taken when the P bit is

set, or the bus is Idle, with both the S and P bits clear.

In Firmware Controlled Master mode, user code

conducts all I2C bus operations based on Start and

Stop bit conditions.

Once Master mode is enabled, the user has six

options.

1. Assert a Start condition on SDAx and SCLx.

2. Assert a Repeated Start condition on SDAx and

SCLx.

3. Write to the SSPxBUF register initiating

transmission of data/address.

4. Configure the I2C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a Stop condition on SDAx and SCLx.

The following events will cause the MSSP Interrupt

Flag bit, SSPxIF, to be set (and MSSP interrupt, if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated Start

FIGURE 16-16: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)

Note: The MSSP module, when configured in

I2C Master mode, does not allow queueing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPxBUF register to

initiate transmission before the Start con-

dition is complete. In this case, the

SSPxBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPxBUF did not occur.

Read Write

SSPxSR

Start bit, Stop bit,

SSPxBUF

Internal

Data Bus

Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1);

Shift

Clock

MSb LSb

SDAx

Acknowledge

Generate

Stop bit Detect,

Write Collision Detect,

Clock Arbitration,

State Counter for

End of XMIT/RCV

SCLx

SCLx In

Bus Collision

SDAx In

Receive Enable

Clock Cntl

Clock Arbitrate/WCOL Detect

(hold off clock source)

SSPxADD<6:0>

Baud

Set SSPxIF, BCLxIF;

Reset ACKSTAT, PEN (SSPxCON2)

Rate

Generator

SSPM<3:0>

Start bit Detect,

PIC18F45J10 FAMILY

16.4.6.1 I2C Master Mode Operation

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDAx, while SCLx outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘0’. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDAx, while SCLx outputs

the serial clock. Serial data is received 8 bits at a time.

After each byte is received, an Acknowledge bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

The Baud Rate Generator used for the SPI mode

operation is used to set the SCLx clock frequency for

either 100 kHz, 400 kHz or 1 MHz I2C operation. See

Section 16.4.7 “Baud Rate” for more detail.

A typical transmit sequence would go as follows:

1. The user generates a Start condition by setting

the Start Enable bit, SEN (SSPxCON2<0>).

2. SSPxIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

3. The user loads the SSPxBUF with the slave

address to transmit.

4. Address is shifted out the SDAx pin until all 8 bits

are transmitted.

5. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPxCON2 register (SSPxCON2<6>).

6. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the

SSPxIF bit.

7. The user loads the SSPxBUF with eight bits of

data.

8. Data is shifted out the SDAx pin until all 8 bits

are transmitted.

9. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPxCON2 register (SSPxCON2<6>).

10. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the

SSPxIF bit.

11. The user generates a Stop condition by setting

the Stop Enable bit, PEN (SSPxCON2<2>).

12. Interrupt is generated once the Stop condition is

complete.

PIC18F45J10 FAMILY

16.4.7 BAUD RATE

In I2C Master mode, the Baud Rate Generator (BRG)

reload value is placed in the lower 7 bits of the

SSPxADD register (Figure 16-17). When a write

occurs to SSPxBUF, the Baud Rate Generator will

automatically begin counting. The BRG counts down to

‘0’ and stops until another reload has taken place. The

BRG count is decremented twice per instruction cycle

CY) on the Q2 and Q4 clocks. In I2C Master mode, the

BRG is reloaded automatically.

Once the given operation is complete (i.e., transmis-

sion of the last data bit is followed by ACK), the internal

clock will automatically stop counting and the SCLx pin

will remain in its last state.

Table 16-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPxADD.

16.4.7.1 Baud Rate and Module

Interdependence

Because MSSP1 and MSSP2 are independent, they

can operate simultaneously in I2C Master mode at

different baud rates. This is done by using different

BRG reload values for each module.

Because this mode derives its basic clock source from

the system clock, any changes to the clock will affect

both modules in the same proportion. It may be pos-

sible to change one or both baud rates back to a

previous value by changing the BRG reload value.

FIGURE 16-17: BAUD RATE GENERATOR BLOCK DIAGRAM

TABLE 16-3: I2C™ CLOCK RATE w/BRG

SSPM<3:0>

BRG Down Counter

CLKO FOSC/4

SSPxADD<6:0>

SSPM<3:0>

SCLx

Reload

Control

Reload

FCY FCY * 2 BRG Value FSCL

(2 Rollovers of BRG)

10 MHz 20 MHz 18h 400 kHz(1)

10 MHz 20 MHz 1Fh 312.5 kHz

10 MHz 20 MHz 63h 100 kHz

4 MHz 8 MHz 09h 400 kHz(1)

4 MHz 8 MHz 0Ch 308 kHz

4 MHz 8 MHz 27h 100 kHz

1 MHz 2 MHz 02h 333 kHz(1)

1 MHz 2 MHz 09h 100 kHz

1 MHz 2 MHz 00h 1 MHz(1)

Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

PIC18F45J10 FAMILY

16.4.7.2 Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

deasserts the SCLx pin (SCLx allowed to float high).

When the SCLx pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCLx pin is actually sampled high. When the

SCLx pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPxADD<6:0> and

begins counting. This ensures that the SCLx high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 16-18).

FIGURE 16-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDAx

SCLx

SCLx deasserted but slave holds

DX – 1DX

BRG

SCLx is sampled high, reload takes

place and BRG starts its count

03h 02h 01h 00h (hold off) 03h 02h

Reload

BRG

Value

SCLx low (clock arbitration)

SCLx allowed to transition high

BRG decrements on

Q2 and Q4 cycles

PIC18F45J10 FAMILY

16.4.8 I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN (SSPxCON2<0>). If the SDAx and

SCLx pins are sampled high, the Baud Rate Generator

is reloaded with the contents of SSPxADD<6:0> and

starts its count. If SCLx and SDAx are both sampled

high when the Baud Rate Generator times out (TBRG),

the SDAx pin is driven low. The action of the SDAx

being driven low while SCLx is high is the Start condi-

tion and causes the S bit (SSPxSTAT<3>) to be set.

Following this, the Baud Rate Generator is reloaded

with the contents of SSPxADD<6:0> and resumes its

count. When the Baud Rate Generator times out

(TBRG), the SEN bit (SSPxCON2<0>) will be automati-

cally cleared by hardware. The Baud Rate Generator is

suspended, leaving the SDAx line held low and the

Start condition is complete.

16.4.8.1 WCOL Status Flag

If the user writes the SSPxBUF when a Start sequence

is in progress, the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

FIGURE 16-19: FIRST START BIT TIMING

Note: If, at the beginning of the Start condition,

the SDAx and SCLx pins are already sam-

pled low, or if during the Start condition, the

SCLx line is sampled low before the SDAx

line is driven low, a bus collision occurs.

The Bus Collision Interrupt Flag, BCLxIF,

is set, the Start condition is aborted and

the I2C module is reset into its Idle state.

Note: Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPxCON2 is disabled until the Start

condition is complete.

SDAx

SCLx

TBRG

1st bit 2nd bit

TBRG

SDAx = 1, At completion of Start bit,

SCLx = 1

Write to SSPxBUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here Set S bit (SSPxSTAT<3>)

and sets SSPxIF bit

PIC18F45J10 FAMILY

16.4.9 I2C MASTER MODE REPEATED

START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit

(SSPxCON2<1>) is programmed high and the I2C logic

module is in the Idle state. When the RSEN bit is set,

the SCLx pin is asserted low. When the SCLx pin is

sampled low, the Baud Rate Generator is loaded with

the contents of SSPxADD<6:0> and begins counting.

The SDAx pin is released (brought high) for one Baud

Rate Generator count (TBRG). When the Baud Rate

Generator times out, if SDAx is sampled high, the SCLx

pin will be deasserted (brought high). When SCLx is

sampled high, the Baud Rate Generator is reloaded

with the contents of SSPxADD<6:0> and begins count-

ing. SDAx and SCLx must be sampled high for one

TBRG. This action is then followed by assertion of the

SDAx pin (SDAx = 0) for one TBRG while SCLx is high.

Following this, the RSEN bit (SSPxCON2<1>) will be

automatically cleared and the Baud Rate Generator will

not be reloaded, leaving the SDAx pin held low. As

soon as a Start condition is detected on the SDAx and

SCLx pins, the S bit (SSPxSTAT<3>) will be set. The

SSPxIF bit will not be set until the Baud Rate Generator

has timed out.

Immediately following the SSPxIF bit getting set, the

user may write the SSPxBUF with the 7-bit address in

7-bit mode or the default first address in 10-bit mode.

After the first eight bits are transmitted and an ACK is

received, the user may then transmit an additional eight

bits of address (10-bit mode) or eight bits of data (7-bit

mode).

16.4.9.1 WCOL Status Flag

If the user writes the SSPxBUF when a Repeated Start

sequence is in progress, the WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 16-20: REPEATED START CONDITION WAVEFORM

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

condition occurs if:

• SDAx is sampled low when SCLx

goes from low-to-high.

• SCLx goes low before SDAx is

asserted low. This may indicate that

another master is attempting to

transmit a data ‘1’.

Note: Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPxCON2 is disabled until the Repeated

Start condition is complete.

SDAx

SCLx

Sr = Repeated Start

Write to SSPxCON2

Write to SSPxBUF occurs here

on falling edge of ninth clock,

end of Xmit

At completion of Start bit,

hardware clears RSEN bit

1st bit

S bit set by hardware

TBRG

SDAx = 1,

SCLx (no change)

SCLx = 1

occurs here:

TBRG TBRG

and sets SSPxIF

RSEN bit set by hardware

TBRG

PIC18F45J10 FAMILY

16.4.10 I2C MASTER MODE

TRANSMISSION

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPxBUF register. This action will

set the Buffer Full flag bit, BF, and allow the Baud Rate

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDAx pin after the falling edge of SCLx is

asserted (see data hold time specification

parameter 106). SCLx is held low for one Baud Rate

Generator rollover count (TBRG). Data should be valid

before SCLx is released high (see data setup time

specification parameter 107). When the SCLx pin is

released high, it is held that way for TBRG. The data on

the SDAx pin must remain stable for that duration and

some hold time after the next falling edge of SCLx.

After the eighth bit is shifted out (the falling edge of the

eighth clock), the BF flag is cleared and the master

releases SDAx. This allows the slave device being

addressed to respond with an ACK bit during the ninth

bit time if an address match occurred, or if data was

received properly. The status of ACK is written into the

ACKDT bit on the falling edge of the ninth clock. If the

master receives an Acknowledge, the Acknowledge

Status bit, ACKSTAT, is cleared; if not, the bit is set.

After the ninth clock, the SSPxIF bit is set and the

master clock (Baud Rate Generator) is suspended until

the next data byte is loaded into the SSPxBUF, leaving

SCLx low and SDAx unchanged (Figure 16-21).

After the write to the SSPxBUF, each bit of the address

will be shifted out on the falling edge of SCLx until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

deassert the SDAx pin, allowing the slave to respond

with an Acknowledge. On the falling edge of the ninth

clock, the master will sample the SDAx pin to see if the

address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT status bit

(SSPxCON2<6>). Following the falling edge of the

ninth clock transmission of the address, the SSPxIF is

set, the BF flag is cleared and the Baud Rate Generator

is turned off until another write to the SSPxBUF takes

place, holding SCLx low and allowing SDAx to float.

16.4.10.1 BF Status Flag

In Transmit mode, the BF bit (SSPxSTAT<0>) is set

when the CPU writes to SSPxBUF and is cleared when

all 8 bits are shifted out.

16.4.10.2 WCOL Status Flag

If the user writes to the SSPxBUF when a transmit is

already in progress (i.e., SSPxSR is still shifting out a

data byte), the WCOL is set and the contents of the buf-

fer are unchanged (the write doesn’t occur) after 2 TCY

after the SSPxBUF write. If SSPxBUF is rewritten

within 2 TCY, the WCOL bit is set and SSPxBUF is

updated. This may result in a corrupted transfer.

The user should verify that the WCOL is clear after

each write to SSPxBUF to ensure the transfer is

correct. In all cases, WCOL must be cleared in

software.

16.4.10.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit (SSPxCON2<6>)

is cleared when the slave has sent an Acknowledge

(ACK =0) and is set when the slave does not Acknowl-

edge (ACK = 1). A slave sends an Acknowledge when

it has recognized its address (including a general call),

or when the slave has properly received its data.

16.4.11 I2C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

Receive Enable bit, RCEN (SSPxCON2<3>).

The Baud Rate Generator begins counting, and on

each rollover, the state of the SCLx pin changes

(high-to-low/low-to-high) and data is shifted into the

SSPxSR. After the falling edge of the eighth clock, the

receive enable flag is automatically cleared, the con-

tents of the SSPxSR are loaded into the SSPxBUF, the

BF flag bit is set, the SSPxIF flag bit is set and the Baud

Rate Generator is suspended from counting, holding

SCLx low. The MSSP is now in Idle state awaiting the

next command. When the buffer is read by the CPU,

the BF flag bit is automatically cleared. The user can

then send an Acknowledge bit at the end of reception

by setting the Acknowledge Sequence Enable bit,

ACKEN (SSPxCON2<4>).

16.4.11.1 BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPxBUF from SSPxSR. It

is cleared when the SSPxBUF register is read.

16.4.11.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPxSR and the BF flag bit is

already set from a previous reception.

16.4.11.3 WCOL Status Flag

If the user writes the SSPxBUF when a receive is

already in progress (i.e., SSPxSR is still shifting in a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write doesn’t occur).

Note: The MSSP module must be in an Idle state

before the RCEN bit is set or the RCEN bit

will be disregarded.

PIC18F45J10 FAMILY

FIGURE 16-21 : I2C™ MASTER MODE WAVEFORM (T RANSMISSION, 7 OR 10-BIT ADDRESSING)

SDAx

SCLx

SSPxIF

BF (SSPxSTAT<0>)

SEN

A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0

ACK

Transmitting Data or Second Half

R/W = 0Transmit Address to Slave

123456789 123456789 P

Cleared in software service routine

SSPxBUF is written in software

from MSSP interrupt

After Start condition, SEN cleared by hardware

SSPxBUF written with 7-bit address and R/W

start transmit

SCLx held low

while CPU

responds to SSPxIF

SEN = 0

of 10-bit Address

Write SSPxCON2<0> (SEN = 1)

Start condition begins From slave, clear ACKSTAT bit (SSPxCON2<6>)

ACKSTAT in

SSPxCON2 = 1

Cleared in software

SSPxBUF written

PEN

R/W

Cleared in software

PIC18F45J10 FAMILY

FIGURE 16-22 : I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING)

D3D4

D6D7

A7 A6 A5 A4 A3 A2 A1

SDAx

SCLx 12

345678912345678 9 1234

Bus master

terminates

transfer

ACK

Receiving Data from Slave

D3D4

D6D7

ACK

R/W = 1

Transmit Address to Slave

SSPxIF

ACK is not sent

Write to SSPxCON2<0> (SEN = 1),

Write to SSPxBUF occurs here, ACK from Slave

Master configured as a receiver

by programming SSPxCON2<3> (RCEN = 1)

PEN bit = 1

written here

Data shifted in on falling edge of CLK

Cleared in software

start XMIT

SEN = 0

SSPOV

SDAx = 0, SCLx = 1

while CPU

(SSPxSTAT<0>)

ACK

Cleared in software

Set SSPxIF interrupt

at end of receive

Set P bit

(SSPxSTAT<4>)

and SSPxIF

ACK from Master,

Set SSPxIF at end

Set SSPxIF interrupt

at end of Acknowledge

sequence

Set SSPxIF interrupt

at end of Acknow-

ledge sequence

of receive

Set ACKEN, start Acknowledge sequence

SDAx = ACKDT = 1

RCEN cleared

automatically

RCEN = 1, start

next receive

Write to SSPxCON2<4>

to start Acknowledge sequence

SDAx = ACKDT (SSPxCON2<5>) = 0

RCEN cleared

automatically

ACKEN

begin Start condition

Cleared in software

SDAx = ACKDT = 0

Last bit is shifted into SSPxSR and

contents are unloaded into SSPxBUF

Cleared in

software

SSPOV is set because

SSPxBUF is still full

responds to SSPxIF

PIC18F45J10 FAMILY

16.4.12 ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN

(SSPxCON2<4>). When this bit is set, the SCLx pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDAx pin. If the user wishes to

generate an Acknowledge, then the ACKDT bit should

be cleared. If not, the user should set the ACKDT bit

before starting an Acknowledge sequence. The Baud

Rate Generator then counts for one rollover period

(TBRG) and the SCLx pin is deasserted (pulled high).

When the SCLx pin is sampled high (clock arbitration),

the Baud Rate Generator counts for TBRG. The SCLx pin

is then pulled low. Following this, the ACKEN bit is auto-

matically cleared, the Baud Rate Generator is turned off

and the MSSP module then goes into Idle mode

(Figure 16-23).

16.4.12.1 WCOL Status Flag

If the user writes the SSPxBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

16.4.13 STOP CONDITION TIMING

A Stop bit is asserted on the SDAx pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN (SSPxCON2<2>). At the end of a

receive/transmit, the SCLx line is held low after the fall-

ing edge of the ninth clock. When the PEN bit is set, the

master will assert the SDAx line low. When the SDAx

line is sampled low, the Baud Rate Generator is

reloaded and counts down to 0. When the Baud Rate

Generator times out, the SCLx pin will be brought high

and one TBRG (Baud Rate Generator rollover count)

later, the SDAx pin will be deasserted. When the SDAx

pin is sampled high while SCLx is high, the P bit

(SSPxSTAT<4>) is set. A TBRG later, the PEN bit is

cleared and the SSPxIF bit is set (Figure 16-24).

16.4.13.1 WCOL Status Flag

If the user writes the SSPxBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 16-23: ACKNOWLEDGE SEQUEN CE WAVEFORM

Note: TBRG = one Baud Rate Generator period.

SDAx

SCLx

SSPxIF set at

Acknowledge sequence starts here,

write to SSPxCON2 ACKEN automatically cleared

Cleared in

TBRG TBRG

the end of receive

ACKEN = 1, ACKDT = 0

SSPxIF

software SSPxIF set at the end

of Acknowledge sequence

Cleared in

software

ACK

PIC18F45J10 FAMILY

FIGURE 16-24: STOP CONDITION RECEIVE OR TRANSMIT MODE

16.4.14 SLEEP OPERATION

While in Sleep mode, the I2C module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

16.4.15 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

16.4.16 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I2C bus may

be taken when the P bit (SSPxSTAT<4>) is set, or the

bus is Idle, with both the S and P bits clear. When the

bus is busy, enabling the MSSP interrupt will generate

the interrupt when the Stop condition occurs.

In multi-master operation, the SDAx line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed in

hardware with the result placed in the BCLxIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An Acknowledge Condition

16.4.17 MULTI-MASTER COMMUNICATION,

BUS COLLISION AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDAx pin, arbitration takes place when the master

outputs a ‘1’ on SDAx, by letting SDAx float high, and

another master asserts a ‘0’. When the SCLx pin floats

high, data should be stable. If the expected data on

SDAx is a ‘1’ and the data sampled on the SDAx

pin = 0, then a bus collision has taken place. The

master will set the Bus Collision Interrupt Flag, BCLxIF

and reset the I2C port to its Idle state (Figure 16-25).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDAx and SCLx lines are deasserted and

the SSPxBUF can be written to. When the user services

the bus collision Interrupt Service Routine, and if the I2C

bus is free, the user can resume communication by

asserting a Start condition.

If a Start, Repeated Start, Stop or Acknowledge condition

was in progress when the bus collision occurred, the

condition is aborted, the SDAx and SCLx lines are deas-

serted and the respective control bits in the SSPxCON2

collision Interrupt Service Routine, and if the I2C bus is

free, the user can resume communication by asserting a

Start condition.

The master will continue to monitor the SDAx and SCLx

pins. If a Stop condition occurs, the SSPxIF bit will be set.

A write to the SSPxBUF will start the transmission of

data at the first data bit regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the determi-

nation of when the bus is free. Control of the I2C bus can

be taken when the P bit is set in the SSPxSTAT register,

or the bus is Idle and the S and P bits are cleared.

SCLx

SDAx

SDAx asserted low before rising edge of clock

Write to SSPxCON2,

set PEN

Falling edge of

SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG

9th clock

SCLx brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG TBRG

after SDAx sampled high. P bit (SSPxSTAT<4>) is set.

TBRG

to set up Stop condition

ACK

TBRG

PEN bit (SSPxCON2<2>) is cleared by

hardware and the SSPxIF bit is set

PIC18F45J10 FAMILY

FIGURE 16-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDAx

SCLx

BCLxIF

SDAx released

SDAx line pulled low

by another source

Sample SDAx. While SCLx is high,

data doesn’t match what is driven

Bus collision has occurred.

Set bus collision

interrupt (BCLxIF)

by the master.

by master

Data changes

while SCLx = 0

PIC18F45J10 FAMILY

16.4.17.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDAx or SCLx are sampled low at the beginning

of the Start condition (Figure 16-26).

b) SCLx is sampled low before SDAx is asserted

low (Figure 16-27).

During a Start condition, both the SDAx and the SCLx

pins are monitored.

If the SDAx pin is already low, or the SCLx pin is

already low, then all of the following occur:

• the Start condition is aborted;

• the BCLxIF flag is set; and

• the MSSP module is reset to its Idle state

(Figure 16-26).

The Start condition begins with the SDAx and SCLx

pins deasserted. When the SDAx pin is sampled high,

the Baud Rate Generator is loaded from

SSPxADD<6:0> and counts down to ‘0’. If the SCLx pin

is sampled low while SDAx is high, a bus collision

occurs, because it is assumed that another master is

attempting to drive a data ‘1’ during the Start condition.

If the SDAx pin is sampled low during this count, the

BRG is reset and the SDAx line is asserted early

(Figure 16-28). If, however, a ‘1’ is sampled on the

SDAx pin, the SDAx pin is asserted low at the end of

the BRG count. The Baud Rate Generator is then

reloaded and counts down to 0. If the SCLx pin is

sampled as ‘0’ during this time, a bus collision does not

occur. At the end of the BRG count, the SCLx pin is

asserted low.

FIGURE 16-26: BUS COLLISION DURING START CONDITION (SDAx ONLY)

Note: The reason that bus collision is not a factor

during a Start condition is that no two bus

masters can assert a Start condition at the

exact same time. Therefore, one master

will always assert SDAx before the other.

This condition does not cause a bus colli-

sion because the two masters must be

allowed to arbitrate the first address

following the Start condition. If the address

is the same, arbitration must be allowed to

continue into the data portion, Repeated

Start or Stop conditions.

SDAx

SCLx

SEN

SDAx sampled low before

SDAx goes low before the SEN bit is set.

S bit and SSPxIF set because

MSSP module reset into Idle state.

SEN cleared automatically because of bus collision.

S bit and SSPxIF set because

Set SEN, enable Start

condition if SDAx = 1, SCLx = 1

SDAx = 0, SCLx = 1.

BCLxIF

SSPxIF

SDAx = 0, SCLx = 1.

SSPxIF and BCLxIF are

cleared in software

SSPxIF and BCLxIF are

cleared in software

Set BCLxIF,

Start condition. Set BCLxIF.

PIC18F45J10 FAMILY

FIGURE 16-27: BUS COLLISION DURING START CONDITION (SCLx = 0)

FIGURE 16-28: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION

SDAx

SCLx

SEN bus collision occurs. Set BCLxIF.

SCLx = 0 before SDAx = 0,

Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1

TBRG TBRG

SDAx = 0, SCLx = 1

BCLxIF

SSPxIF

Interrupt cleared

in software

bus collision occurs. Set BCLxIF.

SCLx = 0 before BRG time-out,

‘0’‘0’

SDAx

SCLx

SEN

Set S

Less than TBRG TBRG

SDAx = 0, SCLx = 1

BCLxIF

SSPxIF

Interrupts cleared

in software

set SSPxIF

SDAx = 0, SCLx = 1,

SCLx pulled low after BRG

time-out

Set SSPxIF

‘0’

SDAx pulled low by other master.

Reset BRG and assert SDAx.

Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1

PIC18F45J10 FAMILY

16.4.17.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDAx when SCLx

goes from low level to high level.

b) SCLx goes low before SDAx is asserted low,

indicating that another master is attempting to

transmit a data ‘1’.

When the user deasserts SDAx and the pin is allowed

to float high, the BRG is loaded with SSPxADD<6:0>

and counts down to 0. The SCLx pin is then deasserted

and when sampled high, the SDAx pin is sampled.

If SDAx is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, see

Figure 16-29). If SDAx is sampled high, the BRG is

reloaded and begins counting. If SDAx goes from

high-to-low before the BRG times out, no bus collision

occurs because no two masters can assert SDAx at

exactly the same time.

If SCLx goes from high-to-low before the BRG times

out and SDAx has not already been asserted, a bus

collision occurs. In this case, another master is

attempting to transmit a data ‘1’ during the Repeated

Start condition (see Figure 16-30).

If, at the end of the BRG time-out, both SCLx and SDAx

are still high, the SDAx pin is driven low and the BRG

is reloaded and begins counting. At the end of the

count, regardless of the status of the SCLx pin, the

SCLx pin is driven low and the Repeated Start

condition is complete.

FIGURE 16-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

FIGURE 16-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

SDAx

SCLx

RSEN

BCLxIF

SSPxIF

Sample SDAx when SCLx goes high.

If SDAx = 0, set BCLxIF and release SDAx and SCLx.

Cleared in software

‘0’

SDAx

SCLx

BCLxIF

RSEN

SSPxIF

Interrupt cleared

in software

SCLx goes low before SDAx,

set BCLxIF. Release SDAx and SCLx.

TBRG TBRG

‘0’

PIC18F45J10 FAMILY

16.4.17.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDAx pin has been deasserted and

allowed to float high, SDAx is sampled low after

the BRG has timed out.

b) After the SCLx pin is deasserted, SCLx is

sampled low before SDAx goes high.

The Stop condition begins with SDAx asserted low.

When SDAx is sampled low, the SCLx pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with

SSPxADD<6:0> and counts down to 0. After the BRG

times out, SDAx is sampled. If SDAx is sampled low, a

bus collision has occurred. This is due to another

master attempting to drive a data ‘0’ (Figure 16-31). If

the SCLx pin is sampled low before SDAx is allowed to

float high, a bus collision occurs. This is another case

of another master attempting to drive a data ‘0’

(Figure 16-32).

FIGURE 16-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)

FIGURE 16-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)

SDAx

SCLx

BCLxIF

PEN

SSPxIF

TBRG TBRG TBRG

SDAx asserted low

SDAx sampled

low after TBRG,

set BCLxIF

‘0’

SDAx

SCLx

BCLxIF

PEN

SSPxIF

TBRG TBRG TBRG

Assert SDAx SCLx goes low before SDAx goes high,

set BCLxIF

‘0’

PIC18F45J10 FAMILY

TABLE 16-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on Pag e

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

PIR2 OSCFIF CMIF —— BCL1IF — — CCP2IF 49

PIE2 OSCFIE CMIE —— BCL1IE — — CCP2IE 49

IPR2 OSCFIP CMIP —— BCL1IP — — CCP2IP 49

PIR3 SSP2IF BCL2IF ——————49

PIE3 SSP2IE BCL2IE ——————49

IPR3 SSP2IP BCL2IP ——————49

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 50

TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 50

SSP1BUF MSSP1 Receive Buffer/Transmit Register 48

SSP1ADD MSSP1 Address Register (I2C™ Slave mode).

MSSP1 Baud Rate Reload Register (I2C Master mode).

SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 48

SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 48

GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN 48

SSP1STAT SMP CKE D/A PSR/WUA BF 48

SSP2BUF MSSP2 Receive Buffer/Transmit Register 50

SSP2ADD MSSP2 Address Register (I2C Slave mode).

MSSP2 Baud Rate Reload Register (I2C Master mode).

SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50

SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 50

GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN 48

SSP2STAT SMP CKE D/A PSR/WUA BF 50

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.

Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.

2: Alternate names and definitions for these bits when the MSSP module is operating in I2C Slave mode. See

Section 16.4.3.2 “Address Masking” for details.

PIC18F45J10 FAMILY

17.0 ENHANCED UNIVER S A L

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is one of the

two serial I/O modules. (Generically, the USART is also

known as a Serial Communications Interface or SCI.)

The EUSART can be configured as a full-duplex,

asynchronous system that can communicate with

peripheral devices, such as CRT terminals and

personal computers. It can also be configured as a half-

duplex synchronous system that can communicate

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs, etc.

The Enhanced USART module implements additional

features, including automatic baud rate detection and

calibration, automatic wake-up on Sync Break recep-

tion and 12-bit Break character transmit. These make it

ideally suited for use in Local Interconnect Network

(LIN/J2602) bus systems.

The EUSART can be configured in the following

modes:

• Asynchronous (full duplex) with:

- Auto-wake-up on character reception

- Auto-baud calibration

- 12-bit Break character transmission

• Synchronous – Master (half duplex) with

selectable clock polarity

• Synchronous – Slave (half duplex) with selectable

clock polarity

The pins of the Enhanced USART are multiplexed

with PORTC. In order to configure RC6/TX/CK and

RC7/RX/DT as an EUSART:

• bit SPEN (RCSTA<7>) must be set (= 1)

• bit TRISC<7> must be set (= 1)

• bit TRISC<6> must be set (= 1)

The operation of the Enhanced USART module is

controlled through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

These are detailed on the following pages in

respectively.

Note: The EUSART control will automatically

reconfigure the pin from input to output as

needed.

PIC18F45J10 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care.

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

bit 6 TX9: 9-Bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: EUSART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 SENDB: Send Break Character bit

Asynchronous mode:

1 = Send Sync Break on next transmission (cleared by hardware upon completion)

0 = Sync Break transmission completed

Synchronous mode:

Don’t care.

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode:

Unused in this mode.

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: 9th Bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC18F45J10 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0 = Serial port disabled (held in Reset)

bit 6 RX9: 9-Bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care.

Synchronous mode – Master:

1 = Enables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave:

Don’t care.

bit 4 CREN: Continuous Receive Enable bit

Asynchronous mode:

1 = Enables receiver

0 = Disables receiver

Synchronous mode:

1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set

0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 9-bit (RX9 = 0):

Don’t care.

bit 2 FERR: Framing Error bit

1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit, CREN)

0 = No overrun error

bit 0 RX9D: 9th Bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC18F45J10 FAMILY

R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit

1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)

0 = No BRG rollover has occurred

bit 6 RCIDL: Receive Operation Idle Status bit

1 = Receive operation is Idle

0 = Receive operation is active

bit 5 Unimplemented: Read as ‘0’

bit 4 SCKP: Synchronous Clock Polarity Select bit

Asynchronous mode:

Unused in this mode.

Synchronous mode:

1 = Idle state for clock (CK) is a high level

0 = Idle state for clock (CK) is a low level

bit 3 BRG16: 16-Bit Baud Rate Register Enable bit

1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG

0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored

bit 2 Unimplemented: Read as ‘0’

bit 1 WUE: Wake-up Enable bit

Asynchronous mode:

1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in

hardware on following rising edge

0 = RX pin not monitored or rising edge detected

Synchronous mode:

Unused in this mode.

bit 0 ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);

cleared in hardware upon completion.

0 = Baud rate measurement disabled or completed

Synchronous mode:

Unused in this mode.

PIC18F45J10 FAMILY

17.1 Baud Rate Generator (BRG)

The BRG is a dedicated 8-bit or 16-bit generator that

supports both the Asynchronous and Synchronous

modes of the EUSART. By default, the BRG operates

in 8-bit mode; setting the BRG16 bit (BAUDCON<3>)

selects 16-bit mode.

The SPBRGH:SPBRG register pair controls the period

of a free-running timer. In Asynchronous mode, bits,

BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>), also

control the baud rate. In Synchronous mode, BRGH is

ignored. Table 17-1 shows the formula for computation

of the baud rate for different EUSART modes which

only apply in Master mode (internally generated clock).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRGH:SPBRG registers can be

calculated using the formulas in Table 17-1. From this,

the error in baud rate can be determined. An example

calculation is shown in Example 17-1. Typical baud

rates and error values for the various Asynchronous

modes are shown in Table 17-2. It may be

advantageous to use the high baud rate (BRGH = 1) or

the 16-bit BRG to reduce the baud rate error, or

achieve a slow baud rate for a fast oscillator frequency.

Writing a new value to the SPBRGH:SPBRG registers

causes the BRG timer to be reset (or cleared). This

ensures the BRG does not wait for a timer overflow

before outputting the new baud rate.

17.1.1 OPERATION IN POWER-MANAGED

MODES

The device clock is used to generate the desired baud

rate. When one of the power-managed modes is

entered, the new clock source may be operating at a

different frequency. This may require an adjustment to

the value in the SPBRG register pair.

17.1.2 SAMPLING

The data on the RX pin is sampled three times by a

majority detect circuit to determine if a high or a low

level is present at the RX pin.

TABLE 17-1: BAUD RATE FORMULAS

Configuration Bits BRG/EUSART Mode Baud Rate Formula

SYNC BRG16 BRGH

000 8-bit/Asynchronous FOSC/[64 (n + 1)]

001 8-bit/Asynchronous FOSC/[16 (n + 1)]

010 16-bit/Asynchronous

011 16-bit/Asynchronous

FOSC/[4 (n + 1)]10x 8-bit/Synchronous

11x 16-bit/Synchronous

Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair

PIC18F45J10 FAMILY

EXAMPLE 17-1: CALCULATING BAUD RATE ERROR

TABLE 17-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset V alues

on page

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49

BAUDCON ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 49

SPBRGH EUSART Baud Rate Generator Register High Byte 49

SPBRG EUSART Baud Rate Generator Register Low Byte 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

For a device wit h FOSC of 16 MHz, desire d baud rate of 960 0, Asynchronous mode, 8-b it BRG:

Desired B aud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1))

Solving for SPBRGH:SPBRG:

X=((FOSC/Desired Baud Rate)/64) – 1

= ((16000000/9600)/64) – 1

= [25.042] = 25

Calcu lated Baud Rate = 16000000/(64 (25 + 1))

= 9615

Error = (Calculated Baud Rate – Desired Baud Rate ) /D esired Baud Rate

= (9615 – 9600)/9600 = 0.16%

PIC18F45J10 FAMILY

TABLE 17-3: BAUD RATES FOR ASYNCHRONOUS MODES

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3————————————

1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103

2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51

9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12

19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —

57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —

115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51

1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12

2.4 2.404 0.16 25 2.403 -0.16 12 — — —

9.6 8.929 -6.99 6 — — — — — —

19.2 20.833 8.51 2 — — — — — —

57.6 62.500 8.51 0 — — — — — —

115.2 62.500 -45.75 0 — — — — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3————————————

1.2————————————

2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207

9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51

19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25

57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8

115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 — — — — — — 0.300 -0.16 207

1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51

2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25

9.6 9.615 0.16 25 9.615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —

PIC18F45J10 FAMILY

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665

1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415

2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207

9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51

19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25

57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8

115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207

1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51

2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25

9.6 9.615 0.16 25 9.615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665

1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665

2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832

9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207

19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103

57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34

115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832

1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207

2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103

9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25

19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12

57.6 58.824 2.12 16 55.555 3.55 8 — — —

115.2 111.111 -3.55 8 — — — — — —

TABLE 17-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

PIC18F45J10 FAMILY

17.1.3 AUTO-BAUD RATE DETECT

The Enhanced USART module supports the automatic

detection and calibration of baud rate. This feature is

active only in Asynchronous mode and while the WUE

bit is clear.

The automatic baud rate measurement sequence

(Figure 17-1) begins whenever a Start bit is received

and the ABDEN bit is set. The calculation is

self-averaging.

In the Auto-Baud Rate Detect (ABD) mode, the clock to

the BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG. In

ABD mode, the internal Baud Rate Generator is used

as a counter to time the bit period of the incoming serial

byte stream.

Once the ABDEN bit is set, the state machine will clear

the BRG and look for a Start bit. The Auto-Baud Rate

Detect must receive a byte with the value 55h (ASCII

“U”, which is also the LIN/J2602 bus Sync character) in

order to calculate the proper bit rate. The measurement

is taken over both a low and a high bit time in order to

minimize any effects caused by asymmetry of the incom-

ing signal. After a Start bit, the SPBRG begins counting

up, using the preselected clock source on the first rising

edge of RX. After eight bits on the RX pin or the fifth ris-

ing edge, an accumulated value totalling the proper BRG

period is left in the SPBRGH:SPBRG register pair. Once

the 5th edge is seen (this should correspond to the Stop

bit), the ABDEN bit is automatically cleared.

If a rollover of the BRG occurs (an overflow from FFFFh

to 0000h), the event is trapped by the ABDOVF status

bit (BAUDCON<7>). It is set in hardware by BRG roll-

overs and can be set or cleared by the user in software.

ABD mode remains active after rollover events and the

ABDEN bit remains set (Figure 17-2).

While calibrating the baud rate period, the BRG regis-

ters are clocked at 1/8th the preconfigured clock rate.

Note that the BRG clock will be configured by the

BRG16 and BRGH bits. Independent of the BRG16 bit

setting, both the SPBRG and SPBRGH will be used as

a 16-bit counter. This allows the user to verify that no

carry occurred for 8-bit modes by checking for 00h in

the SPBRGH register. Refer to Table 17-4 for counter

clock rates to the BRG.

While the ABD sequence takes place, the EUSART

state machine is held in Idle. The RCIF interrupt is set

once the fifth rising edge on RX is detected. The value

in the RCREG needs to be read to clear the RCIF

interrupt. The contents of RCREG should be discarded.

TABLE 17-4: BRG COUNTER

CLOCK RATES

17.1.3.1 ABD and EUSART Transmission

Since the BRG clock is reversed during ABD acquisi-

tion, the EUSART transmitter cannot be used during

ABD. This means that whenever the ABDEN bit is set,

TXREG cannot be written to. Users should also ensure

that ABDEN does not become set during a transmit

sequence. Failing to do this may result in unpredictable

EUSART operation.

Note 1: If the WUE bit is set with the ABDEN bit,

Auto-Baud Rate Detection will occur on

the byte following the Break character.

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible

due to bit error rates. Overall system tim-

ing and communication baud rates must

be taken into consideration when using the

Auto-Baud Rate Detection feature.

BRG16 BRGH BRG Counter Clock

00 FOSC/512

01 FOSC/128

10 FOSC/128

11 FOSC/32

Note: During the ABD sequence, SPBRG and

SPBRGH are both used as a 16-bit counter,

independent of BRG16 setting.

PIC18F45J10 FAMILY

FIGURE 17-1: AUTOMATIC BAUD RATE CALCULATION

FIGURE 17-2: BRG OVERFLOW SEQUENCE

BRG Value

RX pin

ABDEN bit

RCIF bit

Bit 0 Bit 1

(Interrupt)

Read

RCREG

BRG Clock

Start

Auto-Cleared

Set by User

XXXXh 0000h

Edge #1

Bit 2 Bit 3

Edge #2

Bit 4 Bit 5

Edge #3

Bit 6 Bit 7

Edge #4

Stop Bit

Edge #5

001Ch

Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.

SPBRG XXXXh 1Ch

SPBRGH XXXXh 00h

Start Bit 0

XXXXh 0000h 0000h

FFFFh

BRG Clock

ABDEN bit

RX pin

ABDOVF bit

BRG Value

PIC18F45J10 FAMILY

17.2 EUSART Asynchronous Mode

The Asynchronous mode of operation is selected by

clearing the SYNC bit (TXSTA<4>). In this mode, the

EUSART uses standard Non-Return-to-Zero (NRZ) for-

mat (one Start bit, eight or nine data bits and one Stop

bit). The most common data format is 8 bits. An on-chip,

dedicated 8-bit/16-bit Baud Rate Generator can be used

to derive standard baud rate frequencies from the

oscillator.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent but use the same data format and baud

rate. The Baud Rate Generator produces a clock, either

x16 or x64 of the bit shift rate depending on the BRGH

and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity

is not supported by the hardware but can be

implemented in software and stored as the 9th data bit.

When operating in Asynchronous mode, the EUSART

module consists of the following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

• Auto-Wake-up on Sync Break Character

• 12-Bit Break Character Transmit

• Auto-Baud Rate Detection

17.2.1 EUSART ASYNCHRONOUS

TRANSMITTER

The EUSART transmitter block diagram is shown in

Figure 17-3. The heart of the transmitter is the Transmit

(Serial) Shift Register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the Stop

bit has been transmitted from the previous load. As

soon as the Stop bit is transmitted, the TSR is loaded

with new data from the TXREG register (if available).

Once the TXREG register transfers the data to the TSR

CY), the TXREG register is empty

and the TXIF flag bit (PIR1<4>) is set. This interrupt can

be enabled or disabled by setting or clearing the interrupt

enable bit, TXIE (PIE1<4>). TXIF will be set regardless of

the state of TXIE; it cannot be cleared in software. TXIF

is also not cleared immediately upon loading TXREG, but

becomes valid in the second instruction cycle following

the load instruction. Polling TXIF immediately following a

load of TXREG will return invalid results.

While TXIF indicates the status of the TXREG register,

another bit, TRMT (TXSTA<1>), shows the status of

the TSR register. TRMT is a read-only bit which is set

when the TSR register is empty. No interrupt logic is

tied to this bit so the user has to poll this bit in order to

determine if the TSR register is empty.

To set up an Asynchronous Transmission:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

2. Enable the asynchronous serial port by clearing

bit, SYNC, and setting bit, SPEN.

3. If interrupts are desired, set enable bit, TXIE.

4. If 9-bit transmission is desired, set transmit bit,

TX9. Can be used as address/data bit.

5. Enable the transmission by setting bit, TXEN,

which will also set bit, TXIF.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

7. Load data to the TXREG register (starts

transmission).

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 17-3: EUS ART TRANSMIT BLOCK DIAGRAM

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set.

TXIF

TXIE

Interrupt

TXEN Baud Rate CLK

SPBRG

Baud Rate Generator TX9D

MSb LSb

Data Bus

TXREG Register

TSR Register

(8) 0

TX9

TRMT SPEN

TX pin

Pin Buffer

and Control

• • •

SPBRGH

BRG16

PIC18F45J10 FAMILY

FIGURE 17-4: ASYNCHRONOUS TRANSMISSION

FIGURE 17-5: ASYNCHRON OUS TRANSMISSION (BACK TO BACK)

TABLE 17-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49

TXREG EUSART Transmit Register 49

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49

BAUDCON ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 49

SPBRGH EUSART Baud Rate Generator Register High Byte 49

SPBRG EUSART Baud Rate Generator Register Low Byte 49

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

Word 1

Transmit Shift Reg

Start bit bit 0 bit 1 bit 7/8

Write to TXREG

BRG Output

(Shift Clock)

TX (pin)

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

1 TCY

Stop bit

Word 1

Transmit Shift Reg.

Write to TXREG

BRG Output

(Shift Clock)

TX (pin)

TXIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1 Word 2

Stop bit Start bit

Transmit Shift Reg.

Word 1 Word 2

bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram shows two consecutive transmissions.

1 TCY

Start bit

PIC18F45J10 FAMILY

17.2.2 EUSART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 17-6.

The data is received on the RX pin and drives the data

recovery block. The data recovery block is actually a

high-speed shifter operating at x16 times the baud rate,

whereas the main receive serial shifter operates at the

bit rate or at FOSC. This mode would typically be used

in RS-232 systems.

To set up an Asynchronous Reception:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

2. Enable the asynchronous serial port by clearing

bit, SYNC, and setting bit, SPEN.

3. If interrupts are desired, set enable bit, RCIE.

4. If 9-bit reception is desired, set bit, RX9.

5. Enable the reception by setting bit, CREN.

6. Flag bit, RCIF, will be set when reception is

complete and an interrupt will be generated if

enable bit, RCIE, was set.

7. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

8. Read the 8-bit received data by reading the

RCREG register.

9. If any error occurred, clear the error by clearing

enable bit, CREN.

10. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

17.2.3 SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If interrupts are required, set the RCEN bit and

select the desired priority level with the RCIP bit.

4. Set the RX9 bit to enable 9-bit reception.

5. Set the ADDEN bit to enable address detect.

6. Enable reception by setting the CREN bit.

7. The RCIF bit will be set when reception is

complete. The interrupt will be Acknowledged if

the RCIE and GIE bits are set.

8. Read the RCSTA register to determine if any

error occurred during reception, as well as read

bit 9 of data (if applicable).

9. Read RCREG to determine if the device is being

addressed.

10. If any error occurred, clear the CREN bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

FIGURE 17-6: EUS ART R ECE IVE BLOCK DIAGRAM

x64 Baud Rate CLK

Baud Rate Generator

Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR FERR

RSR Register

MSb LSb

RX9D RCREG Register

FIFO

Interrupt RCIF

RCIE

Data Bus

÷ 64

÷ 16

Stop Start

(8) 7 1 0

RX9

• • •

SPBRGSPBRGH

BRG16

÷ 4

PIC18F45J10 FAMILY

FIGURE 17-7: ASYNCHRONOUS RECEPTION

TABLE 17-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

17.2.4 AUTO-WAKE-UP ON SYNC BREAK

CHARACTER

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper byte reception cannot be per-

formed. The auto-wake-up feature allows the controller

to wake-up due to activity on the RX/DT line while the

EUSART is operating in Asynchronous mode.

The auto-wake-up feature is enabled by setting the

WUE bit (BAUDCON<1>). Once set, the typical receive

sequence on RX/DT is disabled and the EUSART

remains in an Idle state, monitoring for a wake-up event

independent of the CPU mode. A wake-up event con-

sists of a high-to-low transition on the RX/DT line. (This

coincides with the start of a Sync Break or a Wake-up

Signal character for the LIN/J2602 support protocol.)

Following a wake-up event, the module generates an

RCIF interrupt. The interrupt is generated synchro-

nously to the Q clocks in normal operating modes

(Figure 17-8) and asynchronously, if the device is in

Sleep mode (Figure 17-9). The interrupt condition is

cleared by reading the RCREG register.

The WUE bit is automatically cleared once a low-to-

high transition is observed on the RX line following the

wake-up event. At this point, the EUSART module is in

Idle mode and returns to normal operation. This signals

to the user that the Sync Break event is over.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49

RCREG EUSART Receive Register 49

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49

BAUDCON ABDOVF RCIDL —SCKP BRG16 — WUE ABDEN 49

SPBRGH EUSART Baud Rate Generator Register High Byte 49

SPBRG EUSART Baud Rate Generator Register Low Byte 49

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

Start

bit bit 7/8

bit 1bit 0 bit 7/8 bit 0

Stop

bit

Start

bit

Start

bit

bit 7/8 Stop

bit

RX (pin)

Rcv Buffer Reg

Rcv Shift Reg

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG

Word 2

RCREG

Stop

bit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing

the OERR (Overrun) bit to be set.

PIC18F45J10 FAMILY

17.2.4.1 Special Considerations Using

Auto-Wake-up

Since auto-wake-up functions by sensing rising edge

transitions on RX/DT, information with any state

changes before the Stop bit may signal a false End-Of-

Character (EOC) and cause data or framing errors. To

work properly, therefore, the initial character in the

transmission must be all ‘0’s. This can be 00h (8 bytes)

for standard RS-232 devices or 000h (12 bits) for LIN

bus.

Oscillator start-up time must also be considered,

especially in applications using oscillators with longer

start-up intervals (i.e., HS mode). The Sync Break (or

Wake-up Signal) character must be of sufficient length

and be followed by a sufficient interval to allow enough

time for the selected oscillator to start and provide

proper initialization of the EUSART.

17.2.4.2 Special Considerations Using

the WUE Bit

The timing of WUE and RCIF events may cause some

confusion when it comes to determining the validity of

received data. As noted, setting the WUE bit places the

EUSART in an Idle mode. The wake-up event causes a

receive interrupt by setting the RCIF bit. The WUE bit is

cleared after this when a rising edge is seen on RX/DT.

The interrupt condition is then cleared by reading the

RCREG register. Ordinarily, the data in RCREG will be

dummy data and should be discarded.

The fact that the WUE bit has been cleared (or is still

set) and the RCIF flag is set should not be used as an

indicator of the integrity of the data in RCREG. Users

should consider implementing a parallel method in

firmware to verify received data integrity.

To assure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process. If

a receive operation is not occurring, the WUE bit may

then be set just prior to entering the Sleep mode.

FIGURE 17-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION

FIGURE 17-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit(1)

RX/DT Line

RCIF

Note 1: The EUSART remains in Idle while the WUE bit is set.

Bit set by user

Cleared due to user read of RCREG

Auto-Cleared

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit(2)

RX/DT Line

RCIF

Bit set by user

Cleared due to user read of RCREG

Sleep Command Executed

Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This

sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

Sleep Ends

Note 1

Auto-Cleared

PIC18F45J10 FAMILY

17.2.5 BREAK CHARACTER SEQUENCE

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN/J2602 support standard. The Break character

transmit consists of a Start bit, followed by twelve ‘0’

bits and a Stop bit. The frame Break character is sent

whenever the SENDB and TXEN bits (TXSTA<3> and

TXSTA<5>) are set while the Transmit Shift register is

loaded with data. Note that the value of data written to

TXREG will be ignored and all ‘0’s will be transmitted.

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN/J2602 support).

Note that the data value written to the TXREG for the

Break character is ignored. The write simply serves the

purpose of initiating the proper sequence.

The TRMT bit indicates when the transmit operation is

active or Idle, just as it does during normal transmis-

sion. See Figure 17-10 for the timing of the Break

character sequence.

17.2.5.1 Break and Sync Transmit Sequence

The following sequence will send a message frame

header made up of a Break, followed by an Auto-Baud

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to set up the

Break character.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware. The Sync character now

transmits in the preconfigured mode.

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

17.2.6 RECEIVING A BREAK CHARACTER

The Enhanced USART module can receive a Break

character in two ways.

The first method forces configuration of the baud rate

at a frequency of 9/13 the typical speed. This allows for

the Stop bit transition to be at the correct sampling loca-

tion (13 bits for Break versus Start bit and 8 data bits for

typical data).

The second method uses the auto-wake-up feature

described in Section 17.2.4 “Auto-Wake-up on Sync

Break Character”. By enabling this feature, the

EUSART will sample the next two transitions on RX/DT,

cause an RCIF interrupt and receive the next data byte

followed by another interrupt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Rate Detect

feature. For both methods, the user can set the ABD bit

once the TXIF interrupt is observed.

FIGURE 17-10: SEND BREAK CHARACTER SEQUENCE

Write to TXREG

BRG Output

(Shift Clock)

Start Bit Bit 0 Bit 1 Bit 11 Stop Bit

Break

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TX (pin)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB

(Transmit Shift

Reg. Empty Flag)

SENDB sampled here Auto-Cleared

Dummy Write

PIC18F45J10 FAMILY

17.3 EUSART Synchronous

Master Mode

The Synchronous Master mode is entered by setting

the CSRC bit (TXSTA<7>). In this mode, the data is

transmitted in a half-duplex manner (i.e., transmission

and reception do not occur at the same time). When

transmitting data, the reception is inhibited and vice

versa. Synchronous mode is entered by setting bit

SYNC (TXSTA<4>). In addition, enable bit SPEN

(RCSTA<7>) is set in order to configure the TX and RX

pins to CK (clock) and DT (data) lines, respectively.

The Master mode indicates that the processor trans-

mits the master clock on the CK line. Clock polarity is

selected with the SCKP bit (BAUDCON<4>). Setting

SCKP sets the Idle state on CK as high, while clearing

the bit sets the Idle state as low. This option is provided

to support Microwire devices with this module.

17.3.1 EUSART SYNCHRONOUS MASTER

TRANSMISSION

The EUSART transmitter block diagram is shown in

Figure 17-3. The heart of the transmitter is the Transmit

(Serial) Shift Register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available).

Once the TXREG register transfers the data to the TSR

the TXIF flag bit (PIR1<4>) is set. The interrupt can be

enabled or disabled by setting or clearing the interrupt

enable bit, TXIE (PIE1<4>). TXIF is set regardless of

the state of enable bit TXIE; it cannot be cleared in

software. It will reset only when new data is loaded into

the TXREG register.

While flag bit TXIF indicates the status of the TXREG

status of the TSR register. TRMT is a read-only bit which

is set when the TSR is empty. No interrupt logic is tied to

this bit so the user has to poll this bit in order to deter-

mine if the TSR register is empty. The TSR is not

mapped in data memory so it is not available to the user.

To set up a Synchronous Master Transmission:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRG16

bit, as required, to achieve the desired baud rate.

2. Enable the synchronous master serial port by

setting bits, SYNC, SPEN and CSRC.

3. If interrupts are desired, set enable bit, TXIE.

4. If 9-bit transmission is desired, set bit, TX9.

5. Enable the transmission by setting bit, TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

7. Start transmission by loading data to the TXREG

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 17-11: SYNCHRONOUS TRANSMISSION

bit 0 bit 1 bit 7

Word 1

Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

bit 2 bit 0 bit 1 bit 7

RC7/RX/DT

RC6/TX/CK pin

Write to

TXREG Reg

TXIF bit

(Interrupt Flag)

TXEN bit ‘1’ ‘1’

Word 2

TRMT bit

Write Word 1 Write Word 2

Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

RC6/TX/CK pin

(SCKP = 0)

(SCKP = 1)

PIC18F45J10 FAMILY

FIGURE 17-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

TABLE 17-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49

TXREG EUSART Transmit Register 49

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49

BAUDCON ABDOVF RCIDL —SCKPBRG16—WUE ABDEN 49

SPBRGH EUSART Baud Rate Generator Register High Byte 49

SPBRG EUSART Baud Rate Generator Register Low Byte 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

RC7/RX/DT pin

RC6/TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

bit 0 bit 1 bit 2 bit 6 bit 7

TXEN bit

PIC18F45J10 FAMILY

17.3.2 EUSART SYNCHRONOUS

MASTER RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either the Single Receive Enable bit,

SREN (RCSTA<5>), or the Continuous Receive

Enable bit, CREN (RCSTA<4>). Data is sampled on the

RX pin on the falling edge of the clock.

If enable bit SREN is set, only a single word is received.

If enable bit CREN is set, the reception is continuous

until CREN is cleared. If both bits are set, then CREN

takes precedence.

To set up a Synchronous Master Reception:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRG16

bit, as required, to achieve the desired baud rate.

2. Enable the synchronous master serial port by

setting bits, SYNC, SPEN and CSRC.

3. Ensure bits, CREN and SREN, are clear.

4. If interrupts are desired, set enable bit, RCIE.

5. If 9-bit reception is desired, set bit, RX9.

6. If a single reception is required, set bit, SREN.

For continuous reception, set bit, CREN.

7. Interrupt flag bit, RCIF, will be set when reception

is complete and an interrupt will be generated if

the enable bit, RCIE, was set.

8. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

bit, CREN.

11. If using interrupts, ensure that the GIE and PEIE bits

in the INTCON register (INTCON<7:6>) are set.

FIGURE 17-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

TABLE 17-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49

RCREG EUSART Receive Register 49

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49

BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 49

SPBRGH EUSART Baud Rate Generator Register High Byte 49

SPBRG EUSART Baud Rate Generator Register Low Byte 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

CREN bit

RC7/RX/DT

RC6/TX/CK pin

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

‘

’

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

‘

’

Q1 Q2 Q3 Q4

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

RC6/TX/CK pin

(SCKP = 0)

(SCKP = 1)

PIC18F45J10 FAMILY

17.4 EUSART Synchronous

Slave Mode

Synchronous Slave mode is entered by clearing bit,

CSRC (TXSTA<7>). This mode differs from the

Synchronous Master mode in that the shift clock is sup-

plied externally at the CK pin (instead of being supplied

internally in Master mode). This allows the device to

transfer or receive data while in any low-power mode.

17.4.1 EUSART SYNCHRONOUS

SLAVE TRANSMISSION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep

mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in the TXREG

c) Flag bit, TXIF, will not be set.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit, TXIF, will now be

set.

e) If enable bit, TXIE, is set, the interrupt will wake

the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

To set up a Synchronous Slave Transmission:

1. Enable the synchronous slave serial port by

setting bits, SYNC and SPEN, and clearing bit,

CSRC.

2. Clear bits, CREN and SREN.

3. If interrupts are desired, set enable bit, TXIE.

4. If 9-bit transmission is desired, set bit, TX9.

5. Enable the transmission by setting enable bit,

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

7. Start transmission by loading data to the TXREG

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on pag e

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49

TXREG EUSART Transmit Register 49

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49

BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 49

SPBRGH EUSART Baud Rate Generator Register High Byte 49

SPBRG EUSART Baud Rate Generator Register Low Byte 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

17.4.2 EUSART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of Sleep, or any

Idle mode and bit, SREN, which is a “don’t care” in

Slave mode.

If receive is enabled by setting the CREN bit prior to

entering Sleep or any Idle mode, then a word may be

received while in this low-power mode. Once the word

is received, the RSR register will transfer the data to the

RCREG register; if the RCIE enable bit is set, the inter-

rupt generated will wake the chip from the low-power

mode. If the global interrupt is enabled, the program will

branch to the interrupt vector.

To set up a Synchronous Slave Reception:

1. Enable the synchronous master serial port by

setting bits, SYNC and SPEN, and clearing bit,

CSRC.

2. If interrupts are desired, set enable bit, RCIE.

3. If 9-bit reception is desired, set bit, RX9.

4. To enable reception, set enable bit, CREN.

5. Flag bit, RCIF, will be set when reception is

complete. An interrupt will be generated if

enable bit, RCIE, was set.

6. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

7. Read the 8-bit received data by reading the

RCREG register.

8. If any error occurred, clear the error by clearing

bit, CREN.

9. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 49

RCREG EUSART Receive Register 49

TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 49

BAUDCON ABDOVF RCIDL —SCKPBRG16—WUE ABDEN 49

SPBRGH EUSART Baud Rate Generator Register High Byte 49

SPBRG EUSART Baud Rate Generator Register Low Byte 49

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

18.0 10-BIT ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has

10 inputs for the 28-pin devices and 13 for the 40/44-pin

devices. This module allows conversion of an analog

input signal to a corresponding 10-bit digital number.

The module has five registers:

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

• A/D Control Register 2 (ADCON2)

The ADCON0 register, shown in Register 18-1,

controls the operation of the A/D module. The

ADCON1 register, shown in Register 18-2, configures

the functions of the port pins. The ADCON2 register,

shown in Register 18-3, configures the A/D clock

source, programmed acquisition time and justification.

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADCAL: A/D Calibration bit

1 = Calibration is performed on next A/D conversion

0 = Normal A/D converter operation (no calibration is performed)

bit 6 Unimplemented: Read as ‘0’

bit 5-2 CHS<3:0>: Analog Channel Select bits

0000 = Channel 0 (AN0)

0001 = Channel 1 (AN1)

0010 = Channel 2 (AN2)

0011 = Channel 3 (AN3)

0100 = Channel 4 (AN4)

0101 = Channel 5 (AN5)(1,2)

0110 = Channel 6 (AN6)(1,2)

0111 = Channel 7 (AN7)(1,2)

1000 = Channel 8 (AN8)

1001 = Channel 9 (AN9)

1010 = Channel 10 (AN10)

1011 = Channel 11 (AN11)

1100 = Channel 12 (AN12)

1101 = Unimplemented(2)

1110 = Unimplemented(2)

1111 = Unimplemented(2)

bit 1 GO/DONE: A/D Conversion Status bit

When ADON = 1:

1 = A/D conversion in progress

0 = A/D Idle

bit 0 ADON: A/D On bit

1 = A/D converter module is enabled

0 = A/D converter module is disabled

Note 1: These channels are not implemented on 28-pin devices.

2: Performing a conversion on unimplemented channels will return a floating input measurement.

PIC18F45J10 FAMILY

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)

1 =V

REF- (AN2)

0 =V

bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)

1 =V

REF+ (AN3)

0 =V

bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits:

A = Analog input D = Digital I/O

Note 1: AN5 through AN7 are available only on 40/44-pin devices.

PCFG<3:0>

AN12

AN11

AN10

AN9

AN8

AN7(1)

AN6(1)

AN5(1)

AN4

AN3

AN2

AN1

AN0

0000 A A AAAAAAAAAAA

0001 A A AAAAAAAAAAA

0010 A A AAAAAAAAAAA

0011 D A AAAAAAAAAAA

0100 D D AAAAAAAAAAA

0101 DDDAAAAAAAAAA

0110 DDDDAAAAAAAAA

0111 DDDDDAAAAAAAA

1000 D D DDDDAAAAAAA

1001 D D DDDDDAAAAAA

1010 D D DDDDDDAAAAA

1011 D D DDDDDDDAAAA

1100 D D DDDDDDDDAAA

1101 D D DDDDDDDDDAA

1110 D D DDDDDDDDDDA

1111 D D DDDDDDDDDDD

PIC18F45J10 FAMILY

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified

0 = Left justified

bit 6 Unimplemented: Read as ‘0’

bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits

111 = 20 T

110 = 16 TAD

101 = 12 TAD

100 = 8 TAD

011 = 6 TAD

010 = 4 TAD

001 = 2 TAD

000 = 0 TAD(1)

bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits

111 = FRC (clock derived from A/D RC oscillator)(1)

110 = FOSC/64

101 = FOSC/16

100 = FOSC/4

011 = FRC (clock derived from A/D RC oscillator)(1)

010 = FOSC/32

001 = FOSC/8

000 = FOSC/2

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D

clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

PIC18F45J10 FAMILY

The analog reference voltage is software selectable to

either the device’s positive and negative supply voltage

(VDD and VSS), or the voltage level on the RA3/AN3/

VREF+ and RA2/AN2/VREF-/CVREF pins.

The A/D converter has a unique feature of being able

to operate while the device is in Sleep mode. To oper-

ate in Sleep, the A/D conversion clock must be derived

from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the

converter, which generates the result via successive

approximation.

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off and any

conversion in progress is aborted.

Each port pin associated with the A/D converter can be

configured as an analog input, or as a digital I/O. The

ADRESH and ADRESL registers contain the result of

the A/D conversion. When the A/D conversion is com-

plete, the result is loaded into the ADRESH:ADRESL

cleared and A/D Interrupt Flag bit, ADIF, is set. The block

diagram of the A/D module is shown in Figure 18-1.

FIGURE 18-1: A/D BLOCK DIAGRAM

(Input Voltage)

VAIN

VREF+

Reference

Voltage

VDD(2)

VCFG<1:0>

CHS<3:0>

AN7(1)

AN6(1)

AN5(1)

AN4

AN3

AN2

AN1

AN0

0111

0110

0101

0100

0011

0010

0001

0000

10-Bit

A/D

VREF-

VSS(2)

Converter

AN12

AN11

AN10

AN9

AN8

1100

1011

1010

1001

1000

Note 1: Channels AN5 through AN7 are not available in 28-pin devices.

2: I/O pins have diode protection to VDD and VSS.

PIC18F45J10 FAMILY

After the A/D module has been configured as desired,

the selected channel must be acquired before the

conversion is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 18.1

“A/D Acquisition Requirements”. After this acquisi-

tion time has elapsed, the A/D conversion can be

started. An acquisition time can be programmed to

occur between setting the GO/DONE bit and the actual

start of the conversion.

The following steps should be followed to do an A/D

conversion:

1. Configure the A/D module:

• Configure analog pins, voltage reference and

digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D acquisition time (ADCON2)

• Select A/D conversion clock (ADCON2)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time (if required).

4. Start conversion:

• Set GO/DONE bit (ADCON0<1>)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result registers (ADRESH:ADRESL);

clear bit, ADIF, if required.

7. For next conversion, go to step 1 or step 2, as

required. The A/D conversion time per bit is

defined as T

AD. A minimum wait of 2 TAD is

required before next acquisition starts.

FIGURE 18-2: ANALOG INPUT MODEL

VAIN CPIN

RSANx

5 pF

VDD

VT = 0.6V

VT = 0.6V ILEAKAGE

RIC ≤ 1k

Sampling

Switch

SS RSS

CHOLD = 25 pF

VSS

Sampling Switch

123 4

(kΩ)

VDD

±100 nA

Legend: CPIN

ILEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage Current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance (from DAC)

various junctions

= Sampling Switch ResistanceRSS

PIC18F45J10 FAMILY

18.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 18-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 kΩ. After the analog input channel is

selected (changed), the channel must be sampled for

at least the minimum acquisition time before starting a

conversion.

To calculate the minimum acquisition time,

Equation 18-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

Equation 18-3 shows the calculation of the minimum

required acquisition time, T

ACQ. This calculation is

based on the following application system

assumptions:

CHOLD =25 pF

Rs = 2.5 kΩ

Conversion Error ≤1/2 LSb

VDD =3V→Rss = 2 kΩ

Temperature = 85°C (system max.)

EQUATION 18-1: ACQUISITION TIME

EQUATION 18-2: A/D MINIMUM CHARGING TIME

EQUATION 18-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

Note: When the conversion is started, the

holding capacitor is disconnected from the

input pin.

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

AMP + TC + TCOFF

VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))

TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)

TACQ =TAMP + TC + TCOFF

TAMP =0.2 μs

TCOFF = (Temp – 25°C)(0.02 μs/°C)

(85°C – 25°C)(0.02 μs/°C)

1.2 μs

Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.

TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) μs

-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0 .0004883) μs

1.05 μs

TACQ =0.2 μs + 1 μs + 1.2 μs

2.4 μs

PIC18F45J10 FAMILY

18.2 Selecting and Configuring

Auto mati c A c q u is i tion Time

The ADCON2 register allows the user to select an

acquisition time that occurs each time the GO/DONE

bit is set.

When the GO/DONE bit is set, sampling is stopped and

a conversion begins. The user is responsible for ensur-

ing the required acquisition time has passed between

selecting the desired input channel and setting the

GO/DONE bit. This occurs when the ACQT<2:0> bits

(ADCON2<5:3>) remain in their Reset state (‘000’) and

is compatible with devices that do not offer

programmable acquisition times.

If desired, the ACQT bits can be set to select a pro-

grammable acquisition time for the A/D module. When

the GO/DONE bit is set, the A/D module continues to

sample the input for the selected acquisition time, then

automatically begins a conversion. Since the acquisi-

tion time is programmed, there may be no need to wait

for an acquisition time between selecting a channel and

setting the GO/DONE bit.

In either case, when the conversion is completed, the

GO/DONE bit is cleared, the ADIF flag is set and the

A/D begins sampling the currently selected channel

again. If an acquisition time is programmed, there is

nothing to indicate if the acquisition time has ended or

if the conversion has begun.

18.3 Selecting the A/D Conversion

Clock

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 11 T

AD per 10-bit conversion.

The source of the A/D conversion clock is software

selectable.

There are seven possible options for TAD:

•2 T

OSC

•4 TOSC

•8 TOSC

•16 TOSC

•32 TOSC

•64 T

OSC

• Internal RC Oscillator

For correct A/D conversions, the A/D conversion clock

AD) must be as short as possible but greater than the

minimum TAD (see parameter 130 in Table 24-25 for

more information).

Table 18-1 shows the resultant T

AD times derived from

the device operating frequencies and the A/D clock

source selected.

TABLE 18-1: TAD vs. DEVICE OPERATING

FREQUENCIES

18.4 Configuring Analog Port Pins

The ADCON1, TRISA, TRISF and TRISH registers

control the operation of the A/D port pins. The port pins

needed as analog inputs must have their correspond-

ing TRIS bits set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) will be

converted.

The A/D operation is independent of the state of the

CHS<3:0> bits and the TRIS bits.

AD Clock Source (TAD)Maximum

Device

Frequency

Operation ADCS<2:0>

2 T

OSC 000 2.86 MHz

4 T

OSC 100 5.71 MHz

8 TOSC 001 11.43 MHz

16 TOSC 101 22.86 MHz

32 TOSC 010 40.0 MHz

64 TOSC 110 40.0 MHz

RC(2) x11 1.00 MHz(1)

Note 1: The RC source has a typical TAD time of

4μs.

2: For device frequencies above 1 MHz, the

device must be in Sleep mode for the entire

conversion or the A/D accuracy may be out

of specification.

Note 1: When reading the PORT register, all pins

configured as analog input channels will

read as cleared (a low level). Pins config-

ured as digital inputs will convert an

analog input. Analog levels on a digitally

configured input will be accurately

converted.

2: Analog levels on any pin defined as a

digital input may cause the digital input

buffer to consume current out of the

device’s specification limits.

PIC18F45J10 FAMILY

18.5 A/D Conversions

Figure 18-3 shows the operation of the A/D converter

after the GO/DONE bit has been set and the

ACQT<2:0> bits are cleared. A conversion is started

after the following instruction to allow entry into Sleep

mode before the conversion begins.

Figure 18-4 shows the operation of the A/D converter

after the GO/DONE bit has been set, the ACQT<2:0>

bits are set to ‘010’ and selecting a 4 TAD acquisition

time before the conversion starts.

Clearing the GO/DONE bit during a conversion will abort

the current conversion. The A/D Result register pair will

NOT be updated with the partially completed A/D

conversion sample. This means the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

AD wait is required before the next acquisition can be

started. After this wait, acquisition on the selected

channel is automatically started.

18.6 Use of the ECCP2 Trigger

An A/D conversion can be started by the “Special Event

Trigger” of the ECCP2 module. This requires that the

CCP2M<3:0> bits (CCP2CON<3:0>) be programmed

as ‘1011’ and that the A/D module is enabled (ADON

bit is set). When the trigger occurs, the GO/DONE bit

will be set, starting the A/D acquisition and conversion

and the Timer1 (or Timer3) counter will be reset to zero.

Timer1 (or Timer3) is reset to automatically repeat the

A/D acquisition period with minimal software overhead

(moving ADRESH/ADRESL to the desired location).

The appropriate analog input channel must be selected

and the minimum acquisition period is either timed by

the user, or an appropriate TACQ time is selected before

the Special Event Trigger sets the GO/DONE bit (starts

a conversion).

If the A/D module is not enabled (ADON is cleared), the

Special Event Trigger will be ignored by the A/D module

but will still reset the Timer1 (or Timer3) counter.

FIGURE 18-3: A/D C ONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 18-4: A/D C ONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

TAD1 TAD2TAD3TAD4 TAD5TAD6 TAD7TAD8TAD11

Set GO/DONE bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10

TCY - TAD

Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion starts

b9 b6 b5 b4 b3 b2 b1

b8 b7

1234567811

Set GO/DONE bit

(Holding capacitor is disconnected)

910

Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is reconnected to analog input.

Conversion starts

123 4

(Holding capacitor continues

acquiring input)

TACQT Cycles TAD Cycles

Automatic

Acquisition

Time

b0b9 b6 b5 b4 b3 b2 b1

b8 b7

PIC18F45J10 FAMILY

18.7 A/D Converter Calibration

The A/D converter in the PIC18F45J10 family of

devices includes a self-calibration feature which com-

pensates for any offset generated within the module.

The calibration process is automated and is initiated by

setting the ADCAL bit (ADCON0<7>). The next time

the GO/DONE bit is set, the module will perform a

“dummy” conversion (that is, with reading none of the

input channels) and store the resulting value internally

to compensate for offset. Thus, subsequent offsets will

be compensated.

The calibration process assumes that the device is in a

relatively steady-state operating condition. If A/D

calibration is used, it should be performed after each

device Reset or if there are other major changes in

operating conditions.

18.8 Operation in Power-Managed

Modes

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ACQT<2:0> and

ADCS<2:0> bits in ADCON2 should be updated in

accordance with the power-managed mode clock that

will be used. After the power-managed mode is entered

(either of the power-managed Run modes), an A/D

acquisition or conversion may be started. Once an

acquisition or conversion is started, the device should

continue to be clocked by the same power-managed

mode clock source until the conversion has been com-

pleted. If desired, the device may be placed into the

corresponding power-managed Idle mode during the

conversion.

If the power-managed mode clock frequency is less

than 1 MHz, the A/D RC clock source should be

selected.

Operation in the Sleep mode requires the A/D RC clock

to be selected. If bits, ACQT<2:0>, are set to ‘000’ and

a conversion is started, the conversion will be delayed

one instruction cycle to allow execution of the SLEEP

instruction and entry to Sleep mode. The IDLEN and

SCS bits in the OSCCON register must have already

been cleared prior to starting the conversion.

TABLE 18-2: REGISTERS ASSOCIATED WITH A/D OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on pag e

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47

PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 49

PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 49

IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 49

PIR2 OSCFIF CMIF — — BCL1IF —— CCP2IF 49

PIE2 OSCFIE CMIE — — BCL1IE —— CCP2IE 49

IPR2 OSCFIP CMIP — — BCL1IP —— CCP2IP 49

ADRESH A/D Result Register High Byte 48

ADRESL A/D Result Register Low Byte 48

ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 48

ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48

ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 48

PORTA ——RA5 — RA3 RA2 RA1 RA0 50

TRISA —— TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 50

TRISB PORTB Data Direction Control Register 50

LATB PORTB Data Latch Register (Read and Write to Data Latch) 50

PORTE(1) — — — — —RE2RE1RE050

TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 50

LATE(1) — — — — — PORTE Data Latch Register

(Read and Write to Data Latch)

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.

Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

19.0 COMPARATOR MODULE

The analog comparator module contains two

comparators that can be configured in a variety of

ways. The inputs can be selected from the analog

inputs multiplexed with pins RA0 through RA5, as well

as the on-chip voltage reference (see Section 20.0

“Comparator Voltage Reference Module”). The digi-

tal outputs (normal or inverted) are available at the pin

level and can also be read through the control register.

The CMCON register (Register 19.1) selects the

comparator input and output configuration. Block

diagrams of the various comparator configurations are

shown in Figure 19-1.

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C2OUT: Comparator 2 Output bit

When C2INV = 0:

1 = C2 VIN+ > C2 VIN-

0 = C2 VIN+ < C2 VIN-

When C2INV = 1:

1 = C2 VIN+ < C2 VIN-

0 = C2 VIN+ > C2 VIN-

bit 6 C1OUT: Comparator 1 Output bit

When C1INV = 0:

1 = C1 VIN+ > C1 VIN-

0 = C1 VIN+ < C1 VIN-

When C1INV = 1:

1 = C1 VIN+ < C1 VIN-

0 = C1 VIN+ > C1 VIN-

bit 5 C2INV: Comparator 2 Output Inversion bit

1 = C2 output inverted

0 = C2 output not inverted

bit 4 C1INV: Comparator 1 Output Inversion bit

1 = C1 output inverted

0 = C1 output not inverted

bit 3 CIS: Comparator Input Switch bit

When CM<2:0> = 110:

1 =C1 VIN- connects to RA3/AN3/VREF+

C2 VIN- connects to RA2/AN2/VREF-/CVREF

0 =C1 VIN- connects to RA0/AN0

C2 VIN- connects to RA1/AN1

bit 2-0 CM<2:0>: Comparator Mode bits

Figure 19-1 shows the Comparator modes and the CM<2:0> bit settings.

PIC18F45J10 FAMILY

19.1 Comparator Configuration

There are eight modes of operation for the compara-

tors, shown in Figure 19-1. Bits, CM<2:0> of the

CMCON register, are used to select these modes. The

TRISA register controls the data direction of the com-

parator pins for each mode. If the Comparator mode is

changed, the comparator output level may not be valid

for the specified mode change delay shown in

Section 24.0 “Electrical Characteristics”.

FIGURE 19-1: COMPARATOR I/O OPERATING MODES

Note: Comparator interrupts should be disabled

during a Comparator mode change;

otherwise, a false interrupt may occur.

RA0/AN0 VIN-

VIN+

RA3/AN3/ Off (Read as ‘0’)

Comparators Reset

CM<2:0> = 000

RA1/AN1 VIN-

VIN+

RA2/AN2/ Off (Read as ‘0’)

VIN-

VIN+C1OUT

Two Independent Comparators

CM<2:0> = 010

VIN-

VIN+C2OUT

VIN-

VIN+C1OUT

Two Commo n Reference Comparators

CM<2:0> = 100

VIN-

VIN+C2OUT

VIN-

VIN+Off (Read as ‘0’)

One Independent Comparator with Output

CM<2:0> = 001

VIN-

VIN+C1OUT

VIN-

VIN+Off (Read as ‘0’)

Comparators Off (POR Default Value)

CM<2:0> = 111

VIN-

VIN+Off (Read as ‘0’)

VIN-

VIN+C1OUT

Four Inputs Multiplexed to Two Comparators

CM<2:0> = 110

VIN-

VIN+C2OUT

From VREF Module

CIS = 0

CIS = 1

CIS = 0

CIS = 1

VIN-

VIN+C1OUT

Two Common Reference Comparators with Outputs

CM<2:0> = 101

VIN-

VIN+C2OUT

A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch

CVREF

VIN-

VIN+C1OUT

Two Independent Comparators with Outputs

CM<2:0> = 011

VIN-

VIN+C2OUT

RA5/AN4/SS1/C2OUT*

RB5/KBI1/T0CKI/C1OUT*

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF/

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF/

RA0/AN0

RA3/AN3/

RA1/AN1

RA2/AN2/

VREF+

VREF-/CVREF

RA0/AN0

RA3/AN3/

VREF+

RA1/AN1

RA2/AN2/

VREF-/CVREF

RB5/KBI1/

RA5/AN4/SS1/C2OUT*

RA0/AN0

RA3/AN3/

VREF+

RA1/AN1

RA2/AN2/

VREF-/CVREF

RB5/KBI1/

* Setting the TRISA<5> bit will disable the comparator outputs by configuring the pins as inputs.

T0CKI/C1OUT*

PIC18F45J10 FAMILY

19.2 Comparator Operation

A single comparator is shown in Figure 19-2, along with

the relationship between the analog input levels and

the digital output. When the analog input at VIN+ is less

than the analog input, VIN-, the output of the

comparator is a digital low level. When the analog input

at VIN+ is greater than the analog input, VIN-, the output

of the comparator is a digital high level. The shaded

areas of the output of the comparator in Figure 19-2

represent the uncertainty due to input offsets and

response time.

19.3 Comparator Reference

Depending on the comparator operating mode, either

an external or internal voltage reference may be used.

The analog signal present at VIN- is compared to the

signal at VIN+ and the digital output of the comparator

is adjusted accordingly (Figure 19-2).

FIGURE 19-2: SINGLE COMPARATOR

19.3.1 EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the

comparator module can be configured to have the com-

parators operate from the same or different reference

sources. However, threshold detector applications may

require the same reference. The reference signal must

be between VSS and VDD and can be applied to either

pin of the comparator(s).

19.3.2 INTERNAL REFERENCE SIGNAL

The comparator module also allows the selection of an

internally generated voltage reference from the

comparator voltage reference module. This module is

described in more detail in Section 20.0 “Comparator

Voltage Reference Module”.

The internal reference is only available in the mode

where four inputs are multiplexed to two comparators

(CM<2:0> = 110). In this mode, the internal voltage

reference is applied to the VIN+ pin of both comparators.

19.4 Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output has a valid level. If the internal ref-

erence is changed, the maximum delay of the internal

voltage reference must be considered when using the

comparator outputs. Otherwise, the maximum delay of

the comparators should be used (see Section 24.0

“Electri cal Characte ristics”).

19.5 Comparator Outputs

The comparator outputs are read through the CMCON

outputs may also be directly output to the RB5 and RA5

I/O pins. When enabled, multiplexors in the output path

of the RB5 and RA5 pins will switch and the output of

each pin will be the unsynchronized output of the

comparator. The uncertainty of each of the

comparators is related to the input offset voltage and

the response time given in the specifications.

Figure 19-3 shows the comparator output block

diagram.

The TRISA bits will still function as an output enable/

disable for the RB5 and RA5 pins while in this mode.

The polarity of the comparator outputs can be changed

using the C2INV and C1INV bits (CMCON<5:4>).

–

VIN+

VIN-

Output

VIN-

VIN+

Note 1: When reading the PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert an analog input according to the

Schmitt Trigger input specification.

2: Analog levels on any pin defined as a

digital input may cause the input buffer to

consume more current than is specified.

PIC18F45J10 FAMILY

FIGURE 19-3: COMPARATOR OUTPUT BLOCK DIAGRAM

19.6 Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that occurred. The CMIF

bit (PIR2<6>) is the Comparator Interrupt Flag. The

CMIF bit must be reset by clearing it. Since it is also

possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

Both the CMIE bit (PIE2<6>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit (INTCON<7>) must also be set. If

any of these bits are clear, the interrupt is not enabled,

though the CMIF bit will still be set if an interrupt

condition occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatch condition will continue to set flag bit, CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit, CMIF, to be cleared.

19.7 Comparator Operation

During Sleep

When a comparator is active and the device is placed

in Sleep mode, the comparator remains active and the

interrupt is functional, if enabled. This interrupt will

wake-up the device from Sleep mode, when enabled.

Each operational comparator will consume additional

current, as shown in the comparator specifications. To

minimize power consumption while in Sleep mode, turn

off the comparators (CM<2:0> = 111) before entering

Sleep. If the device wakes up from Sleep, the contents

of the CMCON register are not affected.

19.8 Effects of a Reset

A device Reset forces the CMCON register to its Reset

state, causing the comparator modules to be turned off

(CM<2:0> = 111). However, the input pins (RA0

through RA3) are configured as analog inputs by

default on device Reset. The I/O configuration for these

pins is determined by the setting of the PCFG<3:0> bits

(ADCON1<3:0>). Therefore, device current is

minimized when analog inputs are present at Reset

time.

To R B5 o r

RA5 pin

Bus

Data

Set

MULTIPLEX

CMIF

bit

Port Pins

Read CMCON

Reset

From

Other

Comparator

CxINV

EN CL

Note: If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR2

PIC18F45J10 FAMILY

19.9 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 19-4. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input, therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up condition may

occur. A maximum source impedance of 10 kΩ is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

FIGURE 19-4: COMPARATOR ANALOG INPUT MODEL

TABLE 19-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 49

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 49

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 50

PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 49

PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 49

IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 49

PORTA ——RA5— RA3 RA2 RA1 RA0 50

LATA —— PORTA Data Latch Register (Read and Write to Data Latch) 50

TRISA —— TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.

RS < 10k

AIN

CPIN

5 pF

VDD

VT = 0.6V

RIC

ILEAKAGE

±100 nA

VSS

Legend: CPIN = Input Capacitance

VT= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC = Interconnect Resistance

RS= Source Impedance

VA = Analog Voltage

Comparator

Input

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

20.0 COMPARATOR VO LTAGE

REFERENC E MODULE

The comparator voltage reference is a 16-tap resistor

ladder network that provides a selectable reference

voltage. Although its primary purpose is to provide a

reference for the analog comparators, it may also be

used independently of them.

A block diagram of the module is shown in Figure 20-1.

The resistor ladder is segmented to provide two ranges

of CVREF values and has a power-down function to

conserve power when the reference is not being used.

The module’s supply reference can be provided from

either device VDD/VSS or an external voltage reference.

20.1 Configuring the Comparator

Voltage Reference

The voltage reference module is controlled through the

CVRCON register (Register 20-1). The comparator

voltage reference provides two ranges of output

voltage, each with 16 distinct levels. The range to be

used is selected by the CVRR bit (CVRCON<5>). The

primary difference between the ranges is the size of the

steps selected by the CVREF Selection bits

(CVR<3:0>), with one range offering finer resolution.

The equations used to calculate the output of the

comparator voltage reference are as follows:

If CVRR = 1:

CVREF = ((CVR<3:0>)/24) x CVRSRC

If CVRR = 0:

CVREF = (CVRSRC x 1/4) + (((CVR<3:0>)/32) x

CVRSRC)

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

VREF- that are multiplexed with RA2 and RA3. The

voltage source is selected by the CVRSS bit

(CVRCON<4>).

The settling time of the comparator voltage reference

must be considered when changing the CVREF

output (see Table 24-3 in Section 24.0 “Electrical

Characteristics”).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CVREN: Comparator Voltage Reference Enable bit

1 =CV

REF circuit powered on

0 =CV

REF circuit powered down

bit 6 CVROE: Comparator VREF Output Enable bit(1)

1 =CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin

0 =CV

REF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin

bit 5 CVRR: Comparator VREF Range Selection bit

1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)

0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)

bit 4 CVRSS: Comparator VREF Source Selection bit

1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)

0 = Comparator reference source, CVRSRC = VDD – VSS

bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0 ≤ (CVR<3:0>) ≤ 15)

When CVRR = 1:

CVREF = ((CVR<3:0>)/24) • (CVRSRC)

When CVRR = 0:

CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) • (CVRSRC)

Note 1: CVROE overrides the TRISA<2> bit setting.

PIC18F45J10 FAMILY

FIGURE 20-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

20.2 Voltage Reference Accuracy/Error

The full range of voltage reference cannot be realized

due to the construction of the module. The transistors

on the top and bottom of the resistor ladder network

(Figure 20-1) keep CVREF from approaching the refer-

ence source rails. The voltage reference is derived

from the reference source; therefore, the CVREF output

changes with fluctuations in that source. The tested

absolute accuracy of the voltage reference can be

found in Section 24.0 “Electrical Characteristics”.

20.3 Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the CVRCON register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

20.4 Effects of a Reset

A device Reset disables the voltage reference by

clearing bit, CVREN (CVRCON<7>). This Reset also

disconnects the reference from the RA2 pin by clearing

bit, CVROE (CVRCON<6>) and selects the high-voltage

range by clearing bit, CVRR (CVRCON<5>). The CVR

value select bits are also cleared.

20.5 Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA2 pin if the

CVROE bit is set. Enabling the voltage reference out-

put onto RA2 when it is configured as a digital input will

increase current consumption. Connecting RA2 as a

digital output with CVRSS enabled will also increase

current consumption.

The RA2 pin can be used as a simple D/A output with

limited drive capability. Due to the limited current drive

capability, a buffer must be used on the voltage

reference output for external connections to VREF.

Figure 20-2 shows an example buffering technique.

16-to-1 MUX

CVR<3:0>

CVREN

CVRSS = 0

VDD

VREF+CVRSS = 1

CVRSS = 0

VREF-CVRSS = 1

16 Steps

CVRR

CVREF

PIC18F45J10 FAMILY

FIGURE 20-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset

Values

on page

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 49

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 49

TRISA —— TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 50

Legend: Shaded cells are not used with the comparator voltage reference.

CVREF Output

–

CVREF

Module

Voltage

Reference

Output

Impedance

R(1)

RA2

Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.

PIC18F45J10

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

21.0 SPECIAL FEATURES OF THE

CPU

PIC18F45J10 family devices include several features

intended to maximize reliability and minimize cost

through elimination of external components. These are:

• Oscillator Selection

• Resets:

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor

• Two-Speed Start-up

• Code Protection

• In-Circuit Serial Programming™ (ICSP™)

The oscillator can be configured for the application

depending on frequency, power, accuracy and cost. All

of the options are discussed in detail in Section 3.0

“Oscillator Configurations”.

A complete discussion of device Resets and interrupts

is available in previous sections of this data sheet.

In addition to their Power-up and Oscillator Start-up

Timers provided for Resets, the PIC18F45J10 family of

devices have a configurable Watchdog Timer which is

controlled in software.

The inclusion of an internal RC oscillator also provides

the additional benefits of a Fail-Safe Clock Monitor

(FSCM) and Two-Speed Start-up. FSCM provides for

background monitoring of the peripheral clock and

automatic switchover in the event of its failure.

Two-Speed Start-up enables code to be executed

almost immediately on start-up, while the primary clock

source completes its start-up delays.

All of these features are enabled and configured by

setting the appropriate Configuration register bits.

21.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’) or left unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped starting

at program memory location 300000h. A complete list

is shown in Table 21-1. A detailed explanation of the

various bit functions is provided in Register 21-1

through Register 21-8.

21.1.1 CONSIDERATIONS FOR

CONFIGURING THE PIC18F45J10

FAMILY DEVICES

Unlike most PIC18 microcontrollers, devices of the

PIC18F45J10 family do not use persistent memory

registers to store configuration information. The config-

uration bytes are implemented as volatile memory

which means that configuration data must be

programmed each time the device is powered up.

Configuration data is stored in the four words at the top

of the on-chip program memory space, known as the

Flash Configuration Words. It is stored in program

memory in the same order shown in Table 21-1, with

CONFIG1L at the lowest address and CONFIG3H at

the highest. The data is automatically loaded in the

proper Configuration registers during device power-up.

When creating applications for these devices, users

should always specifically allocate the location of the

Flash Configuration Word for configuration data; this is

to make certain that program code is not stored in this

address when the code is compiled.

The volatile memory cells used for the Configuration

bits always reset to ‘1’ on Power-on Resets. For all

other type of Reset events, the previously programmed

values are maintained and used without reloading from

program memory.

The four Most Significant bits of CONFIG1H,

CONFIG2H and CONFIG3H in program memory

should also be ‘1111’. This makes these Configuration

Words appear to be NOP instructions in the remote

event that their locations are ever executed by

accident. Since Configuration bits are not implemented

in the corresponding locations, writing ‘1’s to these

locations has no effect on device operation.

To prevent inadvertent configuration changes during

code execution, all programmable Configuration bits

are write-once. After a bit is initially programmed during

a power cycle, it cannot be written to again. Changing

a device configuration requires a device Reset.

PIC18F45J10 FAMILY

TABLE 21-1: CONFIGURATION BITS AND DEVICE IDs

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/

Unprogrammed

Value(1)

300000h CONFIG1L DEBUG XINST STVREN — — — —WDTEN111- ---1

300001h CONFIG1H —(2) —(2) —(2) —(2) —(3) CP0 — — 1111 01--

300002h CONFIG2L IESO FCMEN — — — FOSC2 FOSC1 FOSC0 11-- -111

300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 1111 1111

300004h CONFIG3L — — — — — — — — ---- ----

300005h CONFIG3H —(2) —(2) —(2) —(2) — — — CCP2MX 1111 ---1

3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(4)

3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0001 110x(4)

Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.

Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset

states, the configuration bytes maintain their previously programmed states.

2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it

is accidentally executed.

3: This bit should always be maintained as ‘0’.

4: See Register 21-7 and Register 21-8 for DEVID values. These registers are read-only and cannot be programmed by

the user.

PIC18F45J10 FAMILY

R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 U-0 R/WO-1

DEBUG XINST STVREN ————WDTEN

bit 7 bit 0

Legend:

R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 DEBUG: Background Debugger Enable bit

1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins

0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug

bit 6 XINST: Extended Instruction Set Enable bit

1 = Instruction set extension and Indexed Addressing mode enabled

0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = Reset on stack overflow/underflow enabled

0 = Reset on stack overflow/underflow disabled

bit 4-1 Unimplemented: Read as ‘0’

bit 0 WDTEN: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled (control is placed on SWDTEN bit)

U-0 U-0 U-0 U-0 U-0 R/WO-1 U-0 U-0

—(1) —(1) —(1) —(1) —(2) CP0 — —

bit 7 bit 0

Legend:

R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘1’(1)

bit 3 Unimplemented: Read as ‘0’(2)

bit 2 CP0: Code Protection bit

1 = Program memory is not code-protected

0 = Program memory is code-protected

bit 1-0 Unimplemented: Read as ‘0’

Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is

executed as a NOP if it is accidentally executed.

2: This bit should always be maintained as ‘0’.

PIC18F45J10 FAMILY

R/WO-1 R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1

IESO FCMEN — — — FOSC2 FOSC1 FOSC0

bit 7 bit 0

Legend:

R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit

1 = Two-Speed Start-up enabled

0 = Two-Speed Start-up disabled

bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor enabled

0 = Fail-Safe Clock Monitor disabled

bit 5-3 Unimplemented: Read as ‘0’

bit 2 FOSC2: Default/Reset System Clock Select bit

1 = Clock selected by FOSC<1:0> as system clock is enabled when OSCCON<1:0> = 00

0 = INTRC enabled as system clock when OSCCON<1:0> = 00

bit 1-0 FOSC<1:0>: Oscillator Selection bits

11 = EC oscillator, PLL enabled and under software control, CLKO function on OSC2

10 = EC oscillator, CLKO function on OSC2

01 = HS oscillator, PLL enabled and under software control

00 = HS oscillator

PIC18F45J10 FAMILY

U-0 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1

—(1) —(1) —(1) —(1) WDTPS3 WDTPS2 WDTPS1 WDTPS0

bit 7 bit 0

Legend:

R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘1’(1)

bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1:64

0101 = 1:32

0100 = 1:16

0011 = 1:8

0010 = 1:4

0001 = 1:2

0000 = 1:1

Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is

executed as a NOP if it is accidentally executed.

PIC18F45J10 FAMILY

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 Unimplemented: Read as ‘0’

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/WO-1

—(1) —(1) —(1) —(1) — — — CCP2MX

bit 7 bit 0

Legend:

R = Readable bit WO = Write Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 Unimplemented: Read as ‘1’(1)

bit 0 CCP2MX: CCP2 MUX bit

1 = CCP2 is multiplexed with RC1

0 = CCP2 is multiplexed with RB3

Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is

executed as a NOP if it is accidentally executed.

PIC18F45J10 FAMILY

RRRRRRRR

DEV2(1) DEV1(1) DEV0(1) REV4 REV3 REV2 REV1 REV0

bit 7 bit 0

Legend:

R = Read-only bit

-n = Value when device is unprogrammed

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

bit 7-5 DEV<2:0>: Device ID bits

011 = PIC18LF4XJ10

010 = PIC18LF2XJ10

001 = PIC18F4XJ10

000 = PIC18F2XJ10

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to indicate the device revision.

Note 1: Where values for DEV<2:0> are shared by more than one device number, the specific device is always

identified by using the entire DEV<10:0> bit sequence.

RRRRRRRR

DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1)

bit 7 bit 0

Legend:

R = Read-only bit

bit 7-0 DEV<10:3>: Device ID bits(1)

These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.

0001 1100 = PIC18FX5J10 devices

0001 1101 = PIC18FX4J10 devices

Note 1: The values for DEV<10:3> may be shared with other device families. The specific device is always

identified by using the entire DEV<10:0> bit sequence.

PIC18F45J10 FAMILY

21.2 Watchdog Timer (WDT)

For PIC18F45J10 family devices, the WDT is driven by

the INTRC oscillator. When the WDT is enabled, the

clock source is also enabled. The nominal WDT period

is 4 ms and has the same stability as the INTRC

oscillator.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is selected

by a multiplexor, controlled by the WDTPS bits in Config-

uration Register 2H. Available periods range from about

4 ms to 135 seconds (2.25 minutes) depending on volt-

age, temperature and Watchdog postscaler. The WDT

and postscaler are cleared whenever a SLEEP or

CLRWDT instruction is executed, or a clock failure

(primary or Timer1 oscillator) has occurred.

21.2.1 CONTROL REGISTER

The WDTCON register (Register 21-9) is a readable

and writable register. The SWDTEN bit enables or

disables WDT operation.

FIGURE 21-1: WDT BLOCK DIAGRAM

TABLE 21-2: SUMMARY OF WATCHDOG TIMER REGISTERS

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

2: When a CLRWDT instruction is executed,

the postscaler count will be cleared.

u-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —SWDTEN

(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 Unimplemented: Read as ‘0’

bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1)

1 = Watchdog Timer is on

0 = Watchdog Timer is off

Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values

on page

RCON IPEN —CM RI TO PD POR BOR 48

WDTCON — — — — — — —SWDTEN 48

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

INTRC Oscillator

WDT

Wake-up from

Reset

WDT

WDT Counter

Programmable Postscaler

1:1 to 1:32,768

Enable WDT

WDTPS<3:0>

SWDTEN

CLRWDT

Power-Managed

Reset

All Device Resets

Sleep

INTRC Control

÷128

Modes

PIC18F45J10 FAMILY

21.3 On-Chip Voltage Regulator

In parts designated “LF”, the microcontroller core is

powered from an external source that is separate from

VDD. This voltage is supplied on the VDDCORE pin.

In “F” devices, a low-ESR capacitor must be connected

to the VDDCORE/VCAP pin for proper device operation.

In parts designated with an “LF” part number (i.e.,

PIC18LF45J10), power to the core must be supplied on

VDDCORE/VCAP. It is always good design practice to

have sufficient capacitance on all supply pins.

Examples are shown in Figure 21-2.

The specifications for core voltage and capacitance

are listed inTable 24-4 of Section 24.0 “Electrical

Characteristics”.

FIGURE 21-2: CONNE CTIONS FOR THE

ON-CHIP REGULATOR

21.3.1 ON-CHIP REGULATOR AND BOR

When the on-chip regulator is enabled, PIC18F45J10

family devices also have a simple brown-out capability.

If the voltage supplied to the regulator is inadequate to

maintain a regulated level, the regulator Reset circuitry

will generate a BOR Reset. This event is captured by

the BOR flag bit (RCON<0>).

The operation of the BOR is described in more detail in

Section 5.4 “Brown-out Reset (BOR)

(PIC18F2XJ10/4XJ10 Devices Only)” and

Section 5.4.1 “Detecting BOR”. The brown-out voltage

levels are specific in Section 23 .1 “DC Chara cteristics:

Supply Volta ge” .

21.3.2 POWER-UP REQUIREMENTS

The on-chip regulator is designed to meet the power-up

requirements for the device. While powering up,

VDDCORE must never exceed VDD by 0.3 volts.

Note: The on-chip voltage regulator is only

available in parts designated with an “F”,

such as PIC18F45J10.

Note: In parts designated with an “LF”, such as

PIC18LF45J10, VDDCORE must never

exceed VDD.

VDD

VDDCORE/VCAP

VSS

PIC18LFXXJ10

3.3V

2.5V

VDD

VDDCORE/VCAP

VSS

PIC18FXXJ10

CEFC

3.3V

PIC18FXXJ10 Devices (Regulator En abled):

VDD

VDDCORE/VCAP

VSS

PIC18LFXXJ10

2.5V

PIC18LFXXJ10 Devices (Regulator Disabled):

PIC18F45J10 FAMILY

21.4 Two-Speed S tar t-up

The Two-Speed Start-up feature helps to minimize the

latency period, from oscillator start-up to code execu-

tion, by allowing the microcontroller to use the INTRC

oscillator as a clock source until the primary clock

source is available. It is enabled by setting the IESO

Configuration bit.

Two-Speed Start-up should be enabled only if the

primary oscillator mode is HS (Crystal-Based) modes.

Since the EC mode does not require an OST start-up

delay, Two-Speed Start-up should be disabled.

When enabled, Resets and wake-ups from Sleep mode

cause the device to configure itself to run from the

internal oscillator block as the clock source, following

the time-out of the Power-up Timer after a POR Reset

is enabled. This allows almost immediate code execu-

tion while the primary oscillator starts and the OST is

running. Once the OST times out, the device

automatically switches to PRI_RUN mode.

In all other power-managed modes, Two-Speed

Start-up is not used. The device will be clocked by the

currently selected clock source until the primary clock

source becomes available. The setting of the IESO bit

is ignored.

21.4.1 SPECIAL CONSIDERATIONS FOR

USING TWO-SPEED START-UP

While using the INTRC oscillator in Two-Speed

Start-up, the device still obeys the normal command

sequences for entering power-managed modes,

including serial SLEEP instructions (refer to

Section 4.1.4 “Multiple Sleep Commands”). In

practice, this means that user code can change the

SCS<1:0> bit settings or issue SLEEP instructions

before the OST times out. This would allow an applica-

tion to briefly wake-up, perform routine “housekeeping”

tasks and return to Sleep before the device starts to

operate from the primary oscillator.

User code can also check if the primary clock source is

currently providing the device clocking by checking the

status of the OSTS bit (OSCCON<3>). If the bit is set,

the primary oscillator is providing the clock. Otherwise,

the internal oscillator block is providing the clock during

wake-up from Reset or Sleep mode.

FIGURE 21-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC)

Q1 Q3 Q4

OSC1

Peripheral

Program PC PC + 2

INTOSC

PC + 6

Q3 Q4 Q1

CPU Clock

PC + 4

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC. These intervals are not shown to scale.

Wake From Interrupt Event OSTS bit Set

TOST(1)

PIC18F45J10 FAMILY

21.5 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the

microcontroller to continue operation in the event of an

external oscillator failure by automatically switching the

device clock to the internal oscillator block. The FSCM

function is enabled by setting the FCMEN

Configuration bit.

When FSCM is enabled, the INTRC oscillator runs at

all times to monitor clocks to peripherals and provide a

backup clock in the event of a clock failure. Clock

monitoring (shown in Figure 21-4) is accomplished by

creating a sample clock signal which is the INTRC out-

put divided by 64. This allows ample time between

FSCM sample clocks for a peripheral clock edge to

occur. The peripheral device clock and the sample

clock are presented as inputs to the Clock Monitor latch

(CM). The CM is set on the falling edge of the device

clock source but cleared on the rising edge of the

sample clock.

FIGURE 21-4: FSCM BLOCK DIAGRAM

Clock failure is tested for on the falling edge of the

sample clock. If a sample clock falling edge occurs

while CM is still set, a clock failure has been detected

(Figure 21-5). This causes the following:

• the FSCM generates an oscillator fail interrupt by

setting bit, OSCFIF (PIR2<7>);

• the device clock source is switched to the internal

oscillator block (OSCCON is not updated to show

the current clock source – this is the fail-safe

condition); and

•the WDT is reset.

During switchover, the postscaler frequency from the

internal oscillator block may not be sufficiently stable

for timing sensitive applications. In these cases, it may

be desirable to select another clock configuration and

enter an alternate power-managed mode. This can be

done to attempt a partial recovery or execute a

controlled shutdown. See Section 4.1.4 “Multiple

Sleep Commands” and Section 21.4.1 “Special

Considerations for Using Two-Speed Start-up” for

more details.

To use a higher clock speed on wake-up, the INTOSC

or postscaler clock sources can be selected to provide

a higher clock speed by setting bits IRCF<2:0>

immediately after Reset. For wake-ups from Sleep, the

INTOSC or postscaler clock sources can be selected

by setting IRCF<2:0> prior to entering Sleep mode.

The FSCM will detect failures of the primary or second-

ary clock sources only. If the internal oscillator block

fails, no failure would be detected, nor would any action

be possible.

21.5.1 FSCM AND THE WATCHDOG TIMER

Both the FSCM and the WDT are clocked by the

INTRC oscillator. Since the WDT operates with a

separate divider and counter, disabling the WDT has

no effect on the operation of the INTRC oscillator when

the FSCM is enabled.

As already noted, the clock source is switched to the

INTRC clock when a clock failure is detected; this may

mean a substantial change in the speed of code execu-

tion. If the WDT is enabled with a small prescale value,

a decrease in clock speed allows a WDT time-out to

occur and a subsequent device Reset. For this reason,

Fail-Safe Clock Monitor events also reset the WDT and

postscaler, allowing it to start timing from when execu-

tion speed was changed and decreasing the likelihood

of an erroneous time-out.

21.5.2 EXITING FAIL-SAFE OPERATION

The fail-safe condition is terminated by either a device

Reset or by entering a power-managed mode. On

Reset, the controller starts the primary clock source

specified in Configuration Register 2H (with the OST

oscillator, start-up delays if running in HS mode). The

INTRC oscillator provides the device clock until the

primary clock source becomes ready (similar to a

Two-Speed Start-up). The clock source is then

switched to the primary clock (indicated by the OSTS

bit in the OSCCON register becoming set). The

Fail-Safe Clock Monitor then resumes monitoring the

peripheral clock.

The primary clock source may never become ready

during start-up. In this case, operation is clocked by the

INTRC oscillator. The OSCCON register will remain in

its Reset state until a power-managed mode is entered.

Peripheral

INTRC ÷ 64

(32 μs) 488 Hz

(2.048 ms)

Clock Monitor

Latch (CM)

(edge-triggered)

Clock

Failure

Detected

Source

Clock

PIC18F45J10 FAMILY

FIGURE 21-5: FSCM TIMING DIAGRAM

21.5.3 FSCM INTERRUPTS IN

POWER-MANAGED MODES

By entering a power-managed mode, the clock

multiplexor selects the clock source selected by the

OSCCON register. Fail-Safe Monitoring of the

power-managed clock source resumes in the

power-managed mode.

If an oscillator failure occurs during power-managed

operation, the subsequent events depend on whether

or not the oscillator failure interrupt is enabled. If

enabled (OSCFIF = 1), code execution will be clocked

by the INTOSC multiplexor. An automatic transition

back to the failed clock source will not occur.

If the interrupt is disabled, subsequent interrupts while

in Idle mode will cause the CPU to begin executing

instructions while being clocked by the INTOSC

source.

21.5.4 POR OR WAKE-UP FROM SLEEP

The FSCM is designed to detect oscillator failure at any

point after the device has exited Power-on Reset

(POR) or low-power Sleep mode. When the primary

device clock is either EC or INTRC modes, monitoring

can begin immediately following these events.

For HS mode, the situation is somewhat different.

Since the oscillator may require a start-up time consid-

erably longer than the FSCM sample clock time, a false

clock failure may be detected. To prevent this, the

internal oscillator block is automatically configured as

the device clock and functions until the primary clock is

stable (the OST timer has timed out). This is identical

to Two-Speed Start-up mode. Once the primary clock is

stable, the INTRC returns to its role as the FSCM

source.

As noted in Section 21.4.1 “Special Considerations

for Using Two-Speed Start-up”, it is also possible to

select another clock configuration and enter an alternate

power-managed mode while waiting for the primary

clock to become stable. When the new power-managed

mode is selected, the primary clock is disabled.

OSCFIF

CM Output

Device

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

CM Test CM Test CM Test

Note: The same logic that prevents false oscilla-

tor failure interrupts on POR, or wake from

Sleep, will also prevent the detection of

the oscillator’s failure to start at all

following these events. This can be

avoided by monitoring the OSTS bit and

using a timing routine to determine if the

oscillator is taking too long to start. Even

so, no oscillator failure interrupt will be

flagged.

PIC18F45J10 FAMILY

21.6 Program Verification and

Code Protection

For all devices in the PIC18F45J10 family of devices,

the on-chip program memory space is treated as a

single block. Code protection for this block is controlled

by one Configuration bit, CP0. This bit inhibits external

reads and writes to the program memory space. It has

no direct effect in normal execution mode.

21.6.1 CONFIGURATION REGISTER

PROTECTION

The Configuration registers are protected against

untoward changes or reads in two ways. The primary

protection is the write-once feature of the Configuration

bits which prevents reconfiguration once the bit has

been programmed during a power cycle. To safeguard

against unpredictable events, Configuration bit

changes resulting from individual cell-level disruptions

(such as ESD events) will cause a parity error and

trigger a device Reset.

The data for the Configuration registers is derived from

the Flash Configuration Words in program memory.

When the CP0 bit is set, the source data for device

configuration is also protected as a consequence.

21.7 In-Circuit Serial Programming

PIC18F45J10 family microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

21.8 In-Circuit Debugger

When the DEBUG Configuration bit is programmed to

a ‘0’, the In-Circuit Debugger functionality is enabled.

This function allows simple debugging functions when

used with MPLAB® IDE. When the microcontroller has

this feature enabled, some resources are not available

for general use. Table 21-3 shows which resources are

required by the background debugger.

TABLE 21-3: DEBUGGER RESOURCES

I/O pins: RB6, RB7

Stack: 2 levels

Program Memory: 512 bytes

Data Memory: 32 bytes

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

22.0 INSTRUCTION SET SUMMARY

PIC18F45J10 family devices incorporate the standard

set of 75 PIC18 core instructions, as well as an extended

set of 8 new instructions, for the optimization of code that

is recursive or that utilizes a software stack. The

extended set is discussed later in this section.

22.1 Standard Instruction Set

The standard PIC18 instruction set adds many

enhancements to the previous PIC® MCU instruction

sets, while maintaining an easy migration from these

PIC MCU instruction sets. Most instructions are a sin-

gle program memory word (16 bits), but there are four

instructions that require two program memory

locations.

Each single-word instruction is a 16-bit word divided

into an opcode, which specifies the instruction type and

one or more operands, which further specify the

operation of the instruction.

The instruction set is highly orthogonal and is grouped

into four basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal operations

•Control operations

The PIC18 instruction set summary in Table 22-2 lists

byte-oriented, bit-oriented, literal and control

operations. Table 22-1 shows the opcode field

descriptions.

Most byte-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The destination of the result (specified by ‘d’)

3. The accessed memory (specified by ‘a’)

The file register designator ‘f’ specifies which file

designator ‘d’ specifies where the result of the opera-

tion is to be placed. If ‘d’ is zero, the result is placed in

the WREG register. If ‘d’ is one, the result is placed in

the file register specified in the instruction.

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The bit in the file register (specified by ‘b’)

3. The accessed memory (specified by ‘a’)

The bit field designator ‘b’ selects the number of the bit

affected by the operation, while the file register

designator ‘f’ represents the number of the file in which

the bit is located.

The literal instructions may use some of the following

operands:

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

• No operand required

(specified by ‘—’)

The control instructions may use some of the following

operands:

• A program memory address (specified by ‘n’)

• The mode of the CALL or RETURN instructions

(specified by ‘s’)

• The mode of the table read and table write

instructions (specified by ‘m’)

• No operand required

(specified by ‘—’)

All instructions are a single word, except for four

double-word instructions. These instructions were

made double-word to contain the required information

in 32 bits. In the second word, the 4 MSbs are ‘1’s. If

this second word is executed as an instruction (by

itself), it will execute as a NOP.

All single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles, with the additional instruction cycle(s) executed

as a NOP.

The double-word instructions execute in two instruction

cycles.

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 μs. If a conditional test is

true, or the program counter is changed as a result of

an instruction, the instruction execution time is 2 μs.

Two-word branch instructions (if true) would take 3 μs.

Figure 22-1 shows the general formats that the instruc-

tions can have. All examples use the convention ‘nnh’

to represent a hexadecimal number.

The Instruction Set Summary, shown in Table 22-2,

lists the standard instructions recognized by the

Microchip Assembler (MPASMTM).

Section 22.1.1 “Standard Instruction Set” provides

a description of each instruction.

PIC18F45J10 FAMILY

TABLE 22-1: OPCODE FIELD DESCRIPTIONS

Field Description

aRAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb Bit address within an 8-bit file register (0 to 7).

BSR Bank Select Register. Used to select the current RAM bank.

C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.

dDestination select bit

d = 0: store result in WREG

d = 1: store result in file register f

dest Destination: either the WREG register or the specified register file location.

f8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).

fs12-bit register file address (000h to FFFh). This is the source address.

fd12-bit register file address (000h to FFFh). This is the destination address.

GIE Global Interrupt Enable bit.

kLiteral field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

label Label name.

mm The mode of the TBLPTR register for the table read and table write instructions.

Only used with table read and table write instructions:

*No change to register (such as TBLPTR with table reads and writes)

*+ Post-Increment register (such as TBLPTR with table reads and writes)

*- Post-Decrement register (such as TBLPTR with table reads and writes)

+* Pre-Increment register (such as TBLPTR with table reads and writes)

nThe relative address (2’s complement number) for relative branch instructions or the direct address for

Call/Branch and Return instructions.

PC Program Counter.

PCL Program Counter Low Byte.

PCH Program Counter High Byte.

PCLATH Program Counter High Byte Latch.

PCLATU Program Counter Upper Byte Latch.

PD Power-down bit.

PRODH Product of Multiply High Byte.

PRODL Product of Multiply Low Byte.

sFast Call/Return mode select bit

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

TBLPTR 21-bit Table Pointer (points to a program memory location).

TABLAT 8-bit Table Latch.

TO Time-out bit.

TOS Top-of-Stack.

uUnused or unchanged.

WDT Watchdog Timer.

WREG Working register (accumulator).

xDon’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for

compatibility with all Microchip software tools.

zs7-bit offset value for indirect addressing of register files (source).

zd7-bit offset value for indirect addressing of register files (destination).

{ } Optional argument.

[text] Indicates an indexed address.

(text) The contents of text.

[expr]<n> Specifies bit n of the register indicated by the pointer expr.

→Assigned to.

< > Register bit field.

∈In the set of.

italics User-defined term (font is Courier New).

PIC18F45J10 FAMILY

FIGURE 22-1: GENE RAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

15 10 9 8 7 0

d = 0 for result destination to be WREG register

OPCODE d a f (FILE #)

d = 1 for result destination to be file register (f)

a = 0 to force Access Bank

Bit-oriented file register operations

15 12 11 9 8 7 0

OPCODE b (BIT #) a f (FILE #)

b = 3-bit position of bit in file register (f)

Literal operations

15 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Byte to Byte move operations (2-word)

15 12 11 0

OPCODE f (Source FILE #)

CALL, GOTO and Branch operations

15 8 7 0

OPCODE n<7:0> (literal)

n = 20-bit immediate value

a = 1 for BSR to select bank

f = 8-bit file register address

a = 0 to force Access Bank

a = 1 for BSR to select bank

f = 8-bit file register address

15 12 11 0

1111 n<19:8> (literal)

15 12 11 0

1111 f (Destination FILE #)

f = 12-bit file register address

Control operations

Example Instruction

ADDWF MYREG, W, B

MOVFF MYREG1, MYREG2

BSF MYREG, bit, B

MOVLW 7Fh

GOTO Label

15 8 7 0

OPCODE n<7:0> (literal)

15 12 11 0

1111 n<19:8> (literal)

CALL MYFUNC

15 11 10 0

OPCODE n<10:0> (literal)

S = Fast bit

BRA MYFUNC

15 8 7 0

OPCODE n<7:0> (literal) BC MYFUNC

PIC18F45J10 FAMILY

TABLE 22-2: PIC18FXXXX INSTRUCTION SET

Mnemonic,

Operands Description Cycles 16-Bit Instruction Word Status

Affected Notes

MSb LSb

BYTE-ORIENTED OPERATIONS

ADDWF

ADDWFC

ANDWF

CLRF

COMF

CPFSEQ

CPFSGT

CPFSLT

DECF

DECFSZ

DCFSNZ

INCF

INCFSZ

INFSNZ

IORWF

MOVF

MOVFF

MOVWF

MULWF

NEGF

RLCF

RLNCF

RRCF

RRNCF

SETF

SUBFWB

SUBWF

SUBWFB

SWAPF

TSTFSZ

XORWF

f, d, a

f, a

f, d, a

f, a

f, d, a

fs, fd

f, a

f, d, a

f, a

f, d, a

f, a

f, d, a

Add WREG and f

Add WREG and Carry bit to f

AND WREG with f

Clear f

Complement f

Compare f with WREG, Skip =

Compare f with WREG, Skip >

Compare f with WREG, Skip <

Decrement f

Decrement f, Skip if 0

Decrement f, Skip if Not 0

Increment f

Increment f, Skip if 0

Increment f, Skip if Not 0

Inclusive OR WREG with f

Move f

Move fs (source) to 1st Word

fd (destination) 2nd Word

Move WREG to f

Multiply WREG with f

Negate f

Rotate Left f through Carry

Rotate Left f (No Carry)

Rotate Right f through Carry

Rotate Right f (No Carry)

Set f

Subtract f from WREG with

Borrow

Subtract WREG from f

Subtract WREG from f with

Borrow

Swap Nibbles in f

Test f, Skip if 0

Exclusive OR WREG with f

1 (2 or 3)

0010

0001

0110

0001

0110

0000

0010

0100

0010

0011

0100

0001

0101

1100

1111

0110

0000

0110

0011

0100

0011

0100

0110

0101

0011

0110

0001

01da

00da

01da

101a

11da

001a

010a

000a

01da

11da

10da

11da

10da

00da

ffff

111a

001a

110a

01da

00da

100a

01da

11da

10da

011a

10da

ffff

C, DC, Z, OV, N

Z, N

None

C, DC, Z, OV, N

None

C, DC, Z, OV, N

None

Z, N

None

C, DC, Z, OV, N

C, Z, N

Z, N

C, Z, N

Z, N

None

C, DC, Z, OV, N

None

Z, N

1, 2

1,2

1, 2

1, 2, 3, 4

1, 2

1, 2, 3, 4

1, 2

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

PIC18F45J10 FAMILY

BIT-ORIENTED OPERATIONS

BCF

BSF

BTFSC

BTFSS

BTG

f, b, a

f, d, a

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

Bit Toggle f

1 (2 or 3)

1001

1000

1011

1010

0111

bbba

ffff

None

1, 2

3, 4

1, 2

CONTROL OPERATIONS

BNC

BNN

BNOV

BNZ

BOV

BRA

CALL

CLRWDT

DAW

GOTO

NOP

POP

PUSH

RCALL

RESET

RETFIE

RETLW

RETURN

SLEEP

n, s

—

Branch if Carry

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

Call subroutine 1st Word

2nd Word

Clear Watchdog Timer

Decimal Adjust WREG

Go to address 1st Word

2nd Word

No Operation

Pop Top of Return Stack (TOS)

Push Top of Return Stack (TOS)

Relative Call

Software Device Reset

Return from Interrupt Enable

Return with Literal in WREG

Return from Subroutine

Go into Standby mode

1 (2)

1110

1101

1110

1111

0000

1110

1111

0000

1111

0000

1101

0000

0010

0110

0011

0111

0101

0001

0100

0nnn

0000

110s

kkkk

0000

1111

kkkk

0000

xxxx

0000

1nnn

0000

1100

0000

nnnn

kkkk

0000

kkkk

0000

xxxx

0000

nnnn

1111

0001

kkkk

0001

0000

nnnn

kkkk

0100

0111

kkkk

0000

xxxx

0110

0101

nnnn

1111

000s

kkkk

001s

0011

None

TO, PD

None

All

GIE/GIEH,

PEIE/GIEL

None

TO, PD

TABLE 22-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands Description Cycles 16-Bit Instruction Word Status

Affected Notes

MSb LSb

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

PIC18F45J10 FAMILY

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

f, k

Add Literal and WREG

AND Literal with WREG

Inclusive OR Literal with WREG

Move Literal (12-bit) 2nd Word

to FSR(f) 1st Word

Move Literal to BSR<3:0>

Move Literal to WREG

Multiply Literal with WREG

Return with Literal in WREG

Subtract WREG from Literal

Exclusive OR Literal with WREG

0000

1110

1111

0000

1111

1011

1001

1110

0000

0001

1110

1101

1100

1000

1010

kkkk

00ff

kkkk

0000

kkkk

C, DC, Z, OV, N

Z, N

None

C, DC, Z, OV, N

Z, N

DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS

TBLRD*

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read

Table Read with Post-Increment

Table Read with Post-Decrement

Table Read with Pre-Increment

Table Write

Table Write with Post-Increment

Table Write with Post-Decrement

Table Write with Pre-Increment

0000

1000

1001

1010

1011

1100

1101

1110

1111

None

TABLE 22-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands Description Cycles 16-Bit Instruction Word Status

Affected Notes

MSb LSb

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

PIC18F45J10 FAMILY

22.1.1 STANDARD INSTRUCTION SET

ADDLW ADD Literal to W

Syntax: ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1111 kkkk kkkk

Description: The contents of W are added to the

8-bit literal ‘k’ and the result is placed in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to W

Example: ADDLW 15h

Before Instruction

W = 10h

After Instruction

W = 25h

ADDWF ADD W to f

Syntax: ADDWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) + (f) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 01da ffff ffff

Description: Add W to register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: ADDWF REG, 0, 0

Before Instruction

W = 17h

REG = 0C2h

After Instruction

W = 0D9h

REG = 0C2h

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

PIC18F45J10 FAMILY

ADDWFC ADD W and Carry bit to f

Syntax: ADDWFC f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) + (f) + (C) → dest

Status Affected: N,OV, C, DC, Z

Encoding: 0010 00da ffff ffff

Description: Add W, the Carry flag and data memory

location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: ADDWFC REG, 0, 1

Before Instruction

Carry bit = 1

REG = 02h

W=4Dh

After Instruction

Carry bit = 0

REG = 02h

W = 50h

ANDLW AND Literal with W

Syntax: ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. k → W

Status Affected: N, Z

Encoding: 0000 1011 kkkk kkkk

Description: The contents of W are ANDed with the

8-bit literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’

Process

Data

Write to W

Example: ANDLW 05Fh

Before Instruction

W=A3h

After Instruction

W = 03h

PIC18F45J10 FAMILY

ANDWF AND W with f

Syntax: ANDWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) .AND. (f) → dest

Status Affected: N, Z

Encoding: 0001 01da ffff ffff

Description: The contents of W are ANDed with

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: ANDWF REG, 0, 0

Before Instruction

W = 17h

REG = C2h

After Instruction

W = 02h

REG = C2h

BC Bra nch if Carry

Syntax: BC n

Operands: -128 ≤ n ≤ 127

Operation: if Carry bit is ‘1’,

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0010 nnnn nnnn

Description: If the Carry bit is ‘1’, then the program

will branch.

The 2’s complement number, ‘2n’, is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BC 5

Before Instruction

PC = address (HERE)

After Instruction

If Carry = 1;

PC = address (HERE + 12)

If Carry = 0;

PC = address (HERE + 2)

PIC18F45J10 FAMILY

BCF Bit Clear f

Syntax: BCF f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation: 0 → f

Status Affected: None

Encoding: 1001 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is cleared.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example:BCF FLAG_REG, 7, 0

Before Instruction

FLAG_REG = C7h

After Instruction

FLAG_REG = 47h

BN Branch if Negative

Syntax: BN n

Operands: -128 ≤ n ≤ 127

Operation: if Negative bit is ‘1’,

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0110 nnnn nnnn

Description: If the Negative bit is ‘1’, then the

program will branch.

The 2’s complement number, ‘2n’, is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BN Jump

Before Instruction

PC = address (HERE)

After Instruction

If Negative = 1;

PC = address (Jump)

If Negative = 0;

PC = address (HERE + 2)

PIC18F45J10 FAMILY

BNC Branch if Not Carry

Syntax: BNC n

Operands: -128 ≤ n ≤ 127

Operation: if Carry bit is ‘0’,

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0011 nnnn nnnn

Description: If the Carry bit is ‘0’, then the program

will branch.

The 2’s complement number, ‘2n’, is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BNC Jump

Before Instruction

PC = address (HERE)

After Instruction

If Carry = 0;

PC = address (Jump)

If Carry = 1;

PC = address (HERE + 2)

BNN Branch if Not Negative

Syntax: BNN n

Operands: -128 ≤ n ≤ 127

Operation: if Negative bit is ‘0’,

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0111 nnnn nnnn

Description: If the Negative bit is ‘0’, then the

program will branch.

The 2’s complement number, ‘2n’, is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example:HERE BNN Jump

Before Instruction

PC = address (HERE)

After Instruction

If Negative = 0;

PC = address (Jump)

If Negative = 1;

PC = address (HERE + 2)

PIC18F45J10 FAMILY

BNOV Branch if Not Overflow

Syntax: BNOV n

Operands: -128 ≤ n ≤ 127

Operation: if Overflow bit is ‘0’,

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0101 nnnn nnnn

Description: If the Overflow bit is ‘0’, then the

program will branch.

The 2’s complement number, ‘2n’, is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BNOV Jump

Before Instruction

PC = address (HERE)

After Instruction

If Overflow = 0;

PC = address (Jump)

If Overflow = 1;

PC = address (HERE + 2)

BNZ Branch if Not Zero

Syntax: BNZ n

Operands: -128 ≤ n ≤ 127

Operation: if Zero bit is ‘0’,

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0001 nnnn nnnn

Description: If the Zero bit is ‘0’, then the program

will branch.

The 2’s complement number, ‘2n’, is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BNZ Jump

Before Instruction

PC = address (HERE)

After Instruction

If Zero = 0;

PC = address (Jump)

If Zero = 1;

PC = address (HERE + 2)

PIC18F45J10 FAMILY

BRA Unconditional Branch

Syntax: BRA n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1101 0nnn nnnn nnnn

Description: Add the 2’s complement number, ‘2n’, to

the PC. Since the PC will have

incremented to fetch the next instruction,

the new address will be PC + 2 + 2n. This

instruction is a two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

Example: HERE BRA Jump

Before Instruction

PC = address (HERE)

After Instruction

PC = address (Jump)

BSF Bit Set f

Syntax: BSF f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation: 1 → f

Status Affected: None

Encoding: 1000 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is set.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: BSF FLAG_REG, 7, 1

Before Instruction

FLAG_REG = 0Ah

After Instruction

FLAG_REG = 8Ah

PIC18F45J10 FAMILY

BTFSC Bit Test File, Skip if Clear

Syntax: BTFSC f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation: skip if (f) = 0

Status Affected: None

Encoding: 1011 bbba ffff ffff

Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next

instruction is skipped. If bit ‘b’ is ‘0’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates in

Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh).

See Section 22.2.3 “Byte-Orien ted and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE

FALSE

TRUE

BTFSC

FLAG, 1, 0

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0;

PC = address (TRUE)

If FLAG<1> = 1;

PC = address (FALSE)

BTFSS Bit Test File, Skip if Set

Syntax: BTFSS f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b < 7

a ∈ [0,1]

Operation: skip if (f) = 1

Status Affected: None

Encoding: 1010 bbba ffff ffff

Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next

instruction is skipped. If bit ‘b’ is ‘1’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh).

See Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructi o ns in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE

FALSE

TRUE

BTFSS

FLAG, 1, 0

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0;

PC = address (FALSE)

If FLAG<1> = 1;

PC = address (TRUE)

PIC18F45J10 FAMILY

BTG Bit Toggle f

Syntax: BTG f, b {,a}

Operands: 0 ≤ f ≤ 255

0 ≤ b < 7

a ∈ [0,1]

Operation: (f) → f

Status Affected: None

Encoding: 0111 bbba ffff ffff

Description: Bit ‘b’ in data memory location ‘f’ is

inverted.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Liter a l Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: BTG PORTC, 4, 0

Before Instruction:

PORTC = 0111 0101 [75h]

After Instruction:

PORTC = 0110 0101 [65h]

BOV Bra nch if Overf low

Syntax: BOV n

Operands: -128 ≤ n ≤ 127

Operation: if Overflow bit is ‘1’,

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0100 nnnn nnnn

Description: If the Overflow bit is ‘1’, then the

program will branch.

The 2’s complement number, ‘2n’, is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BOV Jump

Before Instruction

PC = address (HERE)

After Instruction

If Overflow = 1;

PC = address (Jump)

If Overflow = 0;

PC = address (HERE + 2)

PIC18F45J10 FAMILY

BZ Branch if Zero

Syntax: BZ n

Operands: -128 ≤ n ≤ 127

Operation: if Zero bit is ‘1’,

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1110 0000 nnnn nnnn

Description: If the Zero bit is ‘1’, then the program

will branch.

The 2’s complement number, ‘2n’, is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BZ Jump

Before Instruction

PC = address (HERE)

After Instruction

If Zero = 1;

PC = address (Jump)

If Zero = 0;

PC = address (HERE + 2)

CALL Subroutine Call

Syntax: CALL k {,s}

Operands: 0 ≤ k ≤ 1048575

s ∈ [0,1]

Operation: (PC) + 4 → TOS,

k → PC<20:1>;

if s = 1,

(W) → WS,

(STATUS) → STATUSS,

(BSR) → BSRS

Status Affected: None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111 110s

k19kkk k7kkk

kkkk kkkk0

kkkk8

Description: Subroutine call of entire 2-Mbyte

memory range. First, return address

(PC + 4) is pushed onto the return

stack. If ‘s’ = 1, the W, STATUS and

BSR registers are also pushed into their

respective shadow registers, WS,

STATUSS and BSRS. If ‘s’ = 0, no

update occurs (default). Then, the

20-bit value ‘k’ is loaded into PC<20:1>.

CALL is a two-cycle instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’<7:0>,

PUSH PC to

stack

Read literal

‘k’<19:8>,

Write to PC

operation

Example: HERE CALL THERE, 1

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE)

TOS = address (HERE + 4)

WS = W

BSRS = BSR

STATUSS = STATUS

PIC18F45J10 FAMILY

CLRF Clear f

Syntax: CLRF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: 000h → f,

1 → Z

Status Affected: Z

Encoding: 0110 101a ffff ffff

Description: Clears the contents of the specified

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: CLRF FLAG_REG, 1

Before Instruction

FLAG_REG = 5Ah

After Instruction

FLAG_REG = 00h

CLRWDT Clear Watchdog Timer

Syntax: CLRWDT

Operands: None

Operation: 000h → WDT,

000h → WDT postscaler,

1 → TO,

1 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0100

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets the

postscaler of the WDT. Status bits, TO

and PD, are set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

Process

Data

operation

Example: CLRWDT

Before Instruction

WDT Counter = ?

After Instruction

WDT Counter = 00h

WDT Postscaler = 0

TO =1

PD =1

PIC18F45J10 FAMILY

COMF Complement f

Syntax: COMF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) → dest

Status Affected: N, Z

Encoding: 0001 11da ffff ffff

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: COMF REG, 0, 0

Before Instruction

REG = 13h

After Instruction

REG = 13h

W=ECh

CPFSEQ Compare f with W, Skip if f = W

Syntax: CPFSEQ f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (f) – (W),

skip if (f) = (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 001a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If ‘f’ = W, then the fetched instruction is

discarded and a NOP is executed

instead, making this a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE CPFSEQ REG, 0

NEQUAL :

EQUAL :

Before Instruction

PC Address = HERE

W=?

REG = ?

After Instruction

If REG = W;

PC = Address (EQUAL)

If REG ≠ W;

PC = Address (NEQUAL)

PIC18F45J10 FAMILY

CPFSGT Compare f with W, Skip if f > W

Syntax: CPFSGT f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (f) – (W),

skip if (f) > (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 010a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of the W by

performing an unsigned subtraction.

If the contents of ‘f’ are greater than the

contents of WREG, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE CPFSGT REG, 0

NGREATER :

GREATER :

Before Instruction

PC = Address (HERE)

W= ?

After Instruction

If REG > W;

PC = Address (GREATER)

If REG ≤ W;

PC = Address (NGREATER)

CPFSLT Compare f with W, Skip if f < W

Syntax: CPFSLT f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (f) – (W),

skip if (f) < (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 000a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If the contents of ‘f’ are less than the

contents of W, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE CPFSLT REG, 1

NLESS :

LESS :

Before Instruction

PC = Address (HERE)

W= ?

After Instruction

If REG < W;

PC = Address (LESS)

If REG ≥ W;

PC = Address (NLESS)

PIC18F45J10 FAMILY

DAW Decimal Adjust W Register

Syntax: DAW

Operands: None

Operation: If [W<3:0> > 9] or [DC = 1] then,

(W<3:0>) + 6 → W<3:0>;

else,

(W<3:0>) → W<3:0>

If [W<7:4> + DC > 9] or [C = 1] then,

(W<7:4>) + 6 + DC → W<7:4>;

else,

(W<7:4>) + DC → W<7:4>

Status Affected: C

Encoding: 0000 0000 0000 0111

Description: DAW adjusts the eight-bit value in W,

resulting from the earlier addition of two

variables (each in packed BCD format)

and produces a correct packed BCD

result.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example 1:

DAW

Before Instruction

W=A5h

C=0

DC = 0

After Instruction

W = 05h

C=1

DC = 0

Example 2:

Before Instruction

W=CEh

C=0

DC = 0

After Instruction

W = 34h

C=1

DC = 0

DECF Decrement f

Syntax: DECF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – 1 → dest

Status Affected: C, DC, N, OV, Z

Encoding: 0000 01da ffff ffff

Description: Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: DECF CNT, 1, 0

Before Instruction

CNT = 01h

Z=0

After Instruction

CNT = 00h

Z=1

PIC18F45J10 FAMILY

DECFSZ Decrement f, Skip if 0

Syntax: DECFSZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – 1 → dest,

skip if result = 0

Status Affected: None

Encoding: 0010 11da ffff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE DECFSZ CNT, 1, 1

GOTO LOOP

CONTINUE

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT – 1

If CNT = 0;

PC = Address (CONTINUE)

If CNT ≠0;

PC = Address (HERE + 2)

DCFSNZ Decrement f, Skip if Not 0

Syntax: DCFSNZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – 1 → dest,

skip if result ≠ 0

Status Affected: None

Encoding: 0100 11da ffff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE DCFSNZ TEMP, 1, 0

ZERO :

NZERO :

Before Instruction

TEMP = ?

After Instruction

TEMP = TEMP – 1,

If TEMP = 0;

PC = Address (ZERO)

If TEMP ≠0;

PC = Address (NZERO)

PIC18F45J10 FAMILY

GOTO Unconditional Branch

Syntax: GOTO k

Operands: 0 ≤ k ≤ 1048575

Operation: k → PC<20:1>

Status Affected: None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111 1111

k19kkk k7kkk

kkkk kkkk0

kkkk8

Description: GOTO allows an unconditional branch

anywhere within entire

2-Mbyte memory range. The 20-bit

value ‘k’ is loaded into PC<20:1>. GOTO

is always a two-cycle instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’<7:0>,

operation

Read literal

‘k’<19:8>,

Write to PC

operation

Example: GOTO THERE

After Instruction

PC = Address (THERE)

INCF Increment f

Syntax: INCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) + 1 → dest

Status Affected: C, DC, N, OV, Z

Encoding: 0010 10da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: INCF CNT, 1, 0

Before Instruction

CNT = FFh

Z=0

C=?

DC = ?

After Instruction

CNT = 00h

Z=1

C=1

DC = 1

PIC18F45J10 FAMILY

INCFSZ Increment f, Skip if 0

Syntax: INCFSZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) + 1 → dest,

skip if result = 0

Status Affected: None

Encoding: 0011 11da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE INCFSZ CNT, 1, 0

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT + 1

If CNT = 0;

PC = Address (ZERO)

If CNT ≠0;

PC = Address (NZERO)

INFSNZ Increment f, Skip if Not 0

Syntax: INFSNZ f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) + 1 → dest,

skip if result ≠ 0

Status Affected: None

Encoding: 0100 10da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE INFSNZ REG, 1, 0

ZERO

NZERO

Before Instruction

PC = Address (HERE)

After Instruction

REG = REG + 1

If REG ≠0;

PC = Address (NZERO)

If REG = 0;

PC = Address (ZERO)

PIC18F45J10 FAMILY

IORLW Inclusive OR Literal with W

Syntax: IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → W

Status Affected: N, Z

Encoding: 0000 1001 kkkk kkkk

Description: The contents of W are ORed with the

eight-bit literal ‘k’. The result is placed in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to W

Example: IORLW 35h

Before Instruction

W=9Ah

After Instruction

W=BFh

IORWF Inclusive OR W with f

Syntax: IORWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) .OR. (f) → dest

Status Affected: N, Z

Encoding: 0001 00da ffff ffff

Description: Inclusive OR W with register ‘f’. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is placed back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: IORWF RESULT, 0, 1

Before Instruction

RESULT = 13h

W = 91h

After Instruction

RESULT = 13h

W = 93h

PIC18F45J10 FAMILY

LFSR Load FSR

Syntax: LFSR f, k

Operands: 0 ≤ f ≤ 2

0 ≤ k ≤ 4095

Operation: k → FSRf

Status Affected: None

Encoding: 1110

1111 1110

0000 00ff

k7kkk k11kkk

kkkk

Description: The 12-bit literal ‘k’ is loaded into the

File Select Register pointed to by ‘f’.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’ MSB

Process

Data

Write

literal ‘k’

MSB to

FSRfH

Decode Read literal

‘k’ LSB

Process

Data

Write literal

‘k’ to FSRfL

Example: LFSR 2, 3ABh

After Instruction

FSR2H = 03h

FSR2L = ABh

MOVF Move f

Syntax: MOVF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: f → dest

Status Affected: N, Z

Encoding: 0101 00da ffff ffff

Description: The contents of register ‘f’ are moved to

a destination dependent upon the

status of ‘d’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write W

Example: MOVF REG, 0, 0

Before Instruction

REG = 22h

W=FFh

After Instruction

REG = 22h

W = 22h

PIC18F45J10 FAMILY

MOVFF Move f to f

Syntax: MOVFF fs,fd

Operands: 0 ≤ fs ≤ 4095

0 ≤ fd ≤ 4095

Operation: (fs) → fd

Status Affected: None

Encoding:

1st word (source)

2nd word (destin.)

1100

1111 ffff

ffff ffff

ffff ffffs

ffffd

Description: The contents of source register ‘fs’ are

moved to destination register ‘fd’.

Location of source ‘fs’ can be anywhere

in the 4096-byte data space (000h to

FFFh) and location of destination ‘fd’

can also be anywhere from 000h to

FFFh.

Either source or destination can be W

(a useful special situation).

MOVFF is particularly useful for

transferring a data memory location to a

peripheral register (such as the transmit

buffer or an I/O port).

The MOVFF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

Words: 2

Cycles: 2 (3)

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

(src)

Process

Data

operation

Decode No

operation

No dummy

read

operation

Write

(dest)

Example: MOVFF REG1, REG2

Before Instruction

REG1 = 33h

REG2 = 11h

After Instruction

REG1 = 33h

REG2 = 33h

MOVLB Move L iteral to Low Nibble in BSR

Syntax: MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → BSR

Status Affected: None

Encoding: 0000 0001 kkkk kkkk

Description: The eight-bit literal ‘k’ is loaded into the

Bank Select Register (BSR). The value

of BSR<7:4> always remains ‘0’,

regardless of the value of k7:k4.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write literal

‘k’ to BSR

Example: MOVLB 5

Before Instruction

BSR Register = 02h

After Instruction

BSR Register = 05h

PIC18F45J10 FAMILY

MOVLW Move Literal to W

Syntax: MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → W

Status Affected: None

Encoding: 0000 1110 kkkk kkkk

Description: The eight-bit literal ‘k’ is loaded into W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to W

Example: MOVLW 5Ah

After Instruction

W=5Ah

MOVWF Move W to f

Syntax: MOVWF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (W) → f

Status Affected: None

Encoding: 0110 111a ffff ffff

Description: Move data from W to register ‘f’.

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index ed

Literal Offset Mod e” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: MOVWF REG, 0

Before Instruction

W=4Fh

REG = FFh

After Instruction

W=4Fh

REG = 4Fh

PIC18F45J10 FAMILY

MULLW Multiply Literal with W

Syntax: MULLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) x k → PRODH:PRODL

Status Affected: None

Encoding: 0000 1101 kkkk kkkk

Description: An unsigned multiplication is carried

out between the contents of W and the

8-bit literal ‘k’. The 16-bit result is

placed in the PRODH:PRODL register

pair. PRODH contains the high byte.

W is unchanged.

None of the Status flags are affected.

Note that neither overflow nor carry is

possible in this operation. A zero result

is possible but not detected.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write

registers

PRODH:

PRODL

Example: MULLW 0C4h

Before Instruction

W=E2h

PRODH = ?

PRODL = ?

After Instruction

W=E2h

PRODH = ADh

PRODL = 08h

MULWF Multiply W with f

Syntax: MULWF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: (W) x (f) → PRODH:PRODL

Status Affected: None

Encoding: 0000 001a ffff ffff

Description: An unsigned multiplication is carried

out between the contents of W and the

result is stored in the PRODH:PRODL

high byte. Both W and ‘f’ are

unchanged.

None of the Status flags are affected.

Note that neither overflow nor carry is

possible in this operation. A zero

result is possible but not detected.

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 22.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

registers

PRODH:

PRODL

Example: MULWF REG, 1

Before Instruction

W=C4h

REG = B5h

PRODH = ?

PRODL = ?

After Instruction

W=C4h

REG = B5h

PRODH = 8Ah

PRODL = 94h

PIC18F45J10 FAMILY

NEGF Negate f

Syntax: NEGF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: ( f ) + 1 → f

Status Affected: N, OV, C, DC, Z

Encoding: 0110 110a ffff ffff

Description: Location ‘f’ is negated using two’s

complement. The result is placed in the

data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Liter a l Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: NEGF REG, 1

Before Instruction

REG = 0011 1010 [3Ah]

After Instruction

REG = 1100 0110 [C6h]

NOP No Operation

Syntax: NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 0000

1111 0000

xxxx 0000

xxxx

Description: No operation.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

Example:

None.

PIC18F45J10 FAMILY

POP Pop Top of Return Stack

Syntax: POP

Operands: None

Operation: (TOS) → bit bucket

Status Affected: None

Encoding: 0000 0000 0000 0110

Description: The TOS value is pulled off the return

stack and is discarded. The TOS value

then becomes the previous value that

was pushed onto the return stack.

This instruction is provided to enable

the user to properly manage the return

stack to incorporate a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

POP TOS

value

operation

Example: POP

GOTO NEW

Before Instruction

TOS = 0031A2h

Stack (1 level down) = 014332h

After Instruction

TOS = 014332h

PC = NEW

PUSH Push Top of Return Stack

Syntax: PUSH

Operands: None

Operation: (PC + 2) → TOS

Status Affected: None

Encoding: 0000 0000 0000 0101

Description: The PC + 2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows implementing a

software stack by modifying TOS and

then pushing it onto the return stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode PUSH

PC + 2 onto

return stack

operation

Example: PUSH

Before Instruction

TOS = 345Ah

PC = 0124h

After Instruction

PC = 0126h

TOS = 0126h

Stack (1 level down) = 345Ah

PIC18F45J10 FAMILY

RCALL Relative Call

Syntax: RCALL n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC) + 2 → TOS,

(PC) + 2 + 2n → PC

Status Affected: None

Encoding: 1101 1nnn nnnn nnnn

Description: Subroutine call with a jump up to 1K

from the current location. First, return

address (PC + 2) is pushed onto the

stack. Then, add the 2’s complement

number, ‘2n’, to the PC. Since the PC

will have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a

two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

PUSH PC to

stack

Process

Data

Write to PC

operation

Example: HERE RCALL Jump

Before Instruction

PC = Address (HERE)

After Instruction

PC = Address (Jump)

TOS = Address (HERE + 2)

RESET Reset

Syntax: RESET

Operands: None

Operation: Reset all registers and flags that are

affected by a MCLR Reset.

Status Affected: All

Encoding: 0000 0000 1111 1111

Description: This instruction provides a way to

execute a MCLR Reset in software.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Start

Reset

operation

Example: RESET

After Instruction

Registers = Reset Value

Flags* = Reset Value

PIC18F45J10 FAMILY

RETFIE Return from Interrupt

Syntax: RETFIE {s}

Operands: s ∈ [0,1]

Operation: (TOS) → PC,

1 → GIE/GIEH or PEIE/GIEL;

if s = 1,

(WS) → W,

(STATUSS) → STATUS,

(BSRS) → BSR,

PCLATU, PCLATH are unchanged

Status Affected: GIE/GIEH, PEIE/GIEL.

Encoding: 0000 0000 0001 000s

Description: Return from interrupt. Stack is popped

and Top-of-Stack (TOS) is loaded into

the PC. Interrupts are enabled by

setting either the high or low-priority

global interrupt enable bit. If ‘s’ = 1, the

contents of the shadow registers, WS,

STATUSS and BSRS, are loaded into

their corresponding registers, W,

STATUS and BSR. If ‘s’ = 0, no update

of these registers occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

POP PC

from stack

Set GIEH or

GIEL

operation

Example: RETFIE 1

After Interrupt

PC = TOS

W=WS

BSR = BSRS

STATUS = STATUSS

GIE/GIEH, PEIE/GIEL = 1

RETLW Return Literal to W

Syntax: RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → W,

(TOS) → PC,

PCLATU, PCLATH are unchanged

Status Affected: None

Encoding: 0000 1100 kkkk kkkk

Description: W is loaded with the eight-bit literal ‘k’.

The program counter is loaded from the

top of the stack (the return address).

The high address latch (PCLATH)

remains unchanged.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

POP PC

from stack,

Write to W

operation

Example:

CALL TABLE ; W contains table

; offset value

; W now has

; table value

TABLE

ADDWF PCL ; W = offset

RETLW k0 ; Begin table

RETLW k1 ;

:RETLW kn ; End of table

Before Instruction

W = 07h

After Instruction

W = value of kn

PIC18F45J10 FAMILY

RETURN Return from Subroutine

Syntax: RETURN {s}

Operands: s ∈ [0,1]

Operation: (TOS) → PC;

if s = 1,

(WS) → W,

(STATUSS) → STATUS,

(BSRS) → BSR,

PCLATU, PCLATH are unchanged

Status Affected: None

Encoding: 0000 0000 0001 001s

Description: Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter. If

‘s’= 1, the contents of the shadow

registers, WS, STATUSS and BSRS,

are loaded into their corresponding

registers, W, STATUS and BSR. If

‘s’ = 0, no update of these registers

occurs (default).

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

Process

Data

POP PC

from stack

operation

Example: RETURN

After Instruction:

PC = TOS

RLCF Rotate Left f through Carry

Syntax: RLCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n + 1>,

(f<7>) → C,

Status Affected: C, N, Z

Encoding: 0011 01da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used to

select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 22.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: RLCF REG, 0, 0

Before Instruction

REG = 1110 0110

C=0

After Instruction

REG = 1110 0110

W=1100 1100

C=1

Cregister f

PIC18F45J10 FAMILY

RLNCF Rotate Left f (No Carry)

Syntax: RLNCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n + 1>,

(f<7>) → dest<0>

Status Affected: N, Z

Encoding: 0100 01da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the left. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructi ons in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: RLNCF REG, 1, 0

Before Instruction

REG = 1010 1011

After Instruction

REG = 0101 0111

RRCF Rot ate Right f through Carry

Syntax: RRCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n – 1>,

(f<0>) → C,

Status Affected: C, N, Z

Encoding: 0011 00da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in W.

If ‘d’ is ‘1’, the result is placed back in

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: RRCF REG, 0, 0

Before Instruction

REG = 1110 0110

C=0

After Instruction

REG = 1110 0110

W=0111 0011

C=0

Cregister f

PIC18F45J10 FAMILY

RRNCF Rotate Right f (No Carry)

Syntax: RRNCF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<n>) → dest<n – 1>,

(f<0>) → dest<7>

Status Affected: N, Z

Encoding: 0100 00da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the right. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank will be

selected, overriding the BSR value. If ‘a’

is ‘1’, then the bank will be selected as

per the BSR value (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example 1: RRNCF REG, 1, 0

Before Instruction

REG = 1101 0111

After Instruction

REG = 1110 1011

Example 2: RRNCF REG, 0, 0

Before Instruction

W=?

REG = 1101 0111

After Instruction

W=1110 1011

REG = 1101 0111

SETF Set f

Syntax: SETF f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: FFh → f

Status Affected: None

Encoding: 0110 100a ffff ffff

Description: The contents of the specified register

are set to FFh.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: SETF REG, 1

Before Instruction

REG = 5Ah

After Instruction

REG = FFh

PIC18F45J10 FAMILY

SLEEP Enter Sleep mode

Syntax: SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT postscaler,

1 → TO,

0 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0011

Description: The Power-Down status bit (PD) is

cleared. The Time-out status bit (TO)

is set. Watchdog Timer and its

postscaler are cleared.

The processor is put into Sleep mode

with the oscillator stopped.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

Process

Data

Go to

Sleep

Example: SLEEP

Before Instruction

TO =?

PD =?

After Instruction

TO =1 †

PD =0

† If WDT causes wake-up, this bit is cleared.

SUBFWB Subtract f from W with Borrow

Syntax: SUBFWB f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) – (f) – (C) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 01da ffff ffff

Description: Subtract register ‘f’ and Carry flag

(borrow) from W (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored in

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 22.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example 1: SUBFWB REG, 1, 0

Before Instruction

REG = 3

W=2

C=1

After Instruction

REG = FF

W=2

C=0

Z=0

N = 1 ; result is negative

Example 2: SUBFWB REG, 0, 0

Before Instruction

REG = 2

W=5

C=1

After Instruction

REG = 2

W=3

C=1

Z=0

N = 0 ; result is positive

Example 3: SUBFWB REG, 1, 0

Before Instruction

REG = 1

W=2

C=0

After Instruction

REG = 0

W=2

C=1

Z = 1 ; result is zero

N=0

PIC18F45J10 FAMILY

SUBLW Subtract W from Literal

Syntax: SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k – (W) → W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1000 kkkk kkkk

Description W is subtracted from the eight-bit

literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to W

Example 1: SUBLW 02h

Before Instruction

W = 01h

C=?

After Instruction

W = 01h

C = 1 ; result is positive

Z=0

N=0

Example 2: SUBLW 02h

Before Instruction

W = 02h

C=?

After Instruction

W = 00h

C = 1 ; result is zero

Z=1

N=0

Example 3: SUBLW 02h

Before Instruction

W = 03h

C=?

After Instruction

W = FFh ; (2’s complement)

C = 0 ; result is negative

Z=0

N=1

SUBWF Subtract W from f

Syntax: SUBWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – (W) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 11da ffff ffff

Description: Subtract W from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 22.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example 1: SUBWF REG, 1, 0

Before Instruction

REG = 3

W=2

C=?

After Instruction

REG = 1

W=2

C = 1 ; result is positive

Z=0

N=0

Example 2: SUBWF REG, 0, 0

Before Instruction

REG = 2

W=2

C=?

After Instruction

REG = 2

W=0

C=1; result is zero

Z=1

N=0

Example 3: SUBWF REG, 1, 0

Before Instruction

REG = 1

W=2

C=?

After Instruction

REG = FFh ;(2’s complement)

W=2

C = 0 ; result is negative

Z=0

N=1

PIC18F45J10 FAMILY

SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f) – (W) – (C) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 10da ffff ffff

Description: Subtract W and the Carry flag (borrow)

from register ‘f’ (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example 1: SUBWFB REG, 1, 0

Before Instruction

REG = 19h (0001 1001)

W=0Dh(0000 1101)

C=1

After Instruction

REG = 0Ch (0000 1011)

W=0Dh(0000 1101)

C=1

Z=0

N = 0 ; result is positive

Example 2: SUBWFB REG, 0, 0

Before Instruction

REG = 1Bh (0001 1011)

W=1Ah(0001 1010)

C=0

After Instruction

REG = 1Bh (0001 1011)

W = 00h

C=1

Z = 1 ; result is zero

N=0

Example 3: SUBWFB REG, 1, 0

Before Instruction

REG = 03h (0000 0011)

W=0Eh(0000 1101)

C=1

After Instruction

REG = F5h (1111 0100)

; [2’s comp]

W=0Eh(0000 1101)

C=0

Z=0

N = 1 ; result is negative

SWAPF Swap f

Syntax: SWAPF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (f<3:0>) → dest<7:4>,

(f<7:4>) → dest<3:0>

Status Affected: None

Encoding: 0011 10da ffff ffff

Description: The upper and lower nibbles of register

‘f’ are exchanged. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Index e d

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: SWAPF REG, 1, 0

Before Instruction

REG = 53h

After Instruction

REG = 35h

PIC18F45J10 FAMILY

TBLRD Table Read

Syntax: TBLRD ( *; *+; *-; +*)

Operands: None

Operation: if TBLRD *,

(Prog Mem (TBLPTR)) → TABLAT,

TBLPTR – No Change;

if TBLRD *+,

(Prog Mem (TBLPTR)) → TABLAT,

(TBLPTR) + 1 → TBLPTR;

if TBLRD *-,

(Prog Mem (TBLPTR)) → TABLAT,

(TBLPTR) – 1 → TBLPTR;

if TBLRD +*,

(TBLPTR) + 1 → TBLPTR,

(Prog Mem (TBLPTR)) → TABLAT

Status Affected: None

Encoding: 0000 0000 0000 10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description: This instruction is used to read the contents

of Program Memory (P.M.). To address the

program memory, a pointer called Table

Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory. TBLPTR

has a 2-Mbyte address range.

TBLPTR[0] = 0: Least Significant Byte

of Program Memory

Word

TBLPTR[0] = 1: Most Significant Byte

of Program Memory

Word

The TBLRD instruction can modify the value

of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

No operation

(Read Program

Memory)

operation

No operation

(Write TABLAT)

TBLRD Table Read (Continued)

Example 1: TBLRD *+ ;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

MEMORY (00A356h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 00A357h

Example 2: TBLRD +* ;

Before Instruction

TABLAT = AAh

TBLPTR = 01A357h

MEMORY (01A357h) = 12h

MEMORY (01A358h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 01A358h

PIC18F45J10 FAMILY

TBLWT Table Write

Syntax: TBLWT ( *; *+; *-; +*)

Operands: None

Operation: if TBLWT *,

(TABLAT) → Holding Register,

TBLPTR – No Change;

if TBLWT *+,

(TABLAT) → Holding Register,

(TBLPTR) + 1 → TBLPTR;

if TBLWT *-,

(TABLAT) → Holding Register,

(TBLPTR) – 1 → TBLPTR;

if TBLWT +*,

(TBLPTR) + 1 → TBLPTR,

(TABLAT) → Holding Register

Status Affected: None

Encoding: 0000 0000 0000 11nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description: This instruction uses the 3 LSBs of

TBLPTR to determine which of the

8 holding registers the TABLAT is written

to. The holding registers are used to

program the contents of Program

Memory (P.M.). (Refer to Section 7.0

“Flash Program Memory” for additional

details on programming Flash memory.)

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory.

TBLPTR has a 2-MByte address range.

The LSb of the TBLPTR selects which

byte of the program memory location to

access.

TBLPTR[0] = 0: Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1: Most Significant

Byte of Program

Memory Word

The TBLWT instruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

(Read

TABLAT)

operation

(Write to

Holding

TBLWT Table Write (Continued)

Example 1: TBLWT *+;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

HOLDING REGISTER

(00A356h) = FFh

After Instructions (table write completion)

TABLAT = 55h

TBLPTR = 00A357h

HOLDING REGISTER

(00A356h) = 55h

Example 2: TBLWT +*;

Before Instruction

TABLAT = 34h

TBLPTR = 01389Ah

HOLDING REGISTER

(01389Ah) = FFh

HOLDING REGISTER

(01389Bh) = FFh

After Instruction (table write completion)

TABLAT = 34h

TBLPTR = 01389Bh

HOLDING REGISTER

(01389Ah) = FFh

HOLDING REGISTER

(01389Bh) = 34h

PIC18F45J10 FAMILY

TSTFSZ Test f, Skip if 0

Syntax: TSTFSZ f {,a}

Operands: 0 ≤ f ≤ 255

a ∈ [0,1]

Operation: skip if f = 0

Status Affected: None

Encoding: 0110 011a ffff ffff

Description: If ‘f’ = 0, the next instruction fetched

during the current instruction execution

is discarded and a NOP is executed,

making this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE TSTFSZ CNT, 1

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

If CNT = 00h,

PC = Address (ZERO)

If CNT ≠00h,

PC = Address (NZERO)

XORLW Exclusive OR Literal with W

Syntax: XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → W

Status Affected: N, Z

Encoding: 0000 1010 kkkk kkkk

Description: The contents of W are XORed with

the 8-bit literal ‘k’. The result is placed

in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to W

Example: XORLW 0AFh

Before Instruction

W=B5h

After Instruction

W=1Ah

PIC18F45J10 FAMILY

XORWF Exclusive OR W with f

Syntax: XORWF f {,d {,a}}

Operands: 0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation: (W) .XOR. (f) → dest

Status Affected: N, Z

Encoding: 0001 10da ffff ffff

Description: Exclusive OR the contents of W with

in W. If ‘d’ is ‘1’, the result is stored back

in the register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: XORWF REG, 1, 0

Before Instruction

REG = AFh

W=B5h

After Instruction

REG = 1Ah

W=B5h

PIC18F45J10 FAMILY

22.2 Extended Instructio n Set

In addition to the standard 75 instructions of the PIC18

instruction set, PIC18F45J10 family devices also

provide an optional extension to the core CPU function-

ality. The added features include eight additional

instructions that augment indirect and indexed

addressing operations and the implementation of

Indexed Literal Offset Addressing mode for many of the

standard PIC18 instructions.

The additional features of the extended instruction set

are disabled by default. To enable them, users must set

the XINST Configuration bit.

The instructions in the extended set can all be

classified as literal operations, which either manipulate

the File Select Registers, or use them for indexed

addressing. Two of the instructions, ADDFSR and

SUBFSR, each have an additional special instantiation

for using FSR2. These versions (ADDULNK and

SUBULNK) allow for automatic return after execution.

The extended instructions are specifically implemented

to optimize re-entrant program code (that is, code that

is recursive or that uses a software stack) written in

high-level languages, particularly C. Among other

things, they allow users working in high-level

languages to perform certain operations on data

structures more efficiently. These include:

• dynamic allocation and deallocation of software

stack space when entering and leaving

subroutines

• Function Pointer invocation

• Software Stack Pointer manipulation

• manipulation of variables located in a software

stack

A summary of the instructions in the extended instruc-

tion set is provided in Table 22-3. Detailed descriptions

are provided in Section 22.2.2 “Extended Instruction

Set”. The opcode field descriptions in Table 22-1

(page 250) apply to both the standard and extended

PIC18 instruction sets.

22.2.1 EXTENDED INSTRUCTION SYNTAX

Most of the extended instructions use indexed argu-

ments, using one of the File Select Registers and some

offset to specify a source or destination register. When

an argument for an instruction serves as part of

indexed addressing, it is enclosed in square brackets

(“[ ]”). This is done to indicate that the argument is used

as an index or offset. MPASM™ Assembler will flag an

error if it determines that an index or offset value is not

bracketed.

When the extended instruction set is enabled, brackets

are also used to indicate index arguments in byte-

oriented and bit-oriented instructions. This is in addition

to other changes in their syntax. For more details, see

Section 22.2.3.1 “Extended Instruction Syntax with

Standard PIC18 Commands”.

TABLE 22-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

Note: The instruction set extension and the

Indexed Literal Offset Addressing mode

were designed for optimizing applications

written in C; the user may likely never use

these instructions directly in assembler.

The syntax for these commands is pro-

vided as a reference for users who may be

reviewing code that has been generated

by a compiler.

Note: In the past, square brackets have been

used to denote optional arguments in the

PIC18 and earlier instruction sets. In this

text and going forward, optional

arguments are denoted by braces (“{ }”).

Mnemonic,

Operands Description Cycles 16-Bit Instruction Word Status

Affected

MSb LSb

ADDFSR

ADDULNK

CALLW

MOVSF

MOVSS

PUSHL

SUBFSR

SUBULNK

f, k

zs, fd

zs, zd

f, k

Add Literal to FSR

Add Literal to FSR2 and Return

Call Subroutine using WREG

Move zs (source) to 1st Word

fd (destination) 2nd Word

Move zs (source) to 1st Word

zd (destination) 2nd Word

Store Literal at FSR2,

Decrement FSR2

Subtract Literal from FSR

Subtract Literal from FSR2 and

Return

1110

0000

1110

1111

1110

1111

1110

1000

0000

1011

ffff

1011

xxxx

1010

1001

ffkk

11kk

0001

0zzz

ffff

1zzz

xzzz

kkkk

ffkk

11kk

kkkk

0100

zzzz

ffff

zzzz

kkkk

None

PIC18F45J10 FAMILY

22.2.2 EXTENDED INSTRUCTION SET

ADDFSR Add Literal to FSR

Syntax: ADDFSR f, k

Operands: 0 ≤ k ≤ 63

f ∈ [ 0, 1, 2 ]

Operation: FSR(f) + k → FSR(f)

Status Affected: None

Encoding: 1110 1000 ffkk kkkk

Description: The 6-bit literal ‘k’ is added to the

contents of the FSR specified by ‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to

FSR

Example: ADDFSR 2, 23h

Before Instruction

FSR2 = 03FFh

After Instruction

FSR2 = 0422h

ADDULNK Ad d Lit e ral t o FSR 2 an d R e turn

Syntax: ADDULNK k

Operands: 0 ≤ k ≤ 63

Operation: FSR2 + k → FSR2,

(TOS) → PC

Status Affected: None

Encoding: 1110 1000 11kk kkkk

Description: The 6-bit literal ‘k’ is added to the

contents of FSR2. A RETURN is then

executed by loading the PC with the

TOS.

The instruction takes two cycles to

execute; a NOP is performed during

the second cycle.

This may be thought of as a special

case of the ADDFSR instruction,

where f = 3 (binary ‘11’); it operates

only on FSR2.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to

FSR

Operation

Example: ADDULNK 23h

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 0422h

PC = (TOS)

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

PIC18F45J10 FAMILY

CALLW Subroutine Call Using WREG

Syntax: CALLW

Operands: None

Operation: (PC + 2) → TOS,

(W) → PCL,

(PCLATH) → PCH,

(PCLATU) → PCU

Status Affected: None

Encoding: 0000 0000 0001 0100

Description First, the return address (PC + 2) is

pushed onto the return stack. Next, the

contents of W are written to PCL; the

existing value is discarded. Then, the

contents of PCLATH and PCLATU are

latched into PCH and PCU,

respectively. The second cycle is

executed as a NOP instruction while the

new next instruction is fetched.

Unlike CALL, there is no option to

update W, STATUS or BSR.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

WREG

PUSH PC to

stack

operation

Example: HERE CALLW

Before Instruction

PC = address (HERE)

PCLATH = 10h

PCLATU = 00h

W = 06h

After Instruction

PC = 001006h

TOS = address (HERE + 2)

PCLATH = 10h

PCLATU = 00h

W = 06h

MOVSF Move Indexed to f

Syntax: MOVSF [zs], fd

Operands: 0 ≤ zs ≤ 127

0 ≤ fd ≤ 4095

Operation: ((FSR2) + zs) → fd

Status Affected: None

Encoding:

1st word (source)

2nd word (destin.)

1110

1111 1011

ffff 0zzz

ffff zzzzs

ffffd

Description: The contents of the source register are

moved to destination register ‘fd’. The

actual address of the source register is

determined by adding the 7-bit literal

offset ‘zs’ in the first word to the value of

FSR2. The address of the destination

‘fd’ in the second word. Both addresses

can be anywhere in the 4096-byte data

space (000h to FFFh).

The MOVSF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Determine

source addr

Determine

source addr

Read

source reg

Decode No

operation

No dummy

read

operation

Write

(dest)

Example: MOVSF [05h], REG2

Before Instruction

FSR2 = 80h

Contents

of 85h = 33h

REG2 = 11h

After Instruction

FSR2 = 80h

Contents

of 85h = 33h

REG2 = 33h

PIC18F45J10 FAMILY

MOVSS Move Indexed to Indexed

Syntax: MOVSS [zs], [zd]

Operands: 0 ≤ zs ≤ 127

0 ≤ zd ≤ 127

Operation: ((FSR2) + zs) → ((FSR2) + zd)

Status Affected: None

Encoding:

1st word (source)

2nd word (dest.)

1110

1111 1011

xxxx 1zzz

xzzz zzzzs

zzzzd

Description The contents of the source register are

moved to the destination register. The

addresses of the source and destination

registers are determined by adding the

7-bit literal offsets ‘zs’ or ‘zd’,

respectively, to the value of FSR2. Both

registers can be located anywhere in

the 4096-byte data memory space

(000h to FFFh).

The MOVSS instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h. If the

resultant destination address points to

an indirect addressing register, the

instruction will execute as a NOP.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Determine

source addr

Determine

source addr

Read

source reg

Decode Determine

dest addr

Determine

dest addr

Write

to dest reg

Example: MOVSS [05h], [06h]

Before Instruction

FSR2 = 80h

Contents

of 85h = 33h

Contents

of 86h = 11h

After Instruction

FSR2 = 80h

Contents

of 85h = 33h

Contents

of 86h = 33h

PUSHL

Store Literal at FSR2, Decrement FSR2

Syntax: PUSHL k

Operands: 0 ≤ k ≤ 255

Operation: k → (FSR2),

FSR2 – 1 → FSR2

Status Affected: None

Encoding: 1111 1010 kkkk kkkk

Description: The 8-bit literal ‘k’ is written to the data

memory address specified by FSR2. FSR2

is decremented by 1 after the operation.

This instruction allows users to push values

onto a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

data

Write to

destination

Example: PUSHL 08h

Before Instruction

FSR2H:FSR2L = 01ECh

Memory (01ECh) = 00h

After Instruction

FSR2H:FSR2L = 01EBh

Memory (01ECh) = 08h

PIC18F45J10 FAMILY

SUBFSR Subtract Literal from FSR

Syntax: SUBFSR f, k

Operands: 0 ≤ k ≤ 63

f ∈ [ 0, 1, 2 ]

Operation: FSR(f) – k → FSRf

Status Affected: None

Encoding: 1110 1001 ffkk kkkk

Description: The 6-bit literal ‘k’ is subtracted from

the contents of the FSR specified by

‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: SUBFSR 2, 23h

Before Instruction

FSR2 = 03FFh

After Instruction

FSR2 = 03DCh

SUBULNK

Subtract Literal from FSR2 and Return

Syntax: SUBULNK k

Operands: 0 ≤ k ≤ 63

Operation: FSR2 – k → FSR2

(TOS) → PC

Status Affected: None

Encoding: 1110 1001 11kk kkkk

Description: The 6-bit literal ‘k’ is subtracted from the

contents of the FSR2. A RETURN is then

executed by loading the PC with the TOS.

The instruction takes two cycles to

execute; a NOP is performed during the

second cycle.

This may be thought of as a special case of

the SUBFSR instruction, where f = 3 (binary

‘11’); it operates only on FSR2.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Operation

Example: SUBULNK 23h

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 03DCh

PC = (TOS)

PIC18F45J10 FAMILY

22.2.3 BYTE-ORIENTED AND

BIT-ORIENTED INSTRUCTIONS IN

INDEXED LITERAL OFFSET MODE

In addition to eight new commands in the extended set,

enabling the extended instruction set also enables

Indexed Literal Offset Addressing mode (Section 6.5.1

“Indexed Addressing with Literal Offset”). This has

a significant impact on the way that many commands of

the standard PIC18 instruction set are interpreted.

When the extended set is disabled, addresses embed-

ded in opcodes are treated as literal memory locations:

either as a location in the Access Bank (‘a’ = 0), or in a

GPR bank designated by the BSR (‘a’ = 1). When the

extended instruction set is enabled and ‘a’ = 0, how-

ever, a file register argument of 5Fh or less is

interpreted as an offset from the pointer value in FSR2

and not as a literal address. For practical purposes, this

means that all instructions that use the Access RAM bit

as an argument – that is, all byte-oriented and bit-

oriented instructions, or almost half of the core PIC18

instructions – may behave differently when the

extended instruction set is enabled.

When the content of FSR2 is 00h, the boundaries of the

Access RAM are essentially remapped to their original

values. This may be useful in creating backward

compatible code. If this technique is used, it may be

necessary to save the value of FSR2 and restore it

when moving back and forth between C and assembly

routines in order to preserve the Stack Pointer. Users

must also keep in mind the syntax requirements of the

extended instruction set (see Section 22.2.3.1

“Extended Instruction Syntax with Standard PIC18

Commands”).

Although the Indexed Literal Offset Addressing mode

can be very useful for dynamic stack and pointer

manipulation, it can also be very annoying if a simple

arithmetic operation is carried out on the wrong

gramming must keep in mind that, when the extended

instruction set is enabled, register addresses of 5Fh or

less are used for Indexed Literal Offset Addressing.

Representative examples of typical byte-oriented and

bit-oriented instructions in the Indexed Literal Offset

Addressing mode are provided on the following page to

show how execution is affected. The operand condi-

tions shown in the examples are applicable to all

instructions of these types.

22.2.3.1 Extended Instruction Syntax with

Standard PIC18 Commands

When the extended instruction set is enabled, the file

bit-oriented commands is replaced with the literal offset

value, ‘k’. As already noted, this occurs only when ‘f’ is

less than or equal to 5Fh. When an offset value is used,

it must be indicated by square brackets (“[ ]”). As with

the extended instructions, the use of brackets indicates

to the compiler that the value is to be interpreted as an

index or an offset. Omitting the brackets, or using a

value greater than 5Fh within brackets, will generate an

error in the MPASM Assembler.

If the index argument is properly bracketed for Indexed

Literal Offset Addressing, the Access RAM argument is

never specified; it will automatically be assumed to be

‘0’. This is in contrast to standard operation (extended

instruction set disabled) when ‘a’ is set on the basis of

the target address. Declaring the Access RAM bit in

this mode will also generate an error in the MPASM

Assembler.

The destination argument, ‘d’, functions as before.

Refer to the MPLAB® IDE, MPASM™ or MPLAB C18

documentation for information on enabling Extended

Instruction set support

22.2.4 CONSIDERATIONS WHEN

ENABLING THE EXTENDED

INSTRUCTION SET

It is important to note that the extensions to the instruc-

tion set may not be beneficial to all users. In particular,

users who are not writing code that uses a software

stack may not benefit from using the extensions to the

instruction set.

Additionally, the Indexed Literal Offset Addressing

mode may create issues with legacy applications

written to the PIC18 assembler. This is because

instructions in the legacy code may attempt to address

registers in the Access Bank below 5Fh. Since these

addresses are interpreted as literal offsets to FSR2

when the instruction set extension is enabled, the

application may read or write to the wrong data

addresses.

When porting an application to the PIC18F45J10

family, it is very important to consider the type of code.

A large, re-entrant application that is written in ‘C’ and

would benefit from efficient compilation will do well

when using the instruction set extensions. Legacy

applications that heavily use the Access Bank will most

likely not benefit from using the extended instruction

set.

Note: Enabling the PIC18 instruction set

extension may cause legacy applications

to behave erratically or fail entirely.

PIC18F45J10 FAMILY

ADDWF ADD W to Indexed

(Indexed Literal Offset mode)

Syntax: ADDWF [k] {,d}

Operands: 0 ≤ k ≤ 95

d ∈ [0,1]

Operation: (W) + ((FSR2) + k) → dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 01d0 kkkk kkkk

Description: The contents of W are added to the

contents of the register indicated by

FSR2, offset by the value ‘k’.

If ‘d’ is ‘0’, the result is stored in W. If ‘d’

is ‘1’, the result is stored back in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

Data

Write to

destination

Example: ADDWF [OFST] , 0

Before Instruction

W = 17h

OFST = 2Ch

FSR2 = 0A00h

Contents

of 0A2Ch = 20h

After Instruction

W = 37h

Contents

of 0A2Ch = 20h

BSF Bit Set Indexed

(Indexed Literal Offset mode)

Syntax: BSF [k], b

Operands: 0 ≤ f ≤ 95

0 ≤ b ≤ 7

Operation: 1 → ((FSR2) + k)

Status Affected: None

Encoding: 1000 bbb0 kkkk kkkk

Description: Bit ‘b’ of the register indicated by FSR2,

offset by the value ‘k’, is set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: BSF [FLAG_OFST], 7

Before Instruction

FLAG_OFST = 0Ah

FSR2 = 0A00h

Contents

of 0A0Ah = 55h

After Instruction

Contents

of 0A0Ah = D5h

SETF Set Indexed

(Indexed Literal Offset mode)

Syntax: SETF [k]

Operands: 0 ≤ k ≤ 95

Operation: FFh → ((FSR2) + k)

Status Affected: None

Encoding: 0110 1000 kkkk kkkk

Description: The contents of the register indicated by

FSR2, offset by ‘k’, are set to FFh.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

Data

Write

Example: SETF [OFST]

Before Instruction

OFST = 2Ch

FSR2 = 0A00h

Contents

of 0A2Ch = 00h

After Instruction

Contents

of 0A2Ch = FFh

PIC18F45J10 FAMILY

22.2.5 SPECIAL CONSIDERATIONS WITH

MICROCHIP MPLAB® IDE TOOLS

The latest versions of Microchip’s software tools have

been designed to fully support the extended instruction

set of the PIC18F45J10 family of devices. This includes

the MPLAB C18 C compiler, MPASM assembly lan-

guage and MPLAB Integrated Development

Environment (IDE).

When selecting a target device for software

development, MPLAB IDE will automatically set default

Configuration bits for that device. The default setting for

the XINST Configuration bit is ‘0’, disabling the

extended instruction set and Indexed Literal Offset

Addressing mode. For proper execution of applications

developed to take advantage of the extended

instruction set, XINST must be set during

programming.

To develop software for the extended instruction set,

the user must enable support for the instructions and

the Indexed Addressing mode in their language tool(s).

Depending on the environment being used, this may be

done in several ways:

• A menu option, or dialog box within the

environment, that allows the user to configure the

language tool and its settings for the project

• A command line option

• A directive in the source code

These options vary between different compilers,

assemblers and development environments. Users are

encouraged to review the documentation accompany-

ing their development systems for the appropriate

information.

PIC18F45J10 FAMILY

23.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers are supported with a full

range of hardware and software development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C18 and MPLAB C30 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Programmers

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

23.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Visual device initializer for easy register

initialization

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC18F45J10 FAMILY

23.2 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel® standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

23.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC18 and PIC24 families of microcon-

trollers and the dsPIC30 and dsPIC33 family of digital

signal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

23.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

23.5 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

• MPLAB IDE compatibility

23.6 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

PIC18F45J10 FAMILY

23.7 MPLAB ICE 2000

High-Performance

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows® 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

23.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE probe is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB IDE, new devices will be supported,

and new features will be added, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

23.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial ProgrammingTM (ICSPTM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

23.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

PIC18F45J10 FAMILY

23.11 PICSTART Plus Development

Programmer

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

23.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash memory microcontrollers. The PICkit 2 Starter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler, and is designed to help get up to speed

quickly using PIC® microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

23.13 Demonstration, Development and

Evaluation Boards

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

PIC18F45J10 FAMILY

24.0 ELECTRIC AL CHARACTERISTICS

Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +100°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any digital-only input MCLR I/O pin with respect to VSS ........................................................... -0.3V to 6.0V

Voltage on any combined digital and analog pin with respect to VSS ............................................ -0.3V to (VDD + 0.3V)

Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.75V

Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Maximum output current sunk by any PORTB and PORTC I/O pin........................................................................25 mA

Maximum output current sunk by any PORTA, PORTD, and PORTE I/O pin...........................................................4 mA

Maximum output current sourced by any PORTB and PORTC I/O pin ..................................................................25 mA

Maximum output current sourced by any PORTA, PORTD, and PORTE I/O pin .....................................................4 mA

Maximum current sunk by all ports combined.......................................................................................................200 mA

Maximum current sourced by all ports combined..................................................................................................200 mA

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC18F45J10 FAMILY

FIGURE 24-1: PIC18LF45J10 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

FIGURE 24-2: PIC18F45J10 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

Frequency

Voltage (VDDCORE)(1)

3.00V

2.00V

40 MHz

2.75V

2.50V

2.25V

2.7V

4 MHz

2.35V

Note 1: For devices without the voltage regulator, VDD and VDDCORE must be maintained so

that VDDCORE ≤ VDD ≤ 3.6V.

For VDDCORE values, 2V to 2.35V, FMAX = (102.85 MHz/V) * (VDDCORE – 2V) + 4 MHz

PIC18LF24J10/25J10/44J10/45J10

Frequency

Voltage (VDD)

4.0V

40 MHz

3.5V

3.0V

2.5V

3.6V

4 MHz

PIC18F2XJ10/4XJ10

2.7V

PIC18F45J10 FAMILY

D005

24.1 DC Characteristics: Supply Voltage

PIC18F24J10/25J10/ 44J10/45J10 (Industrial)

PIC18LF24J10/25J10/ 44J10/45J10 (Industrial)

PIC18F45J 10 F am ily

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

Param

No. Symbol Characteristic Min Typ Max Units Conditions

D001 VDD Supply Voltage VDDCORE — 3.6 V PIC18LF4XJ10, PIC18LF2XJ10

D001 VDD Supply Voltage 2.7(1) — 3.6 V PIC18F4X/2XJ10

D001B VDDCORE External Supply for

Microcontroller Core 2.0 — 2.7 V Valid only in parts designated “LF”.

See Se cti on 2 1. 3 “ On- Chip

Voltage Regulator ” for details.

D002 VDR RAM Data Retention

Voltage(1) 1.5 — — V

D003 VPOR VDD Star t Volt age

to ensure internal

Power-on Reset signal

— — 0.15 V SeeSection 5.3 “Power-on

Reset (POR)” for details

D004 SVDD VDD Rise Rate

to ensure internal

Power-on Reset signal

0.05 — — V/ms See Section 5.3 “Power-on

Reset (POR)” for details

D005 VBOR Brown-out Reset (BOR)

Voltage 2.35 2.5 2.7 V

Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM

data.

PIC18F45J10 FAMILY

24.2 DC Characteristics: Power-Down and Supply Current

PIC18F24J10/25J10/44J10/45J10 (Industrial)

PIC18LF24J10/2 5J10/44J10/45J10 (Industrial)

PIC18F45J10 Family

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Power-Down Current (IPD)(1)

All devices 19 104 μA -40°C

VDD = 2.5V

(Sleep mode)

25 104 μA +25°C

40 184 μA +85°C

All devices 20 203 μA -40°C

VDD = 3.3V

(Sleep mode)

25 203 μA +25°C

45 289 μA +85°C

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

PIC18F45J10 FAMILY

Supply Current (IDD)(2)

All devices 3.8 7.7 mA -40°C

FOSC = 31 kHz

(RC_RUN mode,

Internal oscillator source)

3.7 7.5 mA +25°C VDD = 2.5V

3.7 7.5 mA +85°C

All devices 3.9 7.9 mA -40°C

3.7 7.5 mA +25°C VDD = 3.3V

3.7 7.5 mA +85°C

All devices 64 167 μA-40°C

FOSC = 31 kHz

(RC_IDLE mode,

Internal oscillator source)

77 193 μA +25°C VDD = 2.5V

95 269 μA +85°C

All devices 65 266 μA-40°C

79 294 μA +25°C VDD = 3.3V

98 360 μA +85°C

24.2 DC Characteristics: Power-Down and Supply Current

PIC18F24J10/25J10/44J10/45J10 (Industrial)

PIC18LF24J10/2 5J10/44J10/45J10 (Industrial) (Continued)

PIC18F45J10 Family

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

PIC18F45J10 FAMILY

Supply Current (IDD)(2)

All devices 4.2 8.5 mA -40°C

FOSC = 1 MHz

(PRI_RUN mode,

EC oscillator)

3.9 8.0 mA +25°C VDD = 2.5V

3.6 7.3 mA +85°C

All devices 4.3 8.6 mA -40°C

4.0 8.1 mA +25°C VDD = 3.3V

3.7 7.6 mA +85°C

All devices 4.6 9.3 mA -40°C

FOSC = 4 MHz

(PRI_RUN mode,

EC oscillator)

4.3 8.7 mA +25°C VDD = 2.5V

4.0 8.1 mA +85°C

All devices 4.7 9.4 mA -40°C

4.4 8.8 mA +25°C VDD = 3.3V

4.1 8.2 mA +85°C

All devices 11.0 22.0 mA -40°C

FOSC = 40 MHz

(PRI_RUN mode,

EC oscillator)

10.5 21.0 mA +25°C VDD = 2.5V

10.0 20.0 mA +85°C

All devices 12.0 24.0 mA -40°C

11.5 23.0 mA +25°C VDD = 3.3V

11.0 22.0 mA +85°C

24.2 DC Characteristics: Power-Down and Supply Current

PIC18F24J10/25J10/44J10/45J10 (Industrial)

PIC18LF24J10/2 5J10/44J10/45J10 (Industrial) (Continued)

PIC18F45J10 Family

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

PIC18F45J10 FAMILY

Supply Current (IDD)(2)

All devices 6.2 14 mA -40°C

VDD = 2.5V

FOSC = 4 MHZ,

16 MHZ internal

(PRI_RUN HS+PLL)

5.7 13 mA +25°C

5.7 13 mA +85°C

All devices 6.6 15 mA -40°C

VDD = 3.3V

FOSC = 4 MHZ,

16 MHZ internal

(PRI_RUN HS+PLL)

6.1 14 mA +25°C

6.1 14 mA +85°C

All devices 11.0 22 mA -40°C

VDD = 2.5V

FOSC = 10 MHZ,

40 MHZ internal

(PRI_RUN HS+PLL)

10.5 21 mA +25°C

10.0 20 mA +85°C

All devices 12.0 24 mA -40°C

VDD = 3.3V

FOSC = 10 MHZ,

40 MHZ internal

(PRI_RUN HS+PLL)

11.5 23 mA +25°C

11.0 22 mA +85°C

24.2 DC Characteristics: Power-Down and Supply Current

PIC18F24J10/25J10/44J10/45J10 (Industrial)

PIC18LF24J10/2 5J10/44J10/45J10 (Industrial) (Continued)

PIC18F45J10 Family

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

PIC18F45J10 FAMILY

Supply Current (IDD)(2)

All devices 150 337 μA-40°C

FOSC = 1 MHz

(PRI_IDLE mode,

EC oscillator)

160 355 μA +25°C VDD = 2.5V

220 512 μA +85°C

All devices 190 518 μA-40°C

200 528 μA +25°C VDD = 3.3V

250 647 μA +85°C

All devices 350 737 μA-40°C

FOSC = 4 MHz

(PRI_IDLE mode,

EC oscillator)

375 787 μA +25°C VDD = 2.5V

420 917 μA +85°C

All devices 410 954 μA-40°C

0.450 1.03 mA +25°C VDD = 3.3V

0.475 1.13 mA +85°C

All devices 5.0 10.1 mA -40°C

FOSC = 40 MHz

(PRI_IDLE mode,

EC oscillator)

5.2 10.6 mA +25°C VDD = 2.5V

5.5 11.1 mA +85°C

All devices 5.5 11.1 mA -40°C

6.0 12.1 mA +25°C VDD = 3.3V

6.5 13.1 mA +85°C

24.2 DC Characteristics: Power-Down and Supply Current

PIC18F24J10/25J10/44J10/45J10 (Industrial)

PIC18LF24J10/2 5J10/44J10/45J10 (Industrial) (Continued)

PIC18F45J10 Family

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

PIC18F45J10 FAMILY

Supply Current (IDD)(2)

All devices 4.1 8.3 mA -40°C

FOSC = 32 kHz

(SEC_RUN mode,

Timer1 as clock)

3.8 7.7 mA +25°C VDD = 2.5V

3.8 7.7 mA +85°C

All devices 4.1 8.3 mA -40°C

3.8 7.7 mA +25°C VDD = 3.3V

3.8 7.7 mA +85°C

All devices 66 169 μA-40°C

FOSC = 32 kHz

(SEC_IDLE mode,

Timer1 as clock)

79 195 μA +25°C VDD = 2.5V

97 271 μA +85°C

All devices 67 268 μA-40°C

81 296 μA +25°C VDD = 3.3V

100 362 μA +85°C

24.2 DC Characteristics: Power-Down and Supply Current

PIC18F24J10/25J10/44J10/45J10 (Industrial)

PIC18LF24J10/2 5J10/44J10/45J10 (Industrial) (Continued)

PIC18F45J10 Family

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

PIC18F45J10 FAMILY

D022

(ΔIWDT)

Module Differential Currents (ΔIWDT, ΔIOSCB, ΔIAD)

Watchdog Timer 3.2 6.5 μA-40°C

VDD = 2.5V

3.2 6.5 μA +25°C

5.1 10.3 μA +85°C

3.5 7.1 μA-40°C

VDD = 3.3V

3.5 7.1 μA +25°C

5.5 11.2 μA +85°C

D025

(ΔIOSCB)

Timer1 Oscillator 8.4 17 μA-40°C

VDD = 2.5V 32 kHz on Timer1(3)

11.5 24 μA +25°C

13.2 30 μA +85°C

9.6 20 μA-40°C

VDD = 3.3V 32 kHz on Timer1(3)

12.4 25 μA +25°C

14.1 29 μA +85°C

D026

(ΔIAD)

A/D Converter 1.0 5 μA -40°C to +85°C VDD = 2.5V A/D on, not converting

1.2 5 μA -40°C to +85°C VDD = 3.3V

24.2 DC Characteristics: Power-Down and Supply Current

PIC18F24J10/25J10/44J10/45J10 (Industrial)

PIC18LF24J10/2 5J10/44J10/45J10 (Industrial) (Continued)

PIC18F45J10 Family

(Industrial) Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

PIC18F45J10 FAMILY

24.3 DC Characteristics: PIC18F45J10 Family (Industrial)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

Param

No. Symbol Characteristic Min Max Units Conditions

VIL Input Low Volta ge

All I/O Ports:

D030 with TTL Buffer VSS 0.15 VDD VVDD < 3.3V

D030A — 0.8 V 3.3V ≤ VDD ≤ 3.6V

D031 with Schmitt Trigger Buffer VSS 0.2 VDD V

D032 MCLR VSS 0.2 VDD V

D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes

D033A

D034

OSC1

T1CKI

VSS

0.2 VDD

0.3

EC, ECPLL modes(1)

VIH Input High Volt age

I/O Ports with non 5.5V

Toler ance:(4)

D040 with TTL Buffer 0.25 VDD + 0.8V VDD VVDD < 3.3V

D040A 2.0 VDD V3.3V ≤ VDD ≤ 3.6V

D041 with Schmitt Trigger Buffer 0.8 VDD VDD V

I/O Ports with 5.5V

Toler ance:(4)

Dxxx with TTL Buffer 0.25 VDD + 0.8V 5.5 V VDD < 3.3V

DxxxA 2.0 5.5 V 3.3V ≤ VDD ≤ 3.6V

Dxxx with Schmitt Trigger Buffer 0.8 VDD 5.5 V

D042 MCLR 0.8 VDD VDD V

D043 OSC1 0.7 VDD VDD V HS, HSPLL modes

D043A

D044

OSC1

T1CKI

0.8 VDD

1.6

VDD

EC, ECPLL modes

IIL Input Leakage Current (2,3)

D060 I/O Ports with non 5.5V

Toler ance(4) —±0.2 μAVSS ≤ VPIN ≤ VDD,

Pin at high-impedance

D060A I/O Ports with 5.5V

Toler ance(4) —±0.2 μAVSS ≤ VPIN ≤ 5.5V,

Pin at high-impedance

D061 MCLR —±0.2 μAVss ≤ VPIN ≤ VDD

D063 OSC1 — ±0.2 μAVss ≤ VPIN ≤ VDD

IPU Weak Pull-up Current

D070 IPURB PORTB Weak Pull-up Current 30 240 μAVDD = 3.3V, VPIN = VSS

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PIC® device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Refer to Table 10-2 for the pins that have corresponding tolerance limits.

PIC18F45J10 FAMILY

VOL Output Low Voltage

D080 I/O Ports (PORTB, PORTC) — 0.4 V IOL = 8.5 mA, VDD 3.3V

-40°C to +85°C

I/O Ports (PORTA, PORTD,

PORTE)

—0.4VI

OL = 3.4 mA, VDD 3.3V

-40°C to +85°C

D083 OSC2/CLKO

(EC mode)

—0.4VI

OL = 1.6 mA, VDD 3.3V

-40°C to +85°C

VOH Output High Voltage(3)

D090 I/O Ports (PORTB, PORTC) 2.4 — V IOH = -6 mA, VDD 3.3V

-40°C to +85°C

I/O Ports (PORTA, PORTD,

PORTE)

2.4 — V IOH = -2 mA, VDD 3.3V

-40°C to +85°C

D092 OSC2/CLKO

(EC mode)

2.4 — V IOH = 1.0 mA, VDD 3.3V

-40°C to +85°C

Capacitive Loading Specs

on Output Pins

D100(4) COSC2 OSC2 Pin — 15 pF In HS mode when

external clock is used to drive

OSC1

D101 CIO All I/O Pins — 50 pF To meet the AC Timing

Specifications

D102 CBSCLx, SDAx — 400 pF I2C™ Specification

24.3 DC Characteristics: PIC18F45J10 Family (Industr ial ) (Continued)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ T

A ≤ +85°C for industrial

Param

No. Symbol Characteristic Min Max Units Conditions

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PIC® device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Refer to Table 10-2 for the pins that have corresponding tolerance limits.

PIC18F45J10 FAMILY

TABLE 24-1: MEMORY PROGRAMMING REQUIREMENTS

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Program Flash Memory

D130 EPCell Endurance 100 1K — E/W -40°C to +85°C

D131 VPR VDD for Read VMIN —3.6VVMIN = Minimum operating

voltage

D132B VPEW Voltage for Self-Timed Erase or

Write:

VDD 2.7 — 3.6 V PIC18FXXJ10

VDDCORE 2.25 — 2.7 V PIC18LFXXJ10

D133A TIW Self-Timed Write Cycle Time — 2.8 — ms

D133B TIE Self-Timed Page Erased Cycle

Time

—33.0—ms

D134 TRETD Characteristic Retention 20 — — Year Provided no other

specifications are violated

D135 IDDP Supply Current during

Programming

—10—mA

† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

PIC18F45J10 FAMILY

TABLE 24-2: COMPARATOR SPECIFICATIONS

TABLE 24-3: VOLT AGE REFERENCE SPECIFICATIONS

TABLE 24-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

D300 VIOFF Input Offset Voltage — ±5.0 ±25 mV

D301 VICM Input Common Mode Voltage*0—VDD – 1.5 V

D302 CMRR Common Mode Rejection Ratio*55 — — dB

D303 TRESP Response Time(1)* —150400 ns

D304 TMC2OV Comparator Mode Change to

Output Valid*—— 10μs

D305 VIRV Internal Reference Voltage — 1.2 — V

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions

from VSS to VDD.

Operating Condit ions : 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

D310 VRES Resolution VDD/24 — VDD/32 LSb

D311 VRAA Absolute Accuracy — — 1/2 LSb

D312 VRUR Unit Resistor Value (R) — 2k — Ω

310 TSET Settling Time(1) — — 10 μs

Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’.

Operating Condit ions : -40°C < T

A < +85°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

VRGOUT Regulator Output Voltage — 2.5 — V

CEFC External Filter Capacitor

Value

4.7 10 — μFSeries resistance < 3 Ohm

recommended;

< 5 Ohm required.

* These parameters are characterized but not tested. Parameter numbers not yet assigned for these

specifications.

PIC18F45J10 FAMILY

24.4 AC (Timing) Characteristics

24.4.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

following one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)

F Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKO rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppercase letters and their meanings:

F Fall P Period

HHigh RRise

I Invalid (High-impedance) V Valid

L Low Z High-impedance

I2C only

AA output access High High

BUF Bus free Low Low

CC:ST (I2C specifications only)

HD Hold SU Setup

DAT DATA input hold STO Stop condition

STA Start condition

PIC18F45J10 FAMILY

24.4.2 TIMING CONDITIONS

The temperature and voltages specified in Table 24-5

apply to all timing specifications unless otherwise

noted. Figure 24-3 specifies the load conditions for the

timing specifications.

TABLE 24-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGURE 24-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

AC CHARACTERISTICS

S tandard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Operating voltage VDD range as described in DC spec Section 24.1 and

Section 24.3.

VDD/2

VSS

RL=464Ω

CL= 50 pF for all pins except OSC2/CLKO

and including D and E outputs as ports

CL = 15 pF for OSC2/CLK0

Load Condition 1 Load Condition 2

PIC18F45J10 FAMILY

24.4.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 24-4: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

TABLE 24-6: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

1A FOSC External CLKI Frequency(1) DC 40 MHz EC Oscillator mode

Oscillator Frequency(1) 4 25 MHz HS Oscillator mode

1TOSC External CLKI Period(1) 25 — ns EC Oscillator mode

Oscillator Period(1) 25 250 ns HS Oscillator mode

CY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, Industrial

3TOSL,

OSH

External Clock in (OSC1)

High or Low Time

10 — ns EC Oscillator mode

OSR,

OSF

External Clock in (OSC1)

Rise or Fall Time

— 7.5 ns EC Oscillator mode

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations.

All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption. All devices are tested to

operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input

is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

OSC1

CLKO

Q4 Q1 Q2 Q3 Q4 Q1

3344

PIC18F45J10 FAMILY

TABLE 24-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5V TO 3.6V)

TABLE 24-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY

PIC18F24J10/25J10/44J10/45J10 (INDUSTRIAL)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

F10 FOSC Oscillator Frequency Range 4 — 10 MHz

F11 FSYS On-Chip VCO System Frequency 20 — 40 MHz

F12 ΤRC PLL Start-up Time (lock time) — — 2 ms

F13 ΔCLK CLKO Stability (Jitter) -2 — +2 %

† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance

only and are not tested.

Param

No. Characteristic Min Typ Max Units Conditions

INTRC Accuracy @ Freq = 31 kHz(1) 21.7 — 40.3 kHz

Note 1: Change of INTRC frequency as VDD core changes.

PIC18F45J10 FAMILY

FIGURE 24-5: CLKO AND I/O TIMING

TABLE 24-9: CLKO AND I/O TIMING REQUIREMENTS

Param

No. Symbol Characteristic Min Typ Max Units Conditions

10 TOSH2CKLOSC1 ↑ to CLKO ↓ — 75 200ns

11 TOSH2CKHOSC1 ↑ to CLKO ↑ — 75 200ns

12 TCKR CLKO Rise Time — 15 30 ns

13 TCKF CLKO Fall Time — 15 30 ns

14 TCKL2IOVCLKO ↓ to Port Out Valid — — 0.5 TCY + 20 ns

15 TIOV2CKH Port In Valid before CLKO ↑ 0.25 TCY + 25 — — ns

16 TCKH2IOI Port In Hold after CLKO ↑ 0——ns

17 TOSH2IOVOSC1 ↑ (Q1 cycle) to Port Out Valid — 50 150 ns

18 TOSH2IOIOSC1 ↑ (Q2 cycle) to Port Input Invalid

(I/O in hold time)

100 — — ns

18A 200 — — ns

19 TIOV2OSH Port Input Valid to OSC1 ↑

(I/O in setup time)

0——ns

20 TIOR Port Output Rise Time — — 6 ns

21 TIOF Port Output Fall Time — — 5 ns

22† TINP INTx pin High or Low Time TCY ——ns

23† TRBP RB<7:4> Change INTx High or Low Time TCY ——ns

† These parameters are asynchronous events not related to any internal clock edges.

Note: Refer to Figure 24-3 for load conditions.

OSC1

CLKO

I/O pin

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

20, 21

19 18

Old Value New Value

PIC18F45J10 FAMILY

FIGURE 24-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

FIGURE 24-7: BROWN-OUT RESET TIMING

TABLE 24-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param.

No. Symbol Characteristic Min Typ Max Units Conditions

30 TMCLMCLR Pulse Width (low) 2 — — μs

31 TWDT Watchdog Timer Time-out Period

(no postscaler)

2.8 4.1 5.4 ms

32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period

33 TPWRT Power-up Timer Period 46.2 66 85.8 ms

34 TIOZ I/O High-Impedance from MCLR

Low or Watchdog Timer Reset

—2—μs

38 TCSD CPU Start-up Time — 200 — μs

VDD

MCLR

Internal

POR

PWRT

Time-out

Oscillator

Time-out

Internal

Reset

Watchdog

Timer

Reset

I/O pins

Note: Refer to Figure 24-3 for load conditions.

VDD

BVDD

VBGAP = 1.2V

VIRVST

Enable Internal

Internal Reference

Reference Voltage

Voltage Stable

PIC18F45J10 FAMILY

FIGURE 24-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 24-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Symbol Characteristic Min Max Units Conditions

40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

42 TT0P T0CKI Period No prescaler TCY + 10 — ns

With prescaler Greater of:

20 ns or

(TCY + 40)/N

—nsN = prescale

value

(1, 2, 4,..., 256)

45 TT1H T1CKI High

Time

Synchronous, no prescaler 0.5 TCY + 20 — ns

Synchronous, with prescaler 10 — ns

Asynchronous 30 — ns

46 TT1L T1CKI Low

Time

Synchronous, no prescaler 0.5 TCY + 5 — ns

Synchronous, with prescaler 10 — ns

Asynchronous 30 — ns

47 TT1P T1CKI Input

Period

Synchronous Greater of:

20 ns or

(TCY + 40)/N

—nsN = prescale

value

(1, 2, 4, 8)

Asynchronous 60 — ns

FT1 T1CKI Oscillator Input Frequency Range DC 50 kHz

48 T

CKE2TMRI Delay from External T1CKI Clock Edge to

Timer Increment

2 TOSC 7 TOSC —

Note: Refer to Figure 24-3 for load conditions.

T0CKI

T1OSO/T1CKI

TMR0 or

TMR1

PIC18F45J10 FAMILY

FIGURE 24-9: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULE)

TABLE 24-12: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULE)

TABLE 24-13: PARALLEL SLAVE PORT REQUIREMENTS

Param

No. Symbol Characteristic Min Max Units Conditions

50 TCCL CCPx Input Low

Time

No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

51 TCCH CCPx Input

High Time

No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

52 TCCP CCPx Input Period 3 TCY + 40

— ns N = prescale

value (1, 4 or 16)

53 TCCR CCPx Output Fall Time — 25 ns

54 TCCF CCPx Output Fall Time — 25 ns

Param.

No. Symbol Characteristic Min Max Units Conditions

62 TdtV2wrH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns

63 TwrH2dtI WR ↑ or CS ↑ to Data–In Invalid (hold time) 20 — ns

64 TrdL2dtV RD ↓ and CS ↓ to Data–Out Valid — 80 ns

65 TrdH2dtI RD ↑ or CS ↓ to Data–Out Invalid 10 30 ns

66 TibfINH Inhibit of the IBF Flag bit being Cleared from

WR ↑ or CS ↑

—3 T

Note: Refer to Figure 24-3 for load conditions.

CCPx

(Capture Mode)

50 51

CCPx

53 54

(Compare or PWM Mode)

PIC18F45J10 FAMILY

FIGURE 24-10 : EX AMP LE SP I™ MASTER MODE TIMING (CKE = 0)

TABLE 24-14: EXAMPLE SPI™ MODE REQUIREMENTS (CKE = 0)

Param

No. Symbol Characteristic Min Max Units Conditions

70 T

SSL2SCH,

SSL2SCL

SSx ↓ to SCKx ↓ or SCKx ↑ Input TCY —ns

73 TDIV2SCH,

TDIV2SCL

Setup Time of SDIx Data Input to SCKx Edge 20 — ns

73A TB2BLast Clock Edge of Byte 1 to the 1st Clock Edge

of Byte 2

1.5 TCY + 40 — ns (Note 1)

74 T

SCH2DIL,

SCL2DIL

Hold Time of SDIx Data Input to SCKx Edge 40 — ns

75 TDOR SDOx Data Output Rise Time — 25 ns

76 TDOF SDOx Data Output Fall Time — 25 ns

78 T

SCR SCKx Output Rise Time (Master mode) — 25 ns

79 T

SCF SCKx Output Fall Time (Master mode) — 25 ns

80 T

SCH2DOV,

SCL2DOV

SDOx Data Output Valid after SCKx Edge — 50 ns

Note 1: Only if Parameter #71A and #72A are used.

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

71 72

75, 76

MSb LSb

bit 6 - - - - - - 1

MSb In LSb In

bit 6 - - - - 1

Note: Refer to Figure 24-3 for load conditions.

PIC18F45J10 FAMILY

FIGURE 24-11: EXAMPLE SPI™ MASTER MODE TIMING (CKE = 1)

TABLE 24-15: EXAMPLE SPI™ MODE REQUIREMENTS (CKE = 1)

Param.

No. Symbol Characteristic Min Max Units Conditions

73 TDIV2SCH,

TDIV2SCL

Setup Time of SDIx Data Input to SCKx Edge 20 — ns

73A TB2BLast Clock Edge of Byte 1 to the 1st Clock Edge

of Byte 2

1.5 TCY + 40 — ns (Note 1)

74 T

SCH2DIL,

SCL2DIL

Hold Time of SDIx Data Input to SCKx Edge 40 — ns

75 TDOR SDOx Data Output Rise Time — 25 ns

76 TDOF SDOx Data Output Fall Time — 25 ns

78 TSCR SCKx Output Rise Time (Master mode) — 25 ns

79 T

SCF SCKx Output Fall Time (Master mode) — 25 ns

80 TSCH2DOV,

SCL2DOV

SDOx Data Output Valid after SCKx Edge — 50 ns

81 TDOV2SCH,

TDOV2SCL

SDOx Data Output Setup to SCKx Edge T

CY —ns

Note 1: Only if Parameter #71A and #72A are used.

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDIx

71 72

75, 76

MSb

MSb In

bit 6 - - - - - - 1

LSb In

bit 6 - - - - 1

LSb

Note: Refer to Figure 24-3 for load conditions.

PIC18F45J10 FAMILY

FIGURE 24-12 : EX AMP LE SP I™ SLAVE MODE TIMING (CKE = 0)

TABLE 24-16: EXAMPLE SPI™ MODE REQUIREMENTS (CKE = 0)

Param

No. Symbol Characteristic Min Max Units Conditions

70 T

SSL2SCH,

SSL2SCL

SSx ↓ to SCKx ↓ or SCKx ↑ Input TCY —ns

71 T

SCH SCKx Input High Time

(Slave mode)

Continuous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 T

SCL SCKx Input Low Time

(Slave mode)

Continuous 1.25 TCY + 30 — ns

72A Single Byte 40 — ns (Note 1)

73 TDIV2SCH,

TDIV2SCL

Setup Time of SDIx Data Input to SCKx Edge 20 — ns

73A TB2BLast Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TSCH2DIL,

SCL2DIL

Hold Time of SDIx Data Input to SCKx Edge 40 — ns

75 TDOR SDOx Data Output Rise Time — 25 ns

76 TDOF SDOx Data Output Fall Time — 25 ns

77 T

SSH2DOZSSx ↑ to SDOx Output High-Impedance 10 50 ns

80 T

SCH2DOV,

SCL2DOV

SDOx Data Output Valid after SCKx Edge — 50 ns

83 T

SCH2SSH,

SCL2SSH

SSx ↑ after SCKx Edge 1.5 TCY + 40 — ns

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDI

71 72

75, 76 77

SDIx

MSb LSb

bit 6 - - - - - - 1

MSb In bit 6 - - - - 1 LSb In

Note: Refer to Figure 24-3 for load conditions.

PIC18F45J10 FAMILY

FIGURE 24-13 : EX AMP LE SP I™ SLAVE MODE TIMING (CKE = 1)

TABLE 24-17: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)

Param

No. Symbol Characteristic Min Max Units Conditions

70 T

SSL2SCH,

SSL2SCL

SSx ↓ to SCKx ↓ or SCKx ↑ Input TCY —ns

71 T

SCH SCKx Input High Time

(Slave mode)

Continuous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 T

SCL SCKx Input Low Time

(Slave mode)

Continuous 1.25 TCY + 30 — ns

72A Single Byte 40 — ns (Note 1)

73A TB2BLast Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 T

SCH2DIL,

SCL2DIL

Hold Time of SDIx Data Input to SCKx Edge 20 — ns

75 TDOR SDOx Data Output Rise Time — 25 ns

76 TDOF SDOx Data Output Fall Time — 25 ns

77 T

SSH2DOZSSx ↑ to SDOx Output High-Impedance 10 50 ns

80 TSCH2DOV,

SCL2DOV

SDOx Data Output Valid after SCKx Edge — 50 ns

82 T

SSL2DOV SDOx Data Output Valid after SSx ↓ Edge — 50 ns

83 T

SCH2SSH,

SCL2SSH

SSx ↑ after SCKx Edge 1.5 TCY + 40 — ns

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDI

71 72

SDIx

75, 76

MSb bit 6 - - - - - - 1 LSb

MSb In bit 6 - - - - 1 LSb In

Note: Refer to Figure 24-3 for load conditions.

PIC18F45J10 FAMILY

FIGURE 24-14 : I2C™ BUS START/STOP BITS TIMING

TABLE 24-18: I2C™ BUS START/S TOP BITS REQUIREMENTS (SLAVE MODE)

FIGURE 24-15 : I2C™ BUS DATA TIMING

Param.

No. Symbol Characteristic Min Max Units Conditions

90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated

Start condition

Setup Time 400 kHz mode 600 —

91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first

clock pulse is generated

Hold Time 400 kHz mode 600 —

92 TSU:STO Stop Condition 100 kHz mode 4700 — ns

Setup Time 400 kHz mode 600 —

93 THD:STO Stop Condition 100 kHz mode 4000 — ns

Hold Time 400 kHz mode 600 —

Note: Refer to Figure 24-3 for load conditions.

SCLx

SDAx

Start

Condition

Stop

Condition

Note: Refer to Figure 24-3 for load conditions.

91 92

100

101

103

106 107

109 109

110

102

SCLx

SDAx

Out

PIC18F45J10 FAMILY

TABLE 24-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Clock High Time 100 kHz mode 4.0 — μs

400 kHz mode 0.6 — μs

MSSP Module 1.5 TCY —

101 TLOW Clock Low Time 100 kHz mode 4.7 — μs

400 kHz mode 1.3 — μs

MSSP Module 1.5 TCY —

102 TRSDAx and SCLx Rise Time 100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 to 400 pF

103 TFSDAx and SCLx Fall Time 100 kHz mode — 300 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 to 400 pF

90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — μs Only relevant for Repeated

Start condition

400 kHz mode 0.6 — μs

91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — μs After this period, the first clock

pulse is generated

400 kHz mode 0.6 — μs

106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 μs

107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — μs

400 kHz mode 0.6 — μs

109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

110 TBUF Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free

before a new transmission can

start

400 kHz mode 1.3 — μs

D102 CBBus Capacitive Loading — 400 pF

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)

of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.

2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT ≥250 ns,

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal.

If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,

TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx

line is released.

PIC18F45J10 FAMILY

FIGURE 24-16: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS

TABLE 24-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS

FIGURE 24-17: MASTER SS P I2C™ BUS DATA TIMING

Param.

No. Symbol Characteristic Min Max Units Conditions

90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for

Repeated Start

condition

Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the

first clock pulse is

generated

Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns

Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ns

Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.

Note: Refer to Figure 24-3 for load conditions.

91 93

SCLx

SDAx

Start

Condition

Stop

Condition

90 92

Note: Refer to Figure 24-3 for load conditions.

90 91 92

100

101

103

106 107

109 109 110

102

SCLx

SDAx

Out

PIC18F45J10 FAMILY

TABLE 24-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

102 TRSDAx and SCLx

Rise Time

100 kHz mode — 1000 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1) — 300 ns

103 TFSDAx and SCLx

Fall Time

100 kHz mode — 300 ns CB is specified to be from

10 to 400 pF

400 kHz mode 20 + 0.1 CB 300 ns

1 MHz mode(1) — 100 ns

90 T

SU:STA Start Condition

Setup Time

100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for

Repeated Start

condition

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

91 THD:STA Start Condition

Hold Time

100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first

clock pulse is generated

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

106 THD:DAT Data Input

Hold Time

100 kHz mode 0 — ns

400 kHz mode 0 0.9 ms

1 MHz mode(1) ——ns

107 TSU:DAT Data Input

Setup Time

100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

1 MHz mode(1) ——ns

92 TSU:STO Stop Condition

Setup Time

100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) — ms

109 TAA Output Valid

from Clock

100 kHz mode — 3500 ns

400 kHz mode — 1000 ns

1 MHz mode(1) ——ns

110 TBUF Bus Free Time 100 kHz mode 4.7 — ms Time the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — ms

1 MHz mode(1) ——ms

D102 CBBus Capacitive Loading — 400 pF

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.

2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data

bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before

the SCLx line is released.

PIC18F45J10 FAMILY

FIGURE 24-18: EUSART SYN CHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TABLE 24-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 24-19: EUS ART SYNCHRONOUS RECEIV E (MASTER/SLAVE) TIMING

TABLE 24-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Param

No. Symbol Characteristic Min Max Units Conditions

120 T

CKH2DTV SYNC XMIT (MASTER and SLAVE)

Clock High to Data Out Valid — 40 ns

121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns

122 TDTRF Data Out Rise Time and Fall Time — 20 ns

Param.

No. Symbol Characteristic Min Max Units Conditions

125 TDTV2CKL SYNC RCV (MASTER and SLAVE)

Data Hold before CK ↓ (DT hold time) 10 — ns

126 TCKL2DTL Data Hold after CK ↓ (DT hold time) 15 — ns

121 121

120 122

TX/CK

RX/DT

Note: Refer to Figure 24-3 for load conditions.

125

126

TX/CK

RX/DT

Note: Refer to Figure 24-3 for load conditions.

PIC18F45J10 FAMILY

TABLE 24-24: A/D CONVERT ER CH AR ACT ERI STIC S:PIC1 8F 24 J10 /2 5J1 0/44 J10/ 45J 10 ( IND UST RIA L)

FIGURE 24-20: A/D CONVERSION TIMING

Param

No. Symbol Characteristic Min Typ Max Units Conditions

A01 NRResolution — — 10 bit ΔVREF ≥ 3.0V

A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V

A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V

A06 EOFF Offset Error — — <±3 LSb ΔVREF ≥ 3.0V

A07 EGN Gain Error — — <±3 LSb ΔVREF ≥ 3.0V

A10 — Monotonicity Guaranteed(1) —VSS ≤ VAIN ≤ VREF

A20 ΔVREF Reference Voltage Range

(VREFH – VREFL)

1.8

—

VDD < 3.0V

VDD ≥ 3.0V

A21 VREFH Reference Voltage High VSS —VREFH V

A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V

A25 VAIN Analog Input Voltage VREFL —VREFH V

A30 ZAIN Recommended Impedance of

Analog Voltage Source

——2.2kΩ

A50 IREF VREF Input Current(2) —

—

150

μA

During VAIN acquisition.

During A/D conversion

cycle.

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.

VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.

3: Maximum allowed impedance is 8.8 kΩ. This requires higher acquisition time than described in the A/D

chapter.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

987 21 0

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEP instruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . . . . .

TCY

PIC18F45J10 FAMILY

TABLE 24-25: A/D CONVERSION REQUIREMENTS

Param

No. Symbol Characteristic Min Max Units Conditions

130 TAD A/D Clock Period 0.7 25.0(1) μsTOSC based, VREF ≥ 2.0V

131 TCNV Conversion Time

(not including acquisition time) (Note 2) 11 12 TAD

132 TACQ Acquisition Time (Note 3) 1.4 — μs-40°C to +85°C

135 TSWC Switching Time from Convert → Sample — (Note 4)

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

2: ADRES registers may be read on the following TCY cycle.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.

4: On the following cycle of the device clock.

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

25.0 PACKAGING INFORMATION

25.1 Package Marking Information

28-Lead SPDIP

XXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F24J10

0910017

28-Lead SOIC

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F24J10-I/SO

0910017

28-Lead SSOP

XXXXXXXXXXXX

YYWWNNN

Example

PIC18F24J10

-I/SS

0910017

28-Lead QFN

XXXXXXXX

YYWWNNN

Example

18F24J10

-I/ML

0910017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

-I/SP

PIC18F45J10 FAMILY

Package Marking Information (Continued)

40-Lead PDIP

XXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC18F44J10-I/P

0910017

XXXXXXXXXX

44-Lead QFN

XXXXXXXXXX

YYWWNNN

18F44J10

Example

-I/ML

0910017

44-Lead TQFP

XXXXXXXXXX

YYWWNNN

Example

18F45J10

I/PT

0910017

PIC18F45J10 FAMILY

25.2 Package Details

The following sections give the technical details of the packages.



!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#/!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

!" 3&'!&"&4#*!(!!&4%&&#&

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& .  - --

##4>#& .  < 

: 9&  - -? 

&& 9  - 

9#4!!  <  

69#>#& )   

9*9#>#& )  < 

: *+ 1 = = -

NOTE 1

  * ,1

PIC18F45J10 FAMILY

##$%&'(#)

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  = = ?

##44!!   = =

&#%%+   = -

: >#& . -1,

##4>#& . 1,

: 9&  1,

,'%@&A   = 

3&9& 9  = 

3&& 9 .3

3& IB = <B

9#4!!  < = --

9#>#& ) - = 

#%& DB = B

#%&1&&' EB = B

NOTE 1

123

  * ,1

PIC18F45J10 FAMILY

*+#('#

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  ?1,

: 8&  = = 

##44!!  ?  <

&#%%   = =

: >#& .  < <

##4>#& .  - ?

: 9&    

3&9& 9   

3&& 9 .3

9#4!!   = 

3& B B <B

9#>#& )  = -<

NOTE 1

  * ,-1

PIC18F45J10 FAMILY

,-%!./010,-!

2*'(().*

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 4!!*!"&#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  ?1,

: 8&  <  

&#%%    

,&&4!! - .3

: >#& . ?1,

.$!##>#& . -? - 

: 9&  ?1,

.$!##9&  -? - 

,&&>#& ) - - -

,&&9& 9   

,&&&.$!## C  = =

DEXPOSED D2

NOTE 1

TOP VIEW BOTTOM VIEW

PAD

  * ,1

PIC18F45J10 FAMILY

,-%!./010,-!

2*'(().*

&&255***''54

PIC18F45J10 FAMILY

30

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

 '!#&.0

1,2 1!'!&$& "!**&"&&!

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 

&  1,

&&  = = 

##44!!   = 

1!&&   = =

"#&"#>#& .  = ?

##4>#& . < = <

: 9&  < = 

&& 9  = 

9#4!!  < = 

69#>#& ) - = 

9*9#>#& )  = -

: *+ 1 = = 

NOTE 1

123

A1 b1

  * ,?1

PIC18F45J10 FAMILY

33,-%!./1,-!

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 4!!*!"&#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 

&  ?1,

: 8&  <  

&#%%    

,&&4!! - .3

: >#& . <1,

.$!##>#& . ?- ? ?<

: 9&  <1,

.$!##9&  ?- ? ?<

,&&>#& )  - -<

,&&9& 9 -  

,&&&.$!## C  = =

DEXPOSED

PAD

NOTE 1

BOTTOM VIEW

TOP VIEW

A3 A1

  * ,-1

PIC18F45J10 FAMILY

33,-%!./1,-!

&&255***''54

PIC18F45J10 FAMILY

334*,-5461616%'4,-

!"

  !"#$%&"' ()"&'"!&)&#*&&&#

 ,'%!&!&D!E' 

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%9#! 7 

9#&  <1,

: 8&  = = 

##44!!    

&#%%   = 

3&9& 9  ? 

3&& 9 .3

3& B -B B

: >#& . 1,

: 9&  1,

##4>#& . 1,

##49&  1,

9#4!!   = 

9#>#& ) - - 

#%& B B -B

#%&1&&' B B -B

NOTE 1 NOTE 2

123

  * ,?1

PIC18F45J10 FAMILY

334*,-5461616%'4,-

&&255***''54

PIC18F45J10 FAMILY

APPENDIX A: REVISI ON HISTORY

Revision A (March 2005)

Original data sheet for PIC18F45J10 family devices.

Revision B (November 2006)

Packaging diagrams have been updated.

Revision C (January 2007)

Packaging diagrams have been updated.

Revision D (November 2008)

Electrical characteristics and packaging diagrams have

been updated. Minor edits to text throughout document.

Revision E (May 2009)

Pin diagrams have been edited to indicate 5.5V tolerant

input pins. Packaging diagrams have been updated.

Section 2.0 “Guidelines for Getting Started with

PIC18FJ Microcontrollers” has been added. Minor text

edits throughout the document.

PIC18F45J10 FAMILY

APPENDIX B: MIGRATION

BETWEEN HIGH-END

DEVICE FAMILIES

Devices in the PIC18F45J10 family and PIC18F4520

families are very similar in their functions and feature

sets. However, there are some potentially important

differences which should be considered when

migrating an application across device families to

achieve a new design goal. These are summarized in

Table B-1. The areas of difference which could be a

major impact on migration are discussed in greater

detail later in this section.

TABLE B-1: NOTABLE DIFFERENCES BETWEEN PIC18F45J10 AND PIC18F4520 FAMILIES

Characteristic PIC18F45J10 Family PIC18F4520 Family

Operating Frequency 40 MHz @ 2.15V 40 MHz @ 4.2V

Supply Voltage 2.0V-3.6V 2.0V-5.5V

Operating Current Low Lower

Program Memory Endurance 1,000 write/erase cycles (typical) 100,000 write/erase cycles (typical)

I/O Sink/Source at 25 mA PORTB and PORTC only All ports

Input Voltage Tolerance on I/O pins 5.5V on digital only pins VDD on all I/O pins

I/O 32 36

Pull-ups PORTB PORTB

Oscillator Options Limited options

(EC, HS, fixed 32 kHz INTRC)

More options (EC, HS, XT, LP, RC,

PLL, flexible INTRC)

Program Memory Retention 10 years (minimum) 40 years (minimum)

Programming Time (Normalized) 156 μs/byte (10 ms/64-byte block) 15.6 μs/byte (1 ms/64-byte block)

Programming Entry Low Voltage, Key Sequence VPP and LVP

Code Protection Single block, all or nothing Multiple code protection blocks

Configuration Words Stored in last 4 words of

Program Memory space

Stored in Configuration Space,

starting at 300000h

Start-up Time from Sleep 200 μs (typical) 10 μs (typical)

Power-up Timer Always on Configurable

Data EEPROM Not available Available

Brown-out Reset Simple BOR(1) Programmable BOR

LVD Not available Available

A/D Calibration Required Not required

In-Circuit Emulation Not available Available

TMR3 Not available Available

Second MSSP Available(2) Not available

Note 1: Brown-out Reset is not available on PIC18LFXXJ10 devices.

2: Available on 40/44-pin devices only.

PIC18F45J10 FAMILY

B.1 Power Requirement Differences

The most significant difference between the

PIC18F45J10 family and PIC18F4520 device families

is the power requirements. PIC18F45J10 family

devices are designed on a smaller process; this results

in lower maximum voltage and higher leakage current.

The operating voltage range for PIC18F45J10 family

devices is 2.0V to 3.6V. One of the VDD pins is separated

for the core logic supply (VDDCORE). This pin has specific

voltage and capacitor requirements as described in

Section 24.0 “Electrical Characteristics”.

The current specifications for PIC18F45J10 family

devices are yet to be determined.

B.2 Pin Differences

There are several differences in the pinouts between

the PIC18F45J10 family and the PIC18F4520 families:

• Input voltage tolerance

• Output current capabilities

• Available I/O

Pins on the PIC18F45J10 family that have digital only

input capability will tolerate voltages up to 5.5V and are

thus tolerant to voltages above VDD. Table 10-1 in

Section 10.0 “I/O Ports” contains the complete list.

In addition to input differences, there are output differ-

ences as well. Not all I/O pins can source or sink equal

levels of current. Only PORTB and PORTC support the

25 mA source/sink capability that is supported by all

output pins on the PIC18F4520. Table 10-2 in

Section 10.0 “I/O Ports” contains the complete list of

output capabilities.

There are additional differences in how some pin func-

tions are implemented on PIC18F45J10 family

devices. First, the OSC1/OSC2 oscillator pins are

strictly dedicated to the external oscillator function;

there is no option to re-allocate these pins to I/O (RA6

or RA7) as on PIC18F4520 devices. Second, the

MCLR pin is dedicated only to MCLR and cannot be

configured as an input (RE3). Finally, RA4 does not

exist on PIC18F45J10 family devices.

All of these pin differences (including power pin

differences) should be accounted for when making a

conversion between PIC18F4520 and PIC18F45J10

family devices.

B.3 Oscillator Differences

PIC18F4520 family devices have a greater range of

oscillator options than PIC18F45J10 family devices.

The latter family is limited primarily to operating modes

that support HS and EC oscillators.

In addition, the PIC18F45J10 family has an internal RC

oscillator with only a fixed 32 kHz output. The higher

frequency RC modes of the PIC18F4520 family are not

available.

B.4 Peripherals

The PIC18F45J10 family is able to operate at 40 MHz

down to 2.15 volts unlike the PIC18F4520 family where

40 MHz operation is limited to 4.2 +V applications.

Peripherals must also be considered when making a

conversion between the PIC18F45J10 family and the

PIC18F4520 families:

•Data EEPROM: PIC18F45J10 family devices do

not have this module.

•BOR: PIC18F45J10 family devices do not have a

programmable BOR. Simple brown-out capability

is provided through the use of the internal voltage

regulator (not available in PIC18LFXXJ10

devices).

•LVD: PIC18F45J10 family devices do not have

this module.

• Timer3 (TMR3) has been removed from the

PIC18F45J10 family.

• The T0CKI/C1OUT pins have been moved from

RA4 to RB5.

• The 40/44-pin devices in the PIC18F45J10 family

have a second MSSP module available on pins

RD<3:0>.

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

INDEX

A/D ................................................................................... 215

A/D Converter Interrupt, Configuring ....................... 219

Acquisition Requirements ........................................ 220

ADCAL Bit ................................................................ 223

ADCON0 Register .................................................... 215

ADCON1 Register .................................................... 215

ADCON2 Register .................................................... 215

ADRESH Register ............................................ 215, 218

ADRESL Register .................................................... 215

Analog Port Pins, Configuring .................................. 221

Associated Registers ............................................... 223

Automatic Acquisition Time ...................................... 221

Calculating the Minimum Required

Acquisition Time .............................................. 220

Calibration ................................................................ 223

Configuring the Module ............................................ 219

Conversion Clock (TAD) ........................................... 221

Conversion Status (GO/DONE Bit) .......................... 218

Conversions ............................................................. 222

Converter Characteristics ........................................ 334

Operation in Power-Managed Modes ...................... 223

Special Event Trigger (ECCP) ......................... 136, 222

Use of the ECCP2 Trigger ....................................... 222

Absolute Maximum Ratings ............................................. 303

AC (Timing) Characteristics ............................................. 317

Load Conditions for Device

Timing Specifications ...................................... 318

Parameter Symbology ............................................. 317

Temperature and Voltage Specifications ................. 318

Timing Conditions .................................................... 318

Access Bank

Mapping with Indexed Literal Offset Mode ................. 70

ACKSTAT ........................................................................ 182

ACKSTAT Status Flag ..................................................... 182

ADCAL Bit ........................................................................ 223

ADCON0 Register ............................................................ 215

GO/DONE Bit ........................................................... 218

ADCON1 Register ............................................................ 215

ADCON2 Register ............................................................ 215

ADDFSR .......................................................................... 292

ADDLW ............................................................................ 255

ADDULNK ........................................................................ 292

ADDWF ............................................................................ 255

ADDWFC ......................................................................... 256

ADRESH Register ............................................................ 215

ADRESL Register .................................................... 215, 218

Analog-to-Digital Converter. See A/D.

ANDLW ............................................................................ 256

ANDWF ............................................................................ 257

Assembler

MPASM Assembler .................................................. 300

Auto-Wake-up on Sync Break Character ......................... 206

Bank Select Register (BSR) ............................................... 58

Baud Rate Generator ....................................................... 178

BC .................................................................................... 257

BCF .................................................................................. 258

BF .................................................................................... 182

BF Status Flag ................................................................. 182

Block Diagrams

A/D ........................................................................... 218

Analog Input Model .................................................. 219

Baud Rate Generator .............................................. 178

Capture Mode Operation ......................................... 129

Comparator Analog Input Model .............................. 229

Comparator I/O Operating Modes ........................... 226

Comparator Output .................................................. 228

Comparator Voltage Reference ............................... 232

Comparator Voltage Reference Output

Buffer Example ................................................ 233

Compare Mode Operation ....................................... 130

Device Clock .............................................................. 30

Enhanced PWM ....................................................... 137

EUSART Receive .................................................... 205

EUSART Transmit ................................................... 203

External Power-on Reset Circuit

(Slow VDD Power-up) ........................................ 43

Fail-Safe Clock Monitor ........................................... 245

Generic I/O Port Operation ........................................ 97

Interrupt Logic ............................................................ 84

MSSP (I2C Master Mode) ........................................ 176

MSSP (I2C Mode) .................................................... 159

MSSP (SPI Mode) ................................................... 149

On-Chip Reset Circuit ................................................ 41

PIC18F24J10/25J10 .................................................. 10

PIC18F44J10/45J10 .................................................. 11

PLL ............................................................................ 29

PORTD and PORTE (Parallel Slave Port) ............... 113

PWM Operation (Simplified) .................................... 132

Reads from Flash Program Memory ......................... 75

Single Comparator ................................................... 227

Table Read Operation ............................................... 71

Table Write Operation ............................................... 72

Table Writes to Flash Program Memory .................... 77

Timer0 in 16-Bit Mode ............................................. 116

Timer0 in 8-Bit Mode ............................................... 116

Timer1 ..................................................................... 120

Timer1 (16-Bit Read/Write Mode) ............................ 121

Timer2 ..................................................................... 126

Watchdog Timer ...................................................... 242

BN .................................................................................... 258

BNC ................................................................................. 259

BNN ................................................................................. 259

BNOV .............................................................................. 260

BNZ ................................................................................. 260

BOR. See Brown-out Reset.

BOV ................................................................................. 263

BRA ................................................................................. 261

Break Character (12-Bit) Transmit and Receive .............. 208

BRG. See Baud Rate Generator.

Brown-out Reset (BOR) ..................................................... 43

and On-Chip Voltage Regulator .............................. 243

Disabling in Sleep Mode ............................................ 43

BSF .................................................................................. 261

BTFSC ............................................................................. 262

BTFSS ............................................................................. 262

BTG ................................................................................. 263

BZ .................................................................................... 264

C Compilers

MPLAB C18 ............................................................. 300

MPLAB C30 ............................................................. 300

PIC18F45J10 FAMILY

Calibration (A/D Converter) .............................................. 223

CALL ................................................................................ 264

CALLW .............................................................................293

Capture (CCP Module) ..................................................... 129

Associated Registers ............................................... 131

CCP Pin Configuration ............................................. 129

CCPRxH:CCPRxL Registers ................................... 129

Prescaler ..................................................................129

Software Interrupt .................................................... 129

Capture (ECCP Module) .................................................. 136

Capture/Compare/PWM (CCP) ........................................ 127

Capture Mode. See Capture.

CCP Modules and Timer Resources ....................... 128

CCPRxH Register .................................................... 128

CCPRxL Register ..................................................... 128

Compare Mode. See Compare.

Interactions Between ECCP1/CCP1 and

CCP2 for Timer Resources ..............................128

Module Configuration ...............................................128

Clock Sources .................................................................... 30

Default System Clock on Reset ................................. 31

Selection Using OSCCON Register ........................... 31

CLRF ................................................................................265

CLRWDT ..........................................................................265

Code Examples

16 x 16 Signed Multiply Routine ................................ 82

16 x 16 Unsigned Multiply Routine ............................ 82

8 x 8 Signed Multiply Routine .................................... 81

8 x 8 Unsigned Multiply Routine ................................ 81

Changing Between Capture Prescalers ................... 129

Computed GOTO Using an Offset Value ................... 55

Erasing a Flash Program Memory Row .....................76

Fast Register Stack .................................................... 55

How to Clear RAM (Bank 1) Using

Indirect Addressing ............................................ 66

Implementing a Real-Time Clock Using

a Timer1 Interrupt Service ...............................124

Initializing PORTA ...................................................... 98

Initializing PORTB .................................................... 101

Initializing PORTC .................................................... 104

Initializing PORTD .................................................... 107

Initializing PORTE .................................................... 110

Loading the SSP1BUF (SSP1SR) Register ............. 152

Reading a Flash Program Memory Word .................. 75

Saving STATUS, WREG and

BSR Registers in RAM ....................................... 95

Writing to Flash Program Memory .............................78

Code Protection ............................................................... 235

COMF ............................................................................... 266

Comparator ...................................................................... 225

Analog Input Connection Considerations ................. 229

Associated Registers ............................................... 229

Configuration ............................................................ 226

Effects of a Reset ..................................................... 228

Interrupts .................................................................. 228

Operation .................................................................227

Operation During Sleep ........................................... 228

Outputs ....................................................................227

Reference ................................................................ 227

External Signal ................................................. 227

Internal Signal .................................................. 227

Response Time ........................................................ 227

Comparator Specifications ............................................... 316

Comparator Voltage Reference ....................................... 231

Accuracy and Error .................................................. 232

Associated Registers ............................................... 233

Configuring .............................................................. 231

Connection Considerations ...................................... 232

Effects of a Reset .................................................... 232

Operation During Sleep ........................................... 232

Compare (CCP Module) .................................................. 130

Associated Registers ............................................... 131

CCPRx Register ...................................................... 130

Pin Configuration ..................................................... 130

Software Interrupt .................................................... 130

Special Event Trigger .............................................. 130

Timer1 Mode Selection ............................................ 130

Compare (ECCP Module) ................................................ 136

Special Event Trigger ...................................... 136, 222

Computed GOTO ............................................................... 55

Configuration Bits ............................................................ 235

Configuration Register Protection .................................... 247

Context Saving During Interrupts ....................................... 95

CPFSEQ .......................................................................... 266

CPFSGT .......................................................................... 267

CPFSLT ........................................................................... 267

Crystal Oscillator/Ceramic Resonator ................................ 27

Customer Change Notification Service ............................ 363

Customer Notification Service ......................................... 363

Customer Support ............................................................ 363

Data Addressing Modes .................................................... 66

Comparing Addressing Modes with the

Extended Instruction Set Enabled ..................... 69

Direct ......................................................................... 66

Indexed Literal Offset ................................................ 68

Instructions Affected .......................................... 68

Indirect ....................................................................... 66

Inherent and Literal .................................................... 66

Data Memory ..................................................................... 58

Access Bank .............................................................. 60

and the Extended Instruction Set .............................. 68

Bank Select Register (BSR) ...................................... 58

General Purpose Registers ....................................... 60

Map for PIC18F45J10 Family .................................... 59

Special Function Registers ........................................ 61

DAW ................................................................................ 268

DC Characteristics ........................................................... 313

Power-Down and Supply Current ............................ 306

Supply Voltage ........................................................ 305

DCFSNZ .......................................................................... 269

DECF ............................................................................... 268

DECFSZ .......................................................................... 269

Default System Clock ........................................................ 31

Development Support ...................................................... 299

Device Overview .................................................................. 7

Core Features .............................................................. 7

Details on Individual Family Members ......................... 8

Features (table) ........................................................... 9

Other Special Features ................................................ 8

Direct Addressing .............................................................. 67

PIC18F45J10 FAMILY

Effect on Standard PIC Instructions ................................. 296

Effects of Power-Managed Modes on

Various Clock Sources ............................................... 32

Electrical Characteristics .................................................. 303

Enhanced Capture/Compare/PWM (ECCP) .................... 135

Associated Registers ............................................... 148

Capture and Compare Modes .................................. 136

Capture Mode. See Capture (ECCP Module).

Outputs and Configuration ....................................... 136

Pin Configurations for ECCP1 Modes ...................... 136

PWM Mode. See PWM (ECCP Module).

Standard PWM Mode ............................................... 136

Timer Resources ...................................................... 136

Enhanced PWM Mode. See PWM (ECCP Module). ........ 137

Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART). See EUSART.

Equations

A/D Acquisition Time ................................................ 220

A/D Minimum Charging Time ................................... 220

Errata ................................................................................... 6

EUSART

Asynchronous Mode ................................................ 203

12-Bit Break Transmit and Receive ................. 208

Associated Registers, Receive ........................ 206

Associated Registers, Transmit ....................... 204

Auto-Wake-up on Sync Break ......................... 206

Receiver ........................................................... 205

Setting Up 9-Bit Mode with

Address Detect ........................................ 205

Transmitter ....................................................... 203

Baud Rate Generator

Operation in Power-Managed Mode ................ 197

Baud Rate Generator (BRG) .................................... 197

Associated Registers ....................................... 198

Auto-Baud Rate Detect .................................... 201

Baud Rate Error, Calculating ........................... 198

Baud Rates, Asynchronous Modes ................. 199

High Baud Rate Select (BRGH Bit) ................. 197

Sampling .......................................................... 197

Synchronous Master Mode ...................................... 209

Associated Registers, Receive ........................ 211

Associated Registers, Transmit ....................... 210

Reception ......................................................... 211

Transmission ................................................... 209

Synchronous Slave Mode ........................................ 212

Associated Registers, Receive ........................ 213

Associated Registers, Transmit ....................... 212

Reception ......................................................... 213

Transmission ................................................... 212

Extended Instruction Set

ADDFSR .................................................................. 292

ADDULNK ................................................................ 292

and Using MPLAB IDE Tools ................................... 298

CALLW ..................................................................... 293

Considerations for Use ............................................ 296

MOVSF .................................................................... 293

MOVSS .................................................................... 294

PUSHL ..................................................................... 294

SUBFSR .................................................................. 295

SUBULNK ................................................................ 295

Syntax ...................................................................... 291

External Clock Input (EC Modes) ....................................... 28

Fail-Safe Clock Monitor ........................................... 235, 245

Interrupts in Power-Managed Modes ...................... 246

POR or Wake-up from Sleep ................................... 246

WDT During Oscillator Failure ................................. 245

Fast Register Stack ........................................................... 55

Firmware Instructions ...................................................... 249

Flash Configuration Words .............................................. 235

Flash Program Memory ..................................................... 71

Associated Registers ................................................. 79

Control Registers ....................................................... 72

EECON1 and EECON2 ..................................... 72

TABLAT (Table Latch) ....................................... 74

TBLPTR (Table Pointer) .................................... 74

Erase Sequence ........................................................ 76

Erasing ...................................................................... 76

Operation During Code-Protect ................................. 79

Reading ..................................................................... 75

Table Pointer

Boundaries Based on Operation ....................... 74

Table Pointer Boundaries .......................................... 74

Table Reads and Table Writes .................................. 71

Write Sequence ......................................................... 77

Writing To .................................................................. 77

Protection Against Spurious Writes ................... 79

Unexpected Termination ................................... 79

Write Verify ........................................................ 79

FSCM. See Fail-Safe Clock Monitor.

GOTO .............................................................................. 270

Hardware Multiplier ............................................................ 81

Introduction ................................................................ 81

Operation ................................................................... 81

Performance Comparison .......................................... 81

I/O Ports ............................................................................ 97

I2C Mode (MSSP)

Acknowledge Sequence Timing .............................. 185

Associated Registers ............................................... 192

Baud Rate Generator .............................................. 178

Bus Collision

During a Repeated Start Condition .................. 190

During a Stop Condition .................................. 191

Clock Arbitration ...................................................... 179

Clock Stretching ...................................................... 171

10-Bit Slave Receive Mode (SEN = 1) ............ 171

10-Bit Slave Transmit Mode ............................ 171

7-Bit Slave Receive Mode (SEN = 1) .............. 171

7-Bit Slave Transmit Mode .............................. 171

Clock Synchronization and the CKP Bit .................. 172

Effects of a Reset .................................................... 186

General Call Address Support ................................. 175

I2C Clock Rate w/BRG ............................................ 178

Master Mode ............................................................ 176

Baud Rate Generator ...................................... 178

Operation ......................................................... 177

Reception ........................................................ 182

Repeated Start Condition Timing .................... 181

Start Condition Timing ..................................... 180

Transmission ................................................... 182

PIC18F45J10 FAMILY

Multi-Master Communication, Bus Collision

and Arbitration .................................................. 186

Multi-Master Mode ...................................................186

Operation .................................................................164

Read/Write Bit Information (R/W Bit) ............... 164, 166

Registers .................................................................. 159

Serial Clock (SCKx/SCLx) ....................................... 166

Slave Mode ..............................................................164

Addressing ....................................................... 164

Reception ......................................................... 166

Transmission .................................................... 166

Sleep Operation ....................................................... 186

Stop Condition Timing ..............................................185

INCF .................................................................................270

INCFSZ ............................................................................ 271

In-Circuit Debugger .......................................................... 247

In-Circuit Serial Programming (ICSP) ...................... 235, 247

Indexed Literal Offset Addressing

and Standard PIC18 Instructions ............................. 296

Indexed Literal Offset Mode ............................................. 296

Indirect Addressing ............................................................ 67

INFSNZ ............................................................................271

Initialization Conditions for All Registers ...................... 47–50

Instruction Cycle ................................................................. 56

Clocking Scheme .......................................................56

Instruction Flow/Pipelining .................................................56

Instruction Set .................................................................. 249

ADDLW .................................................................... 255

ADDWF .................................................................... 255

ADDWF (Indexed Literal Offset Mode) .................... 297

ADDWFC .................................................................256

ANDLW .................................................................... 256

ANDWF .................................................................... 257

BC ............................................................................ 257

BCF .......................................................................... 258

BN ............................................................................ 258

BNC ......................................................................... 259

BNN ......................................................................... 259

BNOV ....................................................................... 260

BNZ .......................................................................... 260

BOV ......................................................................... 263

BRA .......................................................................... 261

BSF .......................................................................... 261

BSF (Indexed Literal Offset Mode) .......................... 297

BTFSC ..................................................................... 262

BTFSS .....................................................................262

BTG .......................................................................... 263

BZ ............................................................................ 264

CALL ........................................................................ 264

CLRF ........................................................................265

CLRWDT ..................................................................265

COMF ......................................................................266

CPFSEQ .................................................................. 266

CPFSGT .................................................................. 267

CPFSLT ................................................................... 267

DAW ......................................................................... 268

DCFSNZ .................................................................. 269

DECF .......................................................................268

DECFSZ ................................................................... 269

Extended Instruction Set .......................................... 291

General Format ........................................................ 251

GOTO ......................................................................270

INCF ......................................................................... 270

INCFSZ ....................................................................271

INFSNZ ....................................................................271

IORLW ..................................................................... 272

IORWF ..................................................................... 272

LFSR ....................................................................... 273

MOVF ...................................................................... 273

MOVFF .................................................................... 274

MOVLB .................................................................... 274

MOVLW ................................................................... 275

MOVWF ................................................................... 275

MULLW .................................................................... 276

MULWF .................................................................... 276

NEGF ....................................................................... 277

NOP ......................................................................... 277

Opcode Field Descriptions ....................................... 250

POP ......................................................................... 278

PUSH ....................................................................... 278

RCALL ..................................................................... 279

RESET ..................................................................... 279

RETFIE .................................................................... 280

RETLW .................................................................... 280

RETURN .................................................................. 281

RLCF ....................................................................... 281

RLNCF ..................................................................... 282

RRCF ....................................................................... 282

RRNCF .................................................................... 283

SETF ....................................................................... 283

SETF (Indexed Literal Offset Mode) ........................ 297

SLEEP ..................................................................... 284

Standard Instructions ............................................... 249

SUBFWB ................................................................. 284

SUBLW .................................................................... 285

SUBWF .................................................................... 285

SUBWFB ................................................................. 286

SWAPF .................................................................... 286

TBLRD ..................................................................... 287

TBLWT .................................................................... 288

TSTFSZ ................................................................... 289

XORLW ................................................................... 289

XORWF ................................................................... 290

INTCON Registers ............................................................. 85

Inter-Integrated Circuit. See I2C Mode.

Internal Oscillator Block ..................................................... 30

Internal RC Oscillator

Use with WDT .......................................................... 242

Internet Address .............................................................. 363

Interrupt Sources ............................................................. 235

A/D Conversion Complete ....................................... 219

Capture Complete (CCP) ......................................... 129

Compare Complete (CCP) ....................................... 130

Interrupt-on-Change (RB7:RB4) .............................. 101

INTx Pin ..................................................................... 95

PORTB, Interrupt-on-Change .................................... 95

TMR0 ......................................................................... 95

TMR0 Overflow ........................................................ 117

TMR1 Overflow ........................................................ 119

TMR2-to-PR2 Match (PWM) ............................ 132, 137

Interrupts ............................................................................ 83

Interrupts, Flag Bits

Interrupt-on-Change (RB7:RB4)

Flag (RBIF Bit) ................................................. 101

INTOSC, INTRC. See Internal Oscillator Block.

IORLW ............................................................................. 272

IORWF ............................................................................. 272

IPR Registers ..................................................................... 92

PIC18F45J10 FAMILY

LFSR ................................................................................ 273

Master Clear (MCLR) ......................................................... 43

Master Synchronous Serial Port (MSSP). See MSSP.

Memory Organization ......................................................... 51

Data Memory ............................................................. 58

Program Memory ....................................................... 51

Memory Programming Requirements .............................. 315

Microchip Internet Web Site ............................................. 363

MOVF ............................................................................... 273

MOVFF ............................................................................ 274

MOVLB ............................................................................ 274

MOVLW ........................................................................... 275

MOVSF ............................................................................ 293

MOVSS ............................................................................ 294

MOVWF ........................................................................... 275

MPLAB ASM30 Assembler, Linker, Librarian .................. 300

MPLAB ICD 2 In-Circuit Debugger .................................. 301

MPLAB ICE 2000 High-Performance

Universal In-Circuit Emulator ................................... 301

MPLAB Integrated Development

Environment Software .............................................. 299

MPLAB PM3 Device Programmer ................................... 301

MPLAB REAL ICE In-Circuit Emulator System ................ 301

MPLINK Object Linker/MPLIB Object Librarian ............... 300

MSSP

ACK Pulse ........................................................ 164, 166

Control Registers (general) ...................................... 149

I2C Mode. See I2C Mode.

Module Overview ..................................................... 149

SPI Master/Slave Connection .................................. 153

SSPxBUF Register .................................................. 154

SSPxSR Register ..................................................... 154

MULLW ............................................................................ 276

MULWF ............................................................................ 276

NEGF ............................................................................... 277

NOP ................................................................................. 277

Notable Differences Between PIC18F4520

and PIC18F45J10 Families ...................................... 350

Oscillator Options ..................................................... 351

Peripherals ............................................................... 351

Pinouts ..................................................................... 351

Power Requirements ............................................... 351

Oscillator Configuration ...................................................... 27

EC .............................................................................. 27

ECPLL ........................................................................ 27

HS .............................................................................. 27

HS Modes .................................................................. 27

HSPLL ........................................................................ 27

Internal Oscillator Block ............................................. 30

INTRC ........................................................................ 27

Oscillator Selection .......................................................... 235

Oscillator Start-up Timer (OST) ......................................... 33

Oscillator Switching ............................................................ 30

Oscillator Transitions ......................................................... 31

Oscillator, Timer1 ............................................................. 119

Packaging Information ..................................................... 337

Details ...................................................................... 339

Marking .................................................................... 337

Parallel Slave Port (PSP) ......................................... 107, 113

Associated Registers ............................................... 114

CS (Chip Select) ...................................................... 113

PORTD .................................................................... 113

RD (Read Input) ...................................................... 113

Select (PSPMODE Bit) .................................... 107, 113

WR (Write Input) ...................................................... 113

PICSTART Plus Development Programmer .................... 302

PIE Registers ..................................................................... 90

Pin Functions

MCLR .................................................................. 12, 16

OSC1/CLKI .......................................................... 12, 16

OSC2/CLKO ........................................................ 12, 16

RA0/AN0 .............................................................. 13, 17

RA1/AN1 .............................................................. 13, 17

RA2/AN2/VREF-/CVREF ....................................... 13, 17

RA3/AN3/VREF+ .................................................. 13, 17

RA5/AN4/SS1/C2OUT ......................................... 13, 17

RB0/INT0/FLT0/AN12 ......................................... 14, 18

RB1/INT1/AN10 ................................................... 14, 18

RB2/INT2/AN8 ..................................................... 14, 18

RB3/AN9/CCP2 ................................................... 14, 18

RB4/KBI0/AN11 ................................................... 14, 18

RB5/KBI1/C1OUT ...................................................... 18

RB5/KBI1/T0CKI/C1OUT .......................................... 14

RB6/KBI2/PGC .................................................... 14, 18

RB7/KBI3/PGD .................................................... 14, 18

RC0/T1OSO/T1CKI ............................................. 15, 19

RC1/T1OSI/CCP2 ............................................... 15, 19

RC2/CCP1 ................................................................. 15

RC2/CCP1/P1A ......................................................... 19

RC3/SCK1/SCL1 ................................................. 15, 19

RC4/SDI1/SDA1 .................................................. 15, 19

RC5/SDO1 ........................................................... 15, 19

RC6/TX/CK .......................................................... 15, 19

RC7/RX/DT .......................................................... 15, 19

RD0/PSP0/SCK2/SCL2 ............................................. 20

RD1/PSP1/SDI2/SDA2 .............................................. 20

RD2/PSP2/SDO2 ...................................................... 20

RD3/PSP3/SS2 ......................................................... 20

RD4/PSP4 ................................................................. 20

RD5/PSP5/P1B ......................................................... 20

RD6/PSP6/P1C ......................................................... 20

RD7/PSP7/P1D ......................................................... 20

RE0/RD/AN5 ............................................................. 21

RE1/WR/AN6 ............................................................. 21

RE2/CS/AN7 .............................................................. 21

VDD ...................................................................... 15, 21

VDDCORE/VCAP .................................................... 15, 21

VSS ...................................................................... 15, 21

Pinout I/O Descriptions

PIC18F24J10/25J10 .................................................. 12

PIC18F44J10/45J10 .................................................. 16

PIR Registers ..................................................................... 88

PLL Frequency Multiplier ................................................... 29

ECPLL Oscillator Mode ............................................. 29

HSPLL Oscillator Mode ............................................. 29

POP ................................................................................. 278

POR. See Power-on Reset.

PIC18F45J10 FAMILY

PORTA

Associated Registers ............................................... 100

LATA Register ............................................................ 98

PORTA Register ........................................................ 98

TRISA Register .......................................................... 98

PORTB

Associated Registers ............................................... 103

LATB Register .......................................................... 101

PORTB Register ...................................................... 101

RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 101

TRISB Register ........................................................ 101

PORTC

Associated Registers ............................................... 106

LATC Register ......................................................... 104

PORTC Register ...................................................... 104

RC3/SCK1/SCL1 Pin ............................................... 166

TRISC Register ........................................................ 104

PORTD

Associated Registers ............................................... 109

LATD Register ......................................................... 107

Parallel Slave Port (PSP) Function .......................... 107

PORTD Register ...................................................... 107

TRISD Register ........................................................ 107

PORTE

Associated Registers ............................................... 112

LATE Register .......................................................... 110

PORTE Register ...................................................... 110

PSP Mode Select (PSPMODE Bit) .......................... 107

TRISE Register ........................................................ 110

Power-Managed Modes ..................................................... 35

and EUSART Operation ........................................... 197

and Multiple Sleep Commands .................................. 36

and PWM Operation ................................................ 147

and SPI Operation ................................................... 157

Clock Transitions and Status Indicators ..................... 36

Entering ...................................................................... 35

Exiting Idle and Sleep Modes .................................... 40

by Reset ............................................................. 40

by WDT Time-out ...............................................40

Without an Oscillator Start-up Delay .................. 40

Idle Modes ................................................................. 38

PRI_IDLE ........................................................... 39

RC_IDLE ............................................................ 40

SEC_IDLE .......................................................... 39

Run Modes ................................................................. 36

PRI_RUN ...........................................................36

RC_RUN ............................................................ 37

SEC_RUN .......................................................... 36

Selecting ....................................................................35

Sleep Mode ................................................................ 38

Summary (table) ........................................................ 35

Power-on Reset (POR) ......................................................43

Power-up Timer (PWRT) ........................................... 44

Time-out Sequence .................................................... 44

Power-up Delays ................................................................ 33

Power-up Timer (PWRT) .............................................. 33, 44

Prescaler

Timer2 ...................................................................... 138

Prescaler, Timer0 ............................................................. 117

Prescaler, Timer2 ............................................................. 133

PRI_IDLE Mode ................................................................. 39

PRI_RUN Mode ................................................................. 36

Program Counter ................................................................ 53

PCL, PCH and PCU Registers ................................... 53

PCLATH and PCLATU Registers ..............................53

Program Memory

and Extended Instruction Set .................................... 70

Flash Configuration Words ........................................ 52

Instructions ................................................................ 57

Two-Word .......................................................... 57

Interrupt Vector .................................................... 51, 52

Look-up Tables .......................................................... 55

Map and Stack (diagram) .......................................... 51

Memory Maps

Hard Vectors and Configuration Words ............. 52

Reset Vector ........................................................ 51, 52

Program Verification and Code Protection ...................... 247

Programming, Device Instructions ................................... 249

PSP. See Parallel Slave Port.

Pulse-Width Modulation. See PWM (CCP Module)

and PWM (ECCP Module).

PUSH ............................................................................... 278

PUSH and POP Instructions .............................................. 54

PUSHL ............................................................................. 294

PWM (CCP Module)

Associated Registers ............................................... 134

Auto-Shutdown (CCP1 Only) ................................... 133

CCPR1H:CCPR1L Registers ................................... 137

Duty Cycle ....................................................... 132, 138

Example Frequencies/Resolutions .................. 133, 138

Period .............................................................. 132, 137

Setup for Operation ................................................. 133

TMR2-to-PR2 Match ........................................ 132, 137

PWM (ECCP Module) ...................................................... 137

Direction Change in Full-Bridge Output Mode ......... 142

Effects of a Reset .................................................... 147

Enhanced PWM Auto-Shutdown ............................. 144

Full-Bridge Application Example .............................. 142

Full-Bridge Mode ..................................................... 141

Half-Bridge Mode ..................................................... 140

Half-Bridge Output Mode Applications Example ...... 140

Operation in Power-Managed Modes ...................... 147

Operation with Fail-Safe Clock Monitor ................... 147

Output Configurations .............................................. 138

Output Relationships (Active-High) .......................... 139

Output Relationships (Active-Low) .......................... 139

Programmable Dead-Band Delay ............................ 144

Setup for PWM Operation ........................................ 147

Start-up Considerations ........................................... 146

Q Clock .................................................................... 133, 138

RAM. See Data Memory.

RBIF Bit ........................................................................... 101

RC_IDLE Mode .................................................................. 40

RC_RUN Mode .................................................................. 37

RCALL ............................................................................. 279

RCON Register

Bit Status During Initialization .................................... 46

Reader Response ............................................................ 364

Registers

ADCON0 (A/D Control 0) ......................................... 215

ADCON1 (A/D Control 1) ......................................... 216

ADCON2 (A/D Control 2) ......................................... 217

BAUDCON (Baud Rate Control) .............................. 196

CCP1CON (ECCP1 Control) ................................... 135

CCPxCON (CCPx Control) ...................................... 127

PIC18F45J10 FAMILY

CMCON (Comparator Control) ................................ 225

CONFIG1H (Configuration 1 High) .......................... 237

CONFIG1L (Configuration 1 Low) ............................ 237

CONFIG2H (Configuration 2 High) .......................... 239

CONFIG2L (Configuration 2 Low) ............................ 238

CONFIG3H (Configuration 3 High) .......................... 240

CONFIG3L (Configuration 3 Low) ............................ 240

CVRCON (Comparator Voltage

Reference Control) .......................................... 231

DEVID1 (Device ID Register 1) ................................ 241

DEVID2 (Device ID Register 2) ................................ 241

ECCP1DEL (PWM Dead-Band Delay) .................... 144

EECON1 (EEPROM Control 1) .................................. 73

EUSART Receive Status and Control ...................... 195

INTCON (Interrupt Control) ........................................ 85

INTCON2 (Interrupt Control 2) ................................... 86

INTCON3 (Interrupt Control 3) ................................... 87

IPR1 (Peripheral Interrupt Priority 1) .......................... 92

IPR2 (Peripheral Interrupt Priority 2) .......................... 93

IPR3 (Peripheral Interrupt Priority 3) .......................... 93

OSCCON (Oscillator Control) .................................... 32

OSCTUNE (PLL Control) ........................................... 29

PIE1 (Peripheral Interrupt Enable 1) .......................... 90

PIE2 (Peripheral Interrupt Enable 2) .......................... 91

PIE3 (Peripheral Interrupt Enable 3) .......................... 91

PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 88

PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 89

PIR3 (Peripheral Interrupt Request (Flag) 3) ............. 89

RCON (Reset Control) ......................................... 42, 94

SSPxCON1 (MSSPx Control 1, I2C Mode) .............. 161

SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 151

SSPxCON2 (MSSPx Control 2,

I2C Master Mode) ............................................ 162

SSPxCON2 (MSSPx Control 2,

I2C Slave Mode) .............................................. 163

SSPxSTAT (MSSPx Status, I2C Mode) ................... 160

SSPxSTAT (MSSPx Status, SPI Mode) .................. 150

STATUS ..................................................................... 65

STKPTR (Stack Pointer) ............................................ 54

T0CON (Timer0 Control) .......................................... 115

T1CON (Timer1 Control) .......................................... 119

T2CON (Timer2 Control) .......................................... 125

TRISE (PORTE/PSP Control) .................................. 111

TXSTA (EUSART Transmit Status

and Control) ..................................................... 194

WDTCON (Watchdog Timer Control) ...................... 242

RESET ............................................................................. 279

Reset

Brown-out Reset (BOR) ............................................. 41

Configuration Mismatch (CM) .................................... 41

MCLR Reset, During Power-Managed Modes ........... 41

MCLR Reset, Normal Operation ................................ 41

Power-on Reset (POR) .............................................. 41

RESET Instruction ..................................................... 41

Stack Full Reset ......................................................... 41

Stack Underflow Reset .............................................. 41

Watchdog Timer (WDT) Reset ................................... 41

Resets .............................................................................. 235

Brown-out Reset (BOR) ........................................... 235

Oscillator Start-up Timer (OST) ............................... 235

Power-on Reset (POR) ............................................ 235

Power-up Timer (PWRT) ......................................... 235

RETFIE ............................................................................ 280

RETLW ............................................................................ 280

RETURN .......................................................................... 281

Return Address Stack ........................................................ 53

Return Stack Pointer (STKPTR) ........................................ 54

Revision History ............................................................... 349

RLCF ............................................................................... 281

RLNCF ............................................................................. 282

RRCF ............................................................................... 282

RRNCF ............................................................................ 283

SCKx ............................................................................... 149

SDIx ................................................................................. 149

SDOx ............................................................................... 149

SEC_IDLE Mode ............................................................... 39

SEC_RUN Mode ................................................................ 36

Serial Clock, SCKx .......................................................... 149

Serial Data In (SDIx) ........................................................ 149

Serial Data Out (SDOx) ................................................... 149

Serial Peripheral Interface. See SPI Mode.

SETF ............................................................................... 283

Slave Select (SSx) ........................................................... 149

SLEEP ............................................................................. 284

Sleep

OSC1 and OSC2 Pin States ...................................... 33

Software Simulator (MPLAB SIM) ................................... 300

Special Event Trigger. See Compare (ECCP Module).

Special Event Trigger. See Compare (ECCP/CCP Modules).

Special Features of the CPU ........................................... 235

Special Function Registers ................................................ 61

Map ............................................................................ 61

SPI Mode (MSSP)

Associated Registers ............................................... 158

Bus Mode Compatibility ........................................... 157

Clock Speed and Module Interactions ..................... 157

Effects of a Reset .................................................... 157

Enabling SPI I/O ...................................................... 153

Master Mode ............................................................ 154

Master/Slave Connection ........................................ 153

Operation ................................................................. 152

Operation in Power-Managed Modes ...................... 157

Serial Clock ............................................................. 149

Serial Data In ........................................................... 149

Serial Data Out ........................................................ 149

Slave Mode .............................................................. 155

Slave Select ............................................................. 149

Slave Select Synchronization .................................. 155

SPI Clock ................................................................. 154

Typical Connection .................................................. 153

SSPOV ............................................................................ 182

SSPOV Status Flag ......................................................... 182

SSPxSTAT Register

R/W Bit ............................................................ 164, 166

SSx .................................................................................. 149

Stack Full/Underflow Resets .............................................. 55

STATUS Register .............................................................. 65

SUBFSR .......................................................................... 295

SUBFWB ......................................................................... 284

SUBLW ............................................................................ 285

SUBULNK ........................................................................ 295

SUBWF ............................................................................ 285

SUBWFB ......................................................................... 286

SWAPF ............................................................................ 286

Table Pointer Operations (table) ........................................ 74

Table Reads/Table Writes ................................................. 55

TBLRD ............................................................................. 287

TBLWT ............................................................................ 288

PIC18F45J10 FAMILY

Timer0 .............................................................................. 115

Associated Registers ............................................... 117

Clock Source Select (T0CS Bit) ............................... 116

Operation .................................................................116

Overflow Interrupt .................................................... 117

Prescaler ..................................................................117

Prescaler Assignment (PSA Bit) ..............................117

Prescaler Select (T0PS2:T0PS0 Bits) ..................... 117

Prescaler. See Prescaler, Timer0.

Reads and Writes in 16-Bit Mode ............................ 116

Source Edge Select (T0SE Bit) ................................ 116

Switching Prescaler Assignment .............................. 117

Timer1 .............................................................................. 119

16-Bit Read/Write Mode ........................................... 121

Associated Registers ............................................... 124

Interrupt .................................................................... 122

Operation .................................................................120

Oscillator .......................................................... 119, 121

Layout Considerations ..................................... 122

Oscillator, as Secondary Clock .................................. 30

Overflow Interrupt .................................................... 119

Resetting, Using the ECCP/CCP

Special Event Trigger .......................................123

Special Event Trigger (ECCP) ................................. 136

TMR1H Register ...................................................... 119

TMR1L Register .......................................................119

Use as a Clock Source ............................................ 122

Use as a Real-Time Clock .......................................123

Timer2 .............................................................................. 125

Associated Registers ............................................... 126

Interrupt .................................................................... 126

Operation .................................................................125

Output ...................................................................... 126

PR2 Register .................................................... 132, 137

TMR2-to-PR2 Match Interrupt .......................... 132, 137

Timing Diagrams

A/D Conversion ........................................................ 334

Acknowledge Sequence .......................................... 185

Asynchronous Reception ......................................... 206

Asynchronous Transmission .................................... 204

Asynchronous Transmission (Back to Back) ........... 204

Automatic Baud Rate Calculation ............................202

Auto-Wake-up Bit (WUE) During

Normal Operation .............................................207

Auto-Wake-up Bit (WUE) During Sleep ................... 207

Baud Rate Generator with Clock Arbitration ............ 179

BRG Overflow Sequence ......................................... 202

BRG Reset Due to SDAx Arbitration During

Start Condition .................................................189

Brown-out Reset (BOR) ........................................... 322

Bus Collision During a Repeated

Start Condition (Case 1) .................................. 190

Bus Collision During a Repeated

Start Condition (Case 2) .................................. 190

Bus Collision During a

Start Condition (SCLx = 0) ............................... 189

Bus Collision During a

Stop Condition (Case 1) ...................................191

Bus Collision During a

Stop Condition (Case 2) ...................................191

Bus Collision During

Start Condition (SDAx Only) ............................ 188

Bus Collision for Transmit and Acknowledge ........... 187

Capture/Compare/PWM

(Including ECCP Module) ................................ 324

CLKO and I/O .......................................................... 321

Clock Synchronization ............................................. 172

Clock/Instruction Cycle .............................................. 56

EUSART Synchronous Receive (Master/Slave) ...... 333

EUSART Synchronous Transmission

(Master/Slave) ................................................. 333

Example SPI Master Mode (CKE = 0) ..................... 325

Example SPI Master Mode (CKE = 1) ..................... 326

Example SPI Slave Mode (CKE = 0) ....................... 327

Example SPI Slave Mode (CKE = 1) ....................... 328

External Clock (All Modes Except PLL) ................... 319

Fail-Safe Clock Monitor ........................................... 246

First Start Bit Timing ................................................ 180

Full-Bridge PWM Output .......................................... 141

Half-Bridge PWM Output ......................................... 140

I2C Bus Data ............................................................ 329

I2C Bus Start/Stop Bits ............................................ 329

I2C Master Mode (7 or 10-Bit Transmission) ........... 183

I2C Master Mode (7-Bit Reception) .......................... 184

I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 169

I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 174

I2C Slave Mode (10-Bit Transmission) .................... 170

I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 167

I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 173

I2C Slave Mode (7-Bit Transmission) ...................... 168

I2C Slave Mode General Call Address

Sequence (7 or 10-Bit Address Mode) ............ 175

I2C Stop Condition Receive or Transmit Mode ........ 186

Master SSP I2C Bus Data ........................................ 331

Master SSP I2C Bus Start/Stop Bits ........................ 331

Parallel Slave Port (PSP) Read ............................... 114

Parallel Slave Port (PSP) Write ............................... 114

PWM Auto-Shutdown (PRSEN = 0,

Auto-Restart Disabled) .................................... 146

PWM Auto-Shutdown (PRSEN = 1,

Auto-Restart Enabled) ..................................... 146

PWM Direction Change ........................................... 143

PWM Direction Change at Near

100% Duty Cycle ............................................. 143

PWM Output ............................................................ 132

Repeated Start Condition ........................................ 181

Reset, Watchdog Timer (WDT), Oscillator Start-up

Timer (OST) and Power-up Timer (PWRT) ..... 322

Send Break Character Sequence ............................ 208

Slave Synchronization ............................................. 155

Slow Rise Time (MCLR Tied to VDD,

VDD Rise > TPWRT) ............................................ 45

SPI Mode (Master Mode) ......................................... 154

SPI Mode (Slave Mode, CKE = 0) ........................... 156

SPI Mode (Slave Mode, CKE = 1) ........................... 156

Synchronous Reception

(Master Mode, SREN) ..................................... 211

Synchronous Transmission ..................................... 209

Synchronous Transmission (Through TXEN) .......... 210

Time-out Sequence on Power-up

(MCLR Not Tied to VDD), Case 1 ...................... 45

Time-out Sequence on Power-up

(MCLR Not Tied to VDD), Case 2 ...................... 45

Time-out Sequence on Power-up

(MCLR Tied to VDD, VDD Rise /Tpwrt) ............... 44

Timer0 and Timer1 External Clock .......................... 323

Transition for Entry to Idle Mode ................................ 39

Transition for Entry to SEC_RUN Mode .................... 36

Transition for Entry to Sleep Mode ............................ 38

Transition for Two-Speed Start-up (INTRC) ............ 244

PIC18F45J10 FAMILY

Transition for Wake From Idle to Run Mode .............. 39

Transition for Wake From Sleep ................................ 38

Transition From RC_RUN Mode to

PRI_RUN Mode ................................................. 37

Transition to RC_RUN Mode ..................................... 37

Timing Diagrams and Specifications

A/D Conversion Requirements ................................ 335

AC Characteristics

Internal RC Accuracy ....................................... 320

Capture/Compare/PWM Requirements

(Including ECCP Module) ................................ 324

CLKO and I/O Requirements ................................... 321

EUSART Synchronous Receive

Requirements .................................................. 333

EUSART Synchronous Transmission

Requirements .................................................. 333

Example SPI Mode Requirements

(CKE = 0) ................................................. 325, 327

Example SPI Mode Requirements

(CKE = 1) ......................................................... 326

Example SPI Slave Mode Requirements (CKE = 1) 328

External Clock Requirements .................................. 319

I2C Bus Data Requirements (Slave Mode) .............. 330

I2C Bus Start/Stop Bits Requirements

(Slave Mode) ................................................... 329

Master SSP I2C Bus Data Requirements ................ 332

Master SSP I2C Bus Start/Stop Bits

Requirements .................................................. 331

Parallel Slave Port Requirements ............................ 324

PLL Clock ................................................................. 320

Reset, Watchdog Timer, Oscillator Start-up

Timer, Power-up Timer and Brown-out

Reset Requirements ........................................ 322

Timer0 and Timer1 External Clock

Requirements .................................................. 323

Top-of-Stack Access .......................................................... 53

TRISE Register

PSPMODE Bit .......................................................... 107

TSTFSZ ........................................................................... 289

Two-Speed Start-up ................................................. 235, 244

Two-Word Instructions

Example Cases .......................................................... 57

TXSTA Register

BRGH Bit ................................................................. 197

Voltage Reference Specifications .................................... 316

Voltage Regulator (On-Chip) ........................................... 243

Watchdog Timer (WDT) ........................................... 235, 242

Associated Registers ............................................... 242

Control Register ....................................................... 242

During Oscillator Failure .......................................... 245

Programming Considerations .................................. 242

WCOL ...................................................... 180, 181, 182, 185

WCOL Status Flag ................................... 180, 181, 182, 185

WWW Address ................................................................ 363

WWW, On-Line Support ...................................................... 6

XORLW ........................................................................... 289

XORWF ........................................................................... 290

PIC18F45J10 FAMILY

NOTES:

PIC18F45J10 FAMILY

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PIC18F45J10 FAMILY

READER RESP ONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

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DS39682EPIC18F45J10 Family

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

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PIC18F45J10 FAMILY

PIC18F45J10 FAMILY PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device PIC18F24J10/25J10, PIC18F44J10/45J10,

PIC18F24J10/25J10T(1), PIC18F44J10/45J10T(1);

VDD range 2.7V to 3.6V

PIC18LF24J10/25J10, PIC18LF44J10/45J10,

PIC18LF24J10/25J10T(1), PIC18LF44J10/45J10T(1);

VDDCORE range 2.0V to 2.7V

Temperature Range I = -40°C to +85°C (Industrial)

Package PT = TQFP (Thin Quad Flatpack)

SO = SOIC

SP = Skinny Plastic DIP

P=PDIP

ML = QFN

SS = SSOP

Pattern QTP, SQTP, Code or Special Requirements

(blank otherwise)

Examples:

a) PIC18LF45J10-I/P 301 = Industrial temp.,

PDIP package, QTP pattern #301.

b) PIC18LF24J10-I/SO = Industrial temp., SOIC

package.

c) PIC18LF44J10-I/P = Industrial temp., PDIP

package.

Note 1: T = in tape and reel TQFP

packages only.

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03/26/09