LTC3623 15V, 5A Rail-to-Rail Synchronous Buck Regulator Description Features Single Resistor Programmable VOUT: 0V to VIN - 0.5V nn Silent Switcher(R) Architecture nn I ISET Accuracy: 1% nn Tight V OUT Regulation Across VOUT Range nn Output Current Monitor Accuracy: 5% nn Programmable Wire Drop Compensation nn Easy to Parallel for Higher Current and Heat Spreading nn Input Supply Voltage Regulation Loop nn High Efficiency: Up to 96% nn Output Current: 5A nn Integrated N-MOSFETs (60m Top & 30m Bottom) nn Adjustable Switching Frequency: 400kHz to 4MHz nn V Range: 4V to 15V IN nn Current Mode Operation for Excellent Line and Load Transient Response nn Shutdown Mode Draws Less Than 1A Supply Current nn Low Profile 24-Lead 3mm x 5mm QFN Package nn Applications Tracking Supply or DDR Memory Supply ASIC Substrate Biasing nn Point-of-Load (POL) Power Supply nn Portable Instruments, Battery-Powered Equipment nn Thermo Electric Cooler (TEC) Systems nn nn The LTC(R)3623 is a high efficiency, monolithic synchronous buck regulator in which the output voltage is programmed with a single external resistor. The accurate internally generated 50A current source on the ISET pin allows the user to program an output voltage from 0V to 0.5V below VIN. The user can also directly drive the ISET pin with an external voltage supply to program the converter's VOUT. The VOUT voltage is fed directly back to the error amplifier to be regulated to the ISET voltage. The operating supply voltage range for the SVIN pin is from 15V down to 4V, while the PVIN pin's voltage range is 15V down to 1.5V, making it suitable for dual Li-Ion batteries and for taking power from a 12V or 5V rail. The operating frequency is programmable from 400kHz to 4MHz with an external RT resistor. Higher switching frequency allows the use of smaller surface mount inductors while lower frequency allows for higher power efficiency. The unique constant-frequency/controlled on-time architecture is ideal for high step-down ratio applications that are operating at high frequency while demanding fast transient response. L, LT, LTC, LTM, OPTI-LOOP, Silent Switcher, Linear Technology and the Linear logo are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5847554, 6580258. Typical Application SVIN 90 0.1F 22F ERROR AMP SW 80 1H VOUT 5V 5A 47F PGND VOUT 70 50 40 POWER LOSS 1.8 CCM 1.2 30 20 0 0.001 3623 TA01 2.4 DCM 60 10 PGOOD ITH PGFB INTVCC MODE/ SYNC IMON VIN_REG ISET IOUT/50k VIN = 12V VOUT = 5V POWER LOSS (W) PWM CONTROL AND SWITCH DRIVER EFFICIENCY (%) 50A 3.0 100 LTC3623EUD LOAD RUN Efficiency and Power Loss vs Load Current BOOST PVIN RT VIN (5.5V TO 15V) 0.6 CCM DCM 0.01 0.1 1 LOAD CURRENT (A) 10 0 3623 TA01a 100k 0.1F 1F 10k 10nF 3623fa For more information www.linear.com/LTC3623 1 LTC3623 Absolute Maximum Ratings Pin Configuration (Note 1) IMON VIN_REG RT TOP VIEW ITH PVIN, SVIN Voltage...................................... -0.3V to 17V VOUT, ISET Voltage..........................................-0.3 to VIN BOOST Voltage............................... SW -0.3V to SW+6V RUN Voltage.............................................. -0.3V to SVIN MODE/SYNC Voltage.................................... -0.3V to 6V ITH, RT, VIN_REG Voltage..................... -0.3V to INTVCC IMON, PGOOD, PGFB Voltage................ -0.3V to INTVCC GSNS Voltage..............................................-0.3V to 12V Operating Junction Temperature Range (Notes 4, 5).............................................. -40C to 125C 24 23 22 21 ISET 1 20 PGFB PGOOD 2 19 INTVCC RUN 3 18 BOOST GSNS 4 17 SVIN 25 PGND PVIN 5 16 PVIN SW 6 15 SW NC 7 14 NC MODE/SYNC 8 13 VOUT PGND PGND PGND PGND 9 10 11 12 UDD PACKAGE 24-LEAD (3mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 36C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB Order Information (http://www.linear.com/product/LTC3623#orderinfo) LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3623EUDD#PBF LTC3623EUDD#TRPBF LGMW 24-Lead (3mm x 5mm) Plastic QFN -40C to 125C LTC3623IUDD#PBF LTC3623IUDD#TRPBF LGMW 24-Lead (3mm x 5mm) Plastic QFN -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 3623fa For more information www.linear.com/LTC3623 LTC3623 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C. (Note 4) VIN = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SVIN Signal VIN Supply Range 4 15 V PVIN Power VIN Supply Range 1.5 15 V VOUT VOUT Range (Note 6) VIN = 15V 0 14.5 V IISET Reference Current 25C 25C to 130C -45C to 25C 50.5 50.5 51.5 A A A ISET ISET Dropout Voltage VIN - ISET ISET Line Regulation VIN = 5V to 15V l l 49.5 49 49.5 50 50 50 360 l -10 mV 10 nA/V ISET Load Regulation (Note 6) ILOAD = 0 to 5A 0.5 % VOUT Load Regulation ITH = 0.9V to 1.6V 0.05 % EA's Input Offset ISET = 3V -4.5 gm (EA) Error Amplifier Transconductance ITH = 1.2V 0.21 IQ Input DC Supply Current (Note 2) Shutdown Discontinuous RUN = 0 Mode = 0, RT = 33.2k 4.5 mV 0.28 0.35 mS 0 1.45 5 1.75 A mA ton(min) Minimum On Time (Note 6) 30 ns toff(min) Minimum Off Time (Note 6) 100 ns ILIM Current Limit RTOP Top Switch ON Resistance RBOTTOM Bottom Switch On Resistance VINTVCC Internal VCC Voltage 5.5V < VIN < 15V VUVLO INTVCC Undervoltage Lockout Threshold INTVCC Rising VRUN Run Threshold Run Hysteresis RUN Rising Run Leakage RUN = 15V INTVCC Load Regulation ILOAD = 0 to 20mA OV Output Overvoltage PGFB Upper Threshold PGFB Rising 0.585 0.63 UV Output Undervoltage PGFB Lower Threshold PGFB Falling 0.5 0.54 RPGOOD PGOOD Pull-Down Resistance fOSC Frequency RT = 33.2k RT = INTVCC MODE/SYNC Threshold MODE VIL(MAX) MODE VIH(MIN) SYNC VIH(MIN) SYNC VIL(MAX) MODE/SYNC = 5V l Negative Current Limit 5.2 6.2 7.4 -5 -6.5 -9 60 m 30 m 5 V 3.6 3.8 1.2 UVLO Hysteresis 4 V 1.45 0.34 1.67 V V 0 1 A 0.36 l % 0.67 15 PGFB UV Hysteresis 5mA Load mV 0.575 VIN_REG Input Voltage Regulation Reference (Note 6) 0.94 0.75 V 15 mV 1 l V 100 PGOOD Leakage MODE/SYNC Pin Current V 0.5 PGFB OV Hysteresis A 1 1 4.5 2.5 10 1.45 A 1.07 1.22 MHz MHz 0.4 V V V V A 0.4 V 3623fa For more information www.linear.com/LTC3623 3 LTC3623 Electrical Characteristics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C. (Note 4) VIN = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN VOUT Resistance to GND VINOV VIN Overvoltage Lockout VIN Rising 15.5 IMON Current Limit Threshold IMON Gain ILOAD = 5A, Not Switching Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 3: The LTC3623 is tested in a feedback loop that adjusts VOUT to achieve a specified error amplifier output voltage (ITH). Note 4: The LTC3623 is tested under pulsed load conditions such that TJ TA. The LTC3623E is guaranteed to meet performance specifications from 0C to 85C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3623I is guaranteed over the full -40C to 125C operating 4 MAX 600 VIN 0V Hystersis IIMON TYP UNITS k 16.8 V 1.4 V 2.15 2.35 2.55 20 21 22 V A/A junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (TJ, in C) is calculated from the ambient temperature (TA, in C) and power dissipation (PD, in watts) according to the formula: TJ = TA + (PD * JA), where JA (in C/W) is the package thermal impedance. Note 5: This IC includes overtemperature protection that is intended protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 6: Guaranteed by design. 3623fa For more information www.linear.com/LTC3623 LTC3623 Typical Performance Characteristics Load Regulation ISET Current vs. Temperature 50.0 49.5 0 VOUT VISET 99 49 98 97 95 45 VIN = 12V VOUT = 3.3V 0 1 2 3 LOAD CURRENT (A) 4 100 90 90 80 EFFICIENCY (%) EFFICIENCY (%) 60 CCM 50 40 30 20 8 10 VIN (V) 12 14 16 0.01 0.1 1 LOAD CURRENT (A) 3623 G04 10 3623 G03 40 30 fSW = 1MHz 0.01 0.1 1 LOAD CURRENT (A) 10 Shutdown Current vs VIN 1.0 4 VRUN = 0 0.8 0.7 3 IQ (A) CCM 2 30 0.6 0.5 0.4 0.3 20 0 0.001 16 CCM 50 0.9 40 10 60 Quiescent Current vs VIN DCM 14 3623 G06 5 IQ (mA) EFFICIENCY (%) 50 12 DCM 70 0 0.001 90 60 8 10 VISET (V) 3623 G05 100 70 6 10 fSW = 1MHz 0 0.001 Efficiency vs Load Current VOUT = 1.8V, VIN = 12V 80 4 20 10 VISET = 2.5V 6 2 80 DCM 70 49.9 4 0 Efficiency vs Load Current VOUT = 3.3V, VIN = 12V 100 50.1 IISET (A) 44 5 Efficiency vs Load Current VOUT = 5V, VIN = 12V 50.2 2 47 3623 G02 ISET Current Line Regulation 0 48 46 96 25 50 75 100 125 150 TEMPERATURE (C) 50.0 VIN = 16V 50 3623 G01 49.8 51 IISET (A) 50.5 IISET (A) ISET Current vs VISET 100 NORMALIZED VISET AND VOUT (%) 51.0 49.0 -50 -25 TA = 25C, unless otherwise noted. 1 fSW = 1MHz 0.01 0.1 1 LOAD CURRENT (A) 10 3623 G07 0.2 0.1 DCM 0 0 2 4 6 8 10 VIN (V) 12 14 16 3623 G08 0 0 2 4 6 8 10 VIN (V) 12 14 16 3623 G09 3623fa For more information www.linear.com/LTC3623 5 LTC3623 Typical Performance Characteristics RDS(ON) vs VIN 150 80 VOUT(AC) 200mV/DIV 120 MTOP RDS(ON) (m) RDS(ON) (m) Transient Response CCM Operation, External Compensation RDS(ON) vs Temperature 100 60 40 MBOT 20 0 TA = 25C, unless otherwise noted. 90 MTOP IL 5A/DIV 60 MBOT 30 0 3 6 9 VIN (V) 12 15 18 3623 G12 0 -50 -25 0 20s/DIV VIN = 12V fSW = 1MHz VOUT = 3.3V RITH = 20k, CITH = 470pF IOUT = 0A TO 4A MODE = INTVCC L = 1.2H COUT = 47F 25 50 75 100 125 150 TEMPERATURE (C) 3623 G10 3623 G11 Transient Response CCM Operation, Internal Compensation Transient Response DCM Operation, External Compensation Transient Response DCM Operation, Internal Compensation VOUT(AC) 200mV/DIV VOUT(AC) 200mV/DIV VOUT(AC) 200mV/DIV IL 5A/DIV IL 5A/DIV IL 5A/DIV 20s/DIV VIN = 12V fSW = 1MHz VOUT = 3.3V ITH = INTVCC IOUT = 0A TO 4A MODE = INTVCC L = 1.2H COUT = 47F 3623 G14 3623 G13 Output Tracking ISET VOLTAGE VOUT 2V/DIV IL 2A/DIV ISET VOLTAGE VOUT 1ms/DIV 6 3623 G16 20s/DIV VIN = 12V fSW = 1MHz VOUT = 3.3V RITH = 20k, CITH = 470pF IOUT = 0.5A TO 4A MODE = 0V L = 1.2H COUT = 47F 20s/DIV VIN = 12V fSW = 1MHz VOUT = 3.3V ITH = INTVCC IOUT = 0.5A TO 4A MODE = 0V L = 1.2H COUT = 47F Discontinuous Conduction Mode (DCM) Operation Continuous Conduction Mode (CCM) Operation VSW 10V/DIV VSW 10V/DIV IL 2A/DIV IL 2A/DIV VIN = 16V VOUT=2.5V MODE=0V L=1.0H 500ns/DIV 3623 G17 VIN = 16V VOUT=2.5V MODE=INTVCC L=1.0H 500ns/DIV 3623 G15 3623 G18 3623fa For more information www.linear.com/LTC3623 LTC3623 Typical Performance Characteristics Switching Frequency/Period vs RT Switch Leakage Current INTVCC Load Regulation 5.00 VIN = 15V 2.0 1.5 2 1.0 1 PERIOD (s) 3 4.95 90 60 MBOT MTOP 30 20 40 60 RT (k) 0 100 80 4.90 4.85 4.80 0.5 0 INTVCC VOLTAGE (V) TSW fSW LEAKAGE CURRENT (A) 2.5 4 FREQUENCY (MHz) 120 3.0 5 0 TA = 25C, unless otherwise noted. 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 4.75 0 20 40 60 80 LOAD CURRENT (mA) 3623 G20 3623 G19 Rising RUN Threshold vs Temperature 100 3623 G21 Start-up Waveform in CCM Start-up Waveform in DCM RUN THRESHOLD (V) 1.50 1.45 1.40 RUN 5V/DIV RUN 5V/DIV VOUT(DC) 2V/DIV VOUT(DC) 2V/DIV IL 2A/DIV IL 2A/DIV 1.35 1ms/DIV 1.30 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 3623 G23 1ms/DIV MODE = INTVCC NO PREBIASED VOUT VIN = 12V VOUT = 3.3V MODE = OV NO PREBIASED VOUT VIN = 12V VOUT = 3.3V Prebiased Start-up Waveform in DCM VIN Overvoltage 3623 G24 3623 G22 Prebiased Start-up Waveform in CCM RUN 5V/DIV RUN 5V/DIV VIN 5V/DIV VOUT(DC) 2V/DIV VOUT(DC) 2V/DIV VOUT 1V/DIV IL 2A/DIV IL 2A/DIV 1ms/DIV MODE = INTVCC VOUT IS PREBIASED TO 2V VIN = 12V VOUT = 3.3V 3623 G25 SW 10V/DIV 1ms/DIV 3623 G26 MODE = OV VOUT IS PREBIASED TO 2V VIN = 12V VOUT = 3.3V 20ms/DIV VIN = 12V TO 18V TO 12V VOUT = 3.3V IOUT = 1A MODE = CCM 3623 G27 3623fa For more information www.linear.com/LTC3623 7 LTC3623 Pin Functions ISET (Pin 1): Accurate 50A Current Source. Positive input to the error amplifier. Connect an external resistor from this pin to signal GND to program the VOUT voltage. Connecting an external capacitor from ISET to ground will soft start the output voltage and reduce current inrush at the input cap when turning on. VOUT can also be programmed by driving ISET directly with an accurate external voltage supply from 0 to VIN, in which case the external supply would be sinking this 50A. Do not drive ISET above VIN or below GND. PGOOD (Pin 2): Output Power Good with Open-Drain Logic. PGOOD is pulled to ground when the PGFB pin is more than 0.63V or less than 0.54V. If PGFB is tied to INTVCC, the open drain logic on PGOOD is disabled. PGOOD voltage is referred to GSNS. RUN (Pin 3): Run Control Input. Enables chip operation by tying RUN above 1.45V. Tying RUN below 1V shuts down switching regulator. Tying RUN below 0.4V shuts off the entire chip. RUN voltage is referred to GSNS. GSNS (Pin 4): System Ground SENSE. Ground reference for the RUN, PGOOD and MODE/SYNC pins. For positive VOUT applications, connect GSNS to PGND. For negative VOUT applications, connect GSNS to ground return of the system board. PVIN (Pins 5, 16): Power VIN. Input voltage connected to the drain of the top power NMOS. Must be decoupled to PGND with capacitor close to PVIN pin. PVIN operates down to 1.5V as long as SVIN > 4V. SW (Pins 6, 15): Switch Node Connection to External Inductor. Voltage swing of SW is from a diode voltage drop below ground to PVIN. MODE/SYNC (Pin 8): Operation Mode Select. Tie this pin to INTVCC to force continuous synchronous operation at all output loads. Tying it to GSNS enables discontinuous mode operation at light loads. Applying an external clock signal to this pin will synchronize switching frequency to the external clock. MODE/SYNC voltage is referred to GSNS. During external clock synchronization, RT value should be set up such that the free running frequency is within 30% of the external clock frequency. 8 PGND (Pins 9, 10, 11, 12, Exposed Pad Pin 25): Power Ground. Return path of Internal Power MOSFETs. Connect these pins to the negative terminals of the input and output capacitors. The exposed pad must be soldered to the PCB ground for electrical contact and rated thermal performance. VOUT (Pin 13): Output Voltage Pin. Negative input of the error amplifier which is driven to be the same voltage as ISET. SVIN (Pin 17): Signal VIN. Input voltage to power internal bias circuitry. SVIN must be above 4V. BOOST (Pin 18): Boosted Floating Driver Supply for Internal Top Power MOSFET. The (+) terminal of the bootstrap capacitor connects here. This pin swings from a diode voltage drop below INTVCC up to PVIN + INTVCC. INTVCC (Pin 19): Internal 5V Regulator Output. The internal power drivers and control circuits are powered from this voltage. Decouple this pin to PGND with a minimum of 1F low ESR ceramic capacitor. PGFB (Pin 20): Power Good Feedback. Place a resistor divider on VOUT to detect power good level. If PGFB is more than 0.63V or less than 0.54V, PGOOD will be pulled down. Tie PGFB to INTVCC to disable PGOOD function. Tying PGFB to a voltage between 0.67V and 4V will force continuous synchronous operation regardless of the MODE/SYNC state. IMON (Pin 21): Current Monitor Pin. There will be a current equal to 21A * IOUT coming out of the IMON pin. Place a resistor in parallel with a filtering capacitor (10nF) from IMON to GND to report IOUT. When the voltage on IMON is above 2.35V, IOUT will be limited. IMON can also be used to program VOUT to compensate for output voltage drop at the load due to wire resistance by injecting the IMON current into a portion of the ISET resistor. VIN_REG (Pin 22): Control Pin for VIN regulation. Tie this pin to INTVCC for buck converter operation where VOUT is regulated to ISET. Tie this pin to a resistor divider from VIN to GND to enable input voltage regulation. When VIN_REG drops below 1.45V, the system will reduce the inductor current to keep VIN from dropping. 3623fa For more information www.linear.com/LTC3623 LTC3623 Pin Functions RT (Pin 23): Switching Frequency Programming Pin. Connect an external resistor (between 100k to 10k) from RT to GND to program the frequency from 400kHz to 4MHz. Tying the RT pin to INTVCC programs 1MHz operation. Floating the RT pin shuts off the power switches. ITH (Pin 24): Error Amplifier Output and Switching Regulator Compensation Point. The internal current comparator's trip threshold is linearly proportional to this voltage, whose normal range is from 0.55V to 1.85V. For external compensation, tie a resistor (RITH) in series with a capacitor (CITH) to signal GND. A separate 10pF high frequency filtering cap can also be placed from ITH to signal GND. Tying ITH to INTVCC enables the default internal compensation and removes the need for external compensation components. 3623fa For more information www.linear.com/LTC3623 9 LTC3623 FUNCTIONAL Diagram 100k GND 2pF VON 200k 400k 0.2V 100pF 17 4V PVIN IION = OSC 19 18 R - TG ON Q SWITCH LOGIC AND ANTISHOOT-THROUGH + ICMP - 600k CB L1 6, 15 IREV VOUT SENSE+ COUT BG -6.7A TO 3.3A RT M1 SW ENABLE 4 GSNS CVCC BOOST 20k + RT 23 CIN INTVCC S 8 5, 16 0.0122 * VIN RT V tON = VON (1pF) IION V ! IN INTVCC VIN 5V REG VON BUFFER ION PLL-SYNC (30%) MODE/SYNC SVIN VOUT M2 IOUT 50k PGB SENSE- PGND 21 IMON 9-12, 25 PGOOD 2 6.7A 0A TO 10A VOUT 13 - - 1 180k + 0.63V RPG2 OV INTVCC PGFB + 50pF RPG1 - 100k 20 UV + VIN RUN gm RIN22 (OPT) 22 24 ITH 50A VIN VIN_REG RIN21 (OPT) - EA + + 1.45V 1 ISET - RITH - CITH 1.45V 0.54V SVIN + RIN12 (OPT) RUN 3 RIN11 (OPT) RISET 3623 FD 10 3623fa For more information www.linear.com/LTC3623 LTC3623 Operation Main Control Loop The LTC3623 is a current mode monolithic step down regulator. The accurate 50A current source on the ISET pin allows the user to use just one external resistor to program the output voltage in a unity gain buffer fashion. In normal operation, the internal top power MOSFET is turned on for a fixed interval determined by a fixed one-shot timer OST. When the top power MOSFET turns off, the bottom power MOSFET turns on until the current comparator ICMP trips, restarting the one shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage drop across the SW and PGND nodes of the bottom power MOSFET. The voltage on the ITH pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this ITH voltage by comparing the VOUT voltage with the voltage on ISET. If the load current increases, it causes a drop in the VOUT voltage relative to VISET. The ITH voltage then rises until the average inductor current matches that of the load current. At low load current, the inductor current can drop to zero and become negative. This is detected by current reversal comparator IREV, which then shuts off the bottom power MOSFET, resulting in discontinuous operation. Both power MOSFETs will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level to initiate another cycle. Discontinuous mode operation is disabled by tying the MODE pin to INTVCC, which forces continuous synchronous operation regardless of output load. The operating frequency is determined by the value of the RT resistor, which programs the current for the internal oscillator as well as the current for the internal one-shot timer. An internal phase-lock loop servos the switching regulator on-time to track the internal oscillator to force constant switching frequency. If an external synchronization clock is present on the MODE/SYNC pin, the regulator on-time and switching frequency would then track the external clock. Overvoltage and under-voltage comparators OV and UV pull the PGOOD output low if the output power-good feedback voltage VPGFB exits a 7.5% window around the regulation point. Continuous operation is forced during an OV condition. To defeat the PGOOD function, simply tie PGFB to INTVCC. Pulling the RUN pin to ground forces the LTC3623 into its shutdown state, turning off both power MOSFETs as well as all of its internal control circuitry. Bringing the RUN pin above 0.7V turns on the internal reference only, while still keeping the power MOSFETs off. Further increasing the RUN voltage above 1.45V turns on the entire chip. INTVCC Regulator An internal low drop out (LDO) regulator produces the 5V supply that powers the drivers and the internal bias circuitry. The INTVCC can supply up to 50mA RMS and must be bypassed to ground with a minimum of 1F ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the power MOSFET gate drivers. Applications with high input voltage and high switching frequency will increase die temperature because of the higher power dissipation across the LDO. Connecting a load to the INTVCC pin is not recommended since it will further push the LDO into its RMS current rating while increasing power dissipation and die temperature. VIN Overvoltage Protection In order to protect the internal power MOSFET devices against transient voltage spikes, the LTC3623 constantly monitors the VIN pin for an overvoltage condition. When VIN rises above 16.8V, the regulator suspends operation by shutting off both power MOSFETs and discharges the ISET pin voltage to ground. Once VIN drops below 15.4V, the regulator immediately resumes normal switching operation by first charging up the ISET pin to its programmed voltage. Programming Switching Frequency Connecting a resistor from the RT pin to GND programs the switching frequency from 400kHz to 4MHz according to the following formula: 3.32 *1010 Frequency(Hz)= RT For ease of use, the RT pin can be connected directly to the INTVCC pin for 1MHz operation. The internal on-time phase lock loop has a synchronization range of 30% around its programmed frequency. Therefore, during external clock synchronization, the proper RT value should For more information www.linear.com/LTC3623 3623fa 11 LTC3623 Operation be selected such that the external clock frequency is within this 30% range of the RT programmed frequency. MODE/SYNC Operation The MODE/SYNC pin is a multipurpose pin allowing both mode selection and operating frequency synchronization. Connecting it to ground enables Discontinuous Mode operation for superior efficiency at low load currents at the expense of slightly higher output voltage ripple. When the MODE/SYNC pin is tied to INTVCC, forced continuous mode operation is selected, creating the lowest fixed output ripple at the expense of lower light load efficiency. The LTC3623 will detect the presence of an external clock signal on the MODE/SYNC pin and synchronize the switching frequency to that of the incoming clock. The presence of an external clock will place the part into forced continuous mode operation. Current Monitor and Programmable Output Current Limit The LTC3623 provides a 21A scaled replica of the average output current at the IMON pin. Placing an external resistor at the IMON pin will generate a corresponding IMON voltage reflecting that of the output current. An internal current limit amplifier with a threshold of 2.35V is placed on the IMON pin, allowing the user to use an appropriately valued resistor to program the output current limit: RLIM = 2.35V 21A *ILIM Output Cable Drop Compensation For applications where the actual load is far away from the output of the LTC3623 converter and the resistance of the connecting cable is affecting the output regulation voltage at the load, the user can compensate for such cable drop voltage by placing an additional resistor between IMON and ISET. This resistor's value should be (1/21) times that of the measured cable resistance. RISET2 = 2*RCABLE / 21A VOUT =IISET *(RISET1 +RISET2 ) VOUT,COMP =IISET *RISET1 +(IISET +IIMON )*RISET2 L SW LTC3623 ISET VOUT,COMP VOUT RCABLE COUT R CABLE IMON PGND VOUT ILOAD RISET1 CISET 10nF RISET2 3623 F01 Figure 1. Output Cable Drop Compensation If there's an equivalent cable resistance for the ground return between the load and the converter, then the resistor's value should be doubled. As a result, the ISET programming reference voltage would increase as the load current increase, compensating for the VOUT cable drop at the load. Output Voltage Tracking and Soft Start where ILIM is the programmable output current limit. For instance, placing a 50k resistor between IMON and ground would program an approximate 2.2A output current limit. When the programmable current limit feature is used, a compensation capacitor (10nF typical) should be placed in parallel with the chosen resistor. To disable output current monitor or remove output current programmability, connect IMON to ground. The LTC3623 allows the user to program its output voltage ramp rate by means of the ISET pin. Since VOUT servos its voltage to that of the ISET pin, placing an external capacitor CISET on the ISET pin will program the ramp-up rate of the ISET pin and thus the VOUT voltage: -t (RISET *CISET ) VOUT (t)=IISET *RISET 1-e From 0 to 90% of VOUT t SS = -RISET *CISET *ln(1-0.9) 12 t SS = 2.3 *RISET *CISET For more information www.linear.com/LTC3623 3623fa LTC3623 Operation The soft-start time tss (from 0% to 90% VOUT) is 2.3 times of time constant (RISET * CISET). The ISET pin can also be driven by an external Voltage supply capable of sinking the provided 50A. When starting up into a pre-biased VOUT, the LTC3623 will stay in discontinuous mode and keep the power switches off until the voltage on ISET has ramped up to be equal to VOUT, at which point the switcher will begin switching and VOUT will ramp up with ISET. Input Voltage Regulation Loop for Backup Power Supply The input voltage regulation loop circuit is used to hold up and regulate the input voltage for backup power supply applications when the input supply is removed or is very resistive. An external resistor divider from VIN can be used to sense the VIN voltage and feeds into the VIN_REG pin of the LTC3623. When the voltage on the VIN_REG pin is less than 1.45V, the part will dynamically reduce the inductor current to prevent the input voltage from drooping below the 1.45V threshold. If the VIN voltage and the VIN_REG pin voltage continues to fall, charge will be transferred from the VOUT capacitor to the VIN capacitor in order to hold up the VIN voltage. Duration of the holdup will depend on the amount of charge stored in the output capacitor. Activation and termination of the input voltage regulation loop can also be set using a separate resistor divider from VIN to drive the RUN pin, which has a rising threshold of 1.45V to enable the chip, and a falling threshold of 1.1V to disable the chip. If the VIN voltage regulation feature is not used, connect the VIN_REG pin to INTVCC. R +R VINholdup = DIR1 DIR2 *1.45V RDIR1 RRUN1 50K RUN RDIR2 10K RRUN2 10K When the LTC3623's output voltage is within the 7.5% window of the regulation point, which is reflected back as a VPGFB voltage in the range of 0.54V to 0.63V, the output voltage is in regulation and the PGOOD pin is pulled high with an external resistor. Otherwise, an internal open-drain pull down device (100) will pull the PGOOD pin low. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTC3623's PGOOD falling edge includes a blanking delay of approximately 20sec. Internal/External ITH Compensation For ease of use, the user can simplify the loop compensation by tying the ITH pin to INTVCC to enable internal compensation. This connects an internal 100k resistor in series with a 50pF cap to the output of the error amplifier (internal ITH compensation point). This is a trade-off for simplicity instead of OPTI-LOOP(R) optimization, where ITH components are external and are selected to optimize the loop transient response with minimum output capacitance. Minimum Off-Time Considerations The minimum off-time tOFF(min) is the smallest amount of time that the LTC3623 is capable of turning on the bottom power MOSFET, tripping the current comparator and turning the power MOSFET back off. This time is generally about 100ns. The minimum off-time limit imposes a maximum duty cycle of ton/(tON+tOFF(min)). If the maximum duty cycle is reached, due to the input voltage dropping, for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: ( tON + tOFF(MIN) VIN(MIN) = VOUT * tON VIN RDIR1 45K Output Power Good ) Conversely, the minimum on-time is the smallest duration of time in which the top power MOSFET can be in its "on" state. This time is typically 30ns. In continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: PVIN/SVIN LTC3623 VIN_REG PGND DCMIN = f * tON(MIN) 3623 F02 Figure 2. Input Voltage Regulation Where tON(MIN) is the minimum on-time. As the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. 3623fa For more information www.linear.com/LTC3623 13 LTC3623 Operation In the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value. This is an acceptable result in many applications, so this constraint may not be of critical importance in most cases. High switching frequencies may be used in the design without any fear of severe consequences. As the sections on inductor and capacitor selection show, high switching frequencies allow the use of smaller board components, thus reducing the size of the application circuit. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal wave current at the drain of the top power MOSFET. To prevent large voltage transients from occurring, a low ESR input capacitor sized for the maximum RMS current should be used. The maximum RMS current is given by: 1/2 VOUT VIN IRMS =IOUT(MAX) -1 VIN VOUT Using Ceramic Input and Output Capacitors This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further de-rate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response. The output ripple, VOUT, is determined by: 1 VOUT < IL +RESR 8 * fSW *COUT 14 The output ripple is highest at maximum input voltage since IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. Special polymer capacitors are very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics and small footprints. Their relatively low value of bulk capacitance may require multiples in parallel. Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the VIN input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R and X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. Typically, 3 to 4 cycles 3623fa For more information www.linear.com/LTC3623 LTC3623 Operation are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 2 to 3 times the linear drop of the first cycle. Thus, a good place to start with the output capacitor value is approximately: I OUT COUT ~ 2.5 * f SW * VDROOP More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 22F ceramic capacitor is usually enough for these conditions. Place this input capacitor as close to VIN pin as possible. Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: V V IL = OUT 1- OUT VIN fSW *L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a trade-off between component size, efficiency, and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: V VOUT 1- OUT L = fSW * IL(MAX) VIN(MAX) Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard", which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Toko, Vishay, NEC/Tokin, Cooper, TDK, and Wurth Elektronik. Refer to Table 1 for more details Checking Transient Response The OPTI-LOOP compensation allows the transient response to be optimized for a wide range of loads and output capacitors. The availability of the ITH pin not only allows optimization of the control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The ITH external components shown in Figure 5 circuit will provide an adequate starting point for most applications. The series R-C filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because their 3623fa For more information www.linear.com/LTC3623 15 LTC3623 Operation Table 1. Inductor Selection Table INDUCTANCE DCR MAX CURRENT DIMENSIONS HEIGHT 6.7mm x 7mm 3mm Vishay IHLP-2525CZ-01 Series 0.33H 4.1mW 18A 0.47H 6.5mW 13.5A 0.68H 9.4mW 11A 0.82H 11.8mW 10A 1.0H 14.2mW 9A Vishay IHLP-1616BZ-11 Series 0.22H 4.1mW 12A 0.47H 15mW 7A 4.3mm x 4.7mm 2.0mm 7mm x 7.7mm 2.0mm Toko FDV0620 Series 0.20H 4.5mW 12.4A 0.47H 8.3mW 9A 1H 18.3mW 5.7A NEC/Tokin MLC0730L Series 0.47H 4.5mW 16.6A 0.75H 7.5mW 12.2A 1H 9mW 10.6A 6.9mm x 7.7mm 3.0mm 7mm x 7.3mm 3.0mm 6.9mm x 7.3mm 3.2mm 7mm x 7.7mm 3.8mm Cooper HCP0703 Series 0.22H 2.8mW 23A 0.47H 4.2mW 17A 0.68H 5.5mW 15A 0.82H 8mW 13A 1H 10mW 11A 1.5H 14mW 9A TDK RLF7030 Series 1H 8.8mW 6.4A 1.5H 9.6mW 6.1A 2.2H 12mW 5.4A Wurth Elektronik WE-HC 744312 Series 0.25H 2.5mW 18A 0.47H 3.4mW 16A 0.72H 7.5mW 12A 1H 9.5mW 11A 1.5H 10.5mW 9A 16 various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD * ESR, where ESR is the effective series resistance of C OUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with the R and the bandwidth of the loop increases with decreasing C. If R is increased by the same factor that C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, a feed forward capacitor CFF can be added to improve the high frequency response, as shown in Figure 1. Capacitor CFF provides phase lead by creating a high frequency zero with R2 which improves the phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76. In some applications, a more severe transient can be caused by switching in loads with large (>10F) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load 3623fa For more information www.linear.com/LTC3623 LTC3623 Operation switch driver. A Hot Swap controller is designed specifically for this purpose and usually incorporates current limit, short-circuit protection, and soft-start. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100%-(L1 + L2 + L3 +...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3623 circuits: 1) I2R losses, 2) Transition losses, 3) switching losses, 4) other losses. 1. I2R losses are calculated from the DC resistances of the internal switches, RSW, the external inductor, RL, and board trace resistance, Rb. In continuous mode, the average output current flows through inductor L but is "chopped" between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = RDS(ON)(TOP)(DC) + RDS(ON)(BOT)(1-DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R losses: I2R losses = IOUT2(RSW + RL + Rb) 2. Transition loss arises from the brief amount of time the top power MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, internal power MOSFET gate capacitance, internal driver strength, and switching frequency. 3. The INTVCC current is the sum of the power MOSFET driver and control currents. The power MOSFET driver current results from switching the gate capacitance of the power MOSFETs, Each time a power MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the DC control bias current. In continuous mode, IGATECHG = fSW(QT + QB), where QT and QB are the gate charges of the internal top and bottom power MOSFETs and fSW is the switching frequency. Since INTVCC is a low drop out regulator output powered by VIN, the INTVCC current also shows up as VIN current, unless a separate voltage supply (>5V and <6V) is used to drive INTVCC. 4. Other "hidden" losses such as copper trace and internal load resistances can account for additional efficiency degradations in the overall power system. It is very important to include these "system" level losses in the design of a system. Other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In a majority of applications, the LTC3623 does not dissipate much heat due to its high efficiency and low thermal resistance of its exposed-back DFN or MSOP package. However, in applications where the LTC3623 is running at high ambient temperature, high VIN, high switching frequency, and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 160C, both power switches will be turned off until temperature is about 15C cooler. To avoid the LTC3623 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD * JA 3623fa For more information www.linear.com/LTC3623 17 LTC3623 Operation As an example, consider the case when the LTC3623 is used in application where VIN = 12V, IOUT = 5A, f = 1MHz, VOUT = 1.8V. The equivalent power MOSFET resistance RSW is RSW =RDS(ON)TOP * 1.8 12+RDS(ON)BOT * 10.2 12 1.8 10.2 = 0.06 * +0.03 12 12 = 0.0345 The VIN current during 1MHz force continuous operation with no load is about 6mA, which includes switching and internal biasing current loss, transition loss, inductor core loss, and other losses in the application. Therefore, the total power dissipated by the part is: PD = IOUT2 * RSW + VIN * IVIN(No Load) = 25A2 * 0.0345 + 12V * 6mA = 0.93W The QFN 5mm x 3mm package junction-to-ambient thermal resistance, JA, is around 36C/W. Therefore, the junction temperature of the regulator operating in a 25C ambient temperature is approximately: TJ = 0.93 * 36 + 25 = 59C Remembering that the above junction temperature is obtained from an RDS(ON) at 25C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. Redoing the calculation assuming that RSW increased 25% at 59C yields a new junction temperature of 70C, which is still very far away from thermal shutdown or maximum allowed junction temperature rating. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3623. Check the following in your layout: 1. Do the capacitors CIN connect to the power VIN and power GND as close as possible? These capacitors provide the AC current to the internal power MOSFETs and their drivers. 18 2. Are COUT and L1 closely connected? The (-) plate of COUT returns current to PGND and the (-) plate of CIN. 3. The ground terminal of ISET resistor must be connected to other quiet signal GND and together connects to the power GND at only one point. The ISET resistor should be placed and routed away from noisy components and traces, such as the SW line, and its trace should be minimized. 4. Keep sensitive components away from the SW pin. The ISET resistor, RT resistor, the compensation capacitor CC and CITH and all the resistors R1, R3, and RC, and the INTVCC bypass capacitor, should be routed away from the SW trace and the inductor L1. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the signal GND at one point which is then connected to the power GND at the exposed back with minimal resistance. Flood all unused areas on all layers with copper, which reduces the temperature rise of power components. These copper areas should be connected to one of the input supplies: VIN or GND. Design Example As a design example, consider using the LTC3623 in an application with the following specifications: VIN = 10.8V to 13.2V, VOUT = 1.8V, IOUT(MAX) = 5A, IOUT(MIN) = 500mA, fSW = 2MHz Because efficiency is important at both high and low load currents, discontinuous mode operation will be utilized. First select from the characteristic curves the correct RT resistor value for 2MHz switching frequency. Based on that RT should be 16.5k. Then calculate the inductor value for about 40% ripple current at maximum VIN: 1.8V 1.8V L = 1- = 0.39H 2MHz * 2A 13.2V The nearest standard value inductor would be 0.33H. 3623fa For more information www.linear.com/LTC3623 LTC3623 Operation COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. For this design, one 47F ceramic capacitor will be used. CIN should be sized for a maximum current rating of: 1.8V 13.2V IRMS = 5A -1 13.2V 1.8V 1/2 = 1.7A Decoupling the VIN pin with one 22F ceramic capacitor is adequate for most applications. 3623 F04 3623 F03 Figure 3. PCB Layout - Top Side Figure 4. PCB Layout 3623fa For more information www.linear.com/LTC3623 19 LTC3623 Typical Applications Figure 5. 12V to 1.2V 1MHz Buck Regulator with Differential Remote Sense VIN 12V 22F x2 1 0.1F SVIN PVIN BOOST LTC3623 RUN 0.1F VIN_REG 50A ERROR AMP MODE/SYNC 100k PWM CONTROL AND SWITCH DRIVER PGOOD 1H SW 47F PGND GSNS VOUT RT INTVCC ISET IMON ITH 33.2k 24.3k 0.1F 10k 10k 10nF 10k REMOTE SENSE GROUND AT OUTPUT LOAD PGFB 10pF 4.7F VOUT 1.2V 5A 10k 470pF 3623 F05 Figure 6. 12V to 2.5V 1MHz Buck Regulator with Cable Drop Compensation VIN 12V 22F x2 1 0.1F SVIN PVIN BOOST LTC3623 RUN VIN_REG 0.1F 50A PWM CONTROL AND SWITCH DRIVER ERROR AMP MODE/SYNC PGOOD SW 2.2H RCABLE 50m 47F VOUT 2.5V/5A 5A LOAD PGND GSNS VOUT INTVCC RT PGFB ISET IMON ITH 45.2k 4.7F 0.1F 4.99k RCABLE 50m 10pF 10nF 10k 470pF 3623 F06 20 3623fa For more information www.linear.com/LTC3623 LTC3623 Typical Applications Figure 7. 12V to 3.3V 1MHz Buck Regulator with Input Supply Regulation Loop VIN 12V 22F x2 1 0.1F RDIR1 45.2k RRUN1 49.9k SVIN PVIN RUN RRUN2 10k 0.1F 50A VIN_REG RDIR2 10k BOOST LTC3623 ERROR AMP MODE/SYNC PGOOD PWM CONTROL AND SWITCH DRIVER 3.3H SW COUT 4700F PGND GSNS VOUT 3.3V/5A VOUT INTVCC RT PGFB ISET IMON ITH 10pF 4.7F 66.5k 0.1F 10k 470pF 3623 F07 Input Voltage Hold Up SW VIN IL VOUT 3623 F07a 3623fa For more information www.linear.com/LTC3623 21 LTC3623 Typical Applications Figure 8. 12V to 10A 2-Phase Single Output Regulator VIN 12V 22F x2 1 0.1F SVIN PVIN BOOST LTC3623 RUN VIN_REG 0.1F 50A PWM CONTROL AND SWITCH DRIVER ERROR AMP MODE/SYNC PGOOD 1H SW 47F PGND GSNS VOUT INTVCC RT PGFB ISET 4.7F IMON ITH 10k 10k 10pF 10nF VOUT 3.3V 10A 470pF VIN 12V 22F x2 1 0.1F SVIN PVIN BOOST LTC3623 RUN VIN_REG 0.1F 50A PWM CONTROL AND SWITCH DRIVER LTC3623 ERROR AMP MODE/SYNC PGOOD 1H SW 47F PGND GSNS VOUT INTVCC RT PGFB ISET IMON ITH 4.7F 33.2k V+ OUT2 OUT1 MOD LTC6908-1* GND 0.1F 10k 10nF 10pF INTVCC 100k SET *EXTERNAL CLOCK FOR FREQUENCY SYNCHRONIZATION IS RECOMMENDED 22 3623 F08 3623fa For more information www.linear.com/LTC3623 LTC3623 Typical Applications Figure 9. Programmable 5A Current Source IOUT VIN 22F x2 1 0.1F 5A SVIN PVIN BOOST LTC3623 RUN 50A VIN_REG 0.1F PWM CONTROL AND SWITCH DRIVER ERROR AMP MODE/SYNC PGOOD 1H SW 0.5 0.1 IOUT 0A TO 5A 47F PGND GSNS VSHUNT 0 VOUT INTVCC RT ISET PGFB IMON ITH 10pF 4.7F 10k 10k 470pF LTC2054 VSHUNT 3623 F09 + - 0 TO 0.5V + - BSC019N02KS 10k Figure 10. 12V to -1V, 1MHz Buck Regulator VIN 12V 22F x2 1 0.1F SVIN PVIN LTC3623 BOOST RUN 5V 0V 0V 5V 0.1F 50A MODE/SYNC ERROR AMP VIN_REG PGOOD PWM CONTROL AND SWITCH DRIVER 1H SW COUT 47F PGND GSNS VOUT -1V VOUT INTVCC RT PGFB ISET IMON ITH 10pF 4.7F 20k 0.1F 10k 470pF 3623 F10 3623fa For more information www.linear.com/LTC3623 23 LTC3623 Typical Applications Figure 11. LED Driver with Programmable Control IOUT VIN 22F x2 1 0.1F 3A SVIN PVIN LTC3623 BOOST RUN VIN_REG SW 50A 0.1F ERROR AMP MODE/SYNC PGOOD PWM CONTROL AND SWITCH DRIVER 1H PGFB ISET + - ITH 10k LTC2054 + - IMON 10pF 4.7F VSHUNT IOUT 0A TO 3A VOUT INTVCC RT 0V TO 0.3V 0.3 0.1 22F PGND GSNS VSHUNT 0 BSC019N02KS 5.23k 1nF 3623 F11 10k 24 3623fa For more information www.linear.com/LTC3623 LTC3623 Typical Applications Figure 12. High Efficiency 12V Audio Driver VIN 12V 22F x2 1 0.1F SVIN PVIN LTC3623 BOOST 10F RUN 50A VIN_REG 0.1F ERROR AMP MODE/SYNC PGOOD PWM CONTROL AND SWITCH DRIVER 4.7H SW 4.7F PGND GSNS 8 SPEAKER 10F VOUT INTVCC RT PGFB ISET IMON ITH 10nF 3.01k 4.7F AUDIO SIGNAL 121k 220pF 3623 F12 3623fa For more information www.linear.com/LTC3623 25 VIN 22F x2 0.1F 26 For more information www.linear.com/LTC3623 4.7F ISET 0.1F PVIN 50A INTVCC RT PGFB GSNS PGOOD MODE/SYNC VIN_REG RUN SVIN 1 0 to 121k 12.1k ERROR AMP LTC3623 10pF ITH PWM CONTROL AND SWITCH DRIVER SW VOUT PGND IMON 470pF 10k BOOST 10F 2.2H LDO OUTPUT + 0.6V 0.1F Figure 13. Low Noise Step Down Regulator IN 3623 F13 SET 0.1F LT3083 VCONTROL 10F 909* *OPTIONAL FOR MINIMUM 1mA LOAD REQUIREMENT OUT LDO OUTPUT 0V TO 12V IMAX = 3A LTC3623 Typical Applications 3623fa LTC3623 Typical Applications Figure 14. Regulate Positive or Negative Current Across a Peltier Device VIN 9V TO 15V 22F x2 1 0.1F SVIN PVIN LTC3623 BOOST RUN 0.1F 50A VIN_REG ERROR AMP MODE/SYNC PGOOD PWM CONTROL AND SWITCH DRIVER 1H SW VOUT 2V TO 8V 100F PGND GSNS VOUT INTVCC RT PGFB 4.7F IMON ISET 40k TO 160k ITH 10pF 10k 0.1F 470pF 100F 22F x2 PELTIER 3V/3A 1 0.1F SVIN PVIN LTC3623 BOOST RUN 0.1F 50A VIN_REG ERROR AMP MODE/SYNC PGOOD PWM CONTROL AND SWITCH DRIVER 1H SW FIXED 5V 100F PGND GSNS VOUT INTVCC RT PGFB ISET IMON ITH 10pF 4.7F 100k 0.1F 10k 470pF 3623 F14 3623fa For more information www.linear.com/LTC3623 27 LTC3623 Package Description Please refer to http://www.linear.com/product/LTC3623#packaging for the most recent package drawings. UDD Package 24-Lead Plastic QFN (3mm x 5mm) (Reference LTC DWG # 05-08-1833 Rev O) 0.70 0.05 3.50 0.05 2.10 0.05 3.65 0.05 1.50 REF 1.65 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 3.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 0.10 0.75 0.05 1.50 REF 23 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.25 x 45 CHAMFER 24 0.40 0.10 PIN 1 TOP MARK (NOTE 6) 5.00 0.10 1 2 3.65 0.10 3.50 REF 1.65 0.10 (UDD24) QFN 0808 REV O 0.200 REF 0.00 - 0.05 R = 0.115 TYP 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 28 3623fa For more information www.linear.com/LTC3623 LTC3623 Revision History REV DATE DESCRIPTION A 07/17 Modified Typical Application Circuit PAGE NUMBER Changed ISET to IISET 1 3, 5 Changed MODE/SYNC GND to GNDS 8 Added Figure 14 27 3623fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC3623 29 LTC3623 Typical Application Figure 15. High Efficiency 5A VTT Supply for DDR Termination VIN 5V 22F x2 0.1F PVIN SVIN LTC3623 VDD 2.5V 0.1F BOOST RUN 50A VIN_REG ERROR AMP MODE/SYNC PGOOD PWM CONTROL AND SWITCH DRIVER 1H SW VTT 1.25V 5A 47F PGND GSNS VOUT INTVCC RT PGFB IMON ISET ITH 10pF 4.7F 24.9k 0.1F 10k 470pF 3623 F15 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC3600 15V, 1.5A (IOUT), Synchronized Rail-to-Rail Step-Down DC/DC Converter 96% Efficiency, VIN: 4V to 15V, VOUT(MIN) = 0V, IQ = 700A, 3mm x 3mm DFN-12 and MSOP-12E Packages LTC3601 15V, 1.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 300A, ISD < 1A, 4mm x 4mm QFN-20 and MSOP-16E Packages LTC3603 15V, 2.5A (IOUT), 3MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 75A, ISD < 1A, 4mm x 4mm QFN-20 and MSOP-16E Packages LTC3633/ LTC3633A 15V/20V, Dual 3A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 3.6V to 15V/20V, VOUT(MIN) = 0.6V, IQ = 500A, ISD < 15A, 4mm x 5mm QFN-28 and TSSOP-28E Packages LTC3605/ LTC3605A 15V/20V, 5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4V to 15V/20V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15A, 4mm x 4mm QFN-24 and MSOP-16E Packages LTC3604 15V, 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 3.6V to 15V, VOUT(MIN) = 0.6V, IQ = 300A, ISD < 14A, 3mm x 3mm QFN-16 and MSOP-16E Packages LT3080 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2 Supply Operation), Low Noise = 40VRMS VIN: 1.2V to 36V, VOUT: 0V to 35.7V, MSOP-8, 3mm x 3mm DFN Packages LT3083 Adjustable 3A Single Resistor Low Dropout Regulator 310mV Dropout Voltage, Low Noise 40VRMS VIN: 1.2V to 23V, VOUT: 0V to 22.7V, 4mm x 4mm DFN, TSSOP-16E Packages LTC7149 60V, 4A Synchronous Step-Down Regulator for Inverting Inputs Wide VIN Range: 3.4V to 60V; Wide VOUT Range: 0V to 28V; Single Resistor VOUT Programming; 92% Efficiency with 12VIN and -5VOUT; Regulated IQ: 440A, Shutdown IQ: 15A; 28-Lead (4mm x 5mm) QFN and TSSOP Packages LTC3649 60V, 4A Synchronous Step-Down Regulator with Rail-to-Rail Programmable Output Wide VIN Range: 3.1V to 60V; Wide VOUT Range: 0V to (VIN - 0.5V); Single Resistor VOUT Programming; 95% Efficiency with 12VIN and 5VOUT; Regulated IQ: 440A, Shutdown IQ: 15A; 28-Lead (4mm x 5mm) QFN and TSSOP Packages 30 3623fa LT 0716 REV A * PRINTED IN USA www.linear.com/LTC3623 For more information www.linear.com/LTC3623 LINEAR TECHNOLOGY CORPORATION 2016