ky, SGS-THOMSON 4 wicrosuecrromcs 28440 28441-28442 Z80 SIO SERIAL INPUT/OUTPUT CONTROLLER ws TWO INDEPENDENT FULL-DUPLEX CHAN- NELS, WITH SEPARATE CONTROL AND STATUS LINES FOR MODEMS OR OTHER DEVICES = DATA RATES OF 0 TO 500K BITS/SECOND IN THE XL CLOCK MODE WITH A 2.5MHz CLOCK (28440), OR 0 TO 800K BITS/SECOND WITH A 4.0MHz CLOCK (Z8440A) ASYNCHRONOUS PROTOCOLS : EVERY- THING NECESSARY FOR COMPLETE MESS- AGES IN 5, 6, 7 OR 8 BITS/CHARACTER. INCLUDES VARIABLE STOP BITS AND SEV- ERAL CLOCK-RATE MULTIPLIERS ; BREAK GENERATION AND DETECTION ; PARITY ; OVERRUN AND FRAMING ERROR DETEC- TION a SYNCHRONOUS PROTOCOLS : EVERYTHING NECESSARY FOR COMPLETE BIT- OR BYTE- ORIENTED MESSAGES IN 5, 6, 7 OR 8 BITS/CHARACTER, INCLUDING IBM BISYNC, SDLC, HDLC, CCITT-X.25 AND OTHERS. AUTOMATIC CRC GENERATION/CHECKING SYNC CHARACTER AND ZERO INSER- TION/DELETION, ABORT GENERATION/DE- TECTION AND FLAG INSERTION RECEIVER DATA REGISTERS QUADRUPLY BUFFERED, TRANSMITTER REGISTERS DOUBLY BUFFERED e HIGHLY SOPHISTICATED AND FLEXIBLE DAISY-CHAIN INTERRUPT VECTORING FOR INTERRUPTS WITHOUT EXTERNAL LOGIC DESCRIPTION The Z80 SIO Serial Input/Output Controller is a dual- channel data communication interface with extraor- dinary versatility and capability. Its basic functions as a serial-to-parallel, parallel-to-serial conver- ter/controlier can be programmed by a CPU for a broad range of serial communication applications. The device supports all common asynchronous and synchronous protocols, byte- or bit-oriented and performs all of the functions traditionally done by UARTs, USARTs and synchronous communication controllers combined, plus additional functions tradi- tionally performed by the CPU. Moreover, it does this on two fully-independent channels, with an ex- September 1988 BIF D DiP-40 (Plastic and Frit-Seal} DIP-40 (Ceramic) Cc PLCOC44 (Plastic) (Ordering Information at the end of the datasheet) ceptionally sophisticated interrupt structure that allows very fast transfers. Full interfacing is provided for CPU or DMA control. In addition to data communication, the circuit can handle virtually all types of serial 1/O with fast (or slow) peripheral devices. While designed primarily as a member of the Z80 family, its versatility makes it well suited to many other CPUs. The Z80 SIO is an n-channel silicon-gate depletion- load device and uses a single + 5V power supply and the standard Z80 Family single-phase clock. 1/20 20528440-28441-Z8442 PIN DESCRIPTIONS Figures 1 through 6 illustrate the three pin configu- rations (bonding options) available in the SIO. The constraints of a 40-pin package make it impossible to bring_out the Receive Clock (RxC), Transmitt Clock (TxC), Data Terminal Ready (DTR) and Syne (SYNC) signals for both channels. Therefore, either Channel B lacks a signal or two signals are bonded together in the three bonding options offered : a 280 SIO-2 lacks SYNCB = 280 SIO-1 lacks DTRB = 280 SIO-0 as a four signal, but TxCB and RxCB are bonded together The first bonding option above (SIO-2) is the preferred version for most applications. The Chip- Carrier package version, having a 44-pin facility, re- sume the three bonding option configurations. It is named 28444 (figure 7). The pin description are as follows : B/A. Channel A Or B Select (Input, High selects Channel B). This input defines which channel is ac- cessed during a data transfer between the CPU and the SIO. Address bit Ao from the CPU is often used for the selection function. C/D. Contro! Or Data Select (input, High selects Control). This input defines the type of information transfer performed between the CPU and the SIO. A High at this input during a CPU write to the SIO Figure 1 : Z80 SIO-2 Logic Function. causes the information on the data bus to be inter- preted as a command for the channel selected by B/A. A Low at C/D means that the information on the data bus is data. Address bit Aj is often used for this function. C/E. Chip Enable (Input, Active Low). A Low level at this input enables the SIO to accept command or data input from the CPU during a write cycle or to transmit data to the CPU during a read cycle. CLK. System Clock (Input). The SIO uses the stand- ard Z80 System Clock to synchronize internal sig- nals. This is a single-phase clock. CTSA, CTSB. Clear To Send (Inputs, Active Low). When programmed as Auto Enables, a Low on these inputs enables the respective transmitter. If not programmed as Auto Enables, these inputs may be programmed as general-purpose inputs. Both in- puts are Schmitt-trigger buffered to accomodate slow-risetime signals. The SIO detects pulses on these inputs and interrupts the CPU on both logic level transitions. The Schmitt-trigger buffering does not guarantee a specified noise-level margin. Do-D7. System Data Bus (Bidirectional, 3-state). The system data bus transfers data and commands between the CPU and the Z80 SIO. Do is the least significant bit. DCDA, DCDB. Data Carrier Detect (Inputs, Active Low). These pins function as receiver enables if the cpu DATA BUS ce aESET 1 f | 28442 CONTROL FROM cpu tond 8D co BA Daisy j _ 4m CHAIN INTERRUPT \ CONTROL | RxDA RaCA TDA Vata SYNCA WIRDYA ATSA CTSA OTAR BCDA a08 AXCE T108 Tac winDya RISB cis ores ocia CHANNEL A MODEM CONTROL CHANNEL B MODEM CONTROL | UND cL n 2/20 iy SGS-THOMSON MICROELECTROMICS 206Figure 2 : Z80 S!O-2 Dual in Line Pin Configuration. ooo D Pew oe s m= om 3| jalatelavatalatata eee Oe me we Ho L] , ay [J 0, [ona [J ce 1] BAA 8 cd [J a6 [uno |} wadve [] a:08 Py ace Pj rca [} tx08 ] ores Pj sts [y crsa Ty) oto8 [J reset SIO is programmed for Auto Enables ; otherwise they may be used as general-purpose input pins. Both pins are Schmitt-trigger buffered to accommo- date slow-risetime signals. The SiO detects pulses 28440-28441-Z8442 on these pins and interrupts the CPU on both logic level transitions. Schmitt-trigger buffering does not guarantee a specific noise-level margin. DTRA, DTRB. Daia Terminal Ready Outputs, Active Low). These outputs follow the state programmed into Z80 SIO. They can also be programmed as general-purpose outputs. In the Z80 SIO-1 bonding option, DTRB is omitted. IEI. Interrupt Enable in (Input, Active High). This sig- nal is used with IEO to form a priority daisy chain when there is more than one interrupt-driven device. A High on this line indicates that no other device of higher priority is being serviced by a CPU interrupt service routine. IEO. interrupt Enable Out (Output, Active High). IEO is High only if IEI is High and the CPU is not servic- ing an interrupt from this SIO. Thus, this signal biocks lower priority devices form interrupting while a higher priority device is being serviced by its CPU interrupt service routine. INT. interrupt Request (Output, Open Drain, Active Low)._When the SIO is requesting an interrupt, it puils INT Low. IORQ. Input/Output Request (Input from CPU, Ac- tive Low). IQRQ is used in conjunction with B/A, C/D, CE and RD to transfer commands and data be- tween the CPU and the SIO. When CE, RD and Figure 3 : Z80 SIO-I Logic Function. cpu cara gus CONTROL FROM cpu DAISY CHAIN INTERRUPT CONTROL |-___ |--___. }____ oe }e- } __ Po ___. |___. _ oe p__ -+| od, axDA ~>+] p, Rica ~ +] 0, Tapa +] 0, tata +e] 0, SYNCA -e] o, winDvA +] +] 0, aYSA Sa . Oras e] ce Ocha ] RESET zeaat e] a: R08 +] fone asce +] ao 1.08 nce e| 6 SYNCE . WiRDYE e] sa _ arse yr cm otos to I ano i] MODEM CONTAOL MODEM CONTROL CHAMNEL A CHANNEL ir SGS-THOMSON 3/20 MICROE.ZCTRONICS 20728440-28441-28442 Figure 4 : 280 SIO-| Dual in Line Pin Configuration. ra 40 4 Dg o, (2 a3 [] b, o,()3 wf]o. o,(j a7 [ , int Cs 36 [] ord ver C] 6 3s [J ce 10 (7 34 aa mi Cs 3 co Vcc (Js 32 [) #0 wRovA(] 10 7ggqq 1 LJ Gno syaca (] 30 [] wrove Rada (J 12 23 [] synce Aca C13 ze [-} Rx08 aA (] 14 27 [J Race Tx04 [] 15 26 [J Ce OTRA (] 16 25 12D8 rsa [J 17 2a] atsa cTsa (Jaa 23 [J crse ocoa (] 9 22 [ ocos cix (] 20 21) AeseT \ORQ are all active, the channel selected by B/A transfers data to the CPU (a read operation). When CE and |ORQ are active but RD is inactive, the chan- nel selected by B/A is written to by the CPU with either data_or control information as specified by C/D. If lORQ and M1 are active simultaneously, the Figure 5 : Z80 SiO-0 Logic Function. CPU is acknowledging an interrupt and the SIO automatically places its interrupt vector on the CPU data bus if it is the highest priority device requesting an interrupt. M1. Machine_Cycie (Input from Z80 CPU, Active Low). When M1 is active and RD is also active, the Z80 CPU is fetching an_instruction from memory ; when M1 is active while IORQ is active, the SIO ac- cepts M1 and IORQ as an interrupt acknowledge if the SIO is the highest priority device that has inter- rupted the 280 CPU. RxCA, RxCB. Receiver Clocks (Inputs), Receive data is sampled on the rising edge of RxC. The Re- ceive Clocks may be 1, 16, 32 or 64 times the data rate in asynchronous modes. These clocks may be driven by the Z80 CTC Counter Timer Circuit for pro- grammable baud rate generation. Both inputs are Schmitt-trigger buffered (no noise level margin is specified). In the Z80 SIO-0 bonding option, RxCB is bonded together with TxCB. RD. Read Cycle Status (Input from CPU, Active Low). If RD is active, a memory or I/O read _oper- ation is in progress. RD is used with B/A, CE and 1ORQ to transfer data from the SIO to the CPU. RxDA, RxDB. Receive Data (inputs, Active High). Serial data at TTL levels. RESET. Resef (Input, Active Low). A Low RESET disables both receivers and transmitters, forces cru DATA BUS CHANNEL A | je _ e La | --___ +| ~s- Po + +l, arsx |}__+- CTSA |- | MODEM _ zesag ORK} > / CONTROL _+| cE oma |~__. +] RESET +| mi contro. | +1 iono 08 + ree} | 89 FRTICB | x08 -__ +| od WNC x FRDYS -e | 8A CHANNEL 8 ATSB -___+ Daisy | int rss }~+ | movem wrennure 6 1 !! ava | ( CONTROL contro. | -1!0 od +54 GND 4/20 ky SGS-THOMSON ME SRORLEST SOR ISS 208Figure 6 : Z80 SIO-0 Dual in Line Pin Z28440-28441-28442 Figure 7 : Chip Carrier Pin Configuration. Configuration. a(t wr 40 DJ 00 Been on ole ie og: 39 [J & Zoageagcaodg GIS tu Os(j3 nfo a 1 7 Gh 6) 47 4 40 offs y 3 De ard) s 36 [] ona iC e 36D) cE 10 [] 7 34 A BA mC) 30 ca ve sesso | 32 a0 WanvA (] 10 z80$10/0 31] ono Syaca C11 aD wraps Rxoa (] 12 20 0] svnce Pata CQ 13 28 [J Axo Wea CJ 14 az] ance Taba (] 15 2 [} bos BYRA (12 2s [OTR Rrsk (| 7 2a [1] Fs ERPS SREEEE TEAC] ts a3 [J crse 6S le 1G 1S We 1S IG te fo 50K C2 22 fy boos cux C] 2 21 [1] RESET Notes : NC = No Connection. | Z80 SIO-0 or Dart in Asynchronous Mode. TxDA and TxDB marking, forces the modem con- trols High and disables all interrupts. The control registers must be rewritten after the SIO is reset and before data is transmitted or received. RTSA. RTSB. Request To Send (Outputs, Active Low). When the RTS __bit in Write Register 5 (figure 14) is set, the RTS output goes Low. When the RTS bit is reset in the Asynchronous mode. the output goes High after the transmitter is empty. In Synchronous modes, the RTS pin strictly follows the state of the RTS bit. Both pins can be used as general-purpose outputs. SYNCA, SYNCB. Synchronization (Inputs/Outputs, Active Low). These pins can act either as inputs or outputs. In the asynchronous receive mode, they are inputs similar to CTS and DCD. In this mode, the transitions on these lines affect the state of the Sync/Hunt status bits in Read Register 0 (figure 14), but have no other function. In the External Sync mode, these lines also act as inputs. When external synchronization is achieved, SYNC _must be driven Low on the second rising edge of RxC after that ris- ing edge of RxC on which the last bit of the sync character was received. In other words, after the sync pattern is detected, the external logic must wait for two full Receive Clock cycles to activate the SYNC input. Once SYNC is forced Low, it should be kept Low until the CPU informs the external syn- chronization detect logic that synchronization has been lost or a new message is about to start. Char- acter assembly begins on the rising edge of RxC that immediately precedes the falling edge of SYNC in the External Sync mode. In the internal synchronization mode (Monosync and Bisync) these pins act as outputs that are ac- tive during the part of the receive clock (RxC) cycle in which sync characters are recognized. The sync condition is not latched so these outputs are active each time a sync pattern is recognized, regardless of character boundaries. Inthe 280 SIO-2 bonding option, SYNCB is omitted. TxCA-TxCB. Transmitter Clocks (inputs). in asyn- chronous modes, the Transmitter Clocks may be 1, 16, 32 or 64 times the data rate ; however, the clock multiplier for the transmitted and the receiver must be the same. The Transmit Clock inputs are Schmitt-trigger buffered for relaxed rise- and fail- time requirements (no noise level margin is speci- fied). Transmitter Clocks may be driven by the Z80 CTC Counter Timer Circuit for programmable baud rate generation. In the 280 SIO-0 bonding option, TxCB is bonded together with RxCB. TxDA, TxDB. Transmitt Data (Outputs, Active High). Serial data at TTL levels. TxD changes from the falling edge of TxC. W/RDYA, W/RDYB. Wait/Ready A, Wait/Ready B (Outputs, Open Drain when Programmed for Wait function, driven High and Low when programmed for Ready function). These dual-purpose outputs may be programmed as Ready lines for a DMA con- troller or as Wait lines that synchronize the CPU to the SIO data rate. The reset state is open drain. by S&s:THOMso 5/20 20928440-Z8441-Z8442 Figure 8 : Block Diagram. H> | semtai oata - | -- | 7 CHANNEL CLOCKS CHANNEL A jo 5 CAN CHANNEL A joe SYNC ; INTERNAL CONTROL } = WAITREAD CONTAOL AND Loic STATUS REGISTERS CHANNEL & +_ CONTROL _ { MODEM OR AND P= | OTHER CONTROLS STATUS = oata * cru INTERNAL 8U5 BUS HO INTERNAL . TONIROL 6 > CHANNEL 8 _. CONTROL wee ( MODEM OF Ww AND p+ j OTHER conTROLS STATUS | CHANNEL & INFERAUPE oP INTERRUPT CONTROL cONtTROL CONTROL AND _- LOGIC STATUS nes REGISTERS, __ ' SERIAL DATA > CHANNEL & TOT | canner cocks _ SYNC -= WAITREADY FUNCTIONAL DESCRIPTION The functional capabilities of the Z80 SIO can be de- scribed from two different points of view : as a data communication device, it transmits and receives serial data in a wide variety of data-communication protocols ; as a Z80 family peripheral, it interacts with the Z80 CPU and other peripheral circuits, shar- ing the data, address and control buses, as well as being a part of the Z80 interrupt structure. As a pe- ripheral to other microprocessors, the SIO offers valuable features such as non-vectored interrupts, polling and simple handshake capability. Figure 9 illustrates the conventional devices that the SIO replaces. The first part of the following discussion covers SIO data-communication capabilities ; the second part describes interactions between the CPU and the SIO. Figure 9 : Conventional Devices Replaced by the Z80 SIO. UART -| CHANNEL a SYNC! COMMUNICATIONS CONTROLLER - __ MIC KUPHOCESSUN INTERRUPL INTERFACE * CONTROLLER _ Bl vAAT CHANNEL 8 L$ SYNCHAONOUS COMMUNICATION CONIRULLER MICROPROCESSOR INTERFACE ++ ~~ _ CHANNEL a -_> zZa0c aI ~~ CHANNEL 8 6/20 ky SGS-THOMSON MISRORLEST RONICE 210DATA COMMUNICATION CAPABILITIES The SIO provides two independent full-duplex chan- neis that can be programmed for use in any common asynchronous or synchronous data-communication protocol. Figure 10 illustrates some of these proto- cols. The following is a short description of them. A more detailed explanation of these modes can be found in the 280 Family Technical Manual. ASYNCHRONOUS MODES Transmission and reception can be done inde- pendently on each channel with five to eight bits per character, plus optional even or odd parity. The transmitters can supply one, one-and-a-half or two stop bits per character and can provide a break out- put at any time. The receiver break-detection logic interrupts the CPU both at the start and end of a re- ceived break. Reception is protected from spikes by a transient spikerejectian mechanism that checks the signal one-half a bit time after a Low level is de- tected on the receive data input (RxDA or RxDB in figure 6). If the Low does not persist-as in the case of a transient-the character assembly process is not started. Framing errors and overrun errors are detected and buffered together with the partial character on which they occurred. Vectored interrupts allow fast servic- ing of error conditions using dedicated routines. Fur- thermore, a built-in checking process avoids interpreting a framing error as a new start bit : a fram- ing error results in the addition of one-half a bit time to the point at which the search for the next start bit is begun. The SIO does not require symmetric transmit and receive clock signals-a feature that allows it to be used with a Z80 CTC or many other clock sources. The transmitter and receiver can handle data at a rate of 1, 1/16, 1/32 or 1/64 of the clock rate sup- plied to the receive and transmit clock inputs. In asynchronous modes, the SYNC pin may be pro- grammed as an input that can be used for functions such as monitoring a ring indicator. SYNCHRONOUS MODES The SIO supports both byte-oriented and bit oriented synchronous communication. Synchronous byte-oriented protocols can be handled in several modes that allow character syn- chronization with an 8-bit sync character (Mono- sync), any 16-bit sync pattern (Bysinc), or with an external sync signal. Leading sync characters can be removed without interrupting the CPU. Five-, six- or seven-bit sync characters are detected with 8- or 16-bit patterns in the SIO by overlapping 28440-Z8441-Z8442 the larger pattern across multiple in-coming sync characters, as shown in figure 11. CRC checking for synchronous byte-oriented modes is delayed by one character time so the CPU may disable CRC checking on specific characters. This permits implementation of protocols such as IBM Bisync. Both CRC-16 (x' + x'5 + x? + 1) and CCITT (x' +xX'?4.x4 1) error checking polynomials are sup- ported. In allnon-SDLC modes, the CRC generator is initialized to 0s ; in SDLC modes, it is initialized to 1s. The SIO can be used for interfacing to periph- erals such as hard-sectored floppy disk, but it can- not generate or check CRC for IBM-compatible soft-sectored disks. The SIO also provides a feature that automatically transmits CRC data when no other data is available for transmissions. This allows very high-speed transmissions under DMA control with no need for CPU intervention at the end of a message. When there is no data or CRC to send in synchronous modes, the transmitter inserts 8- or 16-bit sync characters regardless of the pro- grammed character length. The SIO supports synchronous bit-oriented proto- cols such as SDLC and HDLC by performing auto- matic flag seding, zero insertion and CRC generation. A special command can be used to abort a frame in transmission. At the end of a mess- age the SIO automatically transmits the CRC and trailing flag when the transmit buffer becomes empty. If a transmit underrun occurs in the middle of a message, an external/status interrupt warns the CPU of this status change so that an abort may be issued. One to eight bits per character can be sent, which allows reception of a message with no prior information about the character structure in the in- formation field of a frame. The receiver automatically synchronizes on the leading flag of a frame in SDLC or HDLC, and pro- vides a synchronization signal on the SYNC pin ; an interrupt can also be programmed. The receiver can be programmed to search for frames addressed by a single byte to only a specified user-selected ad- dress or to a global broadcast address. In this mode, frames that do not match either the user-selected or broadcast address are ignored. The number of ad- dress bytes can be extended under software con- trol. For transmitting data, an interrupt on the first received character or on every character can be se- lected. The receiver automatically deletes all zeroes inserted by the transmitter during character assem- bly. It also calculates and automatically checks the CRC to validate frame transmission. At the end of transmission, the status of a received frame is avail- able in the status registers. 7 SSS-THOMSON 7/20 MIGRE SLECTROMES 21128440-28441-Z8442 The SIO can be conveniently used under DMA con- trol to provide high-speed reception or transmission. In reception, for example, the SIO can interrupt the CPU when the first character of a message is re- ceived. The CPU then enables the DMA to transfer the message to memory. The SIO then issues an end-of-frame interrupt and the CPU can check the status of the received message. Thus, the CPU is freed for other service while the message is being received. 1/O INTERFACE CAPABILITIES The SIO offers the choice of polling, interrupt, (vec- tored or non-vectored) and block-transfers modes to transfer data, status and control information to and from the CPU. The block-transfer mode can also be implemented under DMA control. POLLING Two status registers are updated at appropriate times for each function being performed (for example, CRC error-status valid at the end of a message). When the CPU is operated in a polling fashion, one of the SIOs two status registers is used to indicate whether the SIO has some data or needs Figure 11 : Six Bit Sync Character Recognition. some data. Depending on the contents of this reg- ister, the CPU will either write data, read data, or just go on. Two bits in the register indicate that a data transfer is needed. In addition, error and other con- ditions are indicate. The second status register (spe- cial receive conditions) does not have to be read in a polling sequence, until a character has been re- ceived. All interrupt modes are disabled when oper- ating the device in a polled environment. INTERRUPTS The SIO has an elaborate interrupt scheme to pro- vide fast interrupt service in real-time applications. Acontrol register and a status register in Channel B contain the interrupt vector. When programmed to do so, the SIO can modify three bits of the interrupt vector in the status register so that in points direct- ly to one of eight interrupt service routines in mem- ory, thereby servicing conditions in both channels and eliminating most of the needs for a status-ana- lysis routine. Transmitt interrupts, receive interrupts and exter- nal/status interrupts are the main sources of inter- rupts. Each interrupt source is enabled under program control, with Channel A having a higher PARITY \" START MARKING LINE 2 { SYNC ] DATA l [ SYNC l SYNC i DATA ] T r 7 u OaTA | Li DATA ] lL DATA | MARKING LINE ASYNCHRONOUS [para] crc, [sacs J MONOSYNC | DATA | CRCy | CRCy | SIGNAL BISYNC CT) | DATA | CAC, I encz | EXTERNAL SYNC 55 | FLAG | ADDRESS [ INFORMATION 6 BITS | CRC, | CRC, 1 rac | 5 SOLCIMOLCIX.25 Figure 10. Some Z80 SIO Protocols Se 8 16 r 7 | SYNC ] SYNC [sere I Qata | DATA 2 1 T- DATA | DATA J 8/20 i SGS-THOMSON MISROELZCTROVICS 212priority than Channel B, and with receive, transmit and external/status interrupts prioritized in that order within each channel. When the transmit interrupt is enabled, the CPU is interrupted by the transmit buffer becoming empty. (This implies that the transmitter must have had a data character written into it so it can become empty). The receiver can interrupt the CPU in one or two ways : a interrupt on first received character a Interrupt on all received characters Interrupt-on-first-received-character is typically used with the block-transfer mode. Interrupt-on-all- received-characters has the option of modifying the interrupt vector in the event of a parity error. Both of these interrupt modes wiil also interrupt under spe- cial receive conditions on a character or message basis (end-of-frame interrupt in SDLC, for example). This means that the special-receive condition can cause an interrupt only if the interrupt-on-first-recei- ved-character or interrupt-on-all-received-charac- ters mode is selected. In interrupt-on-first-received- character, an interrupt can occur from special-re- ceive conditions (except parity error) after the first- received-character interrupt (example : receive- overrun interrupt). The main function of the external/status interrupt is to monitor the signal transitions of the Clear To Send (CTS), Data Carrier Detect (DCD) and Synchroni- zation (SYNC) pins (figures 1 through 6). In addi- tion, an external/status interrupt is also caused by a CRC-sending condition or by the detection of a break sequence (asynchronous mode) or abort se- 28440-28441 -28442 quence (SDLC mode) in the data stream. The inter- rupt caused by the break/abort sequence allows the SIO to interrupt when the break/abort sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the break/abort condition in external logic. Ina Z80 CPU environment (figure 12), SO interrupt vectoring is automatic : the SIO passes its inter- nally-modificable 8-bit interrupt vector to the CPU, which adds an additional 8 bits from its interrupt-vec- tor (I) register to form the memory address of the in- terrupt-routine table. This table contains the address of the beginning of the interrupt routine itself. The process entails an indirect transfer or CPU control to the interrupt routine, so that the next instruction executed after an interrupt acknowledge by the CPU is the first instruction of the interrupt routine itself. CPU/DMA BLOCK TRANSFER The SIOs block-transfer mode accommodates both CPU block transfers and DMA controllers (Z80 DMA or other designs). The block-transfer mode uses the Wait/Ready output signal, which is selected with three bits in an internal control register. The Wait/Ready output signal can be programmed as a WAIT line in the CPU block-transfer mode or as a READY line in the DMA block-transfer mode. To a DMA controller, the SIO READY output indi- cates that the SiO is ready to transfer data to or from memory. To the CPU, the WAIT output indicates that the SiO is not ready to transfer data, thereby re- questing the CPU to extend the I/O cycle. 57 S6S:THOMSON 920 MICROR.SCTROKICS 21328440-28441 -Z8442 Figure 12 : Typical Z80 Environment. ) +5 tet 4 zero, cre ZC, INT 10 | a) RiCA INT | ef taca ko bP. TacB wiknYa b- WIRDYE S10 SYSTEM BUSES (J Oo int ei OMA (4 INTERNAL STRUCTURE The internal structure of the device includes a Z80 CPU interface, internal control and interrupt logic, and two full-duplex channels. Each channel con- tains its own set of control and status (write and read) registers, and control and status logic that pro- vides the interface to modems or other external de- vices. The registers for each channel are designated as follows : WRO-WR7 - Write Registers 0 through 7 RRO-RR2 - Read Register 0 through 2 The register group includes five 8-bit control regis- ters, two sync-character registers and two status registers. The interrupt vector is written into an ad- ditional 8 -bit register (Write Register 2) in Chan- nelB that may be read through another 8-bit register (Read Register 2) in Channel B. The bit assignment and functional grouping of each register is con- figured to simplify and organize the programming process. Table 1 list the functions assigned to each read or write register. The logic for both channels provides formats, syn- chronization and validation for data transferred to 10/20 ii SGS-THOMSON and from the channel interface. The modem control inputs, Clear To Send (CTS) and Data Carrier De- tect (DCD), are monitored by the external control and status logic under program control. All external Read Register Functions RRO Transmit/Receive Buffer Status, Interrupt Status and External Status RRi Special Receive Condition Status RR2 Modified Interrupt Vector (channel B only) Write Register Functions WRO Register pointers, CRC initialize, initialization commands for the various modes, etc. WRI Transmitt/Receive Interrupt and Data Transfer Mode Definition WR2 Interrupt Vector (channel B only) WR3 Receive Parameters and Control WR4 Transmit/Receive Miscellaneous Parameters and Modes WR5 Transmit Parameters and Controls WR6 Syne Character or SDLC Address Field WR7 Sync Character or SDLC Flag MICROELECTRONICS 214Z8440-Z8441-Z8442 control-and-status-logic signals are general-pur- routed through one of several paths (data or CRC) pose in nature and can be used for functions other depending on the selected mode and-in asynchron- than modem control. DATA PATH ous modes-the character length. The transmitter has an 8-bit transmit data buffer reg- ister that is loaded from the internal data bus, anda 20-bit transmit shift register that can be loaded from the sync-character buffers or from the transmit data register. Depending on the operational mode, out- going data is routed throught one of four main paths before it is transmitted from the Transmit Data out- put (TxD). The transmit and receive data path illustrated for Channel A in figure 13 is identical for both channels. The receiver has three 8-bit buffer registers in a FIFO arrangement, in addition to the 8-bit receive shift register. This scheme creates additional time for the CPU to service an interrupt at the beginning of a block of high-speed data. Incoming data is Figure 13 : Transmit and Receive Data Path (channel A). TO CHANNEL B. EXTERNAL STATUS LOGIC, CONTROL LOGIC. ETC RECEWE TRANSMIT DATA was SYNC REGISTER Y 20-BiT TAANSMIT SHIFT REGISTER rs we ASTRE SYNC oara DATA YRANSHIT _ RECEIVE RECEIVE soLc MULTILEXER b Tada Rac e] cLocx EAROR DATA 42811 DELAY toaic HUNT MODE (BISYNC) cocie ZERO INSERT | ceeienteeienienionien 7 ts BITS) sync war SYNC REGISTER \ CRC 1 t __spue-ene RECEIVE ou SYNC REGISTER Rak 3811S fe! staFT REGISTER oetar Peng oLtere eas [ cation }- J ied GENERATOR CLOC LOGIC th ttt owe ASYNC DATA eRe CRC OELAY REGISTER tA BITS) + ore a] CHECKER Fn resuns SOLEERE 11/20 / L5, 7 SGS-THOMSON MICROELECTRONICS 215Z8440-Z8441-28442 PROGRAMMING The system program first issues a series of com- mands that initialize the basic mode of operation and then other commands that qualify conditions within the selected mode. For example, the asyn- chronous mode, character length, clock rate, num- ber of stop bits, even or odd parity might be set first ; then the interrupt mode ; and finally, receiver or transmitter enable. Both channels contain registers that must be pro- grammed via the system program prior to operation. The channel-select input (B/A) and the control/data input (C/D) are the command-structure addressing controls, and are normally controlled by the CPU ad- dress bus. Figures 16 an 17 illustrate the timing re- lationships for programming the write registers and transfering data and status. READ REGISTER The SIO contains three read registers for Chan- nel B and two read registers for Channel A(RRO-RR2 in figure 14) that can be to obtain the status informa- tion ; RR2 contains the internally-modifiable interrupt vector and is only in the Channel B register set. The status information includes error conditions, interrupt vector and standard communications-interface sig- nals. To read the contents of a selected read register other than RRO, the system program must first write the pointer byte to WRO in exactly the same way as a write register operation. Then, by executing a read instruction, the contents of the addressed read reg- ister can be read by the CPU. The status bits of RRO and RR1 are carefully grouped to simplify status monitoring. For example. when the interrupt vector indicates that a Special Receive Condition interrupt has occurred, all the ap- propriate error bits can be read from a single regis- ter (RAI). WRITE REGISTERS The SIO contains eight write registers for Chan- nel B and seven write registers for Channel A (WRO- WR7 in figure 15) that are programmed separately to configure the functional personality of the chan- nels ; WR2 contains the interrupt vector for both channels and is only in the Channel B register set. With the exception of WRO, programming the write registers requires two bytes. The first byte is to WRO 12/20 kyr SGS-THOMSON and contains three bits (Do-Dz) that point to the se- lected register ; the second byte is the actual con- trol word that is written into the register to configure the SIO. WRO is a special case in that all of the basic com- mands can be written to it with a single byte. Reset (internal or external) initializes the pointer bits Do-Dz2 to point to WRO. This implies that a channel reset must not be combined with the pointing to any reg- ister. Figure 14 : Read Register Bit Functions. READ REGISTER 0 [e270 ]705 15 Jo] Rix CHARACTER AVAILABLE INT PENDING (CH. A ONLY} Tx BUFFER EMPTY ocD SYNCIHUNT cis * Tx UNDERRUNIEOM SREAKIABORT *Used With External/Status interrupt Mode READ REGISTER It | lL ALL SENT { : {FIELD BITS 1 FIELD BITS IN IN PREVIOUS SECOND PREVIOUS BYTE BYTE 9 3 Owes o4e4 Ga nOonno Onan sgna Nacooce EN | i PARITY ERROR Rx OVERRUN ERROR b____ CRC/FRAMING ERROR EN oF FRAME (SDLC) Residue Data For Eight Rx Bits/Character Programmed tUsed With Special Receive Condition Mode READ REGISTER 2 Dy: 04,0, 0, 0, D,. 0, / 0 vo vit : vat vat) INTERRUPT va / VECTOR vs ve vr Tvariable if "Status Affects Vector is Programmed MICROELZCTRORICS 216Z8440-28441-Z8442 Figure 15 : Write Register Bit Functions. WRITE REGISTER 0 REGISTER 0 REGISTER 1 REGISTER Z REGISTER J REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 aa OOOO at OOOO ae AR 222 Ono NULL CODE SEND ABORT (SDLC} RESET EXTJSTATUS INTERRUPTS CHANNEL RESET ENABLE INT ON NEXT Ax CHARACTER RESET Tx INT PENOING ERROR RESET RETURN FROM INT (CH-A ONLY} a ot BDOCO sage 4400 AO OmO4e NULL CODE RESET Rx CRC CHECKER RESET Tx CRC GENERATOR RESET Tx UNDERRUN/EOM LATCH a~-=o90 woud WRITE REGISTER 1 [9:]>[o.[o. |. 10,] 0, [00] [_ ExT INT ENABLE Tx INT ENABLE STATUS AFFECTS VECTOR (CH. B ONLY} 0 @ Rx INT DISABLE 0 1 Rx INT ON FIRST CHARACTER 1 0) INT ON ALL Rx CHARACTERS (PARITY AFFECTS VECTOR) 1 of INT ON ALL Rx CHARACTERS (PARITY DOES NOT AFFECT VECTOR) WAITIREADY ON RIT *Or on WAITIREADY FUNCTION 7 WAITREAOY ENABLE Special Condition WRITE REGISTER 2 (CHANNEL B ONLY) Vi INTERRUPT ve f VECTOR vi WRITE REGISTER 3 Brel eels [es] | L= Rx ENABLE SYNC CHARACTER LOAD INHIGIT ADDRESS SEARCH MODE (SDLC) Rx CRC ENABLE ENTER HUNT PHASE AUTO ENABLES Ax BITSICHARACTER fix 7 BITSICHARACTER Rx 6 BITSICHARACTER Ra & BITSICHARACTER moa mone WRITE REGISTER 4 [Po] 5]. [5 [02/0 |. LL parity ENABLE _ PARITY EVEN/OGD SYNC MODES ENABLE 1 STOP BITICHARACTER 1'2 STOP SITSICHARACTER 2 STOP BITSICHARACTER wh OO Oud 0 OG @ BIT SYNC CHARACTER 0 4 +8 BIT SYNC CHARACTER 4 0 SOLC MODE (01111110 FLAG} + 4 EXTERNAL SYNC MODE X1 CLOCK MODE woe ono x a e 9 2 x z oO m X64 CLOCK MODE WRITE REGISTER 5 CIESCSCACIDICIGS Tx CRC ENABLE ATS SDLCICRC-16 Tx ENABLE 7 SEND SREAK Tx 5 BITS (OR LESSVCHARACTER Tx 7 BITSICHARACTER Tx 6 BITSICHARACTER Tx 6 SITSICHARACTER I ~ 200 AO me BTR WRITE REGISTER 6 SYNC BIT O SYNC BIT 1 SYNC BIT 2 SYNC BIT 3 SYNC BIT 4 SYNC BIT 5 SYNC BIT.6 SYNC BIT? *also SDLC Address Field [ WRITE REGISTER 7 SYNC BITS SYNC BIT 9 SYNC BIT 10 SYNC BIT it SYNC BIT 12 SYNC BIT 13 SYNC BIT 44 SYNC BIT 5 *For SDLC it Must Be Programmed to "01111110" For Flag Recognition : ky SGS-THOMSON Y7 MickomscTromes 13/20 21728440-28441-Z8442 TIMING The SIO must have the same clock as the CPU (same phase and frequency relationship, not necessarily the same driver). READ CYCLE The timing signals generated by a Z80 CPU input instruction to read a data or status byte from the SIO are illustrated in figure 16. WRITE CYCLE Figure 16 illustrates the timing and data signals generated by a Z80 CPU output instruction to write a data or control byte into the SIO. INTERRUPT-ACKNOWLEDGE CYCLE After receiving an interrupt-request signal from an SIO (INT pulled Low), the Z80 CPU sends an inter- rupt-acknowledge sequence (M1 Low, and IORQ Low a few cycles later) as in figure 18. The SiO contains an internal daisy-chained interrupt structure for prioritizing nested interrupts for the vari- ous functions of its two channels, and this structure can be used within an external user-defined daisy chain that prioritizes several peripheral circuits. The IEI of the highest-priority device is terminated High. A device that has an interrupt pending or under service forces its IEO Low. For devices with no interrupt pending or under service, IEO = IE. To insure stable conditions in the daisy chain, all in- terrupt status signals are_ prevented from changing while M1 is Low. When IORQ is Low, the highest Figure 16 : Read Cycle. priority interrupt requestor (the one with IE! High) places its interrupt vector on the data bus and sets its internal interrupt-under-service latch. RETURN FROM INTERRUPT CYCLE Figure 19 illustrates the return from interrupt cycle. Normally, the Z80 CPU issues a RETI (Return From Interrupt) instruction at the end of an interrupt ser- vice routine. RETI is a 2-byte opcode (ED-4D) that resets the interrupt-under-service latch in the SIO to terminate the interrupt that has just been processed. This is accomplished by manipulating the daisy chain in the following way. The normal daisy-chain operation can be used to detect a pending interrupt ; however, it cannot dis- tinguish between an interrupt under service and a pending unacknowledged interrupt of a higher priority. Whenever "ED" is decoded, the daisy chain is modified by forcing High the IEO of any interrupt that has not yet been acknowledged. Thus the daisy chain identifies the device presently under service as the only one with an IEI High and an IEO Low. If the next opcode byte is "4D", the interrupt-under- service latch is reset. The ripple time of the interrupt daisy chain (both the High-to-Low and the Low-to-High transitions) limits the number of devices that can be placed in the daisy chain. Ripple time can be improved with carry- look-ahead, or by extending the interrupt-acknow- ledge cycle. For further information about techniques for increasing the number of daisy- chained devices, refer to the Z80 CPU Data Sheet. Figure 17 : Write Cycle. + cLvockn N | y | CE, C/D, BIA , 14/20 kyr SGS-THOMSON MiSROEL ECT FOR SE 218Figure 18 : Interrupt Acknowledge Cycle. Z8440-28441-Z28442 Figure 19 : Return from Interrupt Cycle. AD + ~------~. Lo (Ei 7 l \ ------~ , \--- ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vi Voltage on all Input and Outputs with Respect to GND 0.3 to + 7.0 Vv Ta Operating Ambient Temperature As Specified in Order Codes Tstg Storage Temperature C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Ex- posure to absolute maximum rating conditions for extended periods may affect device reliability. TEST CONDITIONS The characteristics below apply for the following test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Positive current flows into +5 the referenced pin. Available operating temperature ranges are: 2K 0Cto+ 70C, Faow OuTPUT + 4.75V < Voc < + 5.25V UNDER TEST a 40 C to + 85 C, + 4.75V < Voc < + 5.25V 100 pF 250 a 55 C to +125 C, + 4.75V < Veco < + 5.5V The product number for each operating temperature > = + range may be found in the ordering information sec- tion. CAPACITANCE Symbol Parameter Note Min. Max. Unit Cc Clock Capacitance 40 pF Cin Input Capacitance Unmeasured Pins 5 pF , Returned to Ground Cout Output Capacitance 10 pF Over specified temperature range ;f = 1 MHz. 15/20 i SGS-THOMSON MICROELZCTRORICS 219Z8 440-Z8441 -Z8442 DC CHARACTERISTICS Symbol Parameter Test Conditions Min. Max. Unit Vicc Clock Input Low Voltage -0.3 | + 0.45 Vv Vinc Clock Input High Voltage Veco 0.6/Vcc + 0.3 Vv Vic Input Low Voltage - 0.3 +08 Vv Vin Input High Voltage 2.0 Voc Vv Vor Output Low Voltage lol =2.0 MA - + 0.4 Vv Vou Output High Voltage lon =- 250 [tA + 2.4 Vv lo Input Leakage Current Vin =0 to Veco 10 +10 LA lo 3-State Output Leakage Current in Float Vout =0.4 to Voc - 10 +10 pA lLisy; SYNC Pin Leakage Current 0< Vin < Veco 40 +10 uA loc Power Supply Current 100 mA Over specified temperature and voltage range. AC CHARACTERISTICS 28440, 28440, 28440, 1,2 1,2A 1, 2B N'} Symbol Parameter Min. |Max.| Min. |Max.| Min. |Max. (ns) | (ms) | (Ms) | (ns) | (ns) | (ns) 1 Tc Clock Cycle Time 400 |4000/ 250 |4000] 165 | 4000 2 TwCh Clkock Width (high) 170 |2000/ 105 )2000| 70 |2000 3 TIC Clock Fall Time 30 30 15 4 Tre Clock Rise Time 30 30 15 5 TwCl Clock Width (low) 170 |2000) 105 |2000| 70 {2000 6 TsAD(C) CE, C/D, B/A to Clock * Setup Time 160 145 60 7 TsCS(Cl) TORQ, RD, to Clock 7 Setup Time 240 115 60 8 TdC(DO) Clock * to Data Out Delay 240 220 150 9 TsDI(C) Data in to Clock 7 Setup (write or Mi cycle) 50 50 30 10 TdRDB(DOz) RD T to Data Out Float Delay 230 110 90 1 TdlO(DOl) IORQ J to Data Out Delay (INTACK cycle) 340 160 100 12 TsMi(C) MI to Clock * Setup Time 210 90 75 13 TSIEI(IO) IEl to IORQ Setup Time (INTACK cycle) 200 440 120 14 TdMi(iEQ) Mi. to IEO . Delay (interrupt before Mi) 300 190 160 15 TdlEI(IEOr) IE T to IEO T Delay (after ED decode) 150 100 70 16 TdIEIIEOR IEl L to IEO J Delay 150 100 70 17 TdC(INT) Clock T to INT J Delay 200 200 150 18] TdiO(WRWH | IORQ J or CE L to WRDY ~ Delay (wait mode) 300 210 175 19 TdC(W/RR) Clock T to W/RDY J Delay (ready mode) 120 120 100 20]; TdC(w/RWz) Clock | to W/RDY Float Delay (wait mode) 150 430 110 21 Th Any unspecified hold when setup is specified 0 0 0 16/20 220 ki SGS-THOMSON MISROELE 38AC CHARACTERISTICS (continued) Z8440-28441-Z8442 ze440, | zaa40, | 28440, , 1,2 1,2A 1, 2B N Symbol Parameter Notes Min. |Max.| Min. |Max.| Min. |Max. (ns) | (ns) | (ns) | (ns) | (ns) | (ns) 22 TwPh Pulse Width (high) 200 200 200 23 TwPI Pulse Width low) 200 200 200 24 TeTxC TxC Cycle Time 400} ~ | 400| | 330) ~ 25 TwTxCl TxC Width (low) 180 | o | 180] | 100] 26 TwTxCh TxC Width (high) 180] o | 180] | 100] 27 TdTxC(TxD) TxC 1 to TxD Delay (x!] mode) 400 300 220 28] TdTxC(WRRf) | TxC L to WRDY L Delay Clk Periods | 5 | 9 | 5 | 9 | 5 | 9 (ready mode) 29] TdTxC(INT) | TxC J to INT | Delay Cik Periods* | 5 | 9 | 5 | 9 | 5 |] Q 30 TeRxC RxC Cycle Time | 400| | 400] = | 330] ~ 31 TwRxCl RxC Width (low) 180 | | 180] o | 100] o 32 TwRxCh RxC Width (high) 180 | | 180] | 100] 33 | TsRxD(AxC) | RxD to RxC T Setup Time (xl mode) 0 0 0 34] ThRxD(RxC) | AxC T to RxD Hold Time (x! mode} 140 140 100 35] TdRxC(W/ARA | RxC T to WRDY J Delay Clk Periods* | 10 | 13 | 10 | 13 | 10 | 13 (ready mode) 36] TdRxC(INT) | RxC T to INT l Delay Clk Periods* | 10 | 13 | 10 | 13 | 10 | 13 37 | TdRxC(SYNC) RxC 7 to SYNC 1 Delay Clk Periods* 4 4 7 4 7 (outputs modes) 38 | TsSYNC(RxC) | SYNC L to AxC 7? Setup -100 ~100 -100 (external sync modes) |. In all modes, the System Clock rate must be at least five times the maximum data rate RESET must be active a minimum of one com- plete Clock Cycle. * System Clock. ib SGS-THOMSON 17/20 MICROELECTRONICS 221Z8440-Z8441-Z28442 AC CHARACTERISTICS CLE DoD, int wroy 18/20 ka SGS-THOMSON 7 menonscrsones 22228440-Z8441-28442 AC CHARACTERISTICS (continued) CTS,0C0, SYNC TxC TXO wrROy nT RXC wiRDY INT SYNC {7 SGS-THOMSON 19/20 TF RckomzerRoMies 22328440-28441 -Z8442 ORDERING INFORMATION Type Package Temp. Clock Description 28440/1/2B1 DIP-40 (plastic) 0/+ 70C Z80 Dual Z8440/1/2F1 DIP-40 (frit seal) 0/+ 70C Channel 28440/1/2D1 DIP-40 (ceramic) O/+ 70C 2.5 MHz Serial //O 28440/1/2D6 DIP-40 (ceramic) 40/+ 85C . Controller 28440/1/2D2 DIP-40 (ceramic) 55/+ 125C 28444C1 PLCC44 (plastic chip-carrier) O/+ 70C 28440/1/2AB1 DIP-40 (plastic) 0/+ 70C 28440/1/2AF1 DIP-40 (frit seal) 0/+ 70C 28440/1/2AD1 DIP-40 (ceramic) O/+ 70C 4 MHz 28440/1/2AD6 DIP-40 (ceramic) -40/+ 85C Z8440/1/2AD2 DIP-40 (ceramic) 55/ + 125C ZB444AC1 PLCC44 (plastic chip-carrier) O/+ 70C 28440/1/2BB1 DIP-40 (plastic) O/+ 70C 28440/1/2BF1 DIP-40 (frit seal) O/+ 70C 28440/1/2BD1 DIP-40 (ceramic) O/+ 70C 6 MHz 2Z8440/1/2BD6 DIP-40 (ceramic) 40/+ 85C 2Z8440/1/2BD2 DIP-40 (ceramic) 55/+ 125C 28444BC1 PLCC44 (plastic chip-carrier) O/+ 70C 20/20 * A37 SSctioones 224