3 V, Parallel Input
Micropower 10-/12-Bit DACs
AD7392/AD7393
Rev. C
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FEATURES
Micropower: 100 μA
0.1 μA typical power shutdown
Single-supply 2.7 V to 5.5 V operation
AD7392: 12-bit resolution
AD7393: 10-bit resolution
0.9 LSB differential nonlinearity error
APPLICATIONS
Automotive 0.5 V to 4.5 V output span voltage
Portable communications
Digitally controlled calibration
PC peripherals
FUNCTIONAL BLOCK DIAGRAM
0
112 1 - 0 0 1
12
12
12-BIT
DAC
DAC REGISTER
V
REF
SHDN
AGND
RSD0 TO D11CSDGND
AD7392
V
DD
V
OUT
Figure 1.
GENERAL DESCRIPTION
The AD7392/AD7393 comprise a set of pin-compatible
10-/12-bit voltage output, digital-to-analog converters. The
parts are designed to operate from a single 3 V supply. Built
using a CBCMOS process, these monolithic DACs offer low
cost and ease of use in single-supply 3 V systems. Operation is
guaranteed over the supply voltage range of 2.7 V to 5.5 V,
making this device ideal for battery-operated applications.
The full-scale voltage output is determined by the external ref-
erence input voltage applied. The rail-to-rail REFIN to DACOUT
allows a full-scale voltage equal to the positive supply VDD or
any value in between. The voltage outputs are capable of sourc-
ing 5 mA.
A data latch load of 12 bits with a 45 ns write time eliminates
wait states when interfacing to the fastest processors. Addition-
ally, an asynchronous RS input sets the output to a zero scale at
power-on or upon user demand.
Both parts are offered with similar pinouts, which allows users
to select the amount of resolution appropriate for their applica-
tions without changing the circuit card.
The AD7392/AD7393 are specified for operation over the
extended industrial temperature range of −40°C to +85°C.
The AD7393AR is specified for the automotive temperature
range of −40°C to +125°C. The AD7392/AD7393 are available
in 20-lead PDIP and 20-lead SOIC packages.
For serial data input, 8-lead packaged versions, see the AD7390
and AD7391.
AD7392/AD7393
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 12
Digital-to-Analog Converters................................................... 12
Amplifier Section ....................................................................... 12
Reference Input........................................................................... 12
Power Supply............................................................................... 13
Input Logic Levels ...................................................................... 13
Digital Interface.......................................................................... 13
Reset Pin (RS) ............................................................................. 14
Power Shutdown (SHDN)......................................................... 14
Unipolar Output Operation...................................................... 14
Bipolar Output Operation......................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 17
REVISION HISTORY
8/07—Rev. B to Rev. C
Changes to Specifications Section.................................................. 3
Changes to Table 3............................................................................ 6
Changes to Theory of Operation Section.................................... 12
Changes to Figure 29...................................................................... 13
Changes to Figure 32...................................................................... 14
Changes to Figure 33...................................................................... 15
Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide .......................................................... 17
6/04—Changed from Rev. A to Rev. B
Removed TSSOP.................................................................Universal
Changes to Ordering Guide .......................................................... 17
3/99—Changed from Rev. 0 to Rev. A
11/96—Revision 0: Initial Version
AD7392/AD7393
Rev. C | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VREF = 2.5 V, −40°C < TA < +85°C, unless otherwise noted.
Table 1. AD7392
Parameter Symbol Conditions 3 V ± 10% 5 V ± 10% Unit
STATIC PERFORMANCE
Resolution1 N 12 12 Bits
Relative Accuracy2 INL TA = +25°C ±1.8 ±1.8 LSB max
T
A = −40°C, +85°C ±3 ±3 LSB max
Differential Nonlinearity2 DNL TA = +25°C, monotonic ±0.9 ±0.9 LSB max
Monotonic ±1 ±1 LSB max
Zero-Scale Error VZSE Data = 0x000, TA = +25°C, +85°C 4.0 4.0 mV max
Data = 0x000, TA = −40°C 8.0 8.0 mV max
Full-Scale Voltage Error VFSE TA = +25°C, +85°C, data = 0xFFF ±8 ±8 mV max
T
A = −40°C, data = 0xFFF ±20 ±20 mV max
Full-Scale Temperature Coefficient3 TCVFS 28 28 ppm/°C typ
REFERENCE INPUT
VREF Range VREF 0/VDD 0/VDD V min/max
Input Resistance RREF 2.5 2.5 MΩ typ4
Input Capacitance3 CREF 5 5 pF typ
ANALOG OUTPUT
Current (Source) IOUT Data = 0x800, ∆ VOUT = 5 LSB 1 1 mA typ
Output Current (Sink) IOUT Data = 0x800, ∆ VOUT = 5 LSB 3 3 mA typ
Capacitive Load3 CL No oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage VIL 0.5 0.8 V max
Logic Input High Voltage VIH VDD − 0.6 VDD − 0.6 V min
Input Leakage Current IIL 10 10 μA max
Input Capacitance3 CIL 10 10 pF max
INTERFACE TIMING3, 5
Chip Select Write Width tCS 45 45 ns min
Data Setup tDS 30 15 ns min
Data Hold tDH 20 5 ns min
Reset Pulse Width tRS 40 30 ns min
AC CHARACTERISTICS
Output Slew Rate SR Data = 0x000 to 0xFFF to 0x000 0.05 0.05 V/μs typ
Settling Time6 tS To ±0.1% of full scale 70 60 μs typ
Shutdown Recovery Time tSDR 80 μs typ
DAC Glitch Code 0x7FF to Code 0x800 to Code 0x7FF 65 65 nV/s typ
Digital Feedthrough 15 15 nV/s typ
Feedthrough VOUT/VREF VREF = 1.5 V dc + 1 V p-p, data = 0x000,
f = 100 kHz
−63 −63 dB typ
SUPPLY CHARACTERISTICS
Power Supply Range VDD RANGE DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
Positive Supply Current IDD VIL = 0 V, no load 55/100 55/100 μA typ/max
Shutdown Supply Current IDD-SD SHDN = 0, VIL = 0 V, no load 0.1/1.5 0.1/1.5 μA typ/max
Power Dissipation PDISS VIL = 0 V, no load 300 500 μW max
Power Supply Sensitivity PSS Δ VDD = ±5% 0.006 0.006 %/% max
1 One LSB = VREF/4096 V for the 12-bit AD7392.
2 The first two codes (0x000, 0x001) are excluded from the linearity error measurement.
3 These parameters are guaranteed by design and not subject to production testing.
4 Typicals represent average readings measured at +25°C.
5 All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
AD7392/AD7393
Rev. C | Page 4 of 20
At VREF = 2.5 V, −40°C < TA < +85°C, unless otherwise noted.
Table 2. AD7393
Parameter Symbol Conditions 3 V ± 10% 5 V ± 10% Unit
STATIC PERFORMANCE
Resolution1 N 10 10 Bits
Relative Accuracy2 INL TA = +25°C ±1.75 ±1.75 LSB max
T
A = −40°C, +85°C, +125°C ±2.0 ±2.0 LSB max
Differential Nonlinearity2 DNL Monotonic ±0.8 ±0.8 LSB max
Zero-Scale Error VZSE Data = 0x000 9.0 9.0 mV max
Full-Scale Voltage Error VFSE TA = +25°C, +85°C, +125°C, data = 0x3FF ±32 ±32 mV max
T
A = −40°C, data = 0x3FF ±42 ±42 mV max
Full-Scale Temperature Coefficient3 TCVFS 28 28 ppm/°C typ
REFERENCE INPUT
VREF IN Range VREF 0/VDD 0/VDD V min/max
Input Resistance RREF 2.5 2.5 MΩ typ4
Input Capacitance3 CREF 5 5 pF typ
ANALOG OUTPUT
Output Current (Source) IOUT Data = 0x200, Δ VOUT = 5 LSB 1 1 mA typ
Output Current (Sink) IOUT Data = 0x200, Δ VOUT = 5 LSB 3 3 mA typ
Capacitive Load3 CL No oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage VIL 0.5 0.8 V max
Logic Input High Voltage VIH VDD − 0.6 VDD − 0.6 V min
Input Leakage Current IIL 10 10 μA max
Input Capacitance3 CIL 10 10 pF max
INTERFACE TIMING3, 5
Chip Select Write Width tCS 45 45 ns
Data Setup tDS 30 15 ns
Data Hold tDH 20 5 ns
Reset Pulse Width tRS 40 30 ns
AC CHARACTERISTICS
Output Slew Rate SR Data = 0x000 to 0x3FF to 0x000 0.05 0.05 V/μs typ
Settling Time6 tS To ±0.1% of full scale 70 60 μs typ
Shutdown Recovery Time tSDR 80 μs typ
DAC Glitch Code 0x7FF to Code 0x800 to Code 0x7FF 65 65 nV/s typ
Digital Feedthrough 15 15 nV/s typ
Feedthrough VOUT/VREF VREF = 1.5 V dc 11 V p-p, data = 0x000, f = 100 kHz −63 −63 dB typ
SUPPLY CHARACTERISTICS
Power Supply Range VDD RANGE DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
Positive Supply Current IDD VIL = 0 V, no load, TA = +25°C 55 55 μA typ
V
IL = 0 V, no load 100 100 μA max
Shutdown Supply Current IDD-SD SHDN = 0, VIL = 0 V, no load 0.1/1.5 0.1/1.5 μA typ/max
Power Dissipation PDISS VIL = 0 V, no load 300 500 μW max
Power Supply Sensitivity PSS Δ VDD = ±5% 0.006 0.006 %/% max
1 One LSB = VREF/1024 V for the 10-bit AD7393.
2 The first two codes (0x000, 0x001) are excluded from the linearity error measurement.
3 These parameters are guaranteed by design and not subject to production testing.
4 Typicals represent average readings measured at +25°C.
5 All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.
6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
AD7392/AD7393
Rev. C | Page 5 of 20
TIMING DIAGRAM
0
112 1 - 0 0 4
CS
D11 TO D0
RS
V
OUT
t
CS
DATA VALID
1
0
0
0
1
1
FS
ZS
±0.1%FS
ERROR BAND
t
DS
t
DH
t
RS
t
S
t
S
Figure 2. Timing Diagram
AD7392/AD7393
Rev. C | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VDD to GND −0.3 V, +8 V
VREF to GND −0.3 V, VDD
Logic Inputs to GND −0.3 V, VDD + 0.3 V
VOUT to GND −0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND 50 mA
DGND to AGND −0.3 V, +2 V
Package Power Dissipation (TJ max − TA)/θJA
Thermal Resistance (θJA)
20-Lead PDIP (N 20) 57°C/W
20-Lead SOIC (R-20) 60°C/W
Maximum Junction Temperature (TJ max) 150°C
Operating Temperature Range −40°C to +85°C
AD7393AR −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
Reflow Soldering Peak Temperature
SnPb 240°C
Pb-Free 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7392/AD7393
Rev. C | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
01121-006
AD7392
TOP VIEW
(Not to Scale)
V
DD 1
V
REF
20
SHDN
2
V
OUT
19
CS
3
AGND
18
RS
4
DGND
17
D0
5
D11
16
D1
6
D10
15
D2
7
D9
14
D3
8
D8
13
D4
9
D7
12
D5
10
D6
11
01121-007
AD7393
TOP VIEW
(Not to Scale)
NC = NO CONNECT
VDD 1VREF
20
SHDN 2VOUT
19
CS 3AGND
18
RS 4DGND17
NC 5D916
NC 6D815
D0 7D714
D1 8D613
D2 9D512
D3 10 D4
11
Figure 3. AD7392 Pin Configuration Figure 4. AD7393 Pin Configuration
Table 4. AD7392 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
2 SHDN Power Shutdown Active Low Input. DAC register contents are saved as long as power stays on the VDD pin. When
SHDN = 0, CS strobes write new data into the DAC register.
3 CS Chip Select Latch Enable, Active Low.
4 RS Asynchronous Active Low Input. Resets the DAC register to 0.
5 to 16 D0 to D11 Parallel Input Data Bits. D11 is the MSB; D0 is the LSB.
17 DGND Digital Ground.
18 AGND Analog Ground.
19 VOUT DAC Voltage Output.
20 VREF DAC Reference Input. Establishes the DAC full-scale voltage.
Table 5. AD7393 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
2 SHDN Power Shutdown Active Low Input. DAC register contents are saved as long as power stays on the VDD pin.
When SHDN = 0, CS strobes write new data into the DAC register.
3 CS Chip Select Latch Enable, Active Low.
4 RS Asynchronous Active Low Input. Resets the DAC register to 0.
5, 6 NC No Connect.
7 to 16 D0 to D9 Parallel Input Data Bits. D9 is the MSB; D0 is the LSB.
17 DGND Digital Ground.
18 AGND Analog Ground.
19 VOUT DAC Voltage Output.
20 VREF DAC Reference Input. Establishes the DAC full-scale voltage.
AD7392/AD7393
Rev. C | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 512 1024 1536 2048 2560 3072 3584 4096
AD7392
01121-008
CODE (Decimal)
INL (LSB)
V
DD
= 2.7V
V
REF
= 2.5V
T
A
= 25°C
Figure 5. AD7392 Integral Nonlinearity Error vs. Code
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
AD7393
01121-009
CODE (Decimal)
INL (LSB)
V
DD
= 2.7V
V
REF
= 2.5V
T
A
= 25°C
0 128 256 384 512 640 768 896 1024
Figure 6. AD7393 Integral Nonlinearity Error vs. Code
25
0
5
10
15
20
5.0 5.8 6.6 7.3 8.1 8.9 9.7 10.5 11.2 12.0
01121-010
TOTAL UNADJUSTED ERROR (LSB)
FREQUENCY
AD7392
SS = 100 UNITS
V
DD
= 2.7V
V
REF
= 2.5V
T
A
= 25°C
Figure 7. AD7392 Total Unadjusted Error Histogram
100
90
80
70
60
50
40
30
20
10
0
–10 –3.3 3.3 10 16 23 30 36 43 50
01121-011
TOTAL UNADJUSTED ERROR (LSB)
FREQUENCY
AD7393
SS = 300 UNITS
V
DD
= 2.7V
V
REF
= 2.5V
T
A
= 25°C
Figure 8. AD7393 Total Unadjusted Error Histogram
30
24
18
12
6
0
–66 0–6–12–20–26–32–40–46–52–60
01121-012
FULL-SCALE TEMPERATURE COEFFICIENT (ppm/°C)
FREQUENCY
AD7393
SS = 100 UNITS
V
DD
= 2.7V
V
REF
= 2.5V
T
A
= –40°C TO +85°C
Figure 9. AD7393 Full-Scale Output Temperature Coefficient Histogram
16
14
12
10
8
6
4
2
0
1 10 100 1k 10k 100k
01121-013
FREQUENCY (Hz)
OUTPUT VOLTAGE NOISE (µV/ Hz)
AD7392
V
DD
= 5V
V
REF
= 2.5V
T
A
= 25°C
Figure 10. Voltage Noise Density vs. Frequency
AD7392/AD7393
Rev. C | Page 9 of 20
100
95
90
85
80
75
70
65
60
55
50
0
V
LOGIC
FROM
0V TO 3V
V
LOGIC
FROM
3V TO 0V
3.02.52.01.51.00.5
01121-014
V
IN
(V)
SUPPLY CURRENT (µA)
AD7392
V
DD
= 3V
T
A
= 25°C
Figure 11. Supply Current vs. Logic Input Voltage
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1765432
01121-015
SUPPLY VOLTAGE (V)
THRESHOLD VOLTAGE (V)
AD7392
CODE = 0xFFF
V
REF
= 2V
RS LOGIC VOLTAGE
VARIED
V
LOGIC
FROM
LOW TO HIGH
V
LOGIC
FROM
HIGH TO LOW
Figure 12. Logic Threshold vs. Supply Voltage
100
30
40
50
60
70
80
90
20
–55 –35 –15 5 25 45 65 85 105 125
01121-016
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
V
DD
= 5V, V
LOGIC
= 0V
V
DD
= 3.6V, V
LOGIC
= 2.4V
V
DD
= 3V, V
LOGIC
= 0V
AD7392
SAMPLE SIZE = 300 UNITS
Figure 13. Supply Current vs. Temperature
1000
800
600
400
200
0
1k 10k 100k 1M 10M
01121-017
CLOCK FREQUENCY (Hz)
SUPPLY CURRENT (µA)
a
b
c
d
a. V
DD
= 5.5V, CODE = 0x155
b. V
DD
= 5.5V, CODE = 0x3FF
c. V
DD
= 2.7V, CODE = 0x155
d. V
DD
= 2.7V, CODE = 0x355
AD7392
V
LOGIC
= 0V TO V
DD
TO 0V
V
REF
= 2.5V
T
A
= 25°C
Figure 14. Supply Current vs. Clock Frequency
60
50
40
30
20
10
0
10 100 1k 10k
01121-018
FREQUENCY (Hz)
PSRR (dB)
T
A
= 25°C
V
DD
= 5V ± 5%
V
DD
= 3V ± 5%
Figure 15. Power Supply Rejection Ratio vs. Frequency
40
30
20
10
0
054321
01121-019
V
OUT
(V)
I
OUT
(mA)
V
DD
= 5V
V
REF
= 3V
CODE = 0x000
Figure 16. IOUT at Zero Scale vs. VOUT
AD7392/AD7393
Rev. C | Page 10 of 20
01121-020
TIME (2µs/DIV)
2µs
AD7392
20mV
CS
(5V/DIV)
V
DD
= 5V
V
REF
= 2.5V
fCLK
= 50kHz
CODE: 0x7F TO 0x80
V
OUT
(5mV/DIV)
Figure 17. Midscale Transition Performance
01121-021
TIME (5µs/DIV)
5µs
5mV
V
DD
= 5V
V
REF
= 2.5V
CS = HIGH
V
OUT
(5mV/DIV)
D0 TO D11
(5V/DIV)
Figure 18. Digital Feedthrough
01121-022
TIME (100µs/DIV)
100µs
1V
V
DD
= 5V
V
REF
= 2.5V
AD7392
V
OUT
(1V/DIV)
CS
(5V/DIV)
Figure 19. Large Signal Settling Time
–3010 100 1k 10k 100k
–25
–20
–15
–10
–5
0
5
01121-023
FREQUENCY (Hz)
GAIN (dB)
V
DD
= 5V
V
REF
= 100mV + 2V
DC
DATA = 0xFFF
Figure 20. Reference Multiplying Bandwidth
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
01234
2.0
01121-024
REFERENCE VOLTAGE (V)
INL (LSB)
AD7392
V
DD
= 5V
CODE = 0x768
T
A
= 25°C
5
Figure 21. Integral Nonlinearity Error vs. Reference Voltage
00 100 200 300 400 500 600
1.2
1.0
0.8
0.6
0.4
0.2
01121-025
HOURS OF OPERATION AT 150°C
NOMINAL CHANGE IN VOLTAGE (mV)
AD7392
SAMPLE SIZE = 50
CODE = 0xFFF
CODE = 0x000
Figure 22. Long-Term Drift Accelerated by Burn-In
AD7392/AD7393
Rev. C | Page 11 of 20
01121-026
TIME (100µs/DIV)
R
L
= 1MΩTO GND
T
A
= 25°C
5V 500mV
I
DD
(µA)
100
50
0
V
OUT
(V)
2
0
SHDN
1
0
2V
V
DD
= 5V
V
REF
= 2.5V
CODE = 0xFFF
AD7392
100
90
10
0%
100µs
Figure 23. Shutdown Recovery Time
10
–55 –35 –15 5 25 45 65 85 105 125
100
1000
AD7392
01121-027
TEMPERATURE (°C)
SUPPLY CURRENT (nA)
V
DD
= 5.5V
V
REF
= 2.5V
SHDN = 0V
Figure 24. Shutdown Current vs. Temperature
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 512 1024 1536 2048 2560 3072 3584 4096
AD7392
01121-002
CODE (Decimal)
DNL (LSB)
V
DD
= 2.7V
V
REF
= 2.5V
T
A
= 25°C
Figure 25. AD7392 Differential Nonlinearity Error vs. Code
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 128 256 384 512 640 768 896 1024
AD7393
01121-003
CODE (Decimal)
DNL (LSB)
V
DD
= 2.7V
V
REF
= 2.5V
T
A
= 25°C
Figure 26. AD7393 Differential Nonlinearity Error vs. Code
AD7392/AD7393
Rev. C | Page 12 of 20
THEORY OF OPERATION
The AD7392/AD7393 comprise a set of pin-compatible, 12-/10-
bit digital-to-analog converters (DACs). These single-supply
operation devices consume less than 100 μA of current while
operating from 2.7 V to 5.5 V power supplies, making them
ideal for battery-operated applications. They contain a voltage-
switched, 12-/10-bit, laser-trimmed DAC; rail-to-rail output op
amps; and a parallel input DAC register. The external reference
input has constant input resistance independent of the digital
code setting of the DAC. In addition, the reference input can be
tied to the same supply voltage as VDD, resulting in a maximum
output voltage span of 0 V to VDD. The parallel data interface
consists of a CS write strobe and 12 data bits (D0 to D11) if
utilizing the AD7392 or 10 data bits (D0 to D9) if utilizing
the AD7393. An RS pin is available to reset the DAC register to
zero scale. This function is useful for power-on reset or system
failure recovery to a known state. Additional power savings are
accomplished by activating the SHDN pin, resulting in a 1.5 μA
maximum consumption sleep mode. While the supply voltage is
on, data is retained in the DAC register to reset the DAC output
when the part is taken out of shutdown (SHDN = 1).
DIGITAL-TO-ANALOG CONVERTERS
The voltage switched R-2R DAC generates an output voltage
that depends on the external reference voltage connected to
the VREF pin according to Equation 1.
N
REF
OUT
D
VV
2
×= (1)
where:
D is the decimal data-word loaded into the DAC register.
N is the number of bits of DAC resolution.
If the 10-bit AD7393 uses a 2.5 V reference, Equation 1
becomes
1024
5.2 D
VOUT ×= (2)
Using Equation 2, the nominal midscale voltage at VOUT is
1.25 V, for D = 512; full-scale voltage is 2.497 V. The LSB
step size is 2.5 × 1/1024 = 0.0024 V.
If the 12-bit AD7392 uses a 5.0 V reference, Equation 1
becomes
4096
D
VV REF
OUT ×= (3)
Using Equation 3, the AD7392 provides a nominal midscale volt-
age of 2.50 V (for D = 2048) and a full-scale VOUT of 4.998 V.
The LSB step size is 5.0 × 1/4096 = 0.0012 V.
AMPLIFIER SECTION
The internal DACs output is buffered by a low power consump-
tion precision amplifier. The op amp has a 60 μs typical settling
time to 0.1% of full scale. There are slight differences in settling
time for negative slew signals vs. positive. Also, negative tran-
sition settling time to within the last 6 LSBs of 0 V has an extended
settling time. The rail-to-rail output stage of this amplifier has
been designed to provide precision performance while operating
near either power supply. Figure 27 shows an equivalent output
schematic of the rail-to-rail amplifier with its N-channel pull-
down FETs that pull an output load directly to GND. The
output sourcing current is provided by a P-channel, pull-up
device that can source current-to-GND terminated loads.
01121-028
P-CH
N-CH
V
DD
V
OUT
AGND
Figure 27. Equivalent Analog Output Circuit
The rail-to-rail output stage provides ±1 mA of output current.
The N-channel output pull-down MOSFET, shown in Figure 27,
has a 35 Ω on resistance that sets the sink current capability
near ground. In addition to resistive load driving capability, the
amplifier also has been carefully designed and characterized for
up to 100 pF capacitive load driving capability.
REFERENCE INPUT
The reference input terminal has a constant input resistance
independent of digital code, which results in reduced glitches
on the external reference voltage source. The high 2.5 MΩ input
resistance minimizes power dissipation within the AD7392/
AD7393 DACs. The VREF input accepts input voltages ranging
from ground to the positive supply voltage VDD. One of the
simplest applications for saving an external reference voltage
source is connecting the REF terminal to the positive VDD
supply. This connection results in a rail-to-rail voltage output
span maximizing the programmed range. The reference input
accepts ac signals as long as they stay within the 0 V < VREF <
VDD supply voltage range. The reference bandwidth and integral
nonlinearity error performance are plotted in Figure 20 and
Figure 21. The ratiometric reference feature makes the AD7392/
AD7393 an ideal companion to ratiometric analog-to-digital
converters (ADCs) such as the AD7896.
AD7392/AD7393
Rev. C | Page 13 of 20
POWER SUPPLY
The very low power consumption of the AD7392/AD7393 is
a direct result of a circuit design that optimizes the CBCMOS
process. By using the low power characteristics of CMOS for the
logic and the low noise, tight-matching of the complementary
bipolar transistors, excellent analog accuracy is achieved. One
advantage of the rail-to-rail output amplifiers used in the AD7392/
AD7393 is the wide range of usable supply voltage. The part is
fully specified and tested for operation from 2.7 V to 5.5 V.
01121-029
5V
POWER SUPPLY
5V
5V
RETURN
FERRITE BEAD:
2 TURNS, FAIR-RITE
#2677006301
TTL/CMOS
LOGIC
CIRCUITS +100µF
ELECT.
+10µF TO 22µF
TAN T.
+0.1µF
CER.
Figure 28. Use Separate Traces to Reduce Power Supply Noise
Whether or not a separate power supply trace is available, gen-
erous supply bypassing reduces supply line induced errors. Local
supply bypassing, consisting of a 10 μF tantalum electrolytic in
parallel with a 0.1 μF ceramic capacitor, is recommended for all
applications (see Figure 29).
01121-030
V
OUT
CS
1
20
19
17, 18
4
3
2
C
*
RS
D0 TO D11
2.7
V
TO 5.5V
V
DD
V
REF
GND
SHDN
AD7392
OR
AD7393
0.1µF
10µF
+
* OPTIONAL EXTERNAL
REFERENCE BYPASS
Figure 29. Recommended Supply Bypassing for the AD7392/AD7393
INPUT LOGIC LEVELS
All digital inputs are protected with a Zener-type ESD protection
structure that allows logic input voltages to exceed the VDD supply
voltage (see Figure 30). This feature is useful if the user is driving
one or more of the digital inputs with a 5 V CMOS logic input
voltage level while operating the AD7392/AD7393 on a 3 V
power supply. If this interface is used, make sure that the VOL
of the 5 V CMOS meets the VIL input requirement of the AD7392/
AD7393 operating at 3 V. See Figure 12 for a graph of digital
logic input threshold vs. operating VDD supply voltage.
01121-031
V
DD
LOGIC
IN
GND
1kΩ
Figure 30. Equivalent Digital Input ESD Protection
To minimize power dissipation from input logic levels that
are near the VIH and VIL logic input voltage specifications, a
Schmitt-trigger design was used that minimizes the input
buffer current consumption compared to traditional CMOS
input stages. Figure 11 is a plot of supply current vs. incremental
input voltage, showing that negligible current consumption
takes place when logic levels are in their quiescent state. The
normal crossover current still occurs during logic transitions.
A secondary advantage of this Schmitt trigger is the prevention
of false triggers that would occur with slow moving logic transi-
tions when a standard CMOS logic interface or opto-isolators
are used. Logic inputs D11 to D0, CS, RS, and SHDN all contain
the Schmitt-trigger circuits.
DIGITAL INTERFACE
The AD7392/AD7393 have a parallel data input. A functional
block diagram of the digital section is shown in Figure 31,
while Table 6 contains the truth table for the logic control
inputs. The chip select pin (CS) controls loading of data from
the data inputs on Pin D11 to Pin D0. This active low input
places the input register into a transparent state allowing the
data inputs to directly change the DAC ladder values. When
CS returns to logic high within the data setup-and-hold time
specifications, the new value of data in the input register are
latched. See Table 6 for a complete listing of conditions.
01121-005
Dx
CS
RS
TO
INTERNAL
DAC SWITCHES
1 OF 12 LATCHES
OF THE
DAC REGISTER
Figure 31. Digital Control Logic
Table 6. Control Logic Truth Table
CS RS DAC Register Function
H H Latched
L H Transparent
↑1 H Latched with new data
X2 L Loaded with all zeros
H ↑1 Latched all zeros
1 ↑ = Positive logic transition.
2 X = Don’t care.
AD7392/AD7393
Rev. C | Page 14 of 20
RESET PIN (RS)
Forcing the asynchronous RS pin low sets the DAC register to
all 0s, so the DAC output voltage is 0 V. The reset function is
useful for setting the DAC outputs to 0 at power-up or after a
power supply interruption. Test systems and motor controllers
are two of many applications that benefit from powering up to a
known state. The external reset pulse can be generated by three
methods:
• The microprocessor’s power-on RESET signal
• An output from the microprocessor
• An external resistor and capacitor
RESET has a Schmitt-trigger input, which results in a clean
reset function when using external resistor-/capacitor-generated
pulses (see Table 6).
POWER SHUTDOWN (SHDN)
Maximum power savings can be achieved by using the power
shutdown control function. This hardware-activated feature is
controlled by the active low input SHDN pin. This pin has a
Schmitt-trigger input that helps desensitize it to slowly changing
inputs. Setting this pin to logic low reduces the internal con-
sumption of the AD7392/AD7393 to nanoamp levels, guaranteed
to 1.5 μA maximum over the operating temperature range. If
power is present at all times on the VDD pin while in shutdown
mode, the internal DAC register retains the last programmed
data value. The digital interface is still active in shutdown so
that code changes can be made that produce new DAC settings
when the device is taken out of shutdown. This data is used
when the part is returned to the normal active state by placing
the DAC back to its programmed voltage setting. Figure 23
shows a plot of shutdown recovery time with both IDD and VOUT
displayed. In the shutdown state, the DAC output amplifier
exhibits an open-circuit high resistance state. Any load that is
connected stabilizes at its termination voltage. If the power
shutdown feature is not needed, the user should tie the SHDN
pin to the VDD voltage to disable this function.
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7392. The
AD7392 is designed to drive loads as low as 5 kΩ in parallel
with 100 pF (see Figure 32). The code table for this operation is
shown in Table 7.
The circuit can be configured with an external reference
plus power supply or powered from a single dedicated regu-
lator or reference depending on the application performance
requirements.
01121-032
1
20 19
17, 18
2.7
V
TO 5.5V
V
DD
GND
AD7392
V
OUT
V
REF
R
R
L
≥5kΩ
C
L
≥100pF
0.1µF
0.01µF 10µF
NOTES
1. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
EXT
REF
Figure 32. AD7392 Unipolar Output Operation
Table 7. Unipolar Code Table
DAC Register No.
Hexadecimal Decimal Output Voltage (V), VREF = 2.5 V
0xFFF 4095 2.4994
0x801 2049 1.2506
0x800 2048 1.2500
0x7FF 2047 1.2494
0x000 0 0
AD7392/AD7393
Rev. C | Page 15 of 20
BIPOLAR OUTPUT OPERATION
Although the AD7393 is designed for single-supply operation,
the output can be easily configured for bipolar operation. A
typical circuit is shown in Figure 33. This circuit uses a clean,
regulated 5 V supply for power, which also provides the circuit’s
reference voltage. Since the AD7393 output span swings from
ground to very near 5 V, it is necessary to choose an external
amplifier with a common-mode input voltage range that extends
to its positive supply rail. The micropower consumption OP196
is designed just for this purpose and results in only 50 μA of
maximum current consumption. Connecting the two 470 kΩ
resistors results in a differential amplifier mode of operation
with a voltage gain of 2, which produces a circuit output span
of 10 V, that is, −5 V to +5 V. As the DAC is programmed from
zero-code 0x000 to midscale 0x200 to full scale 0x3FF, the circuit
output voltage, VO, is set at −5 V, 0 V, and +5 V (minus 1 LSB).
The output voltage, VO, is coded in offset binary according to
Equation 4.
51
512 ×
⎥
⎦
⎤
⎢
⎣
⎡−= D
VO (4)
where D is the decimal code loaded in the AD7393 DAC
register.
Note that the LSB step size is 10/1024 = 10 mV. This circuit
is optimized for micropower consumption including the 470 kΩ
gain setting resistors, which should have low temperature
coefficients to maintain accuracy and matching (preferably the
same resistor material, such as metal film).
If better stability is required, the power supply may be substi-
tuted with a precision reference voltage such as the low dropout
REF195, which can easily supply the circuit’s 162 μA of current,
and still provide additional power for the load connected to VO.
The micropower REF195 is guaranteed to source 10 mA output
drive current, but consumes only 50 μA internally.
If higher resolution is required, the AD7392 can be used with
two additional bits of data inserted into the software coding,
which results in a 2.5 mV LSB step size. Tabl e 8 shows examples
of nominal output voltages (VO) provided by the bipolar
operation circuit application.
01121-033
V
O
C
V
REF
GND
+5
V
OP196
+5V
–5V
BIPOLAR
OUTPUT
SWING
–5V
AD7393
NOTES
1. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
<50µA<100µA
I
SY
<162µ
A
<2µA
470kΩ470kΩ
V
OUT
V
DD
Figure 33. Bipolar Output Operation
Table 8. Bipolar Code Table
DAC Register No.
Hexadecimal Decimal Analog Output Voltage (V)
0x3FF 1023 +4.9902
0x201 513 +0.0097
0x200 512 0.0000
0x1FF 511 −0.0097
0x000 0 −5.0000
AD7392/AD7393
Rev. C | Page 16 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001
070706-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
20
110
11
0.100 (2.54)
BSC
1.060 (26.92)
1.030 (26.16)
0.980 (24.89)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 34. 20-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-20)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AC
13.00 (0.5118)
12.60 (0.4961)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
20 11
10
1
1.27
(0.0500)
BSC
060706-A
45°
Figure 35. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
AD7392/AD7393
Rev. C | Page 17 of 20
ORDERING GUIDE
Model Resolution (Bits) Temperature Range Package Description Package Option
AD7392AN 12 −40°C to +85°C 20-Lead PDIP N-20
AD7392ANZ112 −40°C to +85°C 20-Lead PDIP N-20
AD7392AR 12 −40°C to +85°C 20-Lead SOIC_W RW-20
AD7392AR-REEL 12 −40°C to +85°C 20-Lead SOIC_W RW-20
AD7392ARZ112 −40°C to +85°C 20-Lead SOIC_W RW-20
AD7392ARZ-REEL112 −40°C to +85°C 20-Lead SOIC_W RW-20
AD7393AN 10 −40°C to +85°C 20-Lead PDIP N-20
AD7393AR 10 −40°C to +125°C 20-Lead SOIC_W RW-20
AD7393ARZ110 −40°C to +125°C 20-Lead SOIC_W RW-20
1 Z = RoHS Compliant Part.
AD7392/AD7393
Rev. C | Page 18 of 20
NOTES
AD7392/AD7393
Rev. C | Page 19 of 20
NOTES
AD7392/AD7393
Rev. C | Page 20 of 20
NOTES
©1996–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01121-0-8/07(C)
