PIC16(L)F1847 PIC16(L)F1847 Family Silicon Errata and Data Sheet Clarification The PIC16(L)F1847 family devices that you have received conform functionally to the current Device Data Sheet (DS41453B), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC16(L)F1847 silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A2). For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 3 or PICkitTM 3: 1. 2. 3. 4. Note: Data Sheet clarifications and corrections start on page 6, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: Using the appropriate interface, connect the device to the MPLAB ICD 3 programmer/ debugger or PICkitTM 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC16(L)F1847 silicon revisions are shown in Table 1. SILICON DEVREV VALUES DEVICE ID<13:0>(1),(2) Part Number DEV<8:0> Revision ID for Silicon Revision A2 PIC16F1847 01 0100 100 0 0010 PIC16LF1847 01 0100 101 0 0010 Note 1: 2: The Device ID is located in the configuration memory at address 8006h. Refer to the "PIC16(L)F1847/PIC12(L)F1840 Memory Programming Specification" (DS41439) for detailed information on Device and Revision IDs for your specific device. 2011-2012 Microchip Technology Inc. DS80525B-page 1 PIC16(L)F1847 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Issue Summary Affected Revisions(1) A2 Timer1 Timer0 Gate Source 1.1 Toggle mode works improperly. X Timer1 T1 Gate Toggle mode 2.1 T1 gate flip-flop does not clear. X Oscillator HFINTOSC Ready/ Stable bit 3.1 Bits remained set to `1' after initial trigger. X Oscillator Clock Switching 3.2 Clock switching can cause a single corrupted instruction. X Oscillator Oscillator Start-up Timer (OST) bit 3.3 OST bit remains set. X Enhanced Universal Synchronous Asynchronous Receiver (EUSART) Auto-Baud Detect 4.1 Auto-Baud Detect may store incorrect count value in the SPBRG registers. X Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80525B-page 2 2011-2012 Microchip Technology Inc. PIC16(L)F1847 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A2). 3. Module: Oscillator 3.1 OSCSTAT bits: HFIOFR and HFIOFS When HFINTOSC is selected, the HFIOFR and HFIOFS bits will become set when the oscillator becomes ready and stable. Once these bits are set, they become "stuck", indicating that HFINTOSC is always ready and stable. If the HFINTOSC is disabled, the bits fail to be cleared. 1. Module: Timer1 Work around 1.1 Timer1 Gate Toggle Mode with Timer0 as Gate Source None. Timer1 Gate Toggle mode provides unexpected results when Timer0 overflow is selected as the Timer1 gate source. We do not recommend using Timer0 overflow as the Timer1 gate source while in Timer1 Gate Toggle mode or when Toggle mode is used in conjunction with Timer1 Gate Single-Pulse mode. Work around None. Affected Silicon Revisions A2 X 2. Module: Timer1 2.1 Timer1 Gate Toggle mode When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal. To perform this function, the Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the gate signal. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When working properly, clearing either the T1GTM bit or the TMR1ON bit would also clear the output value of this flip-flop, and hold it clear. This is done in order to control which edge is being measured. The issue that exists is that clearing the TMR1ON bit does not clear the output value of the flip-flop and hold it clear. Affected Silicon Revisions A2 X 3.2 Clock Switching When switching clock sources between INTOSC clock source and an external clock source, one corrupted instruction may be executed after the switch occurs. This issue does not affect Two-Speed Start-up or the Fail-Safe Clock Monitor operation. Work around When switching from an external oscillator clock source, first switch to 16 MHz HFINTOSC. Once running at 16 MHz HFINTOSC, configure IRCF to run at desired internal oscillator frequency. When switching from an internal oscillator (INTOSC) to an external oscillator clock source, first switch to HFINTOSC High-Power mode (8 MHz or 16 MHz). Once running from HFINTOSC, switch to the external oscillator clock source. Affected Silicon Revisions A2 X Work around Clear the T1GTM bit in the T1GCON register to clear and hold clear the output value of the flip-flop. Affected Silicon Revisions A2 X 2011-2012 Microchip Technology Inc. DS80525B-page 3 PIC16(L)F1847 3.3 Oscillator Start-up Timer (OST) bit During the Two-Speed Start-up sequence, the OST is enabled to count 1024 clock cycles. After the count is reached, the OSTS bit is set, the system clock is held low until the next falling edge of the external crystal (LP, XT or HS mode), before switching to the external clock source. 4. Module: Enhanced Universal Synchronous Asynchronous Receiver (EUSART) 4.1 Auto-Baud Detect When using automatic baud detection (ABDEN), on occasion, an incorrect count value can be stored at the end of auto-baud detection in the SPBRGH:SPBRGL (SPBRG) registers. The SPBRG value may be off by several counts. This condition happens sporadically when the device clock frequency drifts to a frequency where the SPBRG value oscillates between two different values. The issue is present regardless of the baud rate Configuration bit settings. When an external oscillator is configured as the primary clock and Fail-Safe Clock mode is enabled (FCMEN = 1), any of the following conditions will result in the Oscillator Start-up Timer (OST) failing to restart: * MCLR Reset * Wake from Sleep * Clock change from INTOSC to Primary Clock Work around This anomaly will manifest itself as a clock failure condition for external oscillators which take longer than the clock failure time-out period to start. When using auto-baud, it is a good practice to always verify the obtained value of SPBRG, to ensure it remains within the application specifications. Two recommended methods are shown below. Work around None. For additional auto-baud information, see Technical Brief TB3069, "Use of Auto-Baud for Reception of LIN Serial Communications Devices: Mid-Range and Enhanced Mid-Range". Affected Silicon Revisions A2 X EXAMPLE 1: METHOD 1 - EUSART AUTO-BAUD DETECT WORK AROUND In firmware, define default, minimum and maximum auto-baud (SPBRG) values according to the application requirements. For example, if the application runs at 9600 baud at 16 MHz then, the default SPBRG value would be (assuming 16-bit/ Asynchronous mode) 0x67. The minimum and maximum allowed values can be calculated based on the application. In this example, a +/-5% tolerance is required, so tolerance is 0x67 * 5% = 0x05. #define SPBRG_16BIT const const const const * * * ABDEN while int int int int *((*int)&SPBRG; DEFAULT_BAUD = 0x0067; TOL = 0x05; MIN_BAUD = DEFAULT_BAUD - TOL; MAX_BAUD = DEFAULT_BAUD + TOL; = 1; (ABDEN); // define location for 16-bit SPBRG value // // // // Default Auto-Baud value Baud Rate % tolerance Minimum Auto-Baud Limit Maximum Auto-Baud Limit // Start Auto-Baud // Wait until Auto-Baud completes if((SPBRG_16BIT > MAX_BAUD)||(SPBRG_16BIT < MIN_BAUD)) { // Compare if value is within limits SPBRG_16BIT = DEFAULT_BAUD); // if out of spec, use DEFAULT_BAUD } * // if in spec, continue using the * // Auto-Baud value in SPBRG * DS80525B-page 4 2011-2012 Microchip Technology Inc. PIC16(L)F1847 EXAMPLE 2: METHOD 2 - EUSART AUTO-BAUD DETECT WORK AROUND Similar to Method 1, define default, minimum and maximum auto-baud (SPBRG) values. In firmware, compute a running average of SPBRG. If the new SPBRG value falls outside the minimum or maximum limits, then use the current running average value (Average_Baud), otherwise use the auto-baud SPBRG value and calculate a new running average. For example, if the application runs at 9600 baud at 16 MHz then, the default SPBRG value would be (assuming 16-bit/ Asynchronous mode) 0x67. The minimum and maximum allowed values can be calculated based on the application. In this example, a +/-5% tolerance is required, so tolerance is 0x67 * 5% = 0x05. #define SPBRG_16BIT const const const const int int int int *((*int)&SPBRG; DEFAULT_BAUD = 0x0067; TOL = 0x05; MIN_BAUD = DEFAULT_BAUD - TOL; MAX_BAUD = DEFAULT_BAUD + TOL; int Average_Baud; int Integrator; * * * Average_Baud = DEFAULT_BAUD; Integrator = DEFAULT_BAUD*15; * * * ABDEN = 1; while (ABDEN); // define location for 16-bit SPBRG value // // // // Default Auto-Baud value Baud Rate % tolerance Minimum Auto-Baud Limit Maximum Auto-Baud Limit // Define Average_Baud variable // Define Integrator variable // Set initial average Baud rate // The running 16 count average // Start Auto-Baud // Wait until Auto-Baud completes Integrator+ = SPBRG_16BIT; Average_Baud = Integrator/16; if((SPBRG_16BIT > MAX_BAUD)||(SPBRG_16BIT < MIN_BAUD)) { // Check if value is within limits SPBRG_16BIT = Average_Baud; // If out of spec, use previous average } else // If in spec, calculate the running { // average but continue using the Integrator+ = SPBRG_16BIT; // Auto-Baud value in SPBRG Average_Baud = Integrator/16; Integrator- = Average_Baud; } * * * Affected Silicon Revisions A2 X 2011-2012 Microchip Technology Inc. DS80525B-page 5 PIC16(L)F1847 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41453B): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Oscillator 5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flag will again become set by hardware. DS80525B-page 6 2011-2012 Microchip Technology Inc. PIC16(L)F1847 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (05/2011) Initial release of this document. Rev B Document (02/2012) Updated Table 1; Added Modules 3 and 4; Other minor corrections. Data Sheet Clarifications: Added Module 1, Oscillator. 2011-2012 Microchip Technology Inc. DS80525B-page 7 PIC16(L)F1847 NOTES: DS80525B-page 8 2011-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620760574 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2011-2012 Microchip Technology Inc. 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