AT89C52-12DM/883 - Atmel Corporation

8-Bit

Microcontroller

with 8 Kbytes

Flash

AT89C52

Features

•Compatible with MCS-51TM Products

•8 Kbytes of In-System Reprogrammable Flas h Me mory

Endura nc e: 1, 00 0 Write/Erase Cycle s

•Full y Stati c Ope ration: 0 Hz to 24 MHz

•Three -Le ve l Prog ram Memory Lock

•256 x 8-Bit Inte rnal RAM

•32 Programmable I/O Lines

•Three 16-Bit Timer/Counters

•Eight In terru pt Sou rce s

•Program ma bl e Seri al Channel

•Low Power Id le and Power Down Modes

(T2) P1.0

(T2 EX) P1.1

P0.0 (AD0)

P1.2

(INT0) P3.2

ALE/PROG

(RD) P3.7 P2.3 (A11)

(TXD) P3.1

EA/VPP

(WR) P3.6 P2.4 (A12)

(RXD) P3.0

P0.7 (AD7)

(T1) P3.5 P2.6 (A14)

RST

P0.6 (AD6)

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

P0.2 (AD2)

P1.3

P0.1 (AD1)

(INT1) P3.3

PSEN

XTAL2 P2.2 (A10)

(T0) P3.4 P2.7 (A15)

XTAL1 P2.1 (A9)

GND P2.0 (A8)

P2.5 (A13)

(SS) P1.4

(MOSI) P1.5

(MISO) P1.6

(SCK) P1.7

Pin Confi gur a ti ons PDIP/Cerdip

Description

The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8

Kbytes of Flash programmable and erasable read only memory (PEROM). The de-

vice is manufactured us ing Atmel’s high dens ity nonvolatile memory tec hnology and

is compatible with the industry standar d 80C51 and 80C52 instruction set and pinout.

The on-chip Flash allows the progr am memory to be repr ogrammed in-system or by

a conventional nonvolatile memory pr ogrammer. By combining a vers atile 8-bit CPU

with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer

which provides a highly flex ible and cost effective solution to many embedded control

applications.

(continued)

INDEX

CORNER

P1.0 (T2)

VCC

P1.1 (T2 EX)

P1.2

P1.3

43 40

18192021

121314151617

3837

3635 33

PSEN

XTAL1

GND

XTAL2

GND

P0.0 (AD0)

ALE/PROG

(RD) P3.7

EA/VPP

(WR) P3.6

(RXD) P3.0

P0.7 (AD7)

P2.6 (A14)

P0.6 (AD6)

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

P0.2 (AD2)

P0.1 (AD1)

(INT0) P3.2

(TXD) P3.1

(T1) P3.5

(INT1) P3.3

(T0) P3.4 P2.7 (A15)

(A11) P2.3

(A12) P2.4

(A10) P2.2

(A9) P2.1

(A8) P2.0

RST

P2.5 (A13)

P1.4

(

SS)

(MOSI) P1.5

(MISO) P1.6

(SCK) P1.7

PQFP/TQFP

P1.0 (T2)

VCC

P1.1 (T2 EX)

P0.0 (AD0)

P1.2

ALE/PROG

(RD) P3.7

XTAL1

EA/VPP

(WR) P3.6

GND

(RXD) P3.0

P0.7 (AD7)

P2.6 (A14)

P0.6 (AD6)

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

P0.2 (AD2)

P1.3

P0.1 (AD1)

PSEN

XTAL2

(INT0) P3.2

(TXD) P3.1

(T1) P3.5

(INT1) P3.3

(T0) P3.4 P2.7 (A15)

(A11) P2.3

(A12) P2.4

(A10) P2.2

(A9) P2.1

(A8) P2.0

RST

INDEX

CORNER

P2.5 (A13)

43 40

65444

25 28

20 24

17 29

P1.4 (

SS)

(MOSI) P1.5

(MISO) P1.6

(SCK) P1.7

PLCC/LCC

0313E

PORT 2 DRIVERS

PORT 2

LATCH

P2.0 - P2.7

FLASH

PORT 0

LATCH

RAM

PROGRAM

ADDRESS

BUFFER

INCREMENTER

PROGRAM

COUNTER

DPTR

RAM ADDR.

INSTRUCTION

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

STACK

POINTER

ACC

TMP2 TMP1

ALU

PSW

TIMING

AND

CONTROL

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

OSC

GND

PSEN

ALE/PROG

EA / V

RST

PORT 0 DRIVERS

P0.0 - P0.7

Block Diagra m

2AT89C52

Pin Desc ription

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an

output port, each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-im-

pedance inputs.

Port 0 can also be configured to be the multiplexed low-or-

der address/data bus during accesses to external pro-

gram and data memory. In this mode, P0 has internal pul-

lups.

Port 0 also receives the code bytes during F lash program-

ming and outputs the code bytes during program verifica-

tion. External pullups are required during program verifica-

tion.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs .

When 1s are written to Port 1 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the

timer/counter 2 external count input (P1.0/T2) and the

timer/counter 2 trigger input (P1.1/T2EX), res pectiv ely, as

shown in the following table.

Port Pin Alternate Functions

P1.0 T2 (external count input to

Timer/Counter 2), clock-out

P1.1 T2EX (Timer/Counter 2 capture/reload

trigger and direction control)

The AT89C52 provides the following standard features : 8

Kbytes of Flash, 256 bytes of RAM, 32 I/O lines , thr ee 16-

bit timer/counters, a six -vector two-level interr upt architec-

ture, a full duplex serial port, on-chip oscillator, and clock

circuitry. In addition, the AT89C52 is designed with static

logic for operation down to zero frequency and supports

two software selectable power saving modes. The Idle

Mode stops the CPU while allowing the RAM, timer/count-

ers, serial port, and interrupt system to continue function-

ing. The Power Down Mode sa ves the RAM contents but

freezes the oscillator , disabling all other chip functions un-

til the next hardware reset.

Description (Continued) Port 1 also receives the low-order address bytes during

Flash programming and program verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs .

When 1s are written to Port 2 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX

@ DPTR). In this application, Port 2 uses strong internal

pullups when emitting 1s. During accesses to external

data memory that us e 8-bit addr esses (MO VX @ RI), Port

2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high- order addres s bits and some

control signals during Flash programming and verific ation.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs .

When 1s are written to Port 3 pins, they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source

current (IIL) because of the pullups.

Port 3 also serves the functions of various special features

of the AT89C51, as shown in the following table.

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0 (external interrupt 0)

P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR (external data memory write strobe)

P3.7 RD (external data memory read strobe)

Port 3 also receives some control signals for Flash pro-

gramming and programming verification.

RST

Reset input. A high on this pin for two machine cycles

while the oscillator is running resets the device.

ALE/PROG

Address Latch Enable is an output pulse for latching the

low byte of the address during accesses to external mem-

ory. This pin is also the program pulse input (PROG) dur-

ing Flash programming.

(continued)

AT89C52

In normal operation, ALE is emitted at a constant rate of

1/6 the oscillator frequency and may be used for external

timing or clocking purposes. Note, however , that one ALE

pulse is skipped during each access to external data

memory.

If desired, ALE operation can be disabled by setting bit 0

of SFR location 8EH. With the bit set, ALE is active only

during a MOVX or MOVC instruc tion. Otherwise, the pin is

weakly pulled high. Setting the A LE-disable bit has no ef-

fect if the microcrontroller is in external execution mode.

PSEN

Program Store Enable is the read s trobe to external pro-

gram memory.

When the AT89C52 is executing code from external pro-

gram memory, PSEN is activated twice each machine cy-

cle, except that two PSEN activations are skipped during

each access to external data memory.

Pin Desc ription (Continued) EA/VPP

External Access Enable. EA must be strapped to GND in

order to enable the device to fetch code from exter nal pro-

gram memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is pr ogrammed, EA will be

internally latched on reset.

EA should be strapped to VCC for internal program execu-

tions.

This pin also receives the 12-volt programming enable

voltage (VPP) during Flas h programming when 12-volt pro-

gramming is selected.

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Table 1. AT89C52 SFR Map and Reset Values

0F8H 0FFH

0F0H B

00000000 0F7H

0E8H 0EFH

0E0H ACC

00000000 0E7H

0D8H 0DFH

0D0H PSW

00000000 0D7H

0C8H T2CON

00000000 T2MOD

XXXXXX00 RCAP2L

00000000 RCAP2H

00000000 TL2

00000000 TH2

00000000 0CFH

0C0H 0C7H

0B8H IP

XX000000 0BFH

0B0H P3

11111111 0B7H

0A8H IE

0X000000 0AFH

0A0H P2

11111111 0A7H

98H SCON

00000000 SBUF

XXXXXXXX 9FH

90H P1

11111111 97H

88H TCON

00000000 TMOD

00000000 TL0

00000000 TL1

00000000 TH0

00000000 TH1

00000000 8FH

80H P0

11111111 SP

00000111 DPL

00000000 DPH

00000000 PCON

0XXX0000 87H

4AT89C52

Data Memor y

The AT89C52 implements 256 bytes of on-c hip RAM. The

upper 128 bytes occupy a parallel address space to the

Special Function Registers. That means the upper 128

bytes have the same addres ses as the SFR space but are

physically separate from SFR space.

When an instruction accesses an internal location above

address 7FH, the address mode used in the instruction

specifies whether the CPU accesses the upper 128 bytes

of RAM or the SFR space. Instructions that use direct ad-

dressing access SFR space.

For example, the following direct addressing instruction

accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirec t addressing acces s the upper

128 bytes of RAM. For example, the following indirect ad-

dressing instruction, where R0 contains 0A0H, accesses

the data byte at address 0 A0H, rather than P2 (whos e ad-

dress is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect ad-

dressing, so the upper 128 bytes of data RAM are avail-

able as stack space.

Special Funct ion Regi sters

A map of the on-chip memory area called the Special

Function Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc-

cupied addresses may not be implemented on the chip.

Read accesses to these addresses will in general return

random data, and write accesses will have an indetermi-

nate effect.

User software should not write 1s to these unlisted loca-

tions, since they may be used in future products to invok e

new features. In that case, the reset or inactive values of

the new bits will always be 0.

Timer 2 Registers Control and status bits are contained

in registers T2CON (shown in Table 2) and T2MOD

(shown in Table 4) for Timer 2. The register pair

(RCAP2H, RCAP2L) are the Capture/Reload registers for

Timer 2 in 16-bit capture mode or 16-bit auto- reload mode.

Interrupt Registers The individual interrupt enable bits

are in the IE register. Two priorities can be set for each of

the six interrupt sources in the IP register.

Table 2. T2CON—Timer/Counter 2 Control Register

T2CON Add ress = 0C8 H Reset Val ue = 000 0 00 00B

Bit Add res sa bl e

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2

Bit76543210

Symbol Function

TF2 Timer 2 ove rfl ow flag set by a Ti me r 2 ove rfl ow an d must be clea red by soft ware . TF 2 will not be set when

either RCLK = 1 or TCLK = 1.

EXF2 Time r 2 ext ern al fla g se t whe n ei ther a capt ure or reload is caus ed by a ne ga ti ve transiti on on T2 EX and

EXEN2 = 1. When Ti me r 2 interrupt is enab le d, EXF 2 = 1 wil l caus e th e CPU t o vect or to the Timer 2

interrupt routine. EXF2 must be cle are d by sof twa re. EXF2 does not cau se an in te rrup t in up/down co un te r

mode (DCEN = 1).

RCLK Receive clo ck ena bl e. Whe n se t, cau se s th e serial port to use Timer 2 ov erf lo w p ul ses fo r its re ceiv e cl oc k in

serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK Transmit cl ock en able . Wh en set , caus es the seri al port to us e Timer 2 over flow puls es for its transmit cl ock

in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on

T2EX if Time r 2 is not be in g us ed to cloc k the se ria l po rt. EXEN2 = 0 causes Ti mer 2 to igno re ev en ts at

T2EX.

TR2 Start/ Sto p co nt rol for Ti me r 2. TR2 = 1 sta rts the timer.

C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer fu nc ti on . C/T2 = 1 for external event counter (falling

edge triggered).

CP/RL2 Captu re/ Reload se le ct . CP/RL2 = 1 causes captu res to occu r on ne ga ti ve transition s at T2EX if EXEN2 = 1.

CP/RL2 = 0 caus es aut omatic relo ad s to occur when Time r 2 ove rfl ows or negat iv e tra ns it io ns occ ur at

T2EX when EXEN2 = 1. Wh en either RCLK o r TCLK = 1, t hi s bit is ign ore d an d the time r is fo rced to

auto-reload on Timer 2 overflow.

AT89C52

Timer 0 and 1

Timer 0 and Timer 1 in the AT89C52 operate the same

way as Timer 0 and Timer 1 in the AT89C51.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as

either a timer or an event counter. The type of operation is

selected by bit C/T2 in the SFR T2CON (shown in Table

2). Timer 2 has three operating modes: capture, auto-re-

load (up or down counting), and baud rate generator. The

modes are selected by bits in T2CON, as shown in Table

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the

Timer function, the TL2 register is incremented every ma-

chine cycle. Since a machine cycle consists of 12 oscilla-

tor periods, the count rate is 1/12 of the oscillator fre-

quency.

In the Counter function, the register is incremented in re-

sponse to a l-to-0 transition at its corresponding external

input pin, T2. In this function, the external input is sampled

during S5P2 of every machine cycle. When the samples

Capture Mode

In the capture mode, two options are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer

or counter which upon overflow sets bit TF2 in T2CON.

This bit can then be used to generate an interrupt. If

EXEN2 = 1, Timer 2 performs the same operation, but a

l-to-0 transition at external input T2EX also causes the

current value in TH2 and TL2 to be captur ed into RCAP2H

and RCAP2L, respectively. In addition, the transition at

T2EX causes bit EXF2 in T2CON to be set. T he E XF2 bit,

like TF2, can generate an interrupt. The capture mode is

illustrated in Figure 1.

Auto-Reload (Up or Down Count er)

Timer 2 can be programmed to count up or down when

configured in its 16-bit auto-reload mode. This feature is

invoked by the DCEN (Down Counter Enable) bit located

in the SFR T2MOD (see Table 4). Upon reset, the DCEN

bit is set to 0 so that timer 2 will default to count up. When

DCEN is set, Timer 2 can count up or down, depending on

the value of the T2EX pin.

Figure 2 shows Timer 2 automatically counting up when

DCEN = 0. In this mode, two options are selected by bit

EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to

0FFFFH and then sets the TF2 bit upon overflow. The

(continued)

OSC

EXF2

T2EX PIN

T2 PIN

TR2

EXEN2

C/T2 = 0

C/T2 = 1 CONTROL

CAPTURE

OVERFLOW

CONTROL

TRANSITION

DETECTOR TIMER 2

INTERRUPT

÷12

RCAP2LRCAP2H

TH2 TL2 TH2

Figure 1. Timer 2 in Capture Mode

show a high in one c ycle and a low in the next cycle, the

count is incremented. The new count value appears in the

which the transition was detected. Since two machine cy-

cles (24 oscillator periods) are required to recognize a 1-

to-0 transition, the maximum count rate is 1/24 of the os-

cillator frequency. To ensure that a given level is sampled

at least once before it changes, the level should be held

for at least one full machine cycle.

Table 3. Timer 2 Operating Modes

RCLK + TCLK CP/RL2 TR2 MODE

0 0 1 16-Bit Auto-Relo ad

0 1 1 16-Bi t Cap ture

1 X 1 B aud R ate Generator

X X 0 (Off)

6AT89C52

OSC

EXF2

TF2

T2EX PIN

T2 PIN

TR2

EXEN2

C/T2 = 0

C/T2 = 1

CONTROL

RELOAD

OVERFLOW

CONTROL

TRANSITION

DETECTOR

TIMER 2

INTERRUPT

÷12

RCAP2LRCAP2H

TH2 TL2

Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)

Table 4. T2MOD—Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = XXXX XX00B

Not Bit Addressable

——————T2OEDCEN

Bit76543210

Symbol Function

— Not implemented, reserved for future use.

T2OE Timer 2 Output Enable bit.

DCEN When set, th is bit allows Timer 2 to be config ure d as an up /down counter.

overflow also causes the timer registers to be reloaded

with the 16-bit value in RCAP2H and RCAP2L. The values

in RCAP2H and RCAP2L are preset by software. If

EXEN2 = 1, a 16-bit reload can be triggered either by an

overflow or by a l-to-0 transition at external input T2EX.

This transition also sets the EXF2 bit. Both the TF2 and

EXF2 bits can generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down,

as shown in Figure 3. In this mode, the T2EX pin controls

the direction of the count. A logic 1 at T2EX makes Timer

2 count up. The timer will overflow at 0FFFFH and set the

TF2 bit. This overflow also causes the 16-bit value in

RCAP2H and RCAP2L to be reloaded into the timer regis-

ters, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer

underflows when TH2 and TL2 equal the values stored in

RCAP2H and RCAP2L. The underflow sets the TF2 bit

and causes 0FFFFH to be reloaded into the timer regis-

ters.

The EXF2 bit toggles whenever Timer 2 overflows or un-

derflows and can be used as a 17th bit of resolution. In this

operating mode, EXF2 does not flag an interrupt.

Auto-Reload (Up or Down Count er) (Continued)

AT89C52

OSC

EXF2

TF2

T2EX PIN

COUNT

DIRECTION

1=UP

0=DOWN

T2 PIN

TR2

CONTROL

OVERFLOW

(DOWN COUNTING RELOAD VALUE)

(UP COUNTING RELOAD VALUE)

TOGGLE

TIMER 2

INTERRUPT

RCAP2LRCAP2H

0FFH0FFH

TH2 TL2

C/T2 = 0

C/T2 = 1

Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)

OSC

SMOD1

RCLK

TCLK

CLOCK

T2EX PIN

T2 PIN

TR2

CONTROL

"1"

"0"

TIMER 1 OVERFLOW

NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12

TIMER 2

INTERRUPT

RCAP2LRCAP2H

TH2 TL2

C/T2 = 0

C/T2 = 1

EXF2

CONTROL

TRANSITION

DETECTOR

EXEN2

Figure 4. Timer 2 in Baud Rate Generator Mode

8AT89C52

Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting

TCLK and/or RCLK in T2CON (Table 2). Note that the

baud rates for transmit and receive can be different if

Timer 2 is used for the r eceiv er or transmitter and T imer 1

is used for the other function. Setting RCLK and/or TCLK

puts Timer 2 into its baud rate generator mode, as shown

in Figure 4.

The baud rate generator mode is similar to the auto-reload

mode, in that a rollover in TH2 causes the Timer 2 regis-

ters to be reloaded with the 16-bit value in registers

RCAP2H and RCAP2L, which are preset by software.

The baud rates in Modes l and 3 are determined by Timer

2’s overflow rate according to the following equation.

Modes 1 and 3 Baud Rates = Timer 2 Overflow Rate

The Timer can be configured for either timer or counter

operation. In most applications, it is configured for timer

operation (CP/T2 = 0). The timer operation is different for

Timer 2 when it is used as a baud rate generator. Nor-

mally, as a timer, it increments every machine cycle (at

1/12 the oscillator frequency). As a baud rate generator,

however, it increments ev ery state time ( at 1/2 the os cilla-

tor frequency). The baud rate formula is given below.

Modes 1 and 3

Baud Rate = Oscillator Frequency

32 x [65536 − (RCAP2H, RCAP2L)]

where (RCAP2H, RCAP2L) is the content of RCAP2H and

RCAP2L taken as a 16-bit unsigned integer.

Timer 2 as a baud rate generator is shown in Figure 4.

This figure is valid only if RCLK or TCLK = 1 in T2CON.

Note that a rollover in TH2 does not set TF2 and will not

generate an interrupt. Note too, that if EXEN2 is set, a l-to-

0 transition in T2EX will set E XF2 but will not cause a re-

load from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when

Timer 2 is in use as a baud rate generator, T2EX can be

used as an extra external interrupt.

Note that when Timer 2 is running (TR2 = 1) as a timer in

the baud rate generator mode, TH2 or TL2 should not be

read from or written to. Under these conditions, the Timer

is incremented every state time, and the results of a read

or write may not be accurate. The RCAP2 registers may

be read but should not be written to, becaus e a write might

overlap a reload and cause write and/or reload errors. The

timer should be turned off (clear TR2) before accessing

the Timer 2 or RCAP2 registers.

OSC

EXF2

P1.0

(T2)

P1.1

(T2EX)

TR2

EXEN2

C/T2 BIT

TRANSITION

DETECTOR

TIMER 2

INTERRUPT

T2OE (T2MOD.1)

÷2 TL2

(8-BITS)

RCAP2L RCAP2H

TH2

(8-BITS)

÷2

Figure 5. Timer 2 in Clock-Out Mode

AT89C52

Programm able Clock O ut

A 50% duty cycle clock can be programmed to come out

on P1.0, as shown in Figure 5. This pin, besides being a

regular I/0 pin, has two alternate functions. It can be pro-

grammed to input the external clock for Timer/Counter 2 or

to output a 50% duty c ycle clock ranging from 61 Hz to 4

MHz at a 16

MHz operating frequency.

To configure the Timer/Counter 2 as a c lock gener ator, bit

C/T2 (T2CON.1) must be cleared and bit T2OE

(T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and

stops the timer.

The clock-out frequency depends on the oscillator fre-

quency and the reload value of Timer 2 capture registers

(RCAP2H, RCAP2L), as shown in the following equation.

Clock−Out Frequency = Oscillator Frequency

4 x [65536 − (RCAP2H, RCAP2L)]

In the clock-out mode, Timer 2 roll-overs will not generate

an interrupt. This behavior is similar to when Timer 2 is

used as a baud-rate generator. It is possible to use Timer

2 as a baud-rate generator and a c lock gener ator simulta-

neously. Note, however, that the baud-rate and clock-out

frequencies cannot be determined independently from

one another since they both use RCAP2H and RCAP2L.

UART

The UART in the AT89C52 operates the same way as the

UART in the AT89C51.

Interrupts

The AT89C52 has a total of six interrupt vectors: two ex-

ternal interrupts (INT0 and INT1), three timer interrupts

(Timers 0, 1, and 2), and the serial port interrupt. These

interrupts are all shown in Figure 6.

Each of these interrupt sources can be individually en-

abled or disabled by setting or clearing a bit in Special

Function Register IE. IE also contains a global disable bit,

EA, which disables all interrupts at once.

Note that Table 5 shows that bit position IE.6 is unimple-

mented. In the AT89C51, bit position IE.5 is also unimple-

mented. User softwar e should not write 1s to these bit po-

sitions, since they may be used in future AT89 products.

Timer 2 interrupt is generated by the logical OR of bits TF2

and EXF2 in register T2CON. Neither of these flags is

cleared by hardware when the service routine is vectored

to. In fact, the service routine may have to determine

whether it was TF2 or EXF2 that generated the interrupt,

and that bit will have to be cleared in software.

(MSB) (LSB)

EA — ET2 ES ET1 EX1 ET0 EX0

Enab le Bi t = 1 en ables th e in terrupt.

Enab le Bi t = 0 di sa bl es the interrupt.

Symbol Position Function

EA IE.7

Disabl es all int errupts. If EA = 0, no

int erru pt is acknowled ge d. If EA = 1,

each in terrupt so urce is ind iv id ually

enabled or disabled by setting or

clearing its enable bit.

— IE.6 Reserved.

ET2 IE.5 Timer 2 inte rrupt enab le bit .

ES IE.4 Seria l Port interru pt enabl e bi t.

ET1 IE.3 Timer 1 inte rrupt enab le bit .

EX1 IE.2 Exte rna l interrupt 1 enable bit.

ET0 IE.1 Timer 0 inte rrupt enab le bit .

EX0 IE.0 Exte rna l interrupt 0 enable bit.

User soft ware should ne ver wri te 1s to unimp le ment ed bit s,

because they may be used in future AT89 products.

Table 5. Interrupt Enable (IE) Register

The Timer 0 and Timer 1 flags, TF0 and TFI, are set at

S5P2 of the cycle in which the timers overflow. The values

are then polled by the circuitry in the next cycle. However,

the Timer 2 flag, TF2, is set at S2P2 and is polled in the

same cycle in which the timer overflows.

IE1

IE0

TF1

TF0

INT1

INT0

TF2

EXF2

Figure 6. Interrupt Sources

10 AT89C52

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,

of an inverting amplifier that can be configured for use as

an on-chip oscillator, as shown in Figure 7. Either a quartz

crystal or ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be

left unconnected while XTAL1 is driven, as shown in Fig-

ure 8. There are no requirements on the duty cycle of the

external clock signal, since the input to the internal clock-

ing circuitry is through a divide-by-two flip-flop, but mini-

mum and maximum voltage high and low time specifica-

tions must be observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on- chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware re-

set, the device normally res umes pr ogram ex ecution fr om

where it left off, up to two machine cycles befor e the inter-

nal reset algorithm takes control. On-chip hardware inhib-

its access to internal RAM in this event, but access to the

port pins is not inhibited. To eliminate the possibility of an

unexpected write to a port pin when idle mode is termi-

nated by a reset, the instruction following the one that in-

vokes idle mode should not write to a port pin or to external

memory.

Power Down Mode

In the power down mode, the oscillator is stopped, and the

instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power down mode is termi-

nated. The only exit from power down is a hardwar e reset.

Reset redefines the SFRs but does not change the on-

chip RAM. The reset should not be activated before VCC

is restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and

stabilize.

XTAL2

XTAL1

GND

EXTERNAL

OSCILLATOR

SIGNAL

Figure 8. External Clock Drive Configuration

C2 XTAL2

GND

XTAL1

Figure 7. Oscillator Connections

Notes: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Cerami c Res on ators

Status of Exte rnal Pins During Idle and P owe r Down

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power Down Internal 0 0 Data Data Data Data

Power Down External 0 0 Float Data Data Data

AT89C52

Progra m Me mory Lock Bits

The AT89C52 has three lock bits that can be left unpro-

grammed (U) or can be programmed (P) to obtain the ad-

ditional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA

pin is sampled and latched during reset. If the device is

powered up without a reset, the latch initializes to a ran-

dom value and holds that value until reset is activated. The

latched value of EA must agree with the current logic leve l

at that pin in order for the device to function properly.

Programming the Flash

The AT89C52 is normally shipped with the on-chip Flash

memory array in the erased state (that is, contents = FFH)

and ready to be programmed. The programming interfac e

accepts either a high-voltage (12-volt) or a low-voltage

(VCC) program enable signal. The low voltage program-

ming mode provides a convenient way to program the

AT89C52 inside the user’s system, while the high-voltage

programming mode is compatible with conventional third

party Flash or EPROM programmers.

The AT89C52 is shipped with either the high-voltage or

low-voltage programming mode enabled. The respective

top-side marking and device signature codes are listed in

the following table.

VPP = 12 V VPP = 5 V

Top-Side Mark AT89C52 AT89C52

xxxx xxxx-5

yyww yyww

Signature (030H)=1EH (030H)=1EH

(031H)=52H (031H)=52H

(032H)=FFH (032H)=05H

The AT89C52 code memory array is programmed byte-

by-byte in either programming mode.

To program any

non-blank byte in the on-chip Flash Memory, the entire

memory must be erased using the Chip Erase Mode.

Programming Algorithm: Before programming the

AT89C52, the address, data and control signals should be

set up according to the Flash programming mode table

and Figures 9 and 10. To program the AT89C52, take the

following steps.

1. Input the desired memory location on the address

lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12 V for the high-voltage program-

ming mode.

5. Pulse ALE/PROG once to program a byte in the Flash

array or the lock bits. The byte-write cycle is self-timed and

typically takes no more than 1.5 ms. Repeat steps 1

through 5, changing the address and data for the entire

array or until the end of the object file is reached.

Data Polling: The AT89C52 features Data Polling to indi-

cate the end of a write cycle. During a write cycle, an at-

tempted read of the last byte written will result in the com-

plement of the written data on PO.7. Once the write cycle

has been completed, true data is valid on all outputs, and

the next cycle may begin. Data Polling may begin any time

after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can

also be monitored by the RDY/BSY output signal. P3.4 is

pulled low after ALE goes high during programming to in-

dicate BUSY. P3.4 is pulled high again when program-

ming is done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed code data can be read

back via the address and data lines for verification. The

lock bits cannot be verified directly. Verification of the lock

(continued)

Lock Bit P r ote ction Modes

Program Lock Bits

LB1 LB2 LB3 Protection Type

1 U U U No program lock features.

2PUU

MOVC instructions executed from external program memory are disabled from

fetching code bytes from internal memory, EA is sampled and latched on reset, and

further programming of the Flash memory is disabled.

3 P P U Same as mode 2, but verify is also disabled.

4 P P P Same as mode 3, but external execution is also disabled.

12 AT89C52

Progra mming Interfa ce

Every code byte in the F lash arr ay can be wr itten, and the

entire array can be erased, by using the appropriate com-

bination of control signals. The write operation cycle is

self-timed and once initiated, will automatically time itself

to completion.

All major programming vendors offer worldwide support

for the Atmel microcontroller series. Please contact your

local programming vendor for the appropr iate software re-

vision.

bits is achieved by observing that their features are en-

abled.

Chip Erase: The entire Flash array is erased electrically

by using the proper combination of control signals and by

holding ALE/PROG low for 10 ms. The code array is writ-

ten with all 1s. The chip erase operation must be executed

before the code memory can be reprogrammed.

Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of

locations 030H, 031H, and 032H, except that P3.6 and

P3.7 must be pulled to a logic low. The values retur ned are

as follows.

(030H) = 1EH indicates manufactured by Atmel

(031H) = 52H indicates 89C52

(032H) = FFH indicates 12 V programming

(032H) = 05H indicates 5 V programming

Programming the Flash (Continued)

Flash Pr ogr a mm i ng Modes

Mode RST PSEN ALE/ EA/

VPP P2.6 P2.7 P3.6 P3.7

PROG

Write Code Data H L H/12V(1) LHHH

Read Code Data H L H H L L H H

Write Lock Bit - 1 H L H/12V HHHH

Bit - 2 H L H/12V H H L L

Bit - 3 H L H/12V H L H L

Chip Erase H L H/12V H L L L

Read Signature

Byte HLH HLLLL

Notes: 1. The signature byte at location 032H designates

whether VPP = 12 V or VPP = 5 V should be used to

enableprogramming.

2. Chip Erase requires a 10 ms PROG pulse.

(2)

AT89C52

Flash Pr ogramm ing and V er if i ca ti on Cha rac teristics

TA = 21°C to 27°C, VCC = 5.0 ± 10%

Symbol Parameter Min Max Units

VPP(1) Programming Enable Voltage 11.5 12.5 V

IPP(1) Programming Enable Current 1.0 mA

1/tCLCL Oscillator Frequency 4 24 MHz

tAVGL Address Setup to PROG Low 48tCLCL

tGHAX Address Hold After PROG 48tCLCL

tDVGL Data Setup to PROG Low 48tCLCL

tGHDX Data Hold After PROG 48tCLCL

tEHSH P2.7 (ENABLE) High to VPP 48tCLCL

tSHGL VPP Setup to PROG Low 10 µs

tGHSL(1) VPP Hold After PROG 10 µs

tGLGH PROG Width 1 110 µs

tAVQV Address to Data Valid 48tCLCL

tELQV ENABLE Low to Data Valid 48tCLCL

tEHQV Data Float After ENABLE 0 48tCLCL

tGHBL PROG High to BUSY Low 1.0 µs

tWC Byte Write Cycle Time 2.0 ms

Note: 1. Only used in 12-volt programming mode.

P2.6

P3.6

P2.0 - P2.4

A0 - A7

ADDR.

OOOOH/1FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

4-24 MHz

A8 - A12 P0

+5V

P2.7

PGM

DATA

PROG

V/V

IH PP

VIH

ALE

P3.7

XTAL 2 EA

RST

PSEN

XTAL 1

GND

VCC

AT89C52

Figure 9. Programming the Flash Memory

P2.6

P3.6

P2.0 - P2.4

A0 - A7

ADDR.

OOOOH/1FFFH

SEE FLASH

PROGRAMMING

MODES TABLE

4-24 MHz

A8 - A12 P0

+5V

P2.7

PGM DATA

(USE 10K

PULLUPS)

VIH

ALE

P3.7

XTAL 2 EA

RST

PSEN

XTAL 1

GND

AT89C52

Figure 10. Verifying the Flash Memory

14 AT89C52

tGLGH

tAVGL

tSHGL

tDVGL tGHAX

tAVQV

tGHDX

tEHSH tELQV

tWC

BUSY READY

tGHBL

tEHQZ

P1.0 - P1.7

P2.0 - P2.4

P3.0

ALE/PROG

PORT 0

LOGIC 1

LOGIC 0

EA/V

P2.7

(ENABLE)

P3.4

(RDY/BSY)

PROGRAMMING

ADDRESS VERIFICATION

ADDRESS

DATA IN DATA OUT

Flash Pr ogr amming and V er ification Waveform s - Low V ol ta ge Mode

tGLGH tGHSL

tAVGL

tSHGL

tDVGL tGHAX

tAVQV

tGHDX

tEHSH tELQV

tWC

BUSY READY

tGHBL

tEHQZ

P1.0 - P1.7

P2.0 - P2.4

P3.0

ALE/PROG

PORT 0

LOGIC 1

LOGIC 0

EA/V

P2.7

(ENABLE)

P3.4

(RDY/BSY)

PROGRAMMING

ADDRESS VERIFICATION

ADDRESS

DATA IN DATA OUT

Flash Progr amming and V erifica ti on Wa ve for m s - Hi gh Vol tage Mode

AT89C52

D.C. Characteristics

The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0 V ± 20%, unless otherwise noted.

Symbol Parameter Condition Min Max Units

VIL Inpu t Low Volt ag e (Except EA) -0.5 0.2 VCC-0.1 V

VIL1 Input Low Voltage (EA) -0.5 0.2 VCC-0.3 V

VIH Inpu t High Voltage (Excep t XTAL 1, RST) 0.2 VCC+0.9 VCC+0.5 V

VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V

VOL Output Low Voltage(1)

(Ports 1,2,3) IOL = 1.6 mA 0.4 5 V

VOL1 Output Low Voltage(1)

(Port 0, ALE, PSEN) IOL = 3.2 mA 0.4 5 V

VOH Output High Voltage

(Ports 1,2,3, AL E, PSEN)

IOH = -60 µA, VCC = 5 V ± 10 % 2.4 V

IOH = -25 µA 0.75 VCC V

IOH = -10 µA 0.9 VCC V

VOH1 Outpu t High Vol ta ge

(Port 0 in External Bus Mo de )

IOH = -800 µA, VCC = 5 V ± 10% 2.4 V

IOH = -300 µA 0.75 VCC V

IOH = -80 µA 0.9 VCC V

IIL Logica l 0 Input Current

(Ports 1,2,3) VIN = 0.45 V -50 µA

ITL Logical 1 to 0 Transition

Current (Ports 1,2,3) VIN = 2 V -6 50 µA

ILI Inpu t Le akage Current

(Port 0, EA) 0.45 < VIN < VCC ±10 µA

RRST Reset Pulldown Resistor 50 300 KΩ

CIO Pin Capacitance Test F req . = 1 MHz, T A = 25°C 10 pF

ICC Power Supply Current Active Mode, 12 MHz 25 mA

Idle Mode, 12 MHz 6.5 mA

Power Down Mode(2) VCC = 6 V 100 µA

VCC = 3 V 40 µA

Operating Temperature...................-55°C to +125°C

Storage Temperature......................-65°C to +150°C

Voltage on Any Pin

with Respect to Ground ................... -1.0 V to +7.0 V

Maximum Operating Voltage ............................6.6 V

DC Output Current.......................................15.0 mA

*NOTICE: Stresses beyo nd those liste d unde r “Absolu te Maxi-

mum Ratings ” may cau se permanent dama ge to th e de vi ce.

This is a stress rating only and functional operation of the

device at these or any other conditions beyond those indi-

cated in the operational sections of this specification is not

implie d. Exposure to abs olute ma xi mu m rating co nd itions

for extended periods may affect device reliability.

Absolute Ma ximum Ra ti ngs *

Notes: 1. Under steady state (non-transient) conditions, IOL

must be externally limited as follows:

Maxi mum IOL per port pin:10 mA

Maxi mum IOL per 8-bit port:

Port 0:26 mA

Ports 1, 2, 3: 1 5 mA

Maximum total IOL for all out put pi ns:7 1 mA

If IOL exceeds the test condition, VOL may exceed the

related specification. Pins are not guaranteed to sink

curre nt greater t ha n th e listed t es t co nd itions .

2. Minimum VCC fo r Power Down is 2 V.

16 AT89C52

External Program and Da ta Memory Characte ristics

Symbol Parameter 12 MHz Oscillator Variable Oscillator Units

Min Max Min Max

1/tCLCL Oscillator Frequency 0 24 MHz

tLHLL ALE Pulse Width 127 2tCLCL-40 ns

tAVLL Address Valid to ALE Low 28 tCLCL-13 ns

tLLAX Address Hold After ALE Low 48 tCLCL-20 ns

tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns

tLLPL ALE Low to PSEN Low 43 tCLCL-13 ns

tPLPH PSEN Pulse Width 205 3tCLCL-20 ns

tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-45 ns

tPXIX Input Instruction Hold After PSEN 0 0 ns

tPXIZ Input Instruction Float After PSEN 59 tCLCL-10 ns

tPXAV PSEN to Address Valid 75 tCLCL-8 ns

tAVIV Address to Valid Instruction In 312 5tCLCL-55 ns

tPLAZ PSEN Low to Address Float 10 10 ns

tRLRH RD Pulse Width 400 6t CLCL-100 ns

tWLWH WR Pulse Width 400 6tCLCL-100 ns

tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns

tRHDX Data Hold After RD 0 0 ns

tRHDZ Data Float After RD 97 2tCLCL-28 ns

tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns

tAVDV Address to Valid Data In 585 9tCLCL-165 ns

tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns

tAVWL Address to RD or WR Low 203 4tCLCL-75 ns

tQVWX Data Valid to WR Transition 23 tCLCL-20 ns

tQVWH Data Valid to WR High 433 7tCLCL-120 ns

tWHQX Data Hold After WR 33 tCLCL-20 ns

tRLAZ RD Low to Address Float 0 0 ns

tWHLH RD or WR High to ALE High 43 123 tCLCL-20 tCLCL+25 ns

A.C. Characteristics

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all

other outputs = 80 pF.

AT89C52

LHLL

LLDV

LLWL

LLAX

WHLH

AVLL

RLRH

AVDV

AVWL

RLAZ

RHDX

RLDV

RHDZ

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA IN INSTR IN

External Data Mem ory Read Cy cle

LHLL

LLIV

PLIV

LLAX

PXIZ

PLPH

PLAZ

PXAV

AVLL

LLPL

AVIV

PXIX

ALE

PSEN

PORT 0

PORT 2

A8 - A15

A0 - A7 A0 - A7

A8 - A15

INSTR IN

External Progr am Memor y Read Cycl e

18 AT89C52

External Cloc k Dr ive

Symbol Parameter Min Max Units

1/tCLCL Oscillator Frequency 0 24 MHz

tCLCL Clock Period 41.6 ns

tCHCX High Time 15 ns

tCLCX Low Time 15 ns

tCLCH Rise Time 20 ns

tCHCL Fall Time 20 ns

CHCX

CLCX

CLCL

CHCL

CLCH

V - 0.5V

0.45V 0.2 V - 0.1V

0.7 VCC

External Cloc k Dr ive Wave forms

LHLL

LLWL

LLAX

WHLH

AVLL

WLWH

AVWL

QVWX

QVWH

WHQX

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA OUT INSTR IN

External Data Memory Cy cle

AT89C52

XHDV

QVXH

XLXL

XHDX

XHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

SET TI

SET RI

VALID VALIDVALID VALIDVALID VALIDVALID VALID

Shift Register Mode Timing Waveforms

0.45V

TEST POINTS

V - 0.5V

0.2 V + 0.9V

0.2 V - 0.1V

AC Testing Input /Out put Wa ve for ms (1)

Note: 1. AC Inputs during testing are driven at V CC - 0.5 V

for a logic 1 and 0.45 V for a logic 0. Timing meas-

uremen ts are ma de at VIH min. for a logic 1 and

VIL max. fo r a logi c 0.

Serial Port Timing: Shift Register Mode Test Condi tions

The values in this table are valid for VCC = 5.0 V ± 20% and Load Capacitance = 80 pF.

Symbol Parameter 12 MHz Osc Variable Oscillator Units

Min Max Min Max

tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs

tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns

tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-33 ns

tXHDX Input Data Hold After Clock Rising Edge 0 0 ns

tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

LOAD+ 0.1V

Timing Reference

Points

LOAD- 0.1V

LOAD

OL+ 0.1V

OL - 0.1V

Float Wavefor ms (1)

Note: 1. For timing purposes, a port pin is no longer floating

when a 100 - mV change from loa d vo lt ag e occu rs. A

port pin begins to float when a 100-mV change from

the loaded VOH/VOL level oc curs.

20 AT89C52

Ordering Information

Speed

(MHz) Power

Supply Ordering Code Package Operation Range

12 5 V ± 20% AT89C52-12AC 44A Commercial

AT89C52-12JC 44J (0°C to 70°C)

AT89C52-12PC 40P6

AT89C52-12QC 44Q

AT89C52-12AI 44A Industrial

AT89C52-12JI 44J (-40°C to 85°C)

AT89C52-12PI 40P6

AT89C52-12QI 44Q

AT89C52-12AA 44A Automotive

AT89C52-12JA 44J (-40°C to 125°C)

AT89C52-12PA 40P6

AT89C52-12QA 44Q

5 V ± 10% AT89C52-12DM 40D6 Military

AT89C52-12LM 44L (-55°C to 125°C)

AT89C52-12DM/883 40D6 Military/883C

AT89C52-12LM/883 44L Class B, Fully Compliant

(-55°C to 125°C)

16 5 V ± 20% AT89C52-16AC 44A Commercial

AT89C52-16JC 44J (0°C to 70°C)

AT89C52-16PC 40P6

AT89C52-16QC 44Q

AT89C52-16AI 44A Industrial

AT89C52-16JI 44J (-40°C to 85°C)

AT89C52-16PI 40P6

AT89C52-16QI 44Q

AT89C52-16AA 44A Automotive

AT89C52-16JA 44J (-40°C to 125°C)

AT89C52-16PA 40P6

AT89C52-16QA 44Q

20 5 V ± 20% AT89C52-20AC 44A Commercial

AT89C52-20JC 44J (0°C to 70°C)

AT89C52-20PC 40P6

AT89C52-20QC 44Q

AT89C52-20AI 44A Industrial

AT89C52-20JI 44J (-40°C to 85°C)

AT89C52-20PI 40P6

AT89C52-20QI 44Q

AT89C52

Package Type

44A 44 Lead, Thi n Pla stic Gull Win g Qua d Flat pa ck (TQFP)

40D6 40 Lead, 0.6 00 " Wi de, Non-Wind owed, Ceramic Dual Inlin e Pac ka ge (Cerdip)

44J 44 Lead, Plasti c J-L ea de d Chi p Carrier (PLCC)

44L 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)

40P6 40 Lead, 0.6 00" Wi de , Pla stic Dual Inlin e Pac kage (PDIP)

44Q 44 Lead, Plastic Gul l Wing Quad Flatp ack (PQFP)

Ordering Information

Speed

(MHz) Power

Supply Ordering Code Package Operation Range

24 5 V ± 20% AT89C52-24AC 44A Commercial

AT89C52-24JC 44J (0°C to 70°C)

AT89C52-24PC 44P6

AT89C52-24QC 44Q

AT89C52-24AI 44A Industrial

AT89C52-24JI 44J (-40°C to 85°C)

AT89C52-24PI 44P6

AT89C52-24QI 44Q

22 AT89C52