HD6433045VTF - Renesas Technology / Hitachi Semiconductor

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April 1, 2003

To all our customers

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Hitachi Single-Chip Microcomputer

H8/3048 Series

H8/3048

HD6473048, HD6433048

H8/3047

HD6433047

H8/3045

HD6433045

H8/3044

HD6433044

H8/3048F-ZTAT™

H8/3048F

HD64F3048

Hardware Manual

ADE-602-073E

Rev. 6.0

9/3/2002

Hitachi, Ltd.

The revision list can be viewed directly by 

clicking the title page.

The revision list summarizes the locations of 

revisions and additions. Details should always 

be checked by referring to the relevant text.

Cautions

1. Hitachi neith er warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Hitachi bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demand s especially high quality and reliability or where its failure or malfu nction may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that th e product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Hitachi bears no r e sponsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures su ch as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi pro duc t.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor pro duct s .

Rev. 6.0, 09/02, page iii of xxxii

Preface

The H8/3048 Series is a series of high-performance microcontrollers that integrate system

supporting functions together with an H8/300H CPU core.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a

concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address

space.

The on-chip supporting functions include ROM, RAM, a 16-bit in tegrated timer unit (ITU), a

programmable tim ing pattern controller (TPC), a watchdog timer (WDT), a serial communication

interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller

(DMAC), a refresh controller, and other facilities. Of th e two SCI channels, one has been

expanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added to

reduce power consumption in battery-powered applications: individual modules can be placed in

standby, and th e frequency of the system clock supplied to the chip can be divided down under

software control.

The address space is divided into eight areas. The data bus width and access cycle length can be

selected independently in each area, simplifying the connection of different types of memory.

Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width and

address space size.

With these features, the H8/3048 Series can be used to implement compact, high-performance

systems e asily.

In addition to its mask ROM versions, the H8/3048 Series has a ZTAT™*1 version with user-

programmable on -chip PROM and an F-ZTAT™*2 version with on-chip flash memory that can be

programmed on-board. These versions enable users to respond quickly and flexib ly to changing

application specifications.

The on-chip emulator (E10T) is installed on the H8/3048F-ONE in the H8/3048 series

microcomputer. Refer to the H8/3048F-ONE Hardware Manual for details.

This manua l describes the H8/3048 Series hardware. For details o f the instruction set, refer to the

H8/300H Series Programming Manual.

Notes: *1 ZTAT™ (Zero Turn-Around-Time) is a trademark of Hitachi, Ltd.

*2 F-ZTAT™ (Flexible ZTAT) is a trademark of Hitachi, Ltd.

Rev. 6.0, 09/02, page iv of xxxii

Rev. 6.0, 09/02, page v of xxxi i

List of Items Revised or Added for This Version

Section Page Descriptions

All Description of H8/3048F-ONE deleted.

Comparison of H8/3048

Series Product

Specifications

xvii,

xviii Description amended.

Hardware

Manual H8/3048 Series

(Rev. 6.0) H8/3048F-ONE

(Rev. 1.0)

ROM Type ZTAT Mask ROM F-ZTAT

Model Type H8/3048 H8/3048 mask ROM version

H8/3047 mask ROM version

H8/3045 mask ROM version

H8/3044 mask ROM version

H8/3048F H8/3048F-ONE

Model Spec PROM model Mask ROM model Dual power supply,

flash memory is

installed

Single power supply,

flash memory installed,

internal step-down,

high-speed operation

model

Refer to 1.4,

Differences between

H8/3048F and

H8/3048F-ONE.

Refer to 1.4.3,

Differences between

H8/3048F and

H8/3048F-ONE.

Model Type No. HD6473048 HD6433048

HD6433047

HD6433045

HD6433044

HD64F3048 HD64F3048B

Pin Assignment Refer to figure 1.2, Pin Arrangement of H8/3048ZTAT, H8/3048

Mask ROM Version, H8/3047 Mask ROM Version, H8/3045 Mask

ROM Version, H8/3044 Mask ROM Version, and H8/3048F

(FP-100B or TFP-100B, Top View), in section 1.

5-V operation models

have a V

C L

pin and an

external capacitor must

be connected.

Refer to figure 1.3,

H8/3048F-ONE Pin

Arrangement (FP-100B

or TFP-100B, Top

View), in section 1.

RAM Capacity 4 kbytes H8/3048: 4 kbytes

H8/3047: 4 kbytes

H8/3045: 2 kbytes

H8/3044: 2 kbytes

4 kbytes 4 kbytes

Hardware

Manual H8/3048 Series

(Rev. 6.0) H8/3048F-ONE

(Rev. 1.0)

ROM Type ZTAT Mask ROM F-ZTAT

ROM Capacity 128 kbytes H8/3048: 128 kbytes

H8/3047: 96 kbytes

H8/3045: 64 kbytes

H8/3044: 32 kbytes

128 kbytes 128 kbytes

Flash Memory — — Refer to section 19,

ROM (H8/3048F). Refer to section 18,

Flash Memory

(H8/3048F-ONE Single

Power Supply).

Clock Pulse

Generator Refer to section 20, Clock Pulse Generator. Refer to section 19,

Clock Pulse Generator.

Refer to section 21, Power-Down State. Refer to section 20,

Power-Down State.

Power-Down

State

Clock oscillator settling time: Waiting time of up to 131072 states Clock oscillator settling

time: Waiting time of up

to 262144 states

Refer to table 22.1, Electrical Characteristics of H8/3048 Series

Products, in section 22. Refer to table 21.1,

Electrical

Characteristics of

H8/3048 Series

Products, in section 21.

Electrical

Characteristics

(Clock Rate)

1 to 18 MHz 1 to 16 MHz 5 V operation models:

2 to 25 MHz,

3 V operation models:

2 to 25 MHz.

List of Registers Refer to table B.1, Comparison of H8/3048 Series Internal I/O Register Specifications, in

appendix B.

Refer to appendix B.1, Addresses.

Notes on Usage — — — Refer to section 1.4,

Notes on H8/3048F-

ONE (Single Power

Supply).

On-chip

Emulator (E10T) — — — On-chip emulator

(E10T)

Rev. 6.0, 09/02, page vi of xxxii

Section Page Descriptions

1.1 Overview

Table 1.1 Featur es

2 to 6 Feature of CPU, memory, and product lineup: Description of H8/3048F-ONE deleted.

CPU description added

(also usable as sixteen 8-bit registers + eight 16-b it registers or eigh t 32-b it registers)

1.2 Block Diagram

Figure 1.1 Block

Diagram

7 Description of H8/3048F-ONE deleted.

1.3.1 Pin Arrangement

Table 1.2 Compari s on

of H8/3048 Series Pin

Arrangements

Figure 1.2 Connection of

Pin 1

8 Description of H8/3048F-ONE deleted.

Table 1.2

Description of H8/3048F-ONE deleted.

Figure 1.2

Deleted.

1.3.1 Pin Arrangement

Figure 1.2 Pin

Arrange m ent of

H8/3048ZTAT, H8/3048

Mask ROM Version,

H8/3047 Mask ROM

Version, H8/3045 Mask

ROM Version, H8/3044

Mask ROM Version, and

H8/304 8F (FP-100B or

TFP-10 0B , Top View)

9Note

Description of FWE terminal deleted.

Figure 1.3(2)

Arrange m ent (FP-100B

or TFP-1 00B , To p View)

— Deleted.

1.3.2 Pin Assignments in

Each Mode

Table 1.3 Pin

Assignments in Each

Mode (FP -10 0B or TFP-

100B)

10, 14 Pin No. 1 and 10: Description deleted “Flash memory version with single power supply”

Notes: Description of *4 am en de d, *3 and *4 deleted.

*4For the H8/3048 ZTAT version, H8/3048F version, H8/3048 mask ROM version,

H8/3047 mask ROM version, H8/3045 mask ROM version, and H8/3044 mask

ROM version, this pin is used as the RESO terminal .

1.3.3 Pin Functions

Table 1.4 Pin Functi ons

15 to 19 Description of H8/3048F-ONE deleted.

The following types of description deleted.

Internal step-down pin and system control of FWE pin

Notes deleted.

1.4 Notes on H8/304 8F -

ONE (Single Power Supply) — Deleted.

1.5 Setting Oscillation

Settling Wait Time — Deleted.

1.6 Caution on Crystal

Resonator Connection — Deleted.

1.4 Differences between

H8/304 8F an d H8/3048F-

ONE

20 to 23 Newly added.

Rev. 6.0, 09/02, page vii of xxxi i

Section Page Descriptions

2.1.1 Features 25, 26 High-speed oper ati o n: Descri pti on of H8 /3 04 8F -ONE del ete d.

• Maximum clock frequency: 25MHz description deleted.

• The following description deleted.

— 8/16/32-bit register-register add/subtract: 80 ns @ 25 MHz

— 8 - 8-bit register-register multiply: 560 ns @ 25 MHz

— 16 ÷ 8-bit register-register divide: 560 ns @ 25 MHz

— 16 - 16-bit register-register multiply: 880 ns @ 25 MHz

— 32 ÷ 16 -bit re gi st er- re giste r di vide : 880 ns @ 25 MHz

2.7.2 Effective Address

Calculation

Table 2.13 Effective

Address Calculation

56 Description of normal mode added.

• N or mal mode

23 8 7

H'0000

op abs

abs

16 1515 Memory

contents

H'00

3.2 Mode Control Register

(MDCR) 66 Note delete d.

3.3 System Control

2. For the H8/3048F-ONE version deleted.

4.2.2 Reset Sequence 84 Description of Flash memory version deleted.

For the flash memory version with single power supply (H8/3048F-ONE), hold the

RES pin low for at least 20 system clock (

) cycles.

4.3 Interrupts 88 Note deleted.

5.1.1 Features 91 Note deleted.

5.1.3 Pin Configuration

Table 5.1 Interrupt Pins

93 Note delete d.

5.3.1 External Interrupts

NMI

105 Notes deleted.

5.4.1 Interrupt Handling

Process 110 Note del ete d.

5.5.4 Usage Notes on

External Interrupts 118 Descript ion amended.

The IRQnF flag specification calls for the flag to be cleared by writing 0 to it after it has

been read while set to 1. However, it is possible for the IRQnF flag to be cleared by

mistake simply by writing 0 to it, irrespective of whether it has been read while set to 1,

with the result that interrupt exception handling is not executed. This occurs when the

following conditions are fulfilled.

• Setting conditions

1. Multiple external interrupts (IRQa, IRQb) are being used.

2. Different clearing methods are being used: clearing by writing 0 for the IRQaF flag,

and clearing by hardware for the IRQbF flag.

3. A bit manipulation instruction is used on the IRQ status register to clear the IRQaF

flag, or else ISR is read as a byte unit, the IRQaF flag bit is cleared, and the values

read in the other bits are written as a byte unit.

Rev. 6.0, 09/02, page viii of xxxi i

Section Page Descriptions

5.5.4 Usage Notes on

External Interrupts

Countermeasure

120 Descript ion amended.

Countermeasure 1: When clears IRQaF flag, do not use the bit manipulation

instruction, read the ISR in bytes. Then write a value in bytes whic h sets IRQnF flag to

0 and other bits to 1.

6.1.1 Features 123 Description amended.

• Bus arbitration function

— A built-i n bus ar bite r arbitrates the bus right to the CPU, DMAC, refresh

controlle r, or an ext er nal bus ma ste r.

6.3.6 Interconnections with

Memory (Example)

Figure 6.18

Interconnections with

Memory (Example)

152 Descript ion amended.

EPROM

A to A

19 1 A to A

I/O to I/O

9.1 Overview

Table 9.1 Port Functi o ns

259,

260 Description amended and deleted.

Port 8

Description amended

Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

DDR = 0: generic input

DDR = 1 (after reset):

output

Generic

input/

output

/ S

input,

output, and generic input

DDR = 0 (after reset): generic input

DDR = 1:

output

Port 8 • 5-bit I/O port

• P8

to P8

have Schmitt

inputs

/ /

0 0

input, output, and generic input/output

input and

generic

input/

output

Port A

Descripti on deleted.

• Schmitt inputs output

Port B

Description amended

PB6/TP14/DREQ0/CS7

9.7.2 Register Descriptions

Table 9.11 Port 6 Pin

Fun ctions i n Modes 1 to 6

281 Description of pin amended.

P60/WAIT

9.11.1 Overview

Figure 9.10 Port A Pin

Configuration

295 Descript ion amended.

Port A: Output deleted

PA6/TP6/TIOCA2/A21/CS4

PA5/TP5/TIOCB1/A22/CS5

PA4/TP4/TIOCA1/A23/CS6

Pin function in modes 3, 4, and 6: Output added

A20 (output)

Rev. 6.0, 09/02, page ix of xxxii

Section Page Descriptions

9.11.3 Pin Functions

Table 9.19 Port A Pin

Functions

298,

300,

303

PA7/TP7/TIOCB2/A20

ITU channel 2 settings amended.

Mode 1, 2, 5, 7 3, 4, 6

ITU

channel 2

settings (1) in table

below (2) in table below —

DDR —011—

NDER7 —— 01—

input PA

output TP

outputPin function TIOCB

output TIOCB

input*

output

Note: * TIOCB

input when IOB2 = 1 and PWM2 = 0.

PA5/TP5/TIOCB1/A22/CS5

Description amended.

CS5 output

PA1/TP1/TCLKB/TEND1

Pin function amended.

DMAC

channel 1

settings

(1) in table

below (2) in table

below

DDR —011

NDER1 —— 01

output PA

input PA

output TP

outputPin function

TCLKB input*

Note: *TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and

TPSC0 = 1 in any of TCR4 to TCR0.

PA0/TP0/TCLKA/TEND0

Pin function amended.

DMAC

channel 0

settings

(1) in table

below (2) in table

below

DDR —011

NDER0 —— 01

output PA

input PA

output TP

outputPin function

TCLKA input*

Note: *TCLKA input when MDF = 1 in TMDR, or when TPSC2 = 1 and TPSC1 = 0 in

any of TCR4 to TCR0.

10.2.4 Timer Function

Control Register (TFCR) 332 Description amended.

When these bits select complementary PWM mode or reset-synchronized PWM

mode, they take pr ece dence over the setti ng of the PWM mo de bits (P WM 4 and

PWM3) in TMDR. Settings of complementary PWM mode or re set-synchronized PWM

mode and settings of timer sync bits SYNC4 and SYNC3 in TSNC are valid

simultaneously, however, when complementary PWM mode is selected, channels 3

and 4 must not be synchronized (do not set bits SYNC3 and SYNC4 both to 1 in

TSNC).

12.1.1 Features 435 Description of H8/3048F-ONE amended.

• Watchdog timer reset signal resets the entire chip internally, and can also be output

externally.

12.1.3 Pin Configuration

Table 12.1 WDT Pin

436 Description of H8/3048F-ONE deleted.

12.2.3 Reset Control/

Status Register (RSTCSR) 440 Description of H8/3048F-ONE deleted.

Rev. 6.0, 09/02, page x of xxxi i

Section Page Descriptions

12.3.1 Watchdog Timer

Operation 443 Description of H8/ 3048F-ON E deleted.

13.2.8 Bit Rate Register

(BRR)

Table 13.3 Examples of

Bit Rates and BRR

Settings in Asynchronous

Mode

Table 13.4 Examples of

Bit Rates and BRR

Settings in Synchronous

Mode

Table 13.5 Maximum Bit

Rates for Various

Frequencies

(Asynchr ono us Mo de )

Table 13.6 Maximum Bit

Rates with External Clock

Input (Asynchronous

Mode)

Table 13.7 Maximum Bit

Rates with External Clock

Input (Synchronous

Mode)

469,

470,

472,

473

Table am end ed .

Description of 20 and 25 MHz deleted.

13.3.2 Operation in

Asynchronous Mode

• Receiving Serial Data

(Asynchr ono us Mo de )

Figure 13.7 Sample

Flowchart for

Receiving Serial Data

(1)

482 Descript ion amended.

∨∨

PER FER

ORER = 1?

13.3.3 Multiprocessor

Communication

Trans mitti n g and

Receiving Data

• Receiving

Multiprocessor Serial

Data

Figure 13.12

Sample Flowchart

for Rec eiving

Multiprocessor

Serial Data (1)

489 Descript ion amended.

FER ORER = 1∨

Rev. 6.0, 09/02, page xi of xxxii

Section Page Descriptions

13.3.4 Synchronous

Operation

Trans mitti n g and

Receiving Data

• Transmitting Serial

Data (Synchron ous

Mode)

Figure 13.16

Sample Flowchart

for Serial

Transmitting

494 Description of 1 amended.

1. SCI initialization: the transmit data output function of the TxD pin is selected

automatically.

13.5 Usage Notes

Restrictions on Usage of

the Serial Clock

503 Descript ion amended.

When transmitting data using an external clock as the serial clock, an interval of at

least 5 states is necessary between clearing the TDRE bit in SSR and the Start (falling

edge) of the first transmit clock pulse corresponding to each frame (see figure 13.22).

This condition is also needed for continuous transmission. If ti is not fulfilled,

operational error will occur.

14.3.5 Clock

Table 14.5 Bit Rates

(bits/s) for Different BRR

Settings (when n = 0)

Table 14.6 BRR

Settings for Typical Bit

Rate (bits/s) (when n = 0)

520,

521 Description of 20 and 25 MHz deleted.

15.1.1 Features 533 • High-speed conversion

Description of 18MHz amended and 25MHz deleted

Conversion time: Minimum 7.45 µs per channel (with 18 MHz system clock)

15.1.4 Register

Configuration

Table 15.2 A/D

Converter Registers

536 Description of H8/3048F-ONE deleted.

Initial value of H'FFE9: H'7E deleted.

Notes: *4 deleted.

15.2.3 A/D Control

15.6 Usage Notes

7. A/D Conversion

Accuracy Definitions: A/D

conversi on accu ra cy in

the H8/3048 Series is

defined as follows:

550 Descript ion amended.

• Offset error

Deviation from ideal A/D conversion characteristic of analog input voltage required

to raise digit al out put from minimu m v olta ge val u e B' 000 00 00 000 to B'0000000001

(figure 15.10)

• Full-scale error

Deviation from ideal A/D conversion characteristic of analog input voltage required

to raise digit al out put fr om B'1111111110 to B '1 1111111 11 (fig ur e 15.10)

16.1.1 Features 555 Output voltage amended.

• Output voltage: 0 V to 255/256 * VREF

18.1 Overview

Table 18.1 Operating

Mode and RO M

567 Note: Description of H8/3048F-ONE Hardware Manual (Rev. 1.0) added.

18.4 Notes on Ordering

Mask ROM Version Chip 578 Newly added.

Rev. 6.0, 09/02, page xii of xxxi i

Section Page Descriptions

19.8 Flash Memory

Progra mming and Erasi n g

Precautions (Dual-Power

Supply)

(1) Prog ram with the

specified volt ages and

timing.

(7) If the watchdog timer

generates a reset output

signal when 12 V is not

applied, the rise and fall

of the reset output

waveform will be delayed

by any decoupling

capacitors connected to

the VPP pin.

Figure 19.25 VPP

Power Supply Circuit

Design (Example)

(8) Notes concerning

mounting board

development—handling

of VPP and mode MD2

pins

Figure 19.26 Example

of Mounting B oard

Design for the

H8/3048F-ZTAT with

the Dual-Power Supply

641,

645,

647

Description of H8/3048F-ONE deleted.

Section 20 Flash Memory

(H8/3048F-ONE: Single

Power Supply)

— Deleted.

20.2.1 Connecting a

Crystal Resonator

Figure 20.2 Connection

of Crystal Resonator

(Example)

653 Description added.

CL1 = CL2 = 10 pF to 20 pF

20.2.1 Connecting a

Crystal Resonator

Circuit Configuration

Table 20.1 Damping

Resistance Value

Table 20.2 External

Capacitance Values

653 Description of 20MHz deleted.

Table 20. 1

• H8/3048F-ONE description and damping resistance value of 18 < f ≤ 25 deleted.

• Damping resistance value amended.

4 < f ≤ 8

• N ote am en de d.

A crystal resonator between 2 MHz and 18 MHz can be used. If the chip is to be

operated at less than 2 MHz, the on-chip frequency divider should be used. (A

crystal resonator of less than 2 MHz cannot be used.)

Table 20. 2

Deleted.

20.2.1 Connecting a

Crystal Resonator

Table 20.2 Crystal

Resonator Parameters

654 Description of 20 MHz deleted.

Rev. 6.0, 09/02, page xiii of xxxi i

Section Page Descriptions

20.2.2 External Clock Input

Circuit Configuration

655 Description added.

An external clock signal can be input as shown in the examples in figure 20.5. The

external clock is input from the EXTAL pin. If the XTAL pin is left open, the stray

capacita nce sh ould not exce ed 10 pF .

20.2.2 External Clock Input

External Clock

Table 21. 4(1 ) Cl ock

Timing for H8/3048F-

ONE

— Ta bl e dele t ed .

20.2.2 External Clock Input

External Clock

Table 20.3 Clock Timing

656 Descript ion of note *2 deleted.

20.5.3 Usage Notes

Table 20.5 Comparison

with the Clock Frequency

Ranges in the H8/3048

Series

659 Descriptions of H8/3048F-ONE and 3.0 to 3.6 V specification deleted.

21.2.1 System Control

Bits 6 to 4—Standby

Timer Select (STS2 to

STS0)

664 Descript ion amended.

Line 4

If an external clock is used, any value may be selected.

21.2.1 System Control

2. For H8/304 8F-ONE,

select the setting so that

the waiting time is 100 µs

or more acco rding to the

clock frequency.

— Description deleted.

21.4.3 Selection of Waiting

Time for Exit from Software

Standby Mo de

Crystal Resonator

External Clock

668 Description of H8/3048F-ONE deleted.

Table 22. 3(2 ) Cl ock

Frequency and Waiting

Time for Clock to Settle

— Ta bl e dele t ed .

Section 22 Electrical

Characteristics

Table 22.1 Electrical

Characteristics of

H8/3048 Series Products

675,

676 Descripti on of power supply voltage amended.

3 V operation model: –0.3 to +4.6

*5 note added.

22.1.3 AC Characteristics

Figure 22.3 Output Load

Circuit

690 Description of 5 V deleted.

22.2.3 AC Characteristics

Figure 22.6 Output Load

Circuit

706 Description of 5 V deleted.

Rev. 6.0, 09/02, page xiv of xxxii

Section Page Descriptions

22.2.4 A/D Conversion

Characteristics

Table 22. 18 A/D

Converter Characteristics

707 Conversion time amended.

Condition A Condition C

8 MHz 16 MHz

Item Min Typ Max Min Typ Max Unit

Resolution 10 10 10 10 10 10 bits

Conversion time 16.75 —— 8.375 ——µs

Analog input capacitance ——20 ——20 pF

——10*1——10*3

Permissible signal-source

impedance ——5*2——5*4

kΩ

Nonlinearity error ——±6.0 ——±3.0 LSB

Offset error ——±4.0 ——±2.0 LSB

Full-scale error ——±4.0 ——±2.0 LSB

Quantization error ——±0.5 ——±0.5 LSB

Absolute accuracy ——±8.0 ——±4.0 LSB

Notes: *1 The value is for 4.0 ≤ AVCC ≤ 5.5.

*2 The value is for 2.7 ≤ AVCC < 4.0.

*3 The value is for φ ≤ 12 MHz.

*4 The value is for φ > 12 MHz.

23.3 Electrical

Characteristics of

H8/304 8F -ONE (Si ngl e-

Power Supply)

— Deleted.

Appendix B Internal I/O

Table B.1 Comparison

of H8/3048 Series

Internal I/O Register

Specifications

753 Description of H8/3048F-ONE deleted.

B.2 Addresses

(For H8/3048F-ONE) — Deleted.

B.2 Function

FLMCR

779 Description of H8/3048F-ONE deleted.

B.2 Function

FLMCR 1

FLMCR (FLMCR2)

— Deleted.

B.2 Function

EBR1

780 Description of H8/3048F-ONE deleted.

B.2 Function

EBR

— Deleted.

B.2 Function

EBR2

781 Description of H8/3048F-ONE deleted.

B.2 Function

RAMCR (H'47)

— Deleted.

B.2 Function

RAMCR (H'48)

782 Description of H8/3048F-ONE deleted.

B.2 Function

RSTCSR

811 Description of H8/3048F-ONE deleted.

B.2 Function

ADCR

835 Description of H8/3048F-ONE deleted.

Rev. 6.0, 09/02, page xv of xxxii

Section Page Descriptions

D.1 Port States in Each

Mode

Table D.1 Port States

867,

869 Description amended.

Pin Name Mode Reset

φ—Clock output

RESO *2— T*2

L*4

P17 to P101 to 4 L

5, 6 T

P27 to P201 to 4 L

5, 6 T

PA7

3, 4, 6

1, 2, 5, 7 T

Appendix E Timing of

Transiti on to and Rec ove ry

from Hardware Standby

Mode

Timing of Tr ansi ti on to

Hardware Standby Mode

873 Description added.

≥ 10t

cyc

≥ 0 ns

Appendix F Product Code

Lineup

Table F.1 H8/3048

Series Product Code

Lineup

874 Description of H8/3048F-ONE deleted.

Rev. 6.0, 09/02, page xvi of xxxii

Rev. 6.0, 09/02, page xvii of xxxii

Comparison of H8/3048 Ser i es Product Specifications

There are seven members of the H8/3048 Series; the H8/3048F-ZTAT (H8/3048F*1, H8/3048F-

ONE*2), H8/3048ZTAT, H8/3048 mask ROM version, H8/3047 mask ROM version, H8/3045

mask ROM version, and H8/3044 mask ROM version.

The specifications of each model is compared below.

Notes: *1 H8/3048F has dual power supply with flash memory installed.

*2 H8/3048F-ONE has single power supply with flash memory and E10T installed.

Refer to the H8 /3 048F-ONE Hardware Manual (revision 1) f or d etails.

Hardware

Manual H8/3048 Series

(Rev. 6.0) H8/3048F-ONE

(Rev. 1.0)

ROM Type ZTAT Mask ROM F-ZTAT

Model Type H8/3048 H8/3048 mask ROM version

H8/3047 mask ROM version

H8/3045 mask ROM version

H8/3044 mask ROM version

H8/3048F H8/3048F-ONE

Model Spec PROM model Mask ROM model Dual power supply,

flash memory is

installed

Single power supply,

flash memory inst al l ed,

internal step-down,

high-speed operati on

model

Refer to 1.4,

Differences between

H8/3048F and

H8/3048F-ONE.

Refer to 1.4.3,

Differences between

H8/3048F and

H8/3048F-ONE.

Model Type No. HD6473048 HD6433048

HD6433047

HD6433045

HD6433044

HD64F3048 HD64F3048B

Pin Assignment Refer to figure 1.2, Pin Arrangement of H8/3048ZTAT, H8/3048

Mask ROM Version, H8/3047 Mask ROM Version, H8/3045 Mask

ROM Version, H8/3044 Mask ROM Version, and H8/3048F

(FP-100B or TFP-100B, Top View), in section 1.

5-V operation models

have a VCL pin and an

external capacitor must

be connected.

Refer to figure 1. 3,

H8/3048F-ONE Pin

Arrangement (FP-100B

or TFP-100B, Top

View), i n section 1.

RAM Capacity 4 kbytes H8/ 3048: 4 kbytes

H8/3047: 4 kbytes

H8/3045: 2 kbytes

H8/3044: 2 kbytes

4 kbytes 4 kbytes

Rev. 6.0, 09/02, page xviii of xxxii

Hardware

Manual H8/3048 Series

(Rev. 6.0) H8/3048F-ONE

(Rev. 1.0)

ROM Type ZTAT Mask ROM F-ZTAT

ROM Capacity 128 k byt es H8/3048: 128 kbytes

H8/3047: 96 kbytes

H8/3045: 64 kbytes

H8/3044: 32 kbytes

128 kbytes 128 kbytes

Flash Memory — — Refer to section 19,

ROM (H8/3048F). Refer to section 18,

Flash Memory

(H8/3048F-ONE Single

Power Supply).

Clock Pu ls e

Generator Refer to sect i on 20, Clock Puls e Generator. Refer to section 19,

Clock Puls e Generator.

Refer to secti on 21, Power-Down St ate. Refer to secti on 20,

Power-Down State.

Power-Down

State

Clock oscillator settling time: Waiti ng time of up to 131072 states Clock oscillator settl i ng

time: Waiting time of up

to 262144 states

Refer to table 22.1, Elect rical Characteristics of H8/3048 Series

Products, in secti on 22. Refer to table 21.1,

Electrical

Characteri stics of

H8/3048 Series

Products, in secti on 21.

Electrical

Characteristics

(Clock Rate)

1 to 18 MHz 1 to 16 MHz 5 V operation models:

2 to 25 MHz,

3 V operation models:

2 to 25 MHz.

List of Registers Refer to table B.1, Comparison of H8/ 3048 Series Int ernal I/ O Regist er S pecific at i ons, in

appendix B.

Refer to appendix B.1, Address es.

Notes on Usage — — — Refer to section 1.4,

Notes on H8/3048F-

ONE (Single Power

Supply).

On-chip

Emulator (E10T) — — — On-chip emulator

(E10T)

Rev. 6.0, 09/02, page xix of xxxii

Contents

Section 1 Overview........................................................................................................... 1

1.1 Overview........................................................................................................................... 1

1.2 Block Diagram .................................................................................................................. 7

1.3 Pin Description.................................................................................................................. 8

1.3.1 Pin Arrangement .................................................................................................. 8

1.3.2 Pin Assignments in Each Mode............................................................................ 10

1.3.3 Pin Functions........................................................................................................ 15

1.4 Differences between H8/3048F and H8/3048F-ONE........................................................ 20

Section 2 CPU.................................................................................................................... 25

2.1 Overview........................................................................................................................... 25

2.1.1 Features................................................................................................................ 25

2.1.2 Differences from H8/300 CPU............................................................................. 26

2.2 CPU Operating Modes ...................................................................................................... 27

2.3 Address Space................................................................................................................... 28

2.4 Register Configuration...................................................................................................... 29

2.4.1 Overview.............................................................................................................. 29

2.4.2 General Registers ................................................................................................. 30

2.4.3 Control Registers.................................................................................................. 31

2.4.4 Initial CPU Register Values................................................................................. 32

2.5 Data Formats ..................................................................................................................... 33

2.5.1 General Register Data Formats ............................................................................ 33

2.5.2 Memory Data Formats ......................................................................................... 35

2.6 Instruction Set ................................................................................................................... 36

2.6.1 Instruction Set Overview...................................................................................... 36

2.6.2 Instructions and Addressing Modes ..................................................................... 37

2.6.3 Tables of Instructions Classified by Function...................................................... 38

2.6.4 Basic Instruction Formats ..................................................................................... 48

2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... 49

2.7 Addressing Modes and Effective Address Calculation ..................................................... 50

2.7.1 Addressing Modes................................................................................................ 50

2.7.2 Effective Address Calculation.............................................................................. 53

2.8 Processing States............................................................................................................... 57

2.8.1 Overview.............................................................................................................. 57

2.8.2 Program Execution State...................................................................................... 58

2.8.3 Exception-Handling State..................................................................................... 58

2.8.4 Exception-Handling Sequences............................................................................ 60

2.8.5 Bus-Released State............................................................................................... 61

2.8.6 Reset State............................................................................................................ 61

Rev. 6.0, 09/02, page xx of xxxii

2.8.7 Power-Down State................................................................................................ 61

2.9 Basic Operational Timing.................................................................................................. 62

2.9.1 Overview.............................................................................................................. 62

2.9.2 On-Chip Memory Access Timing ........................................................................ 62

2.9.3 On-Chip Supporting Module Access Timing....................................................... 63

2.9.4 Access to External Address Space ....................................................................... 64

Section 3 MCU Operating Modes ................................................................................ 65

3.1 Overview........................................................................................................................... 65

3.1.1 Operating Mode Selection.................................................................................... 65

3.1.2 Register Configuration......................................................................................... 66

3.2 Mode Control Register (MDCR)....................................................................................... 66

3.3 System Control Register (SYSCR).................................................................................... 67

3.4 Operating Mode Descriptions............................................................................................ 69

3.4.1 Mode 1 ................................................................................................................. 69

3.4.2 Mode 2 ................................................................................................................. 69

3.4.3 Mode 3 ................................................................................................................. 69

3.4.4 Mode 4 ................................................................................................................. 69

3.4.5 Mode 5 ................................................................................................................. 69

3.4.6 Mode 6 ................................................................................................................. 70

3.4.7 Mode 7 ................................................................................................................. 70

3.5 Pin Functions in Each Operating Mode............................................................................. 70

3.6 Memory Map in Each Operating Mode............................................................................. 71

Section 4 Exception Handling ....................................................................................... 81

4.1 Overview........................................................................................................................... 81

4.1.1 Exception Handling Types and Priority ............................................................... 81

4.1.2 Exception Handling Operation............................................................................. 81

4.1.3 Exception Vector Table........................................................................................ 82

4.2 Reset.................................................................................................................................. 84

4.2.1 Overview.............................................................................................................. 84

4.2.2 Reset Sequence..................................................................................................... 84

4.2.3 Interrupts after Reset............................................................................................ 87

4.3 Interrupts ........................................................................................................................... 88

4.4 Trap Instruction............................................................................................................ ..... 89

4.5 Stack Status after Exception Handling.............................................................................. 89

4.6 Notes on Stack Usage........................................................................................................ 90

Section 5 Interrupt Controller........................................................................................ 91

5.1 Overview........................................................................................................................... 91

5.1.1 Features................................................................................................................ 91

5.1.2 Block Diagram..................................................................................................... 92

5.1.3 Pin Configuration................................................................................................. 93

Rev. 6.0, 09/02, page xxi of xxxii

5.1.4 Register Configuration......................................................................................... 93

5.2 Register Descriptions......................................................................................................... 94

5.2.1 System Control Register (SYSCR) ...................................................................... 94

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 95

5.2.3 IRQ Status Register (ISR).................................................................................... 102

5.2.4 IRQ Enable Register (IER)................................................................................... 103

5.2.5 IRQ Sense Control Register (ISCR)..................................................................... 104

5.3 Interrupt Sources............................................................................................................... 105

5.3.1 External Interrupts................................................................................................ 105

5.3.2 Internal Interrupts................................................................................................. 106

5.3.3 Interrupt Vector Table.......................................................................................... 106

5.4 Interrupt Operation............................................................................................................ 110

5.4.1 Interrupt Handling Process................................................................................... 110

5.4.2 Interrupt Sequence................................................................................................ 115

5.4.3 Interrupt Response Time...................................................................................... 116

5.5 Usage Notes....................................................................................................................... 117

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ...................... 117

5.5.2 Instructions that Inhibit Interrupts........................................................................ 118

5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 118

5.5.4 Usage Notes on External Interrupts...................................................................... 118

5.5.5 Notes on Non-Maskable Interrupts (NMI)........................................................... 120

Section 6 Bus Controller ................................................................................................. 123

6.1 Overview........................................................................................................................... 123

6.1.1 Features................................................................................................................ 123

6.1.2 Block Diagram..................................................................................................... 124

6.1.3 Input/Output Pins ................................................................................................. 125

6.1.4 Register Configuration......................................................................................... 126

6.2 Register Descriptions......................................................................................................... 126

6.2.1 Bus Width Control Register (ABWCR)............................................................... 126

6.2.2 Access State Control Register (ASTCR).............................................................. 127

6.2.3 Wait Control Register (WCR).............................................................................. 128

6.2.4 Wait State Controller Enable Register (WCER) .................................................. 129

6.2.5 Bus Release Control Register (BRCR)................................................................. 130

6.2.6 Chip Select Control Register (CSCR).................................................................. 131

6.3 Operation........................................................................................................................... 133

6.3.1 Area Division....................................................................................................... 133

6.3.2 Chip Select Signals............................................................................................... 134

6.3.3 Data Bus............................................................................................................... 136

6.3.4 Bus Control Signal Timing................................................................................... 137

6.3.5 Wait Modes.......................................................................................................... 145

6.3.6 Interconnections with Memory (Example)........................................................... 151

6.3.7 Bus Arbiter Operation.......................................................................................... 153

Rev. 6.0, 09/02, page xxii of xxxii

6.4 Usage Notes....................................................................................................................... 156

6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM...................................... 156

6.4.2 Register Write Timing.......................................................................................... 156

6.4.3 BREQ Input Timing............................................................................................. 158

6.4.4 Transition To Software Standby Mode ................................................................ 158

Section 7 Refresh Controller.......................................................................................... 159

7.1 Overview........................................................................................................................... 159

7.1.1 Features................................................................................................................ 159

7.1.2 Block Diagram..................................................................................................... 160

7.1.3 Input/Output Pins ................................................................................................. 161

7.1.4 Register Configuration......................................................................................... 161

7.2 Register Descriptions......................................................................................................... 162

7.2.1 Refresh Control Register (RFSHCR)................................................................... 162

7.2.2 Refresh Timer Control/Status Register (RTMCSR)............................................. 165

7.2.3 Refresh Timer Counter (RTCNT)........................................................................ 166

7.2.4 Refresh Time Constant Register (RTCOR).......................................................... 167

7.3 Operation........................................................................................................................... 168

7.3.1 Overview.............................................................................................................. 168

7.3.2 DRAM Refresh Control ....................................................................................... 170

7.3.3 Pseudo-Static RAM Refresh Control ................................................................... 185

7.3.4 Interval Timer....................................................................................................... 189

7.4 Interrupt Source................................................................................................................. 195

7.5 Usage Notes....................................................................................................................... 195

Section 8 DMA Controller.............................................................................................. 197

8.1 Overview........................................................................................................................... 197

8.1.1 Features................................................................................................................ 197

8.1.2 Block Diagram..................................................................................................... 198

8.1.3 Functional Overview............................................................................................ 199

8.1.4 Input/Output Pins ................................................................................................. 201

8.1.5 Register Configuration......................................................................................... 201

8.2 Register Descriptions (Short Address Mode).................................................................... 203

8.2.1 Memory Address Registers (MAR)...................................................................... 203

8.2.2 I/O Address Registers (IOAR)............................................................................. 204

8.2.3 Execute Transfer Count Registers (ETCR) .......................................................... 205

8.2.4 Data Transfer Control Registers (DTCR)............................................................. 206

8.3 Register Descriptions (Full Address Mode)...................................................................... 209

8.3.1 Memory Address Registers (MAR)...................................................................... 209

8.3.2 I/O Address Registers (IOAR)............................................................................. 209

8.3.3 Execute Transfer Count Registers (ETCR) .......................................................... 210

8.3.4 Data Transfer Control Registers (DTCR)............................................................. 212

8.4 Operation........................................................................................................................... 218

Rev. 6.0, 09/02, page xxiii of xxxii

8.4.1 Overview.............................................................................................................. 218

8.4.2 I/O Mode.............................................................................................................. 220

8.4.3 Idle Mode............................................................................................................. 222

8.4.4 Repeat Mode ........................................................................................................ 225

8.4.5 Normal Mode....................................................................................................... 229

8.4.6 Block Transfer Mode ........................................................................................... 232

8.4.7 DMAC Activation................................................................................................ 237

8.4.8 DMAC Bus Cycle ................................................................................................ 239

8.4.9 DMAC Multiple-Channel Operation.................................................................... 245

8.4.10 External Bus Requests, Refresh Controller, and DMAC ..................................... 246

8.4.11 NMI Interrupts and DMAC.................................................................................. 247

8.4.12 Aborting a DMA Transfer.................................................................................... 248

8.4.13 Exiting Full Address Mode.................................................................................. 249

8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 250

8.5 Interrupts ........................................................................................................................... 251

8.6 Usage Notes....................................................................................................................... 252

8.6.1 Note on Word Data Transfer................................................................................ 252

8.6.2 DMAC Self-Access.............................................................................................. 252

8.6.3 Longword Access to Memory Address Registers ................................................ 252

8.6.4 Note on Full Address Mode Setup ....................................................................... 252

8.6.5 Note on Activating DMAC by Internal Interrupts................................................ 252

8.6.6 NMI Interrupts and Block Transfer Mode............................................................ 254

8.6.7 Memory and I/O Address Register Values........................................................... 254

8.6.8 Bus Cycle when Transfer is Aborted.................................................................... 255

Section 9 I/O Ports............................................................................................................ 257

9.1 Overview........................................................................................................................... 257

9.2 Port 1................................................................................................................................. 261

9.2.1 Overview.............................................................................................................. 261

9.2.2 Register Descriptions ........................................................................................... 262

9.3 Port 2................................................................................................................................. 264

9.3.1 Overview.............................................................................................................. 264

9.3.2 Register Descriptions ........................................................................................... 265

9.4 Port 3................................................................................................................................. 268

9.4.1 Overview.............................................................................................................. 268

9.4.2 Register Descriptions ........................................................................................... 268

9.5 Port 4................................................................................................................................. 270

9.5.1 Overview.............................................................................................................. 270

9.5.2 Register Descriptions ........................................................................................... 271

9.6 Port 5................................................................................................................................. 274

9.6.1 Overview.............................................................................................................. 274

9.6.2 Register Descriptions ........................................................................................... 275

9.7 Port 6................................................................................................................................. 278

Rev. 6.0, 09/02, page xxiv of xxxii

9.7.1 Overview.............................................................................................................. 278

9.7.2 Register Descriptions ........................................................................................... 279

9.8 Port 7................................................................................................................................. 282

9.8.1 Overview.............................................................................................................. 282

9.8.2 Register Description............................................................................................. 283

9.9 Port 8................................................................................................................................. 284

9.9.1 Overview.............................................................................................................. 284

9.9.2 Register Descriptions ........................................................................................... 285

9.10 Port 9................................................................................................................................. 289

9.10.1 Overview.............................................................................................................. 289

9.10.2 Register Descriptions ........................................................................................... 290

9.11 Port A................................................................................................................................ 294

9.11.1 Overview.............................................................................................................. 294

9.11.2 Register Descriptions ........................................................................................... 296

9.11.3 Pin Functions........................................................................................................ 298

9.12 Port B................................................................................................................................. 304

9.12.1 Overview.............................................................................................................. 304

9.12.2 Register Descriptions ........................................................................................... 306

9.12.3 Pin Functions........................................................................................................ 308

Section 10 16-Bit Integrated Timer Unit (ITU).......................................................... 313

10.1 Overview........................................................................................................................... 313

10.1.1 Features................................................................................................................ 313

10.1.2 Block Diagrams.................................................................................................... 316

10.1.3 Input/Output Pins ................................................................................................. 321

10.1.4 Register Configuration......................................................................................... 322

10.2 Register Descriptions......................................................................................................... 325

10.2.1 Timer Start Register (TSTR)................................................................................ 325

10.2.2 Timer Synchro Register (TSNC).......................................................................... 326

10.2.3 Timer Mode Register (TMDR) ............................................................................ 328

10.2.4 Timer Function Control Register (TFCR)............................................................ 331

10.2.5 Timer Output Master Enable Register (TOER).................................................... 333

10.2.6 Timer Output Control Register (TOCR) .............................................................. 335

10.2.7 Timer Counters (TCNT)....................................................................................... 336

10.2.8 General Registers (GRA, GRB) ........................................................................... 337

10.2.9 Buffer Registers (BRA, BRB).............................................................................. 338

10.2.10 Timer Control Registers (TCR)............................................................................ 339

10.2.11 Timer I/O Control Register (TIOR) ..................................................................... 341

10.2.12 Timer Status Register (TSR)................................................................................ 343

10.2.13 Timer Interrupt Enable Register (TIER) .............................................................. 345

10.3 CPU Interface.................................................................................................................... 347

10.3.1 16-Bit Accessible Registers.................................................................................. 347

10.3.2 8-Bit Accessible Registers.................................................................................... 349

Rev. 6.0, 09/02, page xxv of xxxii

10.4 Operation........................................................................................................................... 351

10.4.1 Overview.............................................................................................................. 351

10.4.2 Basic Functions.................................................................................................... 352

10.4.3 Synchronization.................................................................................................... 361

10.4.4 PWM Mode.......................................................................................................... 363

10.4.5 Reset-Synchronized PWM Mode......................................................................... 367

10.4.6 Complementary PWM Mode ............................................................................... 370

10.4.7 Phase Counting Mode.......................................................................................... 379

10.4.8 Buffering.............................................................................................................. 381

10.4.9 ITU Output Timing .............................................................................................. 388

10.5 Interrupts ........................................................................................................................... 390

10.5.1 Setting of Status Flags.......................................................................................... 390

10.5.2 Clearing of Status Flags ....................................................................................... 392

10.5.3 Interrupt Sources and DMA Controller Activation.............................................. 393

10.6 Usage Notes....................................................................................................................... 394

Section 11 Programmable Timing Pattern Controller............................................... 409

11.1 Overview........................................................................................................................... 409

11.1.1 Features................................................................................................................ 409

11.1.2 Block Diagram ..................................................................................................... 410

11.1.3 TPC Pins............................................................................................................... 411

11.1.4 Registers............................................................................................................... 412

11.2 Register Descriptions......................................................................................................... 413

11.2.1 Port A Data Direction Register (PADDR) ........................................................... 413

11.2.2 Port A Data Register (PADR) .............................................................................. 413

11.2.3 Port B Data Direction Register (PBDDR)............................................................ 414

11.2.4 Port B Data Register (P BDR)............................................................................... 414

11.2.5 Next Data Register A (NDRA)............................................................................. 415

11.2.6 Next Data Register B (NDRB)............................................................................. 417

11.2.7 Next Data Enable Register A (NDERA).............................................................. 419

11.2.8 Next Data Enable Register B (NDERB)............................................................... 420

11.2.9 TPC Output Control Register (TPCR).................................................................. 421

11.2.10 TPC Output Mode Register (TPMR) ................................................................... 423

11.3 Operation........................................................................................................................... 425

11.3.1 Overview.............................................................................................................. 425

11.3.2 Output Timing...................................................................................................... 426

11.3.3 Normal TPC Output............................................................................................. 427

11.3.4 Non-Overlapping TPC Output............................................................................. 429

11.3.5 TPC Output Triggering by Input Capture ............................................................ 431

11.4 Usage Notes....................................................................................................................... 432

11.4.1 Operation of TPC Output Pins ............................................................................. 432

11.4.2 Note on Non-Overlapping Output........................................................................ 432

Rev. 6.0, 09/02, page xxvi of xxxii

Section 12 Watchdog Timer............................................................................................. 435

12.1 Overview........................................................................................................................... 435

12.1.1 Features................................................................................................................ 435

12.1.2 Block Diagram ..................................................................................................... 436

12.1.3 Pin Configuration................................................................................................. 436

12.1.4 Register Configuration......................................................................................... 437

12.2 Register Descriptions......................................................................................................... 437

12.2.1 Timer Counter (TCNT)........................................................................................ 437

12.2.2 Timer Control/Status Register (TCSR) ................................................................ 438

12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 440

12.2.4 Notes on Register Access..................................................................................... 441

12.3 Operation........................................................................................................................... 443

12.3.1 Watchdog Timer Operation.................................................................................. 443

12.3.2 Interval Timer Operation...................................................................................... 444

12.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 444

12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)................................... 445

12.4 Interrupts ........................................................................................................................... 446

12.5 Usage Notes....................................................................................................................... 446

12.6 Notes.................................................................................................................................. 447

Section 13 Serial Communication Interface................................................................. 449

13.1 Overview........................................................................................................................... 449

13.1.1 Features................................................................................................................ 449

13.1.2 Block Diagram ..................................................................................................... 451

13.1.3 Input/Output Pins ................................................................................................. 452

13.1.4 Register Configuration......................................................................................... 452

13.2 Register Descriptions......................................................................................................... 453

13.2.1 Receive Shift Register (RSR)............................................................................... 453

13.2.2 Receive Data Register (RDR) .............................................................................. 453

13.2.3 Transmit Shift Register (TSR).............................................................................. 454

13.2.4 Transmit Data Register (TDR)............................................................................. 454

13.2.5 Serial Mode Register (SMR)................................................................................ 455

13.2.6 Serial Control Register (SCR).............................................................................. 458

13.2.7 Serial Status Register (SSR)................................................................................. 462

13.2.8 Bit Rate Register (BRR)....................................................................................... 466

13.3 Operation........................................................................................................................... 474

13.3.1 Overview.............................................................................................................. 474

13.3.2 Operation in Asynchronous Mode........................................................................ 476

13.3.3 Multiprocessor Communication........................................................................... 485

13.3.4 Synchronous Operation........................................................................................ 492

13.4 SCI Interrupts.................................................................................................................... 500

13.5 Usage Notes....................................................................................................................... 501

Rev. 6.0, 09/02, page xxvii of xxxii

Section 14 Smart Card Interface...................................................................................... 507

14.1 Overview........................................................................................................................... 507

14.1.1 Features................................................................................................................ 507

14.1.2 Block Diagram ..................................................................................................... 508

14.1.3 Input/Output Pins ................................................................................................. 509

14.1.4 Register Configuration......................................................................................... 509

14.2 Register Descriptions......................................................................................................... 510

14.2.1 Smart Card Mode Register (SCMR) .................................................................... 510

14.2.2 Serial Status Register (SSR)................................................................................. 511

14.2.3 Serial Mode Register (SMR)................................................................................ 513

14.2.4 Serial Control Register (SCR).............................................................................. 514

14.3 Operation........................................................................................................................... 515

14.3.1 Overview.............................................................................................................. 515

14.3.2 Pin Connections.................................................................................................... 515

14.3.3 Data Format.......................................................................................................... 517

14.3.4 Register Settings ................................................................................................... 518

14.3.5 Clock.................................................................................................................... 520

14.3.6 Transmitting and Receiving Data......................................................................... 522

14.4 Usage Notes....................................................................................................................... 528

Section 15 A/D Converter................................................................................................. 533

15.1 Overview........................................................................................................................... 533

15.1.1 Features................................................................................................................ 533

15.1.2 Block Diagram ..................................................................................................... 534

15.1.3 Input Pins ............................................................................................................. 535

15.1.4 Register Configuration......................................................................................... 536

15.2 Register Descriptions......................................................................................................... 537

15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 537

15.2.2 A/D Control/Status Register (ADCSR)................................................................ 538

15.2.3 A/D Control Register (ADCR)............................................................................. 540

15.3 CPU Interface.................................................................................................................... 541

15.4 Operation........................................................................................................................... 542

15.4.1 Single Mode (SCAN = 0)..................................................................................... 542

15.4.2 Scan Mode (SCAN = 1)....................................................................................... 544

15.4.3 Input Sampling and A/D Conversion Time.......................................................... 546

15.4.4 External Trigger Input Timing ............................................................................. 547

15.5 Interrupts ........................................................................................................................... 548

15.6 Usage Notes....................................................................................................................... 548

Section 16 D/A Converter................................................................................................. 555

16.1 Overview........................................................................................................................... 555

16.1.1 Features................................................................................................................ 555

16.1.2 Block Diagram ..................................................................................................... 556

Rev. 6.0, 09/02, page xxviii of xxxii

16.1.3 Input/Output Pins ................................................................................................. 557

16.1.4 Register Configuration......................................................................................... 557

16.2 Register Descriptions......................................................................................................... 558

16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 558

16.2.2 D/A Control Register (DACR)............................................................................. 558

16.2.3 D/A Standby Control Register (DASTCR).......................................................... 560

16.3 Operation........................................................................................................................... 561

16.4 D/A Output Control........................................................................................................... 562

16.5 Usage Notes....................................................................................................................... 562

Section 17 RAM................................................................................................................... 563

17.1 Overview........................................................................................................................... 563

17.1.1 Block Diagram ..................................................................................................... 564

17.1.2 Register Configuration......................................................................................... 564

17.2 System Control Register (SYSCR).................................................................................... 565

17.3 Operation........................................................................................................................... 566

Section 18 ROM (H8/3048ZTAT and Mask-ROM Versions)............................... 567

18.1 Overview........................................................................................................................... 567

18.1.1 Block Diagram ..................................................................................................... 568

18.2 PROM Mode ..................................................................................................................... 569

18.2.1 PROM Mode Setting............................................................................................ 569

18.2.2 Socket Adapter and Memory Map ....................................................................... 569

18.3 PROM Programming......................................................................................................... 57 1

18.3.1 Programming and Verification............................................................................. 572

18.3.2 Programming Precautions.................................................................................... 576

18.3.3 Reliability of Programmed Data........................................................................... 577

18.4 Notes on Ordering Mask ROM Version Chip................................................................... 578

Section 19 Flash Memory (H8/3048F: Dual Power Supply (VPP = 12 V)) ......... 581

19.1 Overview........................................................................................................................... 581

19.2 Flash Memory Overview................................................................................................... 582

19.2.1 Flash Memory Operation ..................................................................................... 582

19.2.2 Mode Programming and Flash Memory Address Space...................................... 583

19.2.3 Features................................................................................................................ 584

19.2.4 Block Diagram ..................................................................................................... 585

19.2.5 Input/Output Pins ................................................................................................. 586

19.2.6 Register Configuration......................................................................................... 586

19.3 Flash Memory Register Descriptions................................................................................ 587

19.3.1 Flash Memory Control Register........................................................................... 587

19.3.2 Erase Block Register 1 ......................................................................................... 590

19.3.3 Erase Block Register 2 ......................................................................................... 591

19.3.4 RAM Control Register (RAMCR) ....................................................................... 593

Rev. 6.0, 09/02, page xxix of xxxii

19.4 On-Board Programming Modes ........................................................................................ 594

19.4.1 Boot Mode............................................................................................................ 595

19.4.2 User Program Mode............................................................................................. 600

19.5 Programming and Erasing Flash Memory......................................................................... 602

19.5.1 Program Mode...................................................................................................... 603

19.5.2 Program-Verify Mode.......................................................................................... 603

19.5.3 Programming Flowchart and Sample Program .................................................... 604

19.5.4 Erase Mode........................................................................................................... 607

19.5.5 Erase-Verify Mode............................................................................................... 607

19.5.6 Erasing Flowchart and Sample Program.............................................................. 608

19.5.7 Prewrite-Verify Mode.......................................................................................... 622

19.5.8 Protect Modes....................................................................................................... 623

19.5.9 NMI Input Masking.............................................................................................. 626

19.6 Flash Memory Emulation by RAM................................................................................... 627

19.7 Flash Memory PROM Mode............................................................................................. 629

19.7.1 PROM Mode Setting............................................................................................ 629

19.7.2 Socket Adapter and Memory Map ....................................................................... 630

19.7.3 Operation in PROM Mode................................................................................... 632

19.8 Flash Memory Programming and Erasing Precautions (Dual-Power Supply).................. 641

19.9 Notes when Converting the F-ZTAT (Dual-Power Supply) Application Software

to the Mask-ROM Versions............................................................................................... 649

Section 20 Clock Pulse Generator................................................................................... 651

20.1 Overview........................................................................................................................... 651

20.1.1 Block Diagram ..................................................................................................... 652

20.2 Oscillator Circuit............................................................................................................... 653

20.2.1 Connecting a Crystal Resonator........................................................................... 653

20.2.2 External Clock Input............................................................................................ 655

20.3 Duty Adjustment Circuit................................................................................................... 657

20.4 Prescalers........................................................................................................................... 657

20.5 Frequency Divider............................................................................................................. 658

20.5.1 Register Configuration......................................................................................... 658

20.5.2 Division Control Register (DIVCR)..................................................................... 658

20.5.3 Usage Notes.......................................................................................................... 659

Section 21 Power-Down State.......................................................................................... 661

21.1 Overview........................................................................................................................... 661

21.2 Register Configuration...................................................................................................... 663

21.2.1 System Control Register (SYSCR) ...................................................................... 663

21.2.2 Module Standby Control Register (MSTCR)....................................................... 665

21.3 Sleep Mode........................................................................................................................ 667

21.3.1 Transition to Sleep Mode..................................................................................... 667

21.3.2 Exit from Sleep Mode.......................................................................................... 667

Rev. 6.0, 09/02, page xxx of xxxii

21.4 Software Standby Mode.................................................................................................... 667

21.4.1 Transition to Software Standby Mode.................................................................. 667

21.4.2 Exit from Software Standby Mode ....................................................................... 668

21.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 668

21.4.4 Sample Application of Software Standby Mode.................................................. 670

21.4.5 Note...................................................................................................................... 670

21.5 Hardware Standby Mode................................................................................................... 671

21.5.1 Transition to Hardware Standby Mode ................................................................ 671

21.5.2 Exit from Hardware Standby Mode ..................................................................... 671

21.5.3 Timing for Hardware Standby Mode ................................................................... 671

21.6 Module Standby Function ................................................................................................. 672

21.6.1 Module Standby Timing....................................................................................... 672

21.6.2 Read/Write in Module Standby............................................................................ 672

21.6.3 Usage Notes.......................................................................................................... 673

21.7 System Clock Output Disabling Function......................................................................... 674

Section 22 Electrical Characteristics.............................................................................. 675

22.1 Electrical Characteristics for H8/3048 ZTAT (PROM) and On-Chip Mask ROM

Versions............................................................................................................................. 677

22.1.1 Absolute Maximum Ratings................................................................................. 677

22.1.2 DC Characteristics................................................................................................ 678

22.1.3 AC Characteristics................................................................................................ 684

22.1.4 A/D Conversion Characteristics........................................................................... 691

22.1.5 D/A Conversion Characteristics........................................................................... 692

22.2 Electrical Characteristics of H8/3048F (Dual-Power Supply) .......................................... 693

22.2.1 Absolute Maximum Ratings................................................................................. 693

22.2.2 DC Characteristics................................................................................................ 694

22.2.3 AC Characteristics................................................................................................ 701

22.2.4 A/D Conversion Characteristics........................................................................... 707

22.2.5 D/A Conversion Characteristics........................................................................... 708

22.2.6 Flash Memory Characteristics.............................................................................. 709

22.3 Operational Timing ........................................................................................................... 710

22.3.1 Bus Timing........................................................................................................... 710

22.3.2 Refresh Controller Bu s Timing............................................................................ 714

22.3.3 Control Signal Timing.......................................................................................... 719

22.3.4 Clock Timing ....................................................................................................... 721

22.3.5 TPC and I/O Port Timing..................................................................................... 721

22.3.6 ITU Timing .......................................................................................................... 722

22.3.7 SCI Input/Output Timing..................................................................................... 723

22.3.8 DMAC Timing..................................................................................................... 724

Appendix A Instruction Set............................................................................................. 725

A.1 Instruction List .................................................................................................................. 725

Rev. 6.0, 09/02, page xxxi of xxxii

A.2 Operation Code Map......................................................................................................... 740

A.3 Number of States Required for Execution......................................................................... 743

Appendix B Internal I/O Register.................................................................................. 753

B.1 Addresses .......................................................................................................................... 754

B.2 Function............................................................................................................................. 762

Appendix C I/O Port Block Diagrams......................................................................... 842

C.1 Port 1 Block Diagram........................................................................................................ 842

C.2 Port 2 Block Diagram........................................................................................................ 843

C.3 Port 3 Block Diagram........................................................................................................ 844

C.4 Port 4 Block Diagram........................................................................................................ 845

C.5 Port 5 Block Diagram........................................................................................................ 846

C.6 Port 6 Block Diagrams...................................................................................................... 847

C.7 Port 7 Block Diagrams...................................................................................................... 851

C.8 Port 8 Block Diagrams...................................................................................................... 852

C.9 Port 9 Block Diagrams...................................................................................................... 855

C.10 Port A Block Diagrams ..................................................................................................... 859

C.11 Port B Block Diagrams...................................................................................................... 863

Appendix D Pin States...................................................................................................... 867

D.1 Port States in Each Mode .................................................................................................. 867

D.2 Pin States at Reset ............................................................................................................. 870

Appendix E Timing of Transition to and Recovery

from Hardware Standby Mode............................................................... 873

Appendix F Product Code Lineup................................................................................ 874

Appendix G Package Dimensions................................................................................. 875

Rev. 6.0, 09/02, page xxxii of xxxii

Rev. 6.0, 09/02, page 1 of 876

Section 1 Overview

1.1 Overview

The H8/3048 Series is a series of microcontrollers (MCUs) that integrate system supporting

functions together with an H8/300H CPU core having an original Hitachi architecture.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a

concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address

space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,

enabling easy porting of software from the H8/300 Series.

The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit

(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial

communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory

access controller (DMAC), a refresh controller, and other facilities.

The four members of the H8/3048 Series are the H8/3048, the H8/3047, H8/3045, and the

H8/3044. The H8/3048 has 128 kbytes of ROM and 4 kbytes of RAM. The H8/3047 has 96 kbytes

of ROM and 4 kbytes of RAM. The H8/3045 has 64 kbytes of ROM and 2 kbytes of RAM. The

H8/3044 has 32 kbytes of ROM and 2 kbytes of RAM.

Seven MCU operating modes offer a choice of data bus width and address space size. The modes

(modes 1 to 7) include one single-chip mode and six expanded modes.

In addition to the mask ROM versions of the H8/3048 Series, the H8/3048 has a ZTAT™* 1

version with user-programmable on-chip PROM and an F-ZTAT™*2 version with on-c hip flash

memory that can be programmed on-board. These versions enable users to respond quickly and

flexibly to changing application specifications, growing production volumes, and other conditions.

The F-ZTAT™ version H8/3048F-ONE includes the on-chip emulator E10T.

Table 1.1 summarizes the features of the H8/3048 Series.

Notes: *1 ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.

*2 F-ZTAT (Flexible ZTAT) is a trademark of Hitachi, Ltd.

Rev. 6.0, 09/02, page 2 of 876

Table 1.1 Features

Feature Description

CPU Upward-compatible with the H8/300 CPU at the object-code level

• General-register machine

 Sixteen 16-bit general registers

(also usable as sixteen 8-bit registers + eight 16-bit registers or eight 32-

bit registers)

• High-speed operation (flash memory version)

H8/3048F

 Maximum clock rate: 16 MHz

 Add/subtract: 125 ns

 Multiply/d ivi de: 875 ns

• High-speed operation (mask ROM and PROM versions)

 Maximum clock rate: 18 MHz

 Add/subtract: 111 ns

 Multiply/d ivi de: 778 ns

• 16-Mbyte address space

• Instruction features

 8/16/32-bit data transfer, arithmetic, and logic instructions

 Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16

bits)

 Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16

bits)

 Bit accumulator function

 Bit manipulation instructions with register-indirect specification of bit

positions

Rev. 6.0, 09/02, page 3 of 876

Feature Description

Memory • H8/3048, H8/3048F

 ROM: 128 kbytes

 RAM: 4 kbytes

• H8/3047

 ROM: 96 kbytes

 RAM: 4 kbytes

• H8/3045

 ROM: 64 kbytes

 RAM: 2 kbytes

• H8/3044

 ROM: 32 kbytes

 RAM: 2 kbytes

Interrupt

controller • Seven exte rnal interrupt pins: NMI, IRQ0 to IRQ5

• 30 internal interrupts

• Three selectable interrupt priority levels

Bus controller • Address space can be partit ion ed into eigh t areas, with ind epen dent bus

specifications in each area

• Chi p select output available for areas 0 to 7

• 8-bit access or 16-bit access selectable for each area

• Two-state or three-state acce ss selectable for each area

• Selection of four wait modes

• Bus arbitration funct ion

Refresh

controller • DRAM refresh

 Directly con nect abl e to 16-bit-w id e DRAM

 CAS-before-RAS refresh

 Self-refresh mode selectable

• Pseudo-static RAM refresh

 Self-refresh mode selectable

• Usable as an interval timer

Rev. 6.0, 09/02, page 4 of 876

Feature Description

DMA controller

(DMAC) • Short address mode

 Maximum four channels available

 Selection of I/O mode, idle mode, or repeat mode

 Can be activated by com pare match/ inp ut capt ure A interrupts from ITU

channels 0 to 3, transmit-data-empty and receive-data-full interrupts from

SCI channel 0, or external requests

• Full addres s mode

 Maximum two channels available

 Selection of normal mode or block transfer mode

 Can be activated by com pare match/ inp ut capt ure A interrupts from ITU

channels 0 to 3, external requests, or auto-request

16-bit integrated

timer unit (ITU) • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or

10 pulse inputs

• 16-bit timer counter (channels 0 to 4)

• Two multiplexed output compare/input capture pins (channels 0 to 4)

• Operation can be synchronized (channels 0 to 4)

• PWM mode available (channels 0 to 4)

• Phase counting mode available (channel 2)

• Buffering available (channels 3 and 4)

• Reset-synchronized PWM mode available (channels 3 and 4)

• Complementary PWM mode available (channels 3 and 4)

• DMAC can be activated by compare match/ inp ut capt ure A interrupts

(channels 0 to 3)

Programmable

timing pattern

controller (TPC)

• Maximum 16-bit pulse output, using ITU as time base

• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)

• Non-overlap mode available

• Output data can be transferred by DMAC

Watchdog timer

(WDT),

1 channel

• Reset signal ca n be generated by overflow

• Reset signal can be output exter nal ly

• Usable as an interval timer

Rev. 6.0, 09/02, page 5 of 876

Feature Description

Serial

communication

interface (SCI),

2 channels

• Selection of asynchronous or synchronous mode

• Full duplex: can transmit and receive simultaneously

• On-chip baud-rate generator

• Smart card interface functions added (SCI0 only)

A/D converter • Resolution: 10 bits

• Eight channels, with selection of single or scan mode

• Variable analog conversion voltage range

• Sample-and-hold function

• A/D conversion can be externally triggered

D/A converter • Resolution: 8 bits

• Two channels

• D/A outputs can be sustained in software standby mode

I/O ports • 70 input/output pins

• 8 input-only pins

• Seven MCU operating modes

Mode Address Space Address Pins I nitial Bus Width Max. Bus Width

Mode 1 1 Mbyt e A19 to A08 bits 16 bits

Mode 2 1 Mbyt e A19 to A016 bits 16 bits

Mode 3 16 Mbytes A23 to A08 bits 16 bits

Mode 4 16 Mbytes A23 to A016 bits 16 bits

Mode 5 1 Mbyt e A19 to A08 bits 16 bits

Mode 6 16 Mbytes A23 to A08 bits 16 bits

Mode 7 1 Mbyt e — — —

Operating

modes

• On-chip ROM is disabled in modes 1 to 4

Power-down

state • Sleep mode

• Software standb y mode

• Hardware stan dby mode

• Module stan db y functi on

• Programmable system clock frequency division

Rev. 6.0, 09/02, page 6 of 876

Feature Description

Other features • On-chip clock pulse generator

Product lineup Model (5 V) Model (3 V) Package ROM

HD64F3048TF HD64F3048VTF 100-pin TQFP (TFP-100B)

HD64F3048F HD64F3048VF 100-pin QFP (FP-100B)

Flash memo ry

HD6473048TF HD6473048VTF 100-pin TQFP (TFP-100B)

HD6473048F HD6473048VF 100-pin QFP (FP-100B )

PROM

HD6433048TF HD6433048VTF 100-pin TQFP (TFP-100B)

HD6433048F HD6433048VF 100-pin QFP (FP-100B )

Mask ROM

HD6433047TF HD6433047VTF 100-pin TQFP (TFP-100B)

HD6433047F HD6433047VF 100-pin QFP (FP-100B )

Mask ROM

HD6433045TF HD6433045VTF 100-pin TQFP (TFP-100B)

HD6433045F HD6433045VF 100-pin QFP (FP-100B )

Mask ROM

HD6433044TF HD6433044VTF 100-pin TQFP (TFP-100B)

HD6433044F HD6433044VF 100-pin QFP (FP-100B )

Mask ROM

Rev. 6.0, 09/02, page 7 of 876

1.2 Block Diagram

Figure 1.1 shows an internal block diagram.

VCC

VSS

P37/D15

P36/D14

P35/D13

P34/D12

P33/D11

P32/D10

P31/D9

P30/D8

P47/D7

P46/D6

P45/D5

P44/D4

P43/D3

P42/D2

P41/D1

P40/D0

Port 3 Port 4

Port 5Port 9

P53/A19

P52/A18

P51/A17

P50/A16

P27/A15

P26/A14

P25/A13

P24/A12

P23/A11

P22/A10

P21/A9

P20/A8

P95/SCK1/5

P94/SCK0/4

P93/RxD1

P92/RxD0

P91/TxD1

P90/TxD0

P77/AN7/DA1

P76/AN6/DA0

P75/AN5

P74/AN4

P73/AN3

P72/AN2

P71/AN1

P70/AN0

Port 7

VREF

AVCC

AVSS

PA7/TP7/TIOCB2/A20

PA6/TP6/TIOCA2/A21/4

PA5/TP5/TIOCB1/A22/5

PA4/TP4/TIOCA1/A23/6

PA3/TP3/TIOCB0/TCLKD

PA2/TP2/TIOCA0/TCLKC

PA1/TP1/1/TCLKB

PA0/TP0/0/TCLKA

Port A

PB7/TP15/1/

PB6/TP14/0/7

PB5/TP13/TOCXB4

PB4/TP12/TOCXA4

PB3/TP11/TIOCB4

PB2/TP10/TIOCA4

PB1/TP9/TIOCB3

PB0/TP8/TIOCA3

Port 8

P84/0

P83/1/3

P82/2/2

P81/3/1

P80/ / 0

MD2

MD1

MD0

EXTAL

XTAL

VPP/*

NMI

H8/300H CPU

Clock pulse

generator

Interrupt controller

ROM

(mask ROM,

PROM, or flash

memory)

DMA controller

(DMAC)

Serial communication

interface

(SCI) 2 channels

Watchdog timer

(WDT)

Refresh

controller

Address bus

Data bus (upper)

Data bus (lower)

Port 2

P17/A7

P16/A6

P15/A5

P14/A4

P13/A3

P12/A2

P11/A1

P10/A0

Port 1

P66/

P65/

P64/

P63/

P62/

P61/

P60/

RAM

16-bit integrated

timer unit

(ITU)

A/D converter

D/A converter

Port 6

Bus controller

Programmable

timing pattern

controller (TPC)

Port B

Note: *For the mask ROM version, this pin is also used as the (output) terminal. For the flash memory version dual power

supply (VPP = 12 V) and for the PROM version, this pin is also used as the (output)/VPP (input) terminal.

Figure 1.1 Block Diagram

Rev. 6.0, 09/02, page 8 of 876

1.3 Pin Description

1.3.1 Pin Arrangement

Figure 1.2 shows the pin arrangement of the H8/3048 Series.

The pin arrangement of the H8/3048 Series is shown in figure 1.2. Differences in the H8/3048

Series pin arrangements are shown in table 1.2. Except for the differences shown in table 1.2, the

pin arrangements are the same.

Table 1.2 Comparison of H8/3048 Series Pin Arrangements

Package Pin

Number H8/3048

ZTAT

H8/3048

Mask ROM

Version

H8/3047

Mask ROM

Version

H8/3045

Mask ROM

Version

H8/3044

Mask ROM

Version H8/3048F

CC VCC VCC VCC VCC VCC

FP-100B

(TFP-100B) 10 VPP/RESO RESO RESO RESO RESO VPP/RESO

Rev. 6.0, 09/02, page 9 of 876

TIOCA /TP /PB

TIOCB /TP /PB

TIOCA /TP /PB

TIOCB /TP /PB

TOCXA /TP /PB

TOCXB /TP /PB

/ /TP /PB

TxD /P9

RxD /P9

/SCK /P9

D /P4

P6 /

XTAL

EXTAL

NMI

P6 /

P5 /A

P2 /A

10*

REF

/AN

/DA

/AN

/DA

/ /

/TP

/TCLKA

/TP

/TCLKB

/TP

/TIOCA

/TCLKC

/TP

/TIOCB

/TCLKD

/TP

/TIOCA

/TP

/TIOCB

/TP

/TIOCA

/TP

/TIOCB

100

/P2

/P1

/P3

/P4

Top view

(FP-100B, TFP-100B)

Note: *For the mask ROM version, this pin is also used as the terminal. For the PROM version and

the flash memory version dual power method, this pin is also used as the /V

terminal.

For the flash memory version with single power method.

Figure 1.2 Pin Arrangement of H8/3048ZTAT, H8/3048 Mask ROM Version, H8/3047

Mask ROM Version, H8/3045 Mask ROM Version, H8/3044 Mask ROM Version, and

H8/3048F (FP-100B or TFP-100B, Top View)

Rev. 6.0, 09/02, page 10 of 876

1.3.2 Pin Assignments in Each Mode

Table 1.3 lists the pin assignments in each mode.

Table 1.3 Pin Assignments in Each Mode (FP-100B or TFP-100B)

Pin Name

PROM Mode

No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 M ode 7 EPROM Flash Remarks

1*3VCC VCC VCC VCC VCC VCC VCC VCC VCC Mask

ROM

version,

PROM

version

and flash

memory

version

with dual

power

supply.

2PB

/TP

TIOCA3

B0/TP8/

TIOCA3

B0/TP8/

TIOCA3

B0/TP8/

TIOCA3

B0/TP8/

TIOCA3

B0/TP8/

TIOCA3

B0/TP8/

TIOCA3

NC NC

3PB

/TP

TIOCB3

/TP

TIOCB3

/TP

TIOCB3

/TP

TIOCB3

/TP

TIOCB3

/TP

TIOCB3

/TP

TIOCB3

NC NC

4PB

/TP

TIOCA4

/TP

TIOCA4

/TP

TIOCA4

/TP

TIOCA4

/TP

TIOCA4

/TP

TIOCA4

/TP

TIOCA4

NC NC

5PB

/TP

TIOCB4

/TP

TIOCB4

/TP

TIOCB4

/TP

TIOCB4

/TP

TIOCB4

/TP

TIOCB4

/TP

TIOCB4

NC NC

6PB

/TP

TOCXA4

/TP

TOCXA4

/TP

TOCXA4

/TP

TOCXA4

/TP

TOCXA4

/TP

TOCXA4

/TP

TOCXA4

NC NC

7PB

/TP

TOCXB4

/TP

TOCXB4

/TP

TOCXB4

/TP

TOCXB4

/TP

TOCXB4

/TP

TOCXB4

/TP

TOCXB4

NC NC

8PB

/TP

DREQ0/

CS7

/TP

DREQ0/

CS7

/TP

DREQ0/

CS7

/TP

DREQ0/

CS7

/TP

DREQ0/

CS7

/TP

DREQ0/

CS7

/TP

DREQ0

NC NC

9PB7/TP15/

DREQ1/

ADTRG

PB7/TP15/

DREQ1/

ADTRG

PB7/TP15/

DREQ1/

ADTRG

PB7/TP15/

DREQ1/

ADTRG

PB7/TP15/

DREQ1/

ADTRG

PB7/TP15/

DREQ1/

ADTRG

PB7/TP15/

DREQ1/

ADTRG

NC NC

10*4RESO RESO RESO RESO RESO RESO RESO VPP VPP Mask

ROM

version,

PROM

version

and flash

memory

version

with dual

power

supply.

Rev. 6.0, 09/02, page 11 of 876

Pin Name

PROM Mode

No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 M ode 7 EPROM Flash Remarks

11 VSS VSS VSS VSS VSS VSS VSS VSS VSS

12 P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0NC NC

13 P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1NC NC

14 P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0NC NC

15 P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1NC NC

16 P9

/SCK

IRQ4

/SCK

IRQ4

/SCK

IRQ4

/SCK

IRQ4

/SCK

IRQ4

/SCK

IRQ4

/SCK

IRQ4

NC NC

17 P9

/SCK

IRQ5

/SCK

IRQ5

/SCK

IRQ5

/SCK

IRQ5

/SCK

IRQ5

/SCK

IRQ5

/SCK

IRQ5

NC NC

18 P40/D0*1P40/D0*2P40/D0*1P40/D0*2P40/D0*1P40/D0*1P40NC NC

19 P41/D1*1P41/D1*2P41/D1*1P41/D1*2P41/D1*1P41/D1*1P41NC NC

20 P42/D2*1P42/D2*2P42/D2*1P42/D2*2P42/D2*1P42/D2*1P42NC NC

21 P43/D3*1P43/D3*2P43/D3*1P43/D3*2P43/D3*1P43/D3*1P43NC NC

22 VSS VSS VSS VSS VSS VSS VSS VSS VSS

23 P44/D4*1P44/D4*2P44/D4*1P44/D4*2P44/D4*1P44/D4*1P44NC NC

24 P45/D5*1P45/D5*2P45/D5*1P45/D5*2P45/D5*1P45/D5*1P45NC NC

25 P46/D6*1P46/D6*2P46/D6*1P46/D6*2P46/D6*1P46/D6*1P46NC NC

26 P47/D7*1P47/D7*2P47/D7*1P47/D7*2P47/D7*1P47/D7*1P47NC NC

27 D8D8D8D8D8D8P30EO0I/O0

28 D9D9D9D9D9D9P31EO1I/O1

29 D10 D10 D10 D10 D10 D10 P32EO2I/O2

30 D11 D11 D11 D11 D11 D11 P33EO3I/O3

31 D12 D12 D12 D12 D12 D12 P34EO4I/O4

32 D13 D13 D13 D13 D13 D13 P35EO5I/O5

33 D14 D14 D14 D14 D14 D14 P36EO6I/O6

34 D15 D15 D15 D15 D15 D15 P37EO7I/O7

35 VCC VCC VCC VCC VCC VCC VCC VCC VCC

36 A0A0A0A0P10/A0P10/A0P10EA0A0

37 A1A1A1A1P11/A1P11/A1P11EA1A1

38 A2A2A2A2P12/A2P12/A2P12EA2A2

39 A3A3A3A3P13/A3P13/A3P13EA3A3

40 A4A4A4A4P14/A4P14/A4P14EA4A4

41 A5A5A5A5P15/A5P15/A5P15EA5A5

42 A6A6A6A6P16/A6P16/A6P16EA6A6

43 A7A7A7A7P17/A7P17/A7P17EA7A7

44 VSS VSS VSS VSS VSS VSS VSS VSS VSS

Rev. 6.0, 09/02, page 12 of 876

Pin Name

PROM Mode

No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 M ode 7 EPROM Flash Remarks

45 A8A8A8A8P20/A8P20/A8P20EA8A8

46 A9A9A9A9P21/A9P21/A9P21OE OE

47 A10 A10 A10 A10 P22/A10 P22/A10 P22EA10 A10

48 A11 A11 A11 A11 P23/A11 P23/A11 P23EA11 A11

49 A12 A12 A12 A12 P24/A12 P24/A12 P24EA12 A12

50 A13 A13 A13 A13 P25/A13 P25/A13 P25EA13 A13

51 A14 A14 A14 A14 P26/A14 P26/A14 P26EA14 A14

52 A15 A15 A15 A15 P27/A15 P27/A15 P27CE CE

53 A16 A16 A16 A16 P50/A16 P50/A16 P50VCC VCC

54 A17 A17 A17 A17 P51/A17 P51/A17 P51VCC VCC

55 A18 A18 A18 A18 P52/A18 P52/A18 P52NC NC

56 A19 A19 A19 A19 P53/A19 P53/A19 P53NC NC

57 VSS VSS VSS VSS VSS VSS VSS VSS VSS

58 P60/

WAIT P60/

WAIT P60EA15 A15

59 P61/

BREQ P61/

BREQ P61NC NC

60 P62/

BACK P62/

BACK P62NC NC

61 φφφφφφφNC NC

62 STBY STBY STBY STBY STBY STBY STBY VSS VCC

63 RES RES RES RES RES RES RES NC RES

64 NMI NMI NMI NMI NMI NMI NMI EA9A9

65 VSS VSS VSS VSS VSS VSS VSS VSS VSS

66 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL NC EXTAL

67 XTAL XTAL XTAL XTAL XTAL XTAL XTAL NC XTAL

68 VCC VCC VCC VCC VCC VCC VCC VCC VCC

69 AS AS AS AS AS AS P63NC A16

70 RD RD RD RD RD RD P64NC NC

71 HWR HWR HWR HWR HWR HWR P65NC VCC

72 LWR LWR LWR LWR LWR LWR P66NC NC

73 MD0MD0MD0MD0MD0MD0MD0VSS VSS

74 MD1MD1MD1MD1MD1MD1MD1VSS VSS

75 MD2MD2MD2MD2MD2MD2MD2VSS VSS

76 AVCC AVCC AVCC AVCC AVCC AVCC AVCC VCC VCC

77 VREF VREF VREF VREF VREF VREF VREF VCC VCC

Rev. 6.0, 09/02, page 13 of 876

Pin Name

PROM Mode

No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 M ode 7 EPROM Flash Remarks

78 P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0NC NC

79 P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1NC NC

80 P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2NC NC

81 P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3NC NC

82 P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4NC NC

83 P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5NC NC

84 P7

/AN

DA0

/AN

DA0

/AN

DA0

/AN

DA0

/AN

DA0

/AN

DA0

/AN

DA0

NC NC

85 P7

/AN

DA1

/AN

DA1

/AN

DA1

/AN

DA1

/AN

DA1

/AN

DA1

/AN

DA1

NC NC

86 AVSS AVSS AVSS AVSS AVSS AVSS AVSS VSS VSS

87 P80/

RFSH/

IRQ0

P80/

RFSH/

IRQ0

P80/

RFSH/

IRQ0

P80/

RFSH/

IRQ0

P80/

RFSH/

IRQ0

P80/

RFSH/

IRQ0

P80/IRQ0EA16 NC

88 P8

/CS

IRQ1

/CS

IRQ1

/CS

IRQ1

/CS

IRQ1

/CS

IRQ1

/CS

IRQ1

P81/IRQ1PGM NC

89 P8

/CS

IRQ2

/CS

IRQ2

/CS

IRQ2

/CS

IRQ2

/CS

IRQ2

/CS

IRQ2

P82/IRQ2NC VCC

90 P8

/CS

IRQ3

/CS

IRQ3

/CS

IRQ3

/CS

IRQ3

/CS

IRQ3

/CS

IRQ3

P83/IRQ3NC WE

91 P84/CS0P84/CS0P84/CS0P84/CS0P84/CS0P84/CS0P84NC NC

92 VSS VSS VSS VSS VSS VSS VSS VSS VSS

93 PA

/TP

TEND0/

TCLKA

/TP

TEND0/

TCLKA

/TP

TEND0/

TCLKA

/TP

TEND0/

TCLKA

/TP

TEND0/

TCLKA

/TP

TEND0/

TCLKA

/TP

TEND0/

TCLKA

NC NC

94 PA

/TP

TEND1/

TCLKB

/TP

TEND1/

TCLKB

/TP

TEND1/

TCLKB

/TP

TEND1/

TCLKB

/TP

TEND1/

TCLKB

/TP

TEND1/

TCLKB

/TP

TEND1/

TCLKB

NC NC

95 PA

/TP

TIOCA

TCLKC

/TP

TIOCA

TCLKC

/TP

TIOCA

TCLKC

/TP

TIOCA

TCLKC

/TP

TIOCA

TCLKC

/TP

TIOCA

TCLKC

/TP

TIOCA

TCLKC

NC NC

96 PA

/TP

TIOCB

TCLKD

/TP

TIOCB

TCLKD

/TP

TIOCB

TCLKD

/TP

TIOCB

TCLKD

/TP

TIOCB

TCLKD

/TP

TIOCB

TCLKD

/TP

TIOCB

TCLKD

NC NC

97 PA

/TP

TIOCA

CS6

/TP

TIOCA

CS6

/TP

TIOCA

CS6

/TP

TIOCA

CS6

/TP

TIOCA

CS6

/TP

TIOCA

A23/CS6

/TP

TIOCA1

NC NC

98 PA

/TP

TIOCB

CS5

/TP

TIOCB

CS5

/TP

TIOCB

CS5

/TP

TIOCB

CS5

/TP

TIOCB

CS5

/TP

TIOCB

A22/CS5

/TP

TIOCB1

NC NC

Rev. 6.0, 09/02, page 14 of 876

Pin Name

PROM Mode

No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 M ode 7 EPROM Flash Remarks

99 PA

/TP

TIOCA

CS4

/TP

TIOCA

CS4

/TP

TIOCA

CS4

/TP

TIOCA

CS4

/TP

TIOCA

CS4

/TP

TIOCA

A21/CS4

/TP

TIOCA2

NC NC

100 PA

/TP

TIOCB2

/TP

TIOCB2

A20 A20 PA

/TP

TIOCB2

A20 PA

/TP

TIOCB2

NC NC

Notes: *1 In modes 1, 3, 5, and 6 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected

after a reset, but they can be changed by software.

*2 In modes 2 and 4 the D0 to D7 functions of pins P40/D0 to P4 7/D7 are selected after a

reset, but they can be changed by software.

*3 For the H8/3048 ZTAT version, H8/3048F version, H8/3048 mask ROM version,

H8/3047 mask ROM version, H8/3045 mask ROM version, and H8/3044 mask ROM

version, this pin is also used as the VCC terminal.

*4 For the H8/3048 ZTAT version, H8/3048F version, H8/3048 mask ROM version,

H8/3047 mask ROM version, H8/3045 mask ROM version, and H8/3044 mask ROM

version, this pin is used as the RESO terminal.

Rev. 6.0, 09/02, page 15 of 876

1.3.3 Pin Functions

Table 1.4 summarizes the pin functions.

Table 1.4 Pin Functio ns

Type Symbol Pin No. I/O Name and Function

Power VCC 1, 35, 68 Input Power: For connection to the power supply.

Connect all VCC pins to the system power

supply.

VSS 11, 22, 44,

57, 65, 92 Input Ground: For connection to ground (0 V).

Connect all VSS pins to the 0-V system

power supply.

Clock XTAL 67 Input For connection to a crystal resonator.

For examples of crystal resonator and

external clock input, see section 20, Clock

Pulse Generator.

EXTAL 66 Input For connection to a crystal resonator or

input of an external clock signal. For

examples of crystal resonator and external

clock input, see section 20, Clock Pulse

Generator.

φ61 Output System clock: Supplies the system clock

to external devices.

Operating mode

control MD2 to MD075 to 73 Input Mode 2 to mode 0: For setting the

operating mode, as follows. Inputs at these

pins must not be changed during operation.

MD2MD1MD0Operating Mode

000—

0 0 1 Mode 1

0 1 0 Mode 2

0 1 1 Mode 3

1 0 0 Mode 4

1 0 1 Mode 5

1 1 0 Mode 6

1 1 1 Mode 7

Rev. 6.0, 09/02, page 16 of 876

Type Symbol Pin No. I/O Name and Function

System control RES 63 Input Reset input: When driven low, this pin

resets the chip

RESO

(RESO/VPP)

10 Output Reset output: For the mask ROM version,

outputs a reset signal to external devices

Also used as a power supply for on -board

programming of the flash memory version

with dual power supply.

STBY 62 Input Standby: When driven low, this pin forces a

transition to hardware standby mode

BREQ 59 Input Bus request: Used by an external b us

master to request the bus right

BACK 60 Output Bus request acknowledge: Indicates that

the bus has been granted to an external bus

master

Interrupts NMI 64 Input Nonmaskable interrupt: Requests a

nonmaskable interrupt

IRQ5 to

IRQ0

17, 16,

90 to 87 Input Interrupt request 5 to 0: Maskable

interrupt request pins

Address bus A23 to A097 to 100,

56 to 45,

43 to 36

Output Address bus: Outputs address signals

Data bus D15 to D034 to 23,

21 to 18 Input/

output Data bus: Bidirectional data bus

Bus control CS7 to CS08, 97 to 99,

88 to 91 Output Chip select: Select signals for areas 7 to 0

AS 69 Output Address strobe: Goes low to indicate valid

address output on the address bus

RD 70 Output Read: Goes low to indicate read ing from

the external address space

HWR 71 Output High write: Goes low to indicate writing to

the external address space; indicates valid

data on the upper data bus (D15 to D8).

LWR 72 Output Low write: Goes low to indicate writing to

the external address space; indicates valid

data on the lower data bus (D7 to D0).

WAIT 58 Input Wait: Requests insertion of wait states in

bus cycles during access to the external

address spa ce

Rev. 6.0, 09/02, page 17 of 876

Type Symbol Pin No. I/O Name and Function

RFSH 87 Output Refresh: Indicates a refresh cycle

Refresh

controller CS388 Output Row address strobe RAS

RASRAS

RAS: Row address

strobe signal for DRAM connected to area 3

RD 70 Output Column address strobe CAS

CASCAS

CAS: Column

address strobe signal for DRAM connected

to area 3; used with 2WE DRAM.

Write enable WE

WEWE

WE: Write enable si gnal for

DRAM connected to area 3; used with

2CAS DRAM.

HWR 71 Output Upper write UW

UWUW

UW: Write enable signal for

DRAM connected to area 3; used with 2WE

DRAM.

Upper column address strobe UCAS

UCASUCAS

UCAS:

Column address strobe signal for DRAM

connected to area 3; used with 2CAS

DRAM.

LWR 72 Output Lower write LW

LWLW

LW: Write enable signal for

DRAM connected to area 3; used with 2WE

DRAM.

Lower column address strobe LCAS

LCASLCAS

LCAS:

Column address strobe signal for DRAM

connected to area 3; used with 2CAS

DRAM.

DREQ1,

DREQ0

9, 8 Input DMA request 1 and 0: DMAC activation

requests

DMA controller

(DMAC)

TEND1,

TEND0

94, 93 Output Transfer end 1 and 0: These signals

indicate that the DMAC has ended a data

transfer

TCLKD to

TCLKA 96 to 93 Input Clock input D to A: External clock inputs16-bit integrated

timer unit (ITU)

TIOCA4 to

TIOCA0

4, 2, 99,

97, 95 Input/

output Input capture/output compare A4 to A0:

GRA4 to GRA0 output compare or input

capture, or PWM output

TIOCB4 to

TIOCB0

5, 3, 100,

98, 96 Input/

output Input capture/output compare B4 to B0:

GRB4 to GRB0 output compare or input

capture

TOCXA46 Output Output compare XA4: PWM output

TOCXB47 Output Output compare XB4: PWM output

Rev. 6.0, 09/02, page 18 of 876

Type Symbol Pin No. I/O Name and Function

Programmable

timing pattern

controller (TPC)

TP15 to TP09 to 2,

100 to 93 Output TPC output 15 to 0: Pulse output

TxD1, TxD013, 12 Output Transmit data (channels 0 and 1):

SCI data output

Serial

communication

interface (SCI) RxD1, RxD015, 14 Input Receive data (channels 0 and 1):

SCI data input

SCK1, SCK017, 16 Input/

output Serial clock (channels 0 and 1):

SCI clock input/output

A/D converter AN7 to AN085 to 78 Input Analog 7 to 0: Analog input pins

ADTRG 9 Input A/D trigger: External trigger input for

starting A/D conversion

D/A converter DA1, DA085, 84 Output Analog output: Analog output from the D/A

converter

A/D and D/A

converters AVCC 76 Input Power supply pin for the A/D and D/A

converters. Connect to the system power

supply (VCC) when not using the A/D and

D/A converters.

AVSS 86 Input Ground pin for the A/D and D/A converters.

Connect to system ground (VSS).

VREF 77 Input Reference voltage input pin for the A/D and

D/A converters. Connect to the system

power supply (VCC) when not using the A/D

and D/A converters.

I/O ports P17 to P1043 to 36 Input/

output Port 1: Eight input/output pins.

The direction of each pin can be selected in

the port 1 data direction register (P1DDR).

P27 to P2052 to 45 Input/

output Port 2: Eight input/output pins.

The direction of each pin can be selected in

the port 2 data direction register (P2DDR).

P37 to P3034 to 27 Input/

output Port 3: Eight input/output pins.

The direction of each pin can be selected in

the port 3 data direction register (P3DDR).

P47 to P4026 to 23,

21 to 18 Input/

output Port 4: Eight input/output pins.

The direction of each pin can be selected in

the port 4 data direction register (P4DDR).

P53 to P5056 to 53 Input/

output Port 5: Four input/output pins. The direction

of each pin can be selected in the port 5

data direction register (P5DDR).

Rev. 6.0, 09/02, page 19 of 876

Type Symbol Pin No. I/O Name and Function

I/O ports P66 to P6072 to 69,

60 to 58 Input/

output Port 6: Seven input/output pins. The

direction of each pin can be selected in the

port 6 data direction register (P6DDR).

P77 to P7085 to 78 Input Port 7: Eight input pins

P84 to P8091 to 87 Input/

output Port 8: Five input/output pins. The direction

of each pin can be selected in the port 8

data direction register (P8DDR).

P95 to P9017 to 12 Input/

output Port 9: Six input/output pins. The direction

of each pin can be selected in the port 9

data direction register (P9DDR).

PA7 to PA0100 to 93 Input/

output Port A: Eight input/output pins. The

direction of each pin can be selected in the

port A data direction register (PADDR).

PB7 to PB09 to 2 Input/

output Port B: Eight input/output pins. The

direction of each pin can be selected in the

port B data direction register (PBDDR).

Rev. 6.0, 09/02, page 20 of 876

1.4 Differences between H8/3048F and H8/3048F-ONE

Table 1.5 shows the differences between the H8/3048F (dual power supply model) and H8/3048F-

ONE (single power supply model).

Table 1.5 Differences between H8/3048F and H8/3048F-ONE

Item Models with Dual Powe r Supply:

H8/3048F Models with Single Power Supply:

H8/3048F-ONE*

specifications Pin 1: VCC Pin 1: VCL (when a model which

operates at 5 V is used)

Connected to VSS with 0.1 µF externally

applied. Pin 1 becomes VCC when a

model which operates at 3 V is used.

Pin 10: VPP/RESO Pin 10: FWE

ROM/RAM 128-kbyte flash memory with dual

power supply, RAM: 4 kbytes 128-kbyte flash memory with single

power supply, RAM: 4 kbytes

Units of on-

board writing Writing in 1-byte units Writing in 128-byte units

Write/erase

voltage 12 V is externally applied from VPP pin Application of 12 V is not required.

VCC single power supply

VPP pin functions Multiplexes with RESO FWE function only (no RESO function)

Boot mode

settings

Cancelled by reset

= 12 V

Mode 5

Mode 6

Mode 7

MD2

12 V

MD1

MD0

Set to mode 1 in mode 5

Set to mode 2 in mode 6

Set to mode 3 in mode 7

Cancelled by reset

FWE = 1

Mode 5

Mode 6

Mode 7

MD2

MD1

MD0

Settings for

user program

mode

Cancelled by reset

= 12 V

Mode 5

Mode 6

Mode 7

MD2

MD1

MD0

Cancelled by reset

FWE = 1

Mode 5

Mode 6

Mode 7

MD2

MD1

MD0

Prewrite

processing Necessary before erasing Not necessary

Erasing blocks More than one block can be erased at

the same time (verifies in block units

and erases only the unerased blocks)

Erases in one block units. More than

one block cannot be erased at the same

time (the erasing flow is different)

Rev. 6.0, 09/02, page 21 of 876

Item Models with Dual Powe r Supply:

H8/3048F Models with Single Power Supply:

H8/3048F-ONE*

Write

processing Before writing, sets the block with the

address to be written to EBR1/EBR2 No setting

FLMCR

VPP VPPE——EV PV E P

FLMCR (H'FF40)

FWE SWE ESU PSU EV PV E P

FLMCR1 (H'FF40)

FLER ———————

FLMCR2 (H'FF41)

EBR

LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0

EBR1 (H'FF42)

SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0

EBR2 (H'FF43)

More than one block can be selected

(setting for writing/erasing)

EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

EBR (H'FF42)

Only one block can be sele cted (s etti ng

for erasing)

RAMCR

FLER ———

RAMS RAM2 RAM1 RAM0

RAMCR (H'FF48)

————

RAMS RAM2 RAM1

—

RAMCR (H'FF47)

Division of

flash memory

block

Division in 16 blocks

16 kbytes × 7: LB0 to LB6

12 kbytes × 1: LB7

512 kbytes × 8: SB0 to SB7

LB0 (16 kbytes)

LB1 (16 kbytes)

LB2 (16 kbytes)

LB3 (16 kbytes)

LB4 (16 kbytes)

LB5 (16 kbytes)

LB6 (16 kbytes)

LB7 (12 kbytes)

SB0 (512 bytes)

SB1 (512 bytes)

SB2 (512 bytes)

SB3 (512 bytes)

SB4 (512 bytes)

SB5 (512 bytes)

SB6 (512 bytes)

SB7 (512 bytes)

H'00000

H'1FFFF

Flash memory

Division in 8 blocks

1 kbyte × 4: EB0 to EB3

28 kbytes × 1: EB4

32 kbytes × 3: EB5 to EB7

EB0 (1 kbyte)

EB1 (1 kbyte)

EB2 (1 kbyte)

EB3 (1 kbyte)

EB4 (28 kbytes)

EB5 (32 kbytes)

EB6 (32 kbytes)

EB7 (32 kbytes)

H'00000

H'1FFFF

Flash memory

Rev. 6.0, 09/02, page 22 of 876

Item Models with Dual Powe r Supply:

H8/3048F Models with Single Power Supply:

H8/3048F-ONE*

Division of RAM

emulation block

H'EF10 H'00000

H'1EFFF

H'1F000

H'1F200

H'1F400

H'1F600

H'1F800

H'1FA00

H'1FC00

H'1FE00

H'1FFFF

H'FF0F

H'F000

H'F1FF

On-chip RAM Flash memory

H'EF10 H'00000

H'00400

H'00800

H'00C00

H'01000

H'1FFFF

H'FF0F

H'F000

H'F3FF

On-chip RAM Flash memory

Reset during

operation The RES signal must be kept low during

at least 6 system clock (6

) cycles.

(RES pulse width tRESW = min. 6.0 tcyc)

The RES signal must be kept low during

at least 20 system clock (20

) cycles.

(RES pulse width tRESW = min. 20 tcyc)

A/D ADCR ADCR (H'FFE9)

Initial value: H'7F

Only bit 7 can be read or written.

Other bits are reserved and always read

as 1; writing to these bits is invalid.

ADCR (H'FFE9)

Initial value: H'7E

Only bit 7 can be read or written.

Bit 0 is reserved and must not be set to

Other bits are reserved and always read

as 1; writing to these bits is invalid.

WDT RSTCSR RSTCSR (H'FFAB)

Initial value: H'3F

Only bits 7 and 6 can be read or written.

Other bits are reserved and always read

as 1; writing to these bits is invalid.

RSTCSR (H'FFAB)

Initial value: H'3F

Only bit 7 can be read or written.

Bit 6 is reserved and must not be set to

Other bits are reserved and always read

as 1; writing to these bits is invalid.

Rev. 6.0, 09/02, page 23 of 876

Item Models with Dual Powe r Supply:

H8/3048F Models with Single Power Supply:

H8/3048F-ONE*

Clock oscillator

settling time

(SYSCR STS2–

STS0)

Setting of standby timer select

bits 2 to 0

STS2

STS1

STS0

—

Description

8,192 states

16,384 states

32,768 states

65,536 states

131,072 states

1,024 states

Illegal setting

Setting of standby timer select

bits 2 to 0

STS2

STS1

STS0

Description

8,192 states

16,384 states

32,768 states

65,536 states

131,072 states

262,144 states

1,024 states

Illegal setting

Details on flash

memory Refer to section 19, Flash Memory

(H8/3048F, Dual Power Supply). Refer to section 18, Flash Memory

(H8/3048F-ONE, Single Power Supply)

Electrical

characteristics

(clock rate)

Clock rate: 1 to 16 MHz

Refer to section 22, Table 22.1

Electrical Characteristics of H8/3048

Series Products.

Clock rate: 2 to 25 MHz

Refer to section 21, Table 21.1

Electrical Characteristics of H8/3048

Series Products.

List of registers Refer to appendix B, Table B.1

Comparison of H8/3048 Series Internal

I/O Register Specification

Refer to appendix B, Table B.1

Comparison of H8/3048 Series Internal

I/O Register Specification

Refer to appendix B.1, Addresses

(For H8/3048F, H8/3048ZTAT,

H8/3048 mask-ROM, H8/3047 mask-

ROM, H8/3045 mask-ROM, and

H8/3044 mask-ROM Versions)

Refer to appendix B.1, Addresses

(For H8/3048F-ONE)

On-chip

emulator — On-chip emulator (E10T)

Note: *Refer to the “H8/3048F-ONE, H8/3048F-ZTAT™ Hardware Manual” fo r information about

H8/3048F-ONE.

Rev. 6.0, 09/02, page 24 of 876

Rev. 6.0, 09/02, page 25 of 876

Section 2 CPU

2.1 Overview

The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general

registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

2.1.1 Features

The H8/300H CPU has the following features.

• Upward compatibility with H8/300 CPU

Can execute H8/300 Series object programs

• General-register architecture

Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)

• Sixty-two basic instructions

 8/16/32-bit data transfer and arithmetic an d logic instructions

 Multiply and divide instructions

 Powerful bit-manipulation instructions

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]

 Register indirect with post-increment or pre-decremen t [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, or @aa:24]

 Immediate [#xx:8, #xx: 16, or #xx: 3 2]

 Program-counter relativ e [@(d:8, PC) or @(d:16, PC)]

 Memory indirect [@@aa:8]

• 16-Mbyte linear address space

• High-speed operation

 All frequen tly-used instruction s ex ecute in two to four states

 Maximum clock frequency:

18 MHz (H8/3048ZTAT, H8/3048 mask ROM, H8/3047 mask ROM, H8/3045 mask

ROM, H8/3044 mask ROM)

16 MHz (H8/3048F)

 8/16/32-bit register-register add/subtract: 111 ns @ 18 MHz/125 ns @ 16 MHz

 8 × 8-bit register-register multiply: 778 ns @ 18 MHz/875 ns @ 16 MHz

Rev. 6.0, 09/02, page 26 of 876

 16 ÷ 8-bit register-register divide: 778 ns @ 18 MHz/875 ns @ 16 MHz

 16 × 16-bit register-register multiply : 1,221 ns @ 18 MHz/1 , 375 ns @ 16 MHz

 32 ÷ 16-bit register-register divide: 1,221 ns @ 18 MHz/1,375 ns @ 16 MHz

• Two CPU operating modes

 Normal mode (not available in the H8/3048 Series)

 Advanced mode

• Low-power mode

Transition to power-down state by SLEEP instruction

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8/300H has the following enhancements.

• More general registers

Eight 16-bit registers have been added.

• Expanded address space

 Advanced mode supports a maximum 16 -Mbyte address space.

 Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

(Normal mode is not available in the H8/3048 Series.)

• Enhanced addressing

The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions

 Data transfer, arithmetic, and logic in structions can operate on 32-bit data.

 Signed multiply/divide instructions and other instructions have been added.

Rev. 6.0, 09/02, page 27 of 876

2.2 CPU Operating Modes

The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a

maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2.1.

The H8/3048 Series can be used only in advanced mode. (Information from this point on will

apply to advanced mode unless otherwise stated.)

CPU operating modes

Normal mode

Advanced mode

Maximum 64 kbytes, program

and data areas combined

Maximum 16 Mbytes, program

and data areas combined

Figure 2.1 CPU Operating Modes

Rev. 6.0, 09/02, page 28 of 876

2.3 Address Space

The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3048 Series has various

operating modes (MCU modes), so me providing a 1-Mbyte address space, the others supporting

the full 16 Mby tes.

Figure 2.2 shows the address ranges of the H8/3048 Series. For further details see section 3.6,

Memory Map in Each Operating Mode.

The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are

ignored.

H'00000

H'FFFFF

H'000000

H'FFFFFF

a. 1-Mbyte modes b. 16-Mbyte modes

Figure 2.2 Memory Map

Rev. 6.0, 09/02, page 29 of 876

2.4 Register Configuration

2.4.1 Overview

The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers:

general registers and control registers.

Figure 2.3 CPU Internal Registers

Rev. 6.0, 09/02, page 30 of 876

2.4.2 G eneral Registers

The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally

alike and can be used without distinction between data registers and address registers. When a

general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.

When the general registers are used as 32-bit registers or as address registers, they are designated

by the letters ER (E R0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R

(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit

registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and

RL (R0L to R7 L). These registers are functionally equivalent, providing a maximum sixteen 8-bit

registers.

Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected

independently.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

ER0 to ER7

E registers

(extended registers)

E0 to E7

R registers

R0 to R7

RH registers

R0H to R7H

RL registers

R0L to R7L

Figure 2.4 Usage of General Registers

Rev. 6.0, 09/02, page 31 of 876

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in ex ception handling and subroutine calls. Figure 2.5 shows the

stack.

Free area

Stack area

SP (ER7)

Figure 2.5 Stack

2.4.3 Control Registers

The control registers are the 24-bit program counter (PC) and the 8-bit condition code register

(CCR).

Program Counter (PC): This 24-bit counter ind icates th e address of the next instru ction the CPU

will execute. The leng th of all CPU instructions is 2 by tes ( one word) or a multiple of 2 bytes, so

the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is

regarded as 0.

Condition Code Register (CCR): This 8-bit register contains internal CPU status information,

including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and

carry (C) flags.

• Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is

accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling

sequence.

• Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the

LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt

mask bit. Fo r details see section 5, Interr up t Controller.

• Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or

NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and

cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is

executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise.

When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if

there is a carry or borrow at bit 27, and cleared to 0 otherwise.

Rev. 6.0, 09/02, page 32 of 876

• Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC,

and XORC instructions.

• Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data.

• Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

• Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at

other times.

• Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

 Add instructions, to indicate a carry

 Subtract instructions, to indicate a borrow

 Shift and r otate instructions, to store the value shifted out of the end b it

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,

STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional

branch (Bcc) instructions.

For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and

UI bits, see section 5, Interrupt Controller.

2.4.4 Initial CPU Register Values

In reset exception handling, PC is initialized to a value loaded from the vector table, and the I b it

in CCR is set to 1 . The other CCR bits an d the general registers are not initialized. In particular,

the stack pointer (ER7) is not initialized. The stack pointer must therefore be initialized by an

MOV.L instruction executed immediately after a reset.

Rev. 6.0, 09/02, page 33 of 876

2.5 Data Formats

The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32 -bit

(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1,

2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as

two digits of 4-bit BCD data.

2.5.1 G eneral Register Data Formats

Figures 2.6 and 2.7 show the data formats in general registers.

RnH

RnL

RnH

RnL

RnH

RnL

1-bit data

4-bit BCD data

Byte data

6543210

Don’t care

76543210

Don’t care

Lower digitUpper digit

743

Lower digitUpper digit

Don’t care 0

Don’t care

MSB LSB

Don’t care 70

MSB LSB

Data Type Data Format

General

Figure 2.6 General Register Data Formats (1)

Rev. 6.0, 09/02, page 34 of 876

ERn

Word data

Longword data

15 0

MSB LSB

General

RegisterData Type Data Format

15 0

MSB LSB

31 16

MSB

15 0

LSB

Legend

ERn:

En:

Rn:

RnH:

RnL:

MSB:

LSB:

General register

General register E

General register R

General register RH

General register RL

Most significant bit

Least significant bit

Figure 2.7 General Register Data Formats (2)

Rev. 6.0, 09/02, page 35 of 876

2.5.2 Memory Data Formats

Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and

longword data on memory, but word or longword data must begin at an even address. If an attempt

is made to access word or longword data at an odd address, no address erro r occurs but the least

significant bit of the address is regarded as 0, so the access starts at the preceding address. This

also applies to instruction f e tches.

76543210Address L

Address L

LSB

MSB

LSB

MSB LSB

1-bit data

Byte data

Word data

Longword data

AddressData Type Data Format

Address 2M

Address 2M + 1

Address 2N

Address 2N + 1

Address 2N + 2

Address 2N + 3

Figure 2.8 Memory Data Formats

When ER7 (SP) is used as an address register to access the stack, the operand size should be word

size or longword size.

Rev. 6.0, 09/02, page 36 of 876

2.6 Instruction Set

2.6.1 Instruction Set Overview

The H8/300H CPU has 62 types of instructions, which are classified in table 2.1.

Table 2.1 Instruction Classification

Function Instruction Types

Data transfer MOV, PUSH*1, POP*1, MOVTPE*2, MOVFPE*23

Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,

DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS,

EXTU

Logic operations AND, OR, XOR, NOT 4

Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8

Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,

BXOR, BIXOR, BLD, BILD, BST, BIST 14

Branch Bcc*3, JMP, BSR, JSR, RTS 5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9

Block data transfer EEPMOV 1

Total 62 types

Notes: *1 POP.W Rn is identical to MOV.W @SP+, Rn.

PUSH.W Rn is identical to MOV.W Rn, @–SP.

POP.L ERn is identical to MOV.L @SP+, Rn.

PUSH.L ERn is identical to MOV.L Rn, @–SP.

*2 Not available in the H8/3048 Series.

*3 Bcc is a generic branching instruction.

Rev. 6.0, 09/02, page 37 of 876

2.6.2 Instruct ions and Addressing Mo des

Table 2.2 indicates the instructions available in the H8/300H CPU.

Table 2.2 Instructions and Addressing Modes

Addr ess in g Mo des

Function Instruction

#xx

@ERn

@(d:16,ERn)

@(d:24,ERn)

@ERn+/@–ERn

@aa:8

@aa:16

@aa:24

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

MOV BWL BWL BWL BWL BWL BWL B BWL BWL — — — —

Data

transfer POP, PUSH ——————————— —WL

MOVFPE*,

MOVTPE*———————B—————

ADD, CMP BWLBWL———————————Arithmetic

operations SUB WLBWL———————————

ADDX, SUBX B B———————————

ADDS, SUBS — L—————— —————

INC, DEC —BWL———————————

DAA, DAS —B————————— ——

MULXU, MULXS,

DIVXU, DIVXS —BW———————————

NEG —BWL———————————

EXTU, EXTS —WL———————————

AND, OR, XORBWLBWL———————————

Logic

operations NOT —BWL———————————

Shift instructions —BWL———————————

Bit manipulation —B B———B——————

Branch Bcc, BSR ————————— ——

JMP, JSR — — ————— —— —

RTS ————————————

TRAPA ————————————System

control RTE ————————————

SLEEP ————————————

LDC B BWWWW—WW————

STC —BWWWW—WW————

ANDC, ORC,

XORC B————————————

NOP ————————————

Block data transfer ————————————BW

Legend

B: Byte

W: Word

L: Longword

Note: * Not availabe in the H8/3048 Series.

Rev. 6.0, 09/02, page 38 of 876

2.6.3 Tables of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation

used in these tables is defined next.

Operation Notation

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register or address register)

(EAd) Destination operand

(EAs) Source operand

CCR Condition cod e regist er

N N (negative) flag of CCR

Z Z (zero) flag of CCR

V V (overflow) flag of CCR

C C (carry) flag of CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

– Subtraction

×Multiplication

÷Division

∧AND logical

∨OR logical

⊕Exclusive OR logical

→Move

¬ NOT (logical complement)

:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length

Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).

Rev. 6.0, 09/02, page 39 of 876

Table 2.3 Data Transfer Instructions

Instruction Size*Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general

MOVFPE B (EAs) → Rd

Cannot be used in the H8/3048 Series.

MOVTPE B Rs → (EAs)

Cannot be used in the H8/3048 Series.

POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to

MOV.W @SP+, Rn. Similarly , POP.L ERn is identical to MOV.L

@SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a general register onto the stack. PUSH.W Rn is identical to

MOV.W Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L

ERn, @–SP.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

Rev. 6.0, 09/02, page 40 of 876

Table 2.4 Arithmetic Operation Instructions

Instruction Size*Function

ADD, SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs additi on or subtraction on data in two general registers, or

on immediate data and data in a general register. (Immediate byte

data cannot be subtracted from data in a general register. Use the

SUBX or ADD instruction.)

ADDX, SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on data in two

general registers, or on immediate data and data in a general

INC, DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte

operands can be incremented or decremented by 1 only.)

ADDS, SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit

DAA, DAS B Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a general register

by referring to CCR to produce 4-bit BCD data.

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general registers:

either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general registers:

either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

Rev. 6.0, 09/02, page 41 of 876

Instruction Size*Function

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers: either

16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16

bits → 16-bit quotient and 16-bit remainder.

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16

bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits

→ 16-bit quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general

result.

NEG B/W/L 0 – Rd → Rd

Takes the two’s complement (arithmetic complement) of data in a

general register.

EXTS W/L Rd (sign extension) → Rd

Extends byte data in the lower 8 bits of a 16-bit register to word data,

or extends wo rd data in the lower 16 bits of a 32-bit register to

longword data, by extending the sign bit.

EXTU W/L Rd (zero extension) → Rd

Extends byte data in the lower 8 bits of a 16-bit register to word data,

or extends wo rd data in the lower 16 bits of a 32-bit register to

longword data, by padding with zeros.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

Rev. 6.0, 09/02, page 42 of 876

Table 2.5 Logic Operation Instructions

Instruction Size*Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logi cal AND operation on a general register and another

general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another

general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logi cal exclusive OR operation on a general register and

another general register or immediate data.

NOT B/W/L ¬ Rd → Rd

Takes the one’s complement of general register contents.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

Table 2.6 Shift Instructions

Instruction Size*Function

SHAL,

SHAR B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

SHLL,

SHLR B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

ROTL,

ROTR B/W/L Rd (rotate ) → Rd

Rotates general register contents.

ROTXL,

ROTXR B/W/L Rd (rotate ) → Rd

Rotates general register contents through the carry bit.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

Rev. 6.0, 09/02, page 43 of 876

Table 2.7 Bit Manipulation Instructions

Instruction Size*Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1.

The bit numbe r is specified by 3-bit immediate data or the lower 3

bits of a general register .

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0.

The bit numbe r is specified by 3-bit immediate data or the lower 3

bits of a general register .

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The

bit number is specified by 3-bit immediate data or the lower 3 bits of

a general register.

BTST B ¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and

sets or clears the Z flag accordingly. The bit number is specified by

3-bit immediate data or the lower 3 bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general register or

memory operand and stores the result in the carry flag.

BIAND B C ∧ [¬ (<bit-No.> of <EAd>)] → C

ANDs the carry flag with the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

Note: *Size refers to the operand size.

B: Byte

Rev. 6.0, 09/02, page 44 of 876

Instruction Size*Function

BOR B C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general register or

memory operand and stores the result in the carry flag.

BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C

ORs the carry flag with the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-O Rs the carry flag wit h a specif ied bit in a genera l regist er

or memory operand and stores the result in the carry flag.

BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C

Exclusive-ORs the carry flag with the inverse of a specified bit in a

general register or memory operand and stores the result in the carry

flag.

The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory operand to

the carry flag.

BILD B ¬ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or

memory operand to the carry flag.

The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register

or memory operand.

BIST B C → ¬ (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a

general register or memory operand.

The bit number is specified by 3-bit immediate data.

Note: *Size refers to the operand size.

B: Byte

Rev. 6.0, 09/02, page 45 of 876

Table 2.8 Branching Instruct ions

Instruction Size Function

Bcc — Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic Description Condition

BRA (BT) Always (true) Always

BRN (BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

Bcc (BHS) Carry cl ear (high or same) C = 0

BCS (BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z ∨ (N ⊕ V) = 0

BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP — Branches unconditionally to a specified address

BSR — Branches to a subroutine at a specified address

JSR — Branches to a subroutine at a specified address

RTS — Returns from a subroutine

Rev. 6.0, 09/02, page 46 of 876

Table 2.9 System Control Instructions

Instruction Size*Function

TRAPA — Starts trap-instruction exception handling

RTE — Returns from an exception-handling routine

SLEEP — Causes a transition to the power-down state

LDC B/W (EAs) → CCR

Moves the sour ce opera nd cont ents to the condit ion cod e register.

The condition code register size is one byte, but in transfer from

memory, data is read by word access.

STC B/W CCR → (EAd)

Transfers the CCR contents to a destination location. The condition

code register size is one byte, but in transfer to memory, data is

written by word access.

ANDC B CCR ∧ #IMM → CCR

Logically ANDs the condition code register with immediate data.

ORC B CCR ∨ #IMM → CCR

Logically ORs the condition code register with immediate data.

XORC B CCR ⊕ #IMM → CCR

Logically ex clu si ve-O Rs t he cond iti on code register with imm ediat e

data.

NOP — PC + 2 → PC

Only increments the program counter.

Note: *Size refers to the operand size.

B: Byte

W: Word

Rev. 6.0, 09/02, page 47 of 876

Table 2.10 Block Transfer Instruction

Instruction Size Function

EEPMOV.B — if R4L ≠ 0 then

repeat @ER5+ → @ER6+, R4L – 1 → R4L

until R4L = 0

else next;

EEPMOV.W — if R4 ≠ 0 then

repeat @ER5+ → @ER6+, R4 – 1 → R4

until R4 = 0

else next;

Transfers a data block according to parameters set in general

registers R4L or R4, ER5, and ER6.

R4L or R4: Size of block (bytes)

ER5: Starting source address

ER6: Starting destination address

Execution of the next instruction begins as soon as the transfer is

completed.

Rev. 6.0, 09/02, page 48 of 876

2.6.4 Basic Instruction Formats

The H8/300H instr uctions consist of 2-byte (1-word) units. An instruction consists of an operation

field (OP field), a register f ield ( r field) , an eff ectiv e addr ess extension (EA field), and a condition

field (cc).

Operation Field: Indicates the function of the instruction, the addressing mode, and the operation

to be carried out on the operand. The op eration field always includes the first 4 bits of the

instruction. Some instructions have two operation fields.

registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register

field.

Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute

address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the

first 8 bits are 0 (H'00).

Condition Field: Specifies the branchin g condition of Bcc instructions.

Figure 2.9 shows examples of instruction formats.

op NOP, RTS, etc.

op rn rm

EA (disp)

Operation field only

ADD.B Rn, Rm, etc.

Operation field and register fields

MOV.B @(d:16, Rn), Rm

Operation field, register fields, and effective address extension

BRA d:8

Operation field, effective address extension, and condition field

op cc EA (disp)

Figure 2.9 Instruction Formats

Rev. 6.0, 09/02, page 49 of 876

2.6.5 Notes on Use of Bit Ma nipulation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the

byte, then write the byte back. Care is required when these instructions are used to access registers

with write-only bits, or to access ports.

The BCLR instruction can be used to clear flags in the internal I/O registers. In an interrupt-

handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the

flag ahead of time.

Step Description

1 Read Read data (byte unit) at the specif ied addr es s

2 Bit manipulation Modify the specified bit in the read data

3 Write Write the modified data (byte unit) to the specified address

In the following example, a BCLR instruction is executed on the data direction register (DDR) of

port 4.

P47 and P46 are set as input pins, and are inputting low-level and high-level signals, respectively.

P45 to P40 are set as output pins, and are in the low-level output state.

In this exam ple, the BCLR instruction is used to m a ke P40 an input port.

Before Execution of BCLR Instruction

P47P46P45P44P43P42P41P40

Input/output Input Input Output Output Output Output Output Output

DDR 00111111

DR 10000000

Execution of BCLR Instruction

BCLR #0, @P4DDR ; Execute BCLR instruction on DDR

After Execution of BCLR Instruction

P47P46P45P44P43P42P41P40

Input/output Output Output Output Output Output Output Output Input

DDR 11111110

DR 10000000

Rev. 6.0, 09/02, page 50 of 876

Explanation of BCLR Instruction

To execute the BCLR instru ction, the CPU begin s b y reading P4DDR. Since P4DDR is a wr ite-

only register, it is read as H'FF, even though its true value is H'3F.

Next the CPU clears bit 0 of the read data, changing the value to H'FE.

Finally, the CPU writes this value (H'FE) b ack to DDR to complete the BCLR instruction.

As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR

are set to 1, making P47 and P46 output pins .

The BCLR instruction can be used to clear flags in the internal I/O registers to 0. In an interrupt-

handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the

flag ahead of time.

2.7 Addressing Modes and Effective Address Calculation

2.7.1 Addressing Modes

The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses

a subset of these addressing modes. Arithmetic and logic instructions can use the register direct

and immediate modes. Data transfer instructions can use all addressing modes except program-

counter relative and memory indirect. Bit manipulation instructions use register direct, register

indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,

BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit

number in the operand.

Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16, ERn)/@(d:24, ERn)

4 Register indirect with post-increment

@ERn+

@–ERn

5 Absolute address @aa:8/@aa:16/@aa:24

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8, PC)/@(d:16, PC)

8 Memory indirect @@aa:8

Rev. 6.0, 09/02, page 51 of 876

1 Register Direct—Rn: The register field of the instruction code specifies an 8- , 16-, or 32-bit

R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit

registers.

2 Register Indirect—@ERn: The register field of the instruction code specifies an address

3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit

displacement contained in the instruction code is added to the contents of an address register

(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the

address of a memory operand. A 16-bit displacement is sign-extended when added.

4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) the lower 24 bits

of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is

added to the address register contents (32 bits) and the sum is stored in the address register.

The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or

longword access, the register value should be even.

• Register indirect with pre-decrement—@–ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instru ction code, and the lower 24 bits of th e result become the address of a memory

operand. The result is also stored in the address register. The value subtracted is 1 for byte

access, 2 for word access, or 4 for longword access. For word or longword access, the resulting

5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute

address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long

(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all

assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A

24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible

address ranges.

Rev. 6.0, 09/02, page 52 of 876

Table 2.12 Absolute Address Access Ranges

Absolute Address 1-Mbyte Modes 16-Mbyte Modes

8 bits (@aa:8) H'FFF00 to H'FFFFF

(1048320 to 1048575) H'FFFF00 to H'FFFFFF

(16776960 to 16777215)

16 bits (@aa:16) H'00000 to H'07FFF,

H'F8000 to H'FFFFF

(0 to 32767, 1015808 to 1048575)

H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

(0 to 32767, 16744448 to 16777215)

24 bits (@aa:24) H'00000 to H'FFFFF

(0 to 1048575) H'000000 to H'FFFFFF

(0 to 16777215)

6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit

(#xx:16), or 32-bit (#xx:32) immediate data as an operand.

The instruction codes of the ADDS, SUBS, INC, and DEC instruction s contain immediate data

implicitly. The instruction codes of some bit manipulatio n instructions contain 3-bit immediate

data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data

specifying a vector address.

7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and

BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-

extended to 24 bits and added to th e 24-bit PC contents to generate a 24-bit branch address. The

PC value to which the displacement is added is the address of the first byte of the next instruction,

so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768

bytes (–16383 to +16384 words) from the branch instruction. The resu lting value should be an

even number.

8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

instruction code contains an 8-bit absolute address specifying a memory operand. This memory

operand contains a branch address. The memory operand is accessed by longword access. The first

byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The

upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to

255 (H'000000 to H'0000FF). Note that the first part of this range is also the ex ception vector area.

For further details see section 5, Interrupt Controller.

Rev. 6.0, 09/02, page 53 of 876

Specified by @aa:8 Reserved

Branch address

Figure 2.10 Memory-Indirect Branch Address Specification

When a word-size or longword-size memory operand is specified, or when a branch address is

specified, if the specified memory address is odd, the least significant bit is regarded as 0. The

accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,

Memory Data Formats.

2.7.2 Effective Address Calculation

Table 2.13 explains how an effective address is calculated in each addressing mode. In the

1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to

generate a 20-bit effective address.

Rev. 6.0, 09/02, page 54 of 876

Table 2.13 Effective Address Calculation

No. Addressing Mode and

Instruction Format Effective Address

Calculation Effective Address

1 Register direct (Rn)

op rm rn

Operand is general

2 Register indirect (@ERn)

General register contents

31 0 0

rop

3 Register indirect with displacement

@(d:16, ERn)/@(d:24, ERn)

General register contents

Sign extension disp

31 0

23 0

op r disp

4. Register indirect with post-increment

or pre-decrement

@ERn+

General register contents

1, 2, or 4

31 0 0

@–ERn

General register contents

1 for a byte operand, 2 for a word

operand, 4 for a longword operand

1, 2, or 4

31 0

23 0

op r

Rev. 6.0, 09/02, page 55 of 876

No. Addressing Mode and

Instruction Format Effective Address

Calculation Effective Address

5 Absolute addr es s

@aa:8

@aa:16

@aa:24

08 7

016 15

op abs

abs

H'FFFF

Sign

exten-

sion

6 Immediate

#xx:8, #xx:16, or #xx:32

op IMM

Operand is imm ediate

data

7 Program-counter relative

@(d:8, PC) or @(d:16, PC)

disp

op disp

PC contents

Sign

exten-

sion

Rev. 6.0, 09/02, page 56 of 876

No. Addressing Mode and

Instruction Format Effective Address

Calculation Effective Address

8 Memory indi rect @@aa:8

• Normal mode

23 8 7

H'0000

op abs

abs

16 1515 Memory

contents

H'00

• Advanced mode

23 8 7

H'0000

op abs

abs

Memory contents

Legend:

r, rm, rn:Register field

op: Operation field

disp: Displacement

IMM: Immediate data

abs: Absol ute address

Rev. 6.0, 09/02, page 57 of 876

2.8 Processing States

2.8.1 Overview

The H8/300H CPU has five processing states: the program execution state, exception-handling

state, power-down state, reset state, and bus-released state. The power-down state includes sleep

mode, software standby mode, and hardware standby mode. Figu re 2.11 classifies the processing

states. Figure 2.13 indicates the state transitions.

Processing states Program execution state

Bus-released state

Reset state

Power-down state

The CPU executes program instructions in sequence

A transient state in which the CPU executes a hardware sequence

(saving PC and CCR, fetching a vector, etc.) in response to a reset,

interrupt, or other exception

The external bus has been released in response to a bus request

signal from a bus master other than the CPU

The CPU and all on-chip supporting modules are initialized and halted

The CPU is halted to conserve power

Sleep mode

Software standby mode

Hardware standby mode

Exception-handling state

Figure 2.11 Processing States

Rev. 6.0, 09/02, page 58 of 876

2.8.2 Program Execution State

In this state the CPU executes program instructions in normal sequence.

2.8.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from

the exception vector table and branches to that address. In interrupt and trap exception handling

the CPU references the stack pointer (ER7) and saves the program counter and condition code

Types of Exception Handling and Their Priority: Exception handling is performed for resets,

interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their

priority. Trap instruction exceptions are accepted at all times in the program execution state.

Table 2.14 Exception Handling Types and Priority

Priority Type of

Exception Detection Timing Start of Exception Handling

Reset Synchronized with clock Exception handling starts immediately

when RES changes from low to high

Interrupt End of instruction

execution or end of

exception handling*

When an interrupt is requested,

exception handling starts at the end of

the current instruction or current

exception-handling sequence

High

↑



Low Trap instruction When TRAPA instruction

is executed Exception handling starts when a trap

(TRAPA) instruction is executed

Note: *Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or

immediately after reset exception handling.

Figure 2.12 classifies the exception sources. For further details about exception sources, vector

numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt

Controller.

Rev. 6.0, 09/02, page 59 of 876

Exception

sources

Reset

Interrupt

Trap instruction

External interrupts

Internal interrupts (from on-chip supporting modules)

Figure 2.12 Classification of Exception Sources

Bus-released state

Exception-handling state

Reset state

Program execution state

Sleep mode

Software standby mode

Hardware standby mode

Power-down state

End of bus release

Bus request

End of bus

release Bus

request

End of

exception

handling

Exception

Interrupt

SLEEP

instruction

with SSBY = 0

SLEEP instruction

with SSBY = 1

NMI, IRQ , IRQ ,

or IRQ interrupt

= 1, = 0

= 1

*1*2

Notes: *1

From any state except hardware standby mode, a transition to the reset state occurs

whenever goes low.

From any state, a transition to hardware standby mode occurs when goes low.

Figure 2.13 State Transitions

Rev. 6.0, 09/02, page 60 of 876

2.8.4 Exception-Handling Sequences

Reset Exception Handling: Reset exception handling has the highest priority . The reset state is

entered when the RES signal goes low. Reset exception handling starts after that, when RES

changes from low to high. When reset exception handling starts the CPU fetches a start address

from the exception vector table and starts program execution from that address. All interrupts,

including NMI, are disabled during the reset exception-handling sequence and immediately after it

ends.

Interrupt Exception Handling and Trap Instruction Exception Handling: When these

exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the

program counter and condition code register on the stack. Next, if the UE bit in the system control

is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then

the CPU fetches a start address from the exception vector table and execution branches to that

address.

Figure 2.14 shows the stack after the exception-handling sequence.

SP–4

SP–3

SP–2

SP–1

SP (ER7)

Before exception

handling starts

SP (ER7)

SP+1

SP+2

SP+3

SP+4

After exception

handling ends

Stack area

CCR

Even

address

Pushed on stack

Legend

CCR:

SP: Condition code register

Stack pointer

Notes: 1.

PC is the address of the first instruction executed after the return from the

exception-handling routine.

Registers must be saved and restored by word access or longword access,

starting at an even address.

Figure 2.14 Stack Structure after Exception Handling

Rev. 6.0, 09/02, page 61 of 876

2.8.5 Bus-Released State

In this state the b us is released to a bus master o th e r than the CPU, in response to a b u s r eque st.

The bus masters other than the CPU are the DMA controller, the refresh controller, and an

external bu s ma ster . While the bus is released, the CPU ha lts ex cept for internal operatio ns.

Interrupt requests are not accepted. For details see section 6.3.7, Bus Arbiter Operation.

2.8.6 Reset State

When the RES input goes low all current processing stops and the CPU enters the reset state. The I

bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.

Reset exception handling starts when the RES signal changes from low to high.

The reset state can also be entered by a watchdog timer ov erflow. For details see section 12,

Watchdog Timer.

2.8.7 Power-Down State

In the power-down state the CPU stops operating to conserve power. There are three modes: sleep

mode, software standby mode, and hardware standby mode.

Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the

SSBY bit i s cleared to 0 in the system control register (SYSCR). CPU operations stop

immediately after execution of the SLEEP instruction, but the contents of CPU registers are

retained.

Softwa re Standby Mode: A transition to software standby mode is made if the SLEEP

instruction is executed while th e SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all

on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long

as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.

The I/O ports also remain in their existing states.

Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input

goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting

modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are

retained.

For further information see section 21, Power-Down State.

Rev. 6.0, 09/02, page 62 of 876

2.9 Basic Operational Timing

2.9.1 Overview

The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the

system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of

two or three states. The CPU uses different methods to access on-chip memory, the on-chip

supporting modules, and the external address space. Access to the external address space can be

controlled by the bus cont roll er.

2.9.2 O n-Chip Memory Access Timing

On-chip memory is accessed in two states. The data bus is 16 bits wide, p ermitting both byte an d

word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin

states.

T state

Bus cycle

Internal address bus

Internal read signal

Internal data bus

(read access)

Internal write signal

Internal data bus

(write access)

1T state

Read data

Address

Write data

Figure 2.15 On-Chip Memory Access Cycle

Rev. 6.0, 09/02, page 63 of 876

, , ,

Address bus

D to D

15 0

High

Address

High impedance

Figure 2.16 Pin States during On-Chip Memory Access

2.9.3 O n-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,

depending on the register being accessed. Figure 2.17 shows the on-chip supporting module access

timing. Figure 2.18 indicates the pin states.

Address bus

Internal read signal

Internal data bus

Internal write signal

Address

Internal data bus

T state

Bus cycle

1T state

2T state

Read

access

Write

access Write data

Read data

Figure 2.17 Access Cycle for On-Chip Supporting Modules

Rev. 6.0, 09/02, page 64 of 876

, , ,

1T2

Address bus

D to D

15 0

High

High impedance

Address

Figure 2.1 8 Pin States during Access to O n- Chip Supporting Mo dules

2.9.4 Access to External Address Space

The external address space is divided into eight areas (areas 0 to 7). Bus-controller settin g s

determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in

two or three states. For details see section 6, Bus Controller.

Rev. 6.0, 09/02, page 65 of 876

Section 3 MCU Operating Modes

3.1 Overview

3.1.1 Operating Mode Selection

The H8/3048 Series has seven operating modes (modes 1 to 7) that are selected by the mode pins

(MD2 to MD0) as indicated in table 3.1. The input at these pins determines the size of th e address

space and the initial bus mode.

Table 3.1 Operating Mode Selection

Mode Pins Description

Operating

Mode MD2MD1MD0Address Space Initial Bus

Mode*1On-Chip

ROM On-Chip

RAM

—000— ———

Mode 1 0 0 1 Expanded mode 8 bits Disabled Enabled*2

Mode 2 0 1 0 Expanded mode 16 bits Disabled Enabled*2

Mode 3 0 1 1 Expanded mode 8 bits Disabled Enabled*2

Mode 4 1 0 0 Expanded mode 16 bits Disabled Enabled*2

Mode 5 1 0 1 Expanded mode 8 bits Enabled Enabled*2

Mode 6 1 1 0 Expanded mode 8 bits Enabled Enabled*2

Mode 7 1 1 1 Single-chip advanced

mode — Enabled Enabled

Notes: *1 In modes 1 to 6, an 8-bit or 16-bit data bus can be selected on a per-area basis by

settings made in the area bus width control register (ABWCR). For details see section

6, Bus Controller.

*2 If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses.

For the address space size there are two choices: 1 Mbyte or 16 Mbytes. The external data bus is

either 8 or 16 bits wide depending on ABWCR settings. If 8-bit access is selected for all areas, the

external da ta bus is 8 bits wide. For d e tails see section 6, Bus Controller.

Modes 1 to 4 are externally expanded modes that enable access to external memory and periph eral

devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address sp ace

of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes.

Modes 5 and 6 are externally expanded modes that enable access to external memory an d

peripheral devices and also enable access to the on-chip ROM. Mode 5 supports a maximum

address space of 1 Mbyte. Mode 6 supports a maximum address space of 16 Mbytes.

Rev. 6.0, 09/02, page 66 of 876

Mode 7 is a single-chip mode that operates using the on-chip ROM, RAM, and internal I/O

registers, and makes all I/O po rts available. Mode 7 supports a 1-Mbyte address space.

The H8/3048 Series can be used only in modes 1 to 7. The inputs at the mode pins must select one

of these seven modes. The inputs at the mode pins must not be changed during operation.

3.1.2 Register Configuration

The H8/3048 Series has a mode control register (MDCR) that indicates the inpu ts at the mode pins

(MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers.

Table 3.2 Registers

Address*Name Abbreviation R/W Initial Value

H'FFF1 Mode control register MDCR R Undetermined

H'FFF2 System control regi ster SYSCR R/W H'0B

Note: * The lower 16 bits of the address are indicated.

3.2 Mode Control Register (MDCR)

MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3048

Series.

Bit

Initial value

Read/Write

—

MDS0

—

MDS2

—

MDS1

—

Reserved bits Mode select 2 to 0

Bits indicating the current

operating mode

Reserved bits

Note: Determined by pins MD to MD .*

Bits 7 and 6—Reserved: Read-only bits, always read as 1.

Bits 5 to 3—Reserved: Read-only bits, always read as 0.

Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins

MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to

MDS0 are read-only bits. The mode pin (MD2 to MD0) lev els are latched into these bits when

MDCR is read.

Rev. 6.0, 09/02, page 67 of 876

3.3 System Control Register (SYSCR)

SYSCR is an 8-bit register that controls the operation of the H8/3048 Series.

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

—

Software standby

Enables transition to software standby mode

User bit enable

Selects whether to use the UI bit in CCR

as a user bit or an interrupt mask bit

NMI edge select

Selects the valid edge

of the NMI input

Reserved bit

RAM enable

Enables or

disables

on-chip RAM

Standby timer select 2 to 0

These bits select the waiting time at

recovery from software standby mode

Bit 7—Sof t w are Standby (SSBY) : Enables transition to software standby mode. (For further

information abou t software standby mode see section 21, Power-Down State.)

When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear

this bit, write 0.

Bit 7: SSBY Description

0 SLEEP instruction causes transition to sleep mode (Initial value)

1 SLEEP instruction causes transition to software s tandby mode

Rev. 6.0, 09/02, page 68 of 876

Bits 6 to 4 —St andby Timer Select (STS2 to STS0): These bits select the len gth of time the CPU

and on-chip supporting modules wait for the internal clock oscillator to settle when software

standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so

that the waiting tim e will be at least 7 ms at the system clo c k rate. For further information about

waiting time selection, see section 21.4.3, Selection of Waiting Time for Exit from Software

Standby Mode.

Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description

0 0 0 Waiting time = 8,192 states (Initial value)

1 Waiting time = 16,384 states

1 0 Waiting time = 32,768 states

1 Waiting time = 65,536 states

1 0 0 Waiting time = 131,072 states

1 Waiting time = 1,024 states

1 — Illegal sett ing

Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a

user bit or an inter rup t m a sk bit.

Bit 3: UE Description

0 UI bit in CCR is used as an interrupt mask bit

1 UI bit in CCR is used as a user bit (Initial value)

Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.

Bit 2: NMIEG Description

0 An interrupt is requested at the falling edge of NMI (Initial value)

1 An interrupt is requested at the rising edge of NMI

Bit 1—Reserved: Read-only bit, always read as 1.

Bit 0—RA M Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized by th e rising edge of the RES signal. It is not initialized in software standby mode.

Bit 0: RAME Description

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initial value)

Rev. 6.0, 09/02, page 69 of 876

3.4 Operating Mode Descriptions

3.4.1 Mode 1

Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte

address space. Th e initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least

one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.

3.4.2 Mode 2

Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte

address space. Th e in itial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all

areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.

3.4.3 Mode 3

Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a

maximum 16-Mbyte address space. The initial b us mode after a reset is 8 bits, with 8-bit access to

all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to

16 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register

(BRCR). (In this mode A20 is always used for address output.)

3.4.4 Mode 4

Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a

maximum 16-Mbyte address space. The initial bu s mode after a reset is 16 bits, with 16-bit access

to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to

8 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always

used for address output.)

3.4.5 Mode 5

Ports 1, 2, and 5 can function as address pins A 19 to A0, permitting access to a maximum 1-Mbyte

address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus,

the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set

to 1. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least o ne area is

designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.

Rev. 6.0, 09/02, page 70 of 876

3.4.6 Mode 6

Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a

maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,

and 5 as an address bus, th e corresponding bits in their data direction registers (P1DDR, P2DDR,

and P5DDR) must be set to 1. For A23 to A21 outpu t, clear bits 7 to 5 of BRCR to 0 . (In th is mode

A20 is always used for address output.)

The initial bus mod e after a reset is 8 bits, with 8- b it access to all areas. If at least one area is

designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.

3.4.7 Mode 7

This mode operates using the on-chip ROM, RAM, and internal I/O registers. All I/O ports are

available. Mode 7 supports a 1-Mbyte address space.

3.5 Pin Functions in Each Operating Mode

The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3

indicates their functions in each op erating mode.

Table 3.3 Pin Functions in Each Mode

Port Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

Port 1 A7 to A0A7 to A0A7 to A0A7 to A0P17 to P10*2P17 to P10*2P17 to P10

Port 2 A15 to A8A15 to A8A15 to A8A15 to A8P27 to P20*2P27 to P20*2P27 to P20

Port 3 D15 to D8D15 to D8D15 to D8D15 to D8D15 to D8D15 to D8P37 to P30

Port 4 P47 to P40*1D7 to D0*1P47 to P40*1D7 to D0*1P47 to P40*1P47 to P40*1P47 to P40

Port 5 A19 to A16 A19 to A16 A19 to A16 A19 to A16 P53 to P50*2P53 to P50*2P53 to P50

Port A PA7 to PA4PA7 to PA4PA7 to PA5*3,

A20

PA7 to PA5*3,

A20

PA7 to PA4PA7 to PA5,

A20*3PA7 to PA4

Notes: *1 Initial state. The bus mode can be switched by settings in ABWCR. Thes e pins function

as P47 to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode.

*2 Initial state. These pins become address output pins when the corresponding bits in the

data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.

*3 Initi al state . A20 is always an address ou tput pin. PA7 to P A5 are switched over to A23 to

A21 output by writing 0 in bits 7 to 5 o f BRCR.

Rev. 6.0, 09/02, page 71 of 876

3.6 Memory Map in Each Operating Mode

Figure 3.1 shows a memory map of the H8/3048. Figure 3.2 shows a memory map of the H8/3047.

Figure 3.3 shows a memory map of the H8/3044. Figure 3.4 shows a memory map of the H8/3045.

The address space is divided into eight areas.

The initial bus mo de differs between modes 1 and 2, and also be tween mo d e s 3 and 4.

The address locations of the on-chip RAM and internal I/O registers differ between the 1-Mbyte

modes (modes 1, 2, 5, and 7) and 16-Mbyte modes (modes 3, 4, and 6). The address range

specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also

differs.

Rev. 6.0, 09/02, page 72 of 876

H'00000

H'000FF

H'07FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

Modes 1 and 2

(1-Mbyte expanded modes with

on-chip ROM disabled)

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

H'DFFFF

H'E0000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External address

space

Vector area

On-chip RAM *

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'F8000

H'FEF0F

H'FEF10

H'FFF00

H'FFF0F

H'FFF10

H'FFF1B

H'FFF1C

H'FFFFF

Note: External addresses can be accessed by disabling on-chip RAM.*

Modes 3 and 4

(16-Mbyte expanded modes with

on-chip ROM disabled)

H'000000

H'0000FF

H'007FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

H'1FFFFF

H'200000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External

address

space

Vector area

On-chip RAM *

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'FF8000

H'FFEF0F

H'FFEF10

H'FFFF00

H'FFFF0F

H'FFFF10

H'FFFF1B

H'FFFF1C

H'FFFFFF

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

Figure 3.1 H8/3048 Memory Map in Each Operating Mode

Rev. 6.0, 09/02, page 73 of 876

H'00000

H'000FF

H'07FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

Mode 5

(1-Mbyte expanded mode with

on-chip ROM enabled)

Mode 6

(16-Mbyte expanded mode with

on-chip ROM enabled)

Mode 7

(single-chip advanced mode)

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

H'DFFFF

H'E0000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External address

space

Vector area

On-chip ROM

On-chip RAM *

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'F8000

H'FEF0F

H'FEF10

H'FFF00

H'FFF0F

H'FFF10

H'FFF1B

H'FFF1C

H'FFFFF

H'00000

H'000FF

H'07FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

Vector area

On-chip ROM

On-chip RAM

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'FEF10

H'FFF00

H'FFF0F

H'FFF1C

H'FFFFF

H'1FFFF

H'F8000

Note: External addresses can be accessed by disabling on-chip RAM.*

On-chip ROM

H'000000

H'0000FF

H'007FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

H'1FFFFF

H'200000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 7

External

address

space

Vector area

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'01FFFF

H'020000

H'FFEF0F

H'FFEF10

H'FFFF00

H'FFFF0F

H'FFFF10

H'FFFF1B

H'FFFF1C

H'FFFFFF

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

On-chip RAM *

Area 6

H'FF8000

Figure 3.1 H8/3048 Memory Map in Each Operating Mode (cont)

Rev. 6.0, 09/02, page 74 of 876

H'00000

H'000FF

H'07FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

Modes 1 and 2

(1-Mbyte expanded modes with

on-chip ROM disabled)

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

H'DFFFF

H'E0000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External address

space

Vector area

On-chip RAM *

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'F8000

H'FEF0F

H'FEF10

H'FFF00

H'FFF0F

H'FFF10

H'FFF1B

H'FFF1C

H'FFFFF

Note: External addresses can be accessed by disabling on-chip RAM.*

Modes 3 and 4

(16-Mbyte expanded modes with

on-chip ROM disabled)

H'000000

H'0000FF

H'007FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

H'1FFFFF

H'200000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External

address

space

Vector area

On-chip RAM *

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'FF8000

H'FFEF0F

H'FFEF10

H'FFFF00

H'FFFF0F

H'FFFF10

H'FFFF1B

H'FFFF1C

H'FFFFFF

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

Figure 3.2 H8/3047 Memory Map in Each Operating Mode

Rev. 6.0, 09/02, page 75 of 876

H'00000

H'000FF

H'07FFF

H'17FFF

H'18000

Memory-indirect

branch addresses

16-bit absolute

addresses

Mode 5

(1-Mbyte expanded mode with

on-chip ROM enabled)

Mode 6

(16-Mbyte expanded mode with

on-chip ROM enabled)

Mode 7

(single-chip advanced mode)

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

H'DFFFF

H'E0000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External address

space

Vector area

On-chip ROM

On-chip RAM

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'F8000

H'FEF0F

H'FEF10

H'FFF00

H'FFF0F

H'FFF10

H'FFF1B

H'FFF1C

H'FFFFF

H'00000

H'000FF

H'07FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

Vector area

On-chip ROM

Reserved

On-chip RAM

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'FEF10

H'FFF00

H'FFF0F

H'FFF1C

H'FFFFF

H'17FFF

H'F8000

Notes:

H'1FFFF

H'20000

Reserved

*2Do not access the reserved area.

External addresses can be accessed by disabling on-chip RAM.

H'000000

H'0000FF

H'007FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

H'1FFFFF

H'200000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 7

External

address

space

Vector area

On-chip RAM

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'01FFFF

H'020000

H'FFEF0F

H'FFEF10

H'FFFF00

H'FFFF0F

H'FFFF10

H'FFFF1B

H'FFFF1C

H'FFFFFF

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

H'017FFF

H'018000

H'FF8000

Area 6

Figure 3.2 H8/3047 Memory Map in Each Operating Mode (cont)

Rev. 6.0, 09/02, page 76 of 876

H'00000

H'000FF

H'07FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

Modes 1 and 2

(1-Mbyte expanded modes with

on-chip ROM disabled)

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

H'DFFFF

H'E0000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External address

space

Vector area

On-chip RAM

Reserved

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'F8000

H'FEF10

H'FF70F

H'FF710

H'FFF00

H'FFF0F

H'FFF10

H'FFF1B

H'FFF1C

H'FFFFF

Modes 3 and 4

(16-Mbyte expanded modes with

on-chip ROM disabled)

H'000000

H'0000FF

H'007FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

H'1FFFFF

H'200000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External

address

space

Vector area

On-chip RAM

Reserved

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'FF8000

H'FFEF10

H'FFF70F

H'FFF710

H'FFFF00

H'FFFF0F

H'FFFF10

H'FFFF1B

H'FFFF1C

H'FFFFFF

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

Notes: *1

*2Do not access the reserved area.

External addresses can be accessed by disabling on-chip RAM.

Figure 3.3 H8/3044 Memory Map in Each Operating Mode

Rev. 6.0, 09/02, page 77 of 876

H'00000

H'000FF

H'07FFF

H'08000

Memory-indirect

branch addresses

16-bit absolute

addresses

Mode 5

(1-Mbyte expanded mode with

on-chip ROM enabled)

Mode 6

(16-Mbyte expanded mode with

on-chip ROM enabled)

Mode 7

(single-chip advanced mode)

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External address

space

Vector area

On-chip ROM

On-chip RAM*2

Reserved*1

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'F8000

H'DFFFF

H'E0000

H'FEF10

H'FF70F

H'FF710

H'FFF00

H'FFF0F

H'FFF10

H'FFF1B

H'FFF1C

H'FFFFF

H'00000

H'000FF

Memory-indirect

branch addresses

16-bit absolute

addresses

Vector area

On-chip ROM

On-chip RAM

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'FF710

H'FFF00

H'FFF0F

H'FFF1C

H'FFFFF

H'07FFF

H'F8000

Notes:

Reserved*1

*2Do not access the reserved area.

External addresses can be accessed by disabling on-chip RAM.

H'000000

H'0000FF

H'007FFF

H'008000

H'01FFFF

Memory-indirect

branch addresses

16-bit absolute

addresses

H'1FFFFF

H'200000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External

address

space

Vector area

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'FFEF10

H'FFF70F

H'FFF710

H'FFFF00

H'FFFF0F

H'FFFF10

H'FFFF1B

H'FFFF1C

H'FFFFFF

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

On-chip RAM*2

Reserved*1

On-chip ROM

Reserved*1

H'FF8000

Figure 3.3 H8/3044 Memory Map in Each Operating Mode (cont)

Rev. 6.0, 09/02, page 78 of 876

H'00000

H'000FF

H'07FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

Modes 1 and 2

(1-Mbyte expanded modes with

on-chip ROM disabled)

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

H'DFFFF

H'E0000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External address

space

Vector area

On-chip RAM*2

Reserved*1

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'F8000

H'FEF10

H'FF70F

H'FF710

H'FFF00

H'FFF0F

H'FFF10

H'FFF1B

H'FFF1C

H'FFFFF

Modes 3 and 4

(16-Mbyte expanded modes with

on-chip ROM disabled)

H'000000

H'0000FF

H'007FFF

Memory-indirect

branch addresses

16-bit absolute

addresses

H'1FFFFF

H'200000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External

address

space

Vector area

On-chip RAM*2

Reserved*1

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'FF8000

H'FFEF10

H'FFF70F

H'FFF710

H'FFFF00

H'FFFF0F

H'FFFF10

H'FFFF1B

H'FFFF1C

H'FFFFFF

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

Notes: *1

*2Do not access the reserved area.

External addresses can be accessed by disabling on-chip RAM.

Figure 3.4 H8/3045 Memory Map in Each Operating Mode

Rev. 6.0, 09/02, page 79 of 876

H'00000

H'000FF

H'07FFF

H'0FFFF

H'10000

Memory-indirect

branch addresses

16-bit absolute

addresses

Mode 5

(1-Mbyte expanded mode with

on-chip ROM enabled)

Mode 6

(16-Mbyte expanded mode with

on-chip ROM enabled)

Mode 7

(single-chip advanced mode)

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External address

space

Vector area

On-chip ROM

On-chip RAM

Reserved

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'F8000

H'DFFFF

H'E0000

H'FEF10

H'FF70F

H'FF710

H'FFF00

H'FFF0F

H'FFF10

H'FFF1B

H'FFF1C

H'FFFFF

H'00000

H'000FF

Memory-indirect

branch addresses

16-bit absolute

addresses

Vector area

On-chip ROM

On-chip RAM

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'FF710

H'FFF00

H'FFF0F

H'FFF1C

H'FFFFF

H'07FFF

H'0FFFF

H'F8000

Notes:

Reserved

*2Do not access the reserved area.

External addresses can be accessed by disabling on-chip RAM.

H'000000

H'0000FF

H'007FFF

H'00FFFF

H'010000

H'01FFFF

H'020000

Memory-indirect

branch addresses

16-bit absolute

addresses

H'1FFFFF

H'200000

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

External

address

space

Vector area

External

address

space

Internal I/O

registers

8-bit absolute addresses

16-bit absolute addresses

H'FFEF10

H'FFF70F

H'FFF710

H'FFFF1B

H'FFFF1C

H'FFFFFF

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

On-chip RAM

Reserved

On-chip ROM

Reserved

H'FF8000

Figure 3.4 H8/3045 Memory Map in Each Operating Mode (cont)

Rev. 6.0, 09/02, page 80 of 876

Rev. 6.0, 09/02, page 81 of 876

Section 4 Exception Handling

4.1 Overview

4.1.1 Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.

Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur

simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are

accepted at all times in the program execution state.

Table 4.1 Exception Types and Priority

Priority Exception Type Start of Exception Handling

Reset Starts immediately after a low-to-high transition at the

RES pin

Interrupt Interrupt reques ts are handled when execution of the

current instruction or handling of the current exception is

completed

High

↑



Low Trap instruction (TRAPA) Started by execut ion of a trap instructio n (TRAPA)

4.1.2 Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.

1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.

2. The CCR interrupt mask bit is set to 1.

3. A vector address corresponding to the exception source is generated, and program execution

starts from the address indicated in that address.

Note: For a reset exception, steps 2 and 3 above are carried out.

Rev. 6.0, 09/02, page 82 of 876

4.1.3 Exception Vector Table

The exception sources are classified as shown in figure 4.1. Different vectors are assigned to

different exception sources. Table 4.2 lists the exception sources and their vector addresses.

Exception

sources

• Reset

• Interrupts

• Trap instruction

External interrupts:

Internal interrupts:

NMI, IRQ to IRQ

30 interrupts from on-chip

supporting modules

0 5

Figure 4.1 Exception Sources

Rev. 6.0, 09/02, page 83 of 876

Table 4.2 Exception Vector Table

Exception Source Vector Number Vector Address*1

Reset 0 H'0000 to H'0003

Reserved for system use 1 H'0004 to H'0007

2 H'0008 to H'000B

3 H'000C to H'000F

4 H'0010 to H'0013

5 H'0014 to H'0017

6 H'0018 to H'001B

External interrupt (NMI) 7 H'001C to H'001F

Trap instruction (4 sources) 8 H'0020 to H'0023

9 H'0024 to H'0027

10 H'0028 to H'002B

11 H'002C to H'002F

External interrupt IRQ012 H'0030 to H'0033

External interrupt IRQ113 H'0034 to H'0037

External interrupt IRQ214 H'0038 to H'003B

External interrupt IRQ315 H'003C to H'003F

External interrupt IRQ416 H'0040 to H'0043

External interrupt IRQ517 H'0044 to H'0047

Reserved for system use 18 H'0048 to H'004B

19 H'004C to H'004F

Internal interrupts*220

H'0050 to H'0053

H'00F0 to H'00F3

Notes: *1 Lower 16 bits of the address.

*2 For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table.

Rev. 6.0, 09/02, page 84 of 876

4.2 Reset

4.2.1 Overview

A reset is the highest-priority excep tion. When the RES pin goes low, all processing halts and the

chip enters the r e set state. A r e set initializes the internal state of the CPU and the registers of the

on-chip supporting modules. Reset exception handling begins when the RES pin changes from

low to high.

The chip can also be reset by overflow of the watchdog timer. Fo r details see section 12,

Watchdog Timer.

4.2.2 Reset Sequence

The chip enters the reset state when the RES pin goes low.

To ensure th at the chip is r eset, hold the RES pin low for at least 20 ms at power-up. To reset the

chip during operation, hold the RES pin low for at least 10 system clock (

) cycles. See appendix

D.2, Pin States at Reset, for the states of the pins in the reset state.

When the RES pin goes high after being held low for the necessary time, the chip starts reset

exception handling as follows.

• The internal state of the CPU and the registers of the on-chip supporting modules are

initialized, and the I bit is set to 1 in CCR.

• The contents of the reset vector address (H'0000 to H'0003) are read, and program execution

starts from the address indicated in the vector address.

Figure 4.2 shows the reset sequence in modes 1 and 3. Figure 4.3 shows the reset sequence in

modes 2 and 4. Figure 4.4 shows the reset sequence in modes 5, 6 and 7.

Rev. 6.0, 09/02, page 85 of 876

Address

bus

D to D

15 8

Vector fetch Internal

processing Prefetch of

first program

instruction

(1), (3), (5), (7)

(2), (4), (6), (8)

(9)

(10)

Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.

Address of reset vector: (1) = H'00000, (3) = H'00001, (5) = H'00002, (7) = H'00003

Start address (contents of reset vector)

Start address

First instruction of program

High

(1) (3) (5) (7) (9)

(2) (4) (6) (8) (10)

Figure 4.2 Reset Sequence (Modes 1 and 3)

Rev. 6.0, 09/02, page 86 of 876

Address bus

D to D

15 0

Vector fetch Internal

processing Prefetch of first

program instruction

(1), (3)

(2), (4)

(5)

(6)

Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.

High

Address of reset vector: (1) = H'000000, (3) = H'000002

Start address (contents of reset vector)

Start address

First instruction of program

(2) (4)

(3)(1) (5)

(6)

Figure 4.3 Reset Sequence (Modes 2 and 4)

Rev. 6.0, 09/02, page 87 of 876

Vector fetch Internal

processing

Prefetch of

first program

instruction

Internal

address bus

Internal

read signal

Internal

write signal

Internal

data bus

(16 bits wide)

(1) (3) (5)

(2) (4) (6)

(1), (3)

(2), (4)

(5)

(6)

Address of reset vector ((1) = H'000000, (2) = H'000002)

Start address (contents of reset vector)

Start address

First instruction of program

Figure 4.4 Reset Sequence (Modes 5, 6, and 7)

4.2.3 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC an d CCR

will not be save d corr ectly, leading to a program crash. To prev ent th is, all interrupt requests,

including NMI, are disabled immediately after a reset. The first instruction of the program is

always executed immediately after the reset state end s. This instruction should initialize the stack

pointer (example: MOV.L #xx:32, SP).

Rev. 6.0, 09/02, page 88 of 876

4.3 Interrupts

Interrupt exception handling can be requested by seven external sources (NMI, IRQ0 to IRQ5) and

30 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources

and indicates the number of interrupts of each type.

The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), refresh

controller, 16-bit integrated timer unit (ITU), DMA con troller ( DMAC) , ser ial communication

interface (SCI), and A/D converter. Each interrupt source has a separate vector address.

NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the

interrup t controller. The interrupt controller can assign interrupts other than NMI to two priority

levels, and arbitrate between simultaneo us interrupts. Interrupt prio rities are assigned in interr upt

priority registers A and B (IPRA and IPRB) in the interrupt controller.

For details o n interrupts see section 5, Interrupt Contr oller.

Interrupts

External interrupts

Internal interrupts

NMI (1)

IRQ to IRQ (6)

WDT (1)

Refresh controller (1)

ITU (15)

DMAC (4)

SCI (8)

A/D converter (1)

Notes: Numbers in parentheses are the number of interrupt sources.

When the watchdog timer is used as an interval timer, it generates an interrupt

request at every counter overflow.

When the refresh controller is used as an interval timer, it generates an interrupt

request at compare match.

0 5

Figure 4.5 Interrupt Sources and Number of Interrupts

Rev. 6.0, 09/02, page 89 of 876

4.4 Trap Instruction

Trap instruction exception handling starts wh en a TRAPA instruction is ex ecuted. If the UE bit is

set to 1 in the system control register (SYSCR), the exception han dling sequence sets the I bit to 1

in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a

start address from a vector table entry corresponding to a vector number from 0 to 3, which is

specified in th e instruction code.

4.5 Stack Status after Exception Handling

Figure 4.6 shows the stack after completion of trap instruction ex ception handling and interrupt

exception handling.

SP-4

SP-3

SP-2

SP-1

SP (ER7) →

SP (ER7)

SP+1

SP+2

SP+3

SP+4

→

Before exception handling After exception handling

Stack area

CCR

LEven address

Pushed on stack

Legend

PCE:

PCH:

PCL:

CCR:

SP:

Notes: PC indicates the address of the first instruction that will be executed after return.

Registers must be saved in word or longword size at even addresses.

Bits 23 to 16 of program counter (PC)

Bits 15 to 8 of program counter (PC)

Bits 7 to 0 of program counter (PC)

Condition code register

Stack pointer

Figure 4.6 Stack after Completion of Exception Handling

Rev. 6.0, 09/02, page 90 of 876

4.6 Notes on Stack Usage

When accessing word data or longword data, the H8/3048 Series regards the lowest address bit as

0. The stack should always be accessed by word access or longword access, and the value of the

stack pointer (SP:ER7) should always be kept even. Use the following instructions to save

registers:

PUSH.W Rn (or MOV.W Rn, @–SP)

PUSH.L ERn (or MOV.L E Rn, @–SP)

Use the following instructio ns to restore registers:

POP.W Rn (or MOV.W @SP+, Rn)

POP.L ERn (or MOV.L @SP+, ERn)

Setting SP to an odd value may lead to a malfunction. Figure 4.7 shows an example of what

happens when the SP value is odd.

TRAPA instruction executed

CCR

Legend

CCR:

PC:

R1L:

SP:

R1L

MOV. B R1L, @-ER7

SP set to H'FFFEFF Data saved above SP CCR contents lost

Condition code register

Program counter

General register R1L

Stack pointer

Note: The diagram illustrates modes 3 and 4.

H'FFFEFA

H'FFFEFB

H'FFFEFC

H'FFFEFD

H'FFFEFF

Figure 4.7 Operation when SP Value is Odd

Rev. 6.0, 09/02, page 91 of 876

Section 5 Interrupt Controller

5.1 Overview

5.1.1 Features

The interrupt controller has the following features:

• Interrupt p riority registers (IPRs) for setting interrupt priorities

Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis

in interrupt priority registers A and B (IPRA and IPRB).

• Three-level masking by the I and UI bits in the CPU condition code register (CCR)

• Independent vect or address es

All interrup ts ar e independently vectored; the interrupt service routine does not have to

identify th e interrupt source.

• Seven external interrupt pins

NMI has the highe st priority and is always accepted; either the rising or falling edge can be

selected. For each of IRQ0 to IRQ5, sensing of the falling edge or level sensing can be selected

independently.

Rev. 6.0, 09/02, page 92 of 876

5.1.2 Block Diagram

Figure 5.1 shows a block diagram of the interrupt controller.

ISCR IER IPRA, IPRB

OVF

TME

ADI

ADIE

CPU

CCR

SYSCR

ISCR:

IER:

ISR:

IPRA:

IPRB:

SYSCR:

NMI

input

IRQ input IRQ input

section ISR

Interrupt controller

Priority

decision logic

Interrupt

request

Vector

number

IRQ sense control register

IRQ enable register

IRQ status register

Interrupt priority register A

Interrupt priority register B

System control register

Legend

Figure 5.1 Interrupt Controller Block Diagram

Rev. 6.0, 09/02, page 93 of 876

5.1.3 Pin Configuration

Table 5.1 lists the interrupt pins.

Table 5.1 Interrupt Pin s

Name Abbreviation I/O Function

Nonmaskable interrupt NMI Input Nonmaskable interrupt, rising edge or

falling edge selectable

External interrupt request

5 to 0 IRQ5 to IRQ0Input Maskable interrupts, falling edge or

level sensing selectable

5.1.4 Register Configuration

Table 5.2 lists th e r e gisters of the interrupt con troller.

Table 5.2 Interrupt Controller Registers

Address*1Name Abbreviation R/W Initial Value

H'FFF2 System control regi ster SYSCR R/W H'0B

H'FFF4 IRQ sense control register ISCR R/W H'00

H'FFF5 IRQ enable register IER R/W H'00

H'FFF6 IRQ status register ISR R/(W)*2H'00

H'FFF8 Interrupt priority register A IPRA R/W H'00

H'FFF9 Interrupt priority register B IPRB R/W H'00

Notes: *1 Lower 16 bits of the address.

*2 Only 0 can be written, to clear flags.

Rev. 6.0, 09/02, page 94 of 876

5.2 Register Descriptions

5.2.1 System Control Register (SYSCR)

SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the

action of the UI b it in CCR, selects th e NMI edge, and enables or disable s the on-chip RAM.

Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register

(SYSCR).

SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

—

Software standby

Standby timer

select 2 to 0

User bit enable

Selects whether to use the UI bit in

CCR as a user bit or interrupt mask bit

NMI edge select

Selects the NMI input edge

Reserved bit

RAM enable

Rev. 6.0, 09/02, page 95 of 876

Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an

interrupt mask bit.

Bit 3: UE Description

0 UI bit in CCR is used as interrupt mask bit

1 UI bit in CCR is used as user bit (Initial value)

Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.

Bit 2: NMIEG Description

0 Interrupt is requested at falling edge of NMI input (Initial value)

1 Interrupt is requested at rising edge of NMI input

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)

IPRA and IPRB are 8 - bit readable/writable r egisters that control interrupt priority.

Rev. 6.0, 09/02, page 96 of 876

Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which

interrupt prio rity levels can be set.

Bit

Initial value

Read/Write

IPRA7

R/W

IPRA6

R/W

IPRA5

R/W

IPRA4

R/W

IPRA3

R/W

IPRA0

R/W

IPRA2

R/W

IPRA1

R/W

Priority level A7

Selects the priority level of IRQ interrupt requests

Priority level A3

Selects the priority level of WDT and

refresh controller interrupt requests

Priority level A2

Selects the priority level of

ITU channel 0 interrupt requests

Priority level A1

Selects the priority level

of ITU channel 1

interrupt requests

Priority

level A0

Selects the

priority level

of ITU

channel 2

interrupt

requests

Selects the priority level of IRQ interrupt requests

Priority level A6

Selects the priority level of IRQ and IRQ interrupt requests

Priority level A5

Selects the priority level of IRQ and IRQ

interrupt requests

Priority level A4

IPRA is initialized to H'00 by a reset and in hardware standby mode.

Rev. 6.0, 09/02, page 97 of 876

Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 inter rupt requests.

Bit 7: IPRA7 Description

0IRQ

0 interrupt requests have priority level 0 (low priority) (Initial value)

1IRQ

0 interrupt requests have priority level 1 (high priority)

Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 inter rupt requests.

Bit 6: IPRA6 Description

0IRQ

1 interrupt requests have priority level 0 (low priority) (Initial value)

1IRQ

1 interrupt requests have priority level 1 (high priority)

Bit 5—Priority Level A5 (IPRA5): Selects the priority level of IRQ2 and IRQ3 interrupt requests.

Bit 5: IPRA5 Description

0IRQ

2 and IRQ3 interrupt requests have priority level 0 (low priority)(Initial value)

1IRQ

2 and IRQ3 interrupt requests have priority level 1 (high priority)

Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt requests.

Bit 4: IPRA4 Description

0IRQ

4 and IRQ5 interrupt requests have priority level 0 (low priority)(Initial value)

1IRQ

4 and IRQ5 interrupt requests have priority level 1 (high priority)

Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT and r e fresh controller

interrupt requests.

Bit 3: IPRA3 Description

0 WDT and refres h controller interrupt requests have priority level 0 (low priority)

(Initial value)

1 WDT and refresh controller interrupt requests have priority level 1 (high

priority)

Rev. 6.0, 09/02, page 98 of 876

Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests.

Bit 2: IPRA2 Description

0 ITU channel 0 interrupt requests have priority level 0 (low priority) (Initial value)

1 ITU channel 0 interrupt requests have priority level 1 (high priority)

Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests.

Bit 1: IPRA1 Description

0 ITU channel 1 interrupt requests have priority level 0 (low priority) (Initial value)

1 ITU channel 1 interrupt requests have priority level 1 (high priority)

Bit 0—Priority Level A0 (IPRA0): Selects the priority level of ITU channel 2 interrupt requests.

Bit 0: IPRA0 Description

0 ITU channel 2 interrupt requests have priority level 0 (low priority) (Initial value)

1 ITU channel 2 interrupt requests have priority level 1 (high priority)

Rev. 6.0, 09/02, page 99 of 876

Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which

interrupt prio rity levels can be set.

Bit

Initial value

Read/Write

IPRB7

R/W

IPRB6

R/W

IPRB5

R/W

—

R/W

IPRB3

R/W

—

R/W

IPRB2

R/W

IPRB1

R/W

Priority level B7

Selects the priority level of ITU channel 3 interrupt requests

Priority level B3

Selects the priority level of SCI

channel 0 interrupt requests

Priority level B2

Selects the priority level of

SCI channel 1 interrupt requests

Priority level B1

Selects the priority level

of A/D converter

interrupt request

Reserved bit

Selects the priority level of ITU channel 4 interrupt requests

Priority level B6

Selects the priority level of DMAC

interrupt requests (channels 0 and 1)

Priority level B5

Reserved bit

IPRB is initialized to H'00 by a reset and in hardware standby mode.

Rev. 6.0, 09/02, page 100 of 876

Bit 7—Priority Level B7 (IPRB7): Selects the prio rity level of ITU channe l 3 interrupt requests.

Bit 7: IPRB7 Description

0 ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value)

1 ITU channel 3 interrupt requests have priority level 1 (high priority)

Bit 6—Priority Level B6 (IPRB6): Selects the prio rity level of ITU channe l 4 interrupt requests.

Bit 6: IPRB6 Description

0 ITU channel 4 interrupt requests have priority level 0 (low priority) (Initial value)

1 ITU channel 4 interrupt requests have priority level 1 (high priority)

Bit 5—Priority Level B5 (IPRB5): Selects the prio rity level of DMAC interrupt requests

(channels 0 and 1).

Bit 5: IPRB5 Description

0 DMAC interrupt requests (channels 0 and 1) have priority level 0 (low priority)

(Initial value)

1 DMAC interrupt requests (channels 0 and 1) have priority level 1 (high priority)

Bit 4—Reserved: This bit can be written and read, but it does not af f ect interrupt p r iority .

Rev. 6.0, 09/02, page 101 of 876

Bit 3—Priority Level B3 (IPRB3): Selects the prio rity level of SCI channel 0 interrupt requests.

Bit 3: IPRB3 Description

0 SCI0 interrupt requests have priority level 0 (low priority) (Initial value)

1 SCI0 interrupt requests have priority level 1 (high priority)

Bit 2—Priority Level B2 (IPRB2): Selects the prio rity level of SCI channel 1 interrupt requests.

Bit 2: IPRB2 Description

0 SCI1 interrupt requests have priority level 0 (low priority) (Initial value)

1 SCI1 interrupt requests have priority level 1 (high priority)

Bit 1—Priority Level B1 (IPRB1): Selects the priority level of A/D converter interrupt requests.

Bit 1: IPRB1 Description

0 A/D converter interrupt requests have priority level 0 (low priority) (Initial value)

1 A/D converter interrupt requests have priority level 1 (high priority)

Bit 0—Reserved: This bit can be written and read, but it does not af f ect interrupt p r iority .

Rev. 6.0, 09/02, page 102 of 876

5.2.3 IRQ Status Register (ISR)

ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt

requests.

Bit

Initial value

Read/Write

—

These bits indicate IRQ to IRQ

interrupt request status

Note: Only 0 can be written, to clear flags.*

—

IRQ5F

R/(W) *

IRQ4F

R/(W) *

IRQ3F

R/(W) *

IRQ2F

R/(W) *

IRQ1F

R/(W) *

IRQ0F

R/(W) *

IRQ to IRQ flags

Reserved bits

ISR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 and 6—Reserved: Read-only bits, always read as 0.

Bits 5 to 0—IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to

IRQ0 interrupt requests.

Bits 5 to 0:

IRQ5F to IRQ0F Description

0 [Clearing cond iti ons ] (Initial val ue)

0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.

IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.

IRQnSC = 1 and IRQn interrupt exception handling is carried out.

1 [Setting conditions]

IRQnSC = 0 and IRQn input is low.

IRQnSC = 1 and IRQn input changes from high to low.

Note: n = 5 to 0

Rev. 6.0, 09/02, page 103 of 876

5.2.4 IRQ Enable Register (IER)

IER is an 8-bit readable/writable register that enables or disables IRQ0 to IRQ5 interrupt requests.

Bit

Initial value

Read/Write

—

R/W

These bits enable or disable IRQ to IRQ interrupts

—

R/W

IRQ5E

R/W

IRQ4E

R/W

IRQ3E

R/W

IRQ2E

R/W

IRQ1E

R/W

IRQ0E

R/W

IRQ to IRQ enable

Reserved bits

IER is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable

interrupts.

Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E): These bits enable or disable IRQ5 to

IRQ0 interrupts.

Bits 5 to 0:

IRQ5E to IRQ0E Description

0IRQ

5 to IRQ0 interrupts are disabled (Initial value)

1IRQ

5 to IRQ0 interrupts are enabled

Rev. 6.0, 09/02, page 104 of 876

5.2.5 IRQ Sense Control Reg ist er (ISCR)

ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the

inputs at pins IRQ5 to IRQ0.

Bit

Initial value

Read/Write

—

R/W

These bits select level sensing or falling-edge

sensing for IRQ to IRQ interrupts

—

R/W

IRQ5SC

R/W

IRQ4SC

R/W

IRQ3SC

R/W

IRQ2SC

R/W

IRQ1SC

R/W

IRQ0SC

R/W

IRQ to IRQ sense control

Reserved bits

ISCR is initialized to H'00 by a reset and in hardware standby mod e.

Bits 7 and 6—Reserved: These bits can be written an d read, but they do not select level or

falling-edge sensing.

Bits 5 to 0—IRQ5 to IRQ0 Sense Control (IRQ5SC to IRQ0 SC) : These bits select whether

interru pts IRQ5 to IRQ0 are requested by level sensing of pins IRQ5 to IRQ0, or by falling-edge

sensing.

Bits 5 to 0:

IRQ5SC to IRQ0SC Description

0 Interrupts are requested when IRQ5 to IRQ0 inputs are low (Initial value)

1 Interrupts are requested by falling-edge input at IRQ5 to IRQ0

Rev. 6.0, 09/02, page 105 of 876

5.3 Interrupt Sources

The interrupt sour ces include external interrupts (NMI, IRQ0 to IRQ5) and 30 internal interrupts.

5.3.1 External Interrupts

There are seven external in terrupts: NMI, and IRQ0 to IRQ5. Of these, NMI, IRQ0, IRQ1, and IRQ2

can be used to exit software standby mode.

NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the

I and U I bits in CCR. The NMIEG bit in SYSCR selects wheth er an inte rrupt is req uested by th e

rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector

number 7.

IRQ0 to IRQ5 Interrupt s: These interrupts are requested by input signals at pins IRQ0 to IRQ5.

The IRQ0 to IRQ5 interrupts have th e follo wing features.

• ISCR settings can select whether an interrupt is requested by the low level of the input at pins

IRQ0 to IRQ5, or by the falling edge.

• IER settings can enable or disable the IRQ0 to IRQ5 interrupts. Interrup t prio r ity levels can be

assigned by four bits in IPRA (IPRA7 to IPRA4).

• The status of IRQ0 to IRQ5 interrupt requests is indicated in ISR. The ISR flags can be cleared

to 0 by software.

Figure 5.2 shows a block diagram of interrupts IRQ0 to IRQ5.

input

Edge/level

sense circuit

IRQnSC

IRQnF

IRQnE

IRQn interrupt

request

Clear signal

Note: n = 5 to 0

Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5

Rev. 6.0, 09/02, page 106 of 876

Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).

IRQnF

input pin

Note: n = 5 to 0

Figure 5.3 Timing of Setting of IRQnF

Interrupts IRQ0 to IRQ5 have vector numbers 12 to 17. These interrupts are detected regardless of

whether the corresponding pin is set for input or output. When using a pin for external interrupt

input, clear its DDR bit to 0 and do not use the pin for chip select output, refresh output, or SCI

input or output.

5.3.2 Internal Interrupts

Thirty internal interrupts are requested from the on-chip supporting modules.

• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits

for enabling or disabling interrupts.

• Interrupt priority levels can be assigned in IPRA and IPRB.

• ITU and SCI in ter rupt requests can activate the DMAC, in wh ich case no interrupt reque st is

sent to the interrupt controller, and the I and UI bits are disregarded.

5.3.3 Interrupt Vector Table

Table 5.3 lists the interrup t sources, their vector addresses, and their default priority order. In the

default priority order, smaller vector numbers have higher priority. The priority of interrupts other

than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order

shown in table 5.3.

Rev. 6.0, 09/02, page 107 of 876

Table 5.3 Interrupt Sources, Vector Addresses, a nd Priority

Interrupt Source Origin Vector

Number Vector Address*IPR Priority

NMI External pins 7 H'001C to H'001F —

IRQ012 H'0030 to H'0033 IPRA7

IRQ113 H'0034 to H0037 IPRA6

IRQ214 H'0038 to H'003B IPRA5

IRQ315 H'003C to H'003F

IRQ416 H'0040 to H'0043 IPRA4

IRQ517 H'0044 to H'0047

Reserved — 18 H'0048 to H'004B

19 H'004C to H'004F

WOVI

(interval timer) Watchdog

timer 20 H'0050 to H'0053 IPRA3

CMI

(compare matc h) Refresh

controller 21 H'0054 to H'0057

Reserved — 22 H'0058 to H'005B

23 H'005C to H'005F

IMIA0

(compare matc h/

input capture A0)

ITU channel 0 24 H'0060 to H'0063 IPRA2

IMIB0

(compare matc h/

input capture B0)

25 H'0064 to H'0067

OVI0 (overflow 0) 26 H'0068 to H'006B

Reserved — 27 H'006C to H'006F

IMIA1

(compare matc h/

input capture A1)

ITU channel 1 28 H'0070 to H'0073 IPRA1

IMIB1

(compare matc h/

input capture B1)

29 H'0074 to H'0077

OVI1 (overflow 1) 30 H'0078 to H'007B

Reserved — 31 H'007C to H'007F

High

↑



Low

Rev. 6.0, 09/02, page 108 of 876

Interrupt Source Origin Vector

Number Vector Address*IPR Priority

IMIA2

(compare matc h/

input capture A2)

ITU channel 2 32 H'0080 to H'0083 IPRA0

IMIB2

(compare matc h/

input capture B2)

33 H'0084 to H'0087

OVI2 (overflow 2) 34 H'0088 to H'008B

Reserved — 35 H'008C to H'008F

IMIA3

(compare matc h/

input capture A3)

ITU channel 3 36 H'0090 to H'0093 IPRB7

IMIB3

(compare matc h/

input capture B3)

37 H'0094 to H'0097

OVI3 (overflow 3) 38 H'0098 to H'009B

Reserved — 39 H'009C to H'009F

IMIA4

(compare matc h/

input capture A4)

ITU channel 4 40 H'00A0 to H'00A3 IPRB6

IMIB4

(compare matc h/

input capture B4)

41 H'00A4 to H'00A7

OVI4 (overflow 4) 42 H'00A8 to H'00AB

Reserved — 43 H'00AC to H'00AF

DEND0A DMAC 44 H'00B0 to H'00B3 IPRB5

DEND0B 45 H'00B4 to H'00B7

DEND1A 46 H'00B8 to H'00BB

DEND1B 47 H'00BC to H'00 B F

Reserved — 48 H'00C0 to H'00C3 —

49 H'00C4 to H'00C7

50 H'00C8 to H'00CB

51 H'00CC to H'00CF

High

↑



Low

Rev. 6.0, 09/02, page 109 of 876

Interrupt Source Origin Vector

Number Vector Address*IPR Priority

ERI0

(receive error 0) SCI channel 0 52 H'00D0 to H'00D3 IPRB3

RXI0

(receive data full 0) 53 H'00D4 to H'00D7

TXI0 (transmit data

empty 0) 54 H'00D8 to H'00DB

TEI0

(transmit end 0) 55 H'00 DC to H'00DF

ERI1

(receive error 1) SCI channel 1 56 H'00E0 to H'00E3 IPRB2

RXI1

(receive data full 1) 57 H'00E4 to H'00E7

TXI1 (transmit data

empty 1) 58 H'00E8 to H'00EB

TEI1

(transmit end 1) 59 H'00EC to H'00EF

ADI (A/D end) A/D 60 H'00F0 to H'00F3 IPRB1

High

↑



Low

Note: * Lower 16 bits of the address.

Rev. 6.0, 09/02, page 110 of 876

5.4 Interrupt Operation

5.4.1 Interrupt Handling Process

The H8/3048 Series handles interrupts differently depending on the setting of th e UE bit. When

UE = 1, interrupts are controlled by th e I bit. When UE = 0, interrupts are controlled by the I and

UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I,

and UI bits.

NMI interrupts are always accepted except in the reset and hardware standby states. IRQ interrupts

and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests

are ignored when the enable bits are cleared to 0.

Table 5.4 UE, I, and UI Bit Settings and Interrupt Handling

SYSCR CCR

UE I UI Description

1 0 — All interrupts are accepted. Interrupts with priority level 1 have higher

priority.

1 — No interrupts are accepted except NMI.

0 0 — All interrupts are accepted. Interrupts with priority level 1 have higher

priority.

1 0 NMI and interrupts with priority level 1 are accepted.

1 No interrupts are accepted except NMI.

UE = 1: Interrupts IRQ0 to IRQ5 and interrupts from the on-chip supporting modules can all be

masked b y the I bit in the CPU’s CCR. Inter rupts are masked when the I bit is set to 1, and

unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure

5.4 is a flowchart showing how interrupts are accepted when UE = 1.

Rev. 6.0, 09/02, page 111 of 876

Program execution state

Interrupt requested?

NMI

Yes

Priority level 1?

IRQ

Yes No

IRQ

Yes ADI

Yes

IRQ

Yes No

IRQ

Yes ADI

Yes

I = 0

Yes

Save PC and CCR

I 1

Branch to interrupt

service routine

←

Pending

Yes

Read vector address

Figure 5.4 Process Up to Interrupt Acceptance when UE = 1

Rev. 6.0, 09/02, page 112 of 876

• If an interrupt cond ition occurs and the corresponding interrupt en able bit is set to 1, an

interrup t r eque st is sent to the interrupt controller.

• When the interrupt controller receives on e or more interrupt requests, it selects the highest-

priority request, following the IPR interrupt priority settings, and holds other requests pending.

If two or more interrupts with the same IPR settin g are requested simultaneously, the interrupt

controller follows the priority order shown in table 5.3.

• The interrupt con troller ch ecks the I bit. If the I bit is cleared to 0, the selected interrup t reque st

is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held

pending.

• When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

• In inte rrupt exc eption handling, PC and CCR a re saved to the stack area. The PC value that is

saved indicates the address of the first instruction that will be executed after th e return from the

interrupt ser vice routine.

• Next the I bit is set to 1 in CCR, masking all interrupts except NMI.

• The vector address of the accepted in terrupt is generated, and the interrupt service routine

starts executing from the address indicated by the contents of the vector address.

UE = 0: The I and UI b its in the CPU’s CCR and the IPR bits enable thr ee-level masking of IRQ0

to IRQ5 interrupts and interrupts from the on-chip supporting modules.

• Interrupt req uests with priority level 0 are masked when the I bit is set to 1 , and ar e unmasked

when the I bit is cleared to 0.

• Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1 , and

are unmasked when either the I bit or the UI bit is cleared to 0.

For examp le, if the in ter rup t enable bits of all interrupt reque sts ar e set to 1, IPRA is set to

H'20, and IPRB is set to H'00 (givin g IRQ2 and IRQ3 interrupt requests pr iority over other

interrupts), interrupts are ma sked as follows:

a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ2 > IRQ3 >IRQ0 …).

b. If I = 1 and UI = 0, only NMI, IRQ2, and IRQ3 are unmasked.

c. If I = 1 and UI = 1, all interrupts are masked except NMI.

Figure 5.5 shows the transitions among the above states.

Rev. 6.0, 09/02, page 113 of 876

All interrupts are

unmasked Only NMI, IRQ , and

IRQ are unmasked

Exception handling,

or I 1, UI 1

a. b.

All interrupts are

masked except NMI

UI 0I 0 Exception handling,

or UI 1

I 0

I 1, UI 0

←← ←←

←

←←

Figure 5.5 Interrupt Masking State Transitions (Example)

Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.

• If an interrupt cond ition occurs and the corresponding interrupt en able bit is set to 1, an

interrupt r equ est is sent to the interrupt contro ller .

• When the interrupt controller receives on e or more interrupt requests, it selects the highest-

priority request, following the IPR interrupt priority settings, and holds other requests pending.

If two or more interrupts with the same IPR settin g are requested simultaneously, the interrupt

controller follows the priority order shown in table 5.3.

• The interrupt con troller ch ecks the I bit. If the I bit is cleared to 0, the selected interrup t requ est

is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and

the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted; interrupt

requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1, only

NMI is accepted; all other interrupt requests are held pending.

• When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

• In inte rrupt exc eption handling, PC and CCR a re saved to the stack area. The PC value that is

saved indicates the address of the first instr uction that will be executed after the return from the

interrupt ser vice routine.

• The I and UI bits are set to 1 in CCR, masking all interrupts except NMI.

• The vector address of the accepted in terrupt is generated, and the interrupt service routine

starts executing from the address indicated by the contents of the vector address.

Rev. 6.0, 09/02, page 114 of 876

Program execution state

Interrupt requested?

NMI

Yes

Priority level 1?

IRQ

Yes No

IRQ

Yes ADI

Yes

IRQ

Yes No

IRQ

Yes ADI

Yes

I = 0

Yes

I = 0

Yes

UI = 0

Yes

Save PC and CCR

I 1, UI 1

←

Pending

Branch to interrupt

service routine

Yes

←

Read vector address

Figure 5.6 Process Up to Interrupt Acceptance when UE = 0

Rev. 6.0, 09/02, page 115 of 876

5.4.2 Interrupt Sequence

Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an

external memory area accessed in two states via a 16-bit bus.

Address

bus

Interrupt

request

signal

D to D

15 0

(1)

(2), (4)

(3)

(5)

(7)

Note: Mode 2, with program code and stack in external memory area accessed in two states via 16-bit bus.

Interrupt level

decision and wait

for end of instruction

Interrupt accepted

Instruction

prefetch Internal

processing Stack Vector fetch Internal

processing

Prefetch of

interrupt

service routine

instruction

High

Instruction prefetch address (not executed;

return address, same as PC contents)

Instruction code (not executed)

Instruction prefetch address (not executed)

SP – 2

SP – 4

(6), (8)

(9), (11)

(10), (12)

(13)

(14)

PC and CCR saved to stack

Vector address

Starting address of interrupt service routine (contents of

vector address)

Starting address of interrupt service routine; (13) = (10), (12)

First instruction of interrupt service routine

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

Figure 5.7 Interrupt Sequence (Mode 2, Two-State Access, Stack in External Memory)

Rev. 6.0, 09/02, page 116 of 876

5.4.3 Interrupt Response Time

Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the

first instructio n of the interrupt service routine is executed.

Table 5.5 Interrupt Respo nse Time

External Memory

8-Bit Bus 16-Bit Bus

No. Item On-Chip

Memory 2 States 3 States 2 States 3 States

1 Interrupt priority

decision 2*12*12*12*12*1

2 Maximum number of

states until end of

current instruction

1 to 23 1 to 27 1 to 31*41 to 23 1 to 25*4

3 Saving PC and CCR

to stack 4812

*446

4 Vector fetch 4 8 12*446

5 Instruction prefetch*24812

*446

6 Internal processing*3444 44

Total 19 to 41 31 to 57 43 to 73 19 to 41 25 to 49

Notes: *1 1 state for internal interrupts.

*2 Prefetch after the interrupt is accepted and prefetch of the first instruction in the

interrupt service routine .

*3 Internal processing after the interrupt is accepted and internal processing after prefetch.

*4 The number of states increases if wait states are inserted in external memory access.

Rev. 6.0, 09/02, page 117 of 876

5.5 Usage Notes

5.5.1 Contention between Interrupt and Interrupt-Disabli ng Instruction

When an instr uction clears an interrupt enab le bit to 0 to disable the interrupt, the interrupt is no t

disabled un til af ter execution of the instruction is completed. If an interrupt occurs while a BCLR,

MOV, or other instru ction is being executed to clear its interrupt enable bit to 0, at the instan t

when execution o f the in struction ends the interrup t is still en abled, so its interrupt ex ception

handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception

handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.

This also applies to the clearing of an interrupt flag.

Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in TIER of the ITU.

IMIA exception handlingTIER write cycle by CPU

TIER address

Internal

address bus

Internal

write signal

IMIEA

IMIA

IMFA interrupt

signal

Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction

This type of contention will not occur if the interrupt is mask ed when the interrupt enable bit or

flag is cleared to 0.

Rev. 6.0, 09/02, page 118 of 876

5.5.2 Instructions that Inhibit Interrupts

The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after

determining the interrupt priority, th e interr upt controller requests a CPU interru pt. If the CPU is

currently executing one of these interrupt-inhib iting instructions, however, when the instruction is

completed the CPU always continues by executing the next instruction.

5.5.3 Interrupts during EEP MO V Instruction Ex ecution

The EEPMOV.B and EEPMOV.W instr uctions differ in th eir reactio n to interrupt requests.

When the EEPMOV.B instru ction is executing a transfer, no interrupts are accep ted un til the

transfer is completed, not even NMI.

When the EEPMOV.W instr uction is executing a transfer, interrupt requests other than NMI are

not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at

a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.

Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:

L1: EEPMOV.W

MOV.W R4,R4

BNE L1

5.5.4 Usage Notes on External Interrupts

The IRQnF flag specification calls for the flag to be cleared by writing 0 to it after it has been read

while set to 1. However, it is possible for th e I RQnF f lag to be cleared by mistake simply by

writing 0 to it, irrespective of whether it has been read while set to 1, with the result that interrupt

exception h andling is not executed. This occurs when the following conditions are fulfilled.

• Setting conditions

1. Multiple external interrup ts ( I RQa, I RQb) are being used.

2. Different clearing methods are being used: clearing by writing 0 for the IRQaF flag, and

clearing by hardware for the IRQbF flag.

3. A bit manipulation instruction is used on the IRQ status register to clear the IRQaF flag, or

else ISR is read as a byte unit, the IRQaF flag bit is cleared, and the values read in the other

bits are written as a byte unit.

Rev. 6.0, 09/02, page 119 of 876

• Occurrence conditions

1. When IRQaF = 1, for the IRQaF flag to clear, ISR register read is executed. Thereafter

interrupt processing is carried out and IRQbF flag clears.

2. IRQaF flag clear and IRQbF flag generation compete (IRQaF flag setting).

(The ISR read needed for IRQaF flag clear was at IRQbF = 0 but in the time taken for ISR

write, IRQbF = 1 was reached.)

In all of the setting conditions 1 to 3 and occurrence conditions 1 and 2 are generated, IRQbF

clears in error during ISR write for occurrence condition 2 and interrupt processing is not carried

out. However, if IRQbF flag reaches 0 between occurrence conditions 1 and 2, IRQbF flag does

not clear in error.

Read

1Write

Read

1Write

1IRQb

Execution

Read

1Write

Read

0Write

Clear in error

Occurrence condition 1

IRQaF

IRQbF

Occurrence condition 2

Figure 5.9 IRQ nF F lag When Interrupt Processing Is No t Conducted

Rev. 6.0, 09/02, page 120 of 876

In this situatio n, conduct one of the following countermeasures.

Countermeasure 1: When clears IRQaF flag, do not use th e bit manipulation instruction, read the

ISR in bytes. Then write a value in bytes which sets IRQnF flag to 0 and other bits to 1.

For example, if a = 0

MOV.B @ISR,R0L

MOV.B #HFE,R0L

MOV.B R0L,@ISR

Countermeasure 2: During IRQb interrupt exception processing, carry ou t IRQbF flag clear

dummy processing.

For example, if b = 1

IRQB MOV.B #HFD,R0L

MOV.B R0L,@ISR

5.5.5 Notes on Non-Maskable Interrupts (NMI)

NMI is an exception processing that can be executed by the interrupt controller and CPU when the

chip internal circuits are operating normally under a specified electrical characteristics. If an NMI

is executed when the circuits are not operating normally due to some factors such as software or

abnormal interrupt of input to the pins (r unaway execution), the operation will not be guaranteed.

Incorrect NMI Operation Factors: Software

1. When an interrupt exception processing is executed in an H8/300H CPU, it is assu med that the

stack pointer (SP(ER7)) has already been set by software, and that the stack pointer (SP(ER7))

points to the stack area set in a sy stem such as RAM. If the program is in a runaway execution,

the stack pointer may be overflowed and updated illegally. Therefore, norma l oper ation will

not be guaranteed.

2. Requests for NMIs can be accepted on the rising or falling edge of a pin. Acceptance of the

rising or falling edge depends on the setting of the bit NMIEG in the system contro l register

(SYSCR). It is necessar y for the customer to set the bit according to the designated system.

When the pr ogra m is in a runaway execution, this bit may be rewr itten illegally. Therefore, the

system may not operate as expected.

3. This chip has a break function to implement on-board emulation for specific customers. To use

this break f unction, execute the BRK instruction (H’5770). Note that the BRK instruction is

usually undefined. Therefore, if the CPU accidentally executes the instruction, the chip will

Rev. 6.0, 09/02, page 121 of 876

perform excep tional p rocessin g and will enter the break mode. In the break mode, interrupts

including the NMI are inhibited and the count of the watch dog timer will be stopped. Then by

executing th e RTB (H’56F0) instruction, th e break mod e will be cancelled, and usual program

execution will r e su me. When the execution is reset during break mode, the CPU enter s the

reset state and the break mode is cancelled. Once the reset has been cancelled, normal program

execution will r e su me after the reset exception processing has been executed.

Incorrect NMI Operation Factors: Abnormal Interrupts Input to the Chip Pins

If an abnormal interrupt which was not specified in the electrical characteristics is input to a pin

during a chip oper a tion, the chip may be destroyed. In th is case, the operation of the chip will not

be guaranteed.

When an abnormal interrupt has been input to a pin, the chip may not be destroyed; ho wever, the

internal circu its of the chip may partially or wh olly malfunction, and the CPU may enter an

unimagined undefined state when the CPU was designed. I f this occurs, it will be impo ssible to

control the operation of the chip by external pins other than the external reset and standby pins,

and the operation of the NMI will not be guaranteed. In this case, after some specified signals have

been input to th e pins, input an ex ternal r eset so that the chip can enter the normal program

execution state again.

Rev. 6.0, 09/02, page 122 of 876

Rev. 6.0, 09/02, page 123 of 876

Section 6 Bus Controller

6.1 Overview

The H8/3048 Series has an on -chip bus controller that divides the address space into eight areas

and can assign different bus specifications to each. This enables different types of memory to be

connected easily.

A bus arbitration function of the bus controller controls the operation of the DMA controller

(DMAC) and refresh controller. The bus controller can also release the bus to an external device.

6.1.1 Features

Features of th e bus controller are listed below.

• Independent settings for address areas 7 to 0

 128-kbyte areas in 1-Mbyte modes; 2-Mbyte areas in 16-Mbyte modes.

 Chip select sign a ls (CS7 to CS0) can be output for areas 7 to 0.

 Areas can be designated for 8-bit or 16-bit access.

 Areas can be designated for two-state or three-state access.

• Four wait modes

 Programmable wait mode, pin auto-wait mode, and pin wait modes 0 and 1 can be selected.

 Zero to three wait states can be inserted automatically.

• Bus arbitration func tion

 A built-in b us arbiter arbitrates the bus right to the CPU, DMAC, r efresh controller, or an

external bus master.

Rev. 6.0, 09/02, page 124 of 876

6.1.2 Block Diagram

Figure 6.1 shows a block diagram of the bus controller.

7to

ABWCR

ASTCR

WCER

CSCR

Chip select

control signals

Internal

address bus Area

decoder

Bus control

circuit

Wait-state

controller

Internal data bus

Legend

ABWCR:

ASTCR:

WCER:

WCR:

BRCR:

CSCR:

Bus width control register

Access state control register

Wait state controller enable register

Wait control register

Bus release control register

Chip select control register

CPU bus request signal

DMAC bus request signal

Refresh controller bus request signal

CPU bus acknowledge signal

DMAC bus acknowledge signal

Refresh controller bus acknowledge signal

Internal signals

WCR

BRCR

Bus arbiter

Bus mode control signal

Bus size control signal

Access state control signal

Wait request signal

Internal signals

Figure 6.1 Block Diagram of Bus Controller

Rev. 6.0, 09/02, page 125 of 876

6.1.3 Input/Output Pins

Table 6.1 summarizes the bus controller’s input/output pins.

Table 6.1 Bus Controller Pins

Name Abbreviation I/O Function

Chip select 7 to 0 CS7 to CS0Output Strobe signals selecting areas 7 to 0

Address strobe AS Output Strobe signal indicating valid address output

on the address bus

Read RD Output Strobe signal indicating reading from the

external addr es s spac e

High write HWR Output Strobe signal indicating writing to the

external address space, with valid data on

the upper data bus (D15 to D8)

Low write LWR Output Strobe signal indicating writing to the

external address space, with valid data on

the lower data bus (D7 to D0)

Wait WAIT Input Wait request signal for access to external

three-state -ac ce ss area s

Bus request BREQ Input Request signal for releasing the bus to an

external dev ice

Bus acknowledge BACK Output Acknowledge signal indicating the bus is

released to an external device

Rev. 6.0, 09/02, page 126 of 876

6.1.4 Register Configuration

Table 6.2 summarizes the bus controller’s registers.

Table 6.2 Bus Controller Registers

Initial Value

Address*Name Abbreviation R/W Modes

1, 3, 5, 6 Modes

2, 4, 7

H'FFEC Bus width control register ABWCR R/W H'FF H'00

H'FFED Access state control register ASTCR R/W H'FF H'FF

H'FFEE Wait control register WCR R/W H'F3 H'F3

H'FFEF Wait state controller enable

H'FFF3 Bus release control register BRCR R/W H'FE H'FE

H'FF5F Chip select control register CSCR R/W H'0F H'0F

Note: * Lower 16 bits of the address.

6.2 Register Descriptions

6.2.1 Bus Width Co ntrol Register (ABWCR)

ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.

Bit

Read/Write

ABW7

R/W

ABW6

R/W

ABW5

R/W

ABW4

R/W

ABW3

R/W

ABW0

R/W

ABW2

R/W

ABW1

R/W

Bits selecting bus width for each area

Initial

value Mode 1, 3, 5, 6

Mode 2, 4, 7

When ABWCR contains H'FF (selecting 8-bit access for all areas), the ch ip operates in 8-bit bus

mode: the upper data bus (D15 to D8) is valid, and port 4 is an inpu t/output port. When at least one

bit is cleared to 0 in ABWCR, the chip o perates in 16-bit bus mode with a 16-bit data bus (D15 to

D0). In modes 1, 3, 5, and 6 ABWCR is initialized to H'FF by a reset and in hardware standby

mode. In modes 2, 4, and 7 ABWCR is initialized to H'00 by a reset and in hardware standby

mode. ABWCR is not initialized in software standby mode.

Rev. 6.0, 09/02, page 127 of 876

Bits 7 to 0—Areas 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access

or 16-bit access to the corresponding address areas.

Bits 7 to 0:

ABW7 to ABW0 Description

0 Areas 7 to 0 are 16-bit access areas

1 Areas 7 to 0 are 8-bit access areas

ABWCR specifies the bus width of external memory areas. The bus width of on-chip memory and

internal I/O registers is fixed and does not depend on ABWCR settings. These settings are

therefore meaningless in single-chip mode (mode 7).

6.2.2 Access State Control Register (ASTCR)

ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two

states or three states.

Bit

Initial value

Read/Write

AST7

R/W

AST6

R/W

AST5

R/W

AST4

R/W

AST3

R/W

AST0

R/W

AST2

R/W

AST1

R/W

Bits selecting number of states for access to each area

ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Areas 7 to 0 Access State Control (AST7 to AST0): These bits select whether the

corresponding area is accessed in two or three states.

Bits 7 to 0:

AST7 to AST0 Description

0 Areas 7 to 0 are accessed in two states

1 Areas 7 to 0 are accessed in three states (Initial value)

ASTCR specifies the number of states in which external areas are accessed. On-chip memory and

internal I/O registers are accessed in a fixed number of states that does not depend on ASTCR

settings. These settings are therefore meaningless in single-chip mode (mode 7).

Rev. 6.0, 09/02, page 128 of 876

6.2.3 Wait Control Register (WCR)

WCR is an 8-bit readable/writable re gister that selects the wait mod e for the wait-state controller

(WSC) and specifies the number of wait states.

Bit

Initial value

Read/Write

—

WMS1

R/W

WC0

R/W

WMS0

R/W

WC1

R/W

Wait count 1/0

These bits select the

number of wait states

inserted

Reserved bits

Wait mode select 1/0

These bits select the wait mode

WCR is initia lized to H'F3 by a re set and in hardware standby mode . I t is not initialized in

software standby mode.

Bits 7 to 4—Reserved: Read-only bits, always read as 1.

Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode.

Bit 3: WMS1 Bit 2: WMS0 Description

0 0 Programmable wait mode (Initial value)

1 No wait states inserted by wait-state controller

1 0 Pin wait mode 1

1 Pin auto-wait mode

Bits 1 and 0—Wa it Count 1 and 0 (WC1/0): These bits select the number of wait states inserted

in access to external three-state-access areas.

Bit 1: WC1 Bit 0: WC0 Description

0 0 No wait states inserted by wait-state controller

1 1 state inserted

1 0 2 states inserted

1 3 states in serte d (Initial value)

Rev. 6.0, 09/02, page 129 of 876

6.2.4 Wait State Controller Enable Register (WCER)

WCER is an 8-bit readable/writable register that enables or disables wait-state control of external

three-state-access areas by the wait-state controller.

Bit

Initial value

Read/Write

WCE7

R/W

WCE6

R/W

WCE5

R/W

WCE4

R/W

WCE3

R/W

WCE0

R/W

WCE2

R/W

WCE1

R/W

Wait-state controller enable 7 to 0

These bits enable or disable wait-state control

WCER is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Wait-State Controller Enable 7 to 0 (WCE7 to WCE0): These bits enable or

disable wait-state control of external three-state-access areas.

Bits 7 to 0:

WCE7 to WCE0 Description

0 Wait-state control disabled (pin wait mode 0)

1 Wait-state control enabled (Initial value)

Since WCER enables or disables wait-state control of external three-state-access areas, these

settings are meaningless in single-chip mode (mode 7).

Rev. 6.0, 09/02, page 130 of 876

6.2.5 Bus Release Control Register (BRCR)

BRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A21 and

enables or disables release of the bus to an external device.

Bit

Initial value

A23E

—

R/W

A22E

—

R/W

A21E

—

R/W

—

BRLE

R/W

—

Bus release enable

Enables or disables

release of the bus to

an external device

Reserved bitsAddress 23 to 21 enable

These bits enable PA to

PA to be used for A to

A address output

21 23

Read/

Write

Mode 1, 2, 5, 7

Mode 3, 4, 6

BRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin. Writing

0 in this bit enables A23 address output from PA4. In modes other than 3, 4, and 6 this bit cannot be

modified and PA4 has its ordinary input/output functions.

Bit 7: A23E Description

0PA

4 is the A23 address output pin

1PA

4 is the PA4/TP4/TIOCA1 input/output pin (Initial value)

Bit 6—Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin. Writing

0 in this bit enables A22 address output from PA5. In modes other than 3, 4, and 6 this bit cannot be

modified and PA5 has its ordinary input/output functions.

Bit 6: A22E Description

0PA

5 is the A22 address output pin

1PA

5 is the PA5/TP5/TIOCB1 input/output pin (Initial value)

Rev. 6.0, 09/02, page 131 of 876

Bit 5—Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin. Writing

0 in this bit enables A21 address output from PA6. In modes other than 3, 4, and 6 this bit cannot be

modified and PA6 has its ordinary input/output functions.

Bit 5: A21E Description

0PA

6 is the A21 address output pin

1PA

6 is the PA6/TP6/TIOCA2 input/output pin (Initial value)

Bits 4 to 1—Reserved: Read-only bits, always read as 1.

Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.

Bit 0: BRLE Description

0 The bus cannot be released to an external devic e; BREQ and BACK can be

used as input/output pins (Initial value)

1 The bus can be released to an external device

6.2.6 Chip Select Control Register (CSCR)

CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals

(CS7 to CS4).

If a chip select signal (CS7 to CS4) output is selected in this register, the corresponding pin

functions as a chip select signal (CS7 to CS4) output, this function taking priority over other

functions. CSCR cannot be modified in single-chip mode.

Bit

Initial value

Read/Write

CS7E

R/W

CS6E

R/W

CS5E

R/W

CS4E

R/W

—

Chip select 7 to 4 enable

These bits enable or disable

chip select signal output

Reserved bits

CSCR is initialized to H'0F by a reset and in hardwar e standby mode. It is not initialized in

software standby mode.

Rev. 6.0, 09/02, page 132 of 876

Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable ou tput of

the corresponding chip select signal.

Bit n: CSnE Description

0 Output of chip select signal CSn is disabled (Initial value)

1 Output of chip select signal CSn is enabled

Note: n = 7 to 4

Bits 3 to 0—Reserved: Read-only bits, always read as 1.

Rev. 6.0, 09/02, page 133 of 876

6.3 Operation

6.3.1 Area Division

The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the

1-Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the

memory map.

H'00000 Area 0 (128 kbytes)

Area 1 (128 kbytes)

Area 2 (128 kbytes)

Area 3 (128 kbytes)

Area 4 (128 kbytes)

Area 5 (128 kbytes)

Area 6 (128 kbytes)

Area 7 (128 kbytes)

On-chip RAM

External address space

Internal I/O registers

* *1 2

Notes: The on-chip ROM, on-chip RAM, and internal I/O registers have a fixed bus width and are accessed in a

fixed number of states.

When the RAME bit is cleared to 0 in SYSCR, this area conforms to the specifications of area 7.

This external address area conforms to the specifications of area 7.

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

H'DFFFF

H'E0000

H'FFFFF

H'000000 Area 0 (2 Mbytes)

Area 1 (2 Mbytes)

Area 2 (2 Mbytes)

Area 3 (2 Mbytes)

Area 4 (2 Mbytes)

Area 5 (2 Mbytes)

Area 6 (2 Mbytes)

Area 7 (2 Mbytes)

On-chip RAM

External address space

Internal I/O registers

* *1 2

H'1FFFFF

H'200000

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

H'FFFFFF

H'000000

H'1FFFFF

H'200000

H'3FFFFF

H'400000

H'5FFFFF

H'600000

H'7FFFFF

H'800000

H'9FFFFF

H'A00000

H'BFFFFF

H'C00000

H'DFFFFF

H'E00000

H'FFFFFF

H'00000

Area 1 (128 kbytes)

Area 2 (128 kbytes)

Area 3 (128 kbytes)

Area 4 (128 kbytes)

Area 5 (128 kbytes)

Area 6 (128 kbytes)

* *1 2

H'1FFFF

H'20000

H'3FFFF

H'40000

H'5FFFF

H'60000

H'7FFFF

H'80000

H'9FFFF

H'A0000

H'BFFFF

H'C0000

H'DFFFF

H'E0000

H'FFFFF

1-Mbyte modes with

on-chip ROM disabled

(modes 1 and 2)

16-Mbyte modes with

on-chip ROM disabled

(modes 3 and 4)

c. 1-Mbyte mode with

on-chip ROM enabled

(mode 5)

Area 7 (128 kbytes)

On-chip RAM

External address space

Internal I/O registers

On-chip ROM

Area 0 (128 kbytes)

Area 1 (2 Mbytes)

Area 2 (2 Mbytes)

Area 3 (2 Mbytes)

Area 4 (2 Mbytes)

Area 5 (2 Mbytes)

Area 6 (2 Mbytes)

* *1 2

d. 16-Mbyte mode with

on-chip ROM enabled

(mode 6)

Area 7 (2 Mbytes)

On-chip RAM

External address space

Internal I/O registers

On-chip ROM

Area 0 (2 Mbytes)

Figure 6.2 Access Area Map for Modes 1 to 6

Rev. 6.0, 09/02, page 134 of 876

Chip select sign a ls (CS7 to CS0) can be output for areas 7 to 0. The bus specifications for each area

can be selected in ABWCR, ASTCR, WCER, and WCR as shown in table 6.3.

Table 6.3 Bus Specifications

ABWCR ASTCR WCER WCR Bus Specifications

ABWn ASTn WCEn WMS1 WMS0 Bus

Width Access

States Wait Mode

00———162Disabled

1 0 — — 16 3 Pin wait mode 0

1 0 0 16 3 Programmable wait mode

1163Disabled

1 0 16 3 Pin wait mode 1

1 16 3 Pin auto-wait mode

1 0 — — — 8 2 Disabled

1 0 — — 8 3 Pin wait mode 0

1 0 0 8 3 Programmable wait mode

1 8 3 Disabled

1 0 8 3 Pin wait mode 1

1 8 3 Pin auto-wait mode

Note: n = 0 to 7

6.3.2 Chip Select Signals

For each of areas 7 to 0, the H8/3048 Series can output a chip select signal (CS7 to CS0) that goes

low to indicate when the area is selected. Figure 6.3 shows the output timing of a CSn signal (n = 0

to 7).

Output of CS

CSCS

CS3 to CS

CSCS

CS0: Output of CS3 to CS0 is enabled or disabled in the data direction register

(DDR) of the corresponding port.

In the expanded modes with on-chip ROM disabled, a reset leaves pin CS0 in the output state and

pins CS3 to CS1 in the input state. To output chip select signals CS3 to CS1, the corresponding DDR

bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins CS3 to

CS0 in the input state. To output chip select signals CS3 to CS0, the corresponding DDR bits must

be set to 1. For details see section 9, I/O Ports.

Rev. 6.0, 09/02, page 135 of 876

Output of CS

CSCS

CS7 to CS

CSCS

CS4: Output of CS7 to CS4 is enabled or disabled in the chip select control

to CS4, the corresponding CSCR bits must be set to 1. For details see section 9, I/O Ports.

Address

bus

External address in area n

Figure 6.3 CS

CSCS

CSn Output Timing ( n = 7 to 0)

When the on-chip ROM, on-chip RAM, and internal I/O registers are accessed, CS7 and CS0

remain high. The CSn signals are decoded from the address signals. They can be used as chip

select signals for SRAM and other devices.

Rev. 6.0, 09/02, page 136 of 876

6.3.3 Data Bus

The H8/3048 Series allows either 8-bit access or 16-bit access to be designated for each of areas

7 to 0. An 8-bit-access area uses the upper data bus (D15 to D8). A 16-bit-access area uses both the

upper data bus (D15 to D8) and lower data bus (D7 to D0).

In read access the RD signal applies without distinction to both the upper and lower data bus. In

write access the HWR signal applies to the upper data bus, and the LWR signal applies to the

lower data bus.

Table 6.4 indicates how the two parts of the data bus are used under different access conditions.

Table 6.4 Access Cond itions and Data Bus Usage

Area Access

Size Read/W

rite Address Valid

Strobe Upper Data Bus

(D15 to D8)Lower Data Bus

(D7 to D0)

— Read — RD Valid Invalid

8-bit-access

area Write — HWR Undetermined data

Byte Read Even RD Valid Invalid16-bit-access

area Odd Invalid Valid

Write Even HWR Valid Undetermined data

Odd LWR Undetermined data Valid

Word Read — RD Valid Valid

Write — HWR,

LWR Valid Valid

Note: Undetermined data means that unpredictable data is output.

Invalid means that the bus is in the input state and the inp ut is ignore d.

Rev. 6.0, 09/02, page 137 of 876

6.3.4 Bus Control Signal Timing

8-Bit, Three-State-Access Areas: Figure 6.4 shows the timing of bus control signals for an 8-bit,

three-state-access area. The upper address bus (D15 to D8) is used to access these areas. The LWR

pin is always high. Wait states can be inserted.

Address bus

D to D

15 8

7 0

15 8

7 0

1 T

2 T

Read

access

Write

access

Bus cycle

External address in area n

Valid

Invalid

High

Valid

Undetermined data

Note: n = 7 to 0

Figure 6.4 Bus Control Signal Timing for 8-Bit, Three-State-Access Area

Rev. 6.0, 09/02, page 138 of 876

8-Bit, Two-State-Access Areas: Figure 6.5 shows the timing of bus control signals for an 8-bit,

two-state-access area. The upper address bus (D15 to D8) is used to access these areas. The LWR

pin is always high. Wait states cannot be inserted.

Address bus

D to D

15 8

7 0

15 8

7 0

Read

access

Write

access

High

Bus cycle

External address in area n

Valid

Invalid

Valid

Undetermined data

Note: n = 7 to 0

Figure 6.5 Bus Control Signal Timing for 8-Bit, Two-State-Access Area

Rev. 6.0, 09/02, page 139 of 876

16-Bit, Three-State-Access Areas: Figures 6.6 to 6.8 show the timing of bus control signals for a

16-bit, three-state-access area. In these areas, the upper address bus (D15 to D8) is used to access

even addresses and the lower address bus (D7 to D0) is used to access odd addresses. Wait states

can be inserted.

Address bus

D to D

15 8

7 0

15 8

7 0

1 T

2 T

Read

access

Write

access

Bus cycle

Even external address in area n

Valid

Invalid

Valid

Undetermined data

High

Note: n = 7 to 0

Figure 6.6 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)

(Byte Access to Even Address)

Rev. 6.0, 09/02, page 140 of 876

Address bus

D to D

15 8

7 0

15 8

7 0

1 T

2 T

Read

access

Write

access

Bus cycle

Odd external address in area n

Invalid

Valid

Undetermined data

Valid

High

Note: n = 7 to 0

Figure 6.7 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)

(Byte Access to Odd Address)

Rev. 6.0, 09/02, page 141 of 876

Address bus

D to D

15 8

7 0

15 8

7 0

1 T

2 T

Read

access

Bus cycle

External address in area n

Valid

Write

access

Note: n = 7 to 0

Figure 6.8 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)

(Word Access)

Rev. 6.0, 09/02, page 142 of 876

16-Bit, Two-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for a

16-bit, two-state-access area. In these areas, the upper address bus (D15 to D8) is used to access

even addresses and the lower address bus (D7 to D0) is used to access odd addresses. Wait states

cannot be inserted.

Address bus

D to D

15 8

7 0

15 8

7 0

1 T

Read

access

Write

access

Valid

Undetermined data

High

Valid

Invalid

Bus cycle

Even external address in area n

Note: n = 7 to 0

Figure 6.9 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)

(Byte Access to Even Address)

Rev. 6.0, 09/02, page 143 of 876

Address bus

D to D

15 8

7 0

15 8

7 0

1 T

Read

access Invalid

Valid

High

Bus cycle

Odd external address in area n

Write

access

Undetermined data

Valid

Note: n = 7 to 0

Figure 6.10 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)

(Byte Access to Odd Address)

Rev. 6.0, 09/02, page 144 of 876

Address bus

D to D

15 8

7 0

15 8

7 0

1 T

Read

access

Write

access

Valid

Bus cycle

External address in area n

Note: n = 7 to 0

Figure 6.11 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)

(Word Access)

Rev. 6.0, 09/02, page 145 of 876

6.3.5 Wait Modes

Four wait modes can be selected as shown in table 6.5.

Table 6.5 Wait Mode Select ion

ASTCR WCER WCR

ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control Wai t Mode

0 — — — Disabled No wait states

1 0 — — Disabled Pin wait mode 0

1 0 0 Enabled Programmable wait mode

1 Enabled No wait states

1 0 Enabled Pin wait mode 1

1 Enabled Pin auto-wait mode

Note: n = 7 to 0

Rev. 6.0, 09/02, page 146 of 876

Wait Mode in Areas Where Wait-State Controller is Disabled

External three-state access areas in which the wait-state controller is disabled (ASTn = 1, WCEn =

0) operate in pin wait mode 0. The other wait modes are unavailable. The settings of bits WMS1

and WMS0 are ignored in these areas.

Pin Wait Mode 0: Wait states can only be inserted by WAIT pin control. During access to an

external three-state-access area, if the WAIT pin is low at the fall of the system clock (φ) in the T2

state, a wait state (TW) is inserted. If the WAIT pin remains low, wait states co ntinue to be inserted

until the WAIT signal goes high. Figure 6.12 shows the tim ing.

Address bus

Data bus

Inserted by signal

Write data

Read data

Read

access

Write

access

External address

Note: Arrows indicate time of sampling of the pin.*

Figure 6.12 Pin Wait Mode 0

Rev. 6.0, 09/02, page 147 of 876

Wait Modes in Areas Where Wait-State Controller is Enabled

External three-state access areas in which the wait-state controller is enabled (ASTn = 1, WCEn =

1) can operate in pin wait mode 1, pin auto-wait mode, or programmable wait mode, as selected

by bits WMS1 and WMS0. Bits WMS1 and WMS0 apply to all areas, so all areas in which the

wait-state controller is enabled operate in the same wait mode.

Pin Wait Mode 1: In all accesses to external three-state-access areas, the number of wait states

(TW) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of th e system

clock (φ) in the last of these wait states, an ad ditional wait state is inserted. I f the WAIT pin

remains low, wait states continue to b e inserted until the WAIT signal goes high.

Pin wait mode 1 is useful for inserting four or more wait states, or for inserting different numbers

of wait states for different external devices.

If the wait count is 0 , this mode operates in the sam e way as pin wait mode 0.

Figure 6.13 shows the timin g when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional

wait state is inserted by WAIT input.

Address bus

Data bus

1 T

2 T

W T

Write data

Read data

Read

access

Write

access

Note: Arrows indicate time of sampling of the pin.*

Data bus

External address

Write data

Inserted by

wait count Inserted by

signal

Figure 6.13 Pin Wait Mode 1

Rev. 6.0, 09/02, page 148 of 876

Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (TW) selected by bits

WC1 and WC0 are inserted.

In pin auto-wait mode, if the WAIT pin is low at the fall of the system clo c k (φ) in the T2 state, the

number of wait states (TW) selected by bits WC1 and WC0 are inserted. No additional wait states

are inserted even if the WAIT pin remains low. Pin auto-wait mode can be used for an easy

interface to low-speed memory, simply by routing the chip select signal to the WAIT pin.

Figure 6.14 shows the timing when the wait count is 1.

Address bus

Data bus

Read data Read data

Write data Write data

Read

access

Write

access

Note: Arrows indicate time of sampling of the pin.*

External address External address

Figure 6.14 Pin Auto-Wait Mode

Rev. 6.0, 09/02, page 149 of 876

Programmable Wait Mode: The number of wait states (TW) selected by bits WC1 and WC0 are

inserted in all accesses to external three-state-access areas. Figure 6.15 shows the timing when the

wait count is 1 (WC1 = 0, WC0 = 1).

1 T

2 T

W T

Address bus

Data bus

External address

Read data

Write data

Read

access

Write

access

Figure 6.15 Programmable Wait Mode

Rev. 6.0, 09/02, page 150 of 876

Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF an d

WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can

select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings.

Figure 6.16 shows an example of wait mode settings.

76543210

—

Bit:

ASTCR H'0F:

WCER H'33:

WCR H'F3:

Area 0

Area 1

Area 2

Area 3

Area 4

Area 5

Area 6

Area 7

3-state-access area,

programmable wait mode

(3 states inserted)

3-state-access area,

programmable wait mode

(3 states inserted)

3-state-access area,

pin wait mode 0

3-state-access area,

pin wait mode 0

2-state-access area,

no wait states inserted

2-state-access area,

no wait states inserted

2-state-access area,

no wait states inserted

2-state-access area,

no wait states inserted

Note: Wait states cannot be inserted in areas designated for two-state access by ASTCR.

Figure 6.16 Wait Mode Settings (Example)

Rev. 6.0, 09/02, page 151 of 876

6.3.6 Interconnections with Memory (Example)

For each area, the bus controller can select two- or three-state access and an 8- or 16-bit data bus

width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the

connection of both high-s peed and low-speed devices .

Figure 6.18 shows an example of interconnections between the H8/3048 Series and memory.

Figure 6.17 shows a memory map for this example.

A 256-kword × 16-bit EPROM is connected to area 0. This device is accessed in three states via a

16-bit bus.

Two 32-kword × 8-bit SRAM devices (SRAM1 and SRAM2) are connected to area 1. These

devices are accessed in two states via a 16-bit bus.

One 32-kword × 8-bit SRAM (SRAM3) is connected to area 2. This device is accessed via an 8-bit

bus, using three-state access with an additional wait state inserted in pin auto-wait mode.

H'000000

H'07FFFF

H'1FFFFF

H'200000

H'20FFFF

H'210000

H'3FFFFF

H'400000

H'FFFFFF

On-chip RAM

Internal I/O registers

EPROM

Not used

SRAM 1, 2

Not used

SRAM 3

Area 0

16-bit, three-state-access area

Area 1

16-bit, two-state-access area

Area 2

8-bit, three-state-access area

(one auto-wait state)

H'407FFF

H'5FFFFF

Not used

Figure 6.17 Memory Map (Example)

Rev. 6.0, 09/02, page 152 of 876

EPROM

A to A

I/O to I/O

A to A

19 1

SRAM1 (even addresses)

A to A

I/O to I/O

A to A

15 1

SRAM2 (odd addresses)

A to A

I/O to I/O

A to A

15 1

SRAM3

A to A

I/O to I/O

A to A

14 0

H8/3048 Series

A to A

23 0

D to D

15 8

7 0

Figure 6.18 Interconnections with Memory (Example)

Rev. 6.0, 09/02, page 153 of 876

6.3.7 Bus Arbiter Operation

The bus controller has a built-in bus arbiter that arbitrates between different bus masters. Th er e ar e

four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus

master. When a bus master has the bus right it can carry out read, write, or refresh access. Each

bus master uses a bus request signal to request the bus right. At fixed times the bus arbiter

determines priority and uses a bus ackno wledge signal to grant the bus to a bus master, which can

then operate using the bus.

The bus arbiter checks whether the bus request signal from a bu s master is active or inactive, and

returns an acknowledge signal to the bus master if the bus request signal is active. When two or

more bus masters request the bus, the highest-priority bus master receives an acknowledge signal.

The bus master that receives an acknowledge signal can continue to use the bus until the

acknowledge signal is deactivated.

The bus master prior ity order is:

(High) External bus master > refresh controller > DMAC > CPU (Low)

The bus arbiter samp les the bus request signa ls an d determines prior ity at all times, but it does not

always grant the bus immediately, even when it receives a bus request from a bus master with

higher priority than the current bus master. Each bus master has certain times at which it can

release the bus to a higher-priority bus master.

CPU: The CPU is the lowest-p r io rity bus master. If the DMAC, ref r esh controller, or an external

bus master requests the bus while the CPU has the bus right, the bus arbiter transfers the bus right

to the bus master that requested it. The bus right is transferred at the following times:

• The bus right is transferred at the boundary of a bus cycle. If word data is accessed by two

consecutive byte accesses, however, the bus right is not transferred between the two byte

accesses.

• If another bus master requests the bus while the CPU is performing internal operations, such as

executing a multip ly or divide instruction , the bus right is transferred imme diately. The CPU

continu e s its internal operations.

• If another bus master requests the bus while the CPU is in sleep mode, the bus right is

transferred immediately.

Rev. 6.0, 09/02, page 154 of 876

DMAC: When the DMAC receives an activation request, it requests the bus right from the bus

arbiter. If the DMAC is bus master and the refresh controller or an external bus master requests

the bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the

bus. The bus righ t is transferred at the following times.

The bus right is transferred when the DMAC finishes transferring 1 byte or 1 word. A DMAC

transfer cycle consists of a read cycle and a write cycle. The bus right is not transferred between

the read cycle and the write cycle.

There is a priority order among the DMAC channels. For details see section 8.4.9, DMAC

Multiple-Channel Operation.

Refresh Controller: When a refresh cycle is requested, the refresh controller requests the bus

right from the bus arbiter. When the refresh cycle is completed, the refresh controller releases the

bus. For details see section 7, Refresh Controller.

External Bus Master: When the BRLE bit is set to 1 in BRCR, the b us can be released to an

external bus master. The external bus master has highest priority, and requests the bus right from

the bus arbiter by driv ing the BREQ signal low. Once the external bus master gets the bus, it keeps

the bus right until the BREQ signal goes high. While the bus is released to an external bus master,

the H8/3048 Series holds the address bus and data bus control signals (AS, RD, HWR, and LWR)

in the high-impedance state, holds the ch ip select signals high (CSn: n = 7 to 0), and holds the

BACK pin in the low outpu t state.

The bus arbiter samples the BREQ pin at the rise of the system clock (φ). If BREQ is low, the bus

is released to the external bus master at the appropriate opportunity. The BREQ signal should be

held low u ntil the BACK signal goes low.

When the BREQ pin is high in two consecutive samples, the BACK signal is driven high to end

the bus-release cycle.

Rev. 6.0, 09/02, page 155 of 876

Figure 6.19 shows the timing when the bus right is requested by an external bus master during a

read cycle in a two-state-access area. There is a minimum interval of two states from when the

BREQ signal goes lo w until the bus is released.

Data bus

1 T

Address

21 3456

High

CPU cycles External bus released CPU cycles

Minimum 2 cycles

High-impedance

4, 5

Low signal is sampled at rise of T state.

signal goes low at end of CPU read cycle, releasing bus right to external bus master.

pin continues to be sampled while bus is released to external bus master.

High signal is sampled twice consecutively.

signal goes high, ending bus-release cycle.

Address

bus

High level

n = 7 to 0

Figure 6.19 External-Bus-Released State (Two-State-Access Area, During Read Cycle)

Rev. 6.0, 09/02, page 156 of 876

6.4 Usage Notes

6.4.1 Connection t o Dynamic RAM and Pseudo-Static RAM

A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is

connected to area 3. For details see section 7, Refresh Controller.

6.4.2 Register Write Timing

ABWCR, ASTCR, and WCER Write Ti ming: Data written to ABWCR, ASTCR, or WCER

takes effect starting from the next bus cycle. Figure 6.20 shows the timing when an instruction

fetched from area 0 changes area 0 from three-state access to two-state access.

1 T

2 T

3 T

1 T

2 T

3 T

1 T

ASTCR address

3-state access to area 0 2-state access

to area 0

Address

bus

Figure 6.20 ASTCR Write Timing

Rev. 6.0, 09/02, page 157 of 876

DDR Write Timing: Data written to a data direction register (DDR) to change a CSn pin from CSn

output to generic input, or vice versa, takes effect starting from the T3 state of the DDR write

cycle. Figure 6.21 shows the timing when the CS1 pin is changed from generic input to CS1 output.

P8DDR address

High impedance

Address

bus

Figure 6.21 DDR Write Timing

BRCR Write Timing: Data written to switch between A23, A22, or A21 output and generic input or

output takes effect starting from the T3 state of the BRCR write cycle. Figure 6.22 show s the

timing when a pin is changed from generic input to A23, A22, or A21 output.

A to A

BRCR address

High impedance

Address

bus

Figure 6.22 BRCR Write Timing

Rev. 6.0, 09/02, page 158 of 876

6.4.3 BREQ

BREQBREQ

BREQ Input Timing

After driving the BREQ pin lo w, hold it low until BACK goes low. If BREQ returns to the high

level befo re BACK goes low, the bus arbiter may operate incorrectly.

To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If

BREQ is high for too short an interval, the bu s arbiter may operate incorrectly.

6.4.4 Transitio n To Soft w are Standby Mode

If contention occurs between a transition to software standby mode and a bus request from an

external bus master, the bus may be released for one state just before the transition to software

standby mode (see figure 6.23). When using software standby mode, clear the BRLE bit to 0 in

BRCR before executing the SLEEP instruction.

Address bus

Strobe

Bus-released state Software standby mode

Figure 6.23 Contention between Bus-Released State and Software Standby Mode

Rev. 6.0, 09/02, page 159 of 876

Section 7 Refresh Controller

7.1 Overview

The H8/3048 Series has an on-chip refresh controller that enables direct connection of 16-bit-wide

DRAM or pseudo-static RAM (PSRAM).

DRAM or pseudo-static RAM can be directly connected to area 3 of the external address space.

A maximum 128 kbytes can be connected in modes 1, 2, and 5 (1-Mbyte modes). A maximum

2 Mbytes can be connected in modes 3, 4, and 6 (16-Mbyte modes).

Systems that do not need to refresh DRAM or pseudo-static RAM can use the refresh controller as

an 8-bit in terval tim er .

When the ref r esh controller is not used, it can be independen tly halted to conserve power. For

details see section 21.6, Module Standby Function.

7.1.1 Features

The refresh controller can be used for one of three functions: DRAM refresh control, pseudo-static

RAM refresh co ntrol, or 8-bit interval tim ing. Features of the refresh controller ar e listed below.

Features as a DRAM Refresh Controller

• Enables direct connection of 16-bit-wide DRAM

• Selection of 2CAS or 2WE mode

• Selection of 8-bit or 9-bit column address multiplexing for DRAM address input

Examples:

 1-Mbit DRAM: 8- bit row address × 8-bit column address

 4-Mbit DRAM: 9- bit row address × 9-bit column address

 4-Mbit DRAM: 10-bit row address × 8-bit column address

• CAS-before-RAS refresh control

• Software-selectable refresh interval

• Software-selectable self-refresh mode

• Wait states can be inserted

Features as a Pseudo-Static RAM Refresh Controller

• RFSH signal output for refresh control

• Software-selectable refresh interval

Rev. 6.0, 09/02, page 160 of 876

• Software-selectable self-refresh mode

• Wait states can be inserted

Features as an Interval Timer

• Refresh timer counter (RTCNT) can be used as an 8-bit up-counter

• Selection of seven counter clock sources: φ/2, φ/8, φ/32, φ/128, φ/512, φ/2048, φ/4096

• Interrupts can be generated by compare match between RTCNT and the refresh time constant

7.1.2 Block Diagram

Figure 7.1 shows a block diagram of the refresh controller.

φ/2, φ/8, φ/32,

φ/128, φ/512,

φ/2048, φ/4096

RTCNT

RTCOR

RTMCSR

RFSHCR

Legend

RTCNT:

RTCOR:

RTMCSR:

RFSHCR:

Refresh signal

Clock selector

Comparator CMI interrupt

Bus interface

Internal data bus

Module data bus

Refresh timer counter

Refresh time constant register

Refresh timer control/status register

Refresh control register

Control logic

Figure 7.1 Block Diagram of Refresh Controller

Rev. 6.0, 09/02, page 161 of 876

7.1.3 Input/Output Pins

Table 7.1 summarizes the refresh controller’s input/output pins.

Table 7.1 Refresh Controller Pins

Signal

Pin Name Abbr. I/O Function

RFSH Refresh RFSH Output Goes low during refresh cycles;

used to refresh DRAM and PSRAM

HWR Upper write/upper column

address strobe UW/UCAS Output Connects to the UW pin of 2WE

DRAM or UCAS pin of 2CAS DRAM

LWR Lower write/lower column

address strobe LW/LCAS Output Connects to the LW pin of 2WE

DRAM or LCAS pin of 2CAS DRAM

RD Column address strobe/

write enable CAS/WE Output Connects to the CAS pin of 2WE

DRAM or WE pin of 2CAS DRAM

CS3Row address strobe RAS Output Connects to the RAS pin of DRAM

7.1.4 Register Configuration

Table 7.2 summarizes the refresh controller’s registers.

Table 7.2 Refresh Controller Registers

Address*Name Abbreviation R/W Initial Value

H'FFAC Refresh control register RFSHCR R/W H'02

H'FFAD Refresh timer control/status register RTMCSR R/W H'07

H'FFAE Refresh timer counter RTCNT R/W H'00

H'FFAF Refresh time constant register RTCOR R/W H'FF

Note: * Lower 16 bits of the address.

Rev. 6.0, 09/02, page 162 of 876

7.2 Register Descriptions

7.2.1 Refresh Control Register (RFSHCR)

RFSHCR is an 8 -bit readable/writab le r egister that selects the operatin g mode of the refresh

controller.

Bit

Initial value

Read/Write

SRFMD

R/W

PSRAME

R/W

DRAME

R/W

CAS/WE

R/W

M9/M8

R/W

RCYCE

R/W

RFSHE

R/W

—

Self-refresh mode

Selects self-refresh mode

PSRAM enable and DRAM enable

These bits enable or disable connection of pseudo-static RAM and DRAM

Strobe mode select

Selects 2 or 2 strobing of DRAM

Address multiplex mode select

Selects the number of column address bits

Refresh pin enable

Enables refresh signal output

from the refresh pin

Refresh cycle

enable

Enables or

disables

insertion of

refresh cycles

Reserved bit

RFSHCR is initialized to H'02 by a reset and in hardware standby mode.

Rev. 6.0, 09/02, page 163 of 876

Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh

during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set

to 1, pseudo-static RAM can be self-refreshed when the H8/3048 Series enters software standby

mode. When PSRAME = 0 and DRAME = 1, after the SRFMD bit is set to 1, DRAM can be self-

refreshed when the H8/3048 Series enters software standby mode. In either case, the normal

access state resu mes on exit from software standby mode.

Bit 7: SRFMD Description

0 DRAM or PSRAM self-refresh is disabled in software standby mode

(Initial value)

1 DRAM or PSRAM self-refresh is enabled in software standby mode

Bit 6—PSRAM Enable (PSRAME) and

Bit 5—DRAM Enable (DRAME): These bits enable or disable connection of pseudo-static RAM

and DRAM to area 3 of the external address space.

When DRAM or pseudo-static RAM is connected, the bus cycle and refresh cycle of area 3 consist

of three states, regardless of the setting in the access state control register (ASTCR). If AST3 = 0

in ASTCR, wait states cannot be inserted.

When the PSRAME or DRAME bit is set to 1, bits 0, 2, 3, and 4 in RFSHCR and registers

RTMCSR, RTCNT, and RTCOR are write-disabled, except that the CMF flag in RTMCSR can be

cleared by writing 0 .

Bit 6: PSRAME Bit 5: DRAME Description

0 0 Can be used as an interval timer (Initial value)

(DRAM and PSRAM cannot be directly connected)

1 DRAM can be directly connected

1 0 PSRAM can be directly connected

1 Illegal setting

Bit 4—Strobe Mo de Select (CAS/WE

WEWE

WE): Selects 2CAS or 2WE mode. The setting of th is bit is

valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or

DRAME bit is set to 1.

Bit 4: CAS/WE

WEWE

WE Description

02WE mode (Initial value)

12CAS mode

Rev. 6.0, 09/02, page 164 of 876

Bit 3—Addre ss Multiplex Mode Select (M9/M8

M8M8

M8): Selects 8-bit or 9-bit column addressing.

The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disab led

when the PSRAME or DRAME bit is set to 1.

Bit 3: M9/M8

M8M8

M8 Description

0 8-bit column address mode (Initial value)

1 9-bit column address mode

Bit 2—Refresh Pin Enable (RFSHE): Enables or disables refresh signal output from the RFSH

pin. This bit is wr ite-disabled when the PSRAME or DRAME bit is set to 1.

Bit 2: RFSHE Description

0 Refresh signal output at the RFSH pin is disabled (the RFSH pin can be used

as a generic input/output port) (Initial value)

1 Refresh signal output at the RFSH pin is enabled

Bit 1—Reserved: Read-only bit, always read as 1.

Bit 0—Refresh Cycle Enable (RCYCE): Enables or disables insertion of refresh cycles.

The setting of this bit is valid when PSRAME = 1 or DRAME = 1. When PSRAME = 0 and

DRAME = 0, refresh cycles are not in serted regardless of the setting of this bit.

Bit 0: RCYCE Description

0 Refresh cycles are disabled (Initial value)

1 Refresh cycles are enabled for area 3

Rev. 6.0, 09/02, page 165 of 876

7.2.2 Refresh Timer Control/Status Register (RTMCSR)

RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also

enables or disables interrupt requests when the refresh controller is used as an interval timer.

Bit

Initial value

Read/Write

CMF

R/(W)

CMIE

R/W

CKS2

R/W

CKS1

R/W

CKS0

R/W

—

Compare match flag

Status flag indicating that RTCNT has matched RTCOR

Reserved bitsClock select 2 to 0

These bits select an

internal clock source

for input to RTCNT

Note: Only 0 can be written, to clear the flag.*

Compare match interrupt enable

Enables or disables the CMI interrupt requested by CMF

Bits 7 and 6 ar e initialized by a reset and in standby mode . Bits 5 to 3 are initialized by a reset and

in hardware standby mode, but retain their previous valu es on transition to software standby mode.

Bit 7—Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR

values have matched.

Bit 7: CMF Description

0 [Clearing cond iti on]

Cleared by reading CMF when CMF = 1, then writing 0 in CMF

1 [Setting condition]

When RTCNT = RTCOR

Bit 6—Compare Ma tch Interrupt Enable (CMIE): Enables or disables the CMI interrupt

requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when

PSRAME = 1 or DRAME = 1.

Bit 6: CMIE Description

0 The CMI inte rrupt requested by CMF is disabled (Initial value)

1 The CMI interrupt requested by CMF is enabled

Rev. 6.0, 09/02, page 166 of 876

Bits 5 to 3—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source for

input to RTCNT. When used for refresh control, the refresh controller outputs a refresh request at

periodic intervals determined by compare match between RTCNT and RTCOR. When used as an

interval timer , the refresh controller gener a tes CMI interrupts at period ic intervals determined by

compare ma tch. These bits are write-disabled when the PSRAME bit or DRAME bit is set to 1.

Bit 5: CKS2 Bit 4: CKS1 Bit 3: CKS0 Description

0 0 0 Clock input is disabled (Initial value)

1φ/2 clock source

10φ/8 clock source

1φ/32 clock source

100φ/128 clock source

1φ/512 clock source

10φ/2048 clock source

1φ/4096 clock source

Bits 2 to 0—Reserved: Read-only bits, always read as 1.

7.2.3 Refresh Timer Counter (RTCNT)

RTCNT is an 8-bit readable/writable up-counter.

Bit

Initial value

Read/Write

R/W

RTCNT is an up-counter that is incremented by an internal clock selected by bits CKS2 to CKS0

in RTMCSR. When RTCNT matches RTCOR (compare match ) , the CMF flag is set to 1 and

RTCNT is cleared to H'00.

RTCNT is write-disab led when the PSRAME bit or DRAME bit is set to 1. RTCNT is initialized

to H'00 by a reset and in standby mode.

Rev. 6.0, 09/02, page 167 of 876

7.2.4 Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit readable/writab le r egister that determines the interval at which RTCNT is

compare matched.

Bit

Initial value

Read/Write

R/W

RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1

in RTMCSR, and RTCNT is sim ultaneously cleared to H'00.

RTCOR is write-disabled when th e PSRAME bit or DRAME bit is set to 1. RTCOR is initialized

to H'FF by a reset and in hardware standby mode. In software standby mode it retains its previous

value.

Rev. 6.0, 09/02, page 168 of 876

7.3 Operation

7.3.1 Overview

One of three functions can be selected for the H8/3048 Series refresh controller: interfacing to

DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval

timing. Table 7.3 summarizes the register settings when these three functions are used.

Table 7.3 Refresh Controller Settings

Usage

RFSHCR SRFMD Selects self-refresh

mode Select s sel f-r efresh

mode Cleared to 0

PSRAME Cleared to 0 Set to 1 Cleared to 0

DRAME Set to 1 Cleared to 0 Cleared to 0

CAS/WE Selects 2CAS or

2WE mode ——

M9/M8 Selects colum n

addressing mode ——

RFSHE Selects RFSH signal

output Selects RFSH signal

output Cleared to 0

RCYCE Selects insertio n of

refresh cycles Selects insertion of

refresh cycles —

RTCOR

RTMCSR CKS2 to

CKS0

Refresh in terv al

setting Refresh interval

setting Interrupt interval

setting

CMF Set to 1 when

RTCNT = RTCOR Set to 1 when

RTCNT = RTCOR

CMIE Cleared to 0 Cleared to 0 Enables or disables

interrupt reques ts

P8DDR P81DDR Set to 1 (CS3 output) Set to 1 (CS3 output) Set to 0 or 1

ABWCR ABW3 Cleared to 0 — —

Rev. 6.0, 09/02, page 169 of 876

DRAM Interface: To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR,

RTMCSR, and RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1.

Set bit P81DDR to 1 in the port 8 data direction register (P8DDR) to enable CS3 output. In

ABWCR, make area 3 a 16-bit-access area.

Pseudo-Static RAM Interface: To set up area 3 for connection to pseudo-static RAM, initialize

RTCOR, RTMCSR, and RFSHCR in that order, setting bit PSRAME to 1 and clearing bit

DRAME to 0. Set bit P81DDR to 1 in P8DDR to enable CS3 output.

Interval Timer: When PSRAME = 0 and DRAME = 0, the refresh controller operates as an

interval timer. After setting RTCOR, select an input clock in RTMCSR and set the CMIE bit to 1.

CMI interru pts will be requested at compare match intervals de ter mined by RTCOR and b its

CKS2 to CKS0 in RTMCSR.

When setting RTCOR, RTMCSR, and RFSHCR, make sure that PSRAME = 0 and DRAME = 0.

Writing is disab led when either of these b its is set to 1.

Rev. 6.0, 09/02, page 170 of 876

7.3.2 DRAM Refresh Control

Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is

determined by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. Figur e 7.2 illustrates

the refresh request interval.

RTCOR

H'00

RTCNT

Refresh request

Figure 7.2 Refresh Request Interval (RCYCE = 1)

Refresh requests are generated at regular intervals as shown in figure 7.2, but the refresh cycle is

not actually ex ecuted until th e refresh controller gets the b us right.

Table 7.4 summarizes the relationship among area 3 settings, DRAM read/write cycles, and

refresh cycles.

Table 7.4 Area 3 Settings, DRAM Access Cycles, and Refresh Cycles

Area 3 Settings Read/Write Cycle by CPU

or DMAC Refresh Cycle

2-state-a cce ss area

(AST3 = 0) • 3 states

• Wait states can not be inserted • 3 states

• Wait states can not be inserted

3-state-a cce ss area

(AST3 = 1) • 3 states

• Wait states can be ins erted • 3 states

• Wait states can be ins erted

To insert ref r e sh cycles, set the RCYCE bit to 1 in RFSHCR. Figure 7. 3 shows the state transition s

for execution of refresh cycles.

When the first refresh request occurs after exit from the reset state or standby mode, the refresh

controller does not execute a refresh cycle, but goes into the refresh request pend ing state. Note

this point wh en using a DRAM that requires a r efresh cycle for initialization.

Rev. 6.0, 09/02, page 171 of 876

When a refresh request occurs in the refr esh request pending state, the refresh controller acquires

the bus right, then executes a refresh cycle. If another refresh request occurs during execution of

the refresh cycle, it is ignored.

Refresh

request*

Refresh

request*

Exit from reset or standby mode

Refresh request pending state

Requesting bus right

Executing refresh cycle

Refresh request

Bus granted

End of refresh

cycle

Note: A refresh request is ignored if it occurs while the refresh controller is requesting the

bus right or executing a refresh cycle.

Figure 7.3 State Transitions for Refresh Cycle Execution

Rev. 6.0, 09/02, page 172 of 876

Address Multiplexing: Address multiplexing depends on the setting of the M9 /M8 b it in

RFSHCR, as described in table 7.5. Figure 7.4 shows the address output timing. Address output is

multiplexed only in area 3.

Table 7.5 Address M ult iplexing

Address Pins A23 to

A10 A9A8A7A6A5A4A3A2A1A0

Address signal s dur ing row

address output A23 to

A10

A9A8A7A6A5A4A3A2A1A0

M9/M8 = 0 A23 to

A10

A9A9A16 A15 A14 A13 A12 A11 A10 A0

Address signal s

during column

address output M9/M8 = 1 A23 to

A10

A18 A17 A16 A15 A14 A13 A12 A11 A10 A0

A to A , A

A to A

23 9 0

8 1

1 T

2 T

A to A

Row address

8 1 A to A

Column address

16 9

A to A , A

23 9 0

Address

bus

A to A , A

A to A

23 10 0

9 1

1 T

2 T

A to A

Row address

9 1 A to A

Column address

18 10

A to A , A

23 10 0

Address

bus

a. M9/ = 0

b. M9/ = 1

Figure 7.4 Multiplexed Address Output (Example without Wait States)

Rev. 6.0, 09/02, page 173 of 876

2CAS

CASCAS

CAS and 2WE

WEWE

WE Modes: The CAS/WE bit in RFSHCR can select two control modes for 16-bit-

wide DRAM: one using UCAS and LCAS; the other using UW and LW. These DRAM pins

correspond to H8/3048 Series pins as shown in table 7.6.

Table 7.6 DRAM Pins and H8/3048 Series Pins

DRAM Pin

H8/3048 Series Pin CAS/WE

WEWE

WE = 0 (2WE

WEWE

WE Mode) CAS/WE

WEWE

WE = 1 (2CAS

CASCAS

CAS Mode)

HWR UW UCAS

LWR LW LCAS

RD CAS WE

CS3RAS RAS

Figure 7.5 (1) shows the interface timing for 2WE DRAM. Figure 7.5 (2) shows the interface

timing for 2CAS DRAM.

( )

Read cycle Write cycle Refresh cycle*

Row Column Row Column Area 3 top address

Note: 16-bit access*

Address

bus

Figure 7.5(1) DRAM Control Signal Output Timing (2WE

WEWE

WE Mode)

Rev. 6.0, 09/02, page 174 of 876

( )

Read cycle Write cycle Refresh cycle*

Row Column Row Column Area 3 top address

Note: 16-bit access*

Address

bus

Figure 7.5(2) DRAM Control Signal Output Timing (2CAS

CASCAS

CAS Mode)

Refresh Cycle Priority Order: When there are simu ltaneous bus requests, the priority orde r is:

(High) External bus master > refresh controller > DMA controller > CPU (Low)

For details see section 6.3.7, Bus Arbiter Operation.

Wait State Insertion: When bit AST3 is set to 1 in ASTCR, bus controller settings can cause wait

states to be inserted into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.

Rev. 6.0, 09/02, page 175 of 876

Self-Refresh Mode: Some DRAM devices have a self-refresh function. After the SRFMD bit is

set to 1 in RFSHCR, wh en a transition to so f twar e standby mode occurs, the CAS and RAS

outputs go low in that order so that the DRAM self-refresh function can be used. On exit from

software standby mode, the CAS and RAS outputs both go high.

Table 7.7 shows the pin states in software standby mode. Figure 7.6 shows the signal outpu t

timing.

Table 7.7 Pin States in Software Standby Mode (1) (PSRAME = 0, DRAME = 1)

Software Standby Mode

SRFMD = 0 SRFMD = 1 (self-refresh mode)

Signal CAS/WE

WEWE

WE = 0 CAS/WE

WEWE

WE = 1 CAS/WE

WEWE

WE = 0 CAS/WE

WEWE

WE = 1

HWR High-impedance High-impedance High Low

LWR High-impedance High-impedance High Low

RD High-impedance High-impedance Low High

CS3High High Low Low

RFSH High High Low Low

Rev. 6.0, 09/02, page 176 of 876

( )

High

( )

Software

standby mode

High-impedance

Oscillator

settling time

a. 2 mode (SRFMD = 1)

b. 2 mode (SRFMD = 1)

Software

standby mode

High-impedance

Oscillator

settling time

Address

bus

Address

bus

( )

Figure 7.6 Signal Output Timing in Self -Refresh Mode (PSRAME = 0, DRA ME = 1)

Rev. 6.0, 09/02, page 177 of 876

Operation in Power-Down State: The refresh controller operates in sleep mode. It does not

operate in hard ware standby mode. In softwar e standby mode RTCNT is initialized, b ut RFSHCR,

RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby

mode.

Example 1: Co nnect ion to 2WE

WEWE

WE 1-Mbit DRAM (1-Mbyte Mode): Figure 7.7 shows typical

interconn ections to a 2WE 1-Mbit DRAM, and the corresponding address map. Figure 7.8 shows a

setup procedure to be followed by a program for this example. After power-up the DRAM must be

refreshed to initialize its internal state. Initialization tak e s a cer tain length of time, which can be

measured by using an interrupt from another timer module, or by counting the number of times

RTMCSR bit 7 (CMF) is set. Note that no r e fresh cycle is executed for the first refresh re quest

after exit from the reset state or standby mode (the first time the CMF flag is set; see figure 7.3).

When using this example, ch eck the DRAM device characteristics carefully and use a procedure

that fits them.

H8/3048 Series A

D to D

015

I/O to I/O

15 0

H'60000

H'7FFFF

a. Interconnections (example)

DRAM area Area 3 (1-Mbyte mode)

b. Address map

2 1-Mbit DRAM with

16-bit organization

Figure 7.7 Interconnections and Address Map for 2WE

WEWE

WE 1-Mbit DRAM (Example)

Rev. 6.0, 09/02, page 178 of 876

Set area 3 for 16-bit access

Set P8 DDR to 1 for output

Set RTCOR

Set bits CKS2 to CKS0 in RTMCSR

Write H'23 in RFSHCR

Wait for DRAM to be initialized

DRAM can be accessed

Figure 7.8 Setup Procedure for 2WE

WEWE

WE 1-Mbit DRAM (1-Mbyte Mode)

Rev. 6.0, 09/02, page 179 of 876

Example 2: Co nnect ion to 2WE

WEWE

WE 4-Mbit DRAM (16-Mbyte Mode): Figure 7.9 shows typical

interconn ections to a single 2WE 4-Mbit DRAM, and the corresponding address map. Figure 7.10

shows a setup procedure to be followed by a program for this example.

The DRAM in this example has 10-bit row addresses and 8-bit column addresses. Its address area

is H'600000 to H'67FFFF.

D to D

015

I/O to I/O

15 0

H'600000

H'67FFFF

H'680000

H'7FFFFF

H8/3048 Series

2 4-Mbit DRAM with 10-bit

row address, 8-bit column address,

and 16-bit organization

a. Interconnections (example)

b. Address map

DRAM area

Not used Area 3 (16-Mbyte mode)

Figure 7.9 Interconnections and Address Map for 2WE

WEWE

WE 4-Mbit DRAM (Example)

Rev. 6.0, 09/02, page 180 of 876

Set area 3 for 16-bit access

Set P8 DDR to 1 for output

Set RTCOR

Set bits CKS2 to CKS0 in RTMCSR

Write H'23 in RFSHCR

Wait for DRAM to be initialized

DRAM can be accessed

Figure 7.10 Setup Procedure for 2WE

WEWE

WE 4-Mbit DRAM with 10-Bit Row Address and 8-Bit

Column Address (16-Mbyte Mode)

Rev. 6.0, 09/02, page 181 of 876

Example 3: Co nnect ion to 2CAS

CASCAS

CAS 4-Mbit DRAM ( 16-Mbyte Mode): Figure 7.11 shows typical

interconn ections to a single 2CAS 4-Mbit DRAM, and the corresponding address map.

Figure 7.12 shows a setup procedure to be followed by a program for this example.

The DRAM in this example has 9-bit row addresses and 9-bit column addresses. Its address area is

H'600000 to H'67FFFF.

D to D

I/O to I/O

15 015

H'600000

H'67FFFF

H'680000

H'7FFFFF

H8/3048 Series

2 4-Mbit DRAM with 9-bit

row address, 9-bit column address,

and 16-bit organization×

a. Interconnections (example)

b. Address map

DRAM area

Not used Area 3 (16-Mbyte mode)

Figure 7.11 Interconnections and Address Map for 2CAS

CASCAS

CAS 4-Mbit DRAM (Example)

Rev. 6.0, 09/02, page 182 of 876

Set area 3 for 16-bit access

Set P8 DDR to 1 for output

Set RTCOR

Set bits CKS2 to CKS0 in RTMCSR

Write H'3B in RFSHCR

Wait for DRAM to be initialized

DRAM can be accessed

Figure 7.12 Setup Procedure for 2CAS

CASCAS

CAS 4-Mbit DRAM with 9- Bit Row Address and 9-Bit

Column Address (16-Mbyte Mode)

Rev. 6.0, 09/02, page 183 of 876

Example 4: Connection to Multiple 4-Mbit DRAM Chips (16 -Mbyte Mode): Figure 7.13

shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding

address map. Up to four DRAM chips can be connected to area 3 by decoding upper address bits

A19 and A20.

Figure 7.14 shows a setup procedure to be followed by a program for this example. The DRAM in

this example has 9-bit row addresses and 9-bit column addresses. Both chips must be refreshed

simultaneo usly, so the RFSH pin must be used.

H'600000

H'67FFFF

H'680000

H'6FFFFF

H'700000

H'7FFFFF

A to A

I/O to I/O

15 0

No. 1

A to A

I/O to I/O

15 0

No. 2

A to A

9 1

D to D

15 0

H8/3048 Series

2 4-Mbit DRAM with 9-bit

row address, 9-bit column

address, and 16-bit organization

a. Interconnections (example)

b. Address map

No. 1

DRAM area

No. 2

DRAM area

Not used

Area 3 (16-Mbyte mode)

Figure 7.13 Interconnections and Address Map for Multiple 2CAS

CASCAS

CAS 4- Mbit DRAM Chips

(Example)

Rev. 6.0, 09/02, page 184 of 876

Set area 3 for 16-bit access

Set P8 DDR to 1 for output

Set RTCOR

Set bits CKS2 to CKS0 in RTMCSR

Write H'3F in RFSHCR

Wait for DRAM to be initialized

DRAM can be accessed

Figure 7.14 Setup Procedure for Multiple 2CAS

CASCAS

CAS 4- Mbit DRAM Chips with 9-Bit Row

Address and 9-Bit Column Address (16-Mbyte Mode)

Rev. 6.0, 09/02, page 185 of 876

7.3.3 Pseudo-Static RAM Refresh Control

Refresh Request Interval and Refresh Cycle Execution: The refresh request interv al is

determined as in a DRAM interface, by the settings of RTCOR and b its CKS2 to CKS0 in

RTMCSR. The numbers of states required for pseudo-static RAM read/write cycles and refresh

cycles are the same as for DRAM (see table 7.4). The state transitions are as shown in figure 7.3.

Pseudo-Stat ic RAM Control Signals: Figure 7.15 shows the control signals for pseudo-static

RAM read, write, and refresh cycles.

Read cycle Write cycle *Refresh cycle

Area 3 top address

Note: 16-bit access*

Address

bus

Figure 7.15 Pseudo-Static RAM Control Signal Output Timing

Rev. 6.0, 09/02, page 186 of 876

Refresh Cycle Priority Order: When there are simu ltaneous bus requests, the priority orde r is:

(High) External bus master > refresh controller > DMA controller > CPU (Low)

For details see section 6.3.7, Bus Arbiter Operation.

Wait State Insertion: When bit AST3 is set to 1 in ASTCR, the wait state controller ( WSC) can

insert wait states into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.

Self-Refresh Mode: Some pseudo-static RAM devices have a self-refresh function. After the

SRFMD bit is set to 1 in RFSHCR, when a transition to software standby mode occurs, the

H8/3048 Series’ CS3 output goes high and its RFSH output goes low so that the pseudo-static

RAM self-refresh function can be used. On exit from software standby mode, the RFSH output

goes high.

Table 7.8 shows the pin states in software standby mode. Figure 7.16 shows the signal output

timing.

Table 7.8 Pin States in Software Standby Mode (2) (PSRAME = 1, DRAME = 0)

Software Standby Mode

Signal SRFMD = 0 SRFMD = 1 (Self-Refresh Mode)

CS3High High

RD High-impedance High-impedance

HWR High-impedance High-impedance

LWR High-impedance High-impedance

RFSH High Low

Rev. 6.0, 09/02, page 187 of 876

3High

Software standby mode Oscillator

settling time

High-impedance

Address

bus

Figure 7.1 6 Signal Output Timing in Self-Refresh Mode (PSRAME = 1, DRAME = 0)

Operation in Power-Down State: The refresh controller operates in sleep mode. It does not

operate in hard ware standby mode. In softwar e standby mode RTCNT is initialized, b ut RFSHCR,

RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby

mode.

Example: Pseudo-static RAM may have separate OE and RFSH pins, or these may be combined

into a single OE/RFSH pin. Figure 7.17 shows an example of a circuit for generating an OE/RFSH

signal. Check the device characteristics carefully, and design a circuit that fits them. Figure 7.18

shows a setup procedure to be followed by a program.

H8/3048 Series PSRAM

Figure 7.17 Interconnection to Pseudo-Static RAM with OE

OEOE

OE/RFSH

RFSHRFSH

RFSH Signal (Example)

Rev. 6.0, 09/02, page 188 of 876

Set P8 DDR to 1 for output

Set RTCOR

Set bits CKS2 to CKS0 in RTMCSR

Write H'47 in RFSHCR

Wait for PSRAM to be initialized

PSRAM can be accessed

Figure 7.18 Setup Procedure for Pseudo-Static RAM

Rev. 6.0, 09/02, page 189 of 876

7.3.4 Interval Timer

To use the refresh controller as an interval timer, clear the PSRAME and DRAME both to 0. After

setting RTCOR, select a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit

to 1.

Timing of Setting of Compa re Match Flag a nd Clearing by Compare Match: The CMF flag

in RTCSR is set to 1 by a co mpare match signal output when the RTCOR and RTCNT values

match. The compare match signal is gener ated in the last state in which the values match (when

RTCNT is updated from the matching value to a new value). Accordingly, when RTCNT and

RTCOR match , the compare match signal is not generated un til the next counter clock pulse.

Figure 7.19 shows the timing.

RTCNT

RTCOR

CMF flag

N H'00

Compare

match signal

Figure 7.19 Timing of Setting of CMF Flag

Operation in Power-Down State: The interval timer function operates in sleep mode. It does not

operate in hardware standby mode. In so ftware standby mode RTCNT and RTMCSR bits 7 and 6

are initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settin gs prior to the transitio n to

software standby mode.

Rev. 6.0, 09/02, page 190 of 876

Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the

T3 state of an RTCNT write cycle, clearing of the counter takes priority and the write is not

performed. See figu re 7.20.

Address bus

RTCNT

RTCNT address

N H'00

RTCNT write cycle by CPU

Internal

write signal

Counter

clear signal

Figure 7.20 Contention between RTCNT Write and Clear

Rev. 6.0, 09/02, page 191 of 876

Contention between RTCNT Write and Increment: If an increment pulse occurs in the T3 state

of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 7.21.

1 T

2 T

RTCNT address

Address bus

RTCNT

RTCNT write cycle by CPU

Internal

write signal

RTCNT

input clock

Counter write data

Figure 7.21 Contention between RTCNT Write and Increment

Rev. 6.0, 09/02, page 192 of 876

Contention between RTCOR Write and Compare Match: If a compare match occurs in the T3

state of an RTCOR write cy cle, wr iting takes priority and the compare match sign a l is inhibited.

See figure 7.22.

1 T

2 T

RTCNT address

N N + 1

Address bus

RTCNT

RTCOR

RTCOR write cycle by CPU

Internal

write signal

Compare

match signal

Inhibited

RTCOR write data

Figure 7.22 Contention between RTCOR Write and Compare Match

RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources may

cause RTCNT to increment, depending on the switchover timing. Table 7.9 shows the relation

between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation of

RTCNT.

The RTCNT input clock is generated from the internal clock source by detecting the falling edge

of the internal clock. If a switchover is made from a high clock source to a low clock source, as in

case No. 3 in table 7.9, the switchover will be regarded as a falling edge, an RTCNT clock pulse

will be genera ted , and RTCNT will be incremented.

Rev. 6.0, 09/02, page 193 of 876

Table 7.9 Internal Clock Switchover and RTCNT Operation

No. CKS2 to CKS0

Write Timing RTCNT Operation

1 Low → low switchover*1

Old clock

source

New clock

source

RTCNT N N + 1

CKS bits rewritten

RTCNT

clock

2 Low → high switchover*2

Old clock

source

New clock

source

RTCNT N N + 1

CKS bits rewritten

N + 2

RTCNT

clock

Rev. 6.0, 09/02, page 194 of 876

No. CKS2 to CKS0

Write Timing RTCNT Operation

3 High → low switchover*3

Old clock

source

New clock

source

RTCNT

clock

RTCNT N N + 1

CKS bits rewritten

N + 2

4 High → high switchover*4

Old clock

source

New clock

source

RTCNT

clock

RTCNT N N + 1

CKS bits rewritten

N + 2

Notes: *1 Including switchovers from a low clock source to the halted state, and from the halted

state to a low clock source.

*2 Including switchover from the halted state to a high clock source.

*3 Including switchover from a high clock source to the halted state.

*4 The switchover is regarded as a falling edge, causing RTCNT to increment.

Rev. 6.0, 09/02, page 195 of 876

7.4 Interrupt Source

Compare match interrupts (CMI) can be generated when the refresh controller is used as an

interval timer . Compare match interrupt requests are masked/unmasked with th e CMIE bit of

RTMCSR.

7.5 Usage Notes

When using the DRAM or pseudo-static RAM refresh function, note the following points:

• With the refresh controller, if directly connected DRAM or PSRAM is disconnected *, the

P80/RFSH/IRQ0 pin and the P81/CS3/IRQ1 pin may both become low-level outputs

simultaneously.

Note: * When the DRAM enable bit (DRAME) or PSRAM enable bit (PSRAME) in the refresh

control register ( RFSHC R) is clear ed to 0 after being set to 1.

Address bus Area 3 start address

/ /

Figure 7.23 Operation when DRAM/PSRAM Connection is Switched

• Refresh cycles are not executed while the bus is released, during software standby mode, and

when a bus cycle is greatly prolonged by insertion of wait states. When these conditions occur,

other means of refreshing are required.

• If refresh requests occur while the bus is released, the first request is held and one refresh cycle

is executed after the bus-released state ends. Figure 7.24 shows the bus cycles in this case.

Rev. 6.0, 09/02, page 196 of 876

Refresh

request

Bus-released state Refresh cycle CPU cycle Refresh cycle

Figure 7.24 Refresh Cycles when Bus is Released

• If a bus cycle is prolonged by insertion of wait states, the first refresh request is held, as in the

bus-released state.

• If there is contention with a bus request from an external bus master wh en making a transition

to software standby mode, a one-state bus-released state may occur immediately before the

transition to software standby mode (see figure 7.25).

When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the

SLEEP instruction.

When making a transition to self-refresh mode, the strobe waveform output may not be

guaranteed due to the same kind of contention. This, too, can be prevented by clearing the

BRLE bit to 0 in BRCR.

Address bus

External bus

released state Software standby mode

Strobe

Figure 7.25 Contention between Bus-Released State and Software Standby Mode

Rev. 6.0, 09/02, page 197 of 876

Section 8 DMA Controller

8.1 Overview

The H8/3048 Series has an on-chip DMA controller (DMAC) that can transfer data on up to four

channels.

When the DMA controller is not used, it can be independently halted to conserve power. For

details see section 21.6, Module Standby Function.

8.1.1 Features

DMAC features are listed below.

• Selection of short address mode or full address mode

Short address mode

 8-bit source address and 24-bit destination address, or vice versa

 Maximum four ch annels available

 Selection of I/O mode, idle mode, or repeat mode

Full address mode

 24-bit source and destination addresses

 Maximum two channels available

 Selection of normal mode or block transfer mode

• Directly addressable 16-Mbyte address space

• Selection of byte or word transfer

• Activation by internal interrupts, external reque sts, or auto-request (depending on transfer

mode)

 16-bit in tegrated timer unit (ITU) compare match/input capture interrupts (four)

 Serial communication interface (SCI channel 0) transmit-data-empty /receive-data-full

interrupts

 External requests

 Auto-request

Rev. 6.0, 09/02, page 198 of 876

8.1.2 Block Diagram

Figure 8.1 shows a DMAC block diagram.

IMIA0

IMIA1

IMIA2

IMIA3

TXI0

RXI0

DEND0A

DEND0B

DEND1A

DEND1B

DTCR0A

DTCR0B

DTCR1A

DTCR1B

Control logic

Data buffer

Address buffer

Arithmetic-logic unit

MAR0A

MAR0B

MAR1A

MAR1B

IOAR0A

IOAR0B

IOAR1A

IOAR1B

ETCR0A

ETCR0B

ETCR1A

ETCR1B

Internal address bus

Internal

interrupts

Interrupt

signals

Internal data bus

Module data bus

Legend

DTCR:

MAR:

IOAR:

ETCR:

Data transfer control register

Memory address register

I/O address register

Execute transfer count register

Channel

Figure 8.1 Block Diagram of DMAC

Rev. 6.0, 09/02, page 199 of 876

8.1.3 Functional Overview

Table 8.1 gives an overview of the DMAC functions.

Table 8.1 DMAC Functional Overview

Address

Reg. Length

Transfer Mode Activation Source Destination

• Compare match/

input capture A

interrupts from ITU

channels 0 to 3

• Transmit-data-empty

interrupt from SCI

channel 0

24 8

• Receive-data-full

interrupt from SCI

channel 0

824

Short

address

mode

I/O mode

• Transfers one byt e or one word

per request

• Increments or decrements the

memory address by 1 or 2

• Executes 1 to 65,536 transfers

Idle mode

• Transfers one byt e or one word

per request

• Holds the memory address fixed

• Executes 1 to 65,536 transfers

Repeat mode

• Transfers one byt e or one word per

request

• Increments or decrements the

memory address by 1 or 2

• Executes a specified number (1 to

255) of transfers, then returns to

the initial state and continues

• External request 24 8

Rev. 6.0, 09/02, page 200 of 876

Address

Reg. Length

Transfer Mode Activation Source Destination

Full

address

mode

Normal mode

• Auto-request

 Retains the transfer request

internally

 Executes a specif ied num ber

(1 to 65,536) of transfers

continuously

 Selection of burst mode or

cycle-steal mode

• External request

 Transfers one byt e or one

word per request

 Executes 1 to 65,536 transfers

• Auto-request

• External request

24 24

Block transfer

• Transfers one block of a specified

size per request

• Executes 1 to 65,536 transfers

• Allows either the source or

destination to be a fixed block

area

• Block size can be 1 to 255 bytes

or words

• Compare match/

input capture A

interrupts from ITU

channels 0 to 3

• External request

24 24

Rev. 6.0, 09/02, page 201 of 876

8.1.4 Input/Output Pins

Table 8.2 lists the DMAC pins.

Table 8.2 DMAC Pin s

Channel Name Abbre-

viation Input/

Output Function

0 DMA request 0 DREQ0Input External request for DMAC channel 0

Transfer end 0 TEND0Output Transfer end on DMAC channel 0

1 DMA request 1 DREQ1Input External request for DMAC channel 1

Transfer end 1 TEND1Output Transfer end on DMAC channel 1

Note: External requests cannot be made to channel A in short address mode.

8.1.5 Register Configuration

Table 8.3 lists the DMAC registers.

Rev. 6.0, 09/02, page 202 of 876

Table 8.3 DMAC Registers

Channel Address*Name Abbrev iat ion R/W Initia l Va lue

0 H'FF20 Memory address register 0AR MAR0AR R/W Undetermined

H'FF21 Mem ory address register 0AE MAR0AE R/W Undeterm i ned

H'FF22 Mem ory address register 0AH MAR0AH R/W Undetermined

H'FF23 Mem ory address register 0AL MAR0AL R/W Undeterm i ned

H'FF26 I/O address register 0A IOA R0A R/W Undetermi ned

H'FF24 Execute transfer count register 0AH ETCR0AH R/W Undeterm i ned

H'FF25 Execute transfer count register 0AL ETCR0AL R/ W Undetermined

H'FF27 Data transfer control register 0A DTCR0A R/W H'00

H'FF28 Mem ory address register 0BR MAR0BR R/W Undetermined

H'FF29 Mem ory address register 0BE MAR0BE R/W Undeterm i ned

H'FF2A Memory address regist er 0BH MAR0BH R/W Undetermined

H'FF2B Memory address regist er 0BL MA R0B L R/W Undet erm i ned

H'FF2E I/O address regist er 0B I OAR0B R/ W Undetermined

H'FF2C Execute transfer count register 0BH ETCR0BH R/W Undetermined

H'FF2D Execute transfer count register 0BL ETCR0BL R/W Undetermined

H'FF2F Data transfer control regis ter 0B DTCR0B R/W H'00

1 H'FF30 Memory address register 1AR MAR1AR R/W Undetermined

H'FF31 Mem ory address register 1AE MAR1AE R/W Undeterm i ned

H'FF32 Mem ory address register 1AH MAR1AH R/W Undetermined

H'FF33 Mem ory address register 1AL MAR1AL R/W Undeterm i ned

H'FF36 I/O address register 1A IOA R1A R/W Undetermi ned

H'FF34 Execute transfer count register 1AH ETCR1AH R/W Undeterm i ned

H'FF35 Execute transfer count register 1AL ETCR1AL R/ W Undetermined

H'FF37 Data transfer control register 1A DTCR1A R/W H'00

H'FF38 Mem ory address register 1BR MAR1BR R/W Undetermined

H'FF39 Mem ory address register 1BE MAR1BE R/W Undeterm i ned

H'FF3A Memory address regist er 1BH MAR1BH R/W Undetermined

H'FF3B Memory address regist er 1BL MA R1B L R/W Undet erm i ned

H'FF3E I/O address regist er 1B I OAR1B R/ W Undetermined

H'FF3C Execute transfer count register 1BH ETCR1BH R/W Undetermined

H'FF3D Execute transfer count register 1BL ETCR1BL R/W Undetermined

H'FF3F Data transfer control regis ter 1B DTCR1B R/W H'00

Note: * The lower 16 bits of the address are indicated.

Rev. 6.0, 09/02, page 203 of 876

8.2 Register Descriptions (Short Address Mode)

In short address mode, transfers can be carried out independently on channels A and B. Short

address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA)

as indicated in table 8.4.

Table 8.4 Selection of Short and Full Address Mo des

Channel Bit 2:

DTS2A Bit 1:

DTS1A Description

0 1 1 DMAC channel 0 operates as one channel in full address

mode

Other than above DMAC channels 0A and 0B operate as two independent

channels in short address mode

1 1 1 DMAC channel 1 operates as one channel in full address

mode

Other than above DMAC channels 1A and 1B operate as two independent

channels in short address mode

8.2.1 Memory Address Registers (MAR)

A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or

destination address. The transfer d ir ection is d e ter mined automatically from the activation source.

An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits

of MARR are reserved: they cannot be modified and are always read as 1.

Bit

Initial value

Read/Write

—

Source or destination address

—

R/W

MARR MARE MARH MARL

Undetermined

An MAR functions as a source or destination address register depending on how the DMAC is

activated: as a destination address register if activation is by a receive-data-full interrupt from the

serial communication interface (SCI) (channel 0), and as a source address register otherwise.

Rev. 6.0, 09/02, page 204 of 876

The MAR value is incremented or decremented each time one byte or word is transferred,

automatically updating the source or destin ation memory address. Fo r details, see section 8.2.4,

Data Transfer Control Registers (DTCR).

The MARs are not initialized by a reset or in standby mode .

8.2.2 I/O Address Registers (IOAR)

An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or

destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits

are all 1 (H'FFFF).

Bit

Initial value

Read/Write

R/W

Source or destination address

Undetermined

An IOAR functions as a source or destination address register depending on how the DMAC is

activated: as a source address register if activation is by a receive-data-full interrupt from the SCI

(channel 0), and as a destination address register otherwise.

The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed.

The IOARs are not initialized by a reset or in stan dby mode.

Rev. 6.0, 09/02, page 205 of 876

8.2.3 Execute Transfer Count Registers (ETCR)

An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the

number of transfers to be executed. These registers function in one way in I/O mode and idle

mode, and another way in repeat mode.

• I/O mode and idle mode

Bit

Initial value

Read/Write

R/W

Transfer counter

Undetermined

R/W

In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by

1 each time one transfer is executed. The transfer ends when the count reaches H'0000.

• Repeat mode

Bit

Initial value

Read/Write

R/W

Undetermined

Transfer counter

ETCRH

Bit

Initial value

Read/Write

R/W

Undetermined

Initial count

ETCRL

In repeat mode, ETCRH fun ctions as an 8-bit transfer counter and ETCRL holds the initial

transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH

reaches H'00, the value in ETCRL is reloaded into ETCRH and the same op eration is repeated.

The ETCRs are not initialized by a reset or in standby m ode.

Rev. 6.0, 09/02, page 206 of 876

8.2.4 Data Transfer Control Registers (DTCR)

A data transfer contr ol register (DTCR) is an 8-b it r eadable/writable register that con trols th e

operation of one DMAC channel.

Bit

Initial value

Read/Write

DTE

R/W

DTSZ

R/W

DTID

R/W

RPE

R/W

DTIE

R/W

DTS0

R/W

DTS2

R/W

DTS1

R/W

Data transfer enable

Enables or disables

data transfer

Data transfer interrupt enable

Enables or disables the CPU interrupt

at the end of the transfer

Data transfer select

These bits select the data

transfer activation source

Data transfer size

Selects byte or

word size

Data transfer

increment/decrement

Selects whether to

increment or decrement

the memory address

Repeat enable

Selects repeat

mode

The DTCRs are initialized to H'00 by a reset and in standby mode.

Bit 7—Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the

DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transf er when

activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and does not

accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, th en writing 1.

Bit 7: DTE Description

0 Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0 when

the specified number of transfers have been co mpleted. (Initial value)

1 Data transfer is enabled

If DTIE is set to 1, a CPU interrupt is requested wh en DTE is cleared to 0.

Rev. 6.0, 09/02, page 207 of 876

Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.

Bit 6: DTSZ Description

0 Byte-size transfer (Initial value)

1 Word-size transfer

Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or

decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode.

Bit 5: DTID Description

0 MAR is incremented after each data transfer

• If DTSZ = 0, MAR is incremented by 1 after each transfer

• If DTSZ = 1, MAR is incremented by 2 after each transfer

1 MAR is decremented after each data transfer

• If DTSZ = 0, MAR is decremented by 1 after each transfer

• If DTSZ = 1, MAR is decremented by 2 after each transfer

MAR is not incremented or decremented in idle mode .

Bit 4—Repeat Enable (RPE): Selects wheth er to transfer data in I/O mode, id le mod e, or r epeat

mode.

Bit 4: RPE Bit 3: DTIE Description

0 0 I/O mode (Initial value)

1 0 Repeat mode

1 Idle mode

Operations in these modes are described in sections 8.4.2, I/O Mode, 8.4.3, Idle Mode, and 8.4.4,

Repeat Mode.

Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)

requested when the DTE bit is cleared to 0.

Bit 3: DTIE Description

0 The DEND interrupt requested by DTE is disabled (Initial value)

1 The DEND interrupt requested by DTE is enabled

Rev. 6.0, 09/02, page 208 of 876

Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer

activation source. Some of the selectable sources differ between channels A and B.*

Note: * Refer to section 8.3.4, Data Transfer Control Registers (DTCR).

Bit 2: DTS2 Bit 1: DTS1 Bit 0: DTS0 Description

0 0 0 Compare match/input capture A interrupt from ITU

channel 0 ( Initi al val ue)

1 Compare match/input capture A interrupt from ITU

channel 1

1 0 Compare match/input capture A interrupt from ITU

channel 2

1 Compare match/input capture A interrupt from ITU

channel 3

1 0 0 Transmit-data-empty interrupt from SCI channel 0

1 Receive-data-full interrupt from SCI channel 0

1 0 Falling edge of DREQ input (channel B)

Transfer in full address mode (channel A)

1 Low level of DREQ input (channel B)

Transfer in full address mode (channel A)

The same internal interrupt can be selected as an activation source for two or more channels at

once. In that case the channels are activated in a priority order, highest-priority channel first. For

the prior ity order, see section 8.4.9, DMAC Mu ltiple-Channel Operation .

When a channel is enabled (DTE = 1), its selected DMAC activation source cannot generate a

CPU interrupt.

Rev. 6.0, 09/02, page 209 of 876

8.3 Register Descriptions (Full Address Mode)

In full address mode the A and B channels operate together. Full address mode is selected as

indicated in table 8.4.

8.3.1 Memory Address Registers (MAR)

A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the

source address register of the transfer, and MARB as the destination address register.

An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits

of MARR are reserved: they cannot be modified and are always read as 1.

Bit

Initial value

Read/Write

—

Source or destination address

—

R/W

Undetermined

R/W

MARR MARE MARH MARL

The MAR value is incremented or decremented each time one byte or word is transferred,

automatically updating the source or destin ation memory address. Fo r details, see section 8.3.4,

Data Transfer Control Registers (DTCR).

The MARs are not initialized by a reset or in standby mode .

8.3.2 I/O Address Registers (IOAR)

The I/O address registers (IOARs) are not used in full address mode.

Rev. 6.0, 09/02, page 210 of 876

8.3.3 Execute Transfer Count Registers (ETCR)

An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the

number of tran sfers to be executed. The functions of these registers differ between normal mode

and block transfer mode.

• Normal mode

ETCRA

Bit

Initial value

Read/Write

R/W

Transfer counter

Undetermined

R/W

ETCRB: Is not used in normal mode.

In normal mode ETCRA functions as a 16-bit transfer counter. The count is decremented by 1

each time one transfer is executed. The transfer ends when the count reaches H'0000. ETCRB

is not used.

Rev. 6.0, 09/02, page 211 of 876

• Block transfer mode

ETCRA

Bit

Initial value

Read/Write

R/W

Undetermined

Block size counter

ETCRAH

Bit

Initial value

Read/Write

R/W

Undetermined

Initial block size

ETCRAL

ETCRB

Bit

Initial value

Read/Write

R/W

Block transfer counter

Undetermined

R/W

In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the

initial block size. ETCRAH is d ecremented by 1 each time o ne byte or word is transferred.

When the count reaches H'00, ETCRAH is reloaded from ETCRAL. Blocks consisting of an

arbitrary num ber of bytes or words can be transf erred r epeatedly by setting the same initial

block size value in ETCRAH and ETCRAL.

In b l ock transfer mode ETCRB func tions as a 1 6-bit bl ock transfer counte r. ETCRB is

decremented by 1 each time one block is transferred. The transfer ends when the count reaches

H'0000.

The ETCRs are not initialized by a reset or in standby m ode.

Rev. 6.0, 09/02, page 212 of 876

8.3.4 Data Transfer Control Registers (DTCR)

The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the

operation of the DMAC channels. A channel operates in fu ll address mode when bits DTS2A and

DTS1A a re both set to 1 in DTCRA. DTCRA and DTCRB have di fferent functions in full ad dress

mode.

DTCRA

Bit

Initial value

Read/Write

DTE

R/W

DTSZ

R/W

SAID

R/W

SAIDE

R/W

DTIE

R/W

DTS0A

R/W

DTS2A

R/W

DTS1A

R/W

Data transfer enable

Enables or disables

data transfer

Enables or disables the

CPU interrupt at the end

of the transfer

Data transfer size

Selects byte or

word size

Source address

increment/decrement Data transfer select

2A and 1A

These bits must both be

set to 1

Data transfer

interrupt enable

Source address increment/

decrement enable

These bits select whether

the source address register

(MARA) is incremented,

decremented, or held fixed

during the data transfer

Selects block

transfer mode

Data transfer

select 0A

DTCRA is initialized to H'00 by a reset and in standby mode.

Rev. 6.0, 09/02, page 213 of 876

Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, th is bit enables

or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the

channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the

channel waits for transfers to be requested. Wh en the specified number of transfers have been

completed, th e DTE bit is au tomatically cleared to 0. When DTE is 0, the channel is disabled and

does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then

writing 1.

Bit 7: DTE Description

0 Data transfer is disabled (DTE is cleared to 0 when the specified number of

transfers have been com pl eted) (Initial value)

1 Data transfer is enabled

If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.

Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.

Bit 6: DTSZ Description

0 Byte-size transfer (Initial value)

1 Word-size transfer

Bit 5—Source Address Increment/Decrement (SAID) and

Bit 4—Source Address Increment/Decrement Enable (SAIDE): These bits selec t wh ether the

source address register (MARA) is incremented, decremented, or held fixed during th e data

transfer.

Bit 5: SAID Bit 4: SAIDE Description

0 0 MARA is held fixed (Initial value)

1 MARA is incremented after each data transfer

• If DTSZ = 0, MARA is incremented by 1 after each

transfer

• If DTSZ = 1, MARA is incremented by 2 after each

transfer

1 0 MARA is held fixed

1 MARA is decremented after each data transfer

• If DTSZ = 0, MARA is decremented by 1 after each

transfer

• If DTSZ = 1, MARA is decremented by 2 after each

transfer

Rev. 6.0, 09/02, page 214 of 876

Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)

requested when the DTE bit is cleared to 0.

Bit 3: DTIE Description

0 The DEND interrupt requested by DTE is disabled (Initial value)

1 The DEND interrupt requested by DTE is enabled

Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full

address mod e when DTS2A and DTS1A are both set to 1.

Bit 0—Data Transfer Select 0A (DTS0A): Selects normal mode or block transfer mode.

Bit 0: DTS0A Description

0 Normal mode (Initial value)

1 Block transfer mode

Operations in these modes are described in sections 8.4.5, Normal Mode, and 8.4.6, Block

Transfer Mode.

Rev. 6.0, 09/02, page 215 of 876

DTCRB

Bit

Initial value

Read/Write

DTME

R/W

—

R/W

DAID

R/W

DAIDE

R/W

TMS

R/W

DTS0B

R/W

DTS2B

R/W

DTS1B

R/W

Data transfer master enable

Enables or disables data

transfer, together with

the DTE bit, and is cleared

to 0 by an interrupt

Reserved bit

Destination address

increment/decrement Data transfer select

2B to 0B

These bits select the data

transfer activation source

Transfer mode select

Destination address

increment/decrement enable

These bits select whether

the destination address

decremented, or held fixed

during the data transfer

Selects whether the

block area is the source

or destination in block

transfer mode

DTCRB is initialized to H'00 by a reset and in standby mode.

Bit 7—Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit

enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is

enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the tran sfer so that the

CPU can use the bus. The su spended transfer resumes when DTME is set to 1 again. For further

information on operation in block transfer mode, see section 8.6.6, NMI Interrupts and Block

Transfer Mode.

DTME is set to 1 by reading the register while DTME = 0, then writing 1.

Bit 7: DTME Description

0 Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt occurs)

(Initial value)

1 Data transfer is enabled

Rev. 6.0, 09/02, page 216 of 876

Bit 6—Reserved: Although reserved, this bit can be written and read.

Bit 5—Destination Address Increment/Decrement (DAID) and

Bit 4—Destination Address Increment/Decrement Enable (DAIDE): These bits select whether

the destination address register (MARB) is incremented, decremented, or held fixed during the

data transfer .

Bit 5: DAID Bit 4: DAIDE Description

0 0 MARB is held fixed (Initial value)

1 MARB is incremented after each data transfer

• If DTSZ = 0, MARB is incremented by 1 after each

data transfer

• If DTSZ = 1, MARB is incremented by 2 after each

data transfer

1 0 MARB is held fixed

1 MARB is decremented after each data transfer

• If DTSZ = 0, MARB is decremented by 1 after each

data transfer

• If DTSZ = 1, MARB is decremented by 2 after each

data transfer

Bit 3—Transfer Mode Select (TMS): Selects whether the source or destination is the block area

in block tran sfer mode.

Bit 3: TMS Description

0 Destination is the block area in block transfer mode (Initial value)

1 Source is the block area in block transfer mode

Rev. 6.0, 09/02, page 217 of 876

Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the

data transfer activation source. Th e selectable activation sources differ between normal mode and

block transfer mode.

• Normal mode

Bit 2:

DTS2B Bit 1:

DTS1B Bit 0:

DTS0B Description

000Auto-request (burst mode)(Initial value)

1 Cannot be used

1 0 Auto-request (cycle-steal mode)

1 Cannot be used

100Cannot be used

1 Cannot be used

1 0 Falling edge of DREQ

1 Low level input at DREQ

• Block transfer mode

Bit 2:

DTS2B Bit 1:

DTS1B Bit 0:

DTS0B Description

000Compare match/input capture A interrupt from ITU

channel 0 (Initi al val ue)

1 Compare match/input capture A interrupt from ITU

channel 1

1 0 Compare match/input capture A interrupt from ITU

channel 2

1 Compare match/input capture A interrupt from ITU

channel 3

100Cannot be used

1 Cannot be used

1 0 Falling edge of DREQ

1 Cannot be used

The same internal interrupt can be selected to activate two or more channels. The channels are

activated in a priority order, highest priority first. For the priority order, see section 8.4.9, DMAC

Multiple-Channel Operation.

Rev. 6.0, 09/02, page 218 of 876

8.4 Operation

8.4.1 Overview

Table 8.5 summarizes the DMAC modes.

Table 8.5 DMAC Modes

Transfer Mode Activation Notes

Compare match/input

capture A interrupt from

ITU channels 0 to 3

Transmit-data-empty and

receive-data-full interrupts

from SCI channel 0

Short address

mode I/O mode

Idle mode

Repeat mode

External request

• Up to four channels can

operate independently

• Only the B channels

support external requests

Auto-requestNormal mode External request

Compare match/input

capture A interrupt from ITU

channels 0 to 3

Full address

mode

Block transfer

mode

External request

• A and B channels are

paired; up to two channels

are available

• Burst mode or cycle-steal

mode can be selected for

auto-requests

A summary of operations in th ese modes follows.

I/O Mode: One byte or word is transferred per requ est. A designated number of these tran sfers are

executed. A CPU interrupt can be requested at completion of the designated number of transfers.

One 24-bit address and one 8-bit address are specified. Th e transfer direction is determined

automatically f rom the activation source.

Idle Mode: One byte or word is transferred per request. A designated number of these transfers

are executed. A CPU interrupt can be requested at completion of the designated number of

transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The

transfer dir ection is determined automatically from the activation sour ce.

Repeat Mode: One byte or word is transferred per request. A designated number of these transfers

are executed. When the designated number of tr ansfers are completed, the initial ad dress an d

counter value are restored and operation continues. No CPU interrupt is requested. One 24-bit

address and one 8-bit address are specified. The transfer direction is determined automatically

from th e activ ation source.

Rev. 6.0, 09/02, page 219 of 876

Normal Mode

• Auto-request

The DMAC is activated by register setup alo ne, and continues executing transfers until the

designated number of transfers have been completed. A CPU interrupt can be requested at

completion of the transfers. Both addresses are 24-bit addresses.

 Cycle-steal mode

The bus is released to another bus master after each byte or word is transferred.

 Burst mode

Unless requested by a higher-prio r ity bus master, the bus is not released until the

designated number of transfers have been completed.

• External request

One byte or word is transferred per request. A designated number of these transfers are

executed. A CPU interrupt can be requested at completion of the designated nu mber of

transfers. Both addr esses are 24-bit addresses.

Block Tra nsfer Mode: One block of a specified size is transferred per request. A designated

number of block transfers are executed. At the end of each block transfer, one address is restored

to its initial value. When the design a ted number of blocks have been tran sf erred , a CPU interrupt

can be requested. Both addresses are 24-bit addresses.

Rev. 6.0, 09/02, page 220 of 876

8.4.2 I/O Mode

I/O mode can be selected independently for each channel.

One byte or word is transferred at each transfer request in I/O mode. A designated number of these

transfers are executed. One address is specified in the memory address register (MAR), the other

in the I/O address register (IOAR). The direction of transfer is determined automatically from the

activation source. The transfer is from the address specified in IOAR to the address specified in

MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the address specified

in MAR to the address specified in IOAR otherwise.

Table 8.6 indicates the register functions in I/O mode.

Table 8.6 Register Functions in I/O Mode

Function

Activated by

SCI 0 Receive-

Data-Full

Interrupt Other

Activation Initial Setting Operation

23 0

MAR

Destination

address

Source

address

Destination or

source address Incremented or

decremented

once per

transfer

All 1s IOAR

23 07

Source

address

Destination

address

Source or

destination

address

Held fixed

15 0

ETCR

Transfer

counter Transfer

counter Number of

transfers Decremented

once per

transfer until

H'0000 is

reached and

transfer ends

Legend

MAR: Memory address register

IOAR: I/O address register

ETCR: Execute transfer count register

MAR and IOAR sp ecify the source and destination addresses. MAR specifies a 24-bit source or

destination address, which is incremented or decrem ented as each byte or word is transferred.

IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not

incremented or decremented.

Figure 8.2 illustrates how I/O mode operates.

Rev. 6.0, 09/02, page 221 of 876

Address T

Address B

Transfer

Legend

L = initial setting of MAR

N = initial setting of ETCR

Address T = L

Address B = L + (–1) • (2 • N – 1)

DTID

IOAR

1 byte or word is

transferred per request

DTSZ

Figure 8.2 Operation in I/O Mode

The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at

each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends.

If the DTIE bit is set to 1 , a CPU interrupt is requested at this time. The maximum transfer count

is 65,536, obtained by setting ETCR to H'0000.

Transfers can be requested (activated) by compare match/input captu re A interrupts from ITU

channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and

external request signals.

For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).

Rev. 6.0, 09/02, page 222 of 876

Figure 8.3 shows a sample setup procedure for I/O mode.

Set source and

destination addresses

Set transfer count

Read DTCR

Set DTCR

I/O mode

I/O mode setup

Set the source and destination addresses

in MAR and IOAR. The transfer direction is

determined automatically from the activation

source.

Set the transfer count in ETCR.

Read DTCR while the DTE bit is cleared to 0.

Set the DTCR bits as follows.

Select the DMAC activation source with bits

DTS2 to DTS0.

Set or clear the DTIE bit to enable or disable

the CPU interrupt at the end of the transfer.

Clear the RPE bit to 0 to select I/O mode.

Select MAR increment or decrement with the

DTID bit.

Select byte size or word size with the DTSZ bit.

Set the DTE bit to 1 to enable the transfer.

•

Figure 8.3 I/O Mode Setup Procedure (Example)

8.4.3 Idle Mode

Idle mode can be selected independently for each channel.

One byte or word is transferred at each transfer request in idle mode. A designated number of

these transfers are executed. One address is specified in the memory address register (MAR), the

other in th e I/O address re g ister (IOAR). The direction of transfer is determined automatically

from the activation source. The transfer is from the address specified in IOAR to the address

specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the

address specified in MAR to the address specified in IOAR otherwise.

Table 8.7 indicates the register functions in idle mode.

Rev. 6.0, 09/02, page 223 of 876

Table 8.7 Register Functions in Idle Mode

Function

Activated by

SCI 0 Receive-

Data-Full

Interrupt Other

Activation Initial Setting Operation

23 0

MAR

Destination

address

Source

address

Destination or

source address Held fixed

All 1s IOAR

23 07

Source

address

Destination

address

Source or

destination

address

Held fixed

15 0

ETCR

Transfer

counter Transfer

counter Number of

transfers Decremented

once per

transfer until

H'0000 is

reached and

transfer ends

Legend

MAR: Memory address register

IOAR: I/O address register

ETCR: Execute transfer count register

MAR and IOAR sp ecify the source and destination addresses. MAR specifies a 24-bit source or

destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all

1s. MAR and IOAR are not incremented or decremented.

Figure 8.4 illustrates how idle mode operates.

Transfer

1 byte or word is

transferred per request

IOARMAR

Figure 8.4 Operation in Idle Mode

Rev. 6.0, 09/02, page 224 of 876

The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at

each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and

a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to

H'0000.

Transfers can be requested (activated) by compare match/input captu re A interrupts from ITU

channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and

external request signals.

For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).

Figure 8.5 shows a sample setup procedure for idle mode.

Set source and

destination addresses

Set transfer count

Read DTCR

Set DTCR

Idle mode

Idle mode setup

Set the source and destination addresses

in MAR and IOAR. The transfer direction is deter-

mined automatically from the activation source.

Set the transfer count in ETCR.

Read DTCR while the DTE bit is cleared to 0.

Set the DTCR bits as follows.

Select the DMAC activation source with bits

DTS2 to DTS0.

Set the DTIE and RPE bits to 1 to select idle mode.

Select byte size or word size with the DTSZ bit.

Set the DTE bit to 1 to enable the transfer.

•

Figure 8.5 Idle Mo de Set up P r ocedure (Example)

Rev. 6.0, 09/02, page 225 of 876

8.4.4 Repeat Mode

Repeat mode is useful for cyclically transferring a bit pattern from a table to the prog rammable

timing pattern controller (TPC) in synchronization, for example, with ITU compare match. Repeat

mode can be selected for each channel independ ently.

One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number

of these transfers are ex ecuted. One address is specified in the memory address register (MAR),

the other in the I/O address register (IOAR). At the end of the designated number of transfers,

MAR and ETCR are restored to their original values and operation continues. The direction of

transfer is determined automatically f rom th e activation source. The transfer is from the addr ess

specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-

full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.

Table 8.8 indicates the register functions in repeat mode.

Rev. 6.0, 09/02, page 226 of 876

Table 8.8 Register Functions in Repeat Mo de

Function

Activated by

SCI 0 Receive-

Data-Full

Interrupt Other

Activation Initial Setting Operation

23 0

MAR

Destination

address

Source

address

Destination or

source address Incremented or

decremented at

each transfer

until H'0000,

then restored to

initial value

All 1s IOAR

23 0

Source

address

Destination

address

Source or

destination

address

Held fixed

Transfer

counter Transfer

counter Number of

transfers Decremented

once per

transfer until

H'0000 is

reached, then

reloaded from

ETCRL

ETCRH

ETCRL

Initial transfer

count Initial transfer

count Number of

transfers Held fixed

Legend

MAR: Memory address register

IOAR: I/O address register

ETCR: Execute transfer count register

In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer

count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from

ETCRL. MAR is also restor ed to its initial value, which is calculated from the DTSZ and DTID

bits in DTCR. Specifically , MAR is restored as follows:

MAR ← MAR – (–1)DTID · 2DTSZ · ETCRL

ETCRH and ETCRL should be initially set to the same value.

In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0,

if the CPU sets DTE to 1 again, transf ers resume from the state at which DTE was cleared. No

CPU interrup t is requested.

Rev. 6.0, 09/02, page 227 of 876

As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a

24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper

16 bits are all 1s. IOAR is not incremented or decremented.

Figure 8.6 illustrates how repeat m ode operates.

Address T

Address B

Transfer

1 byte or word is

transferred per request

Legend

L = initial setting of MAR

N = initial setting of ETCRH and ETCRL

Address T = L

Address B = L + (–1) • (2 • N – 1)

DTID DTSZ

IOAR

Figure 8.6 Operation in Repeat Mode

The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer

count is 255, obtained by setting both ETCRH and ETCRL to H'FF.

Transfers can be requested (activated) by compare match/input captu re A interrupts from ITU

channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and

external request signals.

For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR).

Figure 8.7 shows a sample setup procedure for repeat mode.

Rev. 6.0, 09/02, page 228 of 876

Set source and

destination addresses

Set transfer count

Read DTCR

Set DTCR

Repeat mode

Set the source and destination addresses in MAR

and IOAR. The transfer direction is determined

automatically from the activation source.

Set the transfer count in both ETCRH and ETCRL.

Read DTCR while the DTE bit is cleared to 0.

Select byte size or word size with the DTSZ bit.

Set the DTE bit to 1 to enable the transfer.

•

Select the DMAC activation source with bits

DTS2 to DTS0.

Clear the DTIE bit to 0 and set the RPE bit to 1

to select repeat mode.

Select MAR increment or decrement with the

DTID bit.

Set the DTCR bits as follows.

Figure 8.7 Repeat Mode Set up P rocedure (Example)

Rev. 6.0, 09/02, page 229 of 876

8.4.5 Normal Mode

In normal mode the A and B channels are combined. One byte or word is transferred per request.

A designated number of these transfers are executed. Addresses are specified in MARA and

MARB. Table 8.9 indicates the register functions in I/O mode.

Table 8.9 Register Functions in Normal Mode

23 0

MARA

Source address

decremented on ce per

transfer, or held fixed

23 0

MARB

Destination

address register Destination

address Incremen ted or

decremented on ce per

transfer, or held fixed

15 0

ETCRA

Transfer counter Number of

transfers Decremented once per

transfer

Legend

MARA: Memory address register A

MARB: Memory address register B

ETCRA: Execute transfer count register A

The source and destination addresses are both 24-bit addresses. MARA specifies the source

address. MARB specifies the destination address. MARA and MARB can be independently

incremented, decremented, or held fixed as data is transferred.

The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by

1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer

ends. If the DTIE bit is set, a CPU interrupt is requested at this time. The maximum transfer count

is 65,536, obtained by setting ETCRA to H'0000.

Figure 8 . 8 illu str a tes how normal mode operates.

Rev. 6.0, 09/02, page 230 of 876

Address T

Address B

Transfer

Legend

SAID

DAID

Address T

Address B

= initial setting of MARA

= initial setting of MARB

= initial setting of ETCRA

= L

= L + SAIDE • (–1) • (2 • N – 1)

= L

= L + DAIDE • (–1) • (2 • N – 1)

DTSZ

Figure 8.8 Operation in Normal Mode

Transfers can be requested (activated) by an external request or auto-request. An auto-requested

transfer is activated by the register settings alone. The designated number of transfers are executed

automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode the DMAC

releases the bus temporarily after each transfer. In burst mode the DMAC keeps th e b us until the

transfers are completed, unless there is a bus request from a higher-priority bus master.

For the detailed settings see section 8.3.4, Data Transfer Control Registers (DTCR).

Rev. 6.0, 09/02, page 231 of 876

Figure 8.9 shows a sample setup procedure for normal mode.

Set the initial source address in MARA.

Set the initial destination address in MARB.

Set the transfer count in ETCRA.

Set the DTCRB bits as follows.

Set the DTCRA bits as follows.

Read DTCRB with DTME cleared to 0.

Normal mode

Set initial source address

Set initial destination address

Set transfer count

Set DTCRB (1)

Set DTCRA (1)

Read DTCRB

Set DTCRB (2)

Read DTCRA

Set DTCRA (2)

•

Clear the DTME bit to 0.

Set the DAID and DAIDE bits to select whether

MARB is incremented, decremented, or held fixed.

Select the DMAC activation source with bits

DTS2B to DTS0B.

Clear the DTE bit to 0.

Select byte or word size with the DTSZ bit.

Set the SAID and SAIDE bits to select whether

MARA is incremented, decremented, or held fixed.

Set or clear the DTIE bit to enable or disable the

CPU interrupt at the end of the transfer.

Clear the DTS0A bit to 0 and set the DTS2A

and DTS1A bits to 1 to select normal mode.

Set the DTME bit to 1 in DTCRB.

Read DTCRA with DTE cleared to 0.

Set the DTE bit to 1 in DTCRA to enable the transfer.

Note: Carry out settings 1 to 9 with the DEND interrupt masked in the CPU.

If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in

which case the transfer will not start.

Figure 8.9 Normal Mode Setup Procedure (Example)

Rev. 6.0, 09/02, page 232 of 876

8.4.6 Block Transfer Mode

In block transfer mode the A and B channels are combined. One block of a specified size is

transferred per request. A designated number of block transfers are ex ecuted. Addresses are

specified in MARA and MARB. The block area address can be either held fixed or cycled.

Table 8.10 indicates the register functions in block transfer mode.

Table 8.10 Register Functions in Block Transfer Mode

23 0

MARA

Source address

decremented on ce per

transfer, or held fixed

23 0

MARB

Destination

address register Destination

address Incremen ted or

decremented on ce per

transfer, or held fixed

Block size

counter Block size Decremented once per

transfer until H'00 is

reached, then reloaded

from ETCRAL

ETCRAH

ETCRAL

Initial block size Block size Held fixed

15 0

ETCRB

Block transfer

counter Number of block

transfers Decremented once per

block transfer until H'0000

is reached and the

transfer ends

Legend

MARA: Memory address register A

MARB: Memory address register B

ETCRA: Execute transfer count register A

ETCRB: Execute transfer count register B

The source and destination addresses are both 24-bit addresses. MARA specifies the source

address. MARB specifies the destination address. MARA and MARB can be independently

incremented, decremented, or held fixed as data is transferred. One of these registers operates as a

block area register: ev en if it is incremented or decremented, it is r estored to its initial value at the

end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or

destination.

Rev. 6.0, 09/02, page 233 of 876

If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the

number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and

ETCRB should initially be set to N.

Figure 8.10 illustrates how bloc k tran sf er mode operates. In this figu r e, bit TMS is clear ed to 0,

meaning the block area is the destination.

Transfer

Legend

Address T

M bytes or words are

transferred per request

Address B

Block 1

Block N

Block area

Block 2

= initial setting of MARA

= initial setting of MARB

= initial setting of ETCRAH and ETCRAL

= initial setting of ETCRB

= L

= L + SAIDE • (–1) • (2 • M – 1)

= L

= L + DAIDE • (–1) • (2 • M – 1)

SAID

DAID

DTSZ

Figure 8.10 Operation in Block Transfer Mode

Rev. 6.0, 09/02, page 234 of 876

When activated by a transfer request, the DMAC executes a burst transf er. During the transfer

MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented.

When ETCRAH reaches H'00 , it is relo aded from ETCRAL to restore the in itial value. The

memory add r ess register of the block area is also r e stored to its initial value, and ETCRB is

decremented. If ETCRB is not H'0000, the DMAC then waits for the next transfer request.

ETCRAH and ETCRAL should be initially set to the same value.

The above operation is repeated un til ETCRB reaches H'0000, at which point the DTE bit is

cleared to 0 and th e transf er ends. If the DTIE bit is set to 1, a CPU interrupt is r equested at this

time.

Figure 8.11 shows examples of a block transfer with byte data size when the block area is the

destination. In (a) the block area address is cycled. In (b) the block area address is held fixed.

Transfers can be requested (activated) by compare match/input captu re A interrupts from ITU

channels 0 to 3, and by external request signals.

For the detailed settings see section 8.3.4, Data Transfer Control Registers (DTCR).

Rev. 6.0, 09/02, page 235 of 876

Start

(DTE = DTME = 1)

Transfer requested?

Get bus

MARA = MARA + 1

Read from MARA address

Write to MARB address

MARB = MARB + 1

ETCRAH = ETCRAH – 1

ETCRAH = H'00

Release bus

Clear DTE to 0 and end transfer

ETCRAH = ETCRAL

MARB = MARB – ETCRAL

ETCRB = ETCRB – 1

ETCRB = H'0000

Start

(DTE = DTME = 1)

Transfer requested?

Get bus

MARA = MARA + 1

Read from MARA address

Write to MARB address

ETCRAH = ETCRAH – 1

ETCRAH = H'00

Release bus

Clear DTE to 0 and end transfer

ETCRB = ETCRB – 1

ETCRB = H'0000

ETCRAH = ETCRAL

Yes

a. DTSZ = TMS = 0

SAID = DAID = 0

SAIDE = DAIDE = 1

b. DTSZ = TMS = 0

SAID = 0

SAIDE = 1

DAIDE = 0

Figure 8.11 Block Transfer Mode Flowcharts (Examples)

Rev. 6.0, 09/02, page 236 of 876

Figure 8.12 shows a sample setup procedure for block transfer mode.

10.

Block transfer mode

Set source address

Set destination address

Set block transfer count

Set block size

Set DTCRB (1)

Set DTCRA (1)

Read DTCRB

Set DTCRB (2)

Read DTCRA

Set DTCRA (2)

Block transfer mode

Set the source address in MARA.

Set the destination address in MARB.

Set the block transfer count in ETCRB.

Set the block size (number of bytes or words)

in both ETCRAH and ETCRAL.

Set the DTCRB bits as follows.

Set the DTCRA bits as follows.

•

Clear the DTME bit to 0.

Set the DAID and DAIDE bits to select whether

MARB is incremented, decremented, or held fixed.

Set or clear the TMS bit to make the block area

the source or destination.

Select the DMAC activation source with bits

DTS2B to DTS0B.

Clear the DTE to 0.

Select byte size or word size with the DTSZ bit.

Set the SAID and SAIDE bits to select whether

MARA is incremented, decremented, or held fixed.

Set or clear the DTIE bit to enable or disable the

CPU interrupt at the end of the transfer.

Set bits DTS2A to DTS0A all to 1 to select

block transfer mode.

Read DTCRB with DTME cleared to 0.

Set the DTME bit to 1 in DTCRB.

Read DTCRA with DTE cleared to 0.

Set the DTE bit to 1 in DTCRA to enable

the transfer.

Note: Carry out settings 1 to 10 with the DEND interrupt masked in the CPU.

If an NMI interrupt occurs during the setup procedure, it may clear the DTME bit to 0, in

which case the transfer will not start.

Figure 8.12 Block Transfer Mode Setup Procedure (Example)

Rev. 6.0, 09/02, page 237 of 876

8.4.7 DMAC Activation

The DMAC can be activated by an internal interrupt, external request, or auto-request. The

available activation sources differ depending on the transfer mode and channel as indicated in

table 8.11.

Table 8.11 DMAC Activation Sources

Short Address Mode Full Address Mode

Activation Source Channels

0A and 1A Channels

0B and 1B Normal Block

IMIA0 Yes Yes No Yes

IMIA1 Yes Yes No Yes

IMIA2 Yes Yes No Yes

IMIA3 Yes Yes No Yes

TXI0 Yes Yes No No

Internal

interrupts

RXI0 Yes Yes No No

Falling edge of

DREQ No Yes Yes YesExternal

requests Low input at

DREQ No Yes Yes No

Auto-request No No Yes No

Activation by Internal Interrupts: When an interrupt request is selected as a DMAC activation

source and the DTE bit is set to 1, that interrupt request is not sent to the CPU. It is not possible

for an interrupt request to activate the DMAC and simu ltaneously generate a CPU interrupt.

When the DMAC is activated by an interrupt request, the interrupt request flag is cleared

automatically. I f the same interrupt is selected to activate two or more channels, the interrup t

request flag is cleared when the highest-priority channel is activated, but the transfer request is

held pending on the other channels in the DMAC, which are activated in their priority order.

Rev. 6.0, 09/02, page 238 of 876

Activation by External Request: If an external request (DREQ pin) is selected as an activation

source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output

pin, regardless of the port data direction register (DDR) settings. The DREQ input can be level-

sensitive or edge-sensitive.

In short address mode and normal mode, an external request operates as follows. If edge sensing is

selected, one byte or word is transferred each time a high-to-low transition of the DREQ input is

detected. If the next edge is input before the transfer is completed, the next transfer may not be

executed. If level sensing is selected, the transf er con tinue s while DREQ is low, until the transfer

is completed. The bus is released temporarily after each byte or word has been transferred,

however. If the DREQ input goes high during a transfer, the transfer is suspended after the current

byte or word has been transferred. Wh en DREQ goes low, the request is held internally until one

byte or word has been transferred. The TEND signal goes low during the last write cycle.

In block tran sf er mode, an external request operates as f ollows. Only edge-sensitiv e tr ansfer

requests are possible in block transfer mode. Each time a high-to-low transition of the DREQ

input is detected, a block of the specified size is transferred. The TEND signal goes low during the

last write cycle in each block.

Activation by Auto-Request : The transfer starts as soon as enabled by register setup, and

continues until completed. Cycle-steal mode or burst mode can be selected.

In cycle-steal mode the DMAC releases the bus temporarily after transferring each byte or word.

Normally, DMAC cycles alternate with CPU cycles.

In burst mod e the DMAC keeps the bus until the transfer is completed, unless there is a higher-

priority bus request. If there is a higher-pr iority bus request, the bus is released after the current

byte or word has been transferred.

Rev. 6.0, 09/02, page 239 of 876

8.4.8 DMAC Bus Cycle

Figure 8.13 shows an ex ample of the timing of the basic DMAC bus cycle. This example shows a

word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the

DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and

writes to the destination address. During these read and write operations the bus is not released

even if there is anoth e r bus request. DMAC cy cles comply with bu s contro ller settings in the same

way as CPU cycles.

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

3 T

1 T

2 T

3 T

1 T

2 T

1 T

CPU cycle DMAC cycle (word transfer) CPU cycle

Source

address Destination address

Address

bus

Figure 8.13 DMA Transfer Bus Timing (Example)

Rev. 6.0, 09/02, page 240 of 876

Figure 8.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This

example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state

access area. The DMAC continues the transfer while the DREQ pin is held low.

CPU cycle DMAC cycle CPU cycle DMAC cycle

(last transfer cycle) CPU cycle

Source

address Destination

address Source

address Destination

address

Address

bus

Figure 8.14 Bus Timing of DMA Transfer Requested by Low DREQ

DREQDREQ

DREQ Input

Rev. 6.0, 09/02, page 241 of 876

Figure 8.15 shows an auto-requested burst-mode transfer. Th is example shows a transfer of three

words from a 16-bit two-state access area to another 16-bit two-state access area.

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

1 T

CPU cycle DMAC cycle

Source

address Destination

address

CPU cycle

Address

bus

Figure 8.15 Bus Timing of Burst Mode DMA Transfer

When the DMAC is activated from a DREQ pin there is a minimum interval of four states from

when the tran sf er is req uested until the DMAC starts oper a ting. The DREQ pin is not sampled

during the time between the transfer request and the start of the transfer. In short address mode

and normal mode, th e pin is next sampled at the end of the read cycle. In block transfer mode, the

pin is next sampled at the end of one block transfer.

Rev. 6.0, 09/02, page 242 of 876

Figure 8.16 shows the timing when th e DMAC is activated by the falling edge of DREQ in normal

mode.

CPU cycle DMAC cycle CPU

cycle DMAC cycle

Minimum 4 states Next sampling point

Address

bus

Figure 8.16 Timing of DMAC Activation by Falling Edge of DREQ

DREQDREQ

DREQ in Normal Mode

Rev. 6.0, 09/02, page 243 of 876

Figure 8.17 shows the timing when the DMAC is activated by level-sen sitive low DREQ input in

normal mode.

CPU cycle DMAC cycle CPU cycle

Minimum 4 states Next sampling point

Address

bus

Figure 8.17 Timing of DMAC Activation by Low DREQ

DREQDREQ

DREQ Level in No rmal Mode

Rev. 6.0, 09/02, page 244 of 876

Figure 8.18 shows the timing when th e DMAC is activated by the falling edge of DREQ in block

transfer mode.

DMAC cycle DMAC cycleCPU cycle

Next sampling

Minimum 4 states

End of 1 block transfer

Address

bus

Figure 8.18 Timing of DMAC Activation by Falling Edge of DREQ

DREQDREQ

DREQ in Block Transfer Mode

Rev. 6.0, 09/02, page 245 of 876

8.4.9 DMAC Multiple- Channel Operatio n

The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B.

Table 8.12 shows the complete priority order.

Table 8.12 Channel Priority Order

Short Address Mode Full Address Mode Priority

Channel 0A Channel 0

Channel 0B

Channel 1A Channel 1

Channel 1B

High

↑



Low

If transfers are requested on two or more channels simultaneously, or if a transfer on one ch annel

is requested during a transfer on another channel, the DMAC operates as follows.

1. When a transfer is requested, the DMAC requests the bus right. When it gets the bu s right, it

starts a transfer on the highest-priority channel at that time.

2. Once a transfer starts on one channel, r equests to other channels are held pending until that

channel releases the bus.

3. After each transfer in short address mode, and each externally-requested or cycle-steal transfer

in norm al mode, the DMAC releases the bus and returns to step 1. After releasin g the bus, if

there is a transfer request for another channel, the DMAC requests the bus again.

4. After completion of a burst-mode transfer, or after transfer of one block in block transfer

mode, the DMAC releases the bus and returns to step 1. If there is a tran sfer request for a

higher-priority channel or a bus request from a higher-priority bus master, however, the

DMAC releases the bus after completing the transfer o f the curren t byte or word. After

releasing the bus, if th ere is a transfer request for another channel, the DMAC requests the bus

again.

Figure 8.19 shows the timing when channel 0A is set up for I/O mode and channel 1 for burst

mode, and a transfer requ est for channel 0A is received while channel 1 is active.

Rev. 6.0, 09/02, page 246 of 876

DMAC cycle

(channel 1) CPU

cycle DMAC cycle

(channel 0A) CPU

cycle DMAC cycle

(channel 1)

Address

bus

Figure 8.19 Timing of Multiple-Channel Operations

8.4.10 External Bus Requests, Refresh Controller, and DMAC

During a DMA transfer, if the bus right is requested by an external bus request signal (BREQ) or

by the refresh contr oller, the DMAC releases the bus after completing the transfer of the current

byte or word. If there is a transfer request at this point, the DMAC requests the bus right again.

Figure 8.20 shows an example of the timing of insertion of a refresh cycle du ring a burst transfer

on channel 0.

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

1 T

2 T

d T

1 T

2 T

1 T

2 T

1 T

DMAC cycle (channel 0) DMAC cycle (channel 0)

Refresh

cycle

Address

bus

Figure 8.20 Bus Timing of Refresh Controller and DMAC

Rev. 6.0, 09/02, page 247 of 876

8.4.11 NMI Interrupt s and DMA C

NMI interrupts do not affect DMAC operations in short address mode.

If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations.

In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI

input clears the DTME bit to 0. After transferring the current byte or word, the DMAC releases the

bus to the CPU. In normal mode, the suspended transfer resumes when the CPU sets the DTME

bit to 1 again. Check that the DTE bit is set to 1 and the DTME bit is clear ed to 0 b efor e settin g

the DTME bit to 1.

Figure 8.21 shows the procedure for resuming a DMA transfer in normal mode on channel 0 after

the transfer was halted by NMI input.

Resuming DMA transfer

in normal mode

DTE = 1

DTME = 0

Set DTME to 1

DMA transfer continues End

2. Check that DTE = 1 and DTME = 0.

Read DTCRB while DTME = 0,

then write 1 in the DTME bit.

Yes

Figure 8.21 Procedure for Resuming a DMA Transfer Halted by NMI (Example)

For information about NMI interrupts in block transfer mode, see section 8.6.6, NMI Interrupts

and Block Tran sfer Mode.

Rev. 6.0, 09/02, page 248 of 876

8.4.12 Aborting a DMA Transfer

When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the

current byte or word. The DMAC starts again when the DTE bit is set to 1. I n full address mode,

the DTME bit can be used for the same purpose. Figure 8.22 shows the procedure for aborting a

DMA transfer by software.

DMA transfer abort

Set DTCR

DMA transfer aborted

1. Clear the DTE bit to 0 in DTCR.

To avoid generating an interrupt when

aborting a DMA transfer, clear the DTIE

bit to 0 simultaneously.

Figure 8.22 Procedure for Aborting a DMA Transfer

Rev. 6.0, 09/02, page 249 of 876

8.4.13 Exiting Full Address Mode

Figure 8.23 shows the procedure for ex iting full address mode and in itializing the pair of channels.

To set the channels up in another mode after exitin g fu ll addr ess mode, follow the setup procedure

for the relevant mode.

Exiting full address mode

Halt the channel

Initialize DTCRB

Initialize DTCRA

Initialized and halted

Clear the DTE bit to 0 in DTCRA, or wait

for the transfer to end and the DTE bit

to be cleared to 0.

Clear all DTCRB bits to 0.

Clear all DTCRA bits to 0.

Figure 8.23 Procedure for Exiting Full Address Mode (Example)

Rev. 6.0, 09/02, page 250 of 876

8.4.14 DMAC Stat es in Reset Stat e, Standby Modes, and Sleep Mode

When the chip is reset or en ters hardware or software standby mode, the DMAC is initialized and

halts. DMAC operations continue in sleep mode. Figure 8.24 shows the timing of a cycle-steal

transfer in sleep mode.

Address bus

T T

2 1

CPU cycle DMAC cycle DMAC cycle

Sleep mode

Figure 8.24 Timing of Cycle-Steal Transfer in Sleep Mode

Rev. 6.0, 09/02, page 251 of 876

8.5 Interrupts

The DMAC genera tes only DMA-end interrupts. Tab le 8.13 lists the interrupts and th eir pr iority .

Table 8.13 DMAC Interrupts

Description

Interrupt Short Address Mode Full Address Mode Interrupt

Priority

DEND0A End of transfer on channel 0A End of transfer on channel 0

DEND0B End of transfer on channel 0B —

DEND1A End of transfer on channel 1A End of transfer on channel 1

DEND1B End of transfer on channel 1B —

High

↑



Low

Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control

The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B.

Figure 8.25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and

DTIE = 1.

DTE

DTIE

DMA-end interrupt

Figure 8.25 DMA-End Interrupt Logic

The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The

DTME bit does not affect interrupt op erations.

Rev. 6.0, 09/02, page 252 of 876

8.6 Usage Notes

8.6.1 Note on Word Data Transfer

Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set

even values in the memory and I/O address registers (MAR and IOAR).

8.6.2 DMAC Self-Access

The DMAC itself cannot be accessed during a DMAC cycle. DMAC registers cannot be specified

as source or destination addresses.

8.6.3 Longword Access to Memory Address Registers

A memory address register can be accessed as longword data at the MARR address.

Example

MOV.L #LBL, ER0

MOV.L ER0, @MARR

Four byte accesses are performed. Note that the CPU may release the bus between the second byte

(MARE) and third byte (MARH).

Memory address registers should be written and read only when the DMAC is halted.

8.6.4 Note on Full Address Mode Setup

Full address mode is controlled by two registers: DTCRA and DTCRB. Care must be taken to

prevent the B channel from operating in short address mode during the register setup. The enable

bits (DTE and DTME) shou ld not be set to 1 until the end of the setup procedure.

8.6.5 Note on Activating DMAC by Internal Interrupts

When using an internal interrupt to activate the DMAC, mak e sure that the interrupt selected as

the activating source does not occur during the interval after it has been selected but before the

DMAC has been enabled. The on-chip supporting module that will generate the interrupt should

not be activated until th e DMAC has been enabled. If the DMAC mu st be enabled while the on-

chip supporting module is active, follow the procedure in figure 8.26.

Rev. 6.0, 09/02, page 253 of 876

Enabling of DMAC

Selected interrupt

requested?

Interrupt hand-

ling by CPU

Clear selected interrupt’s

enable bit to 0

Enable DMAC

Set selected interrupt’s

enable bit to 1

While the DTE bit is cleared to 0,

interrupt requests are sent to the

CPU.

Clear the interrupt enable bit to 0

in the interrupt-generating on-chip

supporting module.

Enable the DMAC.

Enable the DMAC-activating

interrupt.

DMAC operates

Yes

Figure 8.26 Procedure for Enabling DMAC while On-Chip Sup porting Module is

Operating (Example)

If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected

activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for

example, the selected activating source cannot generate CPU interrupts. To terminate DMAC

operations in this state, clear the DTE bit to 0 to allow CPU inter rupts to be requested. To continue

DMAC operations, carry out steps 2 and 4 in figure 8.26 before and after setting the DTME bit to

When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before

the DMA transfer ends. If one ITU interrupt activates two or more channels, make sure the next

interrupt does not occur before the DMA transfers end on all the activated channels. If the next

interrupt o ccurs before a transfer ends, the channel or channels for which that inter rupt was

selected may fail to accept further activation requests.

Rev. 6.0, 09/02, page 254 of 876

8.6.6 NMI Interrupts and Block Transfer Mode

If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows.

• When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then

clears the DTME bit to 0 and halts. The halt may occur in the middle of a block.

It is possible to find whether a transfer was halted in the middle of a block by checking the

block size counter. If the block size counter does not have its initial value, the transfer was

halted in the middle of a block.

• If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0. The

activation request is not held pending.

• While the DTE bit is set to 1 an d the DTME bit is cleared to 0, the DMAC is halted and does

not accept activating interrupt requests. If an activating interrupt occurs in this state, the

DMAC does not operate and does not hold the transfer request pending internally. Neither is a

CPU interrupt requested.

For this reason, before setting th e DTME bit to 1, fir st clear th e enab le bit of the activating

interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See

section 8.6.5, Note on Activating DMAC by Internal Interrupts.

• When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted

in the middle of a block transfer, the rest of the block is transferred when the next transfer

request occurs. Otherwise, the next block is transferred when the next transfer request occurs.

8.6.7 Memory and I/O Address Regi ster Values

Table 8.14 indicates the address ranges that can be sp ecified in the memory and I/O address

registers (MAR and IOAR).

Table 8.14 Address Ranges Specifiable in MAR and IOAR

1-Mbyte Mode 16-Mbyte Mode

MAR H'00000 to H'FFFFF

(0 to 1048575) H'000000 to H'FFFFFF

(0 to 16777215)

IOAR H'FFF00 to H'FFFFF

(1048320 to 1048575) H'FFFF00 to H'FFFFFF

(16776960 to 16777215)

MAR bits 23 to 20 are ignored in 1-Mbyte mode.

Rev. 6.0, 09/02, page 255 of 876

8.6.8 Bus Cycle when Transfer is Aborted

When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME

bit, if this halts a channel for which the DMAC has a tr ansfer request pending internally, a dead

cycle may occur. Th is dead cycle does not update the halted channel’s address register or counter

value. Figure 8.27 shows an example in which an auto-requested transfer in cycle-steal mode on

channel 0 is aborted by clearing the DTE bit in channel 0.

Address bus

CPU cycle DMAC cycle CPU cycle DMAC

cycle CPU cycle

DTE bit is

cleared

Figure 8.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode

Rev. 6.0, 09/02, page 256 of 876

Rev. 6.0, 09/02, page 257 of 876

Section 9 I/O Ports

9.1 Overview

The H8/3048 Series has 10 input/output ports (ports 1, 2, 3, 4, 5, 6, 8, 9, A, and B) and one input

port (port 7). Table 9.1 summarizes the port functions. The pins in each port are multiplex ed as

shown in table 9.1.

Each port has a data direction register (DDR) for selecting input or output, and a data register

(DR) for storin g output data. In addition to these registers, ports 2, 4, and 5 have an input pull-up

MOS control register (PCR) for switching input pull-up MOS transistors on and off.

Ports 1 to 6 and port 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can

drive one TTL load and a 30-pF capacitive load. Ports 1 to 6 and 8 to B can drive a darlington

pair. Ports 1, 2, 5, and B can drive LEDs (with 10-mA current sink). Pins P82 to P80, PA7 to PA0,

and PB3 to PB0 have Schmitt-trig ger input circuits.

For block diagrams of the po rts see appendix C, I/O Port Block Diagrams.

Rev. 6.0, 09/02, page 258 of 876

Table 9.1 Port Functions

Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

Port 1 • 8-bit I/O port

• Can drive

LEDs

P17 to P10/

A7 to A0

Address output pi ns (A7 to A0) Address out put (A 7

to A0) and generic

input

DDR = 0: generic

input

DDR = 1: address

output

Generic

input/

output

Port 2 • 8-bit I/O port

• Input pull-up

MOS

• Can drive

LEDs

P27 to P20/

A15 to A8

Address output pi ns (A15 to A8) A ddress output (A15

to A8) and generic

input

DDR = 0: generic

input

DDR = 1: address

output

Generic

input/

output

Port 3 • 8-bit I/O port P37 to P30/

D15 to D8

Data input/output (D15 to D8) Generic

input/

output

Port 4 • 8-bit I/O port

• Input pull-up

MOS

P47 to P40/

D7 to D0

Data input/output (D7 to D0) and 8-bit generic input/output

8-bit bus mode: generic input/output

16-bit bus mode: data input/out put

Generic

input/

output

Port 5 • 4-bit I/O port

• Input pull-up

MOS

• Can drive

LEDs

P53 to P50/

A19 to A16

Address out put (A 19 to A16) Address out put (A 19

to A16) and 4-bit

generic input

DDR = 0: generic

input

DDR = 1: address

output

Generic

input/

output

P66/LWR,

P65/HWR,

P64/RD,

P63/AS

Bus control signal output (LWR, HWR, RD, AS)

Port 6 • 7-bit I/O port

P62/BACK,

P61/BREQ,

P60/WAIT

Bus control signal i nput/ output (BACK, BREQ, WAIT) and 3-

bit generic input/out put

Generic

input/

output

P77/AN7/DA1,

P76/AN6/DA0

Analog input (AN7, AN6) to A/D converter, analog output (DA 1, DA 0) f rom

D/A converter, and generic input

Port 7 • 8-bit I/O port

P75 to P70/

AN5 to AN0

Analog input (AN5 to AN0) to A/D converter, and generic input

Rev. 6.0, 09/02, page 259 of 876

Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

P84/CS0DDR = 0: generic input

DDR = 1 (after reset): CS0 output

Generic

input/

output

/CS

/IRQ

/CS

/IRQ

P81/CS3/IRQ1

IRQ3 to IRQ1 input, CS1 to CS3 output, and generic input

DDR = 0 (after reset): generic i nput

DDR = 1: CS1 to CS3 output

Port 8 • 5-bit I/O port

• P82 to P80

have Schmitt

inputs

P80/RFSH/IRQ0IRQ0 input , RFSH output, and generic input/output

IRQ3 to

IRQ0

input and

generic

input/

output

Port 9 • 6-bit I/O port P9

/SCK

/IRQ

/SCK

/IRQ

P93/RxD1,

P92/RxD0,

P91/TxD1,

P90/TxD0

Input and output (SCK1, S CK 0, RxD1, RxD0, TxD1, TxD0) for serial

communicati on i nterf aces 1 and 0 (SCI1/0), IRQ5 and IRQ4 input, and 6-

bit generic input/out put

PA7/TP7/

TIOCB2/A20

Output (TP7) from

programmable

timing pattern

controll er (TPC),

input or output

(TIOCB2) f or 16-bit

integrated tim er unit

(ITU), and generic

input/output

Address out put

(A20)TPC

output

(TP7),

ITU input

or output

(TIOCB

and

generic

input/

output

Address

output

(A20)

TPC

output

(TP7),

ITU input

or output

(TIOCB

and

generic

input/

output

Port A • 8-bit I/O port

• Schmitt

inputs

PA6/TP6/

TIOCA

/CS

PA5/TP5/

TIOCB

/CS

PA4/TP4/

TIOCA1/A23/CS6

TPC output (TP6 to

TP4), ITU input and

output (TIOCA 2,

TIOCB1, TIOCA1),

CS4 to CS6 output,

and generic input/

output

TPC output (TP6 to

TP4), ITU input and

output (TIOCA 2,

TIOCB1, TIOCA1),

address output (A23

to A21), CS4 to CS6

output, and generic

input/output

TPC

output

(TP6 to

TP4), ITU

input and

output

(TIOCA2,

TIOCB1,

TIOCA1),

CS4 to

CS6

output,

and

generic

input/

output

TPC

output

(TP6 to

TP4), ITU

input and

output

(TIOCA2,

TIOCB1,

TIOCA1),

address

output

(A23 to

A21), CS4

to CS6

output,

and

generic

input/out

put

TPC

output

(TP6 to

TP4), ITU

input and

output

(TIOCA2,

TIOCB1,

TIOCA1),

and

generic

input/

output

Rev. 6.0, 09/02, page 260 of 876

Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

Port A • 8-bit I/O port

• Schmitt

inputs

PA3/TP3/

TIOCB0/

TCLKD,

PA2/TP2/

TIOCA0/

TCLKC,

PA1/TP1/

TEND

/TCLKB,

PA0/TP0/

TEND0/TCLKA

TPC output (TP3 to TP0), output (TEND1, TEND0) from DMA controll e r

(DMAC), ITU input and output (TCLKD, TCLKC, TCLKB, TCLKA,

TIOCB0, TIOCA0), and generic i nput/output

PB7/TP15/

DREQ1/ADTRG TPC output (TP15), DMAC input (DREQ1), t ri gger input (ADTRG) to A/D

convert er, and generic input/ output

PB6/TP14/

DREQ0/CS7

TPC output (TP14), DMA C input (DREQ0), CS7 output, and

generic input/out put TPC

output

(TP14),

DMAC

input

(DREQ0),

and

generic

input/

output

Port B • 8-bit I/O port

• Can drive

LEDs

• PB3 to PB0

have Schmitt

inputs

PB5/TP13/

TOCXB4,

PB4/TP12/

TOCXA4,

PB3/TP11/

TIOCB4,

PB2/TP10/

TIOCA4,

PB1/TP9/

TIOCB3,

PB0/TP8/

TIOCA3

TPC output (TP13 to TP8), ITU input and output (TOCXB4, TOCXA4,

TIOCB4, TIOCA4, TIOCB3, TIOCA3), and generic input/output

Rev. 6.0, 09/02, page 261 of 876

9.2 Port 1

9.2.1 Overview

Port 1 is an 8-bit input/output port with the pin configuration shown in figure 9.1. The pin

functions differ between the expanded modes with on-chip ROM disabled, expanded modes with

on-chip ROM enabled, and single-chip mode. In modes 1 to 4 (expanded modes with on-chip

ROM disabled), they are address bus output pins (A7 to A0).

In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings in the port 1 data

direction register (P1DDR) can designate pins for address bus output (A7 to A0) or generic input.

In mode 7 (single-chip mode), port 1 is a generic input/output port.

When DRAM is connected to area 3, A7 to A0 output row and column addresses in read and write

cycles. For details see section 7, Refresh Controller.

Pins in port 1 can driv e one TTL load and a 90-pF capacitive load. They can also dr ive a

darlington transistor pair.

Port 1

P1 /A

P1 (input/output)

A (output)

Port 1 pins Mode 7Modes 1 to 4

P1 (input)/A (output)

Modes 5 and 6

Figure 9.1 Port 1 Pin Configuration

Rev. 6.0, 09/02, page 262 of 876

9.2.2 Register Descriptions

Table 9.2 summarizes the registers of port 1.

Table 9.2 Port 1 Registers

Initial Value

Address*Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7

H'FFC0 Port 1 data direction

H'FFC2 Port 1 data register P1DR R/W H'00 H'00

Note: * Lower 16 bits of the address.

Port 1 Data Direction Register (P1DDR)

P1DDR is an 8-bit write-only register that can select input or ou tput for each pin in port 1.

Bit

Modes

1 to 4 Initial value

Read/Write

Initial value

Read/Write

Modes

5 to 7

P1 DDR

—

P1 DDR

—

P1 DDR

—

P1 DDR

—

P1 DDR

—

P1 DDR

—

P1 DDR

—

P1 DDR

—

Port 1 data direction 7 to 0

These bits select input or

output for port 1 pins

Modes 1 to 4 (Expanded Mo des with On-Chip ROM Disabled): P1DDR values are fixed at 1

and cannot be modified. Port 1 functions as an address bus.

Modes 5 and 6 (Expanded Modes with On-Chip ROM Enabled): A pin in port 1 becomes an

address output pin if th e corresponding P1DDR bit is set to 1, and a generic input pin if this bit is

cleared to 0.

Mode 7 (Single-Chip Mode): Port 1 functions as an input/output port. A pin in port 1 becomes an

output pin if the corresponding P1DDR bit is set to 1, and an input pin if this bit is cleared to 0.

In modes 5 to 7, P1 DDR is a wr ite-only register . I ts value cannot be read. All bits retur n 1 when

read.

Rev. 6.0, 09/02, page 263 of 876

P1DDR is initialized to H'FF in modes 1 to 4 and H'00 in modes 5 to 7 by a reset and in hardware

standby mode. In software standby mode it retains its previous setting. If a P1DDR bit is set to 1,

the corresponding pin maintains its output state in software standby mode.

Port 1 Data Register (P1DR)

P1DR is an 8-b it r eadable/writable register that stores port 1 output data. While port 1 acts as an

output port, the value of this register is output. When this register is read, the pin logic level of a

pin is read for bits for which the P1DDR setting is 0, and the P1DR v a lu e is read for bits for which

the P1DDR setting is 1.

Bit

Initial value

Read/Write

R/W

Port 1 data 7 to 0

These bits store data for port 1 pins

R/W

P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Rev. 6.0, 09/02, page 264 of 876

9.3 Port 2

9.3.1 Overview

Port 2 is an 8-bit input/output port with the pin configuration shown in figure 9.2. The pin

functions differ according to the operating mode.

In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus

output pins (A15 to A8). In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings

in the port 2 data direction register (P2DDR) can designate pins for address bus output (A15 to A8)

or generic input. In mode 7 (single-chip mode), port 2 is a generic input/output port.

When DRAM is connected to area 3, A9 and A8 output row and column addresses in read and write

cycles. For details see section 7, Refresh Controller.

Port 2 has software-programmable built-in pull-up MOS. Pins in port 2 can drive one TTL load

and a 90-pF capacitive load. They can also drive a darlington transistor pa ir .

Port 2

P2 /A

P2 (input/output)

A (output)

Port 2 pins Mode 7Modes 1 to 4

P2 (input)/A (output)

Modes 5 and 6

Figure 9.2 Port 2 Pin Configuration

Rev. 6.0, 09/02, page 265 of 876

9.3.2 Register Descriptions

Table 9.3 summarizes the registers of port 2.

Table 9.3 Port 2 Registers

Initial Value

Address*Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7

H'FFC1 Port 2 data direction

H'FFC3 Port 2 data register P2DR R/W H'00 H'00

H'FFD8 Port 2 input pull-up MOS

control register P2PCR R/W H'00 H'00

Note: * Lower 16 bits of the address.

Port 2 Data Direction Register (P2DDR)

P2DDR is an 8-bit write-only register that can select input or ou tput for each pin in port 2.

Bit

Modes

1 to 4 Initial value

Read/Write

Initial value

Read/Write

Modes

5 to 7

P2 DDR

—

P2 DDR

—

P2 DDR

—

P2 DDR

—

P2 DDR

—

P2 DDR

—

P2 DDR

—

P2 DDR

—

Port 2 data direction 7 to 0

These bits select input or

output for port 2 pins

Modes 1 to 4 (Expanded Mo des with On-Chip ROM Disabled): P2DDR values are fixed at 1

and cannot be modified. Port 2 functions as an address bus.

Modes 5 and 6 (Expanded Modes with On-Chip ROM Enabled): Fo llowing a reset, po r t 2 is

an input port. A pin in port 2 becomes an address output pin if the corresponding P2DDR bit is set

to 1, and a generic input p ort if this bit is cleared to 0.

Mode 7 (Single-Chip Mode): Port 2 functions as an inpu t/output port. A pin in port 2 becomes an

output port if the corresponding P2DDR bit is set to 1, and an input port if this bit is cleared to 0.

In modes 1 to 4, P2DDR always returns 1 when read. No v alue can be written to.

Rev. 6.0, 09/02, page 266 of 876

In modes 5 to 7, P2 DDR is a wr ite-only register . I ts value cannot be read. All bits retur n 1 when

read.

P2DDR is initialized to H'FF in modes 1 to 4 and H'00 in modes 5 to 7 by a reset and in hardware

standby mode. In software standby mode it retains its previous setting. If a P2DDR bit is set to 1,

the corresponding pin maintains its output state in software standby mode.

Port 2 Data Register (P2DR)

P2DR is an 8-bit readable/writable register that stores output data for pins P27 to P20. Wh ile por t 2

acts as an outpu t por t, th e valu e of th is r e gister is output. When a b it in P2DDR is set to 1, if port 2

is read the value of the corresponding P2DR bit is returned. When a b it in P2DDR is cleared to 0,

if port 2 is read the corresponding pin level is read.

Bit

Initial value

Read/Write

R/W

Port 2 data 7 to 0

These bits store data for port 2 pins

R/W

P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Port 2 Input P ull- Up MOS Control Register ( P 2PCR)

P2PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port

Bit

Initial value

Read/Write

P2 PCR

R/W

Port 2 input pull-up MOS control 7 to 0

These bits control input pull-up

transistors built into port 2

P2 PCR

R/W

P2 PCR

R/W

P2 PCR

R/W

P2 PCR

R/W

P2 PCR

R/W

P2 PCR

R/W

P2 PCR

R/W

In modes 5 to 7, when a P2DDR bit is cleared to 0 (selecting generic input), if the corresponding

bit fro m P27PCR to P20PCR is set to 1, the input p ull-up MOS is turned on.

Rev. 6.0, 09/02, page 267 of 876

P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Table 9.4 summarizes the states of the input pull-up transistors.

Table 9.4 Input Pul l-Up MOS States (Por t 2)

Mode Reset Hardware

Standby Mode Software

Standby Mode Other Modes

1 Off Off Off Off

5 Off Off On/off On/off

Legend

Off: The input pull-up MOS is always off.

On/off: The input pull-up MOS is on if P2PCR = 1 and P2DDR = 0. Otherwise, it is off.

Rev. 6.0, 09/02, page 268 of 876

9.4 Port 3

9.4.1 Overview

Port 3 is an 8-bit input/output port with the pin configuration shown in figure 9.3. Port 3 is a data

bus in modes 1 to 6 (expanded modes) and a generic input/output port in mode 7 (single-chip

mode).

Pins in port 3 can driv e one TTL load and a 90-pF capacitive load. They can also dr ive a

darlington transistor pair.

Port 3

P3 /D

P3 (input/output)

D (input/output)

Port 3 pins Mode 7Modes 1 to 6

Figure 9.3 Port 3 Pin Configuration

9.4.2 Register Descriptions

Table 9.5 summarizes the registers of port 3.

Table 9.5 Port 3 Registers

Address*Name Abbreviation R/W Initial Value

H'FFC4 Port 3 data direction register P3DDR W H'00

H'FFC6 Port 3 data register P3DR R/W H'00

Note: * Lower 16 bits of the address.

Rev. 6.0, 09/02, page 269 of 876

Port 3 Data Direction Register (P3DDR)

P3DDR is an 8-bit write-only register that can select input or ou tput for each pin in port 3.

Bit

Initial value

Read/Write

P3 DDR

Port 3 data direction 7 to 0

These bits select input or output for port 3 pins

P3 DDR

Modes 1 to 6 (Expanded Modes): Port 3 functions as a data bus. P3DDR is ignored.

Mode 7 (Single-Chip Mode): Port 3 functions as an inpu t/output port. A pin in port 3 becomes an

output port if the corresponding P3DDR bit is set to 1, and an input port if this bit is cleared to 0.

P3DDR is a write-only register. Its value cannot be read. All bits return 1 when read.

P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting. If a P3DDR bit is set to 1, the corresponding pin m a intains its output

state in software standby mode.

Port 3 Data Register (P3DR)

P3DR is an 8-bit readable/writable register that stores output data for pins P37 to P30. Wh ile por t 3

acts as an outpu t por t, the value of this register is ou tp ut. When a bit in P3DDR is set to 1 , if port 3

is read the value of the co rresponding P3DR bit is returned. When a bit in P3DDR is cleared to 0,

if port 3 is read the corresponding pin level is read.

Bit

Initial value

Read/Write

R/W

Port 3 data 7 to 0

These bits store data for port 3 pins

R/W

P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Rev. 6.0, 09/02, page 270 of 876

9.5 Port 4

9.5.1 Overview

Port 4 is an 8-bit input/output port with the pin configuration shown in figure 9.4. The pin

functions differ according to the operating mode.

In modes 1 to 6 (expanded modes), when the bus width control register (ABWCR) designates

areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic

input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip

operates in 16-bit bus mode and port 4 becomes part of the data bus. In mode 7 (single-chip

mode), port 4 is a generic input/output port.

Port 4 ha s software-programmable built-in pull-u p MOS.

Pins in port 4 can driv e one TTL load and a 90-pF capacitive load. They can also dr ive a

darlington transistor pair.

Port 4

P4 /D

P4 (input/output)/D7 (input/output)

P4 (input/output)/D6 (input/output)

P4 (input/output)/D5 (input/output)

P4 (input/output)/D4 (input/output)

P4 (input/output)/D3 (input/output)

P4 (input/output)/D2 (input/output)

P4 (input/output)/D1 (input/output)

P4 (input/output)/D0 (input/output)

Port 4 pins Modes 1 to 6

P4 (input/output)

Mode 7

Figure 9.4 Port 4 Pin Configuration

Rev. 6.0, 09/02, page 271 of 876

9.5.2 Register Descriptions

Table 9.6 summarizes the registers of port 4.

Table 9.6 Port 4 Registers

Address*Name Abbreviation R/W Initial Value

H'FFC5 Port 4 data direction register P4DDR W H'00

H'FFC7 Port 4 data register P4DR R/W H'00

H'FFDA Port 4 input pull-up MOS control

Note: * Lower 16 bits of the address.

Port 4 Data Direction Register (P4DDR)

P4DDR is an 8-bit write-only register that can select input or ou tput for each pin in port 4.

Bit

Initial value

Read/Write

P4 DDR

Port 4 data direction 7 to 0

These bits select input or output for port 4 pins

P4 DDR

Modes 1 to 6 (Expanded Modes): When all areas are designated as 8-bit-access areas using the

bus width control register (ABWCR) of the bus controller, selecting 8-bit bus mode, port 4

functions as a generic input/output port. A pin in port 4 becomes an output port if the

correspo ndin g P4DDR bit is set to 1, and an input port if this bit is cleared to 0.

When at least one area is designated as a 16-bit-access area, selecting 16-bit bus mode, port 4

functions as part of the data bus regardless of the value in P4DDR.

Mode 7 (Single-Chip Mode): Port 4 functions as an inpu t/output port. A pin in port 4 becomes an

output port if the corresponding P4DDR bit is set to 1, and an input port if this bit is cleared to 0.

P4DDR is a write-only register. Its value cannot be read. All bits return 1 when read.

P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting.

ABWCR and P4DDR are not initialized in software standby mode. When port 4 functions as a

generic in put/output port, if a P4DDR b it is set to 1, the correspo nding pin maintains its o utput

state in software standby mode.

Rev. 6.0, 09/02, page 272 of 876

Port 4 Data Register (P4DR)

P4DR is an 8-bit readable/writable register that stores output data for pins P47 to P40. Wh ile por t 4

acts as an outpu t por t, th e valu e of th is r e gister is output. When a b it in P4DDR is set to 1, if port 4

is read the value of the corresponding P4DR bit is returned. When a b it in P4DDR is cleared to 0,

if port 4 is read the corresponding pin level is read.

Bit

Initial value

Read/Write

R/W

Port 4 data 7 to 0

These bits store data for port 4 pins

R/W

P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Port 4 Input P ull- Up MOS Control Register ( P 4PCR)

P4PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port

Bit

Initial value

Read/Write

P4 PCR

R/W

Port 4 input pull-up MOS control 7 to 0

These bits control input pull-up MOS transistors built into port 4

P4 PCR

R/W

P4 PCR

R/W

P4 PCR

R/W

P4 PCR

R/W

P4 PCR

R/W

P4 PCR

R/W

P4 PCR

R/W

In mode 7 (single-chip mode), and in 8-bit bus mode in modes 1 to 6 (expanded modes), when a

P4DDR bit is cleared to 0 (selecting generic input), if the corresponding P4PCR bit is set to 1, the

input pull-up MOS transistor is turned on.

P4PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Rev. 6.0, 09/02, page 273 of 876

Table 9.7 summarizes the states of the input pull-ups MOS in the 8-bit and 16-bit bus modes.

Table 9.7 Input Pull-Up MO S Transistor States (Port 4)

Mode Reset Hardware

Standby Mode Software

Standby Mode Other Modes

8-bit bus mode On/off On/off1 to 6 16-bit bus mode Off Off

Off Off

On/off On/off

Legend

Off: The input pull-up MOS transistor is always off.

On/off: The input pull-up MOS transistor is on if P4PCR = 1 and P4DDR = 0. Otherwise, it is off.

Rev. 6.0, 09/02, page 274 of 876

9.6 Port 5

9.6.1 Overview

Port 5 is a 4-bit input/output port with the pin configuration shown in figure 9.5. The pin functions

differ depending on the operating mode.

In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 5 consists of address output

pins (A19 to A16). In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings in the

port 5 data direction register (P5DDR) designate pins for address bus output (A19 to A16) or generic

input. In mode 7 (single-chip mode), port 5 is a generic input/output port.

Port 5 ha s software-program mable built-in pull-up MOS transistor s.

Pins in port 5 can driv e one TTL load and a 90-pF capacitive load. They can also drive an LED or

a darlington transistor pair.

Port 5

P5 /A

A (output)

P5 (input)/A (output)

Port 5

pins Modes 1 to 4 Modes 5 and 6

P5 (input/output)

Mode 7

Figure 9.5 Port 5 Pin Configuration

Rev. 6.0, 09/02, page 275 of 876

9.6.2 Register Descriptions

Table 9.8 summarizes the registers of port 5.

Table 9.8 Port 5 Registers

Initial Value

Address*Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7

H'FFC8 Port 5 data direction

H'FFCA Port 5 data register P5DR R/W H'F0 H'F0

H'FFDB Port 5 input pull-up MOS

control register P5PCR R/W H'F0 H'F0

Note: * Lower 16 bits of the address.

Port 5 Data Direction Register (P5DDR)

P5DDR is an 8-bit write-only register that can select input or ou tput for each pin in port 5.

Bits 7 to 4 are reserved. They cannot be modified and are always read as 1.

Bit

Modes

1 to 4 Initial value

Read/Write

Initial value

Read/Write

Modes

5 to 7

—

P5 DDR

—

P5 DDR

—

P5 DDR

—

P5 DDR

—

Reserved bits Port 5 data direction 3 to 0

These bits select input or

output for port 5 pins

Modes 1 to 4 (Expanded Mo des with On-Chip ROM Disabled): P5DDR values are fixed at 1

and cannot be modified. Port 5 functions as an address bus.

Modes 5 and 6 (Expanded Modes with On-Chip ROM Enabled): Fo llowing a reset, port 5 is

an input port. A pin in port 5 becomes an address output pin if the corresponding P5DDR bit is set

to 1, and an input port if this bit is cleared to 0.

Rev. 6.0, 09/02, page 276 of 876

Mode 7 (Single-Chip Mode): Port 5 functions as an input/output port. A pin in port 5 becomes an

output port if the corresponding P5DDR bit is set to 1, and an input port if this bit is cleared to 0.

In modes 1 to 4, P5DDR always returns 1 when read. No v alue can be written to.

In modes 5 to 7, P5 DDR is a wr ite-only register . I ts value cannot be read. All bits retur n 1 when

read.

P5DDR is initialized to H'FF in mod es 1 to 4 and H'F0 in modes 5 to 7 by a reset and in hard ware

standby mode. In software standby mode it retains its previous setting, so if a P5DDR bit is set to

1 while port 5 acts as an I/O port, the corresponding pin maintains its output state in software

standby mode.

Port 5 Data Register (P5DR)

P5DR is an 8-bit readable/writable register that stores output data for pins P53 to P50. Wh ile por t 5

acts as an outpu t por t, th e valu e of th is r e gister is output. When a b it in P5DDR is set to 1, if port 5

is read the value of the corresponding P5DR bit is returned. When a b it in P5DDR is cleared to 0,

if port 5 is read the corresponding pin level is read.

Bits 7 to 4 are reserved. They cannot be modified and are always read as 1.

Bit

Initial value

Read/Write

—

R/W

Reserved bits These bits store data

for port 5 pins

Port 5 data 3 to 0

P5DR is initialized to H'F0 by a reset and in hardware standby mode. In so f twar e stan dby mode it

retains its previous setting.

Rev. 6.0, 09/02, page 277 of 876

Port 5 Input P ull- Up MOS Control Register ( P 5PCR)

Bit

Initial value

Read/Write

—

P5 PCR

R/W

P5 PCR

R/W

P5 PCR

R/W

P5 PCR

R/W

Reserved bits These bits control input pull-up MOS

transistors built into port 5

Port 5 input pull-up MOS control 3 to 0

P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up MOS transistors

in port 5.

Bits 7 to 4 are reserved. They cannot be modified and are always read as 1.

In modes 5 to 7, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding

bit fro m P53PCR to P50PCR is set to 1, the input p ull-up MOS transistor is turned on.

P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting.

Table 9.9 summarizes the states of the input pull-ups MOS in each mode.

Table 9.9 Input Pull-Up MO S Transistor States (Port 5)

Mode Reset Hardware

Standby Mode Software

Standby Mode Other Modes

1 Off Off Off Off

5 Off Off On/off On/off

Legend

Off: The input pull-up MOS transistor is always off.

On/off: The input pull-up MOS transistor is on if P5PCR = 1 and P5DDR = 0. Otherwise, it is off.

Rev. 6.0, 09/02, page 278 of 876

9.7 Port 6

9.7.1 Overview

Port 6 is a 7-bit input/output port that is also used for input and output of bus control signals

(LWR, HWR, RD, AS, BACK, BREQ, and WAIT). When DRAM is connected to area 3, LWR,

HWR, and RD also function as LW, UW, and CAS, or LCAS, UCAS, and WE, respectively. For

details see section 7, Refresh Controller.

Figure 9.6 shows the pin configuration of port 6. In modes 1 to 6 (expanded modes) the pin

functions are LWR, HWR, RD, AS, P62/BACK, P61/BREQ, and P60/WAIT. See table 9.11 for the

method of selecting the pin states. In mode 7 (single-chip mode) port 6 is a generic input/output

port.

Pins in port 6 can driv e one TTL load and a 30-pF capacitive load. They can also dr ive a

darlington transistor pair.

Port 6

P6 /

Port 6 pins

Modes 1 to 6

(expanded modes)

(output)

(input)

Mode 7

(single-chip mode)

(input/output)

(input/output)/

Figure 9.6 Port 6 Pin Configuration

Rev. 6.0, 09/02, page 279 of 876

9.7.2 Register Descriptions

Table 9.10 summarizes the registers of port 6.

Table 9.10 Port 6 Registers

Initial Value

Address*Name Abbreviation R/W Mode 1 to 5 Mode 6, 7

H'FFC9 Port 6 data direction

H'FFCB Port 6 data register P6DR R/W H'80 H'80

Note: * Lower 16 bits of the address.

Port 6 Data Direction Register (P6DDR)

P6DDR is an 8-bit write-only register that can select input or ou tput for each pin in port 6. Bit 7 is

reserved. It cannot be modified and is always read as 1.

Bit

Initial value

Read/Write

—

P6 DDR

Port 6 data direction 6 to 0

These bits select input or output for port 6 pins

Reserved bit

Modes 1 to 6 (Expanded Modes): Port s P6 6 to P63 function as bus control output pins (LWR,

HWR, RD, AS), regardless of the settings of P66DDR to P63DDR. Ports P62 to P60 function as the

bus control pins (BACK, BREQ, WAIT) or I/O ports. For selecting the pin function, see table

9.11. When ports P62 to P60 function as I/O ports and if P6 DDR is set to 1, the corresponding pin

of port 6 functions as an output port. If P6DDR is cleared to 0, the corresponding pin functions as

an input port.

Mode 7 (Single-Chip Mode): Port 6 is a generic input/output port. A pin in port 6 becomes an

output port if the corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.

P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read.

P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode

it retains its prev ious setting. If a P6 DDR bit is set to 1 while port 6 acts as an I/O port, the

corresponding pin maintains its output state in so ftware standby mode.

Rev. 6.0, 09/02, page 280 of 876

Port 6 Data Register (P6DR)

Bit

Initial value

Read/Write

—

R/W

Reserved bit Port 6 data 6 to 0

These bits store data for port 6 pins

P6DR is an 8-bit readable/writable register that stores output data for pins P66 to P60. Wh en th is

P6DDR is 0. When the corresponding bit of P6DDR is 1, bits 6 to 0 return the P6DR value.

Bit 7 is reserved, cannot be modified, and always read as 1.

P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Rev. 6.0, 09/02, page 281 of 876

Table 9.11 Port 6 Pin Functions in Modes 1 to 6

Pin Pin Functions and Selection Method

P66/LWR Functions as follows regardless of P66DDR

P66DDR 0 1

Pin function LWR output

P65/HWR Functions as follows regardless of P65DDR

P65DDR 0 1

Pin function HWR output

P64/RD Functions as follows regardless of P64DDR

P64DDR 0 1

Pin function RD output

P63/AS Functions as follows regardless of P63DDR

P63DDR 0 1

Pin function AS output

P62/BACK Bit BRLE in BRCR and bit P62DDR select the pin function as follows

BRLE 0 1

P62DDR 0 1 —

Pin function P62 input P62 output BACK output

P61/BREQ Bit BRLE in BRCR and bit P61DDR select the pin function as follows

BRLE 0 1

P61DDR 0 1 —

Pin function P61 input P61 output BREQ input

P60/WAIT Bits WCE7 to WCE0 in WCER, bit WMS1 in WCR, and bit P60DDR select the

pin function as follows

WCER All 1s Not all 1s

WMS1 0 1 —

P60DDR 0 1 0*0*

Pin function P60 input P6 0 output WAIT input

Note: * Do not set bit P60DDR to 1.

Rev. 6.0, 09/02, page 282 of 876

9.8 Port 7

9.8.1 Overview

Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog

output from the D/A converter. The pin functions are the same in all operating modes. Figure 9.7

shows the pin configuration of port 7.

For the analog input pins of the A/D converter, see section 15, A/D Converter.

For the analog input pins of the D/A converter, see section 16, D/A Converter.

Port 7

P7 (input)/AN (input)/DA (output)

P7 (input)/AN (input)

Port 7 pins

Figure 9.7 Port 7 Pin Configuration

Rev. 6.0, 09/02, page 283 of 876

9.8.2 Register Description

Table 9.12 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction

Table 9.12 Port 7 Data Register

Address*Name Abbreviation R/W Initial Value

H'FFCE Port 7 data register P7DR R Undetermined

Note: * Lower 16 bits of the address.

Port 7 Data Register (P7DR)

Bit

Initial value

Read/Write

—

Note: *

—

Determined by pins P7 to P7 .

When P7DR is read, the logic level of the pin is always read. No data can b e written to.

Rev. 6.0, 09/02, page 284 of 876

9.9 Port 8

9.9.1 Overview

Port 8 is a 5-bit input/output port that is also used for CS3 to CS0 output, RFSH output, and IRQ3 to

IRQ0 input. Figure 9.8 shows th e pin configuration of port 8.

In modes 1 to 6 (expanded modes), port 8 can provide CS3 to CS0 output, RFSH output, and IRQ3

to IRQ0 input. See table 9.14 for the selection of pin functions in expanded modes.

In mode 7 (single-chip mode), port 8 can provide IRQ3 to IRQ0 input. See table 9.15 for the

selection of pin functions in single-chip mode.

The IRQ3 to IRQ0 functions are selected by IER settings, regardless of whether the pin is used for

input or output. For details see section 5, Interrupt Controller.

Pins in port 8 can driv e one TTL load and a 90-pF capacitive load. They can also dr ive a

darlington transistor pair.

Pins P82 to P80 ha ve Schmitt-trigger inputs.

Port 8

P8 /

P8 / /

Port 8 pins

P8 (input)/ (output)

P8 (input)/ (output)/ (input)

P8 (input/output)/ (output)/ (input)

Pin functions in modes 1 to 6

(expanded modes)

P8 /(input/output)

P8 /(input/output)/ (input)

Pin functions in mode 7

(single-chip mode)

Figure 9.8 Port 8 Pin Configuration

Rev. 6.0, 09/02, page 285 of 876

9.9.2 Register Descriptions

Table 9.13 summarizes the registers of port 8.

Table 9.13 Port 8 Registers

Initial Value

Address*Name Abbreviation R/W Mode 1 to 4 Mode 5 to 7

H'FFCD Port 8 data direction

H'FFCF Port 8 data register P8DR R/W H'E0 H'E0

Note: * Lower 16 bits of the address.

Port 8 Data Direction Register (P8DDR)

P8DDR is an 8-bit write-only register that can select input or ou tput for each pin in port 8.

Bits 7 to 5 are reserved. They cannot be modified and are always read as 1.

—

P8 DDR

Reserved bits Port 8 data direction 4 to 0

These bits select input or

output for port 8 pins

Bit

Modes

1 to 4 Initial value

Read/Write

Initial value

Read/Write

Modes

5 to 7

Modes 1 to 6 (Expanded Modes): When bits in P8DDR bit are set to 1, P84 to P81 become CS0 to

CS3 output pins. Wh en bits in P8DDR are cleared to 0, the corresponding pins become input ports.

In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset only CS0 is

output. The other three pins are input ports. In modes 5 and 6 (expanded modes with on-chip

ROM enabled), follo wing a reset all four pins are input ports.

When the refresh controller is enabled, P80 is used unconditionally for RFSH output. When the

refresh controller is disabled, P80 becomes a generic input/output port accord ing to the P8DDR

setting. For details see table 9.15.

Rev. 6.0, 09/02, page 286 of 876

Mode 7 (Single-Chip Mode): Port 8 is a generic input/output port. A pin in port 8 becomes an

output port if the corresponding P8DDR bit is set to 1, and an input port if this bit is cleared to 0.

P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.

P8DDR is initialized to H'F0 in modes 1 to 4 and H'E0 in modes 5 to 7 by a reset and in ha r dware

standby mode. In software standby mode it retains its previous setting, so if a P8DDR bit is set to

1 while port 8 acts as an I/O port, the corresponding pin maintains its output state in software

standby mode.

Port 8 Data Register (P8DR)

P8DR is an 8-bit readable/writable register that stores output data for pins P84 to P80. Wh ile por t 8

acts as an outpu t por t, th e valu e of th is r e gister is output. When a b it in P8DDR is set to 1, if port 8

is read the value of the corresponding P8DR bit is returned. When a b it in P8DDR is cleared to 0,

if port 8 is read the corresponding pin level is read.

Bits 7 to 5 are reserved. They cannot be modified and always are read as 1.

Bit

Initial value

Read/Write

—

R/W

Reserved bits Port 8 data 4 to 0

These bits store data

for port 8 pins

P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Rev. 6.0, 09/02, page 287 of 876

Table 9.14 Port 8 Pin Functions in Modes 1 to 6

Pin Pin Functions and Selection Method

P84/CS0Bit P84DDR selects the pin function as follows

P84DDR 0 1

Pin function P84 input CS0 output

P83/CS1/IRQ3Bit P83DDR selects the pin function as follows

P83DDR 0 1

P83 input CS1 outputPin function

IRQ3 input

P82/CS2/IRQ2Bit P82DDR selects the pin function as follows

P82DDR 0 1

P82 input CS2 outputPin function

IRQ2 input

P81/CS3/IRQ1Bit P81DDR selects the pin function as follows

P81DDR 0 1

P81 input CS3 outputPin function

IRQ1 input

P80/RFSH/IRQ0Bit RFSHE in RFSHCR and bit P80DDR select the pin function as follows

RFSHE 0 1

P80DDR 0 1 —

P80 input P80 output RFSH outputPin function

IRQ0 input

Rev. 6.0, 09/02, page 288 of 876

Table 9.15 Port 8 Pin Functions in Mode 7

Pin Pin Functions and Selection Method

P84Bit P84DDR selects the pin function as follows

P84DDR 0 1

Pin function P84 input P84 output

P83/IRQ3Bit P83DDR selects the pin function as follows

P83DDR 0 1

P83 input P83 outputPin function

IRQ3 input

P82/IRQ2Bit P82DDR selects the pin function as follows

P82DDR 0 1

P82 input P82 outputPin function

IRQ2 input

P81/IRQ1Bit P81DDR selects the pin function as follows

P81DDR 0 1

P81 input P81 outputPin function

IRQ1 input

P80/IRQ0Bit P80DDR select the pin function as follows

P80DDR 0 1

P80 input P80 outputPin function

IRQ0 input

Rev. 6.0, 09/02, page 289 of 876

9.10 Port 9

9.10.1 Overview

Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1,

SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5

and IRQ4 input. See table 9.17 for the selection of pin functions.

The IRQ5 and IRQ4 functions are selected by IER settings, regardless of whether the pin is used for

input or output. For details see section 5, Interrupt Controller.

Port 9 has the same set of pin functions in all operating modes. Figure 9.9 shows the pin

configuration of port 9.

Pins in port 9 can driv e one TTL load and a 30-pF capacitive load. They can also dr ive a

darlington transistor pair.

Port 9

P9 (input/output)/SCK

P9 (input/output)/RxD (input)

P9 (input/output)/TxD (output)

Port 9 pins

(input/output)/ (input)

Figure 9.9 Port 9 Pin Configuration

Rev. 6.0, 09/02, page 290 of 876

9.10.2 Register Descriptions

Table 9.16 summarizes the registers of port 9.

Table 9.16 Port 9 Registers

Address*Name Abbreviation R/W Initial Value

H'FFD0 Port 9 data direction register P9DDR W H'C0

H'FFD2 Port 9 data register P9DR R/W H'C0

Note: * Lower 16 bits of the address.

Port 9 Data Direction Register (P9DDR)

P9DDR is an 8-bit write-only register that can select input or ou tput for each pin in port 9.

Bits 7 and 6 are reserved. They cannot be modified and are always read as 1.

Bit

Initial value

Read/Write

—

P9 DDR

Reserved bits Port 9 data direction 5 to 0

These bits select input or

output for port 9 pins

While port 9 acts as an I/O port, a pin in port 9 becomes an output port if the corresponding

P9DDR bit is se t to 1, and an input port if this bit is cleared to 0. For selecting the pin function, see

table 9.17.

P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read.

P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting. If a P9DDR bit is set to 1 while p ort 9 acts as an I/O port, the

corresponding pin maintains its output state in so ftware standby mode.

Rev. 6.0, 09/02, page 291 of 876

Port 9 Data Register (P9DR)

P9DR is an 8-bit readable/writable register that stores output data for pins P95 to P90. Wh ile por t 9

acts as an outpu t por t, the value of this register is ou tp ut. When a bit in P9DDR is set to 1 , if port 9

is read the value of the co rresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0,

if port 9 is read the corresponding pin level is read.

Bit

Initial value

Read/Write

—

R/W

Reserved bits Port 9 data 5 to 0

These bits store data

for port 9 pins

Bits 7 and 6 are reserved. They cannot be modified and are always read as 1.

P9DR is initia lized to H'C0 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Rev. 6.0, 09/02, page 292 of 876

Table 9.17 Port 9 Pin Functions

Pin Pin Functions and Selection Method

P95/SCK1/IRQ5Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P95DDR

select the pin function as follows

CKE1 0 1

C/A01—

CKE0 0 1 — —

P95DDR 0 1 — — —

P95

input P95

output SCK1

input

Pin function

IRQ5 input

P94/SCK0/IRQ4Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI0, and bit P94DDR

select the pin function as follows

CKE1 0 1

C/A01—

CKE0 0 1 — —

P94DDR 0 1 — — —

P94

input P94

output SCK0

input

Pin function

IRQ4 input

P93/RxD1Bit RE in SCR of SCI1 and bit P93DDR select the pin function as follows

RE 0 1

P93DDR 0 1 —

Pin function P93 input P93 output RxD1 input

P92/RxD0Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin

function as follow s

SMIF 0 1

RE 0 1 —

P92DDR 0 1 — —

Pin function P92 input P9 2 output RxD0 input RxD0 input

Rev. 6.0, 09/02, page 293 of 876

Pin Pin Functions and Selection Method

P91/TxD1Bit TE in SCR of SCI1 and bit P91DDR select the pin function as follows

TE 0 1

P91DDR 0 1 —

Pin function P91 input P91 output TxD1 output

P90/TxD0Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin

function as follow s

SMIF 0 1

TE 0 1 —

P90DDR 0 1 — —

Pin function P90 input P9 0 output TxD0 output TxD0 output*

Note: *Functions as the TxD0 output pin, but there are two states: one in which

the pin is driven, and another in which the pin is at high-impedance.

Rev. 6.0, 09/02, page 294 of 876

9.11 Port A

9.11.1 Overview

Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the programmable

timing pattern controller (TPC), input and output (TIOCB2, TIOCA2, TIOCB1, TIOCA1, TIOCB0,

TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timer unit (ITU), output

(TEND1, TEND0) from the DMA controller (DMAC), CS4 to CS6 output, and address output (A23

to A20). A reset or hardware standby leaves port A as an input port, except that in modes 3, 4, and

6, one pin is always used for A20 output. For selecting the pin function, see table 9.19. Usage of

pins for TPC, ITU, and DMAC input and output is described in the sections on those modules. For

output of address bits A23 to A21 in modes 3, 4, and 6, see section 6.2.5, Bus Release Control

Pins not assigned to any of these functions are available for generic input/output. Figure 9.10

shows the pin configuration of port A.

Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a

darlington transistor pair. Port A has Schmitt-trigger inputs.

Rev. 6.0, 09/02, page 295 of 876

Port A

PA /TP /TIOCB /A

PA /TP /TIOCA /A

PA /TP /TIOCB /A

PA /TP /TIOCA /A

PA /TP /TIOCB /TCLKD

PA /TP /TIOCA /TCLKC

PA /TP / /TCLKB

PA /TP / /TCLKA

Port A pins

PA (input/output)/TP (output)/TIOCB (input/output)

PA (input/output)/TP (output)/TIOCA (input/output)/

(output)

PA (input/output)/TP (output)/TIOCB (input/output)/

(output)

PA (input/output)/TP (output)/TIOCA (input/output)/

(output)

Pin functions in modes 1, 2, and 5

PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)

PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)

PA (input/output)/TP (output)/ (output)/TCLKB (input)

PA (input/output)/TP (output)/ (output)/TCLKA (input)

Pin functions in mode 7

(output)

PA (input/output)/TP (output)/TIOCA (input/output)/A (output)/

(output)

PA (input/output)/TP (output)/TIOCB (input/output)/A (output)/

(output)

PA (input/output)/TP (output)/TIOCA (input/output)/A (output)/

(output)

Pin functions in modes 3, 4, and 6

PA (input/output)/TP (output)/ (output)/TCLKA (input)

PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)

PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)

PA (input/output)/TP (output)/ (output)/TCLKB (input)

(input/output)/TP

(output)/TIOCB

(input/output)

(input/output)/TP

(output)/TIOCA

(input/output)

(input/output)/TP

(output)/TIOCB

(input/output)

(input/output)/TP

(output)/TIOCA

(input/output)

(input/output)/TP

(output)/TIOCB

(input/output)/TCLKD (input)

(input/output)/TP

(output)/TIOCA

(input/output)/TCLKC (input)

(input/output)/TP

(output)/

(output)/TCLKB (input)

(input/output)/TP

(output)/

(output)/TCLKA (input)

Figure 9.10 Port A Pin Configuration

Rev. 6.0, 09/02, page 296 of 876

9.11.2 Register Descriptions

Table 9.18 summarizes the registers of port A.

Table 9.18 Port A Registers

Initial Value

Address*Name Abbreviation R/W Modes

1, 2, 5, and 7 Modes

3, 4, and 6

H'FFD1 Port A data direction

H'FFD3 Port A data register PADR R/W H'00 H'00

Note: * Lower 16 bits of the address.

Port A Data Direction Register (PADDR)

PADDR is an 8-bit write-only register that can select input or output for each pin in port A. When

pins are used for TPC output, the corresponding PADDR bits must also be set.

PA DDR

—

Port A data direction 7 to 0

These bits select input or output for port A pins

PA DDR

Bit

Modes

3, 4,

and 6 Initial value

Read/Write

Initial value

Read/Write

Modes

1, 2, 5,

and 7

While port A acts as an I/O port, a pin in port A becomes an ou tput pin if the corresponding

PADDR bit is set to 1, and an input pin if this bit is cleared to 0. In modes 3, 4, and 6, PA7DDR is

fixed at 1 and PA7 functions as an address output pin.

PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.

PADDR is initialized to H'0 0 by a reset and in hardware standby mode in mod es 1, 2, 5, and 7.

It is initialized to H'80 by a reset and in hardware standby mode in modes 3, 4, and 6. In software

standby mode it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin

maintains its output state in software standby mode.

Rev. 6.0, 09/02, page 297 of 876

Port A Data Register (PADR)

PADR is an 8-bit readable/writable register that stores output data for pins PA7 to PA0. While port

A acts as an outpu t port, th e value of this register is output. When a bit in PADDR is set to 1 , if

port A is read the value of th e correspondin g PADR bit is return ed. When a bit in PADDR is

cleared to 0, if port A is read the corresponding pin level is read.

Bit

Initial value

Read/Write

R/W

Port A data 7 to 0

These bits store data for port A pins

PADR is initialized to H'00 by a reset and in hard war e standby mode. In software standby mod e it

retains its previous setting.

Rev. 6.0, 09/02, page 298 of 876

9.11.3 Pin Functions

Table 9.19 describes the selection of pin functions.

Table 9.19 Port A Pin Functions

Pin Pin Functions and Selection Method

PA7/TP7/

TIOCB2/A20

The mode setting, ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to IOB0 in

TIOR2), bit NDER7 in NDERA, and bit PA7DDR in PADDR select the pin function as

follows

Mode 1, 2, 5, 7 3, 4, 6

ITU

channel 2

settings (1) in table

below (2) in table below —

PA7DDR — 0 1 1 —

NDER7 — — 0 1 —

PA7 input PA7 output TP7 outputPin function TIOCB2

output TIOCB2 input*

A20 output

Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0.

ITU

channel 2

settings (2) (1) (2)

IOB2 0 1

IOB1 001—

IOB0 0 1 — —

Rev. 6.0, 09/02, page 299 of 876

Pin Pin Functions and Selection Method

PA6/TP6/

TIOCA2/

A21/CS4

The mode setting, bit A21E in BRCR, bit CS4E in CSCR, ITU channel 2 settings (bit

PWM2 in TMDR and bits IOA2 to IOA0 in TIOR2), bit NDER6 in NDERA, and bit

PA6DDR in PADDR select the pin function as follows

Mode 1, 2, 5 3, 4, 6 7

CS4E 0 1 0 1 —

A21E——10——

ITU

channel 2

settings

(1) in

table

below

(2) in table

below —(1) in

table

below

(2) in table

below ——(1) in

table

below

(2) in table

below

PA6DDR — 011——011——— 011

NDER6 — — 0 1 — — — 0 1 — — — — 0 1

PA6

input PA6

out-

put

TP6

out-

put

PA6

input PA6

out-

put

TP6

out-

put

PA6

input PA6

out-

put

TP6

out-

put

function TIOCA2

output

TIOCA2 input*

CS4

out-

put

TIOCA2

output

TIOCA2 input*

A21

out-

put

CS4

out-

put

TIOCA2

output

TIOCA2 input*

Note: * TIOCA2 input when IOA2 = 1.

ITU

channel 2

settings (2) (1) (2) (1)

PWM2 0 1

IOA2 0 1 —

IOA1 0 0 1 — —

IOA0 0 1 — — —

Rev. 6.0, 09/02, page 300 of 876

Pin Pin Functions and Selection Method

PA5/TP5/

TIOCB1/

A22/CS5

The mode setting, bit A22E in BRCR, bit CS5E in CSCR, ITU channel 1 settings (bit

PWM1 in TMDR and bits IOB2 to IOB0 in TIOR1), bit NDER5 in NDERA, and bit

PA5DDR in PADDR select the pin function as follows

Mode 1, 2, 5 3, 4, 6 7

CS5E 0 1 0 1 —

A22E——10——

ITU

channel 1

settings

(1) in

table

below

(2) in table

below —(1) in

table

below

(2) in table

below ——(1) in

table

below

(2) in table

below

PA5DDR — 011——011——— 011

NDER5 — — 0 1 — — — 0 1 — — — — 0 1

PA5

input PA5

out-

put

TP5

out-

put

PA5

input PA5

out-

put

TP5

out-

put

PA5

input PA5

out-

put

TP5

out-

put

function TIOCB1

output

TIOCB1 input*

CS5

out-

put

TIOCB1

output

TIOCB1 input*

A22

out-

put

CS5

out-

put

TIOCB1

output

TIOCB1 input*

Note: * TIOCB1 input when IOB2 = 1 and PWM1 = 0.

ITU

channel 1

settings (2) (1) (2)

IOB2 0 1

IOB1 0 0 1 —

IOB0 0 1 — —

Rev. 6.0, 09/02, page 301 of 876

Pin Pin Functions and Selection Method

PA4/TP4/

TIOCA1/

A23/CS6

The mode setting, bit A23E in BRCR, bit CS6E in CSCR, ITU channel 1 settings (bit

PWM1 in TMDR and bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit

PA4DDR in PADDR select the pin function as follows

Mode 1, 2, 5 3, 4, 6 7

CS6E 0 1 0 1 —

A23E——10——

ITU

channel 2

settings

(1) in

table

below

(2) in table

below —(1) in

table

below

(2) in table

below ——(1) in

table

below

(2) in table

below

PA4DDR — 011——011——— 011

NDER4——01———01————01

PA4

input PA4

out-

put

TP4

out-

put

PA4

input PA4

out-

put

TP4

out-

put

PA4

input PA4

out-

put

TP4

out-

put

function TIOCA1

output

TIOCA1 input*

CS6

out-

put

TIOCA1

output

TIOCA1 input*

A23

out-

put

CS6

out-

put

TIOCA1

output

TIOCA1 input*

Note: * TIOCA1 input when IOA2 = 1.

ITU

channel 1

settings (2) (1) (2) (1)

PWM1 0 1

IOA2 0 1 —

IOA1 0 0 1 — —

IOA0 0 1 — — —

Rev. 6.0, 09/02, page 302 of 876

Pin Pin Functions and Selection Method

PA3/TP3/

TIOCB0/

TCLKD

ITU channel 0 settings (bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0), bits

TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER3 in NDERA, and bit PA3DDR in PADDR

select the pin function as follows

ITU channel 0

settings (1) in table

below (2) in table

below

PA3DDR — 0 1 1

NDER3 — — 0 1

PA3 input PA3 output TP3 outputTIOCB0 output TIOCB0 input*1

Pin function

TCLKD input*2

Notes: *1TIOCB

0 input when IOB2 = 1 and PWM0 = 0.

*2 TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of TCR4 to TCR0.

ITU channel 0

settings (2) (1) (2)

IOB2 0 1

IOB1 0 0 1 —

IOB0 0 1 — —

PA2/TP2/

TIOCA0/

TCLKC

ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits

TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA2DDR in PADDR

select the pin function as follows

ITU channel 0

settings (1) in table

below (2) in table

below

PA2DDR — 0 1 1

NDER2 — — 0 1

PA2 input PA2 output TP2 outputIOCA0 output TIOCA0 input*1

Pin function

TCLKC input*2

Notes: *1TIOCA

0 input when IOA2 = 1.

*2 TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of TCR4 to

TCR0.

ITU channel 0

settings (2) (1) (2) (1)

PWM0 0 1

IOA2 0 1 —

IOA1 001——

IOA0 0 1 ———

Rev. 6.0, 09/02, page 303 of 876

Pin Pin Functions and Selection Method

DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and DTCR1B),

bit NDER1 in NDERA, and bit PA1DDR in PADDR select the pin function as follows

PA1/TP1/

TCLKB/

TEND1DMAC

channel 1

settings

(1) in table

below (2) in table

below

PA1DDR — 0 1 1

NDER1 — — 0 1

TEND1 output PA1 input PA1 output TP1 outputPin function TCLKB input*

Note: *TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and

TPSC0 = 1 in any of TCR4 to TCR0.

DMAC

channel 1

settings (2) (1) (2) (1) (2) (1)

DTS2A,

DTS1A Not both 1 Both 1

DTS0A — 00111

DTS2B 01101011

DTS1B — 0 1 ——— 0 1

DMAC channel 0 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR0A and DTCR0B),

bit NDER0 in NDERA, and bit PA0DDR in PADDR select the pin function as follows

PA0/TP0/

TCLKA/

TEND0DMAC

channel 0

settings

(1) in table

below (2) in table

below

PA0DDR — 0 1 1

NDER0 — — 0 1

TEND0 output PA0 input PA0 output TP0 outputPin function TCLKA input*

Note: *TCLKA input when MDF = 1 in TMDR, or when TPSC2 = 1 and TPSC1 = 0 in

any of TCR4 to TCR0.

DMAC

channel 0

settings (2) (1) (2) (1) (2) (1)

DTS2A,

DTS1A Not both 1 Both 1

DTS0A — 00111

DTS2B 01101011

DTS1B — 0 1 ——— 0 1

Rev. 6.0, 09/02, page 304 of 876

9.12 Port B

9.12.1 Overview

Port B is an 8-bit input/output port that is also used for output (TP15 to TP8) from the

programmable timing pattern controller (TPC), input/output (TIOCB4, TIOCB3, TIOCA4, TIOCA3)

and output (TOCXB4, TOCXA4) by the 16-bit integrated timer unit (ITU), input (DREQ1, DREQ0)

to the DMA controller (DMAC), ADTRG input to the A/D converter, and CS7 output. A reset or

hardware standby leaves port B as an input port. For selecting the pin function, see table 9.21.

Usage of pins for TPC, ITU, DMAC, and A/D converter input and output is described in the

sections on those modules. For output of CS7 in modes 1 to 6, see section 6.3.2, Chip Select

Signals. Pins not assigned to any of these functions are available for generic input/output. Figure

9.11 shows the pin configuration of port B.

Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive an LED or

darlington transistor pair. Pins PB3 to PB0 have Schmitt-trigger inpu ts.

Rev. 6.0, 09/02, page 305 of 876

Port B

/TP

/TOCXB

/TP

/TOCXA

/TP

/TIOCB

/TP

/TIOCA

/TP

/TIOCB

/TP

/TIOCA

Port B pins

(input/output)/TP

(output)/

(input)/ (input)

(input/output)/TP

(output)/

(input)/

(output)

(input/output)/TP

(output)/TOCXB

(output)

(input/output)/TP

(output)/TOCXA

(output)

(input/output)/TP

(output)/TIOCB

(input/output)

(input/output)/TP

(output)/TIOCA

(input/output)

(input/output)/TP

(output)/TIOCB

(input/output)

(input/output)/TP

(output)/TIOCA

(input/output)

Pin functions in modes 1 to 6

(input/output)/TP

(output)/

(input)/ (input)

(input/output)/TP

(output)/

(input)

(input/output)/TP

(output)/TOCXB

(output)

(input/output)/TP

(output)/TOCXA

(output)

(input/output)/TP

(output)/TIOCB

(input/output)

(input/output)/TP

(output)/TIOCA

(input/output)

(input/output)/TP

(output)/TIOCB

(input/output)

(input/output)/TP

(output)/TIOCA

(input/output)

Pin functions in mode 7

Figure 9.11 Port B Pin Configuration

Rev. 6.0, 09/02, page 306 of 876

9.12.2 Register Descriptions

Table 9.20 summarizes the registers of port B.

Table 9.20 Port B Registers

Address*Name Abbreviation R/W Initial Value

H'FFD4 Port B data direction register PBDDR W H'00

H'FFD6 Port B data register PBDR R/W H'00

Note: * Lower 16 bits of the address.

Port B Data Direction Register (PBDDR)

PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. When

pins are used for TPC output, the corresponding PBDDR bits must also be set.

Bit

Initial value

Read/Write

PB DDR

Port B data direction 7 to 0

These bits select input or output for port B pins

PB DDR

While port B acts as an I/O port, a pin in port B becomes an output pin if the corresponding

PBDDR bit is set to 1, and an in put pin if this bit is cleared to 0.

PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.

PBDDR is initialized to H'00 b y a reset and in hardware standby mode . I n sof tware standby mode

it retains its previous setting. If a PBDDR bit is set to 1 while p ort B acts as an I/O por t, the

corresponding pin maintains its output state in so ftware standby mode.

Rev. 6.0, 09/02, page 307 of 876

Port B Data Register (PBDR)

PBDR is an 8-bit readable/writable register that stores output data for pins PB7 to PB0. While port

B acts as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if

port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is

cleared to 0, if port B is read the corresponding pin level is read.

Bit

Initial value

Read/Write

R/W

Port B data 7 to 0

These bits store data for port B pins

PBDR is initialized to H'00 by a reset and in h ardwar e standby mode. In software stand by mode it

retains its previous setting.

Rev. 6.0, 09/02, page 308 of 876

9.12.3 Pin Functions

Table 9.21 describes the selection of pin functions.

Table 9.21 Port B Pin Functions

Pin Pin Functions and Selection Method

DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and DTCR1B),

bit TRGE in ADCR, bit NDER15 in NDERB, and bit PB7DDR in PBDDR select the pin

function as follow s

PB7/TP15/

DREQ1/

ADTRG

PB7DDR 0 1 1

NDER15 — 0 1

PB7 input PB7 output TP15 output

DREQ1 input*1

Pin function

ADTRG input*2

Notes: *1DREQ1 input under DMAC channel 1 settings (1) in the table below.

*2ADTRG input when TRGE = 1.

DMAC

channel

1 settings (2) (1) (2) (1) (2) (1)

DTS2A, DTS1A Not both 1 Both 1

DTS0A — 00111

DTS2B 01101011

DTS1B — 0 1 — — — 0 1

Rev. 6.0, 09/02, page 309 of 876

Pin Pin Functions and Selection Method

Bit CS7E in CSCR, DMAC channel 0 settings (bits DTS2/1/0A and DTS2/1/0B in

DTCR0A and DTCR0B), bit NDER14 in NDERB, and bit PB6DDR in PBDDR select the

pin function as follows

PB6/TP14/

DREQ0/

CS7PB6DDR 0 1 1 —

CS7E 0001

NDER14 — 0 1 —

PB6 input PB6 output TP14 output —Pin function

DREQ0 input*CS7 output

Note: * DREQ0 input under DMAC channel 0 settings (1) in the table below.

DMAC

channel 0

settings (2) (1) (2) (1) (2) (1)

DTS2A, DTS1A Not both 1 Both 1

DTS0A — 00111

DTS2B 01101011

DTS1B — 0 1 — — — 0 1

ITU channel 4 settings (bit CMD1 in TFCR and bit EXB4 in TOER), bit NDER13 in

NDERB, and bit PB5DDR in PBDDR select the pin function as follows

PB5/TP13/

TOCXB4EXB4, CMD1 Not both 1 Both 1

PB5DDR 0 1 1 —

NDER13 — 0 1 —

Pin function PB5 input PB5 output TP13 output TOCXB4 output

PB4/TP12/

TOCXA4

ITU channel 4 settings (bit CMD1 in TFCR and bit EXA4 in TOER), bit NDER12 in

NDERB, and bit PB4DDR in PBDDR select the pin function as follows

EXA4, CMD1 Not both 1 Both 1

PB4DDR 0 1 1 —

NDER12 — 0 1 —

Pin function PB4 input PB4 output TP12 output TOCXA4 output

Rev. 6.0, 09/02, page 310 of 876

Pin Pin Functions and Selection Method

ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and

bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB

DDR in PBDDR select

the pin function as follows

PB3/TP11/

TIOCB4

ITU channel 4

settings (1) in table

below (2) in table

below

PB3DDR — 0 1 1

NDER11 — — 0 1

PB3 input PB3 output TP11 outputPin function TIOCB4 output TIOCB4 input*

Note: * TIOCB4 input when CMD1 = PWM4 = 0 and IOB2 = 1.

ITU channel 4

settings (2) (2) (1) (2) (1)

EB4 0 1

CMD1 — 0 1

IOB2 —0001—

IOB1 —001——

IOB0 — 0 1 — — —

ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and

bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB

DDR in PBDDR select

the pin function as follows

PB2/TP10/

TIOCA4

ITU channel 4

settings (1) in table

below (2) in table

below

PB2DDR — 0 1 1

NDER10 — — 0 1

PB2 input PB2 output TP10 outputPin function TIOCA4 output TIOCA4 input*

Note: * TIOCA4 input when CMD1 = PWM4 = 0 and IOA2 = 1.

ITU channel 4

settings (2) (2) (1) (2) (1)

EA4 0 1

CMD1 — 0 1

PWM4 — 0 1 —

IOA2 —0001——

IOA1 — 0 0 1 — — —

IOA0 — 0 1 — — — —

Rev. 6.0, 09/02, page 311 of 876

Pin Pin Functions and Selection Method

ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and

bits IOB2 to IOB0 in TIOR3), bit NDER9 in NDERB, and bit PB1DDR in PBDDR select

the pin function as follows

PB1/TP9/

TIOCB3

ITU channel 3

settings (1) in table

below (2) in table

below

PB1DDR — 0 1 1

NDER9 — — 0 1

PB1 input PB1 output TP9 outputPin function TIOCB3 output TIOCB3 input*

Note: * TIOCB3 input when CMD1 = PWM3 = 0 and IOB2 = 1.

ITU channel 3

settings (2) (2) (1) (2) (1)

EB3 0 1

CMD1 — 0 1

IOB2 —0001—

IOB1 —001——

IOB0 — 0 1 — — —

ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and

bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB0DDR in PBDDR select

the pin function as follows

PB0/TP8/

TIOCA3

ITU channel 3

settings (1) in table

below (2) in table

below

PB0DDR — 0 1 1

NDER8 — — 0 1

PB0 input PB0 output TP8 outputPin function TIOCA3 output TIOCA3 input*

Note: * TIOCA3 input when CMD1 = PWM3 = 0 and IOA2 = 1.

ITU channel 3

settings (2) (2) (1) (2) (1)

EA3 0 1

CMD1 — 0 1

PWM3 — 0 1 —

IOA2 —0001——

IOA1 — 0 0 1 — — —

IOA0 — 0 1 — — — —

Rev. 6.0, 09/02, page 312 of 876

Rev. 6.0, 09/02, page 313 of 876

Section 10 16-Bit Integrated Timer Unit (ITU)

10.1 Overview

The H8/3048 Ser ies has a built-in 16-bit integ r ated timer unit (ITU) with five 16-bit tim er

channels.

When the ITU is not used, it can be independently halted to conserve power. For details see

section 21.6, Module Standby Function.

10.1.1 Features

ITU features are listed below.

• Capability to process up to 12 pulse outputs or 10 pulse inputs

• Ten general registers (GRs, two per channel) with independently-assignable output comp are or

input capture functions

• Selection of eight counter clock sources for each channel:

Internal clocks: φ, φ/2, φ/4, φ/8

External clocks: TCLKA, TCLKB, TCLKC, TCLKD

• Five operating modes selectable in all channels:

 Waveform output by compare match

Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)

 Input capture function

Rising edge, falling edge, or both edges (selectable)

 Counter clearing function

Counters can be cleared by compare match or input capture

 Synchronization

Two or more timer counters (TCNTs) can be preset simultaneously, or cleared

simultaneously by compare match or input capture. Counter synchron ization enables

synchronous register input and output.

 PWM mode

PWM output can be provided with an arbitrary duty cycle. With synchronization, up to

five-phase PWM output is possible

• Phase counting mode selectable in channel 2

Two-phase encoder output can be counted automatically.

Rev. 6.0, 09/02, page 314 of 876

• Three additional modes selectable in channels 3 and 4

 Reset-synchronized PWM mode

If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of

complementary waveforms.

 Complementary PWM mode

If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of

non-overlapping complementary waveforms.

 Buffering

Input capture registers can be double-buffered. Output compare registers can be updated

automatically.

• High-speed access via internal 16-bit bus

The 16-bit timer counters, general registers, and buffer registers can be accessed at high sp eed

via a 16-bit bus.

• Fifteen interrupt sources

Each channel has two compare match/input capture interrupts and an overflow interrupt. All

interrupts can be requested independently.

• Activation of DMA controller (DMAC)

Four of the compare match/input capture interrupts from channels 0 to 3 can start the DMAC.

• Output triggering of programmable timing pattern controller (TPC)

Compare match/input capture signals from channels 0 to 3 can be used as TPC output triggers.

Rev. 6.0, 09/02, page 315 of 876

Table 10.1 summarizes the ITU functions.

Table 10.1 ITU Functions

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4

Clock s ources Internal cl ocks: φ, φ/2, φ/4, φ/8

External clocks : TCLKA, TCLKB, TCLKC, TCLKD, selectabl e independently

General regist ers

(output compare/input

capture regist ers)

GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4

Buffer registers———BRA3, BRB3BRA4, BRB4

Input/output pi ns TIOCA0,

TIOCB0

TIOCA1,

TIOCB1

TIOCA2,

TIOCB2

TIOCA3,

TIOCB3

TIOCA4,

TIOCB4

Output pins ————TOCXA4,

TOCXB4

Counter cleari ng funct i on GRA0/GRB0

compare

match or

input capture

GRA1/GRB1

compare

match or

input capture

GRA2/GRB2

compare

match or

input capture

GRA3/GRB3

compare

match or

input capture

GRA4/GRB4

compare

match or

input capture

0OOOOO

1OOOOO

Compare match

output

Toggle O O — O O

Input capture function OOOOO

SynchronizationOOOOO

PWM mode OOOOO

Reset-synchronized

PWM mode ———O O

Complementary PWM

mode ———O O

Phase counting mode — — O — —

Buffering ———O O

DMAC activation GRA0 compare

match or input

capture

GRA1 compare

match or input

capture

GRA2 compare

match or input

capture

GRA3 compare

match or input

capture

—

Interrupt sources Three sources

• Compare

match/input

capture A0

• Compare

match/input

capture B0

• Overflow

Three sources

• Compare

match/input

capture A1

• Compare

match/input

capture B1

• Overflow

Three sources

• Compare

match/input

capture A2

• Compare

match/input

capture B2

• Overflow

Three sources

• Compare

match/input

capture A3

• Compare

match/input

capture B3

• Overflow

Three sources

• Compare

match/input

capture A4

• Compare

match/input

capture B4

• Overflow

Legend

O: Available

—: Not available

Rev. 6.0, 09/02, page 316 of 876

10.1.2 Block Diagrams

ITU Block Diagram (Overall): Figure 10.1 is a block diagram of the ITU.

16-bit timer channel 4

16-bit timer channel 3

16-bit timer channel 2

16-bit timer channel 1

16-bit timer channel 0

Module data bus

Bus interface

Internal data bus

IMIA0 to IMIA4

IMIB0 to IMIB4

OVI0 to OVI4

TCLKA to TCLKD

φ, φ/2, φ/4, φ/8

TOCXA4, TOCXB4

Clock selector

Control logic

TIOCA0 to TIOCA4

TIOCB0 to TIOCB4

TOER

TOCR

TSTR

TSNC

TMDR

TFCR

TOER:

TOCR:

TSTR:

TSNC:

TMDR:

TFCR:

Legend Timer output master enable register (8 bits)

Timer output control register (8 bits)

Timer start register (8 bits)

Timer synchro register (8 bits)

Timer mode register (8 bits)

Timer function control register (8 bits)

Figure 10.1 ITU Block Diagram (Overall)

Rev. 6.0, 09/02, page 317 of 876

Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Bo th have

the structure shown in figure 10.2.

Clock selector

Comparator

Control logic

TCLKA to TCLKD

φ, φ/2, φ/4, φ/8

TIOCA

TIOCB

IMIA0

IMIB0

OVI0

TCNT

GRA

GRB

TCR

TIOR

TIER

TSR

Module data bus

Legend

TCNT:

GRA, GRB:

TCR:

TIOR:

TIER:

TSR:

Timer counter (16 bits)

General registers A and B (input capture/output compare registers) (16 bits 2)

Timer control register (8 bits)

Timer I/O control register (8 bits)

Timer interrupt enable register (8 bits)

Timer status register (8 bits)

Figure 10.2 Block Diagram of Channels 0 and 1 (for Channel 0)

Rev. 6.0, 09/02, page 318 of 876

Block Diagram of Channel 2: Figure 10.3 is a block diagram of channel 2. This is the channel

that provides only 0 output and 1 output.

Clock selector

Comparator

Control logic

TCLKA to TCLKD

φ, φ/2, φ/4, φ/8

TIOCA2

TIOCB2

IMIA2

IMIB2

OVI2

TCNT2

GRA2

GRB2

TCR2

TIOR2

TIER2

TSR2

Module data bus

Legend

TCNT2:

GRA2, GRB2:

TCR2:

TIOR2:

TIER2:

TSR2:

Timer counter 2 (16 bits)

General registers A2 and B2 (input capture/output compare registers)

(16 bits 2)

Timer control register 2 (8 bits)

Timer I/O control register 2 (8 bits)

Timer interrupt enable register 2 (8 bits)

Timer status register 2 (8 bits)

Figure 10.3 Block Diagram of Channel 2

Rev. 6.0, 09/02, page 319 of 876

Block Diagrams of Channels 3 and 4: Figure 10.4 is a block diagram of channel 3. Figure 10.5 is

a block diagram of channel 4.

TCNT3

BRA3

Legend

TCNT3:

GRA3, GRB3:

BRA3, BRB3:

TCR3:

TIOR3:

TIER3:

TSR3:

Timer counter 3 (16 bits)

General registers A3 and B3 (input capture/output compare registers)

(16 bits 2)

Buffer registers A3 and B3 (input capture/output compare buffer registers)

(16 bits 2)

Timer control register 3 (8 bits)

Clock selector

Comparator

Control logic

GRA3

BRB3

GRB3

TCR3

TIOR3

TIER3

TSR3

TCLKA to

TCLKD

φ, φ/2,

φ/4, φ/8

TIOCA3

TIOCB3

Module data bus

IMIA3

IMIB3

OVI3

Timer I/O control register 3 (8 bits)

Timer interrupt enable register 3 (8 bits)

Timer status register 3 (8 bits)

Figure 10.4 Block Diagram of Channel 3

Rev. 6.0, 09/02, page 320 of 876

TCNT4

BRA4

Legend

TCNT4:

GRA4, GRB4:

BRA4, BRB4:

TCR4:

TIOR4:

TIER4:

TSR4:

Timer counter 4 (16 bits)

General registers A4 and B4 (input capture/output compare registers)

(16 bits 2)

Buffer registers A4 and B4 (input capture/output compare buffer registers)

(16 bits 2)

Timer control register 4 (8 bits)

Clock selector

Comparator

Control logic

GRA4

BRB4

GRB4

TCR4

TIOR4

TIER4

TSR4

Module data bus

TCLKA to

TCLKD

φ, φ/2,

φ/4, φ/8

Timer I/O control register 4 (8 bits)

Timer interrupt enable register 4 (8 bits)

Timer status register 4 (8 bits)

TOCXA

TOCXB

TIOCA

TIOCB

IMIA4

IMIB4

OVI4

Figure 10.5 Block Diagram of Channel 4

Rev. 6.0, 09/02, page 321 of 876

10.1 .3 Input/Output Pins

Table 10.2 summarizes the ITU pins.

Table 10.2 ITU Pins

Channel Name Abbre-

viation Input/

Output Function

Common Clock input A TCLKA Input External clock A input pin

(phase-A input pin in phase cou ntin g mode)

Clock input B TCLKB Input External clock B input pin

(phase-B input pin in phase cou ntin g mode)

Clock input C TCLKC Input External clock C input pin

Clock input D TCLKD Input External clock D input pin

0 Input capture/output

compare A0 TIOCA0Input/

output GRA0 output compare or input capture pin

PWM output pin in PWM mode

Input capture/ outp ut

compare B0 TIOCB0Input/

output GRB0 output compare or input capture pin

1 Input capture/output

compare A1 TIOCA1Input/

output GRA1 output compare or input capture pin

PWM output pin in PWM mode

Input capture/ outp ut

compare B1 TIOCB1Input/

output GRB1 output compare or input capture pin

2 Input capture/output

compare A2 TIOCA2Input/

output GRA2 output compare or input capture pin

PWM output pin in PWM mode

Input capture/ outp ut

compare B2 TIOCB2Input/

output GRB2 output compare or input capture pin

3 Input capture/output

compare A3 TIOCA3Input/

output GRA3 output compare or input capture pin

PWM output pin in PWM mode,

complementary PWM mode, or reset-

synchronized PWM mode

Input capture/ outp ut

compare B3 TIOCB3Input/

output GRB3 output compare or input capture pin

PWM output pin in complementary PWM

mode or reset-synchronized PWM mode

4 Input capture/output

compare A4 TIOCA4Input/

output GRA4 output compare or input capture pin

PWM output pin in PWM mode,

complementary PWM mode, or reset-

synchronized PWM mode

Input capture/ outp ut

compare B4 TIOCB4Input/

output GRB4 output compare or input capture pin

PWM output pin in complementary PWM

mode or reset-synchronized PWM mode

Output compare XA4 TOCXA4Output PWM output pin in complementary PWM

mode or reset-synchronized PWM mode

Output compare XB4 TOCXB4Output PWM output pin in complementary PWM

mode or reset-synchronized PWM mode

Rev. 6.0, 09/02, page 322 of 876

10.1.4 Register Configuration

Table 10.3 summarizes the ITU registers.

Table 10.3 ITU Registers

Channel Address*1Name Abbre-

viation R/W Initial

Value

Common H'FF60 Timer start register TSTR R/W H'E0

H'FF61 Timer synchro register TSNC R/W H'E0

H'FF62 Timer mode register TMDR R/W H'80

H'FF63 Timer function control register TFCR R/W H'C0

H'FF90 Timer output master enable register TOER R/W H'FF

H'FF91 Timer output control register TOCR R/W H'FF

0 H'FF64 Timer control register 0 TCR0 R/W H'80

H'FF65 Timer I/O control register 0 TIOR0 R/W H'88

H'FF66 Timer interrupt enable register 0 TIER0 R/W H'F8

H'FF67 Timer status register 0 TSR0 R/(W)*2H'F8

H'FF68 Timer counter 0 (high) TCNT0H R/W H'00

H'FF69 Timer counter 0 (low) TCNT0L R/W H'00

H'FF6A General register A0 (high) GRA0H R/W H'FF

H'FF6B General register A0 (low) GRA0L R/W H'FF

H'FF6C General register B0 (high) GRB0H R/W H'FF

H'FF6D General register B0 (low) GRB0L R/W H'FF

1 H'FF6E Timer control register 1 TCR1 R/W H'80

H'FF6F Timer I/O control register 1 TIOR1 R/W H'88

H'FF70 Timer interrupt enable register 1 TIER1 R/W H'F8

H'FF71 Timer status register 1 TSR1 R/(W)*2H'F8

H'FF72 Timer counter 1 (high) TCNT1H R/W H'00

H'FF73 Timer counter 1 (low) TCNT1L R/W H'00

H'FF74 General register A1 (high) GRA1H R/W H'FF

H'FF75 General register A1 (low) GRA1L R/W H'FF

H'FF76 General register B1 (high) GRB1H R/W H'FF

H'FF77 General register B1 (low) GRB1L R/W H'FF

Rev. 6.0, 09/02, page 323 of 876

Channel Address*1Name Abbre-

viation R/W Initial

Value

2 H'FF78 Timer control register 2 TCR2 R/W H'80

H'FF79 Timer I/O control register 2 TIOR2 R/W H'88

H'FF7A Timer interrupt enable register 2 TIER2 R/W H'F8

H'FF7B Timer status register 2 TSR2 R/(W)*2H'F8

H'FF7C Timer counter 2 (high) TCNT2H R/W H'00

H'FF7D Timer counter 2 (low) TCNT2L R/W H'00

H'FF7E General register A2 (high) GRA2H R/W H'FF

H'FF7F General register A2 (low) GRA2L R/W H'FF

H'FF80 General register B2 (high) GRB2H R/W H'FF

H'FF81 General register B2 (low) GRB2L R/W H'FF

3 H'FF82 Timer control register 3 TCR3 R/W H'80

H'FF83 Timer I/O control register 3 TIOR3 R/W H'88

H'FF84 Timer interrupt enable register 3 TIER3 R/W H'F8

H'FF85 Timer status register 3 TSR3 R/(W)*2H'F8

H'FF86 Timer counter 3 (high) TCNT3H R/W H'00

H'FF87 Timer counter 3 (low) TCNT3L R/W H'00

H'FF88 General register A3 (high) GRA3H R/W H'FF

H'FF89 General register A3 (low) GRA3L R/W H'FF

H'FF8A General register B3 (high) GRB3H R/W H'FF

H'FF8B General register B3 (low) GRB3L R/W H'FF

H'FF8C Buffer register A3 (high) BRA3H R/W H'FF

H'FF8D Buffer register A3 (low) BRA3L R/W H'FF

H'FF8E Buffer register B3 (high) BRB3H R/W H'FF

H'FF8F Buffer register B3 (low) BRB3L R/W H'FF

Rev. 6.0, 09/02, page 324 of 876

Channel Address*1Name Abbre-

viation R/W Initial

Value

4 H'FF92 Timer control register 4 TCR4 R/W H'80

H'FF93 Timer I/O control register 4 TIOR4 R/W H'88

H'FF94 Timer interrupt enable register 4 TIER4 R/W H'F8

H'FF95 Timer status register 4 TSR4 R/(W)*2H'F8

H'FF96 Timer counter 4 (high) TCNT4H R/W H'00

H'FF97 Timer counter 4 (low) TCNT4L R/W H'00

H'FF98 General register A4 (high) GRA4H R/W H'FF

H'FF99 General register A4 (low) GRA4L R/W H'FF

H'FF9A General register B4 (high) GRB4H R/W H'FF

H'FF9B General register B4 (low) GRB4L R/W H'FF

H'FF9C Buffer register A4 (high) BRA4H R/W H'FF

H'FF9D Buffer register A4 (low) BRA4L R/W H'FF

H'FF9E Buffer register B4 (high) BRB4H R/W H'FF

H'FF9F Buffer register B4 (low) BRB4L R/W H'FF

Notes: *1 Lower 16 bits of the address.

*2 Only 0 can be written, to clear flags.

Rev. 6.0, 09/02, page 325 of 876

10.2 Register Descriptions

10.2.1 Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register th at starts and stops the timer counter ( T CNT) in

channels 0 to 4.

Bit

Initial value

Read/Write

—

STR4

R/W

STR3

R/W

STR2

R/W

STR1

R/W

STR0

R/W

Reserved bits Counter start 4 to 0

These bits start and

stop TCNT4 to TCNT0

TSTR is initialized to H'E0 by a reset and in standby mode.

Bits 7 to 5—Reserved: Read-only bits, always read as 1.

Bit 4—Counter Start 4 (STR4): Starts and stops timer counter 4 (TCNT4).

Bit 4: STR4 Description

0 TCNT4 is halted (Initial val ue)

1 TCNT4 is counting

Bit 3—Counter Start 3 (STR3): Starts and stops timer counter 3 (TCNT3).

Bit 3: STR3 Description

0 TCNT3 is halted (Initial val ue)

1 TCNT3 is counting

Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (TCNT2).

Bit 2: STR2 Description

0 TCNT2 is halted (Initial val ue)

1 TCNT2 is counting

Rev. 6.0, 09/02, page 326 of 876

Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1).

Bit 1: STR1 Description

0 TCNT1 is halted (Initial val ue)

1 TCNT1 is counting

Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0).

Bit 0: STR0 Description

0 TCNT0 is halted (Initial val ue)

1 TCNT0 is counting

10.2.2 Timer Synchro Register (TSNC)

TSNC is an 8-bit readable/writable register that selects whether channels 0 to 4 operate

independently or synchronously . Channels are synchronized by setting the corresponding bits to 1.

Bit

Initial value

Read/Write

—

SYNC4

R/W

SYNC3

R/W

SYNC2

R/W

SYNC1

R/W

SYNC0

R/W

Reserved bits Timer sync 4 to 0

These bits synchronize

channels 4 to 0

TSNC is initialized to H'E0 by a reset and in standby mod e.

Bits 7 to 5—Reserved: Read-only bits, always read as 1.

Bit 4—Timer Sync 4 (SYNC4): Selects whether channel 4 operates independently or

synchronously.

Bit 4: SYNC4 Description

0 Channel 4’s timer counter (TCNT4) operates independently (Initial value)

TCNT4 is preset and cleared inde pe ndently of other channels

1 Channel 4 operates synchronously

TCNT4 can be synchronously preset and cleared

Rev. 6.0, 09/02, page 327 of 876

Bit 3—Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or

synchronously.

Bit 3: SYNC3 Description

0 Channel 3’s timer counter (TCNT3) operates independently (Initial value)

TCNT3 is preset and cleared ind epe ndently of other channels

1 Channel 3 operates synchronously

TCNT3 can be synchronously preset and cleared

Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or

synchronously.

Bit 2: SYNC2 Description

0 Channel 2’s timer counter (TCNT2) operates independently (Initial value)

TCNT2 is preset and cleared ind epe ndently of other channels

1 Channel 2 operates synchronously

TCNT2 can be synchronously preset and cleared

Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or

synchronously.

Bit 1: SYNC1 Description

0 Channel 1’s timer counter (TCNT1) operates independently (Initial value)

TCNT1 is preset and cleared ind epen dently of other channels

1 Channel 1 operates synchronously

TCNT1 can be synchronously preset and cleared

Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or

synchronously.

Bit 0: Bit 0 Description

0 Channel 0’s timer counter (TCNT0) operates independently (Initial value)

TCNT0 is preset and cleared ind epe ndently of other channels

1 Channel 0 operates synchronously

TCNT0 can be synchronously preset and cleared

Rev. 6.0, 09/02, page 328 of 876

10.2.3 Timer Mode Register (TMDR)

TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also

selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.

Bit

Initial value

Read/Write

—

MDF

R/W

FDIR

R/W

PWM4

R/W

PWM3

R/W

PWM0

R/W

PWM2

R/W

PWM1

R/W

Reserved bit

PWM mode 4 to 0

These bits select PWM

mode for channels 4 to 0

Phase counting mode flag

Selects phase counting mode for channel 2

Flag direction

Selects the setting condition for the overflow

flag (OVF) in timer status register 2 (TSR2)

TMDR is initialized to H'80 by a reset and in standby mode.

Bit 7—Reserved: Read-only bit, always read as 1.

Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in

phase counting mode.

Bit 6: MDF Description

0 Channel 2 operates normally (Initial value)

1 Channel 2 operates in phase cou ntin g mode

Rev. 6.0, 09/02, page 329 of 876

When MDF is set to 1 to select phase counting mode, TCNT2 operates as an up/down-counter and

pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts both rising and falling

edges of TCLKA and TCLKB, and counts up or down as follows.

Counting Direction Down-Counting Up-Counting

TCLKA pin ↑High ↓Low ↑Low ↓High

TCLKB pin Low ↑High ↓High ↓Low ↓

In phase counting mode channel 2 operates as above regardless of the external clock edges

selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0 in

TCR2. Phase counting mode takes precedence over these settings.

The counter clearing condition selected by the CCLR1 and CCLR0 bits in TCR2 and the compare

match/input capture settings and interrupt functions of TIOR2, TIER2, and TSR2 remain effective

in phase counting mode.

Bit 5—Flag Direction (FDIR): Designates the setting condition for the OVF flag in TSR2. The

FDIR designation is valid in all modes in channel 2.

Bit 5: FDIR Description

0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows (Initial value)

1 OVF is set to 1 in TSR2 when TCNT2 overflows

Bit 4—PWM Mode 4 (PWM4): Selects whether channel 4 operates normally or in PWM mode.

Bit 4: PWM4 Description

0 Channel 4 operates normally (Initial value)

1 Channel 4 operates in PWM mode

When bit PWM4 is set to 1 to select PWM mode, pin TIOCA4 becomes a PWM output pin. The

output goes to 1 at compare match with GRA4, and to 0 at compare match with GRB4.

If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and

CMD0 in TFCR, the CMD1 and CMD0 settin g takes precedence and the PWM4 settin g is

ignored.

Rev. 6.0, 09/02, page 330 of 876

Bit 3—PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode.

Bit 3: PWM3 Description

0 Channel 3 operates normally (Initial value)

1 Channel 3 operates in PWM mode

When bit PWM3 is set to 1 to select PWM mode, pin TIOCA3 becomes a PWM output pin. The

output goes to 1 at compare match with GRA3, and to 0 at compare match with GRB3.

If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and

CMD0 in TFCR, the CMD1 and CMD0 settin g takes precedence and the PWM3 settin g is

ignored.

Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.

Bit 2: PWM2 Description

0 Channel 2 operates normally (Initial value)

1 Channel 2 operates in PWM mode

When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The

output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2.

Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.

Bit 1: PWM1 Description

0 Channel 1 operates normally (Initial value)

1 Channel 1 operates in PWM mode

When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The

output goes to 1 at compare match with GRA1, and to 0 at compare match with GRB1.

Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.

Bit 0: PWM0 Description

0 Channel 0 operates normally (Initial value)

1 Channel 0 operates in PWM mode

When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The

output goes to 1 at compare match with GRA0, and to 0 at compare match with GRB0.

Rev. 6.0, 09/02, page 331 of 876

10.2.4 Timer Function Control Register (TFCR)

TFCR is an 8-bit readable/writable register that selects complementary PWM mode, reset-

synchronized PWM mode, and buffering for channels 3 and 4.

Bit

Initial value

Read/Write

—

CMD1

R/W

CMD0

R/W

BFB4

R/W

BFA3

R/W

BFA4

R/W

BFB3

R/W

Reserved bits

Combination mode 1/0

These bits select complementary

PWM mode or reset-synchronized

PWM mode for channels 3 and 4

Buffer mode B4 and A4

These bits select buffering of

general registers (GRB4 and

GRA4) by buffer registers

(BRB4 and BRA4) in channel 4

Buffer mode B3 and A3

These bits select buffering

of general registers (GRB3

and GRA3) by buffer

registers (BRB3 and BRA3)

in channel 3

TFCR is initialized to H'C0 by a reset and in standby mode.

Bits 7 and 6—Reserved: Read-only bits, always read as 1.

Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels

3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode.

Bit 5: CMD1 Bit 4: CMD0 Description

1Channels 3 and 4 operate normally (Initial value)

1 0 Channels 3 and 4 operate together in complementary

PWM mode

1 Channels 3 and 4 operate together in reset-sync hronized

PWM mode

Rev. 6.0, 09/02, page 332 of 876

Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer

counter or counters that will be used in these modes.

When these bits select complementary PWM mode or reset-synchronized PWM mode, they take

precedence over the setting of the PWM mode b its (PWM4 and PWM3) in TMDR. Setting s of

complementary PWM mode or reset-synchronized PWM mode and settings of timer sync bits

SYNC4 and SYNC3 in TSNC are valid simultaneously, however, when complementary PWM

mode is selected, channels 3 and 4 must not be synchronized (do not set bits SYNC3 and SYNC4

both to 1 in TSNC).

Bit 3—Buf fer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or

whether GRB4 is buffered by BRB4.

Bit 3: BFB4 Description

0 GRB4 operates norm all y (Initial val ue)

1 GRB4 is buffered by BRB4

Bit 2—Buffer Mode A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or

whether GRA4 is buffered by BRA4.

Bit 2: BFA4 Description

0 GRA4 operates norm all y (Initial val ue)

1 GRA4 is buffered by BRA4

Bit 1—Buf fer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or

whether GRB3 is buffered by BRB3.

Bit 1: BFB3 Description

0 GRB3 operates norm all y (Initial val ue)

1 GRB3 is buffered by BRB3

Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or

whether GRA3 is buffered by BRA3.

Bit 0: BFA3 Description

0 GRA3 operates norm all y (Initial val ue)

1 GRA3 is buffered by BRA3

Rev. 6.0, 09/02, page 333 of 876

10.2.5 Timer Output Master Enable Register (TOER)

TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3

and 4.

Bit

Initial value

Read/Write

—

EXB4

R/W

EXA4

R/W

EB3

R/W

EA3

R/W

EB4

R/W

EA4

R/W

Reserved bits

Master enable TOCXA4, TOCXB4

These bits enable or disable output

settings for pins TOCXA

and TOCXB

Master enable TIOCA3, TIOCB3 , TIOCA4, TIOCB4

These bits enable or disable output settings for pins

TIOCA

, TIOCB

, TIOCA

, and TIOCB

TOER is initialized to H'FF by a reset and in standby mode.

Bits 7 and 6—Reserved: Read-only bits, always read as 1.

Bit 5—Master En able TOCXB4 (EXB4): Enables or disables ITU output at pin TOCXB4.

Bit 5: EXB4 Description

0TOCXB

4 output is disabled regardless of TFCR settings (TOCXB4 operates as

a generic input/output pin).

If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1.

1TOCXB

4 is enabled for output according to TFCR settings (Initial value)

Bit 4—Master Enable TOCXA4 (EXA4): Enables or disables ITU output at pin TOCXA4.

Bit 4: EXA4 Description

0TOCXA

4 output is disabled regardless of TFCR settings (TOCXA4 operates as

a generic input/output pin).

If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.

1TOCXA

4 is enabled for output according to TFCR settings (Initial value)

Rev. 6.0, 09/02, page 334 of 876

Bit 3—Master En able TIOC B3 (EB3 ): Enables or disables ITU output at pin TIOCB3.

Bit 3: EB3 Description

0TIOCB

3 output is disabled regardless of TIOR3 and TFCR settings (TIOCB3

operates as a generic input/output pin).

If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.

1TIOCB

3 is enabled for output according to TIOR3 and TFCR settings

(Initial value)

Bit 2—Master En able TIOC B4 (EB4 ): Enables or disables ITU output at pin TIOCB4.

Bit 2: EB4 Description

0TIOCB

4 output is disabled regardless of TIOR4 and TFCR settings (TIOCB4

operates as a generic input/output pin).

If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.

1TIOCB

4 is enabled for output according to TIOR4 and TFCR settings

(Initial value)

Bit 1—Master Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA4.

Bit 1: EA4 Description

0TIOCA

4 output is disabled regardless of TIOR4, TMDR, and TFCR settings

(TIOCA4 operates as a generic input/output pin).

If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.

1TIOCA

is enabled for output according to TIOR4, TMDR, and TFCR settings

(Initial value)

Bit 0—Master Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA3.

Bit 0: EA3 Description

0TIOCA

3 output is disabled regardless of TIOR3, TMDR, and TFCR settings

(TIOCA3 operates as a generic input/output pin).

If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.

1TIOCA

is enabled for output according to TIOR3, TMDR, and TFCR settings

(Initial value)

Rev. 6.0, 09/02, page 335 of 876

10.2.6 Timer Output Control Register (TOCR)

TOCR is an 8-bit readable/writable register th at selects externally triggered disabling of outpu t in

complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels.

Bit

Initial value

Read/Write

—

XTGD

R/W

—

OLS3

R/W

—

OLS4

R/W

Reserved bits Output level select 3, 4

These bits select output

levels in complementary

PWM mode and reset-

synchronized PWM mode

External trigger disable

Selects externally triggered disabling of output in

complementary PWM mode and reset-synchronized

PWM mode

Reserved bits

The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode

and reset-synchronized PWM mode. These settings do not affect other modes.

TOCR is initialized to H'FF by a reset and in standby mode.

Bits 7 to 5—Reserved: Read-only bits, always read as 1.

Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output

in complementary PWM mode and reset-synchronized PWM mode.

Bit 4: XTGD Description

0 Input capture A in channel 1 is used as an external trigger signal in

complementary PWM mode and reset-synchronized PWM mode.

When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0, disabling

ITU output.

1 External triggering is disabled (Initial value)

Bits 3 and 2—Reserved: Read-only bits, always read as 1.

Rev. 6.0, 09/02, page 336 of 876

Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and

reset-synchronized PWM mode.

Bit 1: OLS4 Description

0TIOCA

3, TIOCA4, and TIOCB4 outputs are inverted

1TIOCA

3, TIOCA4, and TIOCB4 output s are not inverte d (Initi al val ue)

Bit 0—Output Level Select 3 (OLS3): Selects output levels in complementary PWM mode and

reset-synchronized PWM mode.

Bit 0: OLS3 Description

0TIOCB

3, TOCXA4, and TOCXB4 outputs are inve rted

1TIOCB

3, TOCXA4, and TOCXB4 outputs are not inverted (Initial value)

10.2.7 Timer Counters (TCNT)

TCNT is a 16-bit counter. The ITU has five TCNTs, one for each channel.

Channel Abbreviation Function

0 TCNT0

1 TCNT1 Up-counter

2 TCNT2 Phase counting mode: up/down-counter

Other modes: up-counter

3 TCNT3

4 TCNT4 Complementary PWM mode: up/down-counter

Other modes: up-counter

Bit

Initial value

Read/Write

R/W

Each TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock so urce. The

clock source is selected by bits TPSC2 to TPSC0 in TCR.

TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and

an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM

mode and up-counters in other modes.

Rev. 6.0, 09/02, page 337 of 876

TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to GRA

or GRB (counter clearing function) in the same channel.

When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TSR of the

corresponding channel.

When TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TSR of the

corresponding channel.

The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either

word access or byte access.

Each TCNT is initialized to H'0000 by a reset and in standby mode.

10.2.8 General Registers (GRA, GRB)

The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel.

Channel Abbreviation Function

0GRA0, GRB0

1GRA1, GRB1

2GRA2, GRB2

Output compare/input capture register

3GRA3, GRB3

4GRA4, GRB4

Output compare/input capture register; can be buffered by

buffer registers BRA and BRB

Bit

Initial value

Read/Write

R/W

A general register is a 16-bit readable/writable register that can function as either an ou tput

compare register or an input capture register. The function is selected by settings in TIOR.

When a general register is used as an output compare register, its value is constantly compared

with the TCNT value. When the two values match ( comp are match), the IMFA or IMFB flag is set

to 1 in TSR. Co mpare match output can be selected in TIOR.

When a general register is used as an input capture register, rising edges, falling edges, or both

edges of an external input capture signal are detected and the current TCNT value is stored in the

general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The

valid edge or edges of the input capture signal are selected in TIOR.

Rev. 6.0, 09/02, page 338 of 876

TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized

PWM mode.

General register s ar e linked to the CPU by an intern al 16- bit bus and can be written or read by

either word access or byte access.

General register s ar e initialized to the output compare function (with no output sig nal) by a reset

and in standby mode. The initial value is H'FFFF.

10.2.9 Buffer Registers (BRA, BRB)

The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3

and 4.

Channel Abbreviation Function

3 BRA3, BRB3

4 BRA4, BRB4 Used for buffering

• When the corresponding GRA or GRB functions as an

output compare register, BRA or BRB can function as an

output compare buffer register: the BRA or BRB value is

automatically transferred to GRA or GRB at compare match

• When the corresponding GRA or GRB functions as an input

capture register, BRA or BRB can function as an input

capture buffer register: the GRA or GRB value is

automatically transferred to BRA or BRB at input capture

Bit

Initial value

Read/Write

R/W

A buffer register is a 16-bit readable/writable register that is used when buffering is selected.

Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR.

The buffer register and general register operate as a pair. When the general register functions as an

output compare register, the buffer register functions as an output compare buffer register. When

the general register functions as an input capture register, the buffer register functions as an input

capture buffer register.

The buffer registers are lin ked to the CPU by an internal 1 6-b it bus an d can be written or read by

either word or byte access.

Buffer registers are initialized to H'FFFF by a reset and in standby mode.

Rev. 6.0, 09/02, page 339 of 876

10.2.10 Timer Control Registers (TCR)

TCR is an 8-bit register. The ITU has five TCRs, one in each ch annel.

Channel Abbreviation Function

0 TCR0

1 TCR1

2 TCR2

3 TCR3

4 TCR4

TCR controls the timer counter. The TCRs in all channels are

function all y ident ic al. When pha se cou nting mode is se lec ted in

channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2

to TPSC0 in TCR2 are ignored.

Bit

Initial value

Read/Write

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Timer prescaler 2 to 0

These bits select the

counter clock

Reserved bit

Clock edge 1/0

These bits select external clock edges

Counter clear 1/0

These bits select the counter clear source

Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects

the edge or edges of external clock sources, and selects how the counter is cleared.

TCR is initialized to H'8 0 by a reset and in stan dby mode.

Bit 7—Reserved: Read-only bit, always read as 1.

Rev. 6.0, 09/02, page 340 of 876

Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.

Bit 6: CCLR1 Bit 5: CCLR0 Description

0 0 TCNT is not cleared (Initial value)

1 TCNT is cleared by GRA compare match or input

capture*1

1 0 TCNT is cleared by GRB compare match or input

capture*1

1 Synchronous clear: TCNT is cle ared in synchronization

with other synchronized timers*2

Notes: *1 TCNT is cleared by com par e match when the general r egi ster fun cti ons as an outp ut

compare register, and by input capture when the general register functions as an input

capture register.

*2 Selec ted in TSNC.

Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges

when an external clock source is used.

Bit 4: CKEG1 Bit 3: CKEG0 Description

0 0 Count rising edges (Initial value)

1 Count falling edges

1 — Count both edges

When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.

Phase counting takes precedence.

Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock

source.

Bit 2: TPSC2 Bit 1: TPSC1 Bit 0: TPSC0 Description

0 0 0 Internal clock: φ(Initial value)

1 Internal clo ck: φ/2

1 0 Internal clock: φ/4

1 Internal clo ck: φ/8

1 0 0 External clock A: TCLKA input

1 External clock B: TCLKB input

1 0 External clock C: TCLKC input

1 External clo ck D: TC LKD input

Rev. 6.0, 09/02, page 341 of 876

When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only

falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts

the edge or edges selected by bits CKEG1 and CKEG0.

When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to

TPSC0 in TCR2 are ignored. Phase counting takes precedence.

10.2.11 Timer I/O Control Register (TIOR)

TIOR is an 8-bit register. The ITU has five TIORs, one in each channel.

Channel Abbreviation Function

0TIOR0

1TIOR1

2TIOR2

3TIOR3

4TIOR4

TIOR controls the general registers. Some functions differ in

PWM mode. TIOR3 and TIOR4 settings are ignored when

complementary PWM mode or reset-synchronized PWM mode

is selected in channels 3 and 4.

Bit

Initial value

Read/Write

—

IOB2

R/W

IOB1

R/W

IOB0

R/W

—

IOA0

R/W

IOA2

R/W

IOA1

R/W

I/O control A2 to A0

These bits select GRA

functions

Reserved bit

I/O control B2 to B0

These bits select GRB functions

Reserved bit

Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture

function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins. If the

output compare function is selected, TIOR also selects the type of output. If input capture is

selected, TIOR also selects the edge or edges of the input capture signal.

TIOR is initialized to H'8 8 by a reset and in stand by mode.

Bit 7—Reserved: Read-only bit, always read as 1.

Rev. 6.0, 09/02, page 342 of 876

Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.

Bit 6:

IOB2 Bit 5:

IOB1 Bit 4:

IOB0 Description

0 0 0 No output at compare match (Initial value)

1 0 output at GRB compare match*1

1 0 1 output at GRB compare match*1

GRB is an output

compare register

Output toggles at GRB compare match

(1 output in channel 2)*1 *2

1 0 0 GRB captures rising edge of input

1 GRB captures falling edge of input

GRB is an input

capture register

GRB captures both edges of input

Notes: *1 After a reset, the output is 0 until the first compare match.

*2 Channel 2 output cannot be toggled by compare match. This setting selects 1 output

instead.

Bit 3—Reserved: Read-only bit, always read as 1.

Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.

Bit 2:

IOA2 Bit 1:

IOA1 Bit 0:

IOA0 Description

0 0 0 No output at compare match (Initial value)

1 0 output at GRA compare match*1

1 0 1 output at GRA compare match*1

GRA is an output

compare register

Output toggles at GRA compare match

(1 output in channel 2)*1 *2

1 0 0 GRA captures rising edge of input

1 GRA captures falling edge of input

GRA is an input

capture register

GRA captures both edges of input

Notes: *1 After a reset, the output is 0 until the first compare match.

*2 Channel 2 output cannot be toggled by compare match. This setting selects 1 output

instead.

Rev. 6.0, 09/02, page 343 of 876

10.2.12 Timer Status Register (TSR)

TSR is an 8-bit register. The ITU has five TSRs, one in each channel.

Channel Abbreviation Function

0TSR0

1TSR1

2TSR2

3TSR3

4TSR4

Indicates input capture, compare match, and overflow status

Bit

Initial value

Read/Write

—

—*

OVF

R/(W)

Reserved bits

Note: Only 0 can be written, to clear the flag.*

IMFB

R/(W) *

IMFA

R/(W)

Overflow flag

Status flag indicating

overflow or underflow

Input capture/compare match flag B

Status flag indicating GRB compare

match or input capture

Input capture/compare match flag A

Status flag indicating GRA compare

match or input capture

Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or

underflow and GRA or GRB compare match or input capture. These flags are interrupt sources

and generate CPU interrupts if enabled by corresponding bits in TIER.

TSR is initialized to H'F8 by a reset and in standby mode.

Bits 7 to 3—Reserved: Read-only bits, always read as 1.

Rev. 6.0, 09/02, page 344 of 876

Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.

Bit 2: OVF Description

0 [Clearing cond iti on] (Initial value)

Read OVF when OVF = 1, then write 0 in OVF

1 [Setting condition]

TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to

H'FFFF*

Notes: *TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow

occurs only under the following conditions:

1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR)

2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0 in

TFCR)

Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB

compare match or input capture events.

Bit 1: IMFB Description

0 [Clearing cond iti on] (Initial value)

Read IMFB when IMFB = 1, then write 0 in IMFB

1 [Setting conditions]

TCNT = GRB when GRB functions as an output compare register.

TCNT value is transferred to GRB by an input capture signal, when GRB

functions as an input capture register.

Bit 0—Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA

compare match or input capture events.

Bit 0: IMFA Description

0 [Clearing cond iti on] (Initial value)

Read IMFA when IMFA = 1, then write 0 in IMFA.

DMAC activated by IMIA interrupt (channels 0 to 3 only).

1 [Setting conditions]

TCNT = GRA when GRA functions as an output compare register.

TCNT value is transferred to GRA by an input capture signal, when GRA

functions as an input capture register.

Rev. 6.0, 09/02, page 345 of 876

10.2.13 Timer Interrupt Enable Register (TIER)

TIER is an 8-bit register. The ITU has five TIERs, one in each channel.

Channel Abbreviation Function

0TIER0

1TIER1

2TIER2

3TIER3

4TIER4

Enables or disables interrupt requests.

Bit

Initial value

Read/Write

—

OVIE

R/W

IMIEB

R/W

IMIEA

R/W

Reserved bits

Overflow interrupt enable

Enables or disables OVF

interrupts

Input capture/compare match

interrupt enable B

Enables or disables IMFB interrupts

Input capture/compare match

interrupt enable A

Enables or disables IMFA

interrupts

Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt

requests and general register compare match and input capture interrupt requests.

TIER is initialized to H'F8 by a reset and in standby mode.

Bits 7 to 3—Reserved: Read-only bits, always read as 1.

Rev. 6.0, 09/02, page 346 of 876

Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables th e interrupt requested by the

OVF flag in TSR when OVF is set to 1 .

Bit 2: OVIE Description

0 OVI interrupt requested by OVF is disabled (Initial value)

1 OVI interrupt requested by OVF is enabled

Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the

interrup t r eque sted by the IMFB flag in TSR when I M FB is set to 1.

Bit 1: IMIEB Description

0 IMIB interrupt requested by IMFB is disabled (Initial value)

1 IMIB interrupt requested by IMFB is enabled

Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the

interrupt r eque sted by the IMFA flag in TSR when IMFA is set to 1.

Bit 0: IMIEA Description

0 IMIA interrupt requested by IMFA is disabled (Initial value)

1 IMIA interrupt requested by IMFA is enabled

Rev. 6.0, 09/02, page 347 of 876

10.3 CPU Interface

10.3.1 16-Bit Accessible Registers

The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A

and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data

bus. These registers can be written or read a word at a time, or a byte at a time.

Figures 10.6 and 10.7 show examples of word access to a timer counter (TCNT). Figures 10.8 to

10.11 show examples of byte access to TCNTH and TCNTL.

On-chip data bus

CPU

L Bus interface

LModule

data bus

TCNTH TCNTL

Figure 10.6 Access to Timer Counter (CPU Writes to TCNT, Word)

On-chip data bus

CPU

L Bus interface

LModule

data bus

TCNTH TCNTL

Figure 10.7 Access to Timer Counter (CPU Reads TCNT, Word)

Rev. 6.0, 09/02, page 348 of 876

On-chip data bus

CPU

L Bus interface

LModule

data bus

TCNTH TCNTL

Figure 10.8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte)

On-chip data bus

CPU

L Bus interface

LModule

data bus

TCNTH TCNTL

Figure 10.9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte)

On-chip data bus

CPU

L Bus interface

LModule

data bus

TCNTH TCNTL

Figure 10.10 Access to Timer Counter (CPU Reads TCN T, Upper Byte)

Rev. 6.0, 09/02, page 349 of 876

On-chip data bus

CPU

L Bus interface

LModule

data bus

TCNTH TCNTL

Figure 10.11 Access to Timer Counter (CPU Reads TCNT, Lower Byte)

10.3.2 8-Bit Accessible Registers

The registers other than the timer counters, general registers, and buffer registers are 8-bit

registers. These registers are linked to the CPU by an internal 8-bit data bus.

Figures 10.12 and 10.13 show examples of byte read and write access to a TCR.

If a word-size data transfer instruction is executed, two byte transfers are performed.

On-chip data bus

CPU

L Bus interface

LModule

data bus

TCR

Figure 10.12 Access to Timer Counter (CPU Writes to TCR)

Rev. 6.0, 09/02, page 350 of 876

On-chip data bus

CPU

L Bus interface

LModule

data bus

TCR

Figure 10.13 Access to Timer Counter (CPU Reads TCR)

Rev. 6.0, 09/02, page 351 of 876

10.4 Operation

10.4.1 Overview

A summary of operations in the various modes is given below.

Normal Operation: Each channel has a timer counter and general registers. The timer counter

counts up, and can operate as a free-running counter, periodic counter, or external event counter.

General registers A and B can be used for input capture or output compare.

Synchronous Opera tion: The timer counters in designated channels are preset synchronously.

Data written to the tim er counter in any one of these channels is simultaneously written to th e

timer counters in the other channels as well. The timer coun ters can also be cleared synchronously

if so desig nated by the CCLR1 an d CCLR0 bits in the TCRs.

PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare

match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending

on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB

automatically become output compar e registers.

Reset-Synchronized PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with

complementary waveforms. (The three phases are related by having a common transition point.)

When reset-synchronized PWM mode is selected GRA3, GRB3, GRA4, and GRB4 automatically

function as output compare registers, TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and

TOCXB4 function as PWM output pins, and TCNT3 operates as an up-counter. TCNT4 operates

independently, and is not compared with GRA4 or GRB4.

Complementary PWM Mo de: Channels 3 and 4 are paired for three-phase PWM output with

non-overlapping complementary waveforms. When complementary PWM mode is selected

GRA3, GRB3, GRA4, and GRB4 automatically function as output compar e registers, and

TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 function as PWM output pins.

TCNT3 and TCNT4 operate as up/down-counters.

Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and

TCLKB is detected and TCNT2 coun ts up or down accordingly. When phase counting mode is

selected TCLKA and TCLKB become clock input pins and TCNT2 operates as an up/down-

counter.

Rev. 6.0, 09/02, page 352 of 876

Buffering

• If the general register is an output compare register

When compare match occu rs the buffer register value is transferred to the general register.

• If the general register is an input capture register

When input capture occurs the TCNT value is transferred to the general register, and the

previous general register value is transferred to the buffer register.

• Complementary PWM mode

The buffer register value is transferred to the general register when TCNT3 and TCNT4

change counting direction.

• Reset-synchronized PWM mode

The buffer register value is transferred to the general register at GRA3 compare match.

10.4.2 Basic Functions

Counter Operation: When one of bits STR0 to STR4 is set to 1 in th e timer start register ( T STR),

the timer counter (TCNT) in the corresponding channel starts counting. The counting can be free-

running or periodic.

• Sample setup procedure for counter

Figure 10.14 shows a sample procedure for setting up a counter.

Rev. 6.0, 09/02, page 353 of 876

Counter setup

Select counter clock

Type of counting?

Periodic counting

Yes

Select counter clear source

Select output compare

Set period

Start counter

Free-running counting

Start counter

Periodic counter Free-running counter

Figure 10.14 Counter Setup Procedure (Example)

1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock

source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the

external clock signal.

2. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA compare

match or GRB compare match.

3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in

step 2.

4. Write the count period in GRA or GRB, whichever was selected in step 2.

5. Set the STR bit to 1 in TSTR to start the timer counter.

Rev. 6.0, 09/02, page 354 of 876

• Free-running and periodic counter operation

A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A

free-runnin g counter star ts counting up when th e corr esponding bit in TSTR is set to 1. When

the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TSR. If the

correspo ndin g OVIE bit is set to 1 in TIER, a CPU inter r upt is r equested. After the overflow,

the counter continues counting up from H'0000. Figure 10.15 illustrates free-running counting.

TCNT value

H'FFFF

H'0000

STR0 to

STR4 bit

OVF

Time

Figure 10.15 Free-Running Counter Opera tio n

When a channel is set to have its counter cleared by compare match, in that channel TCNT

operates as a periodic counter. Select the output compare function of GRA or GRB, set bit

CCLR1 or CCLR0 in TCR to have the counter cleared by compare match, and set the count

period in GRA or GRB. After these settings, the counter starts counting up as a periodic

counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or

GRB, the IMFA or IMFB flag is set to 1 in TSR and the counter is cleared to H'0000. If the

correspo nding IMIEA or IMIEB bit is set to 1 in TIER, a CPU interrupt is re quested at this

time. After the compare match, TCNT continues counting up from H'0000. Figure 10.16

illustrates periodic counting.

Rev. 6.0, 09/02, page 355 of 876

TCNT value

H'0000

STR bit

IMF

Time

Counter cleared by general

Figure 10.16 Periodic Counter Operation

• TCNT count timing

 Internal clock source

Bits TPSC2 to TPSC0 in TCR select th e system clock (φ) or one of three internal clock

sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).

Figure 10.17 shows the timing.

TCNT input

TCNT

Internal

clock

N – 1 N N + 1

Figure 10.17 Count Timing for Internal Clock Sources

 External clock source

Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD), and

its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling

edge, or both edges can be selected.

The pulse width of the external clock signal must be at least 1.5 system clocks when a

single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter

pulses will not be counted correctly.

Figure 10.18 shows the timing when both edges are detected.

Rev. 6.0, 09/02, page 356 of 876

TCNT input

TCNT

External

clock input

N – 1 N N + 1

Figure 10.18 Count Timing for External Clock Sources (when Both Edges are Detected)

Wavefo rm Output by Compare Ma tch: In ITU channels 0, 1, 3, and 4, compare match A or B

can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the

output can only go to 0 or go to 1.

• Sample setup procedure for waveform output by compare match

Figure 10.19 shows a sample procedure for setting up waveform output by compare match.

Output setup

Select waveform

output mode

Set output timing

Start counter

Waveform output

Select the compare match output mode (0, 1, or

toggle) in TIOR. When a waveform output mode

is selected, the pin switches from its generic input/

output function to the output compare function

(TIOCA or TIOCB). An output compare pin outputs

Set a value in GRA or GRB to designate the

compare match timing.

Set the STR bit to 1 in TSTR to start the timer

counter.

0 until the first compare match occurs.

Figure 10.19 Setup Procedure for Waveform Output by Compare Match (Example)

• Examples of waveform output

Figure 10.20 shows examples of 0 and 1 output. TCNT operates as a free-running counter, 0

output is selected for compare match A, and 1 output is selected for compare match B. Wh en

the pin is already at the selected output level, the pin level does not change.

Rev. 6.0, 09/02, page 357 of 876

Time

H'FFFF

GRB

TIOCB

TIOCA

GRA

No change

1 output

0 output

TCNT value

H'0000

Figure 10.20 0 and 1 Output (Examples)

Figure 10.21 shows examples of toggle output. TCNT operates as a periodic counter, cleared

by compare match B. Toggle output is selected for both compare match A and B.

GRB

TIOCB

TIOCA

GRA

TCNT value

Time

Counter cleared by compare match with GRB

Toggle

output

Toggle

output

H'0000

Figure 10.21 Toggle Output (Example)

Rev. 6.0, 09/02, page 358 of 876

• Output compare timing

The compare match signal is generated in the last state in which TCNT and the general register

match (when TCNT changes from the matching value to the next value). When the compare

match signal is generated, the output value selected in TIOR is output at the output compare

pin (TIOCA or TIOCB). When TCNT matches a general register, the compare match signal is

not generated until the next counter clock pulse.

Figure 10.22 shows the output compare timing.

N + 1N

TCNT input

clock

TCNT

Compare

match signal

TIOCA,

TIOCB

Figure 10.22 Output Compare Timing

Input Capture Function: The TCNT value can be captured into a general register when a

transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take

place on the rising edge, falling edge, or both edges. The input capture function can be used to

measure pulse width or period.

• Sample setup procedure for input capture

Figure 10.23 shows a sample procedure for setting up input capture.

Rev. 6.0, 09/02, page 359 of 876

Input selection

Select input-capture input

Start counter

Input capture

Set TIOR to select the input capture function of a

general register and the rising edge, falling edge,

or both edges of the input capture signal. Clear the

port data direction bit to 0 before making these

TIOR settings.

Set the STR bit to 1 in TSTR to start the timer

counter.

Figure 10.23 Setup Procedure for Input Ca pture (Example)

• Examples of input capture

Figure 10.24 illustrates input capture when the falling edge of TIOCB and both edges of

TIOCA are selected as capture edges. TCNT is cleared by input capture into GRB.

H'0005

H'0180

Time

H'0180

H'0160

H'0005

H'0000

TIOCB

TIOCA

GRA

GRB

Counter cleared by TIOCB

input (falling edge)

TCNT value

H'0160

Figure 10.24 Input Capture (Example)

Rev. 6.0, 09/02, page 360 of 876

• Input capture signal timing

Input capture on the rising edge, falling edge, or both edges can be selected by settings in

TIOR. Figure 10.25 shows the timing when the rising edge is selected. The pulse width of the

input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system

clocks for capture of both edges.

Input-capture input

Internal input

capture signal

TCNT

GRA, GRB

Figure 10.25 Input Capture Signal Timing

Rev. 6.0, 09/02, page 361 of 876

10.4.3 Synchronization

The synchron ization function enables two or more tim er counters to be synchronized by wr iting

the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or

more timer counters can also be cleared simultaneously (synchronous clear). Synchronization

enables additional general registers to be associated with a single time base. Synchronization can

be selected for all channels (0 to 4).

Sample Setup Pr ocedure for Synchronization: Figure 10.26 shows a sample procedure for

setting up synchronization.

Setup for synchronization

Synchronous preset

Set the SYNC bits to 1 in TSNC for the channels to be synchronized.

When a value is written in TCNT in one of the synchronized channels, the same value is

simultaneously written in TCNT in the other channels (synchronized preset).

Select synchronization

Synchronous preset

Write to TCNT

Synchronous clear

Clearing

synchronized to this

channel?

Select counter clear source

Start counter

Counter clear Synchronous clear

Start counter

Select counter clear source

Yes

Set the CCLR1 or CCLR0 bit in TCR to have the counter cleared by compare match or input capture.

Set the CCLR1 and CCLR0 bits in TCR to have the counter cleared synchronously.

Set the STR bits in TSTR to 1 to start the synchronized counters.

Figure 10.26 Setup Procedure for Synchronization (Example)

Rev. 6.0, 09/02, page 362 of 876

Example of Synchronization: Figure 10.27 shows an example of synchron ization. Channels 0, 1,

and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing

by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The

timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by

compare match with GRB0. A three-phase PWM waveform is ou tput from pins TIOCA0, TIOCA1,

and TIOCA2. For further information on PWM mode, see section 10.4.4, PWM Mode.

TIOCA2

Time

TIOCA1

TIOCA0

GRA2

GRA1

GRB2

GRA0

GRB1

GRB0

Value of TCNT0 to TCNT2 Cleared by compare match with GRB0

H'0000

Figure 10.27 Synchronization (Example)

Rev. 6.0, 09/02, page 363 of 876

10.4.4 PWM Mode

In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.

GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which

the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a

PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can

be selected in all chan nels (0 to 4).

Table 10.4 summarizes the PWM output pins and corresponding registers. If the same value is set

in GRA and GRB, the output does not change when compare match occurs.

Table 10.4 PWM Output Pin s and Registers

Channel Output Pin 1 Output 0 Output

0TIOCA

0GRA0 GRB0

1TIOCA

1GRA1 GRB1

2TIOCA

2GRA2 GRB2

3TIOCA

3GRA3 GRB3

4TIOCA

4GRA4 GRB4

Rev. 6.0, 09/02, page 364 of 876

Sample Setup P r ocedure for PWM Mode: Figure 10.28 shows a sample pr ocedure for setting

up PWM mode.

PWM mode 1. Set bits TPSC2 to TPSC0 in TCR to

select the counter clock source. If an

external clock source is selected, set

bits CKEG1 and CKEG0 in TCR to

select the desired edge(s) of the

external clock signal.

PWM mode

Select counter clock 1

Select counter clear source 2

Set GRA 3

Set GRB 4

Select PWM mode 5

Start counter 6

2. Set bits CCLR1 and CCLR0 in TCR

to select the counter clear source.

3. Set the time at which the PWM

waveform should go to 1 in GRA.

4. Set the time at which the PWM

waveform should go to 0 in GRB.

5. Set the PWM bit in TMDR to select

PWM mode. When PWM mode is

selected, regardless of the TIOR

contents, GRA and GRB become

output compare registers specifying

the times at which the PWM output

goes to 1 and 0. The TIOCA pin

automatically becomes the PWM

output pin. The TIOCB pin conforms

to the settings of bits IOB1 and IOB0

in TIOR. If TIOCB output is not

desired, clear both IOB1 and IOB0 to 0.

6. Set the STR bit to 1 in TSTR to start

the timer counter.

Figure 10.28 Setup Procedure for PWM Mode (Example)

Rev. 6.0, 09/02, page 365 of 876

Examples of PWM Mode: Figure 10.29 shows examples of operation in PWM mode. In PWM

mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0

at compare match with GRB.

In the examples shown, TCNT is cleared by compare match with GRA or GRB. Synchronized

operation and free-running counting are also possible.

TCNT value Counter cleared by compare match with GRA

Time

GRA

GRB

TIOCA

a. Counter cleared by GRA

TCNT value Counter cleared by compare match with GRB

Time

GRB

GRA

TIOCA

b. Counter cleared by GRB

H'0000

Figure 10.29 PWM Mode (Example 1)

Rev. 6.0, 09/02, page 366 of 876

Figure 10.30 shows examples of the output of PWM waveforms with duty cycles of 0% and

100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value

than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB

is set to a higher value than GRA, the duty cycle is 100%.

TCNT value Counter cleared by compare match with GRB

Time

GRB

GRA

TIOCA

a. 0% duty cycle

TCNT value Counter cleared by compare match with GRA

Time

GRA

GRB

TIOCA

b. 100% duty cycle

Write to GRA Write to GRA

Write to GRB Write to GRB

H'0000

Figure 10.30 PWM Mode (Example 2)

Rev. 6.0, 09/02, page 367 of 876

10.4.5 Reset-Synchronized PWM Mode

In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of

complementary PWM waveforms, all having one waveform transition point in common.

When reset-synchronized PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4,

and TOCXB4 automatically become PWM output pins, and TCNT3 functions as an up-counter.

Table 10.5 lists the PWM output pins. Table 10.6 su mmarizes the register settings.

Table 10.5 Output Pins in Reset-Synchronized PWM Mode

Channel Output Pin Description

3TIOCA

3PWM output 1

TIOCB3PWM output 1´ (complementary waveform to PWM output 1)

4TIOCA

4PWM output 2

TOCXA4PWM output 2´ (complementary wa veform to PWM output 2)

TIOCB4PWM output 3

TOCXB4PWM output 3´ (complementary wa veform to PWM output 3)

Table 10.6 Register Settings in Reset-Synchronized PWM Mode

TCNT3 Initially set to H'0000

TCNT4 Not used (operates independently)

GRA3 Specifies the count period of TCNT3

GRB3 Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3

GRA4 Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4

GRB4 Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4

Rev. 6.0, 09/02, page 368 of 876

Sample Setup Procedure for Reset-Synchronized PWM Mode: Figure 10.31 shows a sample

procedure for setting up reset-synchronized PWM mode.

Reset-synchronized PWM mode 1. Clear the STR3 bit in TSTR to 0 to

halt TCNT3. Reset-synchronized

PWM mode must be set up while

TCNT3 is halted.

Reset-synchronized PWM mode

Stop counter 1

Select counter clock 2

Select counter clear source 3

Select reset-synchronized

PWM mode 4

Set TCNT 5

Set general registers 6

2. Set bits TPSC2 to TPSC0 in TCR to

select the counter clock source for

channel 3. If an external clock source

is selected, select the external clock

edge(s) with bits CKEG1 and CKEG0

in TCR.

3. Set bits CCLR1 and CCLR0 in TCR3

to select GRA3 compare match as

the counter clear source.

4. Set bits CMD1 and CMD0 in TFCR to

select reset-synchronized PWM mode.

TIOCA3, TIOCB3, TIOCA4, TIOCB4,

TOCXA4, and TOCXB4 automatically

become PWM output pins.

5. Preset TCNT3 to H'0000. TCNT4

need not be preset.

Start counter 7

6. GRA3 is the waveform period register.

Set the waveform period value in

GRA3. Set transition times of the

PWM output waveforms in GRB3,

GRA4, and GRB4. Set times within

the compare match range of TCNT3.

X GRA3 (X: setting value)

≤

7. Set the STR3 bit in TSTR to 1 to start

TCNT3.

Figure 10.31 Setup Procedure for Reset - Synchronized PWM Mode ( Ex ample)

Rev. 6.0, 09/02, page 369 of 876

Example of Reset-Synchronized PWM Mode: Figure 10.32 shows an example of operation in

reset-synchronized PWM mode. TCNT3 operates as an up-counter in this mode. TCNT4 operates

independently, detached from GRA4 and GRB4. When TCNT3 matches GRA3, TCNT3 is cleared

and resumes counting from H'0000. The PWM outputs toggle at compare match of TCNT3 with

GRB3, GRA4, and GRB4 respectively, and all toggle when the counter is cleared.

TCNT3 value Counter cleared at compare match with GRA3

Time

GRA3

GRB3

GRA4

GRB4

H'0000

TIOCA3

TIOCB3

TIOCA4

TOCXA4

TIOCB4

TOCXB4

Figure 10.32 Operation in Reset-Synchronized PWM Mode (Example)

(when OLS3 = O LS4 = 1)

For the settings and operation when reset-synchronized PWM mode and buffer mode are both

selected, see section 10.4.8, Buffering.

Rev. 6.0, 09/02, page 370 of 876

10.4.6 Complementary PWM Mode

In complementary PWM mode channels 3 and 4 are combined to output three pairs of

complementary, non-overlapping PWM waveforms.

When complementary PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and

TOCXB4 automatically become PWM output pins, and TCNT3 and TCNT4 function as up/down-

counters.

Table 10.7 lists the PWM output pins. Table 10.8 su mmarizes the register settings.

Table 10. 7 Output Pins in Co mplementary PWM Mode

Channel Output Pin Description

3TIOCA

3PWM output 1

TIOCB3PWM output 1´ (non-overlapping complementary waveform

to PWM output 1)

4TIOCA

4PWM output 2

TOCXA4PWM output 2´ (non-overlapping complementary waveform

to PWM output 2)

TIOCB4PWM output 3

TOCXB4PWM output 3´ (non-overlapping complementary waveform

to PWM output 3)

Table 10. 8 Register Setting s in Complementar y PWM Mode

TCNT3 Initially specifies the non-overlap margin (difference to TCNT4)

TCNT4 Initially set to H'0000

GRA3 Specifies the upper limit value of TCNT3 minus 1

GRB3 Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3

GRA4 Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4

GRB4 Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4

Rev. 6.0, 09/02, page 371 of 876

Setup Procedure for Complementary P WM Mode: Figure 10.33 shows a sample procedure for

setting up complementary PWM mode.

Complementary PWM mode 1. Clear bits STR3 and STR4 to 0 in

TSTR to halt the timer counters.

Complementary PWM mode must be

set up while TCNT3 and TCNT4 are

halted.

Complementary PWM mode

Stop counting 1

Select counter clock 2

Select complementary

PWM mode 3

Set TCNTs 4

Set general registers 5

Start counters 6

2. Set bits TPSC2 to TPSC0 in TCR to

select the same counter clock source

for channels 3 and 4. If an external

clock source is selected, select the

external clock edge(s) with bits

CKEG1 and CKEG0 in TCR. Do not

select any counter clear source

with bits CCLR1 and CCLR0 in TCR.

3. Set bits CMD1 and CMD0 in TFCR

to select complementary PWM mode.

TIOCA

, TIOCB

, TIOCA

, TIOCB

TOCXA

, and TOCXB

automatically

become PWM output pins.

4. Clear TCNT4 to H'0000. Set the

non-overlap margin in TCNT3. Do not

set TCNT3 and TCNT4 to the same

value.

5. GRA3 is the waveform period

TCNT3 minus 1 in GRA3. Set

transition times of the PWM output

waveforms in GRB3, GRA4, and

GRB4. Set times within the compare

match range of TCNT3 and TCNT4.

T X (X: initial setting of GRB3,

GRA4, or GRB4. T: initial setting of

TCNT3)

≤

6. Set bits STR3 and STR4 in TSTR to

1 to start TCNT3 and TCNT4.

Note: After exiting complementary PWM mode, to resume operating in complementary

PWM mode, follow the entire setup procedure from step 1 again.

Figure 10.33 Setup Procedure for Complementary PWM Mode (Example)

Rev. 6.0, 09/02, page 372 of 876

Clearing Procedure for Complementary PWM Mode: Figure 10.34 shows the steps to clear

complementary PWM mode.

Complementary PWM mode 1. Clear the CMD1 bit of TFCR to 0 to

set channels 3 and 4 to normal

operating mode.

Normal operating mode

Clear complementary PWM mode 1

Stop counter operation 2

2. After setting channels 3 and 4 to

normal operating mode, wait at least

one counter clock period, then clear

bits STR3 and STR4 of TSTR to 0 to

stop counter operation of TCNT3 and

TCNT4.

Figure 10.34 Clearing Procedure for Complementary PWM Mode

Rev. 6.0, 09/02, page 373 of 876

Examples of Complementary PWM Mode: Figure 10.35 shows an example of operation in

complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down

from compare match between TCNT3 and GRA3 and counting up from the point at which TCNT4

underflows. During each up-and-down counting cycle, PWM waveforms are generated by

compare m a tch with general registers GRB3, GRA4, and GRB4. Since TCNT3 is initially set to a

higher value than TCNT4, compare match events occur in the sequence TCNT3, TCNT4, TCNT4,

TCNT3.

TCNT3 and

TCNT4 values Down-counting starts at compare

match between TCNT3 and GRA3

Time

GRA3

GRB3

GRA4

GRB4

H'0000

TIOCA

TIOCB

TIOCA

TOCXA

TIOCB

TOCXB

TCNT3

TCNT4

Up-counting starts when

TCNT4 underflows

Figure 10.35 Operation in Complementary PWM Mode (Example 1, OLS3 = OLS4 = 1)

Rev. 6.0, 09/02, page 374 of 876

Figure 10.36 shows examples of waveforms with 0% and 100% duty cycles (in on e phase) in

complementary PWM mode. In this example the outputs change at compare match with GRB3, so

waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larger than

GRA3. The duty cycle can be changed easily during operation by use of the buffer registers. For

further information see section 10.4.8, Buffering.

TCNT3 and

TCNT4 values

Time

GRA3

GRB3

TIOCA

TIOCB

0% duty cycle

a. 0% duty cycle

TCNT3 and

TCNT4 values

Time

GRA3

GRB3

TIOCA

TIOCB

100% duty cycle

b. 100% duty cycle

H'0000

Figure 10.36 Operation in Complementary PWM Mode (Example 2, OLS3 = OLS4 = 1)

Rev. 6.0, 09/02, page 375 of 876

In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions

between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3 and

the OVF bit in chan nel 4 differ from the usual conditions. In buffered oper ation the buffer transfer

conditions also differ. Timing diagrams are shown in figures 10.37 and 10.38.

TCNT3

GRA3

IMFA

Buffer transfer

signal (BR to GR)

N – 1 N N + 1 N N – 1

Set to 1

Flag not set

No buffer transfer

Buffer transfer

Figure 10.37 Overshoot Timing

Rev. 6.0, 09/02, page 376 of 876

TCNT4

OVF

Buffer transfer

signal (BR to GR)

H'0001 H'0000 H'FFFF H'0000

Set to 1

Flag not set

No buffer transfer

Buffer transfer

Underflow Overflow

Figure 10.38 Undershoot Timing

In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when

an underflow occurs. When buffering is selected, buffer register contents are transferred to the

general register at compare match A3 during up-counting, and when TCNT4 underflows.

General Register Settings in Complementary PWM Mode: When setting up general registers

for complementary PWM mode or changing their settings during operation, note the following

points.

• Initial settings

Do not set valu es f rom H'0000 to T – 1 (where T is the initial value of TCNT3). Af ter the

counters start and the first compare match A3 event has occurred, however, settings in this

range also become po ssible.

• Changing settings

Use the buffer registers. Correct waveform output may not be obtained if a general register is

written to directly.

• Cautions on changes of general register settings

Figure 10.39 shows six correct examples and one incorrect example.

Rev. 6.0, 09/02, page 377 of 876

GRA3

H'0000

Not allowed

Figure 10.39 Changing a General Register Setting by Buffer Transfer (Example 1)

 Buffer transfer at transition from up-counting to down-countin g

If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a

buffer register value outside this range. Conversely, if the general register value is outside

this range, do not transfer a value within this range. See figure 10.40.

GRA3 + 1

GRA3

GRA3 – T + 1

GRA3 – T

Illegal changes

TCNT3

TCNT4

Figure 10.40 Changing a General Register Setting by Buffer Transfer (Caution 1)

 Buffer transfer at transition from down-counting to up-countin g

If the general register valu e is in the range from H'0000 to T – 1, do not transfer a buffer

range, do not transfer a value within this range. See figure 10.41.

Rev. 6.0, 09/02, page 378 of 876

T – 1

H'0000

H'FFFF

Illegal changes

TCNT3

TCNT4

Figure 10.41 Changing a General Register Setting by Buffer Transfer (Caution 2)

 General register settings outside the counting range (H'0000 to GRA3)

Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to

a value outside the counting range. When a buffer register is set to a value outside the

counting rang e, then later restored to a value within the counting range, the counting

direction (up or down) must be the same both times. See figure 10.42.

0% duty cycle 100% duty cycle

Write during down-counting Write during up-counting

GRA3

H'0000

Output pin

Figure 10.42 Changing a General Register Setting by Buffer Transfer (Example 2)

Settings can be made in this way by detecting GRA3 compare match or TCNT4 underflow

before writing to the buffer register. They can also be made by using GRA3 compare match

to activate the DMAC.

Rev. 6.0, 09/02, page 379 of 876

10.4.7 Phase Counting Mode

In phase counting mode the phase difference between two external clock inputs (at the TCLKA

and TCLKB pins) is detected, and TCNT2 counts up or down accordingly.

In phase countin g mode, the TCLKA and TCLKB pins automatically function as external clock

input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to

TPSC0, CKEG1, and CKEG0 in TCR2. Settings of bits CCLR1, CCLR0 in TCR2, and settings in

TIOR2, TIER2, TSR2, GRA2, and GRB2 are valid. The input capture and output compare

functions can be used, and interrupts can be generated.

Phase counting is available only in chann e l 2.

Sample Setup P rocedure for Phase Counting Mode: Figure 10.43 shows a sample procedure

for setting up phase counting mode.

Phase counting mode

Select phase counting mode

Select flag setting condition

Start counter

Phase counting mode

Set the MDF bit in TMDR to 1 to select

phase counting mode.

Select the flag setting condition with

the FDIR bit in TMDR.

Set the STR2 bit to 1 in TSTR to start

the timer counter.

Figure 10.43 Setup Procedure for Phase Co unt ing Mode (Example)

Rev. 6.0, 09/02, page 380 of 876

Example of Phase Counting Mode: Figure 10.44 shows an example of operations in phase

counting mode. Table 10.9 lists the up-counting and down-counting conditions for TCNT2.

In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted . The

phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must

also be at least 1.5 states, and the pulse width must be at least 2.5 states. See figure 10.45.

TCNT2 value

Counting up Counting down

Time

TCLKB

TCLKA

Figure 10.44 Operation in Phase Counting Mode (Example)

Table 10.9 Up/Down Counting Condit ions

Counting Direction Up-Counting Down-Counting

TCLKB ↑High ↓Low High ↓Low ↑

TCLKA Low ↑High ↓↓Low ↑High

TCLKA

TCLKB

Phase

difference Phase

difference Pulse width Pulse width

Overlap Overlap

Phase difference and overlap:

Pulse width: at least 1.5 states

at least 2.5 states

Figure 10.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

Rev. 6.0, 09/02, page 381 of 876

10.4.8 Buffering

Buffering operates differently depending on whether a general register is an output compare

and complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering

operations under the conditions mentioned above are described next.

• General register used for output compare

The buffer register value is transferred to the general register at compare match.

See figure 10.46.

Compare match signal

Comparator TCNTGRBR

Figure 10.46 Compare Match Buffering

• General register used for input capture

The TCNT value is transferred to the general register at input capture. The previous general

See figure 10.47.

Input capture signal

BR GR TCNT

Figure 10.47 Input Capture Buffering

Rev. 6.0, 09/02, page 382 of 876

• Complementary PWM mode

The buffer register value is transferred to the general register when TCNT3 and TCNT4

change countin g direction. This occurs at the following two times:

 When TCNT3 compare matches GRA3

 When TCNT4 underflows

• Reset-synchronized PWM mode

The buffer register value is transferred to the general register at compare match A3.

Sample Buffering Set up Procedure: Figure 10.48 shows a sample buffering setup procedure.

Buffering

Select general register functions

Set buffer bits

Start counters

Buffered operation

11.

Set TIOR to select the output compare or input

capture function of the general registers.

Set bits BFA3, BFA4, BFB3, and BFB4 in TFCR

to select buffering of the required general registers.

Set the STR bits to 1 in TSTR to start the timer

counters.

Figure 10.48 Buffering Setup Procedure (Example)

Rev. 6.0, 09/02, page 383 of 876

Examples of Buffering: Figure 10.49 shows an example in which GRA is set to function as an

output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by

GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B.

Because of the buffer setting, when TIOCA toggles at compare match A, the BRA value is

simultaneously transferred to GRA. This operation is repeated each time compare match A occurs.

Figure 10.50 shows the transfer timing.

GRB

H'0250

H'0200

H'0100

H'0000

BRA

GRA

TIOCB

TIOCA

TCNT value Counter cleared by compare match B

Time

Toggle

output

Toggle

output

Compare match A

H'0200

H'0250

H'0100

H'0200 H'0100

H'0200

Figure 10.49 Register Buffering (Example 1: Buffering of Output Compare Register)

Rev. 6.0, 09/02, page 384 of 876

TCNT

Compare

match signal

Buffer transfer

signal

n n + 1

Figure 10.50 Compare Match and Buffer Transfer Timing (Example)

Rev. 6.0, 09/02, page 385 of 876

Figure 10.51 shows an example in which GRA is set to function as an input capture register

buffered by BRA, and TCNT is cleared by input capture B. The falling ed ge is selected as the

input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because

of the buffer setting, when the TCNT value is captured in to GRA at input capture A, the previous

GRA value is simu ltaneously transf erred to BRA. Figu r e 10 .52 shows the transfer timing.

H'0180

H'0160

H'0005

H'0000

TIOCB

TIOCA

GRA

BRA

GRB

H'0005

H'0160

H'0005

H'0180

TCNT value Counter cleared by

input capture B

Time

Input capture A

H'0160

Figure 10.51 Register Buffering (Exa mple 2 : Buffering of Input Capture Register)

Rev. 6.0, 09/02, page 386 of 876

TCNT

TIOC pin

Input capture

signal

nn + 1 N

N + 1

Figure 10. 52 Input Capture and Buff er Transfer Timing (Example)

Rev. 6.0, 09/02, page 387 of 876

Figure 10.53 shows an example in which GRB3 is buffered by BRB3 in complem e ntary PWM

mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform

with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and

when TCNT4 underflows.

TCNT3 and

TCNT4 values

Time

GRA3

H'0999

H'0000

TCNT3

TCNT4

GRB3

H'1FFF

BRB3

GRB3

TIOCA

TIOCB

H'0999

H'0999 H'0999

H'1FFF H'0999

H'1FFF H'1FFF H'0999

Figure 10.53 Register Buffering (Example 3: Buffering in Complementary PWM Mode)

Rev. 6.0, 09/02, page 388 of 876

10.4.9 ITU Output Timing

The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external

trigger, or in verted by bit settings in TOCR.

Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is

disabled by clearing a master enable bit to 0 in TOER. An arbitrary value can be output by

appropriate settings of the data register (DR) and data direction register (DDR) of the

corresponding input/outpu t por t. Figure 10.54 illustrates the timing of the enablin g and disabling

of ITU output by TOER.

Address bus

TOER

ITU output pin

TOER address

Timer output I/O port

Generic input/outputITU output

Figure 10.54 Timing of Disabling of ITU Output by Writing to TOER (Example)

Rev. 6.0, 09/02, page 389 of 876

Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in

TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture

A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU

output. Figure 10.55 shows the timing.

TIOCA1 pin

TOER

ITU output I/O port ITU output I/O port

Generic

input/output Generic

input/output

ITU outputITU output

Input capture

signal

ITU output

pins

NNH'C0 H'C0

N: Arbitrary setting (H'C1 to H'FF)

Figure 10.55 Timing of Disabling of ITU Output by External Trigger (Example)

Timing o f Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and

complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and

OLS3) in TOCR. Figure 10.56 shows the timing.

Address bus

TOCR

ITU output pin

TOCR address

Inverted

Figure 10.56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example)

Rev. 6.0, 09/02, page 390 of 876

10.5 Interrupts

The ITU has two type s of interrupts: input capture/compare match inter rup ts, and overflow

interrupts.

10.5.1 Setting of Status Flags

Timing o f Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a

compare match signal generated when TCNT matches a general register (GR). The compare match

signal is generated in the last state in which the values match (when TCNT is updated from the

matching count to the next count). Therefore, when TCNT matches a general register, the compare

match sign al is not generated until the next timer clock input. Fig ure 10.57 shows the timing of the

setting of IMFA and IMFB.

TCNT

IMF

IMI

TCNT input

clock

Compare

match signal

N N + 1

Figure 10.57 Timing of Setting of IMFA and IMFB by Compare Match

Rev. 6.0, 09/02, page 391 of 876

Timing of Setting of IMF A and IMFB by Input Capture: IMFA and IMFB are set to 1 by an

input capture signal. The TCNT contents are simultaneously transferred to the corresponding

general register. Figure 10.58 shows the timing.

Input capture

signal

IMF

TCNT

IMI

Figure 10. 58 Timing of Setting of IMFA and IMFB by Input Capture

Rev. 6.0, 09/02, page 392 of 876

Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from

H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 10.59 shows the timing.

Overflow

signal

H'FFFF H'0000

TCNT

OVF

OVI

Figure 10.59 Timing of Setting of OVF

10.5.2 Clearing of Status Flags

If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is

cleared. Figure 10.60 shows the timing.

Address

IMF, OVF

TSR write cycle

TSR address

Figure 10.60 Timing of Clearing of Status Flags

Rev. 6.0, 09/02, page 393 of 876

10.5.3 Interrupt Sources and DMA Controller Activation

Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input

capture B interr upt, and an overflow interrupt. In total there are 15 interrupt sour ces, all

independently vectored. An interrupt is requested when the interrupt request flag and interrupt

enable bit are both set to 1.

The priority order of the channels can be modified in interrupt priority registers A and B (IPRA

and IPRB). Fo r details see section 5, Interrupt Controller.

Compare ma tch/input capture A interrupts in ch anne ls 0 to 3 can activate the DMA controller

(DMAC). When the DMAC is activated a CPU interrupt is not requested.

Table 10.10 lists the interrupt sources.

Table 10.10 ITU Interrupt Sources

Channel Interrupt

Source Description DMAC

Activatable Priority*

0 IMIA0 Compare match/input capture A0 Yes

IMIB0 Compare match/input capture B0 No

OVI0 Overflow 0 No

1 IMIA1 Compare match/input capture A1 Yes

IMIB1 Compare match/input capture B1 No

OVI1 Overflow 1 No

2 IMIA2 Compare match/input capture A2 Yes

IMIB2 Compare match/input capture B2 No

OVI2 Overflow 2 No

3 IMIA3 Compare match/input capture A3 Yes

IMIB3 Compare match/input capture B3 No

OVI3 Overflow 3 No

4 IMIA4 Compare match/input capture A4 No

IMIB4 Compare match/input capture B4 No

OVI4 Overflow 4 No

High

↑



Low

Note: *The priority immediately after a reset is indicated. Inter-channel priorities can be changed

by settings in IPRA and IPRB.

Rev. 6.0, 09/02, page 394 of 876

10.6 Usage Notes

This section describes contention and other matters requiring special attention during ITU

operations.

Contention between TCNT Write and Clear: If a counter clear signal occurs in the T3 state of a

TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure

10.61.

Address bus

Internal write signal

Counter clear signal

TCNT

TCNT write cycle

TCNT address

N H'0000

T1T2T3

Figure 10.61 Contention between TCNT Write and Clear

Rev. 6.0, 09/02, page 395 of 876

Contention between TCNT Word Write and Increment: If an increment pulse occurs in the T3

state of a TCNT word wr ite cycle, writing takes priority and TCNT is n ot incremented. See figure

10.62.

Address bus

Internal write signal

TCNT input clock

TCNT N

TCNT address

TCNT write data

TCNT word write cycle

T1T2T3

Figure 10.62 Contention between TCNT Word Write and Increment

Rev. 6.0, 09/02, page 396 of 876

Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T2

or T3 state of a TCNT byte write cycle, writing takes prio rity and TCNT is not incremented. The

TCNT byte that was no t wr itten retains its previo us value. See figure 10.63, which shows an

increment pulse occurring in the T2 state of a byte write to TCNTH.

Address bus

Internal write signal

TCNT input clock

TCNTH

TCNTL

TCNTH byte write cycle

T1T2T3

TCNTH address

TCNT write data

XXX + 1

Figure 10.63 Contention between TCNT Byte Write and Increment

Rev. 6.0, 09/02, page 397 of 876

Contention between General Register Write and Compare Match: If a compare match occurs

in the T3 state of a general register write cycle, writing takes priority and the compare match signal

is inhibited. See figure 10.64.

Address bus

Internal write signal

TCNT

Compare match signal

General register write cycle

GR address

N N + 1

General register write data

Inhibited

Figure 10.64 Contention between General Register Write and Compare Match

Rev. 6.0, 09/02, page 398 of 876

Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T3

state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set

to 1. The same holds for underflow. See figure 10.65.

Address bus

Internal write signal

TCNT input clock

Overflow signal

TCNT

OVF

H'FFFF

TCNT address

TCNT write data

TCNT write cycle

T1T2T3

Figure 10.65 Contention between TCNT Write and Overflow

Rev. 6.0, 09/02, page 399 of 876

Contention between General Register Read and Input Capture: If an input capture signal

occurs during th e T3 state of a general register read cycle, the value before input capture is read.

See figure 10.66.

Address bus

Internal read signal

Input capture signal

Internal data bus

GR address

General register read cycle

T1T2T3

Figure 10.66 Contention between Genera l Register Read and Input Capture

Rev. 6.0, 09/02, page 400 of 876

Contention between Counter Clearing by Input Capture and Counter Increment: If an input

capture signal and counter increment signal occu r simultaneously, the counter is cleared according

to the input capture signal. The counter is not incremented by the increment signal. The value

before the counter is cleared is transferred to the general register. See figure 10.67.

Input capture signal

Counter clear signal

TCNT input clock

TCNT

GR N

N H'0000

Figure 10.67 Contention between Counter Clearing by Input Capture and Counter

Increment

Rev. 6.0, 09/02, page 401 of 876

Contention between General Register Write and Input Capture: If an input cap ture signal

occurs in the T3 state of a general register write cycle, input capture takes priority and the write to

the general register is not performed. See figure 10.68.

Address bus

Internal write signal

Input capture signal

TCNT

GR M

GR address

General register write cycle

Figure 10.68 Contention between Genera l Register Write and Input Capture

Note on Waveform Period Setting: When a counter is cleared by co mpare match, the counter is

cleared in the last state at which the TCNT value matches the general register value, at the time

when this value would normally be updated to the next count. The actual counter frequency is

therefore given by the following formula:

f = φ

(N + 1)

(f: counter frequency. φ: system clock frequency. N: value set in general register.)

Rev. 6.0, 09/02, page 402 of 876

Contention between Buf fer Register Write and Input Capture: If a buffer register is used for

input capture buffering and an input capture signal occurs in the T3 state of a write cycle, input

capture takes priority and the write to th e buffer register is not performed. See figure 10.69.

Address bus

Internal write signal

Input capture signal

BR address

Buffer register write cycle

TCNT value

Figure 10.69 Contention between Buffer Register Write and Input Capture

Rev. 6.0, 09/02, page 403 of 876

Note on Synchro nous Preset: When channels are synchronized, if a TCNT value is modified by

byte write access, all 16 bits of all synchronized counters assume the same value as the counter

that was ad dressed.

Example: When channels 2 and 3 are synchronized

• Byte write to channel 2 or byte write to channel 3

TCNT2

TCNT3

TCNT2

TCNT3

TCNT2

TCNT3

TCNT2

TCNT3

TCNT2

TCNT3

• Word write to channel 2 or word write to channel 3

Upper byte Lower byte

Write A to upper byte

of channel 2

Write A to lower byte

of channel 3

Write AB word to

channel 2 or 3

Note on Setup of Reset-Synchro nized P WM Mode and Complementary P WM Mode: When

setting bits CMD1 and CMD0 in TFCR, take the following precautions:

• Write to bits CMD1 and CMD0 only when TCNT3 and TCNT4 are stopped.

• Do not switch directly between reset-synchronized PWM mode and complementary PWM

mode. First switch to normal mode (by clearing bit CMD1 to 0), then select reset-synchronized

PWM mode or complementary PWM mode.

Rev. 6.0, 09/02, page 404 of 876

ITU Operating Modes

Table 10.11 (a) ITU Operat ing Modes (Channel 0)

Operating Mode

TSNC TMDR TFCR TOCR TOER TIOR0 TCR0

Synchro-

nization MDF FDIR PWM Comple-

mentary

PWM

Reset-

Synchro-

nized

PWM

Buffer-

ing XTGD Output

Level

Select

Master

Enable IOA IOB Clear

Select Clock

Select

Synchronous preset

PWM mode

Output compare A

Output compare B

Input capture A

Input capture B

Counter

clearing By compare

match/input

capture A

By compare

match/input

capture B

Syn-

chronous

clear

Legend: : Setting available (valid).

—: Setting does not affect this mode.

Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.

SYNC0 = 1

—

PWM0 = 1

PWM0 = 0

—

IOA2 = 0

Other bits

unrestricted

IOA2 = 1

Other bits

unrestricted

IOB2 = 0

Other bits

unrestricted

IOB2 = 1

Other bits

unrestricted

CCLR1 = 0

CCLR0 = 1

CCLR1 = 1

CCLR0 = 0

CCLR1 = 1

CCLR0 = 1

Rev. 6.0, 09/02, page 405 of 876

Table 10.11 (b) ITU Operating Modes (Channel 1)

Operating Mode

TSNC TMDR TFCR TOCR TOER TIOR1 TCR1

Synchro-

nization MDF FDIR PWM Comple-

mentary

PWM

Reset-

Synchro-

nized

PWM

Buffer-

ing XTGD Output

Level

Select

Master

Enable IOA IOB Clear

Select Clock

Select

Synchronous preset

PWM mode

Output compare A

Output compare B

Input capture A

Input capture B

Counter

clearing By compare

match/input

capture A

By compare

match/input

capture B

Syn-

chronous

clear

SYNC1 = 1

—

PWM1 = 1

PWM1 = 0

—

IOA2 = 0

Other bits

unrestricted

IOA2 = 1

Other bits

unrestricted

IOB2 = 0

Other bits

unrestricted

IOB2 = 1

Other bits

unrestricted

CCLR1 = 0

CCLR0 = 1

CCLR1 = 1

CCLR0 = 0

CCLR1 = 1

CCLR0 = 1

Legend: : Setting available (valid).

—: Setting does not affect this mode.

Notes: *1 The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.

*2 Valid only when channels 3 and 4 are operating in complementary PWM mode or reset-synchronized PWM mode.

Rev. 6.0, 09/02, page 406 of 876

Table 10.11 (c) ITU Operating Modes (Channel 2)

Operating Mode

TSNC TMDR TFCR TOCR TOER TIOR2 TCR2

Synchro-

nization MDF FDIR PWM Comple-

mentary

PWM

Reset-

Synchro-

nized

PWM

Buffer-

ing XTGD Output

Level

Select

Master

Enable IOA IOB Clear

Select Clock

Select

Synchronous preset

PWM mode

Output compare A

Output compare B

Input capture A

Input capture B

Counter

clearing By compare

match/input

capture A

By compare

match/input

capture B

Syn-

chronous

clear

Legend: : Setting available (valid).

—: Setting does not affect this mode.

Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.

SYNC2 = 1

—

PWM2 = 1

PWM2 = 0

—

IOA2 = 0

Other bits

unrestricted

IOA2 = 1

Other bits

unrestricted

IOB2 = 0

Other bits

unrestricted

IOB2 = 1

Other bits

unrestricted

CCLR1 = 0

CCLR0 = 1

CCLR1 = 1

CCLR0 = 0

CCLR1 = 1

CCLR0 = 1

Phase counting

mode MDF = 1 —————— —

Rev. 6.0, 09/02, page 407 of 876

Table 10.11 (d) ITU Operating Modes (Channel 3)

Operating Mode TSNC TMDR TFCR TOCR TOER TIOR3 TCR3

Synchro-

nization MDF FDIR PWM Comple-

mentary

PWM

Reset-

Synchro-

nized

PWM

Buffer-

ing XTGD Output

Level

Select

Master

Enable IOA IOB Clear

Select Clock

Select

Synchronous preset

PWM mode

Output compare A

Output compare B

Input capture A

Input capture B

Counter

clearing By compare

match/input

capture A

Complementary

PWM mode

Reset-synchronized

PWM mode

Buffering

(BRA)

Buffering

(BRB)

By compare

match/input

capture B

Syn-

chronous

clear

SYNC3 = 1

—

PWM3 = 1

PWM3 = 0

—

CMD1 = 0

Illegal setting:

CMD1 = 1

CMD0 = 0

CMD1 = 0

Illegal setting:

CMD1 = 1

CMD0 = 0

CMD1 = 1

CMD0 = 0

CMD1 = 1

CMD0 = 1

CMD1 = 0

CMD1 = 1

CMD0 = 0

CMD1 = 1

CMD0 = 1 BFA3 = 1

Other bits

unrestricted

BFA3 = 1

Other bits

unrestricted

—

EA3 ignored

Other bits

unrestricted

EB3 ignored

Other bits

unrestricted

IOA2 = 0

Other bits

unrestricted

IOA2 = 1

Other bits

unrestricted

IOB2 = 0

Other bits

unrestricted

IOA2 = 1

Other bits

unrestricted CCLR1 = 0

CCLR0 = 1

CCLR1 = 1

CCLR0 = 0

CCLR1 = 1

CCLR0 = 1

CCLR1 = 0

CCLR0 = 0

CCLR1 = 0

CCLR0 = 1

—

——

Legend: : Setting available (valid).

—: Setting does not affect this mode.

Notes: *1 Master enable bit settings are valid only during waveform output.

*2 The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.

*3 Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.

*4 The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected.

*5 In complementary PWM mode, select the same clock source for channels 3 and 4.

*6 Use the input capture A function in channel 1.

Rev. 6.0, 09/02, page 408 of 876

Table 10.11 (e) ITU Operating Modes (Channel 4)

Operating Mode TSNC TMDR TFCR TOCR TOER TIOR4 TCR4

Synchro-

nization MDF FDIR PWM Comple-

mentary

PWM

Reset-

Synchro-

nized

PWM

Buffer-

ing XTGD Output

Level

Select

Master

Enable IOA IOB Clear

Select Clock

Select

Synchronous preset

PWM mode

Output compare A

Output compare B

Input capture A

Input capture B

Counter

clearing By compare

match/input

capture A

Complementary

PWM mode

Reset-synchronized

PWM mode

Buffering

(BRA)

Buffering

(BRB)

By compare

match/input

capture B

Syn-

chronous

clear

SYNC4 = 1

—

PWM4 = 1

PWM4 = 0

—

CMD1 = 0

Illegal setting:

CMD1 = 1

CMD0 = 0

Illegal setting:

CMD1 = 1

CMD0 = 0

CMD1 = 1

CMD0 = 0

CMD1 = 1

CMD0 = 1

CMD1 = 0

CMD1 = 1

CMD0 = 0

CMD1 = 1

CMD0 = 1 BFA4 = 1

Other bits

unrestricted

BFA4 = 1

Other bits

unrestricted

—

EA4 ignored

Other bits

unrestricted

EB4 ignored

Other bits

unrestricted

IOA2 = 0

Other bits

unrestricted

IOA2 = 1

Other bits

unrestricted

IOB2 = 0

Other bits

unrestricted

IOA2 = 1

Other bits

unrestricted CCLR1 = 0

CCLR0 = 1

CCLR1 = 1

CCLR0 = 0

CCLR1 = 1

CCLR0 = 1

CCLR1 = 0

CCLR0 = 0

—

——

Illegal setting:

CMD1 = 1

CMD0 = 0

*6*6

Legend: : Setting available (valid).

—: Setting does not affect this mode.

Notes: *1 Master enable bit settings are valid only during waveform output.

*2 The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.

*3 Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.

*4 When reset-synchronized PWM mode is selected, TCNT4 operates independently and the counter clearing function is available. Waveform output is not affected.

*5 In complementary PWM mode, select the same clock source for channels 3 and 4.

*6 TCR4 settings are valid in reset-synchronized PWM mode, but TCNT4 operates independently, without affecting waveform output.

Rev. 6.0, 09/02, page 409 of 876

Section 11 Programmable Timing Pattern Controller

11.1 Overview

The H8/3048 Ser ies has a built-in program m able timing pattern controller (T PC) that provides

pulse outputs by using the 16-bit integrated timer unit (ITU) as a time base. The TPC pulse

outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and

independently.

11.1.1 Features

TPC features are listed below.

• 16-bit output data

Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis.

• Four output groups

Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit

outputs.

• Selectable output trigger signals

Output trigger signals can be selected for each group from the compare-match signals of four

ITU channels.

• Non-overlap mode

A non-overlap margin can be provided between pulse outputs.

• Can operate to gether with the DMA controller (DMAC)

The compare-match signals selected as trigger signals can activate the DMAC for sequential

output of d ata without CPU intervention.

Rev. 6.0, 09/02, page 410 of 876

11.1.2 Block Diagram

Figure 11.1 shows a block diagram of the TPC.

PADDR

NDERA

TPMR

PBDDR

NDERB

TPCR

Internal

data bus

Control logic

ITU compare match signals

Pulse output

pins, group 3

PBDR

PADR

Legend

TPMR:

TPCR:

NDERB:

NDERA:

PBDDR:

PADDR:

NDRB:

NDRA:

PBDR:

PADR:

Pulse output

pins, group 2

Pulse output

pins, group 1

Pulse output

pins, group 0

TPC output mode register

TPC output control register

Next data enable register B

Next data enable register A

Port B data direction register

Port A data direction register

Next data register B

Next data register A

Port B data register

Port A data register

NDRB

NDRA

Figure 11.1 TPC Block Diagram

Rev. 6.0, 09/02, page 411 of 876

11.1.3 TPC Pins

Table 11.1 summarizes the TPC output pins.

Table 11.1 TPC Pins

Name Symbol I/O Function

TPC output 0 TP0Output Group 0 pulse output

TPC output 1 TP1Output

TPC output 2 TP2Output

TPC output 3 TP3Output

TPC output 4 TP4Output Group 1 pulse output

TPC output 5 TP5Output

TPC output 6 TP6Output

TPC output 7 TP7Output

TPC output 8 TP8Output Group 2 pulse output

TPC output 9 TP9Output

TPC output 10 TP10 Output

TPC output 11 TP11 Output

TPC output 12 TP12 Output Group 3 pulse output

TPC output 13 TP13 Output

TPC output 14 TP14 Output

TPC output 15 TP15 Output

Rev. 6.0, 09/02, page 412 of 876

11.1.4 Registers

Table 11.2 summarizes the TPC registers.

Table 11.2 TPC Registers

Address*1Name Abbreviation R/W Initial Value

H'FFD1 Port A data direction register PADDR W H'00

H'FFD3 Port A data register PADR R/(W)*2H'00

H'FFD4 Port B data direction register PBDDR W H'00

H'FFD6 Port B data register PBDR R/(W)*2H'00

H'FFA0 TPC output mode register TPMR R/W H'F0

H'FFA1 TPC output control register TPCR R/W H'FF

H'FFA2 Next data enable register B NDERB R/W H'00

H'FFA3 Next data enable register A NDERA R/W H'00

H'FFA5/

H'FFA7*3Next data register A NDRA R/W H'00

H'FFA4

H'FFA6*3Next data register B NDRB R/W H'00

Notes: *1 Lower 16 bits of the address.

*2 Bits us ed for TPC output cannot be written.

*3 The NDRA address is H'FFA5 when the same output trigger is selected for TPC output

groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA

address is H'FFA7 for group 0 and H'FFA5 for group 1. Similarly, the address of NDRB

is H'FFA4 when the same output trigger is selected for TPC output groups 2 and 3 by

settings in TPCR. When the output triggers are different, the NDRB address is H'FFA6

for group 2 and H'FFA4 for group 3.

Rev. 6.0, 09/02, page 413 of 876

11.2 Register Descriptions

11.2.1 Port A Data Direction Register (PADDR)

PADDR is an 8-bit write-only register that selects input or output for each pin in port A.

Bit

Initial value

Read/Write

PA DDR

Port A data direction 7 to 0

These bits select input or

output for port A pins

PA DDR

Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must

be set to 1. For further information about PADDR, see section 9.11, Port A.

11.2.2 P o rt A Data Register (PADR)

PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when

these TPC output groups are used.

Bit

Initial value

Read/Write

R/(W)

Port A data 7 to 0

These bits store output data

for TPC output groups 0 and 1

********

Note: Bits selected for TPC output by NDERA settings become read-only bits.*

For further in formation about PADR, see section 9.11, Port A.

Rev. 6.0, 09/02, page 414 of 876

11.2.3 Port B Data Direction Register (PBDDR)

PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.

Bit

Initial value

Read/Write

PB DDR

Port B data direction 7 to 0

These bits select input or

output for port B pins

PB DDR

Port B is multip lexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must

be set to 1. For further information about PBDDR, see section 9.12, Port B.

11.2.4 Port B Data Register (PBDR)

PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when

these TPC output groups are used.

Bit

Initial value

Read/Write

R/(W)

Port B data 7 to 0

These bits store output data

for TPC output groups 2 and 3

********

Note: Bits selected for TPC output by NDERB settings become read-only bits.*

For further in formation about PBDR, see section 9.12, Port B.

Rev. 6.0, 09/02, page 415 of 876

11.2.5 Nex t Da ta Register A (NDRA)

NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups

1 and 0 (pins TP7 to TP0). During TPC output, when an ITU compare match event specified in

TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of

NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or

different output triggers.

NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by

the same compare match event, the NDRA address is H'FFA5. The upper 4 bits belong to group 1

and the lower 4 bits to group 0. Address H'FFA7 consists entirely of reserved bits that cannot be

modified and are always read as 1.

Address H'FFA5

Bit

Initial value

Read/Write

NDR7

R/W

NDR6

R/W

NDR5

R/W

NDR4

R/W

NDR3

R/W

NDR2

R/W

NDR1

R/W

NDR0

R/W

Next data 3 to 0

These bits store the next output

data for TPC output group 0

Next data 7 to 4

These bits store the next output

data for TPC output group 1

Address H'FFA7

Bit

Initial value

Read/Write

—

Reserved bits

Rev. 6.0, 09/02, page 416 of 876

Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered

by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5

and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7

to 4 of address H'FFA7 are reserved bits that cannot be modified and are always read as 1.

Address H'FFA5

Bit

Initial value

Read/Write

NDR7

R/W

NDR6

R/W

NDR5

R/W

NDR4

R/W

—

Reserved bitsNext data 7 to 4

These bits store the next output

data for TPC output group 1

Address H'FFA7

Bit

Initial value

Read/Write

—

NDR3

R/W

NDR2

R/W

NDR1

R/W

NDR0

R/W

Next data 3 to 0

These bits store the next output

data for TPC output group 0

Reserved bits

Rev. 6.0, 09/02, page 417 of 876

11.2.6 Nex t Da ta Register B (NDRB)

NDRB is an 8-bit readable/writable register that stores th e next output data for TPC output groups

3 and 2 (pins TP15 to TP8). During TPC output, when an ITU compare match event specified in

TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of

NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or

different output triggers.

NDRB is initialized to H'00 by a reset an d in h ardware standby mode. It is not initialized in

software standby mode.

Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by

the same compare match event, the NDRB address is H'FFA4. The upper 4 bits belong to group 3

and the lower 4 bits to group 2. Address H'FFA6 consists entirely of reserved bits that cannot be

modified and are always read as 1.

Address H'FFA4

Bit

Initial value

Read/Write

NDR15

R/W

NDR14

R/W

NDR13

R/W

NDR12

R/W

NDR11

R/W

NDR10

R/W

NDR9

R/W

NDR8

R/W

Next data 11 to 8

These bits store the next output

data for TPC output group 2

Next data 15 to 12

These bits store the next output

data for TPC output group 3

Address H'FFA6

Bit

Initial value

Read/Write

—

Reserved bits

Rev. 6.0, 09/02, page 418 of 876

Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered

by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFA4

and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7

to 4 of address H'FFA6 are reserved bits that cannot be modified and are always read as 1.

Address H'FFA4

Bit

Initial value

Read/Write

NDR15

R/W

NDR14

R/W

NDR13

R/W

NDR12

R/W

—

Reserved bitsNext data 15 to 12

These bits store the next output

data for TPC output group 3

Address H'FFA6

Bit

Initial value

Read/Write

—

NDR11

R/W

NDR10

R/W

NDR9

R/W

NDR8

R/W

Next data 11 to 8

These bits store the next output

data for TPC output group 2

Reserved bits

Rev. 6.0, 09/02, page 419 of 876

11.2.7 Nex t Data Enable Register A (NDERA)

NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0

(TP7 to TP0) on a bit-by-bit basis.

Bit

Initial value

Read/Write

NDER0

R/W

NDER1

R/W

NDER2

R/W

NDER3

R/W

NDER4

R/W

NDER5

R/W

NDER6

R/W

NDER7

R/W

Next data enable 7 to 0

These bits enable or disable

TPC output groups 1 and 0

If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected in

the TPC output control register (T PCR) occurs, the NDRA valu e is automatically transferr e d to

the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is

not transferred from NDRA to PADR and the output value does not change.

NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC

output groups 1 and 0 (TP7 to TP0) on a bit-by-b i t basis .

Bits 7 to 0:

NDER7 to NDER0 Description

0 TPC outputs TP

to TP

are disabled (Initial value)

(NDR7 to NDR0 are not transferred to PA7 to PA0)

1 TPC outputs TP7 to TP0 are enabled

(NDR7 to NDR0 are transferred to PA7 to PA0)

Rev. 6.0, 09/02, page 420 of 876

11.2.8 Next Data Enable Register B (NDERB)

NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2

(TP15 to TP8) on a bit-by-bit basis.

Bit

Initial value

Read/Write

NDER8

R/W

NDER9

R/W

NDER10

R/W

NDER11

R/W

NDER12

R/W

NDER13

R/W

NDER14

R/W

NDER15

R/W

Next data enable 15 to 8

These bits enable or disable

TPC output groups 3 and 2

If a bit is enabled for TPC output by NDERB, then when the ITU compare match event selected in

the TPC output control register ( T PCR) occurs, the NDRB value is automatically tran sf erred to the

corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is not

transferred from NDRB to PBDR and the output value does not change.

NDERB is initialized to H'00 by a reset and in h ardwar e standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC

output groups 3 and 2 (TP15 to TP8) on a bit-by -bi t basis .

Bits 7 to 0:

NDER15 to NDER8 Description

0 TPC outputs TP

to TP

are disabled (Initial value)

(NDR15 to NDR8 are not transferred to PB7 to PB0)

1 TPC outputs TP15 to TP8 are enabled

(NDR15 to NDR8 are transferred to PB7 to PB0)

Rev. 6.0, 09/02, page 421 of 876

11.2.9 TPC Output Control Register (TPCR)

TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a

group-by-group basis.

Bit

Initial value

Read/Write

G3CMS1

R/W

G3CMS0

R/W

G2CMS1

R/W

G2CMS0

R/W

G1CMS1

R/W

G0CMS0

R/W

G1CMS0

R/W

G0CMS1

R/W

Group 3 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 3

(TP to TP )

Group 2 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 2

(TP to TP )

Group 1 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 1

(TP to TP )

Group 0 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 0

(TP to TP )

15 12

11 8

TPCR is initialized to H'FF by a reset and in hardware standby mode. It is n ot initialized in

software standby mode.

Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits

select the compare match event that triggers TPC output group 3 (TP15 to TP12).

Bit 7: G3CMS1 Bit 6: G3CMS0 Description

0 0 TPC output group 3 (TP15 to TP12) is triggered by compare

match in ITU channel 0

1 TPC output group 3 (TP15 to TP12) is triggered by compare

match in ITU channel 1

1 0 TPC output group 3 (TP15 to TP12) is triggered by compare

match in ITU channel 2

1 TPC output group 3 (TP15 to TP12) is triggered by compare

match in ITU channel 3 (Initial value)

Rev. 6.0, 09/02, page 422 of 876

Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits

select the compare match event that triggers TPC output group 2 (TP11 to TP8).

Bit 5: G2CMS1 Bit 4: G2CMS0 Description

0 0 TPC output group 2 (TP11 to TP8) is trigg ered by com pare

match in ITU channel 0

1 TPC output group 2 (TP11 to TP8) is trigg ered by com par e

match in ITU channel 1

1 0 TPC output group 2 (TP11 to TP8) is trigg ered by com pare

match in ITU channel 2

1 TPC output group 2 (TP11 to TP8) is trigg ered by com par e

match in ITU channel 3 (Initial value)

Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits

select the compare match event that triggers TPC output group 1 (TP7 to TP4).

Bit 3: G1CMS1 Bit 2: G1CMS0 Description

0 0 TPC output group 1 (TP7 to TP4) is triggered by compare

match in ITU channel 0

1 TPC output group 1 (TP7 to TP4) is triggered by compare

match in ITU channel 1

1 0 TPC output group 1 (TP7 to TP4) is triggered by compare

match in ITU channel 2

1 TPC output group 1 (TP7 to TP4) is triggered by compare

match in ITU channel 3 (Initial value)

Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits

select the compare match event that triggers TPC output group 0 (TP3 to TP0).

Bit 1: G0CMS1 Bit 0: G0CMS0 Description

0 0 TPC output group 0 (TP3 to TP0) is triggered by compare

match in ITU channel 0

1 TPC output group 0 (TP3 to TP0) is triggered by compare

match in ITU channel 1

1 0 TPC output group 0 (TP3 to TP0) is triggered by compare

match in ITU channel 2

1 TPC output group 0 (TP3 to TP0) is triggered by compare

match in ITU channel 3 (Initial value)

Rev. 6.0, 09/02, page 423 of 876

11.2.10 TPC Output Mode Register (TPMR)

TPMR is an 8-bit r eadable/writable register that selects normal or non-overlapping TPC output fo r

each group.

Bit

Initial value

Read/Write

—

G3NOV

R/W

G0NOV

R/W

G2NOV

R/W

G1NOV

R/W

Group 3 non-overlap

Selects non-overlapping TPC

output for group 3 (TP to TP )

Reserved bits

Group 2 non-overlap

Selects non-overlapping TPC

output for group 2 (TP to TP )

Group 1 non-overlap

Selects non-overlapping TPC

output for group 1 (TP to TP )

Group 0 non-overlap

Selects non-overlapping TPC

output for group 0 (TP to TP )

15 12

11 8

The output trigger period of a non-overlapping TPC output waveform is set in general register B

(GRB) in the IT U channel selected for outpu t trigge r in g. The non-o verlap margin is set in genera l

11.3.4, Non-Overlapping TPC Output.

TPMR is initialized to H'F0 by a reset and in hardwar e standby mode. It is not initialized in

software standby mode.

Bits 7 to 4—Reserved: Read-only bits, always read as 1.

Rev. 6.0, 09/02, page 424 of 876

Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for

group 3 (TP15 to TP12).

Bit 3: G3NOV Description

0 Normal TPC output in group 3 (output values change at compare match A in

the selected ITU channel) (Initial value)

1 Non-overlapping TPC output in group 3 (independent 1 and 0 output at

compare match A and B in the selected ITU channel)

Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for

group 2 (TP11 to TP8).

Bit 2: G2NOV Description

0 Normal TPC output in group 2 (output values change at compare match A in

the selected ITU channel) (Initial value)

1 Non-overlapping TPC output in group 2 (independent 1 and 0 output at

compare match A and B in the selected ITU channel)

Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for

group 1 (TP7 to TP4).

Bit 1: G1NOV Description

0 Normal TPC output in group 1 (output values change at compare match A in

the selected ITU channel) (Initial value)

1 Non-overlapping TPC output in group 1 (independent 1 and 0 output at

compare match A and B in the selected ITU channel)

Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for

group 0 (TP3 to TP0).

Bit 0: G0NOV Description

0 Normal TPC output in group 0 (output values change at compare match A in

the selected ITU channel) (Initial value)

1 Non-overlapping TPC output in group 0 (independent 1 and 0 output at

compare match A and B in the selected ITU channel)

Rev. 6.0, 09/02, page 425 of 876

11.3 Operation

11.3.1 Overview

When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output

is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.

When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit

contents are transferred to PADR or PBDR to update the output values.

Figure 11.2 illustrates the TPC outp ut operation. Table 11.3 su mmarizes the TPC operatin g

conditions.

DDR NDER

TPC output pin

DR NDR

QD QDInternal

data bus

Output trigger signal

Figure 11.2 TPC Output Operation

Table 11.3 TPC Operating Conditio ns

NDER DDR Pin Function

0 0 Generic input port

1 Generic output port

1 0 Generic input port (but the DR bit is a read-only bit, and when compare

match occurs , the NDR bit va lue is transferred to the DR bit)

1 TPC pulse output

Sequential o utput of up to 16-bit patterns is possible by wr iting new output data to NDRA and

NDRB before the next compare match. For information on non-overlapping operation, see section

11.3.4, Non-Overlapping TPC Output.

Rev. 6.0, 09/02, page 426 of 876

11.3 .2 Output Timing

If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output

when the selected compare match event occurs. Figure 11.3 shows the timing of these operations

for the case of normal output in groups 2 and 3, triggered by compare match A.

TCNT

GRA

Compare

match A signal

NDRB

PBDR

TP to TP

815

N + 1

Figure 11.3 Timing of Transfer of Next Data Register Contents and Output (Example)

Rev. 6.0, 09/02, page 427 of 876

11.3.3 Normal TPC Output

Sample Setup Pr ocedure for Normal TPC O ut put: Figure 11.4 shows a sample procedure for

setting up normal TPC output.

Normal TPC output

Set next TPC output data

Compare match? No

Yes

Set next TPC output data

ITU setup

Port and

TPC setup

ITU setup 10

10.

11.

Set TIOR to make GRA an output compare

Set the TPC output trigger period.

Select the counter clock source with bits

TPSC2 to TPSC0 in TCR. Select the counter

clear source with bits CCLR1 and CCLR0.

Enable the IMFA interrupt in TIER.

The DMAC can also be set up to transfer

data to the next data register.

Set the initial output values in the DR bits

of the input/output port pins to be used for

TPC output.

Set the DDR bits of the input/output port

pins to be used for TPC output to 1.

Set the NDER bits of the pins to be used for

TPC output to 1.

Select the ITU compare match event to be

used as the TPC output trigger in TPCR.

Set the next TPC output values in the NDR bits.

Set the STR bit to 1 in TSTR to start the

timer counter.

At each IMFA interrupt, set the next output

values in the NDR bits.

Select GR functions

Set GRA value

Select counting operation

Select interrupt request

Start counter

Set initial output data

Select port output

Enable TPC output

Select TPC output trigger

Figure 11.4 Setup Procedure for Normal TPC Output (Example)

Rev. 6.0, 09/02, page 428 of 876

Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows

an example in which the TPC is used for cyclic five-phase pulse output.

GRA

H'0000

NDRB

PBDR

•

Time

TCNT

TCNT value

C0 40 60 20 30 10 18 08 88 80 C0

Compare match

The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare

The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt.

H'F8 is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in

TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.

Output data H'80 is written in NDRB.

The timer counter in this ITU channel is started. When compare match A occurs, the NDRB contents

are transferred to PBDR and output. The compare match/input capture A (IMFA) interrupt service routine

writes the next output data (H'C0) in NDRB.

Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing

H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88… at successive IMFA interrupts. If the DMAC is set for

activation by this interrupt, pulse output can be obtained without loading the CPU.

80 C0 40 60 20 30 10 18 08 88 80 C0 40

Figure 11.5 Normal TPC Output Example (Five-Phase Pulse Output)

Rev. 6.0, 09/02, page 429 of 876

11.3.4 Non-Overlapping TPC Output

Sample Setup P rocedure for Non-Overlapping TPC Output : Figure 11.6 shows a sample

procedure for setting up non-overlapping TPC output.

Non-overlapping

TPC output

Set next TPC output data

Compare match A? No

Yes

Set next TPC output data

Start counter

ITU setup

Port and

TPC setup

ITU setup

Set initial output data

Set up TPC output

Enable TPC transfer

Select TPC transfer trigger

Select non-overlapping groups

10.

11.

12.

Set TIOR to make GRA and GRB output

compare registers (with output inhibited).

Set the TPC output trigger period in GRB

and the non-overlap margin in GRA.

Select the counter clock source with bits

TPSC2 to TPSC0 in TCR. Select the counter

clear source with bits CCLR1 and CCLR0.

Enable the IMFA interrupt in TIER.

The DMAC can also be set up to transfer

data to the next data register.

Set the initial output values in the DR bits

of the input/output port pins to be used for

TPC output.

Set the DDR bits of the input/output port pins

to be used for TPC output to 1.

Set the NDER bits of the pins to be used for

TPC output to 1.

In TPCR, select the ITU compare match

event to be used as the TPC output trigger.

In TPMR, select the groups that will operate

in non-overlap mode.

Set the next TPC output values in the NDR

bits.

Set the STR bit to 1 in TSTR to start the timer

counter.

At each IMFA interrupt, write the next output

value in the NDR bits.

Select GR functions

Set GR values

Select counting operation

Select interrupt requests

Figure 11.6 Setup Pro cedure for Non-Overla pping TPC Output (Example)

Rev. 6.0, 09/02, page 430 of 876

Example of Non-Overlapping TPC Output (Example o f Four-Phase Complementary Non-

Overlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase

complementary non-overlapping pulse output.

GRB

H'0000

NDRB

PBDR

Time

59 56 95 65

05 65 41 59 50 56 14 95 05 65

TCNT

H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set

TCNT value

Non-overlap margin

The output trigger ITU channel is set up so that GRA and GRB are output compare registers and the

counter will be cleared by compare match B. The TPC output trigger period is set in GRB. The non-

overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable IMFA interrupts.

This operation example is described below.

•

Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is

written in NDRB.

The timer counter in this ITU channel is started. When compare match B occurs, outputs change from

in TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.

1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed

by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.

Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…

at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be

obtained without loading the CPU.

GRA

Figure 11.7 Non-Overlapping TPC Output Example

(Four-Pha se Co mplement ary Non-Ov erlapping Pulse Output)

Rev. 6.0, 09/02, page 431 of 876

11.3.5 TPC Output Triggering by Input Capture

TPC output can be triggered by ITU input capture as well as by compare match. If GRA and GRB

function s as an input capture register in the ITU channel selected in TPCR, TPC output will b e

triggered by the input capture signal. Figure 11.8 shows the timing.

TIOC pin

Input capture

signal

NDR

DR N

Figure 11.8 TPC Output Triggering by Input Capture (Example)

Rev. 6.0, 09/02, page 432 of 876

11.4 Usage Notes

11.4.1 Operation of TPC Output Pins

TP0 to TP15 are multiplexed with IT U, DMAC, address bus, and other pin function s. Wh en ITU,

DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output. The

data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.

Pin functions should be changed only under conditions in which th e output trigger event will not

occur.

11.4.2 Note on Non-Overlapping Output

During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as

follows.

1. NDR bits are always transferred to DR bits at compare match A.

2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred

if their valu e is 1.

Figure 11.9 illustrates the non-overlapping TPC output operation.

DDR NDER

TPC output pin

DR NDR

QD QD

Compare match A

Compare match B

Internal

data bus

Figure 11.9 Non-Overlapping TPC O ut put

Rev. 6.0, 09/02, page 433 of 876

Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before

compare match A. NDR contents should not be altered during the interval from compare match B

to compare match A (the non-overlap margin).

This can be accomplished by having the IMFA interrupt service routine write the next data in

NDR, or by h aving the IMFA interrupt activate the DMAC. The next data must be written before

the next compare match B occurs.

Figure 11.10 shows the timing relationships.

Compare

match A

Compare

match B

NDR write

NDR

NDR write

0/1 output 0/1 output0 output 0 output

Do not write

to NDR in this

interval

Do not write

to NDR in this

interval

Write to NDR

in this interval

Write to NDR

in this interval

Figure 11.10 Non-Overlapping Operation and NDR Write Timing

Rev. 6.0, 09/02, page 434 of 876

Rev. 6.0, 09/02, page 435 of 876

Section 12 Watchdog Timer

12.1 Overview

The H8/3048 Series has an on-chip watchdog timer (WDT). The WDT has two selectable

functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an

interval timer. As a watchdog timer, it generates a reset signal for the chip if a system cr ash allows

the timer counter (T CNT) to overflow before being rewritten. In in terval timer oper ation, an

interval timer in terrupt is requested at each TCNT overflo w.

12.1.1 Features

WDT features are listed below.

• Selection of eight counter clock sources

φ/2, φ/32, φ/64, φ/128, φ/256, φ/512, φ/2048, or φ/4096

• Interval timer option

• Timer counter overflow generates a reset signal or interrupt.

The reset signal is generated in watchdog timer oper ation. An interval timer interrupt is

generated in inter val timer operation.

• Watchdog timer reset signal resets the entire chip internally, and can also be output externally.

The reset signal generated by timer coun ter overflow during watchdog timer operation resets

the entire chip internally. An external reset signal can be outpu t from the RESO pin to reset

other system devices simultaneously.

Rev. 6.0, 09/02, page 436 of 876

12.1.2 Block Diagram

Figure 12.1 shows a block diagram of the WDT.

φ/2

φ/32

φ/64

φ/128

φ/256

φ/512

φ/2048

φ/4096

TCNT

TCSR

RSTCSR

Reset control

Interrupt signal

Reset

(internal, external)

(interval timer) Interrupt

control

Overflow

Clock Clock

selector

Read/

write

control

Internal

data bus

Internal clock sources

Legend

TCNT:

TCSR:

RSTCSR:

Timer counter

Timer control/status register

Reset control/status register

Figure 12.1 WDT Block Diagram

12.1.3 Pin Configuration

Table 12.1 describes the WDT output pin.

Table 12.1 WDT Pin

Name Abbreviation I/O Function

Reset output RESO Output*External output of the watchdog timer reset

signal

Note: * Open-drain output.

Rev. 6.0, 09/02, page 437 of 876

12.1.4 Register Configuration

Table 12.2 summarizes the WDT registers.

Table 12.2 WDT Registers

Address*1

Write*2Read Name Abbre-

viation R/W Initial

Value

H'FFA8 H'FFA8 Timer control/status register TCSR R/(W)*3H'18

H'FFA9 Timer counter TCNT R/W H'00

H'FFAA H'FFAB Reset control/status register RSTCSR R/(W)*3H'3F

Notes: *1 Lower 16 bits of the address.

*2 Write word data starting at this address.

*3 Only 0 can be written in bit 7, to clear the flag.

12.2 Register Descriptions

12.2.1 Timer Counter (TCNT)

TCNT is an 8-bit readable and writable* up-counter.

Bit

Initial value

Read/Write

R/W

When the TME bit is set to 1 in TCSR, TCNT starts coun ting pulses gen erated from an internal

clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from

H'FF to H'00), th e OVF bit is set to 1 in TCSR. TCNT is initial ized to H'00 by a reset and when

the TME bit is cleared to 0.

Note: * TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register

Access.

Rev. 6.0, 09/02, page 438 of 876

12.2.2 Timer Control/Status Register (TCSR)

TCSR is an 8-b it r eadable and writable* register. Its functions include selectin g the timer mode

and clock source.

Note: * TCSR dif fers from other registers in b e ing more difficult to write. For details see section

12.2.4, Notes on Register Access.

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

OVF

R/(W)

WT/

R/W

TME

R/W

—

CKS0

R/W

CKS2

R/W

CKS1

R/W

Overflow flag

Status flag indicating overflow

Clock select

These bits select the

TCNT clock source

Timer mode select

Selects the mode

Timer enable

Selects whether TCNT runs or halts

Reserved bits

Bits 7 to 5 are in itialized to 0 by a reset and in standby mod e. Bits 2 to 0 are initialized to 0 by a

reset. In softwar e stan dby mode bits 2 to 0 are not initialized, but r e tain their previous values.

Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has ov erflowed

from H'FF to H'00.

Bit 7: OVF Description

0 [Clearing cond iti on]

Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value)

1 [Setting condition]

Set when TCNT changes from H'FF to H'00

Rev. 6.0, 09/02, page 439 of 876

Bit 6—Timer Mode Select (WT/IT

ITIT

IT): Selects whether to use the WDT as a watchdog timer or

interval timer. I f used as an interval timer, the WDT generates an in terval timer interrupt request

when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when

TCNT overflows.

Bit 6: WT/ IT

ITIT

IT Description

0 Interval timer: requests interval timer interrupts (Initial value)

1 Watchdog timer: generates a reset signal

Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.

When WT/IT = 1, clear the SYSCR software standby bit (SSBY) to 0, then set the TME to 1.

When SSBY is set to 1, clear TME to 0.

Bit 5: TME Description

0 TCNT is initialized to H'00 and halted (Initial value)

1 TCNT is counting and CPU interrupt requests are enabled

Bits 4 and 3—Reserved: Read-only bits, always read as 1.

Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources,

obtained by prescaling the system clock (φ), for input to TCNT.

Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Description

000φ/2 (Initial value)

1φ/32

10φ/64

1φ/128

100φ/256

1φ/512

10φ/2048

1φ/4096

Rev. 6.0, 09/02, page 440 of 876

12.2.3 Reset Control/Status Register (RSTCSR)

RSTCSR is an 8- bit readable and writable* register that indicates when a reset signal has been

generated by watchdog timer overflow, and contro ls external output of the reset signal.

Note: * RSTCSR diff e r s f r om other registers in being more difficult to write. Fo r details see

section 12.2.4, Notes on Register Access.

Bit

Initial value

Read/Write

Note: * Only 0 can be written in bit 7, to clear the flag.

WRST

R/(W)

RSTOE

R/W

—

Watchdog timer reset

Indicates that a reset signal has been generated

Reserved bits

Reset output enable

Enables or disables external output of the reset signal

Bits 7 and 6 ar e initialized by input of a reset signal at the RES pin. They are not initialized by

reset signals generated by watchdog timer overflow.

Bit 7—Watchdog Timer Re set (WRST): During watchdog tim er operation, this bit indicates that

TCNT has over f lowed and generated a reset signa l. Th is reset signal resets the en tire chip

internally. I f bit RSTOE is set to 1, this reset signa l is also output (lo w) at the RESO pin to

initialize external sy stem devices.

Bit 7: WRST Description

0 [Clearing cond iti ons ]

Cleared to 0 by reset signal input at RES pin (Initi al val ue)

Cleared by reading WRST when WRST = 1, then writing 0 in WRST

1 [Setting condition]

Set when TCNT overflow generates a reset signal during watchdog timer

operation

Rev. 6.0, 09/02, page 441 of 876

Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of

the reset signal generated if TCNT overflows during watchdog timer operation.

Bit 6: RSTOE Description

0 Reset signal is not outp ut exter nal ly (Initial value)

1 Reset signal is out put externally

Bits 5 to 0—Reserved: Read-only bits, always read as 1.

12.2.4 Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being

more difficult to write. The procedures for writing and reading these registers are given below.

Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.

They cannot be written by byte instructions. Figure 12.2 shows the format of data written to

TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be

contained in the lower byte of the written word. The upper byte must contain H'5A (password for

TCNT) or H'A5 (password for TCSR). This transfers the write da ta from the lower byte to TCNT

or TCSR.

15 8 7 0

H'5A Write dataAddress H'FFA8*

15 8 7 0

H'A5 Write dataAddress H'FFA8*

TCNT write

TCSR write

Note: Lower 16 bits of the address.*

Figure 12.2 Format of Data Written to TCNT and TCSR

Rev. 6.0, 09/02, page 442 of 876

Writing to RSTCSR: RSTCSR must be written b y a word transfer instruction. It cannot be

written by byte tr an sfer instructions. Figur e 12.3 shows the format of data written to RSTCSR. To

write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower

byte. The H'00 in the lower byte clears th e WRST bit in RSTCSR to 0. To wr ite to the RSTOE bit,

the upper byte must contain H'5A and the lower byte must contain the write data. Writing this

word transfers a write data value into the RSTOE bit.

15 8 7 0

H'A5 H'00Address H'FFAA*

15 8 7 0

H'5A Write dataAddress H'FFAA*

Writing 0 in WRST bit

Writing to RSTOE bit

Note: Lower 16 bits of the address.*

Figure 12.3 Format of Data Written to RSTCSR

Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Byte access

instructions can be used. The read addresses are H'FFA8 for TCSR, H'FFA9 for TCNT, and

H'FFAB for RSTCSR, as listed in table 12.3.

Table 12.3 Read Addresses of TCNT, TCS R, and RSTCSR

Address*Register

H'FFA8 TCSR

H'FFA9 TCNT

H'FFAB RSTCSR

Note: * Lower 16 bits of the address.

Rev. 6.0, 09/02, page 443 of 876

12.3 Operation

Operations when the WDT is used as a watchdog timer and as an interval timer are described

below.

12.3.1 Watchdog Timer Operation

Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the

WT/IT and TME b its to 1 in TCSR. Software must prev ent TCNT overflow by rewriting the

TCNT value (no rmally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and

overflows due to a system crash etc., the chip is internally reset for a duration of 518 states.

The watchdog reset sig n a l can be externally output from the RESO p in to reset external system

devices. The reset signal is output externally for 132 states. External output can be enabled or

disabled by the RSTOE bit in RSTCSR.

A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can

distinguish a RES reset from a watch dog reset by checking the WRST bit in RSTCSR.

If a RES reset and a watchdog reset occu r simultaneously, the RES reset takes priority .

H'FF

H'00

WDT overflow

Start H'00 written

in TCNT Reset

TME set to 1

H'00 written

in TCNT

Internal

reset signal

518 states

132 states

TCNT count

value

OVF = 1

Figure 12.4 Watchdog Timer Operation

Rev. 6.0, 09/02, page 444 of 876

12.3.2 Interval Timer Operation

Figure 12 .5 illustr a tes interval timer operation. To use the WDT as an interval timer, clear b it

WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each

TCNT overflow. This function can be used to generate interv al timer interrupts at regular

intervals.

TCNT

count value

Time t

Interval

timer

interrupt

Interval

timer

interrupt

Interval

timer

interrupt

Interval

timer

interrupt

WT/ = 0

TME = 1

H'FF

H'00

Figure 12.5 Interval Timer Operation

12.3.3 Timing of Setting of Overflow Flag (OVF)

Figure 12 .6 sh ows the timing of setting of th e OVF f lag in TCSR. The OVF flag is set to 1 when

TCNT overflows. At the same time, a reset signal is generated in watchdog timer oper ation, or an

interval timer interrupt is generated in in terval tim er oper ation.

TCNT

Overflow signal

OVF

H'FF H'00

Figure 12.6 Timing of Setting of OVF

Rev. 6.0, 09/02, page 445 of 876

12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)

The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.

Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is

set to 1 when TCNT overflows and OVF is set to 1 . At the same time an internal reset sig nal is

generated for the entire chip. This internal reset signal clear s OVF to 0, but the WRST bit remains

set to 1. The reset rou tine must therefore clear the WRST bit.

TCNT

Overflow signal

OVF

WRST

H'FF H'00

WDT internal

reset

Figure 12.7 Timing of Setting of WRST Bit and Internal Reset

Rev. 6.0, 09/02, page 446 of 876

12.4 Interrupts

During interval timer oper ation, an overflow generates an interval timer interrupt (WOVI). The

interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.

12.5 Usage Notes

Contention between TCNT Write and Increment: If a timer counter clock pulse is generated

during the T 3 state of a write cycle to TCNT, the write takes priority and the timer count is not

incremented. See figure 12.8.

TCNT

TCNT NM

Counter write data

Write cycle: CPU writes to TCNT

Internal write

signal

TCNT input

clock

Figure 12.8 Contention between TCNT Write and Increment

Changing CKS2 to CKS0 Va lues: Halt TCNT by clearing the TME bit to 0 in TCSR bef ore

changing the values of bits CKS2 to CKS0.

Rev. 6.0, 09/02, page 447 of 876

12.6 Notes

This chip inco rpor ates an WDT. The timer counter value of the on-chip WDT is no t re wr itten,

even if a system crash occurs. If an overflow occurs, a reset signal is generated and the chip is

reset.

However, if the following three events occur due to a CPU overrun, for example, the above

operations cannot be guaranteed since the WDT and the CPU are incorporated in the same chip.

• When the internal I/O registers related to the on- c hip WDT are rewritten.

• When software standby mode is incorrectly entered.

• When the break mode is incorrectly entered.

In addition, as stated in the NMI above, if an abnormal level is input into the power supply pins or

the system control pins, correct operations cannot be guaranteed.

Except the above cases, the on -chip WDT functions as a device that supports recovery from a

system crash. Accordingly, when a fail-safe function is required in your system, an additional

circuit may be required as necessary.

Rev. 6.0, 09/02, page 448 of 876

Rev. 6.0, 09/02, page 449 of 876

Section 13 Serial Communication Interface

13.1 Overview

The H8/3048 Series has a serial communication interface (SCI) with two independent channels.

The two channels are functionally identical. The SCI can communicate in asynchronous or

synchronous mode. It also has a multiprocessor communication function for ser ial communication

among two or more processors.

When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted

independently. For details see section 21.6, Module Standby Function.

Channel 0 (SCI0) also has a smart card interface function conforming to the ISO/IEC7816-3

(Identification Card) standard. This function supports serial communication with a smart card. For

details, see section 14, Smart Card Interface.

13.1.1 Features

SCI features are listed below.

• Selection of asynchronous or synchronous mode for serial communication

 Asynchronous mode

Serial data communication is synchronized one character at a time. The SCI can

communicate with a universal asynchronous receiver/transmitter (UART), asynchronous

communication interface adapter (ACIA), or other chip that employs standard

asynchronous serial communication. It can also comm unicate with two or mo re other

processors u sin g the multiprocessor comm unication function. There are twelve selectable

serial data communication formats.

• Data length: 7 or 8 bits

• Stop bit length: 1 or 2 bits

• Parity bit: even, odd , or non e

• Multiprocesso r bit: 1 or 0

• Receive error detection: parity, overrun, and framing errors

• Break detection: by reading the RxD level directly when a framing error occurs

 Synchronous mode

Serial data communication is synchron ized with a clock signal. The SCI can communicate

with other chips having a synchronous communication function. There is one serial data

communication format.

• Data length: 8 bits

• Receive error detection: overrun errors

Rev. 6.0, 09/02, page 450 of 876

• Full duplex communication

The transmitting and receivin g sections are in d epend ent, so th e SCI can transmit and receive

simultaneously. The transmitting an d receiving sections are both double-buffered, so serial

data can be transmitted and received continuously.

• Built-in baud rate generator with selectab le bit rates

• Selectable transmit/receive clock so urces: internal clock from baud rate generator, or external

clock from the SCK pin.

• Four types of interrupts

Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested

independently. The transmit-data-empty and receive-data-full interrupts from SCI0 can

activate the DMA contr oller (DMAC) to transfer d ata.

Rev. 6.0, 09/02, page 451 of 876

13.1.2 Block Diagram

Figure 13.1 shows a block diagram of the SCI.

RxD

TxD

SCK

RDR

RSR

TDR

TSR

SSR

SCR

SMR

BRR

Module data bus

Bus interface

Internal

data bus

Transmit/

receive control

Baud rate

generator

φ/4

φ/16

φ/64

ClockParity generate

Parity check

TEI

TXI

RXI

ERI

Legend

External clock

RSR:

RDR:

TSR:

TDR:

SMR:

SCR:

SSR:

BRR:

Receive shift register

Receive data register

Transmit shift register

Transmit data register

Serial mode register

Serial control register

Serial status register

Bit rate register

Figure 13.1 SCI Block Diagram

Rev. 6.0, 09/02, page 452 of 876

13.1 .3 Input/Output Pins

The SCI has serial pins for each channel as listed in table 13.1.

Table 13.1 SCI Pins

Channel Name Abbreviation I/O Function

0 Serial clock pin SCK0Input/output SCI0 clock in put/output

Receive data pin RxD 0Input SCI0 receive data input

Transmit data pin TxD0Output SCI0 transmit data output

1 Serial clock pin SCK1Input/output SCI1 clock in put/output

Receive data pin RxD 1Input SCI1 receive data input

Transmit data pin TxD1Output SCI1 transmit data output

13.1.4 Register Configuration

The SCI has internal registers as listed in table 13.2. These registers select asynchronous or

synchronous mode, specify the data format and bit rate, and control the transmitter and receiver

sections.

Table 13.2 Registers

Channel Address*1Name Abbreviation R/W Initial Value

0 H'FFB0 Serial mode register SMR R/W H'00

H'FFB1 Bit rate register BRR R/W H'FF

H'FFB2 Serial co ntrol register SCR R/W H'00

H'FFB3 Transmit dat a regist er TD R R/W H'FF

H'FFB4 Serial stat us regi ster SSR R/(W)*2H'84

H'FFB5 Recei ve data regi ster RDR R H'00

1 H'FFB8 Serial mode register SMR R/W H'00

H'FFB9 Bit rate register BRR R/W H'FF

H'FFBA Serial control register SCR R/W H'00

H'FFBB Transmit data regist er TDR R/W H'FF

H'FFBC Serial status register SSR R/(W)*2H'84

H'FFBD Receive data register RDR R H'00

Notes: *1 Lower 16 bits of the address.

*2 Only 0 can be written, to clear flags.

Rev. 6.0, 09/02, page 453 of 876

13.2 Register Descriptions

13.2.1 Receive Shift Register (RSR)

RSR is the register that receives serial data.

Bit

Read/Write

—

The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,

thereby converting the data to parallel data. When 1 byte has been received, it is automatically

transferred to RDR. The CPU cannot read or write RSR directly.

13.2.2 Receive Data Register (RDR)

RDR is the register that stores received serial data.

Bit

Initial value

Read/Write

When the SCI finishes receiving 1 byte of serial data, it transfers the received data from RSR into

RDR for storage. RSR is then ready to receive the next data. This double buffering allows data to

be received continuously.

RDR is a read-o nly register. Its contents canno t be modified by the CPU. RDR is initialized to

H'00 by a reset and in standby mode.

Rev. 6.0, 09/02, page 454 of 876

13.2.3 Transmit Shift Register (TSR)

TSR is the register that transmits serial data.

Bit

Read/Write

—

The SCI loads tr ansmit data from TDR into TSR, th en transmits the data serially from the TxD

pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the nex t

transmit data from TDR into TSR and star ts transmitting it. If the TDRE flag is set to 1 in SSR,

however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write TSR

directly.

13.2.4 Transmit Data Register (TDR)

TDR is an 8-bit register that stores data for serial transmission.

Bit

Initial value

Read/Write

R/W

When the SCI detects that TSR is empty, it moves transm it data written in TDR fr om TDR into

TSR and starts serial transmission. Continuous serial transmission is possible by writing the next

transmit da ta in TDR during serial transmission fr om TSR.

The CPU can always read an d write TDR. TDR is initialized to H'FF by a r eset and in standby

mode.

Rev. 6.0, 09/02, page 455 of 876

13.2.5 Serial Mode Register (SMR)

SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock

source for the baud rate generator.

Bit

Initial value

Read/Write

C/A

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Communication mode

Selects asynchronous or synchronous mode

Clock select 1/0

These bits select the

baud rate generator’s

clock source

Character length

Selects character length in asynchronous mode

Parity enable

Selects whether a parity bit is added

Parity mode

Selects even or odd parity

Stop bit length

Selects the stop bit length

Multiprocessor mode

Selects the multiprocessor

function

The CPU can always read an d write SMR. SMR is initialized to H'00 b y a reset and in standby

mode.

Bit 7—Communication Mode (C/A

A): Selects whether the SCI operates in asynchronous or

synchronous mode.

Bit 7: C/A

ADescription

0 Asynchronous mode (Initial value)

1 Synchronous mode

Rev. 6.0, 09/02, page 456 of 876

Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In

synchronous mode the data length is 8 bits regardless of the CHR setting.

Bit 6: CHR Description

0 8-bit data (Initial val ue)

1 7-bit data*

Note: * When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted.

Bit 5—Parity Enable (PE): In async hro nous mode, this bit enables or disab les the addition of a

parity bit to transmit data, and th e checking of the parity bit in receive data. In synchronous mode

the parity bit is neither added nor checked, regard less of the PE setting.

Bit 5: PE Description

0 Parity bit not added or checked (Initial value)

1 Parity bit added and che cke d*

Note: *When PE is set to 1, an even or odd parity bit is added to transmit data according to the

even or odd parity mode selected by the O/E bit, and the parity bit in receive data is

checked to see that it matches the even or odd mode selected by the O/E bit.

Bit 4—Parity Mode (O/E

E): Selects even or odd parity. The O/E bit setting is valid in

asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit.

The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled

in asynchronous mode.

Bit 4: O/E

EDescription

0 Even parity*1(Initi al val ue)

1 Odd parity*2

Notes: *1 When even parity is selected, the parity bit added to transmit data makes an even

number of 1s in the transmitted character and parity bit combined. Receive data must

have an even number of 1s in the received character and parity bit combined.

*2 When odd parity is selected, the parity bit added to transmit data makes an odd number

of 1s in the transmitted character and parity bit combined. Receive data must have an

odd number of 1s in the received character and parity bit combined.

Rev. 6.0, 09/02, page 457 of 876

Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting

is used only in asynchronous mode. In synchronous mode no stop bit is added, so th e STOP bit

setting is ignored.

Bit 3: STOP Description

0 One stop bit*1(Initial value)

1 Two stop bits*2

Notes: *1 One stop bit (with value 1) is added at the end of each transmitted character.

*2 Two stop bits (with value 1) are added at the end of each transmitted character.

In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second

stop bit is 1 it is treated as a stop bit. If the second stop bit is 0 it is treated as the start bit of the

next incoming character.

Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a mu ltiprocessor

format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is

valid only in asynchronous mode. It is ignored in synchronous mode.

For fur ther information on the multip rocessor communication function, see section 13.3.3,

Multiprocessor Commu nication.

Bit 2: MP Description

0 Multiprocessor function disabled (Initial value)

1 Multiprocessor format selected

Bits 1 and 0—Clock Select 1 and 0 (CKS1/0): Th ese bits select the clock source of the on-chip

baud rate generator. Four clock sources are available: φ, φ/4, φ/16, and φ/64.

For the relationship between the clock source, bit rate register setting, and baud rate, see section

13.2.8, Bit Rate Register (BRR).

Bit 1: CKS1 Bit 0: CKS0 Description

00φ(Initial val ue)

1φ/4

10φ/16

1φ/64

Rev. 6.0, 09/02, page 458 of 876

13.2.6 Serial Control Register (SCR)

SCR enables the SCI transmitter and receiver, enables or disables serial clock output in

asynchro nou s mode, enables or disables interrupts, and selects the transmit/receive clock source.

Bit

Initial value

Read/Write

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Transmit interrupt enable

Enables or disables transmit-data-empty interrupts (TXI)

Clock enable 1/0

These bits select the

SCI clock source

Receive interrupt enable

Enables or disables receive-data-full interrupts (RXI) and

receive-error interrupts (ERI)

Transmit enable

Enables or disables the transmitter

Receive enable

Enables or disables the receiver

Multiprocessor interrupt enable

Enables or disables multiprocessor

interrupts

Transmit-end interrupt enable

Enables or disables transmit-

end interrupts (TEI)

The CPU can always read an d write SCR. SCR is initialized to H'0 0 by a reset and in standby

mode.

Rev. 6.0, 09/02, page 459 of 876

Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data- e m pty interrupt

(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial tran sm it data from

TDR to TSR.

Bit 7: TIE Description

0 Transmit-data-empty interrupt request (TXI) is disabled*(Initi al val ue)

1 Transmit-data-empty interrupt request (TXI) is enabled

Note: *TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then

clearing it to 0; or by clearing the TIE bit to 0.

Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)

requested when the RDRF flag is set to 1 in SSR due to transfer of serial receive data from RSR to

RDR; also enables or disables the receive-error interrupt (ERI).

Bit 6: RIE Description

0 Receive-data-ful l (RXI) and r eceiv e-error (ER I) i nterrup t reque sts a re di sable d

(Initial value)

1 Receive-data-ful l (RXI) and r eceiv e-error (ER I) i nterrup t reque sts a re ena bled

Note: *RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER,

PER, or ORER flag, then clearing it to 0; or by clearing the RIE bit to 0.

Bit 5—Transmit Ena ble (TE): Enables or disables the start of SCI serial tr ansmitting op erations.

Bit 5: TE Description

0 Transmitting disabled*1(Initi al val ue)

1 Transmitting enabled*2

Notes: *1 The TDRE bit is locked at 1 in SSR.

*2 In the enable d state, serial transmitting starts when the TDRE bit in SSR is cleared to 0

after writing of transmit data into TDR. Select the transmit format in SMR before setting

the TE bit to 1.

Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.

Bit 4: RE Description

0 Receiving disabled*1(Initi al val ue)

1 Receiving enabled*2

Notes: *1 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These

flags retain their previous values.

*2 In the enabled state, serial receiving starts when a start bit is detected in asynchronous

mode, or serial clock input is detected in synchronous mode. Select the receive format

in SMR before setting the RE bit to 1.

Rev. 6.0, 09/02, page 460 of 876

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR.

The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0.

Bit 3: MPIE Description

0 Multiprocessor interrupts are disabled (normal receive operation) (Initial value)

[Clearing cond iti ons ]

The MPIE bit is cleared to 0.

MPB = 1 in received data.

1 Multiprocessor interrupts are enabled*

Receive-data-f ull interrupts (RXI), receive-error interrupt s (ERI), and sett ing of

the RDRF, FER, and ORER status flags in SSR are disabled until data with the

multiprocessor bit set to 1 is received.

Note: *The SCI does not transfer receive data from RSR to RDR, does not detect receive errors,

and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which

MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0,

enables RXI and ERI interrupts (if the RIE bit is set to 1 in SCR), and allows the FER and

ORER flags to be set.

Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables th e tr ansmit-end interrupt

(TEI) requested if TDR does not con tain new transmit data when the MSB is tr ansmitted.

Bit 2: TEIE Description

0 Transmit-end interrupt requests (TEI) are disabled*(Initi al val ue)

1 Transmit-end interrupt requests (TEI) are enabled*

Note: *TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,

then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing

the TEIE bit to 0.

Rev. 6.0, 09/02, page 461 of 876

Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and

enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0,

the SCK pin can be used for generic input/output, serial clock output, or serial clock input.

The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally

clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external

clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the

CKE1 and CKE0 bits. For further details on selection of the SCI clock source, see table 13.9 in

section 13.3, Operation.

Bit 1:

CKE1 Bit 0:

CKE0 Description

0 0 Asynchronous mode Internal clock, SCK pin available for generic

input/output *1

Synchronous mode Internal clock, SCK pin used for serial clock output *1

1 Asynchronous mode Internal clock, SCK pin used for clock output*2

Synchronous mode Internal clock, SCK pin used for serial clock output

1 0 Asynchronous mode External clock, SCK pin used for clock input *3

Synchronous mode External clock, SCK pin used for serial clock input

1 Asynchronous mode External clock, SCK pin used for clock input *3

Synchronous mode External clock, SCK pin used for serial clock input

Notes: *1 Initial val ue

*2 The output clock frequency is the same as the bit rate.

*3 The input clock frequency is 16 times the bit rate.

Rev. 6.0, 09/02, page 462 of 876

13.2.7 Serial Status Register (SSR)

SSR is an 8-bit register containing multiprocessor b it valu es, and status flags that indicate SCI

operating status.

Bit

Initial value

Read/Write

TDRE

R/(W)

RDRF

R/(W)

ORER

R/(W)

FER

R/(W)

PER

R/(W)

MPBT

R/W

TEND

MPB

Transmit data register empty

Status flag indicating that transmit data has been transferred from TDR into

TSR and new data can be written in TDR

Multiprocessor

bit transfer

Value of multi-

processor bit to

be transmitted

Receive data register full

Status flag indicating that data has been received and stored in RDR

Overrun error

Status flag indicating detection of a receive overrun error

Framing error

Status flag indicating detection of a receive

framing error

Parity error

Status flag indicating detection of

a receive parity error

Transmit end

Status flag indicating end of

transmission

Note: Only 0 can be written, to clear the flag.*

****

Multiprocessor bit

Stores the received

multiprocessor bit value

The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,

and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The

TEND and MPB flags are read-only bits that cannot be written.

SSR is initialized to H'84 by a reset and in standby mode.

Rev. 6.0, 09/02, page 463 of 876

Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data

from TDR in to TSR and the next serial transmit data can be written in TDR.

Bit 7: TDRE Description

0 TDR contains valid transmit data

[Clearing cond iti ons ]

Software reads TDRE while it is set to 1, then writes 0.

The DMAC writes data in TDR.

1 TDR does not contain valid transmit data (Initial value)

[Setting conditions]

The chip is reset or enters standby mode.

The TE bit in SCR is cleared to 0.

TDR contents are loaded into TSR, so new data can be written in TDR.

Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.

Bit 6: RDRF Description

0 RDR does not contain new receive data (Initial value)

[Clearing cond iti ons ]

The chip is reset or enters standby mode.

Software reads RDRF while it is set to 1, then writes 0.

The DMAC reads data from RDR.

1 RDR contains new receive data

[Setting condition]

When serial data is received normally and tran sferred from RSR to RDR.

Note: The RDR contents and RDRF flag are not affected by detection of receive errors or by

clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still

set to 1 when reception of the next data ends, an overrun error occurs and receive data is

lost.

Rev. 6.0, 09/02, page 464 of 876

Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an

overrun error.

Bit 5: ORER Description

0 Receiving is in progress or has ended normally (Initial value)*1

[Clearing cond iti ons ]

The chip is reset or enters standby mode.

Software reads ORER while it is set to 1, then writes 0.

1 A receive overrun error occurred*2

[Setting condition]

Reception of the next serial data ends when RDRF = 1.

Notes: *1 Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its

previous value.

*2 RDR continues to hold the receive data before the overrun error, so subsequent receive

data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In

synchronous mode, serial transmitting is also disabled.

Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing

error in asynchronous mode.

Bit 4: FER Description

0 Receiving is in progress or has ended normally (Initial value)*1

[Clearing cond iti ons ]

The chip is reset or enters standby mode.

Software reads FER while it is set to 1, then writes 0.

1 A receive framing error occurred*2

[Setting condition]

The stop bit at the end of receive data is checked and found to be 0.

Notes: *1 Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous

value.

*2 When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not

checked. When a framing error occurs the SCI transfers the receive data into RDR but

does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set

to 1. In synchronous mode, serial transmitting is also disabled.

Rev. 6.0, 09/02, page 465 of 876

Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error

in asynchronous mode.

Bit 3: PER Description

0 Receiving is in progress or has ended normally*1(Initial value)

[Clearing cond iti ons ]

The chip is reset or enters standby mode.

Software reads PER while it is set to 1, then writes 0.

1 A receive parity error occurred*2

[Setting condition]

The number of 1s in receive data, including the parity bit, does not match the

even or odd parity setting of O/E in SMR.

Notes: *1 Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous

value.

*2 When a parity error occurs the SCI transfers the receive data into RDR but does not set

the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In

synchronous mode, serial transmitting is also disabled.

Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was

transmitted TDR d id not contain new tr ansmit data, so transmissio n has ended. The TEND flag is

a read-only bit and cannot be written.

Bit 2: TEND Description

0 Transmiss ion is in pr ogre ss

[Clearing cond iti ons ]

Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.

The DMAC writes data in TDR.

1 End of transmission (Initial value)

[Setting conditions]

The chip is reset or enters standby mode.

The TE bit is cleared to 0 in SCR.

TDRE is 1 when the last bit of a serial character is transmitted.

Rev. 6.0, 09/02, page 466 of 876

Bit 1—Multiprocessor Bit (MPB): Stores the value of th e multiprocessor bit in receive data

when a multip rocesso r f ormat is used in asynchronous m ode. MPB is a r ead-only bit and cannot

be written.

Bit 1: MPB Description

0 Multiprocessor bit value in receive data is 0*(Initial value)

1 Multiprocessor bit value in receive data is 1

Note: *If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its

previous value.

Bit 0—Multiprocessor Bit Transf er (MPBT): Stores the value of the multiprocessor bit adde d to

transmit data when a multiprocessor for mat is selected for tran sm itting in asynchronous mo de.

The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected,

or when the SCI is not transmitting.

Bit 0: MPBT Description

0 Multiprocessor bit value in transmit data is 0 (Initial value)

1 Multiprocessor bit value in transmit data is 1

13.2.8 Bit Rate Register (BRR)

BRR is an 8-bit register that, to gether with the CKS1 and CKS0 bits in SMR that select th e baud

rate generator clock source, determines the serial communication bit rate.

Bit

Initial value

Read/Write

R/W

The CPU can always read and write BRR. BRR is initialized to H'FF by a r e set and in standby

mode. The two SCI channels have independent baud rate generator control, so different values can

be set in the two channels.

Table 13.3 shows examples of BRR settings in asynchronous mode. Table 13.4 shows examples of

BRR settings in synchronous mode.

Rev. 6.0, 09/02, page 467 of 876

Table 13.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode

φφ

φ (MHz)

2 2.097152 2.4576 3

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03

150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16

300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16

600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16

1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16

2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16

4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34

9600 0 6 –6.99 0 6 –2.48 0 7 0.00 0 9 –2.34

19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 –2.34

31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00

38400 0 1 –18.62 0 1 –14.67 0 1 0.00 — — —

φφ

φ (MHz)

3.6864 4 4.9152 5

Bit Rate

(bits/s) nN Error

(%) nN Error

(%)

110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25

150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16

300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16

600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16

1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16

2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16

4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36

9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73

19200 0 5 0.00 0 6 –6.99 0 7 0.00 0 7 1.73

31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00

38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73

Rev. 6.0, 09/02, page 468 of 876

φφ

φ (MHz)

6 6.144 7.3728 8

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03

150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16

300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16

600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16

1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16

2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16

4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16

9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16

19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16

31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00

38400 0 4 –2.34 0 4 0.00 0 5 0.00 0 6 –6.99

φφ

φ (MHz)

9.8304 10 12 12.288

Bit Rate

(bits/s) nN Error

(%) nN Error

(%)

110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08

150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00

300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00

600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00

1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00

2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00

4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00

9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00

19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00

31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40

38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00

Rev. 6.0, 09/02, page 469 of 876

φφ

φ (MHz)

13 14 14.7456 16

Bit Rate

(bits/s) n N Error

(%) n N Error

(%)

110 2 230 –0.08 2 248 –0.17 3 64 0.70 3 70 0.03

150 2 168 0.16 2 181 0.16 2 191 0.00 2 207 0.16

300 2 84 –0.43 2 90 0.16 2 95 0.00 2 103 0.16

600 1 168 0.16 1 181 0.16 1 191 0.00 1 207 0.16

1200 1 84 –0.43 1 90 0.16 1 95 0.00 1 103 0.16

2400 0 168 0.16 0 181 0.16 0 191 0.00 0 207 0.16

4800 0 84 –0.43 0 90 0.16 0 95 0.00 0 103 0.16

9600 0 41 0.76 0 45 –0.93 0 47 0.00 0 51 0.16

19200 0 20 0.76 0 22 –0.93 0 23 0.00 0 25 0.16

31250 0 12 0.00 0 13 0.00 0 14 –1.70 0 15 0.00

38400 0 10 –3.82 0 10 3.57 0 11 0.00 0 12 0.16

φφ

φ (MHz)

Bit Rate

(bits/s) nN Error

(%)

110 3 79 –0.12

150 2 233 0.16

300 2 116 0.16

600 1 233 0.16

1200 1 116 0.16

2400 0 233 0.16

4800 0 116 0.16

9600 0 58 –0.69

19200 0 28 1.02

31250 0 17 0.00

38400 0 14 –2.34

Rev. 6.0, 09/02, page 470 of 876

Table 13. 4 Examples of Bit Rates and BRR Settings in Synchronous Mode

φφ

φ (MHz)

2 4 8 10 13 16 18

Bit Rate

(bits/s) nN nN nN nN nN nN nN

110 370————————————

250 2 124 2 249 3 124 — — 3 202 3 249 — —

500 1 249 2 124 2 249 — — 3 101 3 124 3 140

1 k 1 124 1 249 2 124 — — 2 202 2 249 3 69

2.5 k 0 199 1 99 1 199 1 249 2 80 2 99 2 112

5 k 0 99 0 199 1 99 1 124 1 162 1 199 1 224

10 k 0 49 0 99 0 199 0 249 1 80 1 99 1 112

25 k 0 19 0 39 0 79 0 99 0 129 0 159 0 179

50 k 0 9 0 19 0 39 0 49 0 64 0 79 0 89

100 k 0 4 0 9 0 19 0 24 — — 0 39 0 44

250 k 0 1 0 3 0 7 0 9 0 12 0 15 0 17

500 k 0 0*01 03 04 —— 07 08

1 M 0 0*01 —— —— 03 04

2 M 0 0*—— —— 0 1 ——

2.5 M — — 0 0*—— —— ——

4 M 0 0*——

Note: Settings with an error of 1% or less are recommended.

Legend

Blank: No setting available

—: Setting possible, but error occurs

*: Continuous transmit/receive not possible

Rev. 6.0, 09/02, page 471 of 876

The BRR setting is calculated as follows:

Asynchronous mode:

N = 64 × 2

2n–1

× B× 10

– 1

Synchronous mode:

N = 8 × 2

2n–1

× B× 10

– 1

B: Bit rate (bits/s)

N: BRR setting for baud rate generator (0 ≤ N ≤ 255)

φ: System clo ck fr equ en cy (MH z)

n: Baud rate generator clock source (n = 0, 1, 2, 3)

(For the clock sources and values of n, see the following tabl e.)

SMR Settings

n Clock Source CKS1 CKS0

0φ00

1φ/4 0 1

2φ/16 1 0

3φ/64 1 1

The bit rate error in asynchronous mode is calculated as follows.

Error (%) = (N + 1) × B × 64 × 22n–1 – 1 × 100

φ × 106

Rev. 6.0, 09/02, page 472 of 876

Table 13.5 indicates the maximum bit rates in asynchronous mode for various system clock

frequencies. Tables 13.6 and 13.7 indicate the maximum bit rates with external clock input.

Table 13. 5 Maximum Bit Rates for Various Frequencies (Asynchrono us Mode)

Settings

φφ

φ (MHz) Maximum Bit Rate (bits/s) n N

2 62500 0 0

2.097152 65536 0 0

2.4576 76800 0 0

3 93750 0 0

3.6864 115200 0 0

4 125000 0 0

4.9152 153600 0 0

5 156250 0 0

6 187500 0 0

6.144 192000 0 0

7.3728 230400 0 0

8 250000 0 0

9.8304 307200 0 0

10 312500 0 0

12 375000 0 0

12.288 384000 0 0

14 437500 0 0

14.7456 460800 0 0

16 500000 0 0

17.2032 537600 0 0

18 562500 0 0

Rev. 6.0, 09/02, page 473 of 876

Table 13. 6 Maximum Bit Rate s with External Clock Input (Asynchronous Mode)

φφ

φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)

2 0.5000 31250

2.097152 0.5243 32768

2.4576 0.6144 38400

3 0.7500 46875

3.6864 0.9216 57600

4 1.0000 62500

4.9152 1.2288 76800

5 1.2500 78125

6 1.5000 93750

6.144 1.5360 96000

7.3728 1.8432 115200

8 2.0000 125000

9.8304 2.4576 153600

10 2.5000 156250

12 3.0000 187500

12.288 3.0720 192000

14 3.5000 218750

14.7456 3.6864 230400

16 4.0000 250000

17.2032 4.3008 268800

18 4.5000 281250

Table 13.7 Maximum Bit Rates with External Clock Input (Synchrono us Mode)

φφ

φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)

2 0.3333 333333.3

4 0.6667 666666.7

6 1.0000 1000000.0

8 1.3333 1333333.3

10 1.6667 1666666.7

12 2.0000 2000000.0

14 2.3333 2333333.3

16 2.6667 2666666.7

18 3.0000 3000000.0

Rev. 6.0, 09/02, page 474 of 876

13.3 Operation

13.3.1 Overview

The SCI has an asynchronous mode in which characters are synchronized individually, and a

synchronous mode in which communication is synchronized with clock pulses. Serial

communication is possible in either mode. Asynchronous or synchronous mode and the

communication format are selected in SMR, as shown in table 13.8. The SCI clock source is

selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13.9.

Asynchronous Mo de

• Data length is selectable: 7 or 8 bits.

• Parity and multiprocessor bits are selectab le. So is the stop bit length (1 or 2 bits). These

selections determine the communication format and character length.

• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break

state.

• An internal or external clock can be selected as the SCI clock source.

 When an internal clock is selected, the SCI operates using the on-chip baud rate generator,

and can output a serial clock signal with a frequency matching the bit rate.

 When an external clock is selected, the external clock input mu st have a frequency 16 times

the bit rate. (The on-chip baud rate generator is not used.)

Synchronous Mo de

• The communication format has a fixed 8-bit data length.

• In receiving, it is possible to detect overrun errors.

• An internal or external clock can be selected as the SCI clock source.

 When an internal clock is selected, the SCI operates using the on-chip baud rate generator,

and outputs a serial clock signal to external devices.

 When an external clock is selected, the SCI operates on the input serial clock. The on-chip

baud rate generator is not used.

Rev. 6.0, 09/02, page 475 of 876

Table 13.8 SMR Settings and Serial Communication Formats

SMR Settings SCI Communication Format

Bit 7:

C/A

ABit 6:

CHR Bit 2:

MP Bit 5:

PE Bit 3:

STOP Mode Data

Length

Multi-

processor

Bit Parity

Bit

Stop

Bit

Length

00000 8-bit dataAbsentAbsent1 bit

12 bits

1 0 Present 1 bit

12 bits

1 0 0 7-bit data Absen t 1 bit

12 bits

1 0 Present 1 bit

Asynchronous

mode

2 bits

0 1 — 0 8-bit data Present Absent 1 bit

12 bits

1 0 7-bit data 1 bit

Asynchronous

mode (multi-

processor

format) 2 bits

1 ———— Synchronous

mode 8-bit data Absent None

Table 13.9 SMR and SCR Settings and SCI Clock Source Selection

SMR SCR Settings SCI Transmit/Receive Clock

Bit 7:

C/A

ABit 1:

CKE1 Bit 0:

CKE0 Mode Clock

Source SCK Pin Function

0 0 0 SCI does not use the SCK pin

Internal

Outputs a clock with frequency

matching the bit rate

Asynchronous

mode

External Inputs a cloc k with frequency 16

times the bit rate

100

1Internal Outputs the serial clo ck

Synchronous

mode

External Inputs the serial clock

Rev. 6.0, 09/02, page 476 of 876

13.3.2 Operation in Asynchronous Mode

In asynchronous mode each transmitted or receiv ed character begins with a start bit and ends with

a stop bit. Serial communication is synchronized one character at a time.

The transmitting and receiving section s of the SCI are independent, so full duplex communication

is possible. The transmitter and receiver are both double buffered, so data can be written and read

while transmitting and receiving are in progress, enabling continuous transmitting and receiving.

Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous

serial communication the communication line is normally held in the mark (high) state. The SCI

monitors the line and starts serial communication when the line goes to the space (low) state,

indicating a start bit. One serial character consists of a star t bit (low), data (LSB first), par ity bit

(high or low), and stop bit (high), in that order.

When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.

The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.

Receive data is latched at the center of each bit.

Serial data 0 1 1

1Idle (mark) state

D0 D1 D2 D3 D4 D5 D6 D7 0/1

(LSB) (MSB)

Start

bit Transmit or receive data Parity

bit Stop

bit

One unit of data (character or frame)

1 bit 7 bits or 8 bits 1 bit or

no bit 1 bit or

2 bits

Figure 13.2 Data Format in Asynchronous Communication

(Example: 8-Bit Data with Parity and 2 Stop Bits)

Rev. 6.0, 09/02, page 477 of 876

Communication Formats: Table 13.10 shows the 12 communication formats that can be selected

in asynchronous mode. The format is selected by settings in SMR.

Table 13.10 Serial Communication Formats (Asynchronous Mo de)

SMR Settings Serial Communication Format and Frame Length

CHRPEMPSTOP 123456789101112

0000 S 8-bit data STOP

0001 S 8-bit data STOP STOP

0100 S 8-bit data PSTOP

0101 S 8-bit data P STOP STOP

1000 S 7-bit data STOP

1001 S 7-bit data STOP STOP

1100 S 7-bit data PSTOP

1101 S 7-bit data P STOP STOP

0—10 S 8-bit data MPB STOP

0—11 S 8-bit data MPB STOP STOP

1—10 S 7-bit data MPB STOP

1—11 S 7-bit data MPB STOP STOP

Legend

S: Start bit

STOP: Stop bit

P: Parity bit

MPB: Multiprocessor bit

Rev. 6.0, 09/02, page 478 of 876

Clock: An internal clock generated by the on-chip baud rate generator or an external clock input

from the SCK pin can be selected as th e SCI transmit/receive clock. The clock source is selected

by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 13.9.

When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the

desired bit rate.

When the SCI operates on an internal clock, it can outpu t a clock signal at the SCK pin. The

frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 13.3 so that

the rising edge of the clock occurs at the center of each transmit data bit.

0 D0D1D2D3D4D5D6D70/1 1 1

1 frame

Figure 13.3 Phase Relationship between Output Clock and Serial Data

(Asynchrono us Mo de)

Transmitting and Receiving Data

• SCI Initialization ( A synchron ous Mo de)

Before transmitting o r receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI

as follows.

When changing the communication mode or format, always clear the TE and RE bits to 0

before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and

initializes TSR. Clearin g RE to 0, howev er, do es not initialize the RDRF, PER, FER, and

ORER flags and RDR, which retain their previous contents.

When an exter nal clock is used, the clock should not be sto pped during initialization or

subsequent operation. SCI operation becomes unreliable if the clock is stopped.

Figure 13.4 is a sample flowchart for initializin g the SCI.

Rev. 6.0, 09/02, page 479 of 876

Clear TE and RE bits

to 0 in SCR

Transmitting or receiving

Yes

Select the communication format in SMR.

Write the value corresponding to the bit rate in BRR.

This step is not necessary when an external clock is used.

Select communication

format in SMR

Set value in BRR

Set TE or RE bit to 1 in SCR

Set RIE, TIE, TEIE, and

MPIE bits as necessary 4

1 bit interval

elapsed?

Wait

Wait for at least the interval required to transmit or receive

1 bit, then set the TE or RE bit to 1 in SCR. Set the RIE,

TIE, TEIE, and MPIE bits as necessary. Setting the TE

or RE bit enables the SCI to use the TxD or RxD pin.

Start of initialization

Set CKE1 and CKE0 bits

in SCR (leaving TE and

RE bits cleared to 0)

Select the clock source in SCR. Clear the RIE, TIE, TEIE,

MPIE, TE, and RE bits to 0. If clock output is selected in

asynchronous mode, clock output starts immediately after

the setting is made in SCR.

Figure 13.4 Sample Flowchart for SCI Initialization

Rev. 6.0, 09/02, page 480 of 876

• Transmitting Serial Data (Asynchronous Mode)

Figure 13 .5 sh ows a sample flowchart for tran smitting serial data and indicates the procedure

to follow.

Start transmitting

Read TDRE flag in SSR

TDRE = 1?

Write transmit data

in TDR and clear TDRE

flag to 0 in SSR

All data

transmitted?

End

Yes

SCI initialization: the transmit data output function

of the TxD pin is selected automatically.

SCI status check and transmit data write: read SSR,

check that the TDRE flag is 1, then write transmit data

in TDR and clear the TDRE flag to 0.

Read TEND flag in SSR

TEND = 1? No

Yes

Output break

signal? No

Yes

Clear TE bit to 0 in SCR

Clear DR bit to 0,

set DDR bit to 1

Initialize

To continue transmitting serial data: after checking

that the TDRE flag is 1, indicating that data can be

written, write data in TDR, then clear the TDRE

flag to 0. When the DMAC is activated by a transmit-

data-empty interrupt request (TXI) to write data in TDR,

the TDRE flag is checked and cleared automatically.

To output a break signal at the end of serial transmission:

set the DDR bit to 1 and clear the DR bit to 0

(DDR and DR are I/O port registers), then clear the

TE bit to 0 in SCR.

Figure 13.5 Sample Flowchart for Transmitting Serial Data

Rev. 6.0, 09/02, page 481 of 876

In transm itting serial data, the SCI operates as follows.

1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI

recognizes that TDR contains new data, and loads this data from TDR into TSR.

2. After loading the data from TDR into TSR, th e SCI sets the TDRE flag to 1 and starts

transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transm it-data-empty

interrup t ( T XI) at th is tim e.

Serial transmit da ta is tr ansmitted in the following order from the TxD pin :

a. Start bit: One 0 bit is o utput.

b. Transmit data: 7 or 8 bits are output, LSB first.

c. Parity bit or m ultiprocessor bit: One p arity bit (even or odd parity) or o ne

multiprocessor bit is output. Formats in which neither a parity bit nor a

multipro cessor bit is output can also be selected.

d. Stop bit: One or two 1 bits (stop bits) are output.

e. Mark state: Output o f 1 bits continues until the star t bit of the next transmit data.

3. The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI

loads new data from TDR into TSR, outpu ts the stop bit, then begins serial transmission of

the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, o utputs the

stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR,

a transmit-end interrupt (TEI) is requested at th is time.

Figure 13.6 shows an example of SCI transmit operation in asynchronous mode.

Start

bit

D0 D1 D7 0/1

Stop

bit

Data Parity

bit Start

bit

D0 D1 D7 0/1

Stop

bit

Data Parity

bit

Idle (mark)

state

TDRE

TEND

TXI

interrupt

request

TXI interrupt handler

writes data in TDR and

clears TDRE flag to 0

1 frame

TEI interrupt request

TXI

interrupt

request

Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode

(8-Bit Data with Parity and 1 Stop Bit)

Rev. 6.0, 09/02, page 482 of 876

• Receiving Serial Data (Asynchronous Mode)

Figure 13.7 shows a sample flowchart for receiving serial data and indicates the procedure to

follow.

Start receiving

Read RDRF flag in SSR

RDRF = 1?

Read receive data

from RDR, and clear

RDRF flag to 0 in SSR

PER FER

ORER = 1?

Clear RE bit to 0 in SCR

Finished

receiving?

End

Error handling

(continued on next page)

Yes

2, 3.

SCI initialization: the receive data function of

the RxD pin is selected automatically.

Receive error handling and break

detection: if a receive error occurs, read the

ORER, PER, and FER flags in SSR to identify

the error. After executing the necessary error

handling, clear the ORER, PER, and FER

flags all to 0. Receiving cannot resume if any

of the ORER, PER, and FER flags remains

set to 1. When a framing error occurs, the

RxD pin can be read to detect the break state.

SCI status check and receive data read: read

SSR, check that RDRF is set to 1, then read

receive data from RDR and clear the RDRF

flag to 0. Notification that the RDRF flag has

changed from 0 to 1 can also be given by the

RXI interrupt.

To continue receiving serial data: check the

RDRF flag, read RDR, and clear the RDRF

flag to 0 before the stop bit of the current

frame is received. If the DMAC is activated

by an RXI interrupt to read the RDR value,

the RDRF flag is cleared automatically.

Read ORER, PER,

and FER flags in SSR 2

Initialize

∨∨ 3

Figure 13.7 Sample Flowchart for Receiving Serial Data (1)

Rev. 6.0, 09/02, page 483 of 876

Yes

Framing error handling

PER = 1?

ORER = 1?

Overrun error handling

FER = 1?

Break?

Error handling

Parity error handling

Clear ORER, PER, and

FER flags to 0 in SSR

Clear RE bit to 0 in SCR

End

Figure 13.7 Sample Flowchart for Receiving Serial Data (2)

Rev. 6.0, 09/02, page 484 of 876

In receiving, the SCI operates as follows.

1. The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes

internally and starts receiving.

2. Receive data is stored in RSR in order from LSB to MSB.

3. The parity bit and stop bit are received.

After receiving, the SCI makes the following checks:

a. Parity check: The number of 1s in the receive data must match the even or odd parity

setting of the O/E bit in SMR.

b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first

stop bit is checked.

c. Status check: The RDRF flag must be 0 so that receive data can be transferred from

RSR into RDR.

If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If

one of the checks fails (receive error), the SCI operates as indicated in table 13.11.

Note: When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is

not set to 1. Be sure to clear the error flags to 0.

4. When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full

interrup t ( RXI) is r e quested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in

SCR is also set to 1, a receive-error interrupt (ERI) is requested.

Table 13.11 Receive Error Conditions

Receive Error Abbreviation Condition Data Transfer

Overrun error ORER Receiving of next data ends

while RDRF flag is still set

to 1 in SSR

Receive data not tran sferre d

from RSR to RDR

Framing error FER Stop bit is 0 Receive data transferred from

RSR to RDR

Parity error PER Parity of receive data differs

from even/odd parity setting

in SMR

Receive data transferre d from

RSR to RDR

Rev. 6.0, 09/02, page 485 of 876

Figure 13.8 shows an example of SCI receive operation in asynchronous mode.

1Start

bit

0D0 D1 D7 0/1

Stop

bit

Data Parity

bit Start

bit

0D0 D1 D7 0/1

Stop

bit

Data Parity

bit 1

Idle (mark)

state

RDRF

FER

1 frame Framing error,

ERI request

RXI interrupt handler

reads data in RDR and

clears RDRF flag to 0

RXI

request

Figure 13.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)

13.3.3 Multiprocessor Communication

The multipr ocessor communication fun c tion enables several processo rs to share a single serial

communication line. The processors communicate in asynchronous mode using a format with an

addition a l multiprocessor bit (multiprocesso r format).

In multiprocessor communication , each receiving processor is ad d r essed by an ID. A serial

communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a

data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending

cycles.

The transmitting p rocesso r starts b y sending the ID of the receiving processor with which it wants

to communicate as d a ta with the multiprocessor bit set to 1. Next the tran smitting processor sends

transmit data with the multiprocessor bit cleared to 0.

Receiving pr ocessors skip incoming data until they receive data with the multiprocessor b it set

to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the

data with their IDs. The receiving processor with a matching ID continues to receive further

incoming data. Processors with IDs not matching the received data skip further incoming data

until they ag ain receive data with the multiprocessor bit set to 1 . Multiple processors can send and

receive data in this way.

Figure 13.9 shows an example of communication among different processors using a

multiprocessor format.

Rev. 6.0, 09/02, page 486 of 876

Communication Formats: Four formats are av ailable. Parity-bit settings are ignored when a

multipro cessor format is selected. For details see table 13.10.

Clock: See the description of asynchronous mode.

Transmitting

processor

Receiving

processor A

Serial communication line

Receiving

processor B Receiving

processor C Receiving

processor D

(ID = 01) (ID = 02) (ID = 03) (ID = 04)

Serial data

H'01 H'AA

(MPB = 1) (MPB = 0)

ID-sending cycle: receiving

processor address Data-sending cycle:

data sent to receiving

processor specified by ID

Legend

MPB: Multiprocessor bit

Figure 13.9 Example of Communication among Processors using Multiprocessor Format

(Sending Data H'AA to Receiving Processor A)

Rev. 6.0, 09/02, page 487 of 876

Transmitting and Receiving Data

• Transmitting Multiprocessor Ser ial Data

Figure 13.10 shows a sample flowchart for transmittin g multiprocessor serial data and

indicates the procedure to follow.

Yes

Initialize

Start transmitting

Read TDRE flag in SSR

TDRE = 1?

Write transmit data in

TDR and set MPBT bit in SSR

Clear TDRE flag to 0

All data transmitted?

Read TEND flag in SSR

TEND = 1?

SCI initialization: the transmit data

output function of the TxD pin is

selected automatically.

SCI status check and transmit data

write: read SSR, check that the TDRE

flag is 1, then write transmit

data in TDR. Also set the MPBT flag to

0 or 1 in SSR. Finally, clear the TDRE

flag to 0.

To continue transmitting serial data:

after checking that the TDRE flag is 1,

indicating that data can be

written, write data in TDR, then clear

the TDRE flag to 0. When the DMAC

is activated by a transmit-data-empty

interrupt request (TXI) to write data in

TDR, the TDRE flag is checked and

cleared automatically.

To output a break signal at the end of

serial transmission: set the DDR bit to

1 and clear the DR bit to 0 (DDR and

DR are I/O port registers), then clear

the TE bit to 0 in SCR.

Output break signal?

Clear DR bit to 0, set DDR bit to 1

Clear TE bit to 0 in SCR

End

Figure 13.10 Sample Flowchart for Transmitting M ultiproces sor Serial Data

Rev. 6.0, 09/02, page 488 of 876

In transm itting serial data, the SCI operates as follows.

1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI

recognizes that TDR contains new data, and loads this data from TDR into TSR.

2. After loading the data from TDR into TSR, th e SCI sets the TDRE flag to 1 and starts

transmitting. If the TIE bit in SCR is set to 1, the SCI requests a transmit-d a ta- e mpty

interrup t ( T XI) at th is tim e.

Serial transmit da ta is tr ansmitted in the following order from the TxD pin :

a. Start bit: One 0 bit is o utput.

b. Transmit data: 7 or 8 bits are output, LSB first.

c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.

d. Stop bit: One or two 1 bits (stop bits) are output.

e. Mark state: Output o f 1 bits continues until the star t bit of the next transmit data.

3. The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI

loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the

next fram e. If the TDRE flag is 1, the SCI sets the TEND flag in SSR to 1, outputs th e stop

bit, then continu e s output of 1 bits in the mark state. I f the TEI E bit is set to 1 in SCR, a

transmit-en d interrupt (TEI) is requested at this time.

Figure 13.11 shows an examp le of SCI tr ansmit operation using a multiprocessor f ormat.

1Start

bit

0D0 D1 D7 0/1

Stop

bit

Data

Multi-

processor

bit

Start

bit

0D0 D1 D7 0/1

Stop

bit

Data 1

Idle (mark)

state

TDRE

TEND

TXI

request TXI interrupt handler

writes data in TDR and

clears TDRE flag to 0

1 frame

TEI request

Multi-

processor

bit

TXI

request

Figure 13.11 Example of SCI Transmit Operation

(8-Bit Data with Multiprocessor Bit and One Stop Bit)

Rev. 6.0, 09/02, page 489 of 876

• Receiving Multipro cessor Serial Data

Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data and indicates

the procedure to follow.

Initialize

Start receiving

Read RDRF flag in SSR

RDRF = 1?

Read receive data from RDR

Read ORER and FER flags in SSR

FER ORER = 1

Read RDRF flag in SSR

∨

RDRF = 1?

Read receive data from RDR

Finished receiving?

Clear RE bit to 0 in SCR

Error handling

(continued on next page)

End

SCI initialization: the receive data function

of the RxD pin is selected automatically.

ID receive cycle: set the MPIE bit to 1 in SCR.

SCI status check and ID check: read SSR,

check that the RDRF flag is set to 1, then read

data from RDR and compare with the

processor’s own ID. If the ID does not match,

set the MPIE bit to 1 again and clear the

RDRF flag to 0. If the ID matches, clear the

RDRF flag to 0.

SCI status check and data receiving: read

SSR, check that the RDRF flag is set to 1,

then read data from RDR.

Receive error handling and break detection:

if a receive error occurs, read the

ORER and FER flags in SSR to identify the error.

After executing the necessary error handling,

clear the ORER and FER flags both to 0.

Receiving cannot resume while either the ORER

or FER flag remains set to 1. When a framing

error occurs, the RxD pin can be read to detect

the break state.

Yes

Set MPIE bit to 1 in SCR

Read ORER and FER flags in SSR

Yes

FER ORER = 1

∨

Own ID?

Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1)

Rev. 6.0, 09/02, page 490 of 876

Yes

Error handling

ORER = 1?

Overrun error handling

FER = 1?

Break?

Framing error handling

Clear ORER, PER, and FER

flags to 0 in SSR

Clear RE bit to 0 in SCR

End

Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)

Figure 13.13 shows an example of SCI receive operation using a multiprocessor format.

Rev. 6.0, 09/02, page 491 of 876

1Start

bit

0D0 D1 D7 1

Stop

bit

Data (ID1) MPB Start

bit

0D0 D1 D7 0

Stop

bit

Data (data1) MPB 1

Idle (mark)

state

MPIE

RDRF

RDR value ID1

RXI request

(multiprocessor

interrupt)

MPB detection

MPIE= 0

MPB detection

MPIE= 0

RXI handler reads

RDR data and clears

RDRF flag to 0

Not own ID, so

MPIE bit is set

to 1 again

No RXI request,

RDR not updated

a. Own ID does not match data

1Start

bit

0D0 D1 D7 1

Stop

bit

Data (ID2) MPB Start

bit

0D0 D1 D7 0

Stop

bit

Data (data2) MPB 1

Idle (mark)

state

MPIE

RDRF

RDR value ID2

RXI request

(multiprocessor

interrupt)

RXI interrupt handler

reads RDR data and

clears RDRF flag to 0

Own ID, so receiving

continues, with data

received by RXI

interrupt handler

MPIE bit is set

to 1 again

b. Own ID matches data

Data 2

Figure 13.13 Example of SCI Receive Operation

(8-Bit Data with Multiprocessor Bit and One Stop Bit)

Rev. 6.0, 09/02, page 492 of 876

13.3.4 Synchronous Operation

In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.

This mode is suitable for high-speed serial communication.

The SCI transmitter and receiver share the same clo ck but are otherwise indep e nden t, so full

duplex communication is possible. The tran smitter and receiver are also double buffered, so

continuous transmittin g or receiving is possible by reading or writing data while tran smitting or

receiving is in progress.

Figure 13.14 shows the general format in synchronous serial communication.

Serial clock

Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

LSB MSB

Don’t care Don’t care

One unit (character or frame) of serial data

* *

Note: High except in continuous transmitting or receiving*

Figure 13.14 Data Format in Synchronous Communication

In synchronous serial communication, each data bit is placed on the communication line from one

falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.

In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After

output of the MSB, the communication line remains in the state of the MSB. In synchronous mode

the SCI receives data by synchronizing with the rise of the serial clock.

Communication Format: The data length is fixed at 8 bits. No parity bit or multiprocessor bit

can be added.

Clock: An internal clock generated by the on-chip baud rate generator or an external clock input

from the SCK pin can be selected by clearing or setting the CKE1 bit in SCR. See table 13.9.

When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock

pulses are output per transmitted or receiv ed character.

When the SCI operates on an internal clock, the serial clock outputs the clock signal at the SCK

pin. Eight clock pulses are output per transmitted or received character. When the SCI is not

transmitting or receiving, the clock signal remains in the high state. Howev e r, when receiving

only, overrun erro r may occur or the serial clock continues output until the RE bit clears at 0 .

When transmitting o r receiving in sing le characters, select the external clock.

Rev. 6.0, 09/02, page 493 of 876

Transmitting and Receiving Data

• SCI Initialization (Synchronous Mode)

Before transmitting or receiving, clear the TE and

RE bits to 0 in SCR, then initialize the SCI as follows.

When changing the communication mode or format, always clear the TE and RE bits to 0

before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1

and initializes TSR. Clearin g the RE bit to 0, h owever, does not initialize the RDRF, PER,

FER, and ORE flags and RDR, which retain their previous contents.

Figure 13.15 is a sample flowchart for in itializing the SCI.

Clear TE and RE

bits to 0 in SCR

1 bit interval

elapsed?

Start transmitting or receiving

Yes

Select the clock source in SCR.Clear the RIE, TIE, TEIE,

MPIE, TE, and RE bits to 0.

Select the communication format in SMR.

Write the value corresponding to the bit rate in BRR.

This step is not necessary when an external clock is used.

Set RIE, TIE, TEIE, MPIE,

CKE1, and CKE0 bits in SCR

(leavingTE and RE bits

cleared to 0)

Set TE or RE to 1 in SCR

Set RIE, TIE, TEIE, and

MPIE bits as necessary 4

Wait

Wait for at least the interval required to transmit or receive

one bit, then set the TE or RE bit to 1 in SCR. Also set

the RIE, TIE, TEIE, and MPIE bits as necessary.

Setting the TE or RE bit enables the SCI to use the

TxD or RxD pin.

Start of initialization

Set value in BRR

Select communication

format in SMR

Note: In simultaneous transmitting and receiving, the TE and

RE bits should be cleared to 0 or set to 1 simultaneously.

Figure 13.15 Sample Flowchart for SCI Initialization

Rev. 6.0, 09/02, page 494 of 876

• Transmitting Ser ial Data (Sy nchronous Mode)

Figure 13.16 shows a sample flowch ar t for tr ansmitting serial data and indicates the procedure

to follow.

Start transmitting

Read TDRE flag in SSR

TDRE = 1?

Write transmit data in

TDR and clear TDRE flag

to 0 in SSR

End

Yes

SCI initialization: the transmit data output function

of the TxD pin is selected automatically.

SCI status check and transmit data write: read SSR,

check that the TDRE flag is 1, then write transmit

data in TDR and clear the TDRE flag to 0.

Read TEND flag in SSR

Yes

Initialize

Clear TE bit to 0 in SCR

To continue transmitting serial data: after checking

that the TDRE flag is 1, indicating that data can be

written, write data in TDR, then clear the TDRE flag

to 0. When the DMAC is activated by a transmit-

data-empty interrupt request (TXI) to write data in

TDR, the TDRE flag is checked and cleared

automatically.

All data

transmitted?

TEND = 1?

Figure 13.16 Sample Flowchart for Serial Transmitting

Rev. 6.0, 09/02, page 495 of 876

In transm itting serial data, the SCI operates as follows.

1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI

recognizes that TDR contains new data, and loads this data from TDR into TSR.

2. After loading the data from TDR into TSR, th e SCI sets the TDRE flag to 1 and starts

transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transm it-data-empty

interrup t ( T XI) at th is tim e.

If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock

source is selected, the SCI outputs data in synchron ization with the input clock. Data is

output from the TxD pin in order from LSB (bit 0) to MSB (bit 7).

3. The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the

SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the

TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB,

holds the TxD pin in the MSB state. If the TEIE bit in SCR is set to 1 , a transmit-end

interrupt ( TEI) is r e quested at this time.

4. After the end of serial transmission, the SCK pin is held in a constant state.

Figure 13.17 shows an example of SCI transmit operation.

Transmit

direction

Serial clock

Serial data

TDRE

TEND

Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

TXI interrupt handler

writes data in TDR

and clears TDRE

flag to 0

TXI

request TEI

request

1 frame

TXI

request

Figure 13.17 Example of SCI Transmit Operation

Rev. 6.0, 09/02, page 496 of 876

• Receiving Serial Data

Figure 13.18 shows a sample flowchart for receiving serial data and indicates the procedure to

follow. When switching from asynchronous mode to synchronous mode, make sure that the

ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag

will not be set and both transmitting and receiving will be disabled.

Start receiving

Read RDRF flag in SSR

Read receive data

from RDR, and clear

RDRF flag to 0 in SSR

Read ORER flag in SSR

Clear RE bit to 0 in SCR

End

Error handling

continued on next page

Yes

2, 3.

SCI initialization: the receive data function of

the RxD pin is selected automatically.

Receive error handling: if a receive error

occurs, read the ORER flag in SSR, then after

executing the necessary error handling, clear

the ORER flag to 0. Neither transmitting nor

receiving can resume while the ORER flag

remains set to 1.

SCI status check and receive data read: read

SSR, check that the RDRF flag is set to 1,

then read receive data from RDR and clear

the RDRF flag to 0. Notification that the RDRF

flag has changed from 0 to 1 can also be

given by the RXI interrupt.

To continue receiving serial data: check the

RDRF flag, read RDR, and clear the RDRF

flag to 0 before the MSB (bit 7) of the current

frame is received. If the DMAC is activated

by a receive-data-full interrupt request (RXI)

to read RDR, the RDRF flag is cleared

automatically.

Initialize

RDRF = 1?

ORER = 1?

Finished

receiving?

Figure 13.18 Sample Flowchart for Serial Receiving (1)

Rev. 6.0, 09/02, page 497 of 876

End

Error handling

Overrun error handling

Clear ORER flag to 0 in SSR

Figure 13.18 Sample Flowchart for Serial Receiving (2)

In receiving, the SCI operates as follows.

1. The SCI synchronizes with serial clock input or output and initializes internally.

2. Receive data is stored in RSR in order from LSB to MSB.

After receiving the data, the SCI checks that the RDRF flag is 0 so that receive data can be

transferre d from RSR to RDR. If th is check passes, the RDRF flag is set to 1 and the

received data is stored in RDR. If the check does not pass (receive error), the SCI operates

as indicated in table 13.11.

3. After settin g the RDRF flag to 1, if the RIE bit is set to 1 in SCR, the SCI requests a

receive-data-full interrupt (RXI). If the ORER flag is set to 1 and the RIE bit in SCR is also

set to 1, the SCI requests a receive-error interrupt (ERI).

Figure 13.19 shows an example of SCI receive operation.

Rev. 6.0, 09/02, page 498 of 876

Serial clock

Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

RXI

request

Receive direction

RDRF

ORER

RXI interrupt

handler reads

data in RDR

and clears

RDRF flag to 0

Overrun error,

ERI request

1 frame

RXI

request

Figure 13.19 Example of SCI Receive Operation

• Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode)

Figure 13.20 shows a sample flowchart for transmitting and receiving serial data

simultaneously and indicates the procedure to follow.

Rev. 6.0, 09/02, page 499 of 876

Yes

Initialize

Start transmitting and receiving

Read TDRE flag in SSR

TDRE = 1?

Write transmit data in TDR and

clear TDRE flag to 0 in SSR

RDRF = 1?

Read RDRF flag in SSR

Read receive data from RDR

and clear RDRF flag to 0 in SSR

Read ORER flag in SSR

ORER = 1?

End of transmitting and

receiving?

SCI initialization: the transmit data

output function of the TxD pin and

receive data input function of the

RxD pin are selected, enabling

simultaneous transmitting and

receiving.

SCI status check and transmit

data write: read SSR, check that

the TDRE flag is 1, then write

transmit data in TDR and clear

the TDRE flag to 0.

Error handling

Note: When switching from tr ansmitting or receiving to simultaneous

transmitting and receiving, clear both theTE bit and the RE bit

to 0, then set both bits to 1.

Clear TE and RE bits to 0 in SCR

End

Notification that the TDRE flag has

changed from 0 to 1 can also be

given by the TXI interrupt.

Receive error handling:if a receive

error occurs, read the ORER flag in

SSR, then after executing the neces-

sary error handling, clear the ORER

flag to 0.

Neither transmitting nor receiving

can resume while the ORER flag

remains set to 1.

SCI status check and receive

data read: read SSR, check that

the RDRF flag is 1, then read

receive data from RDR and clear

the RDRF flag to 0. Notification

that the RDRF flag has changed

from 0 to 1 can also be given

by the RXI interrupt.

To continue transmitting and

receiving serial data: check the

RDRF flag, read RDR, and clear

the RDRF flag to 0 before the

MSB (bit 7) of the current frame

is received.Also check that

the TDRE flag is set to 1, indicat-

ing that data can be written, write

data in TDR, then clear the TDRE

flag to 0 before the MSB (bit 7) of

the current frame is transmitted.

When the DMAC is activated by

a transmit-data-empty interrupt

request (TXI) to write data in TDR,

the TDRE flag is checked and

cleared automatically.When the

DMAC is activated by a receive-

data-full interrupt request (RXI) to

read RDR, the RDRF flag is

cleared automatically.

Figure 13.20 Sample Flowchart for Serial Transmitting

Rev. 6.0, 09/02, page 500 of 876

13.4 SCI Interrupts

The SCI has four in terrupt request sources: TEI (transmit-end interrupt), ERI (receive-error

interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 13.12

lists the interrupt sources and indicates th eir priority. These interrupts can be enabled and disabled

by the TIE, TEIE, and RIE bits in SCR. Each interrupt request is sent sep ar a tely to the interrupt

controller.

The TXI interrupt is requested when the TDRE flag is set to 1 in SSR. The TEI interrupt is

requested when the TEND flag is set to 1 in SSR. The TXI interrupt request can activate the

DMAC to transfer data. Data transfer by the DMAC automatically clears the TDRE flag to 0. The

TEI interrupt request cannot activate the DMAC.

The RXI interrupt is requested when the RDRF flag is set to 1 in SSR. The ERI interrupt is

requested when the ORER, PER, or FER flag is set to 1 in SSR. The RXI interrupt requ est can

activate the DMAC to transfer data. Data transfer by the DMAC automatically clears the RDRF

flag to 0. The ERI interrupt request cannot activate the DMAC.

The DMAC can be activated by interrupts from SCI channel 0.

Table 13.12 SCI Interrupt Sources

Interrupt Description Priority

ERI Receive error (ORER, FER, or PER)

RXI Receive data register full (RDRF)

TXI Transmit data register empty (TDRE)

TEI Transmit end (TEND)

High

↑



Low

Rev. 6.0, 09/02, page 501 of 876

13.5 Usage Notes

Note the following points when using the SCI.

TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of

transmit data f rom TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from

TDR to TSR.

Data can be written in to TDR regardless of the state of the TDRE flag. If new data is written in

TDR when the TDRE flag is 0 , the old data stored in TDR will be lost b ecause this data has no t

yet been transfer r ed to TSR. Before writing transmit data in TDR, be sure to check that the TDRE

flag is set to 1.

Simultaneous Multiple Receive Errors: Table 13.13 indicates the state of SSR status flags when

multiple receive errors occur simultaneou sly. Wh en an overrun error occurs the RSR contents are

not transferred to RDR, so receive data is lost.

Table 13.13 SSR Status Flags and Transfer of Receive Data

RDRF ORER FER PER

Receive Data

Transfer

RSR →

→→

→ RDR Receive Errors

1100×Overrun error

0010O Framing error

0001O Parity error

1110×Overrun error + framing error

1101×Overrun error + parity error

0011O Framing error + parity error

1111×Overrun error + framing error + parity error

Notes: O: Receive data is transferred from RSR to RDR.

×: Receive data is not transferred from RSR to RDR.

Rev. 6.0, 09/02, page 502 of 876

Break Detection and Processing: Break signals can be detected by reading the RxD pin directly

when a framing error (FER) is detected. In the break state the input from the RxD pin consists of

all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the

SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.

Sending a Break Signal: When the TE bit is cleared to 0 the TxD pin becomes an I/O port, the

level and direction (input or output) of which are determined by DR and DDR bits. This feature

can be used to send a break signal.

After the serial tran smitter is initialized, the DR value substitutes for the mark state until the TE

bit is set to 1 (the TxD pin function is not selected until th e TE bit is set to 1). The DDR and DR

bits should therefore both be set to 1 beforehand.

To send a break signal during serial transmission, clear the DR bit to 0, then clear the TE bit to 0.

When the TE bit is clear ed to 0 the transmitter is initialized, r e gardless of its cur rent state, so the

TxD pin become s an output port outputtin g the value 0.

Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive

error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmittin g, even if the TDRE

flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that

clearing the RE bit to 0 does not clear the receive error flags to 0.

Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous

mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI

synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive

data is latched at the rising edge of the eighth base clock pulse. See figure 13.21.

Internal

base clock

Receive data

(RxD)

Synchronization

sampling timing

Data sampling

timing

0715 0 715 0

8 clocks

16 clocks

Start bit

Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode

Rev. 6.0, 09/02, page 503 of 876

The receive margin in asynchronous mode can therefore be expressed as in equation (1).

M = (0.5 – 1

2N D – 0.5

) – (L – 0.5) F – (1 + F) × 100%

................... (1)

M: Receive margin (% )

N: Ratio of clock frequency to bit rate (N = 16)

D: Clock duty cycle (D = 0 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute deviation of clo ck frequ enc y

From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).

D = 0.5, F = 0

M = {0.5 – 1/(2 × 16)} × 100%

= 46.875% ............................................................................................. (2)

This is a theoretical value. A reasonable marg in to allo w in system designs is 20% to 30%.

Restrictions on Usage of DMAC: To have the DMAC read RDR, be sure to select the SCI

receive-data-full interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.

Restrictions on Usage of the Serial Clock: When transmitting d a ta using an external clock as the

serial clock, an interval of at least 5 states is necessary between clearing the TDRE bit in SSR and

the start (falling edge) of the first transmit clock pulse corresponding to each frame (see figure

13.22). Th is condition is also needed for contin uous transmission. I f it is not fulfilled, operational

error will occur.

Ensure that t ≥ 5 states.

SCK

TDRE

TXD

t*t*

Continuous transmission

X0 X1 X2 X3 Y0 Y1 Y2 Y3X4 X5 X6 X7

Note:*

Figure 13.22 Serial Clock Transmission (Example)

Rev. 6.0, 09/02, page 504 of 876

Switching SCK Pin t o Port Output P in F unction in Synchronous Mode: When the SCK pin is

used as the serial clock output in synchronous mode, and is then switched to its output port

function at th e end of transmission, a low level may be output for one half-cycle. Half-cycle low-

level output occurs when SCK is switched to its port function with the following settings when

DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1.

1. End of serial data transmission

2. TE bit = 0

3. C/A bit = 0 ... switchover to port output

4. Occurrence of low-level output (see figure 13.23)

SCK/port

Data

CKE1

CKE0

Bit 7Bit 6

1. End of transmission 4. Low-level output

3. C/ = 0

2. TE = 0

Half-cycle low-level output

Figure 13.23 Operation when Switching from SCK Pin Function to Port Pin Function

Rev. 6.0, 09/02, page 505 of 876

Sample Procedure for Preventing Low-Level Output

As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin

should be pulled up beforehand with an external circuit.

With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings

in the order shown.

1. End of serial data transmission

2. TE bit = 0

3. CKE1 bit = 1

4. C/A bit = 0 ... switchover to port output

5. CKE1 bit = 0

SCK/port

Data

CKE1

CKE0

Bit 7Bit 6

1. End of transmission

3. CKE1 = 1 5. CKE1 = 0

4. C/ = 0

2. TE = 0

High-level output

Figure 13.24 Operation when Switching from SCK Pin Function to Port Pin Function

(Example of Preventing Low-Level Output)

Rev. 6.0, 09/02, page 506 of 876

Rev. 6.0, 09/02, page 507 of 876

Section 14 Smart Card Interface

14.1 Overview

As an extension of its serial communication interface functions, SCI0 supports a smart card (IC

card) interface conforming to the ISO/IEC7816-3 (Identification Card) standard. Switchover

between normal serial communication and the smart card interface is controlled by a register

setting.

14.1.1 Features

Features of the smart-card interface supported by the H8/3048 Series are listed below.

• Asynchronous communication

 Data length: 8 bits

 Parity bits generated and checked

 Error signal outpu t in receive mode (parity error)

 Error sig nal detect and automatic data r etransm it in transmit mode

 Supports both direct convention and inverse convention

• Built-in baud rate generator with selectab le bit rates

• Three types of interrupts

Transmit-data-empty, receive-data-full, and receive-error interrupts are requested

independently. The transmit-data-empty and receive-data-full interrupts can activate the DMA

controller ( DMAC) to transfer data.

Rev. 6.0, 09/02, page 508 of 876

14.1.2 Block Diagram

Figure 14.1 shows a block diagram of the smart card interface.

Module data bus Internal

data

bus

BRR

SCMR

Baud rate

generator

Transmit/receive

control

RDR

TSRRSR

Bus interface

SSR

SCR

SMR

TDR

Legend

SCMR:

RSR:

RDR:

TSR:

TDR:

SMR:

SCR:

SSR:

BRR:

Smart card mode register

Receive shift register

Receive data register

Transmit shift register

Transmit data register

Serial mode register

Serial control register

Serial status register

Bit rate register

φ/4

φ/16

φ/64

TXI

Clock

Parity generate

Parity check

RxD

TxD

SCK

RXI

ERI

Figure 14.1 Smart Card Interface Block Diagram

Rev. 6.0, 09/02, page 509 of 876

14.1 .3 Input/Output Pins

Table 14.1 lists the sm art card interface pins.

Table 14.1 Smart Card Interface Pins

Name Abbreviation I/O Function

Serial clock pin SCK0Output Clock output

Receive data pin RxD0Input Receive data input

Transmit data pin TxD0Output Transmit dat a output

14.1.4 Register Configuration

The smart card interface has the internal registers listed in table 14.2. BRR, TDR, and RDR have

their normal serial communication interface functions, as described in section 13, Serial

Communication Interface.

Table 14.2 Registers

Address*1Name Abbreviation R/W Initial Value

H'FFB0 Serial mode register SMR R/W H'00

H'FFB1 Bit rate register BRR R/W H'FF

H'FFB2 Serial co ntrol register SCR R/W H' 00

H'FFB3 Transmit dat a regist er TDR R/W H'FF

H'FFB4 Serial stat us regi ster SSR R/(W)*2F'84

H'FFB5 Recei ve data regi ster RDR R H'00

H'FFB6 Smart card mode register SCMR R/W H'F2

Notes: *1 Lower 16 bits of the address.

*2 Only 0 can be written, to clear flags.

Rev. 6.0, 09/02, page 510 of 876

14.2 Register Descriptions

This section describes the new or modified registers and bit functions in the smart card interface.

14.2.1 Smart Card Mode Register (SCMR)

SCMR is an 8-bit readable/writable register that selects smart card interface functions.

Bit

Initial value

Read/Write

—

SDIR

R/W

SMIF

R/W

SINV

R/W

—

Reserved bits

Smart card data transfer direction

Selects the serial/parallel conversion format

Smart card data invert

Inverts data logic levels

Smart card interface

mode select

Enables or disables

the smart card

interface function

Reserved bits

SCMR is initial ized to H'F2 by a reset and in standby mode.

Bits 7 to 4—Reserved: Read-only bits, always read as 1.

Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion

format.

Bit 3: SDIR Description

0 TDR contents are transmitted LSB-first (Initial value)

Received data is stored LSB-firs t in RDR

1 TDR contents are transmitted MSB-first

Received data is stored MSB-first in RDR

Rev. 6.0, 09/02, page 511 of 876

Bit 2—Smart Card Data Inverter (SINV): Inverts data logic levels. This function is used in

combination with bit 3 to communicate with inverse-convention cards. SINV does not affect the

logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings.

Bit 2: SINV Description

0 Unmodified TDR contents are transmitted (Initial value)

Received data is stored unmodified in RDR

1 Inverted TDR contents are transmitted

Received data is inverted before storage in RDR

Bit 1—Reserved: Read-only bit, always read as 1.

Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.

Bit 0: SMIF Description

0 Smart card interfac e funct ion is di sabl ed (Initial val ue)

1 Smart card interfac e funct ion is ena ble d

14.2.2 Serial Status Register (SSR)

The function of SSR bit 4 is modified in the smart card in terface. This change also causes a

modification to the setting conditions for bit 2 (TEND).

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

ERS

R/(W)*

PER

R/(W)*

MPBT

R/W

TEND

MPB

Error signal status (ERS)

Status flag indicating that an

error signal has been received

Transmit end

Status flag indicating

end of transmission

Rev. 6.0, 09/02, page 512 of 876

Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13,

Serial Communication Interface.

Bit 4—Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of

the error signal sent from the receiving device to the transmitting dev ice. The smart card interface

does not detect framing errors.

Bit 4: ERS Description

0 Indicates normal data transmission, with no error signal returned (Initial value)

[Clearing cond iti ons ]

The chip is reset or enters standby mode.

Software reads ERS while it is set to 1, then writes 0.

1 Indicates that the receiving device sent an error signal reporting a parity error

[Setting condition]

A low error signal was sampled.

Note: Clearing the TE bi t to 0 in SCR does not affect the ERS flag, which retains its previous

value.

Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13,

Serial Communication Interface. The setting conditions for transmit end (TEND, bit 2), however,

are modified as follows.

Bit 2: TEND Description

0 Transmiss ion is in pr ogre ss

[Clearing cond iti ons ]

Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.

The DMAC writes data in TDR.

1 End of transmission (Initial value)

[Setting conditions]

The chip is reset or enters standby mode.

The TE bit and FER/ERS bit are both cle ared to 0 in SCR.

TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte

serial charac ter is transmitted (normal transmission)

Note: An etu (elementary time unit) is the time needed to transmit one bit.

Rev. 6.0, 09/02, page 513 of 876

14.2.3 Serial Mode Register (SMR)

Bit 7 of SMR has a different function in smart card interface mode. The related serial control

memory version.

Bit

Initial value

Read/Write

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit 7-GSM Mode (GM): Set at 0 when using the regular smart card interface. In GSM mode, set

to 1. When tr ansm issio n is complete, initially the TEND flag set timing appears followed by clock

output restriction mode. Clock output restriction mode comprises serial control register bit 1 and

bit 0.

Bit 7: GM Description

0 Using the regular smart card interface mode

• The TEND flag is set 12.5 etu after the beginning of the start bit (Initial value)

• Clock output on/off control only

1 Using the GSM mode smart card interface mode

• The TEND flag is set 11.0 etu after the beginning of the start bit

• Clock output on/off and fixed-high/fixed-low control

Bits 6 to 0—Operate in the same way as for the normal SCI.

For details, see section 13.2.5, Serial Mode Register (SMR).

Rev. 6.0, 09/02, page 514 of 876

14.2.4 Serial Control Register (SCR)

Bits 1 and 0 have different functions in smart card interface mode. However, this function does

not exist in the flash memory version.

Bit

Initial value

Read/Write

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bits 7 to 2—Operate in the same way as for the normal SCI.

For details, see section 13.2.6, Serial Control Register (SCR).

Bits 1 and 0—Clock Enable (CKE1, CKE0): Setting enable or disable for the SCI clock

selection and clock output from the SCK pin. In smart card interface mode, it is possible to switch

between enabling and disabling of the normal clock output, and specify a fixed high level or fixed

low level for the clock output.

SMR SCR

Bit 7:

GM Bit 1:

CKE1 Bit 0:

CKE0 Description

0 0 0 The internal clock/SCK0 pin functions as an I/O port (Initial value)

0 0 1 The internal clock/SCK0 pin functions as the clock output

1 0 0 The internal clock/SCK0 pin is fixed at low-level output

1 0 1 The internal clock/SCK0 pin functions as the clock output

1 1 0 The internal clock/SCK0 pin is fixed at high-level output

1 1 1 The internal clock/SCK0 pin functions as the clock output

Rev. 6.0, 09/02, page 515 of 876

14.3 Operation

14.3.1 Overview

The main features of the smart-card interface are as fo llows.

• One frame consists of eig ht data bits and a parity bit.

• In transmittin g, a guard time of at least two elementary tim e units ( 2 etu) is provided between

the end of the parity bit and the start of the next frame. (An elem entary time unit is the time

required to transmit one bit.)

• In receiving, if a parity error is detected, a low error signal is output for 1 etu, beginning 10.5

etu after the start bit.

• In transmitting, if an error signal is received, after at least 2 etu, the same data is automatically

transmitted ag ain.

• Only asynchronous communication is supported. There is no synchronous communication

function.

14.3.2 Pin Connections

Figure 14.2 shows a pin connection diagram for the smart card interface.

In communication with a smart card, data is transmitted an d received over the same signal line.

The TxD0 and RxD0 pins should both be connected to this line. The data transmission line should

be pulled up to VCC through a resistor.

If the smart card uses the clock generated by the smart card interface, connect the SCK0 output pin

to the card’s CLK input. If the card uses its own internal clock, this connection is un necessary.

The reset signal should be output from one of the H8/3048 Series’ generic ports.

In addition to these pin connections, power and ground connections will normally also be

necessary.

Rev. 6.0, 09/02, page 516 of 876

H8/3048 Series

Chip

Card-processing device

Smart card

TxD

RxD

SCK

Px (port)

I/O

CLK

RST

Data line

Clock line

Reset line

Figure 14.2 Smart Card Interface Connection Diagram

Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a

smart card.

Rev. 6.0, 09/02, page 517 of 876

14.3.3 Data Format

Figure 14.3 shows the data format of the smart card interface. In receive mode, parity is checked

once per frame . If a parity error is detected, an error signal is return ed to the transmitting device to

request r etransmission. I n transmit mode, the error signal is sampled and the same data is

retransmitted if the error sign al is low.

Parity error

D0 D1 D2 D3

Output from transmitting device

Output from

receiving device

D4 D5 D6 D7 Dp DE

No parity error

D0 D1 D2 D3

Output from transmitting device

D4 D5 D6 D7 Dp

Ds:

D0 to D7:

Dp:

DE:

Start bit

Data bits

Parity bit

Error signal

Figure 14.3 Smart Card Interface Data Format

The operating sequence is as follows.

1. When not in use, the data line is in the high-impedance state, and is pulled up to the high level

through a resistor.

2. To start tr ansmitting a fram e of data, th e transmitting device tr ansmits a low start bit (Ds) ,

followed by eig ht data bits (D0 to D7) and a parity bit (Dp).

3. Next, in the smart card interface, the transmitting device returns the data line to the high-

impedance state. The data line is pulled up to the high level through a resistor.

4. The receiving device perfor ms a parity check. If there is no parity error, the receiving device

waits to receive the next data. If a parity error is present, the receiving device outputs a low

error signal (DE) to request retransmission of the data. After outputting the error signal for a

designated interval, the receiving device returns the signal line to the high-impedance state.

The signal lin e is pulled back up to the high level th r ough the pull-up resistor.

5. If the transmitting device does no t receiv e an error signal, it pro ceeds to transmit th e n ext data.

If it receives an error signal, it returns to step 2 and transmits the same data again.

Rev. 6.0, 09/02, page 518 of 876

14.3.4 Register Settings

Table 14.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or

1 should always be set to the indicated value. The settings of the other bits will be described in this

section.

Table 14.3 Register Settings in Smart Card Interface

SMR H'FFB0 GM 0 1 O/E 1 0 CKS1 CKS0

BRR H'FFB1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0

SCR H'FFB2 TIE RIE TE RE 0 0 CKE1*2CKE0

TDR H'FFB3 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0

SSR H'FFB4 TDRE RDRF ORER ERS PER TEND 0 0

RDR H'FFB5 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0

SCMR H'FFB6 — — — — SDIR SINV — SMIF

Notes: — Unused bit.

*1 Lower 16 bits of the address .

*2 When the GM of the SMR is set at 0, be sure the CKE1 bit is 0.

Serial Mode Register (SMR) Settings: In regular smart card interface mode, set the GM bit at 0.

In regular smart car d mo de, clear the GM bit to 0. In GSM mode, set the GM bit to 1. Clear the

O/E bit to 0 if the smart card uses the direct convention. Set the O/E bit to 1 if the smar t card uses

the inverse co nvention. Bits CKS1 and CKS0 select the clock source of the built-in baud r ate

generator. See section 14.3.5, Clock.

Bit Rate Register (BRR) Settings: This register sets the bit rate. Equations for calculating the

setting are given in section 14.3.5, Clock.

Serial Control Register (SCR): The TIE, RIE, TE, and RE bits have their normal serial

communication functions. For details, see section 13, Serial Co mmunication Interface. The CKE1

and CKE0 bits select clock outpu t. When the GM bit of the SMR is cleared to 0, to disable clock

output, clear this bit to 00. To enable clock output, set this bit to 01. When the GM bit of the SMR

is set to 1, clock output is enabled. Clock output is fixed at high or low.

Smart Card Mode Register (SCMR): If the smart card follows the direct convention, clear the

SDIR and SINV bits to 0. If the smart card follows the indirect convention, set the SDIR and

SINV bits to 1. To use the smart card interface, set the SMIF bit to 1.

Rev. 6.0, 09/02, page 519 of 876

The register settings and examples of starting character waveforms are shown below for two smart

cards, one follo wing the direct convention and one the inverse convention.

• Direct convention (SDIR = SINV = O/E = 0)

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

AZZAZZZAAZ(Z) (Z) State

In the direct convention, state Z corresponds to logic level 1, and state A to logic level 0.

Characters are transmitted and received LSB-first. In the example above the first character data

is H'3B. The parity bit is 1, following th e even parity rule designated for sm ar t cards.

• Inverse convention (SDIR = SINV = O/E = 1)

Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp

AZZAAAAAAZ(Z) (Z) State

In the inverse convention, state A corresponds to the logic level 1, and state Z to the logic level

0. Characters are transmitted and received MSB-first. In th e ex ample above th e first character

data is H'3F. Following the even parity rule d e signated for smart cards, the parity bit logic

level is 0, corresponding to state Z.

In the H8/304 8 Series, th e SI NV bit inverts only the d ata bits D7 to D0. The parity bit is not

inverted, so the O/E bit in SMR must be set to o dd parity mode. This applies in both transmitting

and receiving.

Rev. 6.0, 09/02, page 520 of 876

14.3.5 Clock

As its serial communication clock, the sm art card interface can use only the internal clock

generated by the on-chip baud rate generator. The bit rate can be selected by setting the bit rate

calculated from the equation given below. Table 14 .5 lists some examples of bit rate settings.

If bit CKE0 is set to 1, a clock signal with a frequency equal to 372 times the bit rate is output

from the SCK0 pin.

B = 1488 × 22n–1 × (N + 1) × 106

where, N: BRR setting (0 ≤ N ≤ 255)

B: Bit rate (bits/s)

φ: System clock frequency (MHz)*

n: See table 14.4

Table 14.4 n-Values of CKS1 and CK S0 Settings

n CKS1 CKS0

000

101

210

311

Note: * If the gear function is used to divide the system clock frequency, use the divided

frequency to calculate the bit rate. Th e equation above applies directly to 1/1 frequency

division.

Table 14.5 Bit Rates (bits/s) for Different BRR Settings (when n = 0)

φφ

φ (MHz)

N 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00

0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5

1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8

2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5

Note: Bit rates are rounded off to one decimal place.

Rev. 6.0, 09/02, page 521 of 876

The following eq uation calculates the bit r ate register (BRR) setting from th e syste m clock

frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.

N = 1488 × 2

2n–1

× B× 10

– 1

Table 14.6 BRR Settings for Typical Bit Rate (bits/s) (w hen n = 0)

φφ

φ (MHz)

7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00

Bit/s N Error N Error N Error N Error N Error N Error N Error

9600 0 0.00 1 30.00 1 25.00 1 8.99 1 0.00 1 12.01 2 15.99

Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface)

φφ

φ (MHz) Maximum Bit Rate (bits/s) N n

7.1424 9600 0 0

10.00 13441 0 0

10.7136 14400 0 0

13.00 17473 0 0

14.2848 19200 0 0

16.00 21505 0 0

18.00 24194 0 0

The bit rate error is calcu lated fro m the following equation.

Error (%) = 1488 × 22n–1 × B × (N + 1) × 106 – 1 × 100

Rev. 6.0, 09/02, page 522 of 876

14.3.6 Transmitting and Receiving Data

Initialization: Before transmitting or receiving data, initialize the smart card interface by the

procedure below. Initialization is also necessary when switchin g from transmit mode to receive

mode or from receive mode to transmit mode.

1. Clear the TE and RE bits to 0 in the serial control register (SCR).

2. Clear the ERS, PER, and ORER error flags to 0 in the serial status register (SSR).

3. Set the parity mode bit (O/E) and baud rate generator clock source select bits (CKS1 and

CKS0) as required in the serial mode register (SMR). At the same time, clear the C/A, CHR,

and MP bits to 0, and set the STOP and PE bits to 1.

4. Set the SMIF, SDIR, and SINV bits as required in the smart card mode register (SMR). When

the SMIF bit is set to 1, the TxD0 and RxD0 pins switch from their I/O port functions to their

serial communication interface functions, and are placed in the high-impedance state.

5. Set a value corresponding to the desired bit rate in the bit rate register (BRR).

6. Set clock enable bit 0 (CKE0) as required in the serial control register (SCR). Write 0 in the

TIE, RIE, TE, RE, MPIE, TEIE, and CKE1 bits. If bit CKE0 is set to 1, a serial clock will be

output from the SCK0 pin.

7. Wait for at least the interval required to transmit or receive one bit, then set the TIE, RIE, TE,

and RE bits as necessary in SCR. Do not set TE and RE both to 1, except when performing a

loop-back test.

Transmitting Serial Data: The transmitting p roced ure in smart card mode is different from the

normal SCI procedure, because of the need to sample th e error signal and retransmit. Figure 14.4

shows a flowchart for transmittin g, and figure 14.5 shows th e relation between a transm it

operation and the internal registers.

1. Initialize the sm art card interface by the procedure given abo ve in Initializatio n.

2. Check that the ERS error flag is cleared to 0 in SSR.

3. Check th at the TEND flag is set to 1 in SSR. Repeat steps 2 and 3 until this check passes.

4. Write transmit data in TDR and clear th e TDRE flag to 0. The data will be transm itted and the

TEND flag will be cleared to 0.

5. To con tinue tr ansmitting data, return to step 2.

6. To terminate transmission, clear the TE bit to 0.

This procedure may include interrupt hand ling and DMA transfer.

If the TIE bit is set to 1 to enable interrupt requests, when transmission is com pleted and the

TEND flag is set to 1, a tr ansmit-data-empty interrupt (TXI) is requested. If the RIE b it is set to 1

to enable inter rup t requ ests, when a transmit error occurs and the ERS f lag is set to 1, a

transmit/receive-error interrupt (ERI) is requested.

Rev. 6.0, 09/02, page 523 of 876

The timing of TEND flag setting depends on the GM bit in SMR. The timing is shown in figure

14.6.

If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be

transmitted au tomatically, includ ing automatic retransmit.

For details, see In ter r upt Operations and Data Transfer by DMAC in this section.

FER/ERS = 0 ?

TEND = 1 ?

FER/ERS = 0 ?

TEND = 1 ?

All data

transmitted ?

Initialize

Write data in TDR and clear

TDRE flag to 0 in SSR

Clear TE bit to 0

Start

Error handling

Start transmitting

End

Yes

Figure 14.4 Transmit Flowchart (Example)

Rev. 6.0, 09/02, page 524 of 876

TDR TSR

(shift register)

(1) Data write

(2) Transfer from

TDR to TSR

(3) Serial data output

Data 1

Data 1 ; Data remains in TDR

I/O signal line output

In case of normal transmission: TEND flag is set

In case of transmit error: ERS flag is set

Steps (2) and (3) above are repeated until the TEND flag is set

Data 1

Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first

transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has

been completed.

Figure 14.5 Relation Between Transmit Operation and Internal Registers

I/O data

Guard

time

When GM = 1

When GM = 0

TXI

(TEND interrupt)

DS Da Db Dc Dd De

12.5 etu

11.0 etu

Df Dg Dh Dp DE

Figure 14.6 TEND Flag Occurrence Timing

Rev. 6.0, 09/02, page 525 of 876

Receiving Serial Data: The receiving procedure in smart card mode is the same as the normal

SCI procedure. Figure 14.7 shows a flowchart for receiving.

1. Initialize the smart card interface by the procedure given in Initialization at the beginning of

this section.

2. Check that the ORER and PER error flags are cleared to 0 in SSR. If either flag is set, carry out

the necessary error handling, then clear both the ORER and PER flags to 0.

3. Check that the RDRF flag is set to 1. Repeat steps 2 and 3 until this check passes.

4. Read receive data from RDR.

5. To continue receiving data, clear the RDRF flag to 0 and return to step 2.

6. To terminate receiving, clear the RE bit to 0.

ORER = 0 and

PER = 0 ?

RDRF = 1 ?

All data received ?

Initialize

Read RDR and clear RDRF

flag to 0 in SSR

Clear RE bit to 0

Start

Error handling

Start receiving

Yes

Figure 14.7 Receive Flowchart (Example)

Rev. 6.0, 09/02, page 526 of 876

This procedure may include interrupt hand ling and DMA transfer.

If the RIE bit is set to 1 to enable interrupt requests, when receiving is completed and the RDRF

flag is set to 1, a receive-data-full interrupt (RXI) is requested. If a receive error occurs, either the

ORER or PER flag is set to 1 and a transmit/receive-error interrupt (ERI) is requ ested.

If the RXI inter rupt activates the DMAC, the num ber of bytes designated in the DMAC will b e

transferred, skipping receive data in which an error occurred.

For details, see Interrupt Operations and Data Transfer by DMAC below.

When a parity error occurs and PER is set to 1, the receive data is transferred to RDR, so the

erroneous data can be read.

Switching Modes: To switch from receive mode to transmit mode, check that receiving

operations have completed, then initialize the smart card interface, clearing RE to 0 and setting TE

to 1. Completion of receive operations is indicated by the RDRF, PER, or ORER flag.

To switch from transmit mode to receive mode, check that transmitting operations have

completed, then initialize the smart card interface, clearing TE to 0 and setting RE to 1.

Completion of transmit operations can be verified from th e TEND flag.

Fixing Clo c k Output: When the GM bit of the SMR is set to 1, clock output is fixed by CKE1

and CKE0 of SCR. In this case, the clock pulse can be set at minimum value.

Figure 14.8 shows clock output fixed timing: CKE0 is restricted with GM = 1 and CKE1 = 1.

SCR write

(CKE0 = 1)

SCR write

(CKE0 = 0)

SCK

Specified pulse width Specified pulse width

CKE1 value

Figure 14.8 Clock Output Fixed Timing

Rev. 6.0, 09/02, page 527 of 876

Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty

(TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt

request (TEI) is not available in smart card mode.

A TXI interrup t is r eque sted when the TEND flag is set to 1 in SSR. An RXI in ter r upt is requested

when the RDRF flag is set to 1 in SSR. An ERI interrupt is requested when the ORER, PER, or

ERS flag is set to 1 in SSR. These relationships are shown in table 14.8.

Table 14.8 Smart Card Mode Operat ing States and Interrupt Sources

Operating State Flag Mask Bit Interrupt

Source DMAC

Activation

Transmit mode Normal operation TEND TIE TXI Available

Error ERS RIE ERI No t available

Receive mode Normal operation RDRF RIE RXI Available

Error PER, ORER RIE ERI Not available

Data Transfer by DMAC: The DMAC can be used to transmit and receive in smart card mode,

as in norm al SCI operations. In transmit m ode, when the TEND flag is set to 1 in SSR, the TDRE

flag is set simultaneously, generating a TXI interrupt. If TXI is designated in advance as a DMAC

activation sou rce, the DMAC will be activated by the TXI req uest and will transfer the next

transmit data. Th is data transfer by the DMAC autom atically clears the TDRE and TEND flag s to

0. When an error occurs, the SCI automatically retransm its the same data, keeping TEND cleared

to 0 so that the DMAC is not activated. The SCI and DMAC will therefore automatically transmit

the designated number of bytes, including retransmission when an error occurs. When an error

occurs the ERS flag is not cleared automatically, so the RIE bit should be set to 1 to enable the

error to gene r a te an ERI r equest, and the ERI interrupt handler sh ould clear ERS.

When using the DMAC to transmit or receive, first set up and enable the DMAC, then make SCI

settings. DMAC settings are described in section 8, DMA Controller.

In receive operations, when the RDRF flag is set to 1 in SSR, an RXI interrupt is requested. If RXI

is designated in advance as a DMAC activation source, the DMAC will be activated by th e RXI

request and will transfer the received data. This data transfer by th e DMAC automatically clears

the RDRF flag to 0. When an error occurs, the RDRF flag is not set and an error flag is set instead.

The DMAC is not activated. The ERI interrupt request is directed to the CPU. The ERI interrupt

handler should clear the error flags.

Examples of Operation in GSM Mode: When switching between smart card interface mode and

software standby mode, use the following procedures to maintain the clock duty cycle.

• Switching from smart card interface mode to software standby mode

1. Set the P94 data register (DR) and data direction register (DDR) to the values for the fixed

output state in software standby mode.

Rev. 6.0, 09/02, page 528 of 876

2. Write 0 to the TE and RE b its in the serial control register (SCR) to stop tran smit/receive

operations. At the same time, set the CKE1 bit to the value for the fixed output state in

software standby mode.

3. Write 0 to the CKE0 bit in SCR to stop the clock.

4. Wait for one serial clock cy cle. During this period, the duty cycle is preserved and clock

output is fixed at the specified level.

5. Write H'00 to the serial mode register (SMR) and smart card mode register (SCMR).

6. Make the transition to the software standby state.

• Returning from so ftware standby mode to smart card interface mode

1. Clear the software standby state.

2. Set the CKE1 bit in SCR to the valu e for the fixed output state at the start of software

standby (the current P94 pin state).

3. Set smart card interface mode and output the clock. Clock signal generation is started with

the normal duty cycle.

(1)(2)(3) (1) (2)(3)(4) (5)(6)

Normal operation Normal operation

Software standby

mode

Figure 14.9 Procedure f or Stopping and Restarting t he Clock

Use the following procedure to secure the clock duty cycle after powering on.

1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the

potential.

2. Fix at the output specified by the CKE1 bit in SCR.

3. Set SMR and SCMR, and switch to smart card interface mode operation.

4. Set the CKE0 bit in SCR to 1 to star t clock output.

14.4 Usage Notes

When using the SCI as a smart card interface, note the following points.

Receive Data Sampling Timing in Smart Card Mode and Receive Margin: In smart card

mode the SCI operates on a base clock with 372 times the bit rate frequency. In receiving, the SCI

Rev. 6.0, 09/02, page 529 of 876

synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive

data is latched at the rising edge of the 186th base clock pulse. See figure 14.10.

372 clocks

186 clocks

185 185

Internal

base clock

Receive data

(RxD)

Synchronization

sampling timing

Data sampling

timing

D1D0

37137100

Start

bit

Figure 14.10 Receive Data Sampling Timing in Smart Card Mode

The receive margin can therefore be expressed as follows.

Receive margin in smart card mode:

M = 0.5 – 1

2N D – 0.5

– (L – 0.5) F – (1 + F) × 100%

M: Receive margin (%)

N: Ratio of clock frequency to bit rate (N = 372)

D: Clock duty cycle (D = 0 to 1.0)

L: Frame length (L = 10)

F: Absolute deviation of clo ck frequ enc y

From this equation, if F = 0 and D = 0.5 the receive margin is as follows.

D = 0.5, F = 0

M = {0.5 – 1/(2 × 372)} × 100%

= 49.866%

Rev. 6.0, 09/02, page 530 of 876

Retransmission: Retransmission is described below for the separate cases of transmit mode and

receive mode.

• Retransmission when SCI is in Receive Mode (see figure 14.11)

(1) The SCI checks the received parity bit. If it detects an error, it automatically sets the PER flag

to 1. If the RIE b it in SCR is set to the enable state, an ERI interrupt is requested . The PER

flag should be cleared to 0 in SSR before the next parity bit sampling timing.

(2) The RDRF bit in SSR is not set to 1 for the error frame.

(3) If an error is not detected wh en the parity bit is checked, the PER flag is not set in SSR.

(4) If an error is not detected when the parity bit is checked, receiving operations are assumed to

have ended normally, and the RDRF bit is autom a tically set to 1 in SSR. If the RIE bit in SCR

is set to the enable state, an RXI interrupt is requested. If RXI is enabled as a DMA transfer

activation source, the RDR contents can be read automatically. When the DMAC reads the

RDR data, it autom a tically clears RDRF to 0 .

(5) When a normal frame is received, at the error signal transmit timing, the data pin is held in the

high-impedance state.

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds

(DE) D0 D1 D2 D3 D4

Frame n

RDRF

(2) (4)

(1) (3)

PER

Retransmitted frame Frame n + 1

Figure 14.11 Retransmission in SCI Receive Mode

Rev. 6.0, 09/02, page 531 of 876

• Retransmission when SCI is in Transmit Mode (see figure 14.12)

(6) After transmitting one frame, if the receiving device returns an error signal, the SCI sets the

ERS flag to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is

requested. The ERS flag should be cleared to 0 in SSR before the next parity bit sampling

timing.

(7) The TEND bit in SSR is not set for the frame in which the error signal was received, indicating

an error.

(8) If no error signal is returned from the receiving device, the ERS flag is not set in SSR.

(9) If no error signal is returned from the receiving device, transmission of the frame, including

retransmissio n, is assumed to b e complete, and the TEND bit is set to 1 in SSR. I f the TIE bit

in SCR is set to the enable state, a TXI interrupt is req uested. If TXI is enabled as a DMA

transfer activation source, the next data can be written in TDR automatically. When the

DMAC writes data in TDR, it automatically clears the TDRE bit to 0.

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds

(DE) D0 D1 D2 D3 D4

Frame n

(9)

(7)

Transfer from

TDR to TSR

Transfer from TDR to TSRTransfer from TDR to TSR

TDRE

TEND

ERS

(6) (8)

Retransmitted frame Frame n + 1

Figure 14.12 Retransmission in SCI Transmit Mode

Rev. 6.0, 09/02, page 532 of 876

Rev. 6.0, 09/02, page 533 of 876

Section 15 A/D Converter

15.1 Overview

The H8/3048 Series includes a 10-bit successive-approximations A/D converter with a selection of

up to eight analog input channels.

When the A/D converter is not used, it can be halted independently to conserve power. For details

see section 21.6, Module Standby Function.

15.1.1 Features

A/D converter features are listed below.

• 10-b it resolution

• Eight input channels

• Selectable analog conversion voltage range

The analog voltage conversion range can be programmed by input of an analog reference

voltage at the VREF pin.

• High-speed conversion

Conversion time: Minimum 7.45 µs per channel (with 18 MHz system clock)

• Two conversion modes

Single mode: A/D conversion of on e channel

Scan mode: continuous conversion on one to four channels

• Four 16-bit data registers

A/D conversion results are transferred for storage into data registers corresponding to the

channels.

• Sample-and -hold function

• A/D conversion can be externally triggered

• A/D interrupt requested at end of conversion

At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.

Rev. 6.0, 09/02, page 534 of 876

15.1.2 Block Diagram

Figure 15.1 shows a block diagram of the A/D converter.

Module data bus

Bus interface

Internal

data bus

ADDRA

ADDRB

ADDRC

ADDRD

ADCSR

ADCR

Successive-

approximations register

10-bit D/A

REF

Analog

multi-

plexer

Sample-and-

hold circuit

Comparator

–

Control circuit

φ/8

φ/16

ADI

Legend

ADCR:

ADCSR:

ADDRA:

ADDRB:

ADDRC:

ADDRD:

A/D control register

A/D control/status register

A/D data register A

A/D data register B

A/D data register C

A/D data register D

Figure 15.1 A/D Converter Block Diagram

Rev. 6.0, 09/02, page 535 of 876

15.1.3 Input Pins

Table 15.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided

into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power

supply for the analog circuits in the A/D converter. VREF is the A/D conversion reference voltage.

Table 15.1 A/D Converter Pins

Pin Name Abbre-

viation I/O Function

Analog power supply pin AVCC Input Analog power supply

Analog ground pin AVSS Input Analog ground and reference voltage

Reference volt age pin VREF Input Analog reference voltage

Analog input pin 0 AN0Input Group 0 analog inputs

Analog input pin 1 AN1Input

Analog input pin 2 AN2Input

Analog input pin 3 AN3Input

Analog input pin 4 AN4Input Group 1 analog inputs

Analog input pin 5 AN5Input

Analog input pin 6 AN6Input

Analog input pin 7 AN7Input

A/D external trigger input pin ADTRG Input External trigger input for starting A/D

conversion

Rev. 6.0, 09/02, page 536 of 876

15.1.4 Register Configuration

Table 15.2 summarizes the A/D conv erter’s registers.

Table 15.2 A/D Converter Registers

Address*1Name Abbreviation R/W Initial Value

H'FFE0 A/D data register A (high) ADDRAH R H'00

H'FFE1 A/D data register A (low) ADDRAL R H'00

H'FFE2 A/D data register B (high) ADDRBH R H'00

H'FFE3 A/D data register B (low) ADDRBL R H'00

H'FFE4 A/D data register C (high) ADDRCH R H'00

H'FFE5 A/D data register C (low) ADDRCL R H'00

H'FFE6 A/D data register D (high) ADDRDH R H'00

H'FFE7 A/D data register D (low) ADDRDL R H'00

H'FFE8 A/D control/status register ADCSR R/(W)*2H'00

H'FFE9 A/D control register ADCR R/W H'7F*3

Notes: *1 Lower 16 bits of the address

*2 Only 0 can be written in bit 7, to clear the flag.

*3 H8/3048F, H8/3048ZTAT, H8/3048 mask-ROM, H8/3047 mask-ROM, H8/3045 mask-

ROM, and H8/3044 mask-ROM versions

Rev. 6.0, 09/02, page 537 of 876

15.2 Register Descriptions

15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)

Bit

ADDRn

Initial value

AD8

AD6

AD4

AD2

AD0

—

AD9

AD7

AD5

AD3

AD1

—

A/D conversion data

10-bit data giving an

A/D conversion result

Reserved bits

Read/Write

(n = A to D)

The four A/D data registers (ADDRA to ADDRD) are 16-b it read-on ly registers that store the

results of A/D conversion.

An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data

byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D

data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of analog

input channels and A/D data registers.

The CPU can always read and write the A/D data registers. The upper byte can be read directly,

but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU

Interface.

The A/D data register s ar e initialized to H'0000 by a reset and in standby mode.

Table 15.3 Analog Input Channe ls and A/D Data Regist ers

Analog Input Channel

Group 0 Group 1 A/D Data Register

AN0AN4ADDRA

AN1AN5ADDRB

AN2AN6ADDRC

AN3AN7ADDRD

Rev. 6.0, 09/02, page 538 of 876

15.2.2 A/D Control/Status Register (ADCSR)

Bit

Initial value

Read/Write

ADF

R/(W)

ADIE

R/W

ADST

R/W

SCAN

R/W

CKS

R/W

CH0

R/W

CH2

R/W

CH1

R/W

Note: Only 0 can be written, to clear the flag.*

A/D end flag

Indicates end of A/D conversion

A/D interrupt enable

Enables and disables A/D end interrupts

A/D start

Starts or stops A/D conversion

Scan mode

Selects single mode or scan mode

Clock select

Selects the A/D conversion time

Channel select 2 to 0

These bits select analog

input channels

ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.

ADCSR is initialized to H'00 by a reset and in standby mode.

Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.

Bit 7: ADF Description

0 [Clearing cond iti on] (Initial value)

Cleared by reading ADF while ADF = 1, then writing 0 in ADF

1 [Setting conditions]

Single mode: A/D conversion ends

Scan mode: A/D conversi on ends in all selected channels

Rev. 6.0, 09/02, page 539 of 876

Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the

end of A/D conversion.

Bit 6: ADIE Description

0 A/D end interrupt request (ADI) is di sabl ed (Initial value)

1 A/D end interrupt request (ADI) is enabled

Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during

A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.

Bit 5: ADST Description

0 A/D conversion is stopped (Initial value)

1 Single mode: A/D conversion starts; ADST is automa tically cleared to 0 when

conversion ends.

Scan mode: A/D conversion starts and continues, cycling among the selected

channels, until ADST is cleared to 0 by software, by a reset, or by a transition

to standby mode.

Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on

operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching

the conversion mode.

Bit 4: SCAN Description

0 Single mode (Initial value)

1 Scan mode

Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before

switching the conversion time.

Bit 3: CKS Description

0 Conversion time = 266 states (maximum) (Initial value)

1 Conversion time = 134 states (maximum)

Rev. 6.0, 09/02, page 540 of 876

Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and th e SCAN bit select the analog

input channels. Clear the ADST bit to 0 before changing the channel selection.

Group

Selection Channel Selection Description

CH2 CH1 CH0 Single Mode Scan Mode

000AN

0 (Initial value) AN0

1AN

1AN0, AN1

10 AN

2AN0 to AN2

1AN

3AN0 to AN3

100AN

4AN4

1AN

5AN4, AN5

10 AN

6AN4 to AN6

1AN

7AN4 to AN7

15.2.3 A/D Control Register (ADCR)

Bit

Initial value

Read/Write

TRGE

R/W

—

Trigger enable

Enables or disables external triggering of A/D conversion

Reserved bits

ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D

conversion. ADCR is initialized to H'7F by a reset and in standby mode.

Bit 7—Trigger Ena ble (TRGE): Enables or disables external triggering of A/D conversion.

Bit 7: TRGE Description

0 A/D conversion cannot be externally triggered (Initial value)

1 A/D conversion starts at the falling edge of the external trigger signal (ADTRG)

Bits 6 to 0—Reserved: Read-only bits, always read as 1.

Rev. 6.0, 09/02, page 541 of 876

15.3 CPU Interface

ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.

Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read

through an 8-bit temporary register (TEMP).

An A/D data register is read as follows. When the upper byte is read, the upper-byte value is

transferred directly to the CPU and the lower-byte valu e is transferred into TEMP. Next, when the

lower byte is read, the TEMP conten ts are transferred to the CPU.

When reading an A/D data register, always read the upper byte before the lower byte. It is possible

to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.

Figure 15.2 shows the data flow for access to an A/D data register.

Upper-byte read

Bus interface Module data bus

CPU

(H'AA)

ADDRnH

(H'AA) ADDRnL

(H'40)

Lower-byte read

Bus interface Module data bus

CPU

(H'40)

ADDRnH

(H'AA) ADDRnL

(H'40)

TEMP

(H'40)

TEMP

(H'40)

(n = A to D)

Figure 15.2 A/D Data Register Access Operation (Reading H'AA40)

Rev. 6.0, 09/02, page 542 of 876

15.4 Operation

The A/D converter operates by successive approximations with 10-bit resolution. It has two

operating modes: single mode and scan mode.

15.4.1 Single Mode (SCAN = 0)

Single mode should be selected when only one A/D conversion on one channel is required. A/D

conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The

ADST bit remains set to 1 during A/D conversio n and is automatically cleared to 0 when

conversion ends.

When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is

requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.

When the mode or analog input channel must be switched during analog conversion, to prevent

incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making

the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be

set at the same time as the mode or channel is changed.

Typical operations when channel 1 (AN1) is selected in single mode are described next.

Figure 15.3 shows a timing diagram for this example.

1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0,

CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).

2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time

the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.

3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.

4. The A/D inter r upt handling routine starts.

5. The routine reads ADCSR, then writes 0 in the ADF flag.

6. The routine reads and processes the conversion result (ADDRB).

7. Executio n of the A/D interrupt handling rou tine ends. After that, if the ADST bit is set to 1,

A/D conversion starts again and steps 2 to 7 are repeated.

Rev. 6.0, 09/02, page 543 of 876

ADIE

ADST

ADF

State of channel 0

(AN )

Set

Set Set

Clear Clear

Idle

A/D conversion (1)

A/D conversion (2)

Idle

Read conversion result

A/D conversion result (1) Read conversion result

A/D conversion result (2)

Note: Vertical arrows ( ) indicate instructions executed by software.

A/D conversion

starts

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 1

(AN )

State of channel 2

(AN )

State of channel 3

(AN )

Idle

Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)

Rev. 6.0, 09/02, page 544 of 876

15.4.2 Scan Mode (SCAN = 1)

Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the

ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first

channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are

selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5)

starts immediately. A/D conversion continues cyclically on the selected channels until the ADST

bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers

corresponding to the channels.

When the mode or analog input channel selection must be changed during analog conversion, to

prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After

making th e necessary changes, set the ADST bit to 1. A/D co nver sion will start again from the

first channel in the group. The ADST bit can be set at the same time as the mo de or channel

selection is changed.

Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are

described next. Figure 15.4 shows a timing diagram for this example.

1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels

AN0 to AN2 are selected (CH1 = 1, CH0 = 0) , and A/D conversion is started (ADST = 1).

2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into

ADDRA. Next, conversion of the second channel (AN1) starts automatically.

3. Conversion proceeds in the same way through the third channel (AN2).

4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF f lag is set to 1

and conversion of the first channel (AN0) star ts ag ain. If the ADIE bit is set to 1, an ADI

interrup t is r equested at this time.

5. Steps 2 to 4 are repeated as long as the ADST bit r e m a ins set to 1. When the ADST bit is

cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion

starts again from the first channel (AN0).

Rev. 6.0, 09/02, page 545 of 876

ADST

ADF

State of channel 0

(AN )

Continuous A/D conversion

Set Clear*1

Clear*1

Idle

A/D conversion (1)

Idle

A/D conversion (4) Idle

A/D conversion (2)

Idle

A/D conversion (5)

Idle

A/D conversion (3)

Idle

Transfer A/D conversion result (1) A/D conversion result (4)

A/D conversion result (2)

A/D conversion result (3)

A/D conversion time

Notes:

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 1

(AN )

State of channel 2

(AN )

State of channel 3

(AN )

Vertical arrows ( ) indicate instructions executed by software.

Data currently being converted is ignored.

Figure 15.4 Example of A/D Converter Operation

(Scan Mode, Channels AN0 to AN2 Selected)

Rev. 6.0, 09/02, page 546 of 876

15.4.3 Input Sam pling and A/D Conv ersion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D

conversion timing. Table 15.4 indicates the A/D conversion tim e.

As indicated in figure 15.5, the A/D conversion time includes tD and the input sampling tim e. The

length of tD varies depending on th e timing of the write access to ADCSR. The total conversion

time therefore varies within the ranges indicated in table 15.4.

In scan mode, the values given in table 15 .4 apply to the first conversion. In the second and

subsequent conv ersions the conversion time is fixed at 256 states when CKS = 0 or 128 states

when CKS = 1.

Address bus

Write signal

Input sampling

timing

ADF

(1)

(2)

SPL

CONV

Legend

(1):

(2):

t :

SPL

CONV

ADCSR write cycle

ADCSR address

Synchronization delay

Input sampling time

A/D conversion time

Figure 15.5 A/D Conversion Timing

Rev. 6.0, 09/02, page 547 of 876

Table 15.4 A/D Conversion Time (Sing le Mode)

CKS = 0 CKS = 1

Symbol Min Typ Max Min Typ Max

Synchronization delay tD10 — 17 6 — 9

Input sampling tim e tSPL —63— —31—

A/D conversion time tCONV 259 — 266 131 — 134

Note: Values in the table are numbers of states.

15.4.4 External Trigger Input Timing

A/D conversion can be externally triggered. Wh en the TRGE bit is set to 1 in ADCR, external

trigger in put is en abled at the ADTRG pin. A high-to-low tran sition at the ADTRG pin sets the

ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan

modes, are the same as if the ADST bit had been set to 1 by software. Figure 15.6 shows the

timing.

Internal trigger

signal

ADST

A/D conversion

Figure 15.6 External Trigger Input Timing

Rev. 6.0, 09/02, page 548 of 876

15.5 Interrupts

The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt

request can be enabled or disabled by the ADIE bit in ADCSR.

15.6 Usage Notes

When using the A/D converter, note the following points:

1. Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input

pins should be in the range AVSS ≤ ANn ≤ VREF.

2. Relationships of AVCC and AVSS to VCC and VSS: AVCC, AVSS, VCC, and VSS should be related as

follows: AVSS = VSS. AVCC and AVSS must not be left open, even if the A/D converter is not

used.

3. VREF Programming Range: The reference voltage input at the VREF pin should be in the range

VREF ≤ AVCC.

4. Analog Voltage: When using an A/D converter, make the following voltage settings.

a. VCC ≥ AVCC – 0.3V

b. AVCC ≥ VREF ≥ ANn ≥ AVSS = VSS

(N = 0 to 7)

Note: Restriction for the ZTAT version only; The S-mask version of ZTAT, the Flash

Memory version and Mask ROM version can be used regularly without restriction.

Failure to ob serv e points 1, 2, 3, and 4 above may degrade chip reliability.

5. Note on Board Design: In board layout, separate the digital circuits from the analog circuits as

much as possible. Particularly avoid layouts in which the signal lines of digital circuits cross or

closely approach the signal lines of analog circuits. Induction and other effects may cause the

analog circuits to operate incorrectly, or may adversely affect the accuracy of A/D conversion.

The analog input signals (AN0 to AN7), analog reference voltage (VREF), and analog supply

voltage (AVCC) must be separated from digital circuits by the analog ground (AVSS). The

analog ground (AVSS) should be connected to a stable digital ground (VSS) at one point on the

board.

Rev. 6.0, 09/02, page 549 of 876

6. Note on Noise: To prevent damage from surges and other abnormal voltages at the analog

input pins (AN0 to AN7) and analog reference voltage pin (VREF), connect a protection circuit

like the one in figure 15.7 between AVCC and AVSS. The bypass capacitors connected to AVCC

and VREF and the filter capacitors connected to AN0 to AN7 must be conn ected to AVSS. If filter

capacitors like the ones in figure 15.7 are connected, the voltage values input to the analog

input pins (AN0 to AN7) will be smoothed, which may give rise to error. Error can also occur if

A/D conversion is frequently performed in scan mode so that the current that charges and

discharges the capacitor in the sample-and-hold circuit of the A/D converter becomes greater

than that input to the analog input pins via input impedance Rin. The circuit constants should

therefore be selected carefully.

*1*1

REF

to AN

Notes: *1 Numeric values are approximate.

*2 Rin: input impedance

Rin

100 Ω

0.1 µF

0.01 µF10 µF

Figure 15.7 Example o f Analog Input Pro t ection Circuit

Rev. 6.0, 09/02, page 550 of 876

20 pF

To A/D converterAN0 to AN7

10 kΩ

Note: Numeric values are approximate.

Figure 15.8 Analog Input Pin Equivalent Circuit

Table 15. 5 Analog Input Pin Rat ings

Item Min Max Unit

Analog input capacitance — 20 pF

Allowable sig nal- source impedance — 10*kΩ

Note: *When VCC = 4.0 V to 5.5 V and φ ≤ 12 MHz.

7. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3048 Series is

defined as follows:

• Resolution

Digital output code length of A/D converter

• Offset error

Deviation from ideal A/D conversion characteristic of analog input voltage required to

raise digital output from minimum voltage valu e B'0000000000 to B'0000000001 (figure

15.10)

• Full-scale error

Deviation from ideal A/D conversion characteristic of analog input voltage required to

raise digital output from B'1111111110 to B'1111111111 (figure 15.10)

• Quantization error

Intrinsic error of the A/D converter; 1/2 LSB (figure 15.9)

• Nonlinearity error

Deviation from ideal A/D conversion characteristic in range from zero volts to full scale,

exclusive of offset error, full-scale error, and quantization error.

• Absolute accuracy

Deviation of digital value from analog input value, including offset error, full-scale error,

quantization error, and nonlinearity error.

Rev. 6.0, 09/02, page 551 of 876

111

110

101

100

011

010

001

000 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS

Quantization error

Analog input

voltage

Digital

output

Ideal A/D conversion

characteristic

Figure 15.9 A/D Converter Accuracy Definitions (1)

Rev. 6.0, 09/02, page 552 of 876

Offset error

Nonlinearity

error

Actual A/D conversion

characteristic

Analog input

voltage

Digital

output

Ideal A/D

conversion

characteristic

Full-scale

error

Figure 15.10 A/D Converter Accuracy Definitions (2)

8. Allowable Signal-Source Impedance: The analog inputs of the H8/3048 Series are designed to

assure accurate conversion of input signals with a signal-source impedance not exceeding 10

kΩ. The reason for th is rating is that it enables the input capacitor in the sample-and-hold

circuit in the A/D co nver ter to charge within the samplin g time. If the sensor output impedan ce

exceeds 10 kΩ, charging may be inadequate and the accuracy of A/D conversion cannot be

guaranteed.

If a large external capacitor is provided in scan mode, then the internal 10-kΩ input resistance

becomes the only significant load on the input. In th is case the impedance of the signal source

is not a prob lem.

A large extern al capacitor , however, acts as a low-pass filter. This may make it impossible to

track analog signals with high dv/dt (e.g. a variation of 5 mV/µs) (figure 15.11). To convert

high-speed analog signals or to use scan mode, insert a low-impedance buffer.

Rev. 6.0, 09/02, page 553 of 876

9. Effect on Absolute Accuracy: Attaching an external capacitor creates a coupling with ground,

so if there is noise on the ground line, it may degrade absolute accuracy. The capacitor must be

connected to an electrically stable ground, such as AVSS.

If a filter circuit is used, be careful of interference with digital signals on the same board, and

make sure the circuit does not act as an antenna.

Equivalent circuit of

A/D converter

H8/3048 Series

20 pF

Cin =

15 pF

10 kΩ

Up to 10 kΩ

Low-pass

filter

Up to 0.1 µF

Sensor output impedance

Sensor

input

Figure 15.11 Analog Input Circuit (Example)

Rev. 6.0, 09/02, page 554 of 876

Rev. 6.0, 09/02, page 555 of 876

Section 16 D/A Converter

16.1 Overview

The H8/3048 Series includes a D/A converter with two channels.

16.1.1 Features

D/A converter features are listed below.

• Eight-bit resolution

• Two output channels

• Conversion time: maximum 10 µs (with 20-pF capacitive load)

• Output voltage: 0 V to 255/256 * VREF

• D/A outputs can be sustained in so ftware standby mode

Rev. 6.0, 09/02, page 556 of 876

16.1.2 Block Diagram

Figure 16.1 shows a block diagram of the D/A converter.

DADR0

DADR1

DACR

DASTCR

REF

Legend

DACR:

DADR0:

DADR1:

DASTCR:

8-bit D/A

Module data bus

Bus interface

Internal

data bus

Control circuit

D/A control register

D/A data register 0

D/A data register 1

D/A standby control register

Figure 16.1 D/A Converter Block Diagram

Rev. 6.0, 09/02, page 557 of 876

16.1 .3 Input/Output Pins

Table 16.1 summarizes the D/A converter’s input and output pins.

Table 16.1 D/A Converter Pins

Pin Name Abbreviation I/O Function

Analog power supply pin AVCC Input Analog power supply

Analog ground pin AVSS Input Analog ground and reference voltage

Analog output pin 0 DA0Output Analog output, channel 0

Analog output pin 1 DA1Output Analog output, channel 1

Reference volt age inp ut pin VREF Input Analog reference voltage

16.1.4 Register Configuration

Table 16.2 summarizes the D/A conv erter’s registers.

Table 16.2 D/A Converter Registers

Address*Name Abbreviation R/W Initial Value

H'FFDC D/A data register 0 DADR0 R/W H'00

H'FFDD D/A data register 1 DADR1 R/W H'00

H'FFDE D/A control register DACR R/W H'1F

H'FF5C D/A standby control register DASTCR R/W H'FE

Note: * Lower 16 bits of the address

Rev. 6.0, 09/02, page 558 of 876

16.2 Register Descriptions

16.2.1 D/A Data Registers 0 and 1 (DADR0 /1)

Bit

Initial value

Read/Write

R/W

The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the

data to be converted. When analog output is enabled, the D/A data register values are constantly

converted and output at the analog output pins.

The D/A data registers are initialized to H'00 by a reset and in standby mode.

16.2.2 D/A Control Register (DACR)

Bit

Initial value

Read/Write

DAOE1

R/W

DAOE0

R/W

DAE

R/W

—

D/A output enable 1

D/A output enable 0

D/A enable

Controls D/A conversion and analog output

Controls D/A conversion

DACR is an 8-b it readable/writable register that co ntrols the operation of the D/A conver ter .

DACR is initialized to H'1F by a reset and in standby mode.

Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.

Bit 7: DAOE1 Description

0DA

1 analog output is disabled (Initial value)

1 Channel-1 D/A conversion and DA1 analog output are enabled

Rev. 6.0, 09/02, page 559 of 876

Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.

Bit 6: DAOE0 Description

0DA

0 analog output is disabled (Initial value)

1 Channel-0 D/A conversion and DA0 analog output are enabled

Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1.

When the DAE bit is cleared to 0, analog conversion is controlled independently in channels 0 an d

1. When the DAE bit is set to 1, analog conversion is controlled together in channels 0 and 1.

Output of the conversion results is always controlled indepen dently by DAOE0 and DAOE1.

Bit 7:

DAOE1 Bit 6:

DAOE0 Bit 5:

DAE Description

0 0 — D/A conversion is disabled in channels 0 and 1

1 0 D/A conversion is enabled in channel 0

D/A conversion is disabled in channel 1

1 D/A conversion is enabled in channels 0 and 1

100D/A conversion is disabled in channel 0

D/A conversion is enabled in channel 1

1 D/A conversion is enabled in channels 0 and 1

1 — D/A conversion is enabled in channels 0 and 1

When the DAE bit is set to 1 , ev en if bits DAOE0 and DAOE1 in DACR and the ADST bit in

ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D

and D/A conversion.

Bits 4 to 0—Reserved: Read-only bits, always read as 1.

Rev. 6.0, 09/02, page 560 of 876

16.2.3 D/A Standby Control Register (DASTCR)

DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software

standby mode.

Bit

Initial value

Read/Write

—

DASTE

R/W

—

Reserved bits D/A standby enable

Enables or disables D/A output

in software standby mode

DASTCR is initia lized to H'FE by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 1—Reserved: Read-only bits, always read as 1.

Bit 0—D/A Sta ndby Enable (DASTE): Enables or disables D/A output in software standby

mode.

Bit 0: DASTE Description

0 D/A output is disabled in software standby mode (Initial value)

1 D/A output is enabled in software standby mode

Rev. 6.0, 09/02, page 561 of 876

16.3 Operation

The D/A converter has two built-in D/A conversion circuits that can perform conversion

independently.

D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value

is modified, conversion of the new data begins immediately. The conversion results are output

when bits DAOE0 an d DAOE1 are set to 1.

An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 16.2.

1. Data to be co nverted is written in DADR0.

2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an outpu t pin. The

converted result is output af ter the conversion time. The output value is (DADR0

contents/256) × VREF. Output of this conversion result con tinues until the value in DADR0 is

modified or the DAOE0 bit is cleared to 0.

3. If the DADR0 value is modified, conversion starts immediately, and the result is outp u t after

the conversion time.

4. When the DAOE0 b it is cleared to 0, DA0 becomes an input pin.

DADR0

write cycle DACR

write cycle DADR0

write cycle DACR

write cycle

Address

bus

DADR0

DAOE0

Conversion data 1 Conversion data 2

High-impedance state Conversion

result 1

Conversion

result 2

tDCONV tDCONV

Legend

t : D/A conversion time

DCONV

Figure 16.2 Example of D/A Converter Operation

Rev. 6.0, 09/02, page 562 of 876

16.4 D/A Output Control

In the H8/3048 Series, D/A converter output can be enabled or disabled in software standby mode.

When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby

mode. The D/A converter registers retain the values they held prior to the transition to software

standby mode.

When D/A output is enabled in software standby mode, the reference supply current is the same as

during normal operation.

16.5 Usage Notes

When using an D/A converter, note the following.

1. VCC ≥ AVCC – 0.3V

2. AVCC ≥ VREF ≥ ANn ≥ AVSS = VSS

(N = 0 to 7)

Note: Restriction for the ZTATTM version only; The S Mask version of ZTATTM, the Flash

Memory version and Mask ROM version can be used regularly without restriction.

Rev. 6.0, 09/02, page 563 of 876

Section 17 RAM

17.1 Overview

The H8/3048 and H8/3047 have 4 kbytes of high-speed static RAM on-chip. The H8/3045 and

H8/3044 have 2 kbytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU

accesses both byte data and word data in two states, making the RAM useful for rapid data

transfer.

The on-chip RAM of the H8/304 8 and H8/3047 is assigned to add resses H'FEF10 to H'FFF0 F in

modes 1, 2, 5, and 7, and to addresses H'FFEF10 to H'FFFF0 F in modes 3, 4, and 6. The on-chip

RAM of the H8/3045 and H8/3044 are assigned to addresses H'FF710 to H'FFF0F in modes 1, 2,

5, and 7, and to addresses H'FFF710 to H'FFFF0F in modes 3, 4, and 6. The RAM enable bit

(RAME) in the system control register (SYSCR) can enable or disable the on-chip RAM.

Rev. 6.0, 09/02, page 564 of 876

17.1.1 Block Diagram

Figure 17.1 shows a block diagram of the on-chip RAM.

H'FEF10*

H'FEF12*

H'FFF0E*

H'FEF11*

H'FEF13*

H'FFF0F*

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Bus interface SYSCR

On-chip RAM

Even addresses Odd addresses

Legend

SYSCR: System control register

Note: *This example is of the H8/3048 operating in mode 7. The lower 20 bits of the address

are shown.

Figure 17.1 RAM Block Diagram

17.1.2 Register Configuration

The on-chip RAM is controlled by SYSCR. Table 1 7.1 gives the address and initial value of

SYSCR.

Table 17.1 System Control Register

Address*Name Abbreviation R/W Initial Value

H'FFF2 System control register SYSCR R/W H'0B

Note: * Lower 16 bits of the address.

Rev. 6.0, 09/02, page 565 of 876

17.2 System Control Register (SYSCR)

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

NMIEG

R/W

—

RAME

R/W

Software standby Standby timer select 2 to 0

User bit enable

NMI edge select

Reserved bit

RAM enable

Enables or

disables

on-chip RAM

One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is

enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,

System Control Register (SYSCR).

Bit 0—RA M Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized at the rising edge of the input at the RES pin. It is not initialized in software standby

mode.

Bit 0: RAME Description

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initial value)

Rev. 6.0, 09/02, page 566 of 876

17.3 Operation

When the RAME bit is set to 1, the on- chip RAM is enabled. Accesses to add resses H'FEF10 to

H'FFF0F in the H8/3048 and H8/3047 in modes 1, 2, 5, and 7, addresses H'FFEF10 to H'FFFF0F

in the H8/3048 and H8/3047 in modes 3, 4, and 6, addresses H'FF710 to H'FFF0F in the H8/3045

and H8/3044 in modes 1, 2, 5, and 7, and addresses H'FFF710 to H'FFFF0F in the H8/3045 and

H8/3044 in modes 3, 4, and 6 are directed to the on-chip RAM. In modes 1 to 6 (expanded

modes), when the RAME bit is cleared to 0, the off-chip address space is accessed. In mode 7

(single-chip mode), wh en the RAME bit is cleared to 0, the on-chip RAM is not accessed: read

access always results in H'FF data, and write access is ignored.

Since the on- chip RAM is co nnected to the CPU by an in ternal 16-b it data bus, it can be written

and read by word access. It can also be written and read by byte access. Byte d ata is accessed in

two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed

in two states using all 16 bits of the data bus.

Rev. 6.0, 09/02, page 567 of 876

Section 18 ROM

(H8/3048ZTAT and Mask-ROM Versions)

18.1 Overview

The H8/3048 has 128 kbytes of on-chip ROM, the H8/3047 has 96 kbytes, the H8/3045 has

64 kbytes and the H8/3044 has 32 kbytes. The ROM is connected to the CPU by a 16-bit data bus.

The CPU accesses both byte data and word data in two states, enabling rapid data transfer.

The mode pins (MD2 to MD0) can be set to enable or disable the on-chip ROM as indicated in

table 18.1.

Table 18.1 Operating Mode and ROM

Mode Pins

Mode MD2MD1MD0On-Chip ROM

Mode 1

(1-Mbyte expanded mode with on-chip ROM disabled) 001

Mode 2

(1-Mbyte expanded mode with on-chip ROM disabled) 010

Mode 3

(16-Mbyte expanded mode with on-chip ROM disabled) 011

Mode 4

(16-Mbyte expanded mode with on-chip ROM disabled) 100

Disabled

(external

address area)

Mode 5

(1-Mbyte expanded mode with on-chip ROM enabled) 101

Mode 6

(16-Mbyte expanded mode with on-chip ROM enabled) 110

Mode 7 (single-chip mode) 1 1 1

Enabled

The PROM version (H8/3048ZTAT) can be set to PROM mode and programmed with a general-

purpose PROM programmer.

Note: Care is required when changing from the H8/3048F-ONE to a model with on-chip mask

ROM (H8/3048, H8/3047, H8/3045, or H8/3044).

For details, refer to the H8/3048F-ONE Hardware Manual (Rev. 1.0) 1.4.5, Note on

Changeover to Mask ROM Version.

Rev. 6.0, 09/02, page 568 of 876

18.1.1 Block Diagram

Figure 18.1 shows a block diagram of the ROM.

H'0000

H'0002

H'1FFFE

H'0001

H'0003

H'1FFFF

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

On-chip ROM

Even addresses Odd addresses

Bus interface

Figure 18.1 ROM Block Diagram (H8/3048, Mode 7)

Rev. 6.0, 09/02, page 569 of 876

18.2 PROM Mode

18.2 .1 PROM Mode Set ting

In PROM mode, the H8/3048 (H8/3048ZTAT) version with on-chip PROM suspends its

microcontroller functions, enabling the on-chip PROM to be programmed. The programming

method is the same as for the HN27C101, except that page programming is not supported. Table

18.2 indicates how to select PROM mode.

Table 18.2 Selecting PROM Mode

Pins Setting

Three mode pins (MD2, MD1, MD0) Low

STBY pin

P51 and P50High

18.2.2 Socket Adapter and Memory Map

The PROM is programmed using a general-pu rpose PROM programmer with a socket adapter to

convert to 32 pins. Table 18.3 lists the socket adapter for each package option. Figure 18.2 shows

the pin assignments of the socket adap ter. Figure 18.3 shows a memory map in PROM mode.

Table 18.3 Socket Adapter

Microcontroller Package Socket Adapter

H8/3048 100-pin QFP (FP-100B) HS3042ESHS1H

100-pin TQFP (TFP-100B) HS3042ESNS1H

The size of the H8/3048 PROM is 128 kbytes. Figure 18.3 shows a memory map in PROM mode.

H'FF data should be specified for unused address areas in the on-chip PROM.

When programming the H8/3048 with a PROM programmer, set the address range to H'00000 to

H'1FFFF.

Rev. 6.0, 09/02, page 570 of 876

H8/3048

FP-100B, TFP-100B

NMI

REF

PROM Socket

HN27C101 (32 Pins)

Legend

V :

EO to EO :

EA to EA :

Programming voltage (12.5 V)

Data input/output

Address input

Output enable

Chip enable

Program

Note: Pins not shown in this diagram should be left open.

This figure shows pin assignments, and does not show the entire socket adapter circuit. When undertaking a new design,

board design (power supply voltage stabilization, noise countermeasures, etc.) as a high-speed CMOS LSI is necessary.

Figure 18.2 Socket Adapter Pin Assignments

Rev. 6.0, 09/02, page 571 of 876

On-chip PROM

H'00000 H'00000

H'1FFFF H'1FFFF

Address in

MCU mode Address in

PROM mode

Figure 18.3 H8/3048ZTAT Memory Map in PROM Mode

18.3 PROM Programming

Table 18.4 indicates how to select the program, verify, and other modes in PROM mode.

Table 18.4 Mode Selection in PROM Mode

Pins

Mode CE

CECE

CE OE

OEOE

OE PGM

PGMPGM

PGM VPP VCC EO7 to EO0EA16 to EA0

Program L H L VPP VCC Data input Address input

Verify LLH V

PP VCC Data output Address input

Program inhibited L L L VPP VCC High impedance Address input

LHH

HLL

HHH

Legend

L: Low voltage level

H: High voltage level

VPP:V

PP voltage level

VCC:V

CC voltage level

Read/write specifications are the same as for the standard HN27C101 EPROM, except that page

programming is not supported. Do not select page programming mode. A PROM programmer that

supports only page-programming mode cannot be used. When selecting a PROM programmer,

check that it supports a byte-at-a-time high-speed programming mode. Be sure to set the addr ess

range to H'00000 to H'1FFFF.

Rev. 6.0, 09/02, page 572 of 876

18.3.1 Programming and Verification

An efficient, high-speed programming procedure can be used to program and verify PROM data.

This procedure programs the chip quickly without subjecting it to voltage stress and without

sacrificing d ata reliability. Unused address areas contain H'FF data. Figure 18.4 shows the basic

high-speed programming flowchart. Tables 18.5 and 18.6 list the electrical characteristics of the

chip during programming. Figure 18.5 shows a timing chart.

Start

Set programming/verification mode

V = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V

CC PP

Address = 0

→

Verification OK?

Program with t = 0.2n ms

OPW

Last address?

Set read mode

V = 5.0 V ± 0.25 V, V = V

CC PP CC

All addresses

read?

End

Fail

n 25<

Address + 1 address→

No Yes

Yes

Program with t = 0.2 ms ± 5%

n = 0

n + 1 n

Yes

Figure 18.4 High-Speed Programming Flowchart

Rev. 6.0, 09/02, page 573 of 876

Table 18.5 DC Characteristics in PROM Mode

(Conditions: VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, VSS = 0 V, Ta = 25°C ± 5°C)

Item Symbol Min Typ Max Unit Test Conditions

Input high

voltage EO7 to EO0,

EA16 to EA0,

OE, CE, PGM

VIH 2.4 — VCC + 0.3 V

Input low

voltage EO7 to EO0,

EA16 to EA0,

OE, CE, PGM

VIL –0.3 — 0.8 V

Output high

voltage EO7 to EO0VOH 2.4 — — V IOH = –200 µA

Output low

voltage EO7 to EO0VOL ——0.45 V I

OL = 1.6 mA

Input leakage

current EO7 to EO0,

EA16 to EA0,

OE, CE, PGM

|ILI| ——2 µAV

in = 5.25 V /0.5 V

VCC current ICC ——40 mA

VPP current IPP ——40 mA

Note: For details on absolute maximum ratings, see section 22.1.1, Absolute Maximum Ratings.

Using an LSI in excess of absolute maximum ratings may result in permanent damage.

VPP peak overshoot should not exceed 13 V.

Rev. 6.0, 09/02, page 574 of 876

Table 18.6 AC Characteristics in PROM Mode

(Conditions: VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)

Item Symbol Min Typ Max Unit Test Conditions

Address setup time tAS 2 — — µs Figure 18.5*1

OE setup time tOES 2——µs

Data setup time tDS 2——µs

Address hold time tAH 0——µs

Data hold time tDH 2——µs

Data output disable time tDF*2— — 130 ns

VPP setup time tVPS 2——µs

Programming pulse width tPW 0.19 0.20 0.21 ms

PGM pulse width for overwrite

programming tOPW*30.19 — 5.25 ms

VCC setup time tVCS 2——µs

CE setup time tCES 2——µs

Data output delay time tOE 0 — 150 ns

Notes: *1 Input pulse level: 0.8 V to 2.2 V

Input rise time and fall time ≤ 20 ns

Timing reference levels: 1.0 V and 2.0 V for input; 0.8 V and 2.0 V for output

*2t

DF is defined at the point where the output is in the open state and the output level

cannot be read.

*3t

OPW is defined by the value given in the flowchart.

Rev. 6.0, 09/02, page 575 of 876

Address

Data

VPP

VCC

VPP

VCC

Program Verify

Input data Output data

tAS

tDS

tVPS

tVCS

tCES

tPW

tOPW*

tDH

tOES tOE

tDF

tAH

Note: t is defined by the value given in the flowchart.*OPW

Figure 18.5 PROM Program/Verify Timing

Rev. 6.0, 09/02, page 576 of 876

18.3.2 Programming Precautions

• Program with the specified voltages and timing.

The programming voltage (VPP) in PROM mode is 12.5 V.

Applied voltages in excess of the rated values can permanently destroy the chip. Be

particularly careful about the PROM programmer’s overshoot characteristics.

If the PROM programmer is set to Hitachi HN27C101 specifications, VPP will be 12.5 V.

• Before program ming, check that the chip is correctly mounted in the PROM programmer.

Overcurrent damage to the chip can result if the index marks on the PROM programmer,

socket adapter, and chip are not correctly aligned.

• Don’t touch the socket adapter or chip while programming. Touching either of these can cause

contact faults and write errors.

• Select the programming mode carefully. The chip cannot be programmed in page

programming mode.

• The H8/3048 PROM size is 128 kbytes. Set the address range to H'00000 to H'1FFFF.

Rev. 6.0, 09/02, page 577 of 876

18.3.3 Reliability of Programmed Data

A highly effective way to improve data retention characteristics is to bake the programmed chips

at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM

memory cells prone to early failure.

Figure 18.6 shows the recommended screening procedure.

Install

Program chip and verify programmed data

Bake chip for 24 to 48 hours at

125 C to 150 C with power off

Read and check program

Figure 18.6 Recommended Screening Procedure

If a series of programming errors occurs while the same PROM programmer is in use, stop

programming and check the PROM programmer and socket adapter for defects. Please inform

Hitachi of any abnormal conditions noted during or after programming or in screening of program

data after high -temperature baking.

Rev. 6.0, 09/02, page 578 of 876

18.4 Notes on Ordering Mask ROM Version Chip

When ordering the H8/3048 Series chips with a mask ROM, note the following.

• When ordering through an EPROM, use a 128-kbyte one.

• Fill all the unused addresses with H'FF as shown in figure 18.7 to make the ROM data size 128

kbytes for all H8/3048 Series chips, which incorporate different sizes of ROM. This applies to

ordering through an EPROM and through electrical data transfer.

HD6433048

(ROM: 128 kbytes)

Address:

H'00000–H'1FFFF

H'00000

Note: * Program H'FF to all addresses in these areas.

H'1FFFF

HD6433047

(ROM: 96 kbytes)

Address:

H'00000–H'17FFF

H'00000

Not used*

H'17FFF

H'18000

H'1FFFF

HD6433045

(ROM: 64 kbytes)

Address:

H'00000–H'0FFFF

H'00000

H'0FFFF

H'10000

H'1FFFF

HD6433044

(ROM: 32 kbytes)

Address:

H'00000–H'07FFF

H'00000

H'07FFF

H'08000

H'1FFFF

Figure 18.7 Masked ROM Addresses and Data

Rev. 6.0, 09/02, page 579 of 876

• The flash memory control registers (FLMCR, EBR1, EBR2, and RAMCR)* for use only by

the on-chip flash memory version (H8/3048F (dual-power-supply model)) are not provided in

the mask ROM version. Reading a corresponding address will always return a value of 1, and

writes to the corresponding addresses are invalid. This point must be noted when switching

from a flash memory model to a mask ROM version.

• In the case of the H8/3048F-ONE (single-power-supply model) on-chip flash memory version,

the 5 V version has a VCL pin and requires connection of an external capacitor. Care is

therefore required with the board design when switching to a mask ROM version. (For details,

see section 1.4.5, Notes on Switching to Mask ROM Version, in the H8/3048F-ONE Hardware

Manual (First Edition).

Note: * In the H8/3048F-ONE with on-chip flash memory, the flash memory control registers are

FLMCR1, FLMCR2, EBR, and RAMCR. (For details, see appendix B, Internal I/O

Registers, in the H8/3048F-ONE Hardware Manual (First Edition)).

Rev. 6.0, 09/02, page 580 of 876

Rev. 6.0, 09/02, page 581 of 876

Section 19 Flash Memory

(H8/3048F: Dual Power Supply (VPP = 12 V))

19.1 Overview

The H8/3048F has 128 kbytes of on-chip flash memory. The flash memory is connected to the

CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, enabling

rapid data transfer.

The mode pins (MD2 to MD0) can be set to enable or disable the on-chip ROM as indicated in

table 19.1.

Table 19.1 Operating Mode and ROM

Mode Pins

Mode MD2MD1MD0On-Chip ROM

Mode 1

(1-Mbyte expanded mode with on-chip ROM disabled) 001

Mode 2

(1-Mbyte expanded mode with on-chip ROM disabled) 010

Mode 3

(16-Mbyte expanded mode with on-chip ROM disabled) 011

Mode 4

(16-Mbyte expanded mode with on-chip ROM disabled) 100

Disabled

(external

address area)

Mode 5

(1-Mbyte expanded mode with on-chip ROM enabled) 101

Mode 6

(16-Mbyte expanded mode with on-chip ROM enabled) 110

Mode 7 (single-chip mode) 1 1 1

Enabled

The H8/3048F (dual-power supply flash memory version) can be set to PROM mode and

programmed with a general-purpose PROM programmer.

Rev. 6.0, 09/02, page 582 of 876

19.2 Flash Memory Overview

19.2.1 Flash Memory Operation

Table 19.2 illustrates the principle of operation of the on-chip flash memory of th e H8/3048F

(dual-power supply).

Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws

hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a

programmed memory cell is therefore higher than th at of an erased cell. Cells are erased by

grounding th e gate and applying a high voltage to the source, causing the electrons stored in the

floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like

an EPROM cell, by driving the gate to the high level and detecting the drain current, which

depends on the threshold voltage. Erasing must be done carefully, because if a memory cell is

overerased, its threshold voltage may become negative, causing the cell to operate incorrectly.

Section 19.5.6, Erasing Flowchart and Sample Program shows an optimal erase control flowchart

and sample program.

Table 19.2 Principle of Memory Cell Operation

VdVd

Vg = VPP

Open

Vg = VCC

Vs = VPP

Open Open

0 V

VPP

0 V

Vd 0 V

VCC

0 V

Vd 0 V

VPP

0 V

Program

Memory

cell

Memory

array

Erase Read

Rev. 6.0, 09/02, page 583 of 876

19.2.2 Mode Programming and Flash Memory Address Space

As its on-chip ROM, the H8/3048F has 128 kbytes of flash memory. The flash memory is

connected to the CPU by a 16 -bit data bus. The CPU accesses both byte data and word data in two

states.

The flash memory is assigned to addresses H'00000 to H'1FFFF on the memory map. The mode

pins enable either on-ch ip flash memory or external memory to be selected for this area. Table

19.3 summarizes the mode pin settings and usage of the flash memory area.

Table 19.3 Mode Pin Settings and Flash Memory Area

Mode Pin Setting

Mode MD2MD1MD0Flash Memory Area Usage

Mode 0 0 0 0 Illegal setting

Mode 1 0 0 1 External memory area

Mode 2 0 1 0 External memory area

Mode 3 0 1 1 External memory area

Mode 4 1 0 0 External memory area

Mode 5 1 0 1 On-chip flash memory area

Mode 6 1 1 0 On-chip flash memory area

Mode 7 1 1 1 On-chip flash memory area

Rev. 6.0, 09/02, page 584 of 876

19.2.3 Features

Features of the flash memory are listed below.

• Five flash memory operating modes

The flash memory has five operating modes: program mode, program-verify mode, erase

mode, erase-verify mode, and prewrite-verify mode.

• Block erase designation

Blocks to be erased in the flash memory address space can be selected by bit settings. The

address space includes a large-block area (eight blocks with sizes from 12 kbytes to 16 kbytes)

and a small-block area (eight 512-byte blocks).

• Program and erase time

Programming one byte of flash memory typically takes 50 µs. Erasing all blocks (128 kbytes)

typically takes 1 s.

• Erase-program cycles

Flash memory contents can be erased and reprogrammed up to 100 times.

• On-board programming modes

These modes can be used to program, erase, and verify flash memory contents. There ar e two

modes: boot mode, and user programming mode.

• Automatic bit- r ate alignment

In boot-mode d a ta tr ansfer , the H8/3048F aligns its bit rate auto matically to the host bit rate

(9600 bps, 4800 bps and 2400 bps).

• Flash memory emulation by RAM

Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates

in real time.

• PROM mode

As an alternative to on-board programming, the flash memory can be programmed and erased

in PROM mode, using a general-purpose PROM programmer.

• Protect modes

Flash memory can be program-, erase-, and/or verify-protected in hardware and software

protect modes.

Rev. 6.0, 09/02, page 585 of 876

19.2.4 Block Diagram

Figure 19.1 shows a block diagram of the flash memory.

FLMCR

EBR1

EBR2

H'00000

H'00002

H'00004

H'1FFFC

H'1FFFE

H'00001

H'00003

H'00005

H'1FFFD

H'1FFFF

MD2

MD1

MD0

Internal data bus (upper)

Internal data bus (lower)

Bus interface and control section Operating

mode

On-chip flash memory

(128 kbytes)

Upper byte

(even address) Lower byte

(odd address)

Legend

FLMCR:

EBR1:

EBR2:

Flash memory control register*

Erase block register 1*

Erase block register 2*

Note: *The flash memory control registers (FLMCR, EBR1, and EBR2) and RAMCR are

used only by the flash memory version, and must not be accessed in the mask

ROM (ZTAT) version.

Figure 19.1 Flash Memory Block Diagram

Rev. 6.0, 09/02, page 586 of 876

19.2 .5 Input/Output Pins

Flash memory is controlled by the pins listed in table 19.4.

Table 19.4 Flash Memory Pins

Pin Name Abbreviation Input/Output Function

Programming power VPP Power supply Apply 12.0 V

Mode 2 MD2Input H8/3048F operating mode

programming

Mode 1 MD1Input H8/3048F operating mode

programming

Mode 0 MD0Input H8/3048F operating mode

programming

Transmit data TXD1Output Serial transmit data output

Receive data RXD 1Input Serial receive data input

The transmit data and receive data pins are used in boot mode.

19.2.6 Register Configuration

The flash memory is controlled by the registers listed in table 19.5.

Table 19.5 Flash Memory Registers

Address Name Abbreviation R/W Initial Value

H'FF40 Flash memory control register*3FLMCR R/W*2H'00*1

H'FF42 Erase block register 1*3EBR1 R/W*2H'00*1

H'FF43 Erase block register 2*3EBR2 R/W*2H'00*1

H'FF48 RAM control register RAMCR R/W H'70

Notes: *1 The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled).

*2 In modes 1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be

modified and is always read as H'FF.

*3 Dedicated registers fo r controlling flash memory, which are not provided by the mask-

ROM and ZTAT versions. Therefore, these registers must not be accessed in the mask-

ROM and ZTAT versions. These regi sters cannot be modified in the mask-ROM and

ZTAT versions.

Rev. 6.0, 09/02, page 587 of 876

19.3 Flash Memory Register Descriptions

19.3.1 Flash Memo ry Control Register

The flash memory control register (FLMCR) is an eight-bit register that controls the flash memory

operating modes. Transitions to program mode, erase mode, program-verify mode, and erase-

verify mod e are made by setting bits in th is register. FLMCR is initialized to H'00 by a reset, in

the standby modes, and when 12 V is not applied to VPP. When 12 V is applied to VPP, a reset or

entry to a standby mode initializes FLMCR to H'80.

Bit

Initial value

R/W

6543210

0000000

R/W

— — R/W R/W R/W R/W

—— PV E P

Reserved bits

Erase mode

Designates transition

to or exit from erase

mode

Program mode

Designates

transition to

or exit from

program mode

****

Program-verify mode

Designates transition to

or exit from program-verify

mode

Erase-verify mode

Designates transition to

or exit from erase-verify

mode

Programming power

Status flag indicating the

power to VPP

VPP enable

Disables or enables 12-V

application to VPP pin

V E

Note: *The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes

1, 2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is

always read as H'FF.

Rev. 6.0, 09/02, page 588 of 876

Bit 7—Programming Power (VPP): Prog ramm i ng powe r bit ( VPP) detects VPP, and level is

displayed as “1” or “0.” The permissible output currents for impressed high voltage VH are given

in 22.2.2, “DC Characteristics.” The value of VH ranges from VCC + 2 V to 11.4 V. If a voltage in

excess of VH is applied, “1” is displayed; otherwise “0” is displayed.

This bit restricts the hardware protect functions during write and erase operations for the flash

memory. For details on hardware protect, see section 19.5.8, “Protect Modes.” For notes on VPP

usage, see section 19.8, “Flash Memory Programming and Erasing Precautions (Dual-Power

Supply).”

Bit 7: VPP Description

0 [Clear conditi on] (Initial value)

This is the regular operational mode when a voltage exceeding VH is not

applied to the VPP pin. The flash memory cannot be written or erased.

“Hardware Protect” is displayed.

1 [Set condition]

This is the operational mode when a voltage exceeding VH is applied to the VPP

pin. The flash memory can be written and erased. “Hardware Protect Disabled”

is displayed*.

Note: *For correct write and erase funct ion s, t he setti ng sho uld be VPP = 12.0 V to 0.6 V (11.4 V to

12.6 V).

Bit 6—VPP Enable (VPPE): Disables or enables 12-V application to the VPP pin. After this bit is set,

it is necessary to wait f or at least 5 µs for the internal power supply to stabilize; pro gramming and

erasing cannot be performed until stabilization is complete. After this bit is cleared, it is necessary

to wait for the flash m emory read setup time (tFRS) in order to read flash memory.

Bit 6: VPPE Description

PP pin 12-V power supply is disabled (Initial value)

PP pin 12-V supply is enabled

Note: The power supply system used for the flash memory is switched by means of the VppE bit.

After switching, operation is no t guaranteed during the period before the power supply

system stabilizes. It is therefore prohibited to fetch from flash memory and execute an

instruction that sets or resets the VppE bit.

Bits 5 and 4—Reserved: Read-only bits, always read as 0.

Rev. 6.0, 09/02, page 589 of 876

Bit 3—Erase-Verify Mode (EV)*1: Selects transi tion to or exit from erase-verify mode.

Bit 3: EV Description

0 Exit from erase-verify mode (Initial value)

1 Transition to erase-verify mode

Bit 2—Erase-Verify Mode (PV)*1: Selects transition to or exit from program-verify mode.

Bit 2: PV Description

0 Exit from program-verify mode (Initial value)

1 Transition to program-verify mode

Bit 1—Erase Mo de (E)*1 *2: Selects tr ansition to or exit from erase mode.

Bit 1: E Description

0 Exit from erase mode (Initial value)

1 Transition to erase mode

Bit 0—Program Mode (P)*1 *2: Selects transition to or exit from program mode.

Bit 0: P Description

0 Exit from program mode (Initial value)

1 Transition to program mode

Notes: *1 Do not set two or more of these bits simultaneously. Do not turn off power supply

(VCC–VPP) while a bit is set.

*2 For each bit setting procedure, follow the algorithm describ e d in sectio n 19.5,

Programming and Erasing Flash Memory. For the notes on programming and erasing,

refer to section 19.8, Flash Memory Programming and Erasing Precautions (Dual-

Power Supply). Particularly, be sure to set the watchdog timer beforehand to prevent

program runaway, when the E or P bit is set.

Rev. 6.0, 09/02, page 590 of 876

19.3.2 Erase Block Register 1

Erase block register 1 (EBR1) is an eight-bit register that designates large flash-memory blocks

for programming and erasure. EBR1 is initialized to H'00 by a reset, in the standby modes, when

12 V is applied to VPP while the VPPE bit is 0, and when 12 V is not applied to VPP. When a bit in

EBR1 is set to 1, the corresponding block is selected and can be programmed and erased. Figure

19.2 shows a block map.

Bit 76543210

LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0

Initial value*00000000

Read/Write R/W*R/W*R/W*R/W*R/W*R/W*R/W*R/W*

Note: *The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes 1,

2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is always

read as H'FF.

Bits 7 to 0—Large Block 7 to 0 (LB7 to LB0): These bits select large blocks (LB7 to LB0) to be

programmed and erased.

Bits 7 to 0:

LB7 to LB0 Description

0 Block LB7 to LB0 is not selected (Initial value)

1 Block LB7 to LB0 is selected

Rev. 6.0, 09/02, page 591 of 876

19.3.3 Erase Block Register 2

Erase block register 2 (EBR2) is an eight-bit register that designates small flash-memory blocks

for programming and erasure. EBR2 is initialized to H'00 by a reset, in the standby modes, when

12 V is applied to VPP while the VPPE bit is 0, and when 12 V is not applied to VPP. When a bit in

EBR2 is set to 1, the corresponding block is selected and can be programmed and erased. Figure

19.2 shows a block map.

Bit 76543210

SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0

Initial value*00000000

Read/Write R/W*R/W*R/W*R/W*R/W*R/W*R/W*R/W*

Note: *The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes 1,

2, 3, and 4 (on-chip flash memory disabled), this register cannot be modified and is always

read as H'FF.

Bits 7 to 0—Small Block 7 to 0 (SB7 to SB0): These bits select small block s (SB7 to SB0) to be

programmed and erased.

Bits 7 to 0:

SB7 to SB0 Description

0 Block SB7 to SB0 is not selected (Initial value)

1 Block SB7 to SB0 is selected

Rev. 6.0, 09/02, page 592 of 876

Bit Addresses

LB0

LB1

LB2

LB3

LB4

LB5

LB6

LB7

SB0

SB1

SB2

SB3

SB4

SB5

SB6

SB7

H'00000–H'03FFF

H'04000–H'07FFF

H'08000–H'0BFFF

H'0C000–H'0FFFF

H'10000–H'13FFF

H'14000–H'17FFF

H'18000–H'1BFFF

H'1C000-H'1EFFF

H'1F000–H'1F1FF

H'1F200–H'1F3FF

H'1F400–H'1F5FF

H'1F600–H'1F7FF

H'1F800–H'1F9FF

H'1FA00–H'1FBFF

H'1FC00–H'1FDFF

H'1FE00–H'1FFFF

16 kbytes

12 kbytes

512 bytes

Large block

area

(124 kbytes)

Small block

area

(4 kbytes)

H'00000

H'03FFF

H'04000

H'07FFF

H'08000

H'0BFFF

H'0C000

H'0FFFF

H'10000

H'13FFF

H'14000

H'17FFF

H'18000

H'1BFFF

H'1C000

H'1F1FF

H'1F200

H'1F3FF

H'1F400

H'1F5FF

H'1F600

H'1F7FF

H'1F800

H'1F9FF

H'1FA00

H'1FBFF

H'1FC00

H'1FDFF

H'1FE00

H'1FFFF

H'1EFFF

H'1F000

Figure 19.2 Erase Block Map

Rev. 6.0, 09/02, page 593 of 876

19.3.4 RAM Control Register (RAMCR)

The RAM control register (RAMCR) enables flash-memory updates to be emulated in RAM, and

indicates flash memory errors.

Bit 76543210

FLER — — — RAMS RAM2 RAM1 RAM0

Initial value01110000

Read/Write R — — — R/W R/W R/W R/W

Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was

being programmed or erased. When bit 7 is set, flash memory is placed in an error-protect mode.*1

Bit 7: FLER Description

0 Flash memory is not write/erase-protected (is not in error protect mode*1)

(Initial value)

[Clearing cond iti on]

Reset or hardware stan db y mode

1 Indicates that an error occurred while flash memory was being programmed or

erased, and error protection*1 is in effect

[Setting conditions]

Flash memory was read*2 while being programmed or erased (including vector

or instruction fetch, but not including reading of a RAM area overlapped onto

flash memory).

A hardware exception-handling sequence (other than a reset, trace exception,

invalid instruction, trap instruction, or zero-divide exception) was executed just

before programming or erasing.

The SLEEP instruction (for transition to sleep mode or software standby mode)

was executed during programming or erasing.

A bus was released during programming or erasing.

Notes: *1 For details, see section 19.5.8, Protect Modes.

*2 The read data has undetermined values.

Bits 6 to 4—Reserved: Read-only bits, always read as 1.

Bit 3—RAM Select (RAMS)*: Is used with bits 2 to 0 to reassign an area to RAM (see table

19.6). When bit 3 is set, all flash-memory blocks are protected from programming and erasing,

regardless of the values of bits 2 to 0.

It is initialized by a reset and in hard ware standby mode. It is not initialized in software standby

mode.

Rev. 6.0, 09/02, page 594 of 876

Bits 2 to 0—RAM2 to RAM0*: These bits are used with bit 3 to reassign an area to RAM (see

table 19.6). They are initialized by a re set an d in h ardware stan dby mod e. They are not initialized

in software standby mode.

Note: * These b its can be written to in mod es 5, 6 , and 7 (on-chip flash memory enabled). In o ther

modes, they are always read as 0 and cannot be modified.

Table 19.6 RAM Area Reassignment

Bit 3 Bit 2 Bit 1 Bit 0

RAM Area RAMS RAM2 RAM1 RAM0

H'FFF000 to H'FFF1FF 0 0/1 0/1 0/1

H'01F000 to H'01F1FF 1000

H'01F200 to H'01F3FF 1001

H'01F400 to H'01F5FF 1010

H'01F600 to H'01F7FF 1011

H'01F800 to H'01F9FF 1100

H'01FA00 to H'01FBFF1101

H'01FC00 to H'01FDFF1110

H'01FE00 to H'01FFFF 1111

19.4 On-Board Programming Modes

When an on-board programming mode is selected, the on-chip flash memory can be programmed,

erased, and verified. There are two on-board programming modes: boot mode, and user program

mode. These modes are selected by inputs at the mode pins (MD2 to MD0) and VPP pin. Table 19.7

indicates how to select the on-board programming modes. For information about turning VPP on

and off, see note (4) in section 19.8, Flash Memory Programming and Erasing Precautions (Dual-

Power Supply).

Table 19.7 On-Board Programming Mode Selection

Mode Selections VPP MD2MD1MD0Notes

Mode 5 12 V 12 V 0 1

Mode 6 12 V 1 0

Boot mode

Mode 7 12 V 1 1

Mode 5 1 0 1

Mode 6 1 1 0

User program

mode

Mode 7 1 1 1

0: VIL

1: VIH

Rev. 6.0, 09/02, page 595 of 876

19.4.1 Boot Mode

To use boot mode, a user program for programming and erasing the flash memory must be

provided in advance on th e host machine (which may be a personal computer). Serial

communication interface 1 (SCI 1) is used in asynchronous mode (see figure 19.3). If the

H8/3048F is placed in boot mode, after it comes out of reset, a built-in boot program is activated.

This prog ram starts by measuring th e low period of data transmitted from the host and setting the

bit rate register (BRR) accordingly. The H8/3048F’s built-in serial communication interface (SCI)

can then be used to download the user program from the host machine. The user program is stored

in on-chip RAM.

After the program has been stored, execution branches to address H'FF300 in modes 5 and 6 and

H'FFF300 in mode 7 in the on-chip RAM, and the program stored on RAM is executed to program

and erase the flash memory. Figure 19.4 shows the boot-mode execution procedure.

HOST

Receive data to be programmed

Transmit verification data

H8/3048F

RXD

TXD

SCI1

Figure 19.3 Boot-Mode System Configuration

Rev. 6.0, 09/02, page 596 of 876

Boot-Mode Execution Procedure: Figure 19.4 shows the boot-mode execution procedure.

Start

Program H8/3048F pins for

boot mode, and resets.

After completing bit rate adjustment,

H8/3048F transmits one H'00 byte to the

host to indicate completion.

Host transmits H'00 data

continuously at desired bit rate.

The host confirms that bit rate

adjustment was completed successfully,

then transmits one H'55 byte.

H8/3048F receives, as 2 bytes,

number of program bytes (N) to be

transferred to on-chip RAM*1

H8/3048F transfers user

program to RAM*2

H8/3048F calculates remaining

bytes to be transferred (N = N–1)

H8/3048F transfers part of

boot program to RAM

H8/3048F branches to RAM

boot area, then checks flash

memory user area data

Yes

H8/3048F confirms that all flash

memory data is H'FF, then

transmits one H'AA byte to host

H8/3048F branches to RAM area

address H'FFF300 and executes

user program transferred to RAM

Transfer end byte

count N = 0? No

Yes

H8/3048F measures H'00 low period

for data transmitted from the host.

H8/3048F computes the bit rate, then

sets the value in the bit rate register.

All data = H'FF?

Delete all flash memory

blocks*3,*4

1. Program the H8/3048F pins for boot mode, and start the

H8/3048F from a reset.

2. Set the host's data format to 8 bits + 1 stop bit, select the

desired bit rate (2400, 4800 or 9600), and transmit H'00

data continuously.

3. H8/3048F measures the duration of repeat when the RDX

pin is "Low," then computes the bit rate of the serial

transmission from the host.

4. After H8/3048F completes SCI bit rate adjustment, one byte

of H'00 data is transmitted to indicate completion.

5. On receiving one byte from H8/3048F to indicate completion

of bit rate adjustment, the host confirms regular reception

then transmits one byte of H'55. H8/3048F transmits H'AA to

indicate regular reception.

6. The host transmits the number of user program bytes to be

transferred to the H8/3048F. The number of bytes should

be sent as two bytes, upper byte followed by lower byte.

The host should then sequentially transmit the program set

by the user.

The H8/3048F transmits the received byte count and user

program sequentially to the host, one byte at a time, as

verify data (echo-back).

7. The H8/3048F sequentially writes the received user

program to on-chip RAM area H'FFF300 to H'FFFEFF.

8. The H8/3048F transfers part of the boot program to on-chip

RAM area H'FFEF10 to H'FFF2FF.

9. The H8/3048F branches to the RAM boot program area

(H'FFEF10 to H'FFF2FF) and checks for the presence of

data written in the flash memory. If data has been written in

the flash memory, the H8/3048F erases all blocks. When

erasing ends normally, the H8/3048F transmits one H'AA

byte.

10. The H8/3048F branches to on-chip RAM address H'FFF300

and executes the user program written in that area.

Notes: *1 The user can use 3072 bytes of RAM. The number of

bytes transferred must not exceed 3072 bytes. Be

sure to transmit the byte length in two bytes, most

significant byte first and least significant byte second.

For example, if the byte length of the program to be

transferred is 256 bytes, (H'0100), transmit H'01 as

the most significant byte, followed by H'00 as the

least significant byte.

*2 The part of the user program that controls the flash

memory should be coded according to the flash

memory program/erase algorithms given later.

*3 If a memory cell malfunctions and cannot be erased,

the H8/3048F transmits one H'FF byte to report an

erase error, halts erasing, and halts further

operations.

*4 The allotted boot program area is H'FFF300 to

H'FFFEFF.

Figure 19.4 Boot Mode Flowchart

Rev. 6.0, 09/02, page 597 of 876

Automatic Alignment of SCI Bit Rate

D0 D1 D2 D3 D4 D5 D6 D7

Start

bit Stop

bit

This low period (9 bits) is measured (H'00 data)

High for at

least 1 bit

Figure 19.5 Measurement of Low Period in Data Transmitted from Host

When started in boot mode, the H8/3048F measures the low period in asynchronous SCI data

transmitted fr om the host (figure 19.5). The data format is eight data bits, one stop bit, and no

parity bit. Fr om the measured low period (nine b its), the H8/3048F computes the h ost’s

transmission bit rate. After aligning its ow n bit rate, the H8/3048F sends the host one byte of H'00

data to indicate th at bit-rate alignment is completed. The h ost should check that this alignment-

completed indication is received normally, then transmit one H'55 byte. If the host does not

receive a normal alignment-completed indication, the H8/3048F sh ould be reset, then restarted in

boot mode to measure the low period again. There may be some alignment error between the

host’s and H8/3048F’s bit rates, depending on the host’s bit rate and the H8/3048F’s system clock

frequency. To have the SCI operate normally, set the host’s bit rate to a value 2400, 4800, or 9600

bps*1. Table 19.8 lists typical host bit rates and indicates the clock-frequency ranges over which

the H8/3048F can align its bit rate automatically. Boot mode should be used with in these

frequency ranges.*2

Table 19.8 System Clock Frequencies Permit t ing Automatic B it-Rate Alignment by

H8/3048F

Host Bit Rate*1System Clock Frequencies Permitting

Automatic Bit-Rate Alignment by H8/3048F

9600 bps 8 MHz to 16 MHz

4800 bps 4 MHz to 16 MHz

2400 bps 2 MHz to 16 MHz

Notes: *1 Host bit rate settings are 2400, 4800, and 9600 bps; no other settings should be used.

*2 Although the H8/3048F may perform automatic bit-rate alignment with combinations

of bit rate and system clock other than those shown in table 19.8, there may be a

discrepancy between the bit rates of the host and the H8/3048F, preventing subsequent

transfer from being performed normally. Boot mode execution should therefore be

confined to the range of combinations shown in table 19.8.

Rev. 6.0, 09/02, page 598 of 876

RAM Area Allocation in Boot Mode: In boot mode, the H'3F0 bytes from H'FEF10 to H'FF2FF

in modes 5 and 7, and from H'FFEF10 to H'FFF2FF in mod e 6 are reserved for use by the boot

program. The user program is transferred into the area from H'FF300 to H'FFEFF, in modes 5 and

7, and from H'FFF300 to H'FFFEFF in mode 6 (H'C00 bytes). The boot program area is used

during the transition to execution of the user program transferred into RAM.

User program

transfer area

(H'C00 bytes)

Boot

program

area*

H'FEF10

H'FF300

H'FFF0F

User program

transfer area

(H'C00 bytes)

Reserved*

Boot

program

area

H'FFEF10

H'FFF300

H'FFFF0F

H'FFF00 H'FFFF00

H'FFEFF H'FFFEFF

Modes 5 and 7 Mode 6

Notes: *1 This area is unavailable until the user program transferred into RAM enters execution state (branch

to H'FF300 in modes 5 and 7, and H'FFF300 in mode 6). After branching to the user program area,

the boot program is retained in the boot program area (H'FEF10 to H'FF2FF in modes 5 and 7, and

H'FFEF10 to H'FFF2FF in mode 6).

*2 Do not use reversed areas.

Figure 19.6 RAM Areas in Boot Mode

Rev. 6.0, 09/02, page 599 of 876

Notes on Use of Boot Mode

1. When the H8/3048F comes out of reset in boot mode, it measures the low period of the input at

the SCI1’s RXD1 pin. The reset should end with RXD1 high. After the reset ends, it take s ab out

100 states for the H8/3048F to get ready to measure the low period of the RXD1 input.

2. In boot mode, if any data has been programmed into the flash memory (if all data are not

H'FF), all flash memory blocks are erased. Boot mode is for use when user program mode is

unavailable, e.g. the first time on-board programming is performed, or if th e update program

activated in user program mode is accidentally erased.

3. Interrupts cannot be used while the flash memory is being programmed or erased.

4. The RXD1 and TXD1 lines should be pulled up on-board.

5. Before branching to the user program (at address H'F300 in the RAM area), the H8/3048F

terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE

and TE bits in serial control register (SCR) to 0 in channel 1), but the auto-aligned bit rate

remains set in bit rate register BRR1. The transmit data p in (TXD1) is in the high output state

(in port 9, the P91DDR bit in port 9 data direction register P9DDR and P91DR bit in port 9 data

When the branch to the user program occurs, the conten ts of general registers in the CPU are

undetermined. After the branch, the user program should begin by initializing general registers,

especially the stack p ointer (SP), which is used implicitly in subroutin e calls and at o ther

times. The stack pointer must be set to provide a stack area for use by the user program. The

other on- c hip registers do not have specific initialization r e quirements.

6. Transition to boot mode are shown in figure 19.7, User Program Mode Operation (Example).

This is possible after applying 12 V to pins MD2 and VPP and restarting. In this case, H8/3048F

reset is erased (startup with Low → High) timing*1, mode pin status latches the personal

computer internally to maintain boot mode. Boot mode can be erased if the 12 V applied to th e

MD2 pin and the VPP pin is erased, then reset is erased*1. However, please note the following.

a. When transferring from boot mode to regular mode (VPP ≠ 12 V, M D2 ≠ 12 V), before

transfer the erase must be carried out by the reset input personal computer internal boot

mode RES pin. After VPP interrupt, erase reset. The time needed until reset vector lead is

flash memory read setup (tFRS)*2.

b. While in boot mode, if the 12 V applied to the MD2 pin is erased, as long as reset input

from the RES pin does not occur, the personal computer internal boot mode status will be

maintained an d boot mo de will continue. In boot mode, if watchdog timer reset o ccur, th e

personal computer internal boot mode is not erased, and despite mode pin status the

internal boot program restarts.

c. When transferring to boot mode (reset erase timing) or during boot mode operation,

program voltage VPP should be within the range 12 V to 0.6 V. If this range is exceeded,

boot mode will not operate correctly. In addition, during boot program operation or writing

and erasing the flash memory, do not interrupt VPP*2.

Rev. 6.0, 09/02, page 600 of 876

7. During reset (when RES pin input is Low), if MD2 pin input changes from 0 V to 12 V or vice

versa, by instantaneous transfer to 5 V input, the personal computer switches to operation

mode. As a result, the address port or bus control output signal (AS, RD, HWR, LWR) status

changes, so do not these pins as output signals during reset, as the personal computer internal

section needs to be shut down.

8. Regard ing 12 V application to the VPP and MD2 pins, insure that peak overshoot does not

exceed the maximum rating of 13 V. Also, be sure to connect bypass capacitors to the Vpp and

MD2 pins*1.

Notes: *1 Mode pin input must satisfy the mode programming setup time (tMDS) with respect to

the reset release timing. When 12 V is applied to or disconnected from the MD2 pin, a

delay occurs in the fall and rise waveforms due to the influence of the pull-up/pull-

down resistor conn ected to the MD2 pin, etc. For reset release timing, therefore, this

delay must be confirmed with the actual waveform on the board.

*2 For notes on applying and cutting VPP, refer to 19.8, note (4) of “Flash Memory

Programming and Erasing Precautions (Dual-Power Supply).”

19.4.2 User Program Mode

When set to user program mode, the H8/3048F can erase and program its flash memory by

executing a user program. On-board updates of the on-chip flash memory can be carried out by

providing on-board circuits for supplying VPP and data, and storing an update program in part of

the program area.

To select user program mode, select a mode that enables the on-chip ROM (mode 5, 6, or 7) and

apply 12 V to the VPP pin. In this mode, the on-chip peripheral modules operate as they normally

would in mode 5, 6, or 7, except for the flash memory. A watchdog timer overflow, however,

cannot output a reset signal while 12 V is applied to VPP. The watchdog timer’s reset output enable

bit (RSTOE) should not be set to 1.

The flash memory cannot be read while being programmed or erased, so the update program must

either be stored in external memory, or transferred temporarily to the RAM area and executed in

RAM.

Rev. 6.0, 09/02, page 601 of 876

User Program Mode Execution Procedure: Figure 19.7 shows the procedure for user program

mode execution in RAM.

Transfer on-board update

program into RAM

Store user application programs

Set MD

to MD

to 101, 110, or 111

Apply 0 to 5 V to MD

= 12 V

(user program mode)

Wait 5 to 10 µs

Update flash memory

Execute user application program

Execute on-board update

program in RAM

Set V

E bit

Procedure

1. The user stores application programs in flash

memory. One of these is an on-board

update program that will execute steps 3 to 5

below.

2. Pin inputs are set up for user program mode.

3. A reset starts the CPU, which transfers the

on-board update program into RAM.

4. Following a branch to the program in RAM,

the on-board update program is executed.

VPPE bit in FLMCR is set to update flash

memory.

Wait 5 to 10 µs to stabilize internal power

supply.

Update program is executed.

5. After the on-board update ends, clear the

VPPE bit then a branch is made to the

updated user application program and this

program is executed.

After clearing the VPPE bit, before the flash

memory program executes, flash memory

read setup time (tFRS) is needed.

Note: To prevent microcontroller errors caused by accidental programming or erasing, apply 12 V to

VPP only when the flash memory is programmed or erased, or when flash memory is emulated

by RAM; do not apply 12 V to the VPP pin during normal operation. While 12 V is applied, the

watchdog timer should be running and enabled to halt runaway program execution, so that

program runaway will not lead to overprogramming or overerasing. For further information

about turning VPP on and off, see section 19.8, Flash Memory Programming and Erasing

Precautions (Dual-Power Supply).

Figure 19.7 User Program Mode Operation (Example)

Rev. 6.0, 09/02, page 602 of 876

19.5 Programming and Erasing Flash Memory

The H8/3048F’s on-chip flash memory is programmed and erased by software, using th e CPU.

The flash memory operating modes and state transition diagram are shown in figu re 19.8.

Program/erase modes comprise program mode, erase mode, program-verify mode, erase-verify

mode, and prewrite-verify mode. Transitions to these modes can be made by setting the P, E, PV,

and EV bits in the flash memory control register (FLMCR). Transition to th e prewrite-verify mode

can also be made by clearing all the bits in FLMCR.

The flash memory cannot be read while being programmed or erased. The program that controls

the programming and erasing of the flash memory must be stored and executed in on-chip RAM

or in external memory. A description of each mode is given below, with recommended flowcharts

and sample p rograms for programming and erasing. High-reliability programming and erasing

algorithms are used, which double the programming or erase processing time for each step.

Section 19.8, Flash Memory Programming and Erasing Precautions (Dual-Power Supply), gives

further notes on programming and erasing.

Normal ROM access mode

E= 0

off

EV= 0

Flash memory

program/erase

operations

Note: Do not perform simultaneous setting/clearing of the P, E, PV, and EV bits.

E= 0

EV= 1

E= 1

PV= 0

P= 0 PV= 1

P= 1

Program mode Program-verify

mode Erase-verify

mode

Erase mode

= 12 V and

E= 1

Prewrite-verify mode

Figure 19.8 Flash Memory Program/Erase Operating Mode State Transition Diagram

Rev. 6.0, 09/02, page 603 of 876

19.5.1 Program Mode

To write data in to the flash memory, follow the programming algorithm shown in figure 19.9.

This programming algorithm can write data without subjecting the device to voltage stress or

impairing the reliability of progra m med data.

To program data, first set the VPPE bit in FLMCR, wait 5 to 10 µs, then designate the blocks to be

programmed by erase block registers 1 and 2 (EBR1, EBR2), and write the data to the address to

be programmed, as in writing to RAM. The flash memory latches the address and data in an

address latch and data latch. Next set the P bit in FLMCR, selecting program mode. The

progr amming duration is the time durin g which the P bit is set. A software timer should be used to

provide an in itial p rogramming duration of 15.8 µs or less. Pr ogramming for too long a time, du e

to program runaway for ex ample, can cause device damage. Before selecting program mode, set

up the watchdog timer so as to prevent overprogramming.

19.5.2 Program-Verify Mode

In program-verify mode, after data has been programmed in program mode, the data is read to

check that it has been programmed correctly.

After the programming time has elapsed, exit programming mode (clear the P bit to 0) and select

program-verify mode (set the PV bit to 1). In program-verify mode, a program-verify voltage is

applied to th e memory cells at the latched address. If th e flash memory is read in this state, the

data at the latched addr ess will be read. After selecting program-verify mode, wait 4 µs before

reading, then compare the programmed data with the verify data. If they agree, exit program-

verify mode and program the next address. If they do not agree, select program mode again and

repeat the same program and program-verify sequence. Do not repeat the program and program-

verify sequence more than 6 times for the same bit. (When a bit is programmed repeatedly, set a

loop counter so that the total programming time will not ex ceed 1 ms.)

Rev. 6.0, 09/02, page 604 of 876

19.5.3 Programming Flowchart and Sample Program

Flowchart for Programming One Byte

Write data to flash memory (flash

memory latches write address

and data)

Start

n = 1

Enable watchdog timer

Wait initial value setting x = 15 µs

Select program mode

(P bit = 1 in FLMCR)

Wait (x) µs

Clear P bit

Disable watchdog timer

Select program-verify mode

(PV bit = 1 in FLMCR)

Wait (t

VS1

) µs

Verify (read memory)

No good

Clear PV bit

End (1-byte data programmed)

Programming ends

Clear PV bit

Programming error

n≥ N?

n + 1

Double the programming

time (x × 2 → x)

→ n

Yes

Verify ends

Set erase block register

(set bit of block to be programmed to 1)

Wait (z) µs

V E

Clear bit

Clear erase block register

(clear bit of programmed block to 0)

V E

Clear bit

Set V E bit

(V E bit = 1 in FLMCR)

Clear erase block register

(clear bit of block to be

programmed to 0)

Notes: *1 Write the data to be programmed using a

byte transfer instruction.

*2 Set the watchdog timer overflow interval

by setting CKS2 and CKS1 to 0 and

CKS0 to 1.

*3 Read to verify data from the memory

using a byte transfer instruction.

*4t

VS1:4 µs

z: 5 to 10 µs

N: 6 (set N so that total programming

time does not exceed 1 ms)

*5 Programming time x, which is determined

by the initial time × 2n–1 (n = 1 to 6),

increases in proportion to n. Thus, set the

initial time to 15.8 µs or less to make total

programming time 1 ms or less.

Figure 19.9 Programming Flowchart

Rev. 6.0, 09/02, page 605 of 876

Sample Program for Programming One Byte: This program uses the following registers.

R0: Program-verify fai l counte r

R1: Program-verify timing loop counter

ER2: Stores the address to be programmed as long word data. Valid addresses are H'00000000 to

H'0001FFFF.

R3H: Stores data to be programmed as byte data

R4: Sets and clears TCSR and FLMCR

E4: Stores the initial program loop counter value

R5: Clears FLMCR

E5: Stores the program loop counter value

Arbitrary data can be programmed at an arbitrary address by setting the address in ER2 and the

data in R3H.

The values of #a, #b, and #g depend on the clock frequency. They can be calculated as indicated

under table 19.9.

FLMCR: .EQU FFFF40

EBR1: .EQU FFFF42

EBR2: .EQU FFFF43

TCSR: .EQU FFFFA8

PRGM: MOV.W #0001, R0 ; Program-verify fail count

MOV.W #g, R1 ; Set program loop counter

MOV.W #4140, R4 ;

MOV.B R4L, @FLMCR:8 ; Set VPPE bit

LOOP0: DEC.W #1, R1 ;

BPL LOOP0

MOV.B #**, R0H ;

MOV.B R0H, @EBR*:8 ; Set EBR*

MOV.B R3H, @ER2 ; Dummy wri te

MOV.W #a, E4 ; Set init i al program l oop counter value

PRGMS: MOV.W #A579, R4 ; St art watchdog timer

MOV.W R4, @TCSR:16 ;

MOV:W E4, E5 ; Set program loop counter

MOV.W #4140, R4 ;

MOV.B R4H, @FLMCR:8 ; Set P bit

LOOP1: DEC.W #1, E5 ; Program

BPL LOOP1 ;

MOV.B R4L, @FLMCR:8 ; Clear P bit

MOV.W #A500, R4 ;

MOV.W R4, @TCSR:16 ; St op watc hdog timer

Rev. 6.0, 09/02, page 606 of 876

MOV:W #b , R1 ; Set program -verify l oop counter

MOV.B #44, R4H ;

MOV.B R4H, @FLMCR:8 ; Set PV bit

LOOP2: DEC.W #1, R1 ; Wait

BPL LOOP2 ;

MOV.B @ER2, R1H ; Read programmed address

CMP.B R3H, R1H ; Compare programm ed data with read data

BEQ PVOK ; Program-verify decision

PVNG: MOV.B #40, R5H ;

MOV.B R5H, @FLMCR:8 ; Clear PV bit

CMP.B #06, R0L ; Program-verify executed 6 times?

BEQ NGEND ; If program -verify executed 6 times, branch to NGEND

INC.B R0L ; Program-verify fail count + 1 → R0L

SHLL.W E4 ; Double program l oop count er value

BRA PRGMS ; Program agai n

PVOK: MOV.W #4000, R5 ;

MOV.B R5H, @FLMCR:8 ; Clear PV bit

MOV.B R5L, @EBR*:8 ; Clear EBR*

MOV.B R5L, @FLMCR:8 ; Clear VPPE bit

............................ One byte programmed

NGEND: MOV.W #4000, R5 ;

MOV.B R5L, @EBR*:8 ; Clear EBR*

MOV.B R5L, @FLMCR:8 ; Clear VPPE bit

Programming error

Rev. 6.0, 09/02, page 607 of 876

19.5.4 Erase Mode

To erase the flash memory, follow the erasing algorithm shown in figu re 19.10. This erasing

algorithm can erase data without subjecting the device to voltage stress or impairing the reliability

of programmed data.

To erase flash memory, before starting to erase, first place all memory data in all blocks to be

erased in the prog r ammed state (program all memory data to H'00 ). If all m emory data is not in the

programmed state, follow the sequence described later to program the memory data to zero. To

select the flash memory areas to be erased, first set the VPPE bit in the flash me mory con trol

Next set the E bit in FLMCR, selectin g erase mode. The erase time is the time during which the

E bit is set. To prevent overerasing, use a software timer to divide the erase time. Overerasing, due

to program runaway for example, can give memory cells a negative threshold voltage and cause

them to operate incorrectly. Before selecting erase mode, set up the watchdog timer so as to

prevent overerasing .

19.5.5 Erase-Verify Mo de

In program-verify mode, after data has been erased, it is read to check that it has been erased

correctly. After the erase time has elapsed, exit erase mode (clear the E bit to 0), select erase-

verify mode (set the EV bit to 1), and wait 4 µs. Before reading data in erase-verify mode, write

H'FF dummy data to the address to be read. This dummy wr ite applies an er ase-verify voltage to

the memory cells at the latched address. If the flash memo ry is r ead in this state, the data at the

latched addr ess will be read. After the dummy write, wait 2 µs before reading. If the read data has

been successfully erased, perform the dummy write, wait 2 µs, and erase-verify for the next

address. If the read data has not been erased, select erase mode again and repeat the same erase

and erase-ve r ify sequence through the last address, until all memory data has been erased to 1. Do

not repeat the erase and erase-verify sequence more than 602 times, however.

Rev. 6.0, 09/02, page 608 of 876

19.5.6 Erasing Flowchart and Sample Program

Flowchart for Erasing One Block

Start

Write 0 data in all addresses

to be erased (prewrite)

n = 1

Set erase block register

(set bit of block to be erased to 1)

Enable watchdog timer

Wait initial value setting x = 6.25 ms

Select erase mode

(E bit = 1 in FLMCR)

Clear E bit

Disable watchdog timer

Set top address in block

as verify address

Select erase-verify mode

(EV bit = 1)

Wait (t

VS1

) µs

Dummy write to verify address

(flash memory latches address)

Verify (read memory)

Last address?

Address + 1 → address Yes

No good

Yes

Clear EV bit

Clear erase block register

(clear bit of erased block to 0)

End of block erase

Clear EV bit

Erase error

n≥ N?

n≥ 5?

Erase-verify ends

Erasing ends

n + 1

Double the erase time

(x × 2 → x)

→ n

Wait (z) µs

V E

Set bit

( bit = 1 in FLMCR)

V E

Clear bit V E

Clear bit

Wait (x) ms

V E

Wait (t

VS2

) µs

Clear erase block register

(clear bit of block to be

erased to 0)

Notes: *1 Program all addresses to be

erased by following the prewrite

flowchart.

*2 Set the watchdog timer overflow

interval to the value indicated in

table 19.10.

*3 For the erase-verify dummy

write, write H'FF using a byte

transfer instruction.

*4 Read to verify data from the

memory using a byte transfer

instruction.

*5t

VS1:4 µs

z: 5 to 10 µs

tVS2:2 µs

N: 602

*6 The erase time x is successively

incremented by the initial set

value × 2n–1 (n = 1, 2, 3, 4). An

initial value of 6.25 ms or less

should be set, and the time for

one erasure should be 50 ms or

less.

Figure 19.10 Erasing Flowchart

Rev. 6.0, 09/02, page 609 of 876

Prewrite Flowchart

End of prewrite

n≥ N?

n + 1

Double

the programming

time (x × 2 → x)

→ n

Start

Address = top address

Wait initial value setting x = 15 µs

Write H'00 to flash memory

(flash memory latches

write address and write data)

Enable watchdog timer

Select program mode

(set P bit to 1 in FLMCR)

Wait (x) µs

Clear P bit

Disable watchdog timer

Wait (t

VS1

) µs

Prewrite verify

(read data = H'00?)

Last address?

No good

Yes

Programming ends

Programming error

Address + 1 → address

OK Yes

Set erase block register

(set bit of block to be erased to 1)

Wait (z) µs

n = 1

V E

Clear bit

Clear erase block register

(clear bit of block to be erased to 0)

V E

Set bit

( bit = 1 in FLMCR)

V E

Clear erase block register

(clear bit of block to be erased to 0)

Clear V

E bit

Notes: *1 Use a byte transfer instruction.

*2 Set the watchdog timer overflow

interval by setting CKS2 = 0,

CKS1 = 0 and CKS0 = 1.

*3 In prewrite-verify mode P, E, PV,

and EV are all cleared to 0 and

12 V is applied to V

. Use a

byte transfer instruction.

*4t

VS1

:4 µs

z: 5 to 10 µs

N: 6 (set N so that total

programming time does not

exceed 1 ms)

Figure 19.11 Prewrite Flowchart

Rev. 6.0, 09/02, page 610 of 876

Sample Program for Erasing One Block: This program uses the following registers.

R0: Prewrite-verify and erase-verify fail counter

ER1: Stores address used in prewrite

ER2: Stores address used in prewrite and erase-verify

ER3: Stores address used in erase-verify

ER4: Timing loop counter

R5: Sets appropriate registers

R6: Sets appropriate registers

The values of #a, #c, #d, #e, #f, #g, and #h, in the program depend on the clock frequency. They

can be calculated as indicated in tables 19.9 and 19.10.

FLMCR: .EQU FFFF40

EBR1: .EQU FFFF42

EBR2: .EQU FFFF43

TCSR: .EQU FFFFA8

; #BLKSTR is top address of block to be erased

; #BLKEND is last address of block to be erased

MOV.L #BLKSTR:32, ER1 ; ER1: top address of block to be erased

MOV.L #BLKEND:32, ER2 ; ER2: l ast address of bl ock t o be erased

; Execute prewrite

PREWRT: MOV.W #g, R4 ; Set wait count er

MOV.W #4140, R6 ;

MOV.B R6L, @FLMCR:8 ; Set VPPE bit

LOOPR0: DEC.W #1, R4 ;

BPL LOOPR0 ;

;SET EBR1 or EBR2 bit of block to be erased

MOV.B #**, R5H ;

MOV.B R5H, @EBR* ; Set EBR*

PREWRN: SUB.B R0H, R0H ; R0: prewri t e -verify fail count

MOV.W #a, E4 ; Set initial prewrite loop counter value

PREWRS: MOV.B #00, R5H ; Write #00 data

MOV.B R5H, @ER1 ;

MOV.W #A579, R5 ; St art watchdog timer

MOV.W R5, @TCSR:16 ;

MOV.W E4, R4 ; Set prewri te loop counter

MOV.W #4140, R6 ;

MOV.B R6H, @FLMCR:8 ; Set P bit

Rev. 6.0, 09/02, page 611 of 876

LOOPR1: DEC.W #1, R4 ; Prewrite

BPL LOOPR1 ;

MOV.B R6L, @FLMCR:8 ; Clear P bit

MOV.W #A500, R5 ; St op watc hdog timer

MOV.W R5, @TCSR:16 ;

MOV.W #c , R5 ; Set prewri te-verify loop counter

LOOPR2: DEC.W #1, R5 ; Wait

BPL LOOPR2 ;

MOV.B @ER1, R5H ; Read data = H'00?

BEQ PWVFOK ; If read data = H'00, branch to PWVFOK

CMP.B #05, R0H ; Prewrite-verify execut ed 6 times?

BEQ ABEND1 ; If prewri te-verify executed 6 times, branch to

ABEND1

SHLL.W E4 ; Double prewrit e loop counter value

INC.B R0H ; Prewrite-verify fai l count + 1 → R0H

BRA PREWRS ; Prewrite again

PWVFOK: CMP.L ER2, ER1 ; Last address?

BEQ ERASES ;

INC.L #1, ER1 ; Addres s + 1 → R1

BRA PREWRN ; If not last address , prewrite next address

;Execute erase

ERASES: SUB.W R0, R0 ; R0: eras e-verify fail count

MOV.L #BLKSTR:32,ER3 ; ER3: top address of block to be erased

MOV.W #d, E4 ; Set initial erase loop counter value

ERASE: CMP.W #025A, R0 ; R0 = H'025A? (erase-verify fail count = 603?)

BEQ ABEND2 ; If R0 = H'025A, branch to ABEND2

INC.W #1, R0 ; Erase-verify fail count + 1 → R0

MOV.W E4, R4 ;

MOV.W #f, R5 ; St art watchdog timer

MOV.W R5, @TCSR:16 ;

MOV.B #42, R5H ; Set E bit

MOV.B R5H, @FLMCR:8 ;

LOOPE: PUSH.L ER5

POP.L ER5

PUSH.L ER5

POP.L ER5

Rev. 6.0, 09/02, page 612 of 876

PUSH.L ER5

POP.L ER5

DEC.W #1, R4 ; Erase

BPL LOOPE ;

MOV.B #40, R5H ;

MOV.B R5H, @FLMCR:8 ; Clear E bit

MOV.W #A500, R5 ;

MOV.W R5, @TCSR:16 ; St op watc hdog timer

; Execute erase-verify

MOV.B #48, R5H ;

MOV.B R5H, @FLMCR:8 ; Set EV bit

MOV.W #e , R4 ; R4: eras e-verify loop counter

LOOPEV: DEC.W #1, R4 ;

BPL LOOPEV ; Wait

EVR2: MOV.B #FF, @ER3 ; Dummy wri te

MOV.W #h, R4 ; R4: eras e-verify loop counter

LOOPDW: DEC.W #1, R4 ;

BPL LOOPDW ; Wait

MOV.B @ER3+, R4H ; Read

CMP.B #FF, R4H ; Read data = H'FF?

BNE RERASE ; If read data ≠ H'FF, branch to RERASE

CMP.L ER2, ER3 ; Last address in block?

BGT EVR2 ; If not last address in block, erase-verify next address

BRA OKEND, ; Branch to OKEND

RERASE: MOV.W #4000, R5 ;

MOV.B R5H, @FLMCR:8 ; Clear EV bit

DEC.L #1, ER3 ; Eras e-verify address – 1 → R3

CMP.W #0004, R0 ;

BGE KEEP ; Eras e executed 4 times ?

SHLL.W E4 ; Double eras e l oop count er value

KEEP: BRA ERASE ; Eras e agai n

OKEND: MOV.W #4000, R5 ;

MOV.B R5H, @FLMCR:8 ; Clear EV bit

MOV.W #0000, R5 ;

MOV.W R5, @EBR1:16 ; Clear EBR1 and EBR2

Rev. 6.0, 09/02, page 613 of 876

MOV.B R5L, @FLMCR:8 ; Clear V PPE bit

............................. One block erased

ABEND1: MOV.W #0000, R5 ;

MOV.W R5, @EBR1:16 ; Clear EBR1 and EBR2

MOV.B R5L, @FLMCR:8 ; Clear V PPE bit

Programming error

ABEND2: MOV.W #0000, R5 ;

MOV.W R5, @EBR1:16 ; Clear EBR1 and EBR2

MOV.B R5L, @FLMCR:8 ; Clear V PPE bit

Erase error

Rev. 6.0, 09/02, page 614 of 876

Flowchart for Erasing Multiple Blocks

Start

Write 0 data to all addresses to be

erased (prewrite)

n = 1

Set erase block registers

(set bits of blocks to be erased to 1)

Enable watchdog timer

Wait initial value setting x = 6.25 ms

Select erase mode (E bit = 1 in FLMCR)

Wait (x) ms

Clear E bit

Disable watchdog timer

Select erase-verify mode

(EV bit = 1 in FLMCR)

Wait (t

VS1

) µs

Set top address of block as

verify address

Dummy write to verify address

(flash memory latches address)

Erase-verify

next block

Verify

(read memory)

Last

address in block?

Address + 1 → address

Clear EBR bit of erase-verified block

All erased blocks

verified?

Clear EV bit

All blocks erased?

(EBR1 = EBR2 = 0?)

End of erase n≥ N?

Erase error

n + 1 → n

Yes

No good

Erasing ends

All erased blocks

verified?

Erase-verify next block

Yes

V E

Clear bit

Clear erase block registers

(clear bits of blocks to be erased to 0)

n ≥ 4?

Wait (t

VS2

) µs

Wait (z) µs

V E

Clear bit

PP PP

Set V E bit

(V E bit = 1 in FLMCR)

Double the erase time (x × 2 → x)

Notes: *1 Program all addresses to be erased by

following the prewrite flowchart.

*2 Set the watchdog timer overflow interval to

the value indicated in table 19.10.

*3 For the erase-verify dummy write, write H'FF

with a byte transfer instruction.

*4 When erasing two or more blocks, clear the

bits of erased blocks in the erase block

erased again.

*5t

VS1

: 4 µs

z: 5 to 10 µs

VS2

:2 µs

N: 602

*6 The erase time x is successively

incremented by the initial set value

× 2n

–1

(n = 1, 2, 3, 4). An initial

value of 10 ms or less should be

set, and the time for one erasure

should be 50 ms or less.

Figure 19.12 Multiple-Block Erase Flowchart

Rev. 6.0, 09/02, page 615 of 876

Sample Program for Erasing Multiple Blocks: This program uses the following registers.

R0, R6: Specifies blocks to be erased (set as explained below)

R1H: Prewrite-verify fail counter

R1L: Used to test b its 0 to 15 of R0

ER2: Specifies address where address used in prewrite and erase-verify is stored

ER3: Stores address used in prewrite and erase-verify

ER4: Stores address used in prewrite and erase-verify

ER5: Sets appropriate registers

E0, E1: Timing loop counter

E6: Erase-verify fail counter

Arbitrary blocks can be erased by setting bits in R6.

A bit map of R6 and an example setting for erasing specific blocks are shown next.

LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit

Corresponds to EBR1 Corresponds to EBR2

Example: to erase blocks LB2, SB7, and SB0

LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bit

Corresponds to EBR1 Corresponds to EBR2

Setting 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1

R6 is set as follo ws:

MOV.W #0481, R6

MOV.W R6, @EBR1

The values of #a, #c, #d, #e, #f, #g, and #h in the program depend on the clock frequency. They

can be calculated as indicated in tables 19.9 and 19.10.

For #RAMSTR in the program, substitute the starting destin ation address in RAM, to be used

when this program is moved from flash memory into RAM.

Rev. 6.0, 09/02, page 616 of 876

FLMCR: .EQU FFFF40

EBR1: .EQU FFFF42

EBR2: .EQU FFFF43

TCSR: .EQU FFFFA8

; Set R0 val u e

START: MOV.W #FFFF, R6 ; Select bl ocks to be erased (R6: EBR1/EBR2)

MOV.W R6, R0 ; R0: EB R1/EBR2

SUB.W R1, R1 ; R1L: used to test R1-th bit in R0

; #RAMSTR is starti ng destination address to which program is transferred in RAM

; Set #RAMSTR to even number

MOV.L #RAMSTR:32, ER2 ; Start i ng transf er dest i nation address

ADD.L #ERVADR:32, ER2 ; #RAMST R + #ERVADR → ER2

SUB.L #START:32, ER2 ; ER2: address of data area used i n RAM

PRETST: CMP.B #10, R1L ; R1L = #10?

BEQ ERASES ; If finished checking all R0 bits, branch to ERASES

CMP.B #08, R1L ;

BCC BC0 ;

BTST R1L, R0H ;

BNE PREWRT ;

BRA PWADD1 ;

BC0: BTST R1L, R0L ; Test R1-th bit in R0

BNE PREWRT ; If R1-th bit in R0 is 1, branch to PREWRT

PWADD1: INC.B R1L ; R1L + 1 → R1L

MOV.L @ER2+, ER3 ; Dummy-increment ER2

BRA PRETST

; Execute prewrite

PREWRT: MOV.L @ER2+, ER3 ; ER3: prewri te starting address

MOV.L @ER2, ER4 ; ER4: top address of next block

MOV.W #g, E5 ; Wait counter

MOV.W #4140, R5 ;

MOV.B R5L, @FLMCR:8 ; Set VPPE bit

LOOPR0 DEC.W #1, E5 ;

BPL LOOPR0 ;

MOV.W R6, @EBR1:16 ; Set EBR (R 6: EBR1/EBR2 )

PREW: MOV.B #01, R1H ; Prewrit e-verify fail count

MOV.W #a, E0 ; Set initial prewrite loop counter value

Rev. 6.0, 09/02, page 617 of 876

PREWRS: MOV.B #00, R5H ; Write #00 data

MOV.B R5H, @ER3 ;

MOV.W #A579, E5 ;

MOV.W E5, @TCSR:16 ; Start watchdog timer

MOV.W E0, E1 ; Set program loop counter

MOV.W #4140, R5 ;

MOV.B R5H, @FLMCR:8 ; Set P bit

LOOPR1: DEC.W #1, E1 ; Program

BPL LOOPR1 ;

MOV.B R5L, @FLMCR:8 ; Clear P bit

MOV.W #A500, R5 ;

MOV.W R5, @TCSR:16 ; Stop watc hdog timer

MOV.W #c, R5 ; Prewrit e-verify loop counter

LOOPR2: DEC.W #1, R5 ;

BPL LOOPR2 ;

MOV.B @ER3, R5H ; Read data = #'00?

BEQ PWVFOK ; If read data = #'00, branch to PWVFOK

PWVFNG: CMP.B #06, R1H ; Prewrit e-verify executed 6 times?

BEQ ABEND1 ; If prewrite-verify executed 6 times, branch to ABEND1

INC.B R1H ; Prewrit e-verify fail count + 1 → R1H

SHLL.W E0 ; Double prewrite l oop count er val ue

BRA PREWRS ; Prewrit e agai n

PWVFOK: INC.L #1, ER3 ; Address + 1 → ER3

CMP.L ER4, ER3 ; Last address ?

BEQ PWADD2 ;

BRA PREW ;

PWADD2: INC.B R1L ; Used to test (R1L + 1)–th bit in R0

BRA PRETST ; Branch to PR ETST

; Execute erase

ERASES: MOV.W R6, @EBR1:16 ; Set EBR1 /E B R 2

SUB.W E6, E6 ; E6: erase-v erify fail count

MOV.W #d, E0 ; Set initial erase loop counter value

ERASE: MOV.W #f , R5 ;

MOV.W R5, @TCSR:16 ; Start watchdog timer

MOV.W E0, E1 ; Set erase-loop count er

MOV.W #4240, R5 ;

MOV.B R5H, @FLMCR:8 ; Set E bit

Rev. 6.0, 09/02, page 618 of 876

LOOPE: PUSH.L ER5

POP.L ER5

PUSH.L ER5

POP.L ER5

PUSH.L ER5

POP.L ER5

DEC.W #1, E1 ; Erase

BPL LOOPE

MOV.B R5L, @FLMCR:8 ; Clear E bit

MOV.W #A500, R5 ;

MOV.W R5, @TCSR:16 ; Stop watc hdog timer

; Execute erase-verify

EVR: MOV.W R6, R0 ; R0: EB R1/EBR2

SUB.W R1, R1 ; R1: used to test R1-th bit in R0

; #RAMSTR is starti ng destination address to which program is transferred in RAM

MOV.L #RAMSTR:32, ER2 ; Starting transfer destination address (RA M )

ADD.L #ERVADR:32, ER2 ; #RAMST R + #ERVADR → ER2

SUB.L #START:32, ER2 ; ER2: address of data area used i n RAM

MOV.B #48, R5H ;

MOV.B R5H, @FLMCR:8 ; Set EV bit

MOV.W #e , R5 ; R5: set erase-v eri fy loop counter

LOOPEV: DEC.W #1, R5 ; Program

BPL LOOPEV ; Wait

EBRTST: CMP.B #10, R1L ; R1L = #10?

BEQ HANTEI ; If finished checking all R0 bits, branch to HANTEI

CMP.B #08, R1L ;

BCC BC1 ;

BTST R1L, R0H ;Test R1-th bit i n R0H (EBR1)

BNE ERSEVF ;

BRA ADD01 ;

BC1: BTST R1L, R0L ; Test R1-th bit in R0L (EBR2)

BNE ERSEVF ; If R1-th bit in R0 is 1, branch to ERSEVF

ADD01: INC.B R1L ; R1L + 1 → R1L

MOV.L @ER2+, ER3 ; Dummy-increment R2

BRA EBRTST ;

Rev. 6.0, 09/02, page 619 of 876

ERSEVF: MOV.L @ER2+, ER3 ; ER3: top address of block to be erase-verified

MOV.L @ER2, ER4 ; ER4: top address of next block

EVR2: MOV.B #FF, R5H ;

MOV.B R5H, @ER3 ; Dummy write

MOV.W #h , R5 ; R5: erase-verify loop counter

LOOPDW: DEC.W #1, R5 ;

BPL LOOPDW ; Wait

MOV.B @ER3+, R5L ; Read

CMP.B #FF, R5L ; Read data = #FF?

BNE ADD02 ; If read data ≠ #FF, branch to ADD02

CMP.L ER4, ER3 ; Last address i n block ?

BNE EVR2 ; If not last address in block, branch to EVR2

CMP.B #08, R1L ;

BCC BC2 ;

BCLR R1L, R0H ; Clear R1L-th bi t in R0H (EB R1)

BRA ADD02 ;

BC2: BCLR R1L, R0L ; Clear R1L-th bit i n R0L (EBR2)

ADD02: INC.B R1L ; R1L + 1 → R1L

BRA EBRTST ; Erase-verify next erased block

HANTEI: MOV.W #4000, R5 ;

MOV.B R5H, @FLMCR:8 ; Clear EV bit

MOV.W R0, @EBR1:16 ; Clear bit of eras ed block t o 0

BEQ EOWARI ; If EBR1/EBR2 is all 0, erasing ended nor mally

CMP.W #025A, E6 ; E6 = 025A? (erase-verify fail count = 602?)

BEQ ABEND2 ; If E6 = 025A, branch to ABEND2

INC.W #1, E6 ; Erase-verify fail count + 1 → E6

CMP.W #0004, E6 ;

BGE KEEP ; Erase executed 4-times?

SHLL.W E0 ; Double erase loop counter value

KEEP: BRA ERASE ; Erase agai n

;————<Block address t abl e used in erase-v eri fy >——————————————————

.ALIGN2

ERVADR: .DATA.L 00000000 ; #0000 LB0

.DATA.L 00004000 ; #4000 LB1

.DATA.L 00008000 ; #8000 LB2

.DATA.L 0000C000 ; #C000 LB3

.DATA.L 00010000 ; #10000 LB4

Rev. 6.0, 09/02, page 620 of 876

.DATA.L 00014000 ; #14000 LB5

.DATA.L 00018000 ; #18000 LB6

.DATA.L 0001C000 ; #1C000 LB7

.DATA.L 0001F000 ; #1F000 SB0

.DATA.L 0001F200 ; #1F200 SB1

.DATA.L 0001F400 ; #1F400 SB2

.DATA.L 0001F600 ; #1F600 SB3

.DATA.L 0001F800 ; #1F800 SB4

.DATA.L 0001FA00 ; #1FA00 SB5

.DATA.L 0001FC00 ; #1FC00 SB6

.DATA.L 0001FE00 ; #1FE00 SB7

.DATA.L 00020000 ; #20000 FLASH AREA END ADDRESS

EOWARI: MOV.B #00, R5L ;

MOV.B R5L, @FLMCR:8 ; Clear VPPE bit

Erase end

ABEND1: MOV.W #0000, R5 ;

MOV.W R5, @EBR1:16 ; Clear EB R1 and EBR2

MOV.B R5L, @FLMCR:8 ; Clear VPPE bit

Programming error

ABEND2: MOV.W #0000, R5 ;

MOV.W R5, @EBR1:16 ; Clear EB R1 and EBR2

MOV.B R5L, @FLMCR:8 ; Clear VPPE bit

Erase error

Rev. 6.0, 09/02, page 621 of 876

Loop Counter Values in Programs and Watchdog Timer Overflow Interval Settings: The

values of a to h in the programs depend on the clock frequency. Table 19.9 indicates the values for

10 MHz. Values for other frequencies can be calculated as shown below, but use the settings in

table 19.10 for the value off.

Table 19.9 Loop Counter Values in Program (10 MHz)

Variable

Clock Frequency a (f) b (f) c (f) d (f) e (f) g (f) h (f)

f = 10 MHz Hexadecimal H'0019 H'0007 H'0007 H'03B3 H'0007 H'0009 H'0004

Decimal 25 7 7 947 7 9 4

Comments Program tVS1

at write tVS2

at pre-write Erase tVS1

at erase zt

VS2

Formula:

a (f) to h (f) = × {a (f = 10) to h (f = 10)}

Clock frequency f [MHz]

Examples for 16 MHz:

a (f) = ×25 = 40 ≈ H'0028

b (f) = ×7 = 11.2 ≈ H'000C

c (f) = ×7 = 11.2 ≈ H'000C

d (f) = ×947 = 1515.2 ≈ H'05EC

e (f) = ×7 = 11.2 ≈ H'000C

g (f) = ×9 = 14.4 ≈ H'000F

h (f) = ×4 = 6.4 ≈ H'0007

Rev. 6.0, 09/02, page 622 of 876

Table 19.10 Watchdog Timer Overflow Interval Settings

Variable

Clock Frequency f

10 MHz ≤ frequency ≤ 16 MHz H'A57F

2 MHz ≤ frequency < 10 MHz H'A57E

1 MHz ≤ frequency < 2 MHz H'A57D

Note: The watchdog timer (WDT) set value is calc ulated based on the number of instructions

including write time and eras e time from start to stop of WDT operation. In this program

example, therefore, no more instructions should be added between the start and stop of

WDT operation.

19.5.7 Prewrite-Verify Mode

Prewrite-verif y mode is a verify mode used after writing 0 to all bits to equalize their th r e shold

voltages before erasure.

To program all bits, write H'00 in accordance with the algorithm shown in figure 19.11. Use this

procedure to set all data in the flash memory to H'00 after pr ogr ammin g. After the necessary

programming tim e has elapsed, exit program mode (by clearing the P bit to 0) and select prewrite-

verify mode (leave the P, E, PV, and EV bits all cleared to 0). In prewrite-verify mode, a prewrite-

verify voltage is ap plied to the memory cells at the read address. If the flash memory is read in this

state, the data at the read add r ess will be read. After selecting prewr ite-verify mode, wait 4 µs

before reading.

Note: For a sample prewriting prog r am , see the sam p le erasing program.

Rev. 6.0, 09/02, page 623 of 876

19.5.8 Protect Modes

Flash memory can be protected from programming and erasing by software or hardware methods.

These two protection modes are described below.

Software Protection: Prevents transitions to program mode and erase mode even if the P or E bit

is set in the flash m emory control register ( FLMCR) . Details ar e as follows.

Function

Protection Description Program Erase Verify*1

Block

protect Individual blocks can be erase and

program-protected by the erase block

registers (EBR1 and EBR2). If EBR1 and

EBR2 are both set to H'00, all blocks are

erase- and program-protec ted.

Disabled Disabled Enabled

Emulation

protect When the RAMS bit is set in the RAM

control register (RAMCR), all blocks are

protected from both programming and

erasing.

Disabled*2Disabled*3Enabled

Notes: *1 Three modes: program-verify, erase-verify, and prewrite-verify.

*2 Except in RAM areas overlapped onto flash memory.

*3 All blocks are erase-disabled. It is not possible to specify individual blocks.

Rev. 6.0, 09/02, page 624 of 876

Hardware Protection: Suspends or disables the programming and erasing of flash memory, and

resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2 ).

The error-protect functio n permits the P and E bits to be set, b ut prevents transitions to progra m

mode and erase mode. Details of hardware protection are as follows.

Function

Protection Description Program Erase Verify*1

Programing

voltage (VPP)

protect

When VPP is not applied , FLMCR, EBR1,

and EBR2 are initialized, disabling

programming and erasing. To obtain this

protection, VPP shou ld not exc eed VCC.*3

Disabled Disabled*2Disabled

Reset and

standby

protect

When a reset occurs (including a

watchdog ti mer reset) or standby mode is

entered, FLMCR, EBR1, and EBR2 are

initialized, disabling programming and

erasing. Note that RES input does not

ensure a reset unless the RES pin is held

low for at least 20 ms at power-up (to

enable the oscillator to settle), or at least

10 system clock cycles (φ) during

operation.

Disabled Disabled*2Disabled

Error protect If an operational error is detected during

programming or erasing of flash memory

(FLER = 1), the FLMCR, EBR1, and EBR2

settings are preserv ed, but program m ing

or erasing is aborted immediately. This

type of protection can be cleared only by a

reset or hardware standb y.

Disabled Disabled*2Enabled

Notes: *1 Program-verify, erase-verify, and prewrite-verify modes.

*2 All blocks are erase-disabled. It is not possible to specify individual blocks.

*3 For details, see section 19.8, Flash Memory Programming and Erasing Precautions

(Dual-Power Supply).

Error Protect: This protection mode is entered if one of the error conditions that set the FLER bit

in RAMCR is detected while flash memory is being programmed or erased (while the P bit or E

bit is set in FLMCR). Th ese conditions can occur if microcontroller operations do not fo llow the

programming or erasing algorithm. Error protect is a flash-memory state. It does not affect other

microcontroller operations.

In this state the settings of the flash memory control register (FLMCR) and erase block registers

(EBR1 and EBR2) are preserved*, but program mode or erase mode is terminated as soon as the

error is detected. While the FLER bit is set, it is not possible to enter program mode or erase

mode, even by setting the P bit or E bit in FLMCR again . The PV and EV bits in FLMCR remain

valid, however. Transitions to verify modes are possible in the error-protect state.

Rev. 6.0, 09/02, page 625 of 876

The error-protect state can be cleared only by a reset or entry to hardware standby mode.

Note: * It is possible to write to these registers. Note that a transition to software standby mode

initializes these reg ister s.

P = 1 or E = 1 P = 0 and E = 0

Error occurs

= 0 or = 0

or software standby

= 1 and = 1

and not software standby

= 0 or

= 0

Error occurs

(software standby)

= 0 or

= 0

Software

standby

Software standby

cleared

= 0 or

= 0

RD:

VF:

PR:

ER:

INIT.:

Memory read enabled

Verify read enabled

Programming enabled

Erase enabled

Memory read disabled

Verify read disabled

Programming disabled

Erase disabled

Initialized state of registers (FLMCR, EBR1, EBR2)

Memory read

or verify mode

Program mode

or erase mode

Reset or standby

(hardware protect)

Error-protect mode

(software standby)

Error-protect mode

RD VF

FLER = 0

PR ER

FLER = 0

RD VF

FLER = 1

INIT.

FLER = 1

INIT.

FLER = 0

Figure 19.13 Flash Memory State Transitions in Modes 5, 6, and 7 (On-Chip ROM

Enabled) when Programming Voltage (VPP) is Applied

The purpose of error-protect mode is to prevent overprogramming or overerasing damage to flash

memory by detecting abnormal conditions that occur if the programming or erasing algorithm is

not followed, or if a program crashes while the flash memory is being programmed or erased.

This protection function does not cover abnormal conditions other than the setting conditions of

the flash memory error bit (FLER), however. Also, if too much time elapses before the error-

protect state is reached, the flash memory may already have been damaged. This function

accordingly does not offer foolproof protection from damage to flash memory.

To prevent abno rmal operations, when programming voltage (VPP) is applied, follow the

programming and erasing algorithms correctly, and keep microcontroller operations under

constant internal and external supervision, using the watchdog timer for example. If a transition to

error-protect mode occurs, the flash memory may contain incorrect data due to errors in

programming or erasing, or it may contain data that has been insufficiently programmed or erased

Rev. 6.0, 09/02, page 626 of 876

because of the suspension of these operations. Boot mode should be used to recover to a normal

state.

If the memory contains overerased memory cells, boot mode may not operate correctly. This is

because the H8/3048F’s built-in boot program is located in part of flash memory, and will not read

correctly if memory cells have been overerased.

19.5.9 NMI Input Masking

NMI input is disabled when flash memory is being programmed or erased (when the P or E bit is

set in FLMCR). NMI input is also disabled while the boot program is executing in boot mode,

until the br anch to the on-ch ip RAM ar ea takes place*1. There are three reasons for this.

• NMI input du ring programming or erasing might cause a violation of the programming or

erasing algorithm. Normal operation could not be assured.

• In the NMI exception-handling sequence during programming or erasing, the vector would not

be read correctly*2. The resu lt might be a program runaway.

• If NMI input occurred during boot program execution, the normal boot-mode sequence could

not be executed.

NMI input is also disabled in the error-protect state while the P or E bit remains set in the flash

memory control register (FLMCR).

NMI requests should be disabled externally whenever VPP is applied.

Notes: *1 The disabled state lasts until th e branch to the boot program area in on-ch ip RAM

(addresses H'FFEF10 to H'FFF2FF) that takes place as soon as the transfer of the user

program is completed. After the branch to the RAM area, NMI input is enabled except

during programming or erasing. NMI interrupt requests must therefore be disabled

externally until th e user program has completed in itial programming (including the

vector table and the NMI interrupt-handling program).

*2 The vector may not be read correctly for the following two reasons.

• If flash memory is read while being programmed or erased (while the P or E bit is

set in FLMCR), correct read data will not be obtained. Undetermined values are

returned.

• If the NMI entry in the vector table has not been programmed yet, NMI exception

handling will not be executed correctly.

Rev. 6.0, 09/02, page 627 of 876

19.6 Flash Memory Emulation by RAM

Erasing and programming flash memory takes time, which can make it difficult to tune parameters

and other data in real time. If necessary, real-time updates of flash memory can be emulated by

overlapping the small-block flash-memory area with part of the RAM (H'FFF000 to H'FFF1FF).

This RAM reassignment is performed using bits 3 to 0 of the RAM control register (RAMCR).

After a flash memory area has been overlapped by RAM, it can be accessed from two address

areas: the overlapped flash memo ry area, and the original RAM area (H'FFF000 to H'FFF1FF).

Table 19.11 indicates how to reassign RAM.

RAM Control Register (RAMCR)

Bit 76543210

FLER — — — RAMS RAM2 RAM1 RAM0

Initial value*01110000

Read/Write R — — — R/W R/W R/W R/W

Note: *Bit 7 and bits 3 to 0 are initialized by a reset and in hardware standby mode. They are not

initialized in software standby mode. Bits 3 to 0 can be written to in modes 5, 6, and 7 (on-

chip flash memory enabled). In other modes, they are always read as 0 and cannot be

modified.

Table 19.11 RAM Area Reassignment

Bit 3 Bit 2 Bit 1 Bit 0

RAM Area RAMS RAM2 RAM1 RAM0

H'FFF000 to H'FFF1FF 0 0/1 0/1 0/1

H'01F000 to H'01F1FF 1000

H'01F200 to H'01F3FF 1001

H'01F400 to H'01F5FF 1010

H'01F600 to H'01F7FF 1011

H'01F800 to H'01F9FF 1100

H'01FA00 to H'01FBFF1101

H'01FC00 to H'01FDFF1110

H'01FE00 to H'01FFFF 1111

Rev. 6.0, 09/02, page 628 of 876

Example of Emulation of Real-Time Flash-Memory Update

H'FFF000

H'01F9FF

H'01FA00

H'01FBFF

H'01FDFF

H'01FE00

H'01FFFF

H'FFF1FF

H'FFF200

H'FFFF0F

Flash memory

address space

Small-block

area (SB5)

Overlapped by RAM

H'01F000

On-chip RAM

area

H'FFEF10

Procedure

1. Set the RAME bit to 1 in SYSCR

to enable the on-chip RAM.

2. Overlap part of RAM (H'FFF000

to H'FFF1FF) onto the area

requiring real-time update (SB5).

(Set RAMCR bits 3 to 0 to

1101.)

3. Perform real-time updates in the

overlapping RAM.

4. After finalization of the update

data, clear the RAM overlap (by

clearing the RAMS bit).

5. Program the data written in RAM

addresses H'FFF000 to

H'FFF1FF into the flash memory

area.

Notes: 1. When part of RAM (H'FFF000 to H'FFF1FF) is overlapped onto a small-block area in flash

memory, the overlapped flash memory area cannot be accessed. Access is enabled when the

overlap is cleared.

2. When the RAMS bit is set to 1, all flash memory blocks are write-protected and erase-protected,

regardless of the values of bits RAM2 to RAM0. In this state, no transition to program or erase

mode will take place if the P or E bit is set in the flash memory control register (FLMCR). To

actually program or erase a flash memory area, the RAMS bit must be cleared to 0.

Figure 19.14 Example of RAM Overlap

Rev. 6.0, 09/02, page 629 of 876

19.7 Flash Memory PROM Mode

19.7 .1 PROM Mode Set ting

The on-chip flash memory of the H8/3048F can be programmed and erased not only in the on-

board programming modes but also in PROM mode, using a general-purpose PROM programmer.

Table 19.12 indicates how to select PROM mode. Be sure to use the indicated table 19.13 so cket

adapter in PROM mode.

Table 19.12 Selecting PROM Mode

Pins Setting

Mode pins: MD2, MD1, MD0Low

P80, P81, and P92

STBY and HWR High

P50, P51, and P82

RES Power on reset circuit

XTAL and EXTAL Osc i llator circuit

Rev. 6.0, 09/02, page 630 of 876

19.7.2 Socket Adapter and Memory Map

Programs can be written and verified by attaching a special 1 00- pin/32-pin socket adapter to the

PROM programmer. Table 19.13 gives ordering information for the socket adapter. Figure 19.15

shows a memory map in PROM mode. Figure 19 .16 shows the socket adapter pin

interconnections.

Table 19.13 Socket Adapter

Microcontroller Package Socket Adapter

HD64F3048F 100-pin plastic QFP (FP-100B) HS3048ESHF1H

HD64F3048VF

HD64F3048TF 100-pin plastic TQFP (TFP-100B) HS3048ESNF1H

HD64F3048VTF

H8/3048F

H'00000

H'1FFFF

H'000000

H'01FFFF

On-chip ROM area

MCU mode PROM mode

Figure 19.15 Memory Map in PROM Mode

Note: The FP-100B and TFP-100B pin pitch is only 0.5 mm. Use an appropriate tool when

inserting th e d e vice in the IC socket and removing it. For example, the tool listed in table

19.14 can be used.

Table 19.14

Manufacturer Part Number

ENPLAS CORPORATION HP-100 (vacuum pen)

Rev. 6.0, 09/02, page 631 of 876

H8/3048F

Pin Name

FP-100B, TFP-100B

53, 54, 89

62, 71

76, 77

1, 35, 68

11, 22, 44

57, 65, 92

66, 67

Other pins

HN28F101 (32 Pins)

Pin No.

Pin Name

I/O

Socket Adapter Pin No.

NMI

, P5

, P8

, MD

, P8

, V

REF

EXTAL, XTAL

NC (OPEN)

Power-on

reset circuit

Oscillator circuit

Legend

I/O

to I/O

to A

Programming

power supply

Data input/output

Address input

Output enable

Chip enable

Write enable

Note: This figure shows pin assignments, and does not show the entire socket adapter circuit. When undertaking a new

design, board design (power supply voltage stabilization, noise countermeasures, etc.) and operating timing design

as a high-speed CMOS LSI are necessary.

73 to 75

87, 88, 14 , P9

Figure 19.16 Wiring of Socket Adapter

Rev. 6.0, 09/02, page 632 of 876

19.7.3 Operation in PROM Mode

The program/erase/verify specifications in PROM mode are the same as for the standard

HN28F101 flash memory. Table 19.15 indicates how to select the various operating modes. The

H8/3048F does not have a device recognition code, so the prog rammer cannot read the device

name automatically.

Table 19.15 Operating Mo de Select ion in PROM Mode

Pins

Mode VPP VCC CE

CECE

CE OE

OEOE

OE WE

WEWE

WE I/O7 to I/O0A16 to A0

Read VCC VCC L L H Data output

Output

disable VCC VCC LHHHigh

impedance

Read

Standby VCC VCC HXXHigh

impedance

Read VPP VCC L L H Data output

Output

disable VPP VCC LHHHigh

impedance

Standby VPP VCC HXXHigh

impedance

Command

write

Write VPP VCC L H L Data input

Address input

Legend

L: Low level

H: High level

VPP:V

PP level

VCC:V

CC level

X: Don’t care

Rev. 6.0, 09/02, page 633 of 876

Table 19.16 PROM Mode Commands

1st Cycle 2nd Cycle

Command Cycles Mode Address Data Mode Address Data

Memory read 1 Write X H'00 Read RA Dout

Erase setup/er ase 2 Write X H'20 Write X H'20

Erase-verify 2 Write EA H'A0 Read X EVD

Auto-erase setup/

auto-erase 2 Write X H'30 Write X H'30

Program setup/

program 2 Write X H'40 Write PA PD

Program-verify 2 Write X H'C0 Read X PVD

Reset 2 Write X H'FF Write X H'FF

PA: Program address

EA: Erase-verify address

RA: Read address

PD: Program data

PVD: Program-verify outp ut data

EVD: Erase-verify output data

Rev. 6.0, 09/02, page 634 of 876

High-Speed, High- R eliability Progra mming: Unused areas of the H8/3048F flash memory

contain H'FF data (initial value). The H8/3048F flash memory uses a high-speed, high-reliability

programming procedure. This procedure provides enhanced programming speed with out

subjecting the device to voltage stress and without sacrificing the reliability of programmed data.

Figure 19 .17 shows the basic high-speed, high-reliability program m ing flowchart. Tables 19.17

and 19.18 list the electrical characteristics during programming.

Start

Set V

= 12.0 V ±0.6 V

Address = 0

n = 0

Program command

Program setup command

n + 1 → n

Wait (25 µs)

Program-verify command

Wait (6 µs)

Address + 1 → address

Verification?

Last address?

Set V

= V

End Fail

n = 20?

No good

Yes

Figure 19.17 Hig h-Speed, High-Reliability Prog ramming

Rev. 6.0, 09/02, page 635 of 876

High-Speed, Hig h- Reliability Erasing : The H8/3048F flash memory uses a high-speed, high-

reliability erasin g procedure. This proced ure provides enhanced erasing sp eed without subjecting

the device to voltage stress and without sacrificing data reliability. Figu re 19.18 shows the basic

high-speed, high-reliability erasing flowchar t. Tables 19 . 17 and 1 9.18 list the electrical

characteristics during programming.

Start

Program 0 to all bits*

Address = 0

n = 0

Wait (10 ms)

Erase setup/erase command

n + 1 → n

Erase-verify command

Wait (6 µs)

Address + 1 → address

Verification?

Last address?

End Fail

n = 3000?

No good

Yes

Note: * Follow the high-speed, high-reliability flowchart in programming all bits.

Figure 19.18 Hig h- Speed, H igh-Reliability Erasing

Rev. 6.0, 09/02, page 636 of 876

Table 19.17 DC Characteristics in PROM Mode

(Conditions: VCC = 5.0 V ±10%, VPP = 12.0 V ±0.6 V, VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Typ Max Unit Test Conditions

Input high

voltage I/O7 to I/O0,

A16 to A0,

OE, CE, WE

VIH 2.2 — VCC + 0.3 V

Input low

voltage I/O7 to I/O0,

A16 to A0,

OE, CE, WE

VIL –0.3 — 0.8 V

Output high

voltage I/O7 to I/O0VOH 2.4 — — V IOH = –200 µA

Output low

voltage I/O7 to I/O0VOL ——0.45 V I

OL = 1.6 mA

Input leakage

current I/O7 to I/O0,

A16 to A0,

OE, CE, WE

ILI ——2 µAV

IN = 0 to VCC V

VCC current Read ICC —4080 mA

Program ICC —4080 mA

Erase ICC —4080 mA

VPP current Read IPP — — 200 µA VPP = 5.0 V

—1020 mAV

PP = 12.6 V

Program IPP —2040 mA

Erase IPP —2040 mA

Note: For details on absolute maximum ratings, see section 22.2.1. Using an LSI in excess of

absolute maximum ratings may result in permanent damage*.

*VPP peak overshoot should not exceed 13 V.

Rev. 6.0, 09/02, page 637 of 876

Table 19.18 AC Characteristics in PROM Mode

(Conditions: VCC = 5.0 V ± 10%, VPP = 12.0 V ± 0.6 V, VSS = 0 V, Ta = 25°C ± 5°C)

Item Symbol Min Typ Max Unit Test Conditions

Command write cycle tCWC 120 — — ns

Address setup time tAS 0 ——ns

Address hold time tAH 60——ns

Data setup time tDS 50——ns

Data hold time tDH 10——ns

CE setup time tCES 0 ——ns

CE hold time tCEH 0 ——ns

VPP setup time tVPS 100 — — ns

VPP hold time tVPH 100 — — ns

WE programming pulse

width tWEP 70——ns

WE programming pulse

high time tWEH 20——ns

OE setup time before

command write tOEWS 0 ——ns

OE setup time before verify tOERS 6 ——µs

Verify access tim e tVA — — 500 ns

OE setup time before

status polling tOEPS 120 — — ns

Status polling access time tSPA — — 120 ns

Program wait time tPPW 25——ns

Erase wait time tET 9—11ms

Output disable time tDF 0 — 40 ns

Total auto-era se time tAET 0.5 — 30 s

Figure 19.19

Figure 19.20*

Figure 19.21

Note: CE, OE, and WE should be high during transitions of VPP from 5 V to 12 V and from 12 V to

5 V.

*Input pulse level: 0.45 V to 2.4 V

Input rise time and fall time ≤ 10 ns

Timing reference levels: 0.8 V and 2.0 V for input; 0.8 V and 2.0 V for output

Rev. 6.0, 09/02, page 638 of 876

Auto-erase setup Auto-erase and status polling

Address

Command

Status polling

Command

in Command

5.0 V

12 V

5.0 V

I/O

I/O to I/O

VPS

VPH

CEH

CES

OEWS

WEP

CEH

CES

CWC

WEP

OEPS

AET

WEH

SPA

Figure 19.19 Auto-Erase Timing

Rev. 6.0, 09/02, page 639 of 876

VPH

VPS

CEH

CES

OEWS

WEP

CEH

CES

CWC

WEP

PPW

CES

WEH

CEH

WEP

OERS

Command

Data

Command

Valid data

out

Valid data

out

Data

Program setup Program Program-verify

Valid address

Address

5.0 V

12 V

5.0 V

I/O

I/O to I/O

Note: Program-verify data output values may be intermediate between 1 and 0 if programming is insufficient.

Figure 19.20 Hig h- Speed, High-Reliability Programming Timing

Rev. 6.0, 09/02, page 640 of 876

Address

5.0 V

12 V

5.0 V

I/O

to I/O

Erase setup Erase Erase-verify

Valid address

Command

in Command

Valid data

out

VPS

VPH

OEWS

CWC

CES

WEP

CEH

WEH

CES

WEP

CEH

CES

WEP

CEH

OERS

Note: Erase-verify data output values may be intermediate between 1 and 0 if erasing is insufficient.

Figure 19.21 Erase Timing

Rev. 6.0, 09/02, page 641 of 876

19.8 Flash Memory Programming and Erasing Precautions (Dual-Power

Supply)

(1) Program with the specified voltages and timing.

The rated programming voltage (VPP) of the flash memory is 12.0 V.

If the PROM programmer is set to Hitachi HN2 8F101 specifications, VPP will be 12 . 0 V. App lied

voltages in excess of the rating can permanently damage the device. Insure, in particular, that peak

overshoot at the Vpp and MD2 pins does not exceed the maximu m rating of 13 V. Also, be very

careful about PROM programmer overshoot.

(2) Before programming, check that the chip is correctly mounted in the PROM

programmer. Overcurrent damage to the device can result if the index marks on the PROM

programmer socket, socket adapter, and chip are not correctly aligned.

(3) Don’t touch the socket adapter or chip while programming. Touching either of these can

cause contact faults and write errors.

(4) Precautions in turning the programming voltage (VPP) on and off (see figures 19.22 to

19.24):

• Apply the programming voltage (VPP) after the rise of VCC, when the microc ontr oller is in a

stable condition. Shut off VPP before VCC, again while th e microcontroller is in a stable

condition. If VPP is turned on or off while VCC is not within its r a ted voltage range (VCC = 2.7 to

5.5 V), since microcontroller operation is unstable and flash memory protection is not

functioning, the flash memory may be programmed or erased by mistake. This can occur even

if VCC = 0 V. The same danger of incorrect programming or erasing exists when VCC is within

its rated voltag e r a nge ( VCC = 2.7 to 5.5 V) if the clock oscillator h a s n ot stabilized, if the clock

oscillator has stopped (except in standby), or if a program runaway has occurred. After VCC

power-up, do not apply VPP until the clock oscillator has had time to settle (tOSC1 = 20 ms min)

and the microcontroller is safely in the reset state, or the reset has been cleared.

These power-on and power-off timing requirements should also be satisfied in the event of a

power failure and recovery from a power failure. If these requirements are not satisfied, the

flash memory may not only be unintentionally programmed or erased; it may be permanently

damaged.

• The VPP bit in the flash memory control register (FLMCR) is set or cleared when the V PPE bit

in FLMCR is set or clear ed while a voltage of 12.0 ± 0.6 V is being app lied to the VPP pin.

After the VPPE bit is set, it b ecomes possible to write the erase block reg ister s ( E BR1 and

EBR2) and the EV, PV, E, and P bits in FLMCR. Accordingly, program or erase flash memory

5 to 10 µs after the VPPE bit is set. VPP should be turned off only when the P, E and VPPE bits in

FLMCR are cleared. Be sure that these bits are not set by mistaken access to FLMCR.

Rev. 6.0, 09/02, page 642 of 876

tosc1

12±0.6 V

min 0 µs

MDS

min 0µs

12±0.6 V

0 to Vcc V

2.7 to 5.5 V

VppE

set VppE

cleared

min 10 ø

min 0 µs

0 to Vcc V

FRS

VPS

MD2

E bit

Programming/

erasing

possible

Period during which flash memory access is prohibited

Period during which flash memory can be rewritten

(Execution of program in flash memory prohibited, and data reads other than verify

operations prohibited)

Note: * t

VPS

: 5 to 10µs

Figure 19.22 Power-On and Power-Off Timing (Boot Mode)

Rev. 6.0, 09/02, page 643 of 876

tosc1

12±0.6 V

0 to

Vcc V

2.7 to

5.5 V

VppE

set VppE

cleared

min 0 µs

0 to

Vcc V

FRS

VPS

MD2

to 0

E bit

0 to

Vcc V

MDS

0 to

Vcc V

Programming/

erasing

possible

Period during which flash memory access is prohibited

Period during which flash memory can be rewritten

(Execution of program in flash memory prohibited, and data reads other than verify

operations prohibited)

VPS

: 5 to 10 µs

The level of the mode pins (MD2 to MD0) must be fixed from power-on to power-off

by pulling the pins up or down.

Notes: *1

Figure 19.23 Power-On and Power-Off Timing (User Program Mode)

Rev. 6.0, 09/02, page 644 of 876

tosc1

12±0.6 V

0 to

Vcc V

2.7 to

5.5 V

ppE

set

Clear

VppE

User program modeMode

switch-

ing*

Mode

switch-

ing*

Boot mode User program

mode

User

mode

User

mode

MD2

to 0

E bit

0 to

Vcc V t

MDS

12±0.6 V

min 0µs

min 0 µs min 10 ø

MDS

FRS

Programming/

erasing

possible

FRS

Programming/

erasing

possible

FRS

VPS Programming/

erasing

possible

FRS

VPS Programming/

erasing

possible

VPS

Period during which flash memory access is prohibited

Period during which flash memory can be rewritten

(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)

Notes: When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried

out by means of input. The pin output states change during this switchover interval (the interval during which

the pin is low), and therefore these pins should not be used as output signals during this time.

When making a transition from boot mode to another mode, the flash memory read setup time t

FRS

and

mode programming setup time t

MDS

must be satisfied with respect to RES clearance timing.

VppE

cleared

Figure 19.24 Mode Transition Timing

(Example: Boot Mode →

→→

→ User Mode ↔

↔↔

↔ User Program Mode)

Rev. 6.0, 09/02, page 645 of 876

(5) Do not apply 12 V to the V PP pin during normal operatio n. To prevent microcontroller

errors caused by accidental programming or erasing, apply 12 V to VPP only when the flash

memory is programmed or erased, or when flash memory is emulated by RAM. While 12 V is

applied, the watchdog timer should be running and enabled to halt runaway program execution, so

that program runa way will not lead to overprogramming or overerasin g.

(6) Disable watchdog-timer reset output (RESO

RESORESO

RESO) while the programming voltage (VPP) is

turned on. If 12 V is applied during watchdog timer reset output (while the RESO pin is low),

overcurrent flow will permanently destroy the reset output circuit. The watchdog timers reset

output enable bit (RSTOE) should not be set to 1.

If a pull-up r e sisto r is externally attached to th e VPP/RESO pin, a diode is necessary to prevent

reverse current from flowing to VCC when VPP is applied (figure 19.25).

(7) If the watchdog timer generates a reset output signal when 12 V is not applied, the rise

and fall of t he reset output waveform will be delay ed by any decoupling capacitors

connected to the VPP pin.

0.01 µF1.0 µF

+12 V V /

H8/3048F

(dual-power supply)

+5 V Pull-up resistor and

a diode

Figure 19.25 VPP Power Supply Circuit Design (Example)

Rev. 6.0, 09/02, page 646 of 876

(8) Notes concerning mounting board development—handling of VPP and mode MD2 pins

1. The standard 12 V high voltage is applied to the VPP and mode MD2 pins when erasing or

programming flash memory. The voltage at these pins also includes oversh oot and noise, and

the following points should be noted to ensure that the 13 V maximum rated voltage is not

exceeded.

a. Bypass capacitors should be inserted to eliminate overshoot and noise. These should be

positioned as close as possible to the chip’s VPP and mode MD2 pins.

1.0 µF: Stabilizes fluctuations in the low-frequency components, such as power supply

ripple.

0.01 µF: Bypasses high-frequency components such as induction noise.

b. The VPP and mode MD2 pin wiring should be kept as short as possible to suppress

induction noise. When designing a new board, in particular, noise may be increased by

jumper wires, etc. In this case too, the power supply waveform should be monitored and

measures taken to prevent the maximum rating from being exceeded.

c. The maximum rated voltage is based on the potential of th e VSS pin. If the potential of this

pin oscillates due to current fluctuations, etc., the voltage of the VPP and mode MD2 pins

may reciprocally exceed the maximu m rated voltage. Careful attention must therefore be

paid to stabilizing the reference potential.

Note: When the user system’s 12 V power supply is connected, attention must be paid to the

current capacity. A power supply with a small current capacity will not be able to

handle flu ctuations in the chip’s operating voltag e, resulting in voltage drops and rises

or oscillation that may make it impossible to obtain the rated operating voltage. If the

power supply has a large current capacity, or if the 12 V voltage is turn ed on abruptly

by means of a switch, etc., caution is required since a voltage exceeding the maximum

rating may be generated due to the inductance component of the power supply wiring

or the power supply characteristics.

Before using the power supp ly, check the power supply waveform to ensure that the

above problems will not arise.

Rev. 6.0, 09/02, page 647 of 876

2. 12 V is applied to the VPP and mode MD2 pins when programming or erasing flash memory.

When these pins are pulled up to the VCC line in normal operation, diodes should be inserted to

prevent reverse current from flowing to the VCC line when 12 V is applied.

Note: In normal operation, if the mode MD2 pin to which 12 V is applied is to be set to 0, it

should be pulled down with a resistor.

A sample circuit is shown figure 19.26.

H8/3048F

(dual-

power

supply)

MD2

0.01 µF 1.0 µF

12 V

mode

Adapter board User system

Mode pin

Figure 19.26 Example of Mounting Board Design for the H8/3048F-ZTAT with the Dual-

Power Supply

(Connection to Adapter Board—When VPP Pin and Mode Pin Sett ings Are 1)

(9) Do not set or clear the VppE bit during execution of a program in flash memory.

Flash memory data cannot be read normally when the VppE bit is set or cleared. After the VppE

bit is cleared, flash m emory data can be rewritten after waiting for the elapse of the Vpp enable

setup time (tVPS: 5 10 µs), but flash memory cannot be accessed for purposes other than verification

(verification dur ing p rog ramming, erasing, or prewriting). Af ter the VppE is cleared, wait for the

elapse of the flash memory read setup time before performing program execution and data reading

in flash memory.

(10) Do not use interrupts while programming or erasing flash memory.

When Vpp is applied, disable all interrupt requests, in cluding NMI, to give the programming or

erase operation (including RAM emulation) the highest priority.

Rev. 6.0, 09/02, page 648 of 876

(11) The Vpp flag is set and cleared by a threshold decision on the voltage applied to the

Vpp pin. The threshold level is approximately in the range from Vcc +2 V to 11.4 V.

When this flag is set, it becomes possib le to write to the flash memor y control register (FLMCR)

and the erase block registers (EBR1 and EBR2), even though the Vpp voltage may not yet have

reached the programming voltage range of 12.0 V ±0.6 V. Do not actually program or erase the

flash memory until Vpp has reached the programming voltage range.

The programming voltage range for programming and erasing flash memory is 12.0 V ±0.6 V

(11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this range.

When not programming or erasing the flash memory, ensure that the Vpp vo ltage does not exceed

the Vcc voltage. This will p r event unintentional progra m ming and erasing.

(12) After the Vpp enable bit (VppE) is cleared, the flash memory read setup time (tFRS)*

must elapse before the flash memory is read.

When switching from boot mode or user program mode to normal mode (Vpp ≠ 12 V, MD2 ≠ 12

V), this setup tim e is r e q uired as the period from VppE bit clearance until the flash memory is

read.

When switching from boot mode to another mode, a mode programming setup time (tMDS) is

required with respect to the RES release timing.

Note: * The f lash memory read setup time stipulates the interval before flash m emory is read after

the VppE bit is cleared (figure 19.24). Also, when using an external clock (EXTAL input),

after powering on and when returning from standby mode, the flash memory read setup

time must elapse before the flash memory is read.

Rev. 6.0, 09/02, page 649 of 876

19.9 Notes when Converting the F-ZTAT (Dual-Power Supply)

Application Software to the Mask-ROM Versions

Please note the following when converting the F-ZTAT (dual-power supply) application software

to the mask-ROM versions.

The values read from the internal registers (refer to appendix B, Internal I/O Register, Table B.1)

for the flash ROM of the mask-ROM version and F-ZTAT (dual-power supply) version differ as

follows.

Status

Version Mask-ROM Version

FLMCR VPP 0: Application software running

1: Programming 0: Not read out

1: Application software running

Note: This difference applies to all the F-ZTAT (dual-power supply) versions and all the ma sk-

ROM versions that have different ROM size.

Rev. 6.0, 09/02, page 650 of 876

Rev. 6.0, 09/02, page 651 of 876

Section 20 Clock Pulse Generator

20.1 Overview

The H8/3048 Series has a built-in clock pulse generator (CPG) that ge nerates the system clock (φ)

and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides

the clock frequency to generate the sy stem clock (φ). The system clock is output at the φ pin*1 and

furnished as a master clock to prescalers that supply clock signals to the on-chip supporting

modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency

divider by settings in a division control register (DIVCR). Power consumption in the chip is

reduced in almost direct proportion to the frequency division ratio*2.

Notes: *1 Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit

setting in the module standby control register (MSTCR). For details, see section 21.7,

System Clock Output Disabling Function.

*2 The division ratio of the frequency divider can be changed dynamically during

operation. The clock output at the φ pin also changes when the division ratio is

changed. The frequency output at the φ pin is shown below.

φ = EXTAL × n

where, EXTAL: Frequency of crystal resonator or external clock signal

n: Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)

Rev. 6.0, 09/02, page 652 of 876

20.1.1 Block Diagram

Figure 20.1 shows a block diagram of the clock pulse generator.

XTAL

EXTAL

CPG

φ φ/2 to φ/4096

Oscillator Duty

adjustment

circuit Frequency

divider

Division

control

Prescalers

Data bus

Figure 20.1 Block Diagram of Clock Pulse Generator

Rev. 6.0, 09/02, page 653 of 876

20.2 Oscillator Circuit

Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock

signal.

20.2.1 Connecting a Crystal Resonator

Circuit Configura tion: A crystal resonator can be connected as in the example in figure 20.2.

The damping resistance Rd should be selected according to table 20.1. An AT-cut parallel-

resonance crystal should be used.

EXTAL

XTAL

Rd CL1 = CL2 = 10 pF to 22 pF

Figure 20.2 Connection of Crystal Resonator (Example)

In order to improv e the accuracy of the oscillation frequency, a thorough study of oscillation

matching evaluation, etc., should be carried out when deciding the circuit constants.

Table 20.1 Damping Resistance Value

Frequency f (MHz)

Damping Resistance

Value 2 2 <

< f ≤

≤≤

≤ 44 <

< f ≤

≤≤

≤ 88 <

< f ≤

≤≤

≤ 10 10 <

< f ≤

≤≤

≤ 13 13 <

< f ≤

≤≤

≤ 16 16 <

< f ≤

≤≤

≤ 18

For products

listed below*1 k5002000000

(Ω)

H8/3048F 1 k 1 k 500 200 100 0 —

Note: A crystal resonator between 2 MHz and 18 MHz can be used. If the chip is to be operated

at less than 2 MHz, the on-chip frequency divider should be used. (A crystal resonator of

less than 2 MHz cannot be used.)

*H8/3048ZTAT, H8/3048 mask-ROM, H8/3047 mask-ROM, H8/3045 mask-ROM,

H8/3044 mask-ROM

Rev. 6.0, 09/02, page 654 of 876

Crystal Resonator: Figure 20.3 shows an equivalent circuit of the crystal resonator. The crystal

resonato r should have the characteristics listed in table 20.2.

XTAL

LRs

EXTAL

AT-cut parallel-resonance type

Figure 20.3 Crystal Resonator Equivalent Circuit

Table 20.2 Crystal Resonator Parameters

Frequency (MHz) 2 4 8 10 12 16 18

Rs max (Ω

ΩΩ

Ω)500 120 80 70 60 50 40

C0 max (pF) 7

Use a crystal resonator with a frequency equal to the system clock frequ ency (φ).

Notes on Board Design: When a crystal resonator is connected, the following points should be

noted:

Other signal lines should be routed away from the oscillator circuit to prevent induction from

interfering with correct oscillation. See figure 20.4.

When the board is designed, the crystal resonator and its load capacitors should be placed as close

as possible to the XTAL and EXTAL pins.

Rev. 6.0, 09/02, page 655 of 876

XTAL

EXTAL

H8/3048 Series

Avoid Signal A Signal B

Figure 20.4 Example of Incorrect Board Design

20.2.2 External Clock Input

Circuit Configura tion: An external clock signal can be input as shown in the examples in figure

20.5. The extern al clock is input from the EXTAL pin. If the XTAL pin is left open, the stray

capacitance should not exceed 10 pF. If the stray capacitance at the XTAL pin exceeds 10 pF in

configuration a, use configuration b instead and hold the clock high in standby mode.

EXTAL

XTAL

EXTAL

XTAL

External clock input

Open

74HC04

External clock input

a. XTAL pin left open

b. Complementary clock input at XTAL pin

Figure 20.5 External Clock Input (Exa mples)

Rev. 6.0, 09/02, page 656 of 876

External Clock: The external clock frequency should be equal to the system clock frequency (φ)

when not divided by the on-chip frequency divider. Table 20.3, figures 20.6 and 20.7 indicate the

clock timing.

When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the

on-chip oscillator and duty adjustment circuit. The r esulting stable clock is output to external

devices after the external clock settling time ( tDEXT) has passed after the clock input. The system

must rema in reset with the reset sig nal low during tDEXT, while the clock ou tput is u nstable.

Table 20.3 Clock Timing

VCC =

2.7 V to 5.5 V VCC =

5.0 V ± 10%

Item Symbol Min Max Min Max Unit Test Conditions

External clock

input low pulse

width

tEXL 40 — 20 — ns Figure 20.6

External clock

input high pulse

width

tEXH 40 — 20 — ns

External clock

rise time tEXr —10 —5 ns

External clock

fall time tEXf —10 —5 ns

0.4 0.6 0.4 0.6 tcyc φ ≥ 5 MHz

Clock low pulse

width tCL 80 — 80 — ns φ < 5 MHz

0.4 0.6 0.4 0.6 tcyc φ ≥ 5 MHz

Clock high pulse

width tCH 80 — 80 — ns φ < 5 MHz

Figure

22.7

External clock

output settling

delay time

tDEXT*500 — 500 — µs Figure 20.7

Note: * tDEXT includes 10 tcyc of RES (tRESW).

Rev. 6.0, 09/02, page 657 of 876

EXTAL

tEXr tEXf

VCC × 0.7

0.3 V

tEXH tEXL

VCC × 0.5

Figure 20. 6 External Clock Input Timing

VCC

EXTAL

φ (internal or

external)

tDEXT

VIH

Figure 20.7 External Clock Output Settling Delay Timing

20.3 Duty Adjustment Circuit

When the oscillato r f requency is 5 MHz or higher, the duty adjustment circuit adjusts the duty

cycle of the clock signal from the oscillator to generate the signal that becom e s the system clock.

20.4 Prescalers

The prescalers divide the system clock (φ) to generate internal clocks ( φ/2 to φ/4096).

Rev. 6.0, 09/02, page 658 of 876

20.5 Frequency Divider

The frequency divider divides the duty-adjusted clock signal to generate the system clock ( φ). The

frequency division ratio can be changed dynamically by modifying the value in DIVCR, as

described below. Po wer consumption in the chip is reduced in almost direct proportion to the

frequency division ratio. The system clock generated by the frequency divider can be output at the

φ pin.

20.5.1 Register Configuration

Table 20.4 summarizes the frequency division register.

Table 20.4 Frequency Division Register

Address*Name Abbreviation R/W Initial Value

H'FF5D Division control register DIVCR R/W H'FC

Note: * The lower 16 bits of the address are shown.

20.5.2 Division Control Reg ister (DIVCR)

DIVCR is an 8- bit readable/writable register that selects the division r a tio of the frequency

divider.

Bit

Initial value

Read/Write

—

DIV0

R/W

—

DIV1

R/W

Reserved bits Divide bits 1 and 0

These bits select the

frequency division ratio

DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is n ot initialized in

software standby mode.

Bits 7 to 2—Reserved: Read-only bits, always read as 1.

Rev. 6.0, 09/02, page 659 of 876

Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as

follows.

Bit 1: DIV1 Bit 0: DIV0 Frequency Division Ratio

0 0 1/1 (Initial val ue)

11/2

101/4

11/8

20.5.3 Usage Notes

The DIVCR setting changes the φ frequency, so note the following points.

• Select a frequency division ratio that stays within the assured operation range specified for the

clock cycle time tcyc in the AC electrical characteristics. Note that φMIN must be in the lower

limit of the clock frequency range. Avoid settings that give system clock frequencies less than

the lower limit.

Table 20.5 shows the comparison with the clock frequency range for each version.

Table 20.5 Comparison with the Clock Frequency Ranges in the H8/3048 Series

ROM type F-ZTAT ZTAT Mask ROM

Product type H8/3048F H8/3048 H8/3048

Mask ROM

Version

H8/3047

Mask ROM

Version

H8/3045

Mask ROM

Version

H8/3044

Mask ROM

Version

4.5–5.5 V 1–16 MHz 1–18 MHz 1–18 MHz

3.15–5.5 V — 1–13 MHz 1–13 MHz

Guaranteed

clock

frequency

range 2.7–5.5 V 1–8 MHz 1–8 M Hz 1–8 M Hz

Crystal oscillation range 2–16 MHz 2–18 M Hz 2–18 MHz

• All on-chip module operations are based on φ. Note that th e timing of timer operations, serial

communication, and other time-dependent processing differs before and after any change in

the division ratio. The waiting time for exit from software standby mode also changes when

the division ratio is changed. For details, see section 21.4.3, Selection of Waiting Time for Exit

from Software Standby Mode.

Rev. 6.0, 09/02, page 660 of 876

Rev. 6.0, 09/02, page 661 of 876

Section 21 Power-Down State

21.1 Overview

The H8/3048 Series has a power-down state that greatly reduces power consumption by halting

the CPU, and a module standby function that reduces power consumption by selectively halting

on-chip mo du les.

The power-down state includes the following three modes:

• Sleep mode

• Software standby mode

• Hardware standby mode

The module standby function can halt on-chip supporting modules independently of the power-

down state. The modules that can be halted are the ITU, SCI0, SCI1, DMAC, refresh controller,

and A/D converter.

Table 21.1 indicates the methods of entering and exiting the power-down modes and module

standby mode, and gives the status of the CPU and on-chip supporting modules in each mode.

Rev. 6.0, 09/02, page 662 of 876

Table 21.1 Power-Down State a nd Module Standby Function

Mode Entering

Conditions Clock CPU CPU

Registers DMAC Refresh

Controller ITU SCI0 SCI1 A/D Other

Modules RAM φ Clock

Output

State

I/O Ports Exiting

Conditions

Sleep

mode SLEEP

instruction

executed

while

SSBY = 0

in SYSCR

Active Halted Held Active Active Active Active Active Active Active Held φ output Held • Interrupt

•

Software

standby

mode

SLEEP

instruction

executed

while

SSBY = 1

in SYSCR

Halted Halted Held Halted

and

reset

Halted

and

held

Halted

and

reset

Halted

and

reset

Halted

and

reset

Halted

and

reset

Halted

and

reset

Held High

output Held • NMI

•

Hardware

standby

mode

Low input at

STBY pin Halted Halted Undeter-

mined Halted

and

reset

Halted

and

reset

Halted

and

reset

Halted

and

reset

Halted

and

reset

Halted

and

reset

Halted

and

reset

Held

High

impedance High

impedance •

•

Module

standby Corresponding

bit set to 1 in

MSTCR

Active Active — Halted

and

reset

Halted

and

held

Halted

and

reset

Halted

and

reset

Halted

and

reset

Halted

and

reset

Active — —High

impedance

•

• Clear MSTCR

bit to 0

Notes: *1 RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their previous states.

*2 State in which the corresponding MSTCR bit was set to 1. For details see section 21.2.2, Module Standby Control Register (MSTCR).

*3 The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.

*4 When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR bit to 0, then set

up the module registers again.

Legend

SYSCR: System control register

SSBY: Software standby bit

MSTCR: Module standby control register

Rev. 6.0, 09/02, page 663 of 876

21.2 Register Configuration

The H8/3048 Series has a system control register (SYSCR) that controls the power-down state,

and a module standby control register (MSTCR) that controls the module standby function. Table

21.2 summarizes these registers.

Table 21.2 Control Register

Address*Name Abbreviation R/W Initial Value

H'FFF2 System control regi ster SYSCR R/W H'0B

H'FF5E Module standby control register MSTCR R/W H'40

Note: * Lower 16 bits of the address.

21.2.1 System Control Register (SYSCR)

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

—

Software standby

Enables transition to

software standby mode

RAM enable

Standby timer select 2 to 0

These bits select the

waiting time at exit from

software standby mode

User bit enable

NMI edge select

Reserved bit

SYSCR is an 8-bit readable/writable r e gister. Bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0) con trol

the power-down state. For information on the other SYSCR bits, see section 3.3, System Control

Rev. 6.0, 09/02, page 664 of 876

Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software

standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal

operation. To clear this bit, write 0 .

Bit 7: SSBY Description

0 SLEEP instruction causes transition to sleep mode (Initial value)

1 SLEEP instruction causes transition to software s tandby mode

Bits 6 to 4 —St andby Timer Select (STS2 to STS0): These bits select the len gth of time the CPU

and on-chip supporting modules wait for the clock to settle when software standby mode is exited

by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to

the clock freque ncy so that the waiting time will be at least 7 ms. See tab le 2 1.3. If an external

clock is used, any value may be selected.

Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description

0 0 0 Waiting time = 8,192 states (Initial value)

1 Waiting ti me = 16,384 states

1 0 Waiting time = 32,768 states

1 Waiting ti me = 65,536 states

1 0 0 Waiting time = 131,072 states

1 Waiting ti me = 1,024 states

1 — Illegal sett ing

Rev. 6.0, 09/02, page 665 of 876

21.2.2 Module Standby Control Register (MSTCR)

MSTCR is an 8-bit readable/writable register that controls output of the system clock (φ). It also

controls the module standby function, which places individual on-chip supporting modules in the

standby state. Module standby can be designated for the ITU, SCI0, SCI1, DMAC, refresh

controller, and A/D converter modules.

Bit

Initial value

Read/Write

PSTOP

R/W

—

MSTOP5

R/W

MSTOP4

R/W

MSTOP3

R/W

MSTOP0

R/W

MSTOP2

R/W

MSTOP1

R/W

ø clock stop

Enables or disables

output of the system clock

Module standby 5 to 0

These bits select modules

to be placed in standby

Reserved bit

MSTCR is initialized to H'40 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—φ

φφ

φ Clock Stop (P STOP): Enables or disables output of the system clock (φ).

Bit 1: PSTOP Description

0 System clo ck outp ut is enab led (Initial val ue)

1 System clo ck outp ut is disa bled

Bit 6—Reserved: Read-only bit, always read as 1.

Bit 5—Module Standby 5 (MSTOP5): Selects whether to place the ITU in standby.

Bit 5: MSTOP5 Description

0 ITU operates normally (Initial value)

1 ITU is in standby state

Rev. 6.0, 09/02, page 666 of 876

Bit 4—Module Standby 4 (MSTOP4): Selects whether to place SCI0 in standby.

Bit 4: MSTOP4 Description

0 SCI0 operates normally (Initial value)

1 SCI0 is in standb y state

Bit 3—Module Standby 3 (MSTOP3): Selects whether to place SCI1 in standby.

Bit 3: MSTOP3 Description

0 SCI1 operates normally (Initial value)

1 SCI1 is in standb y state

Bit 2—Module Standby 2 (MSTOP2): Selects whether to place the DMAC in standby.

Bit 2: MSTOP2 Description

0 DMAC operates normally (Initial value)

1 DMAC is in standby state

Bit 1—Module Standby 1 (MSTOP1): Selects whether to place the refresh controller in standby.

Bit 1: MSTOP1 Description

0 Refresh controller operates normally (Initial value)

1 Refresh control ler is in stan dby state

Bit 0—Module Standby 0 (MSTOP0): Selects whether to place the A/D converter in standby.

Bit 0: MSTOP0 Description

0 A/D converter operates normally (Initial value)

1 A/D converter is in standby state

Rev. 6.0, 09/02, page 667 of 876

21.3 Sleep Mode

21.3.1 Transition to Sleep Mode

When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a

transition from the program execution state to sleep mode. Immediately after executing the SLEEP

instruction the CPU halts, but the contents o f its internal registers are retain ed. The DMA

controller (DMAC), refresh controller, and on-chip supporting modules do not halt in sleep mode.

Modules which have been placed in standby by the module standby function, however, remain

halted.

21.3.2 Exit from Sleep Mode

Sleep mode is exited by an interrupt, or by input at the RES or STBY pin.

Exit by Interrupt: An interrup t ter minates sleep mode and causes a transition to the interrupt

exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting

module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by

an interrupt other than NMI if the interrupt is masked by the I and UI bits in CCR and IPR.

Exit by RES

RESRES

RES Input: Low input at the RES pin exits from sleep mode to the reset state.

Exit by STBY

STBYSTBY

STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby

mode.

21.4 Software Standby Mode

21.4.1 Transition to Software Standby Mode

To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in

SYSCR.

In software standby mode, current dissipation is reduced to an extremely low level because the

CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting modules

are reset. As long as the specified voltage is supplied, however, CPU register contents and on-chip

RAM data are retained. The settings of the I/O ports and refresh controller* are also held.

Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized . Oth e r bits and registers hold their

previous states.

When the WDT is used as a watchdog timer (WT/IT = 1), the TME bit must be cleared to 0 before

setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0.

Rev. 6.0, 09/02, page 668 of 876

Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software

standby mode.

21.4.2 Exit from Software Standby Mode

Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or

IRQ2 pin, or by input at the RES or STBY pin.

Exit by Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is received, the

clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0

in SYSCR, stable clock signals are supplied to the entire chip, so ftware standby mode ends, and

interrupt exception handling begins. Software standby mode is not exited if the interrupt enable

bits of interrupts IRQ0, IRQ1, and IRQ2 are cleared to 0, or if these interrupts are masked in the

CPU.

Exit by RES

RESRES

RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are

supplied im mediately to the entire chip. The RES signal must be held low long enough for the

clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.

Exit by STBY

STBYSTBY

STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.

21.4.3 Selection of Waiting Time for Exit from Software Standby Mode

Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.

Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so th at the waiting time (for the clock to

stabilize) is at least 7 ms. Table 21.3 indicates the waiting times that are selected by STS2 to

STS0, DIV1, and DIV0 settings at various system clock frequencies. Refer to table 21.3 for the

operating frequency and the waiting time needed for th e oscillator to settle.

External Clock: Any values may be set.

Rev. 6.0, 09/02, page 669 of 876

Table 21.3 Clock Frequency and Waiting Time for Clock to Settle

DIV1 DI V0 STS 2 STS1 S TS 0 W aiti n g Tim e 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MH z 1 MHz Unit

0 0 0 0 0 8192 states 0.46 0.51 0.65 0.8 1.0 1.3 2.0 4.1 8.2*ms

0 0 1 163 84 stat es 0.91 1.0 1.3 1.6 2.0 2.7 4.1 8.2*16.4

0 1 0 327 68 stat es 1.8 2.0 2.7 3.3 4.1 5.5 8.2*16.4 32.8

0 1 1 655 36 stat es 3.6 4.1 5.5 6.6 8.2*10.9*16.4 32.8 65.5

1 0 0 131072 states 7.3*8.2*10.9*13.1*16.4 21.8 32.8 65.5 131.1

1 0 1 1024 states 0.057 0.064 0.085 0.10 0.13 0.17 0.26 0.51 1.0

1 1 — Illegal setting

0 1 0 0 0 8192 states 0.91 1.02 1.4 1.6 2.0 2.7 4.0 8.2*16.4*ms

0 0 1 163 84 stat es 1.8 2.0 2.7 3.3 4.1 5.5 8.2*16.4 32.8

0 1 0 327 68 stat es 3.6 4.1 5.5 6.6 8.2*10.9*16.4 32.8 65.5

0 1 1 655 36 stat es 7.3*8.2*10.9*13.1*16.4 21.8 32.8 65.5 131.1

1 0 0 131072 states 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1

1 0 1 1024 states 0.11 0.13 0.17 0.20 0.26 0.34 0.51 1.0 2.0

1 1 — Illegal setting

1 0 0 0 0 8192 states 1.8 2.0 2.7 3.3 4.1 5.5 8.2*16.4*32.8*ms

0 0 1 163 84 stat es 3.6 4.1 5.5 6.6 8.2*10.9*16.4 32.8 65.5

0 1 0 327 68 stat es 7.3*8.2*10.9*13.1*16.4 21.8 32.8 65.5 131.1

0 1 1 655 36 stat es 14.6 16.4 21.8 26. 2 32.8 43.7 65. 5 131.1 262.1

1 0 0 131072 states 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3

1 0 1 1024 states 0.23 0.26 0.34 0.41 0.51 0.68 1.02 2.0 4.1

1 1 — Illegal setting

1 1 0 0 0 8192 states 3.6 4.1 5.5 6.6 8.2*10.9*16.4*32.8*65.5 ms

0 0 1 163 84 stat es 7.3*8.2*10.9*13.1*16.4 21.8 32.8 65.5 131.1

0 1 0 327 68 stat es 14.6 16.4 21.8 26. 2 32.8 43.7 65. 5 131.1 262.1

0 1 1 655 36 stat es 29.1 32.8 43.7 52. 4 65.5 87.4 131 .1 262.1 524.3

1 0 0 131072 states 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1048.6

1 0 1 1024 states 0.46 0.51 0.68 0.82 1.0 1.4 2.0 4.1 8.2

1 1 — Illegal setting

*: Recommended setting

Rev. 6.0, 09/02, page 670 of 876

21.4.4 Sample Applicat ion of Software Standby Mode

Figure 21.1 shows an example in which software standby mode is entered at the fall of NMI and

exited at the rise of NMI.

With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an

NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit

is set to 1; then the SLEEP instruction is executed to enter software standby mode.

Software standby mode is exited at the next rising edge of the NMI signal.

NMI

NMIEG

SSBY

NMI interrupt

handler

NMIEG = 1

SSBY = 1

Software standby

mode (power-

down state)

Oscillator

settling time

osc2

)

SLEEP

instruction

NMI exception

handling

Clock

oscillator

Figure 21.1 NMI Timing for Sof t ware Standby Mode (Ex ample)

21.4.5 Note

The I/O ports retain their existing states in software standby mode. If a port is in the high output

state, its output cu r rent is not reduced.

Rev. 6.0, 09/02, page 671 of 876

21.5 Hardware Standby Mode

21.5.1 Transition to Hardware Standby Mode

Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin

goes low. Hardware standby mode redu ces power consumption drastically by halting all functions

of the CPU, DMAC, refresh controller, and on-chip supporting modules. All modules are reset

except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is

retained. I/O ports are placed in the high-impedance state.

Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data.

The inputs at th e mode pins (MD2 to MD0) should not be changed during hardware standby

mode.

21.5.2 Exit from H ardware Standby Mo de

Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when

STBY goes high, the clock oscillator starts running. RES should be held low long enough for the

clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a

transition to the program execution state.

21.5.3 Timing fo r Hardware Standby Mode

Figure 21.2 shows the timing relationships for hardware standby mode. To enter hardware standby

mode, first drive RES low, then driv e STBY low. To exit hardware standby mode, first drive

STBY high , wait f or the clock to settle, then brin g RES from low to high.

Rev. 6.0, 09/02, page 672 of 876

Clock

oscillator

Oscillator

settling time

Reset

exception

handling

Figure 21.2 Hardware Standby Mode Timing

21.6 Module Standby Function

21.6.1 Module Standby Timing

The module standby function can halt several of the on-chip supporting modules (the ITU, SCI0,

SCI1, DMAC, refresh controller, and A/D converter) independently of the power-down state. This

standby function is controlled by bits MSTOP5 to MSTOP0 in MSTCR. When one of these bits is

set to 1, the corresponding on-chip supporting module is placed in standby and halts at the

beginning of the next bus cycle after the MSTCR write cycle.

21.6.2 Read/Write in Module Standby

When an on-chip supporting module is in module standby, read/write access to its registers is

disabled. Read access always results in H'FF data. Write access is ignored.

Rev. 6.0, 09/02, page 673 of 876

21.6.3 Usage Notes

When using the module standby function, note the following points.

DMAC and Refresh Controller: When setting bit MSTOP2 or MSTOP1 to 1 to place the

DMAC or refresh controller in module standby, make sure that the DMAC or refresh controller is

not currently requesting the bus right. If bit MSTOP2 or MSTOP1 is set to 1 when a bus request is

present, operation of the bus arbiter becomes ambiguous and a malfunction may occur.

Internal Peripheral Module Interrupt: When MSTCR is set to “1”, p revent module interrupt in

advance. When an on-chip supporting module is placed in standby by the module standby

function, its registers, including the interrupt flag, are initialized.

Pin States: Pins used by an on-chip supporting module lose their module functions when the

module is placed in module standby. Wh at happens after that depends on the particular pin. For

details, see section 9, I/O Ports. Pins that change from the input to the output state require special

care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data

function and becomes a generic I/O pin. If its data direction bit is set to 1, the pin becomes a data

output pin, and its output may collide with external serial data. Data collisions should be prevented

by clearing the data direction bit to 0 or taking other appropriate action.

function , all its reg ister s ar e initialized. To restart the m odu le, af ter its MSTCR bit is cleared to 0,

its registers mu st be set up again. It is not possible to write to the registers while the MSTCR bit is

set to 1.

MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed

from the CPU. I t can be read by the DMAC, but it cannot be written by the DMAC.

Rev. 6.0, 09/02, page 674 of 876

21.7 System Clock Output Disabling Function

Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCR. When the PSTOP

bit is set to 1, output of the system clock halts and the φ pin is placed in the high-impedance state.

Figure 21.3 shows the timing of the stopping and starting of system clock output. When the

PSTOP bit is cleared to 0, output of the system clock is enabled. Table 21.4 indicates the state of

the φ pin in various operating states.

T1 T2

(PSTOP = 1)

T3 T1 T2

(PSTOP = 0)

MSTCR write cycle MSTCR write cycle

High impedance

φ pin

Figure 21. 3 Starting and Stopping of System Clock O utput

Table 21.4 φ

φφ

φ Pin State in Various Operating States

Operating State PSTOP = 0 PSTOP = 1

Hardware standby High impedance High impedance

Software standby Always high High impedance

Sleep mode System clo ck outp ut High impedance

Normal operatio n System clock outp ut High impedance

Rev. 6.0, 09/02, page 675 of 876

Section 22 Electrical Characteristics

Table 22.1 shows the electrical characteristics of the various products in the H8/3048 Series.

Table 22.1 Electrical Characteristics of H8/3048 Series Products

Item Symbol Unit

H8/3048

F-ZTAT

(Dual Power

Supply)

H8/3048

H8/3047

H8/3045

H8/3044

H8/3048

ZTAT

H8/3048

F-ONE

(Single Power

Supply)*5

VCC = 4.5 to 5.5 V MHz 1 to 16 1 to 18 1 to 18 2 t o 25

VCC = 3.15 to 5.5 V — 1 to 13 1 to 13 —

VCC = 2.7 to 5.5 V 1 to 8 1 to 8 1 to 8 —

Operating

range

VCC = 3.0 to 3.6 V — — — 2 to 25

Regular

specifications Topr °C –20 to +75 –20 to +75 –20 to +75 –20 to +75*1

Operating

temperature

range Wide-range

specifications –40 to +85 –40 t o +85 –40 to +85 –40 to +85*1

VPP pin rating Vin Yes — Yes —

FWE pin rating — — — Yes

Absolute

maximum

ratings VCL pin — — — Cannot be

connected

to power

supply*2

(5 V operation

model only)

Power supply

voltage Vin V –0. 3 t o +7.0 –0.3 to +7.0 –0.3 to +7.0 –0.3 to +7.0

(5 V operation

model)

–0.3 to +4.6

(3 V operation

model)

DC charac-

teristics RESO pin

specification Yes Yes Yes —

FWE pin

specification ——— Yes

Determination

level for applying

high voltage (12 V)

Yes — — —

Standby current

(Ta ≤ 50°C) ICC*3µA M ax 5 Max 5 Max 5 Max 10

Standby current

(50°C < Ta)Max 20 Max 20 Max 20 Max 80

Rev. 6.0, 09/02, page 676 of 876

Item Symbol Unit

H8/3048

F-ZTAT

(Dual Power

Supply)

H8/3048

H8/3047

H8/3045

H8/3044

H8/3048

ZTAT

H8/3048

F-ONE

(Single Power

Supply)*5

Clock cycle time tcyc ns Max 1000 Max 1000 Max 1000 Max 500

RES pulse width tRESW tcyc Mi n 10 Mi n 10 Min 10 Min 20

RESO output

delay time tRESD ns Max 100 Max 100 Max 100 —

AC charac-

teristics

RESO output

pulse width tRESOW tcyc Min 132 Min 132 Min 132 —

Flash

memory

charac-

teristics*4

Other wait times See table

22.20 — — See tabl e

21.11

Notes: *1 The operating temperature range for flash memory programming/erasing is 0°C to +75°.

*2 Connect an external capacitor between the VCL pin and GND.

*3 See the DC Characteristics table for current dissipation during operation.

*4 Refer to the program/erase algorithms for details of flash memory characteristics.

*5 Refer to the H8/3048F-ONE Hardware Manual (Rev. 1.0) for details.

Rev. 6.0, 09/02, page 677 of 876

22.1 Electrical Characteristics for H8/3048 ZTAT (PROM) and On-Chip

Mask ROM Versions

Target product types: H8/3048 ZTAT, H8/3048 mask-ROM, H8/3047 mask-ROM,

H8/3045 mask-ROM, H8/3044 mask-ROM

22.1.1 Absolute Maximum Ratings

Table 22.2 lists the ab solute maximum ratings.

Table 22.2 Absolute Maximum Ratings

Item Symbol Value Unit

Power supply voltage VCC –0.3 to +7.0 V

Programming voltage (H8/3048 ZTAT) VPP –0.3 to +13.5 V

Input voltage (except for port 7) Vin –0.3 to VCC + 0.3 V

Input voltage (port 7) Vin –0.3 to AVCC + 0.3 V

Reference volt age VREF –0.3 to AVCC + 0.3 V

Analog power supply voltage AVCC –0.3 to +7.0 V

Analog input voltage VAN –0.3 to AVCC + 0.3 V

Operating temperature Topr Regular specifications: –20 to +75 °C

Wide-range specifications: –40 to +85 °C

Storage temperature Tstg –55 to +125 °C

Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.

Particularly, insure that peak overshoot at the VPP pin does not exceed 13 V.

Rev. 6.0, 09/02, page 678 of 876

22.1.2 DC Characteristics

Table 22.3 lists the DC characteristics. Table 22.4 lists the permissible output currents.

Table 22.3 DC Characteristics (1)

Conditions: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,

VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-rang e specifications)

Item Symbol Min Typ Max Unit Test Conditions

VT–1.0 — — V

VT+——V

CC × 0.7 V

Schmitt

trigger input

voltages

Port A,

P82 to P80,

PB3 to PB0VT+ – VT–0.4 — — V

RES, STBY,

NMI,

MD2 to MD0

VCC – 0.7 — VCC + 0.3 V

EXTAL VCC × 0.7 — VCC + 0.3 V

Port 7 2.0 — AVCC + 0.3 V

Input high

voltage

Ports 1 to 6, 9,

P83, P84, PB4 to

PB7

VIH

2.0 — VCC + 0.3 V

RES, STBY,

MD2 to MD0

–0.3 — 0.5 VInput low

voltage NMI, EXTAL,

ports 1 to 7, 9,

P84, P83, PB7 to

PB4

VIL

–0.3 — 0.8 V

VCC – 0.5 — — V IOH = –200 µAOutput high

voltage All output pins

(except RESO)VOH 3.5 — — V IOH = –1 mA

All output pins

(except RESO)——0.4VI

OL = 1.6 mA

Ports 1, 2, 5,

and B ——1.0V I

OL = 10 mA

Output low

voltage

RESO

VOL

——0.4VI

OL = 2.6 mA

STBY, NMI,

RES,

MD2 to MD0

——1.0µAV

IN = 0.5 to

VCC – 0.5 V

Input

leakage

current

Port 7

|IIN|

——1.0µAV

IN = 0.5 to

AVCC – 0.5 V

Rev. 6.0, 09/02, page 679 of 876

Item Symbol Min Typ Max Unit Test Conditions

Ports 1 to 6,

8 to B ——1.0µA

Three-state

leakage

current

(off state) RESO

|ITS1|

— — 10.0 µA

VIN = 0.5 to

VCC – 0.5 V

Input pull-up

current Ports 2, 4,

and 5 –IP50 — 300 µA VIN = 0 V

NMI — — 50 pFInput

capacitance All input pins

except NMI

CIN — — 15 pF VIN = 0 V

f = 1 MHz

Ta = 25°C

— 50 65 mA f = 16 MHzNormal

operation — 55 75 mA f = 18 MHz

— 35 50 mA f = 16 MHzSleep mode — 40 55 mA f = 18 MHz

— 20 25 mA f = 16 MHzModule standb y

mode*4— 25 27 mA f = 18 MHz

— 0.01 5.0 µA Ta ≤ 50°C

Current

dissipation*2

Standby mode*3

ICC

— — 20.0 µA 50°C < Ta

During A/D

conversion —1.22.0mA

During A/D and

D/A conversion —1.22.0mA

Analog

power

supply

current

Idle

AICC

— 0.01 5.0 µA DASTE = 0

During A/D

conversion —0.30.6mAV

REF = 5.0 V

During A/D and

D/A conversion —1.33.0mA

Reference

current

Idle

AICC

— 0.01 5.0 µA DASTE = 0

RAM standby voltage VRAM 2.0 — — V

Notes: *1 If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and VREF pins

open. Connect AVCC and VREF to VCC, and connect AVSS to VSS.

*2 Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output

pins unloaded and the on-chip pull-up transistors in the off state.

*3 The values are for VRAM ≤ VCC < 4.5 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.

*4 Module standby current values apply in sleep mode with all modules halted.

Rev. 6.0, 09/02, page 680 of 876

Table 22.2 DC Characteristics (2)

Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,

VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-rang e specifications)

Item Symbol Min Typ Max Unit Test Conditions

VT–VCC × 0.2 — — V

VT+——V

CC × 0.7 V

Schmitt

trigger input

voltages

Port A,

P82 to P80,

PB3 to PB0VT+ – VT–VCC × 0.07 — — V

RES, STBY,

NMI,

MD2 to MD0

VCC × 0.9 — VCC + 0.3 V

EXTAL VCC × 0.7 — VCC + 0.3 V

Port 7 VCC × 0.7 — AVCC + 0.3 V

Input high

voltage

Ports 1 to 6, 9,

P84, P83, PB7 to

PB4

VIH

VCC × 0.7 — VCC + 0.3 V

RES, STBY,

MD2 to MD0

–0.3 — VCC × 0.1 V

VCC × 0.2 V VCC < 4.0 V

Input low

voltage NMI, EXTAL,

ports 1 to 7, 9,

P83, P84 PB4 to

PB7

VIL

–0.3 —

0.8 V VCC =

4.0 V to 5.5 V

VCC – 0.5 — — V IOH = –200 µAOutput high

voltage All output pins

(except RESO)VOH VCC – 1.0 — — V IOH = –1 mA

All output pins

(except RESO)——0.4VI

OL = 1.6 mA

Ports 1, 2, 5,

and B ——1.0VV

CC ≤ 4 V

IOL = 5 mA,

4 V < VCC ≤ 5.5 V

IOL = 10 mA

Output low

voltage

RESO

VOL

——0.4VI

OL = 1.6 mA

STBY, NMI,

RES,

MD2 to MD0

——1.0µAV

IN = 0.5 to

VCC – 0.5 V

Input

leakage

current Port 7

|IIN|

——1.0µAV

IN = 0.5 to

AVCC – 0.5 V

Ports 1 to 6,

8 to B ——1.0µAThree-state

leakage

current

(off state) RESO

|ITS1|

— — 10.0 µA

VIN = 0.5 to

VCC – 0.5 V

Rev. 6.0, 09/02, page 681 of 876

Item Symbol Min Typ Max Unit Test Conditions

Input pull-up

current Ports 2, 4,

and 5 –IP10 — 300 µA VCC = 2.7 V to

5.5 V, VIN = 0 V

NMI — — 50Input

capacitance All input pins

except NMI

CIN ——15pF VIN = 0 V

f = 1 MHz

Ta = 25°C

—12

(3.0 V) 35

(5.5 V) mA f = 8 MHzNormal

operation

—20

(3.3 V) 55

(5.5 V) mA f = 13 MHz

(VCC = 3.15 V to

5.5 V)

—8

(3.0 V) 25

(5.5 V) mA f = 8 MHzSleep mode

—12

(3.3 V) 40

(5.5 V) mA f = 13 MHz

(VCC = 3.15 V to

5.5 V)

—5

(3.0 V) 14

(5.5 V) mA f = 8 MHzModule standb y

mode*5

—7

(3.3 V) 20

(5.5 V) mA 13 MHz

(VCC = 3.15 V to

5.5 V)

— 0.01 5.0 µA Ta ≤ 50°C

Current

dissipation*2

Standby mode*3

ICC*4

— — 20.0 µA 50°C < Ta

—0.41.0mAAV

CC = 3.0 VDuring A/D

conversion —1.2—mAAV

CC = 5.0 V

—0.41.0mAAV

CC = 3.0 VDuring A/D and

D/A conversion —1.2—mAAV

CC = 5.0 V

Analog

power

supply

current

Idle

AICC

— 0.01 5.0 µA DASTE = 0

—0.20.4mAV

REF = 3.0 VDuring A/D

conversion —0.3—mAV

REF = 5.0 V

—0.82.0mAV

REF = 3.0 VDuring A/D and

D/A conversion —1.3—mAV

REF = 5.0 V

Reference

current

Idle

AICC

— 0.01 5.0 µA DASTE = 0

RAM standby voltage VRAM 2.0 — — V

Notes: *1 If the A/D and D/A converters are not used, do not leave the AVCC, AVSS, and VREF pins

open. Connect AVCC and VREF to VCC, and connect AVSS to VSS.

*2 Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output

pins unloaded and the on-chip pull-up transistors in the off state.

*3 The values are for VRAM ≤ VCC < 2.7 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.

Rev. 6.0, 09/02, page 682 of 876

*4I

CC depends on VCC and f as follows:

ICCmax = 3.0 (mA) + 0.75 (mA/MHz·V) × VCC × f [normal mode]

ICCmax = 3.0 (mA) + 0.55 (mA/MHz·V) × VCC × f [sleep mode]

ICCmax = 3.0 (mA) + 0.25 (mA/MHz·V) × VCC × f [module standby mode]

*5 Module standby current values apply in sleep mode with all modules halted.

Table 22.4 Permissible Output Currents

Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,

VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-rang e specifications)

Item Symbol Min Typ Max Unit

Ports 1, 2, 5, and B IOL ——10mAPermissible output

low current (per pin) Other output pins — — 2.0 mA

Permissible output

low current (total) Total of 28 pins in

ports 1, 2, 5, and B ΣIOL ——80mA

Total of all output pins,

including the above — — 120 mA

Permissible output

high current (per pin) All output pins IOH ——2.0mA

Permissible output

high current (total) Total of all output pins ΣIOH ——40mA

Notes: 1. To protect chip reliability, do not exceed the output current values in table 22.4.

2. When driving a darlington pair or LED, always insert a current-limiting resistor in the

output line, as shown in figures 22.1 and 22.2.

Rev. 6.0, 09/02, page 683 of 876

H8/3048

Series

Port 2 kΩ

Darlington pair

Figure 22.1 Darlington Pair Drive Circuit (Example)

H8/3048

Series

Ports 1, 2, 5,

and B

LED

600Ω

Figure 22.2 LED Drive Circuit (Example)

Rev. 6.0, 09/02, page 684 of 876

22.1.3 AC Characteristics

Bus timing parameters are listed in table 22.5. Refresh controller bu s tim ing parameters are listed

in table 22.6. Control signal timing parameters are listed in table 22.7. Timing parameters of the

on-chip supporting modules are listed in table 22.8.

Table 22.5 Bus Timing

Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VREF = 2.7 V to AVCC,

VSS = AVSS = 0 V, φ = 1 MHz to 8 MHz, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range sp ecifications)

Condition B: VCC = 3.15 V to 5.5 V, AVCC = 3.15 V to 5.5 V, VREF = 3.15 V to AVCC,

VSS = AVSS = 0 V, φ = 1 MHz to 13 MHz, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range sp ecifications)

Condition C: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%, VREF = 4.5 V to AVCC,

VSS = AVSS = 0 V, φ = 1 MHz to 18 MHz, Ta = –20°C to +75°C (regular

specifications), Ta = –40°C to +85°C (wide-range sp ecifications)

Condition

ACondition

BCondition

8 MHz 13 MHz 16 MHz 18 M Hz

Item Symbol Min Max Min Max Min Max Min Max Unit Test

Conditions

Clock cycle time tCYC 125 1000 76.9 1000 62.5 1000 55.5 1000 ns

Clock pulse l ow wi dth tCL 40 — 20 — 20 — 17 —

Figure 22.7,

Figure 22.8

Clock pulse high width tCH 40 — 20 — 20 — 17 —

Clock rise time tCR — 20 — 15 — 10 — 10

Clock fall time tCF — 20 — 15 — 10 — 10

Address delay tim e tAD — 60 — 50 — 30 — 25

Address hold time tAH 25 — 20 — 10 — 10 —

Address strobe delay

time tASD — 60 — 50 — 30 — 25

Write strobe delay time tWSD — 60 — 50 — 30 — 25

Strobe delay time tSD — 60 — 50 — 30 — 25

Write data strobe pulse

width 1 tWSW1*85 — 40 — 35 — 32 —

Write data strobe pulse

width 2 tWSW2*150 — 90 — 65 — 62 —

Address setup time 1 tAS1 20 — 15 — 10 — 10 —

Address setup time 2 tAS2 80 — 45 — 40 — 38 —

Read data setup time tRDS 50 — 30 — 20 — 15 —

Read data hold time tRDH 0— 0— 0— 0—

Rev. 6.0, 09/02, page 685 of 876

Condition

ACondition

BCondition

8 MHz 13 MHz 16 MHz 18 M Hz

Item Symbol Min Max Min Max Min Max Min Max Unit Test

Conditions

Write data delay time tWDD — 75 — 75 — 60 — 55 ns

Write data setup time 1 t WDS1 60 — 20 — 15 — 10 —

Figure 22.7,

Figure 22.8

Write data setup time 2 t WDS2 5 — –10 — –5 — –10 —

Write data hold time tWDH 25 — 15 — 20 — 20 —

Read data access time 1 t ACC1*— 120 — 60 — 60 — 50

Read data access time 2 t ACC2*— 240 — 140 — 120 — 105

Read data access time 3 t ACC3*— 70 — 30 — 30 — 20

Read data access time 4 t ACC4*— 180 — 100 — 95 — 80

Precharge time tPCH*85 — 55 — 45 — 40 —

Wait setu p time tWTS 40 — 40 — 25 — 25 — ns Figure 22.9

Wait hold time tWTH 10 — 10 — 5 — 5 —

Bus request setup ime tBRQS 40 — 40 — 40 — 40 — ns Figure 22.21

Bus acknowledge del ay

time 1 tBACD1 — 60 — 50 — 30 — 30

Bus acknowledge del ay

time 2 tBACD2 — 60 — 50 — 30 — 30

Bus-floating time tBZD — 70 — 70 — 40 — 40

Note: *At 8 MHz, the times below depend as indicated on the clock cycle time.

tACC1 = 1.5 × tCYC – 68 (ns) tWSW1 = 1.0 × tCYC – 40 (ns)

tACC2 = 2.5 × tCYC – 73 (ns) tWSW2 = 1.5 × tCYC – 38 (ns)

tACC3 = 1.0 × tCYC – 55 (ns) tPCH = 1.0 × tCYC – 40 (ns)

tACC4 = 2.0 × tCYC – 70 (ns)

At 13 MHz, the times below depend as indicated on the clock cycle time.

tACC1 = 1.5 × tCYC – 56 (ns) tWSW1 = 1.0 × tCYC – 37 (ns)

tACC2 = 2.5 × tCYC – 53 (ns) tWSW2 = 1.5 × tCYC – 26 (ns)

tACC3 = 1.0 × tCYC – 47 (ns) tPCH = 1.0 × tCYC – 32 (ns)

tACC4 = 2.0 × tCYC – 54 (ns)

At 16 MHz, the times below depend as indicated on the clock cycle time.

tACC1 = 1.5 × tCYC – 34 (ns) tWSW1 = 1.0 × tCYC – 28 (ns)

tACC2 = 2.5 × tCYC – 37 (ns) tWSW2 = 1.5 × tCYC – 29 (ns)

tACC3 = 1.0 × tCYC – 33 (ns) tPCH = 1.0 × tCYC – 28 (ns)

tACC4 = 2.0 × tCYC – 30 (ns)

At 18 MHz, the times below depend as indicated on the clock cycle time.

tACC1 = 1.5 × tCYC – 34 (ns) tWSW1 = 1.0 × tCYC – 24 (ns)

tACC2 = 2.5 × tCYC – 34 (ns) tWSW2 = 1.5 × tCYC – 22 (ns)

tACC3 = 1.0 × tCYC – 36 (ns) tPCH = 1.0 × tCYC – 21 (ns)

tACC4 = 2.0 × tCYC – 31 (ns)

Rev. 6.0, 09/02, page 686 of 876

Table 22.6 Refresh Controller Bus Timing