July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Am29LV320MH/L
Data Sheet
Publication Number 26517 Revision BAmendment 1 Issue Date February 12, 2004
For new designs, S29GL032M supercedes Am29LV320MH/L and is the factory-recommended migra-
tion path for this device. Please refer to the S29GLxxxM Family Datasheet for specifications and
ordering information.
THIS PAGE LEFT INTENTIONALLY BLANK.
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 26517 Rev: BAmendment/1
Issue Date: Februar y 12, 20 04
Refer to AMD’s Website (www.amd.com) for the latest information.
For new designs, S29GL032M supercedes Am29LV320MH/L and is the factory-recommended migration path
for this device. Please refer to the S29GLxxxM Family Datasheet for specifications and ordering information.
Am29LV320MH/L
32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit™
3.0 Volt-onl y Uniform Sector Flash Memory with VersatileI/O™ Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■Single power supply operation
— 3 V for read, erase, and program operations
■VersatileI/O™ control
— Device generates data output voltages and tolerates
data input voltages on the DQ inputs/outputs as
determined by the voltage on the VIO pin; operates
from 1.65 to 3.6 V
■Manufactured on 0.23 µm MirrorBit process
technology
■SecSi™ (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identifica tio n throu gh an 8-wor d/1 6-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
■Flexible sector architecture
— Sixty-four 32 Kword/64-Kbyte sectors
■Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
■Minimum 100,000 erase cycle guarantee per sector
■20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■High performance
— 90 ns access time
— 25 ns page read times
— 0.5 s typical sector erase time
— 15 µs typical effective write buffer word programming
time: 16-word/32-byte write buffer reduces overall
programming time for multiple-word/byte updates
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer
■Low power consumption (typical values at 3.0 V, 5
MHz)
— 13 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
■Package options
— 56-pin TSOP
— 64-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
■Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is com pleted
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
— WP#/ACC input:
Write Protect input (WP#) protects first or last sector
regardless of sector protection settings
A CC (hi gh v olt age) accel era tes pr ogr ammi ng ti me f or
higher throughput during system production
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
2 Am29LV320MH/L February 12, 2004
PRELIMINARY
GENERAL DESCRIPTION
The Am29LV320MH/L is a 32 Mbit, 3.0 volt single
power supply flash memory device organized as
2,097,152 words or 4,194,304 bytes. The device has
an 8-bit/16-bit bus and can be p rogrammed either in
the host system or in standard EPROM programmers.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (VCC) and an I/O voltage range (VIO), as
specified in the Product Selector Guide and the Order-
ing Information sections. The device is offered in a
56-pin TSOP or 64-ball Fortified BGA package. Each
device has separate chip enable (C E#), write enable
(WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power
supply for both read and write functions. In addit i on to
a VCC input, a high-voltage accelerated program
(ACC) feature provides shor ter programming times
through increased c urrent on the WP#/ACC input. This
feature is intended to facilitate factory throughpu t dur-
ing system production, but may also be used in the
field if desired.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Com mands ar e wri tten to the device usin g standa rd
microprocessor write timing. Write cycles also inter-
nally latch addresses and data need ed for the pr o-
gr amming and er ase operations.
The sect or erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the da ta co ntents of othe r se ctors. The device is fu lly
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system n eed only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter-
mine wh ether the operation is compl ete. To facilitate
programming, an Un l o ck Bypas s mode reduc es com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The VersatileI/O™ (VIO) control allows the host sys-
tem to set the voltage levels that the device generates
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asser ted on the VIO pin.
Refer to the Ordering Inform ation section for valid VIO
options.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memor y.
This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature allows
the host system to pause an eras e operation in a giv en
secto r to read or program any oth er sector and the n
complete the erase operation. The Program Sus-
pend/P rogram Resume f eature enables the host sys-
tem to pause a program operation in a given sector to
read any other sector a nd then complete the program
operation.
The hardware RE SET# pin term inates any operation
in progress and resets the device, after whic h it is then
ready for a new operation. T he RESET # pin may be
tied to the system res et circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode when it detects sp ecific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The Write Protect (WP#) feature protects the first or
last sector by assert ing a logic low on the WP#/ACC
pin. The protected sector will still be protected even
during accelerated programming.
The SecSi™ (Secured Silicon) Sector provides a
128-word/256-byte area for code or data that can be
per mane ntly prote cted. On ce this s ector is protecte d,
no fur ther changes within the sector can occur.
AMD MirrorBit flash technology combines years of
Flash mem ory manufacturing experience to pro duce
the highest levels of quality, reliability and cost effec-
tiveness . The device electrically erases all bits within a
sector simultaneously via hot-hole ass i st ed erase . The
data is programmed using hot electron injection.
February 12, 2004 Am29LV320MH/L 3
PRELIMINARY
MIRRORBIT 32 MBIT DEVICE FAMILY
RELATED DOCUMENTS
To download related documents, click on the following
links or go to www.amd.com→Flash Memory→Prod-
uct Inform ation→MirrorBit→Flash Information→Tech-
nical Documentation.
MirrorBit™ Flash Memor y Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
Migrat ing from Single-byte to Three-byte Device IDs
AMD MirrorBit™ White Paper
Device Bus Sector Architecture Packages VIO RY/BY# WP#, ACC WP# Protection
LV033MU x8 Uniform (64 Kbyte) 40-pin TSOP (std. & rev. pinout),
48-ball FBGA Yes Yes AC C only No WP#
LV320MT/B x8/x16 Boot (8 x 8 Kbyte
at top & bottom) 48-pin TSOP, 48-ball Fine-pitch BGA,
64-ball Fortified BGA No Yes WP#/ACC pin 2 x 8 Kbyte
top or bottom
LV320MH/L x8/x16 Uniform (64 Kbyte) 56-pin TSOP (std. & re v. pinout),
64 Fortified BGA Yes Yes WP#/AC C pin 1 x 64 Kbyte
high or low
4 Am29LV320MH/L February 12, 2004
PRELIMINARY
TABLE OF CONTENTS
Product Selecto r Guide. . . . . . . . . . . . . . . . . . . . . 5
Bloc k Diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagram s . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Orderin g Information. . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1 . Dev ice Bus Operati o n s... ..... ............................................. 10
VersatileIO
™
(VIO) C on t r o l ... ................ ..................................1 0
Requirements for Reading Array Data .. ....... ................. .........11
Page Mode Read ....................................... ......... ............ .... ............11
Writing Commands/Command Sequence s ......... ...................11
Write Bu ffer ..................................................................... ................11
Accelerated Program Operation ......................................................11
Auto se l ect Funct ion s .......................................................................11
Automatic Sleep Mode ..................... ............ ....... ...................12
RESET#: Hardware Reset Pin ...............................................12
Output Disable Mode ..............................................................12
Table 2 . Se cto r Ad d re ss Tab le...... ..... ......... ....................... ............. 13
Table 3 . Au to se lect Codes, (High Vo lt a g e Method) ....................... 15
Sector Group Protection and Unprotection ............. ....... ....... ..16
Table 4. Sector Group Protection/Unprotection Address Table ..... 16
Temporary Sector Group Unprotect .......................................17
Figure 1. Temporary Sector Group Unprotect Operation ................17
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...18
SecSi (Secured Silicon) Sector Flash Memory Region ...... ....19
Table 5 . Se cSi Sector Contents.... ................................. ................. 19
Fig ur e 3. Se cSi Se cto r Pro tect Verify ..............................................20
Hardware Data Protection ......................................................20
Low VCC Write Inhibit .....................................................................20
Write Pu lse “Gli tch” Pro te c tion ............................................ ............20
Logical Inhibit ............ ..... ....... ........ . ....... ....... ...... ... ....... ......... .... ... ...2 0
Power- Up Write Inhibit ...... ......... ......... .......... ......... ......... ......... .......20
Common Flash Memor y Interface (CFI). . . . . . . 20
Table 6. CFI Query Identification String ..........................................21
Table 7 . System Interfa ce String............................... ......... ......... .... 21
Table 8 . Dev ice Geometry Definition .............................. ................22
Table 9. Primary Vendor-Specific Extended Query ........................23
Command Definition s . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................23
Reset Command ..................................... ............. ..... ..............24
Autoselect Command Sequence .... ..................... ..... ..............24
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..24
Word/Byte Program Command Sequence .............................2 4
Unlock Bypass Command Sequence ..............................................25
Write Bu ffer Pro gr am mi n g ...............................................................25
Accelerated Program ......................................................................26
Fig ur e 4. Wr ite Buffer Pro g ra mming Opera tion ............. ......... .........27
Fig ur e 5. Pro g ra m Oper a tion .......... ....................... ....................... ..28
Program Suspend/Program Resume Command Sequence ...28
Figure 6. Program Suspend/Program Resume ...............................29
Chip Erase Command Sequence ...........................................29
Sector Erase Command Sequence ........................................29
Erase Suspend/Erase Resume Commands .... ....... .. ..............30
Fig ur e 7. Era se Ope ra tion ............................. ...................... ............30
Table 10. Command Definitions (x16 Mode, BYTE# = VIH). ..... ..... 31
Table 11. Command Definitions (x8 Mode, BYTE# = VIL).... .......... 32
Write Operation Status. . . . . . . . . . . . . . . . . . . . . 33
DQ7 : Da t a # P o l lin g ..... ............................... .............................33
Figure 8. Data# Polling Algorithm .................................................. 3 3
DQ6: Toggle Bit I ....................................................................34
Figure 9. Toggle Bit Algorithm ........................................................ 35
DQ2: Toggle Bit II ...................................................................35
Reading Toggle Bits DQ6/DQ2 ...............................................35
DQ5: Exceeded Timing Limits ................................................36
DQ3 : Se c to r Er a se Tim e r ... ................ ................. ...................36
DQ1 : Wri te - t o -B u ffe r Ab o r t . .. ....... ................. ................ ..........36
Table 1 2. Wri te Ope ra tion Status................................................... 36
Figure 10. Maximum Negative Ov ershoot Waveform ................... 37
Figure 11. Maximum Positive Overshoot Waveform ..................... 3 7
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 37
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Test Setu p .................................................................... 39
Table 1 3. Test Sp e c i ficat io n s.... ..................................................... 39
Key to Switching Waveforms. . . . . . . . . . . . . . . . 39
Figure 13. Input Waveforms and
Measurement Levels ...................................................................... 3 9
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40
Read-Only Operations ...........................................................40
Figure 14. Read Operation Tim ing ................................................. 40
Figure 15. Page Read Timings ...................................................... 41
Hardware Reset (RESET#) ............ ............. .. .... ............. .. .... ..42
Figure 16. Reset Timings ............................................................... 4 2
Erase and Program Operations ......... ................. .................. ..43
Figure 17. Program Operation Timings .......................................... 44
Figure 18. Accelerated Program Timing Diagram .......................... 44
Figure 19. Chip/Sector Erase Operation Timings .......................... 45
Figure 20. Data# Polling Timings (During Embedded Algorithms) . 46
Figure 21. Toggle Bit Timings (During Embedded Algorithms) ...... 47
Figure 22. DQ2 vs. DQ6 ................................................................. 47
Temporary Sector Unprotect ..................................................48
Figure 23. Temporary Sector Group Unprotect Timing Diagra m ... 48
Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 49
Alternate CE# Controlled Erase and Program Operations .....50
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings .......................................................................... 51
Erase And Programming Performance. . . . . . . . 52
Latchup C haracteristics. . . . . . . . . . . . . . . . . . . . 52
TSOP Pin and BGA Package Capacitance . . . . . 53
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 54
TS056/TSR056—56-Pin Standard and Reverse Pinout Thin
Small Outline Package (TSOP) ......... ....... ............ ....... ...........54
LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm
Package ..................................................................................55
Re v is ion Su m ma ry . . . . . . . . . . . . . . . . . . . . . . . . 5 6
February 12, 2004 Am29LV320MH/L 5
PRELIMINARY
PRODUCT SELECTOR GUIDE
Note:
1. See “AC Characteristics” for full specifications.
2. For the Am29LV320MH/L de vi ce, t he last numeric dig it in the speed option (e .g. 90R, 101, 112, 120 ) is used for internal purposes
only. Please use OPNs as lis ted when placi ng orders .
BLOCK DIAGRAM
Part Number Am29LV320MH/L
Speed Op tion
VCC =
3.0–3.6 V
90R
(VIO =
3.0–3.6 V)
101R
(VIO =
2.7–3.6 V)
112R
(VIO =
1.65–3.6 V)
120R
(VIO =
1.65–3.6 V)
VCC =
2.7–3.6 V
101
(VIO =
2.7–3.6 V)
112
(VIO =
1.65–3.6 V)
120
(VIO =
1.65–3.6 V)
Max. Access Time (ns) 90 100 110 120
Max. CE# Access Time (ns) 90 100 110 120
Max. Page access Time (tPACC)253030403040
Max. OE# Access Time (ns) 25 30 30 40 30 40
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
WP#/ACC
BYTE#
CE#
OE#
STB
STB
DQ0
–
DQ15 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A20–A0
VIO
6 Am29LV320MH/L February 12, 2004
PRELIMINARY
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC 56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
NC
NC
23
24
25
26
27
28
NC
NC
34
33
32
31
30
29 NC
VIO
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A1
A17
A7
A6
A5
A4
A3
A2
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
NC
NC
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0 23
24
25
26
27
28
A4
A3
A2
A1
NC
NC
34
33
32
31
30
29
OE#
VSS
CE#
A0
NC
VIO
56-Pin Standard TSOP
56-Pin Reverse TSOP
February 12, 2004 Am29LV320MH/L 7
PRELIMINARY
CONNECTION DIAGRAMS
Special Package Handling Instructions
Special handling is required f or Flash Memory products
in molded pac kages (TSOP, BGA, SSOP, PDIP, PLCC).
The package and/or data integ rity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
B3 C3 D3 E3 F3 G3 H3
B4 C4 D4 E4 F4 G4 H4
B5 C5 D5 E5 F5 G5 H5
B6 C6 D6 E6 F6 G6 H6
B7 C7 D7 E7 F7 G7 H7
B8 C8 D8 E8 F8 G8 H8
NCNCNCVSS
VIO
NCNC
VSS
DQ15/A-1BYTE#A16A15A14A12
DQ6
DQ13DQ14DQ7A11A10A8
DQ4VCC
DQ12DQ5A19NCRESET#
DQ3DQ11DQ10DQ2A20A18WP#/ACC
DQ1DQ9DQ8DQ0A5A6A17
A3
A4
A5
A6
A7
A8
NC
A13
A9
WE#
RY/BY#
A7
B2 C2 D2 E2 F2 G2 H2
VSS
OE#CE#A0A1A2A4
A2
A3
B1 C1 D1 E1 F1 G1 H1
NCNCVIO
NCNCNCNC
A1
NC
64-Ball Fortified BGA
Top View, Bal ls Facing Down
8 Am29LV320MH/L February 12, 2004
PRELIMINARY
PIN DESCRIPTION
A20–A0 = 21 Address inputs
DQ14–DQ0 = 15 Data inputs/outputs
DQ15/A-1 = DQ15 (Data input/output, word mode),
A-1 (LSB Address input, by te mode)
CE# = Chip Enable input
OE# = Output Enable input
WE# = Write Enable input
WP#/ACC = Hardware Write Protect input/Pro-
gramming Acceler ation input
RESET# = Hardware Reset Pin input
RY/BY# = Ready/Busy output
BYTE# = Selects 8-bit or 16-bit mode
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VIO = Output Buffer power
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
21 16 or 8
DQ15–DQ0
(A-1)
A20–A0
CE#
OE#
WE#
RESET#
RY/BY#
WP#/ACC
VIO
BYTE#
February 12, 2004 Am29LV320MH/L 9
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Valid C ombinations
V alid Combinati ons list configurations planned to be supported in vol -
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.
Note:
For the Am29L V320MH/L de vice, the last numeric digit in the speed option (e.g.
90R, 101, 112, 120) is used for inter nal purpo ses only. Please use OPNs as
listed when placing orders.
Am29LV320M H 120R PC I
TEMP ER ATU R E RA NG E
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056)
F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056)
PC = 64-Ball Fortified Ball Grid Array
1.0 mm pitch, 13 x 11 mm package (LAA064)
SPEED OPTION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = VIL)
H = Un iform sector device, highest address sector protected
L = Uniform sector device, lowest address sector protec ted
DEVICE NUMBER/DESCRIPTION
Am29LV320M
32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit™ Uni for m Sector Flash Memory
with VersatileIO™ Control, 3.0 Volt-only Read, P rogram, and Erase
Valid Combinations for
TSOP Package Speed
(ns) VIO
Range VCC
Range
Am29LV320MH90R,
Am29LV320ML90R
EI,
FI
90 3.0–3. 6 V 3.0–3.6 V
Am29LV320MH101,
Am29LV320ML101 100 2.7–3.6 V
2.7– 3.6 V
Am29LV320MH112,
Am29LV320ML112 110 1.65–3.6 V
Am29LV320MH120,
Am29LV320ML120 120 1.65–3.6 V
Am29LV320MH101R,
Am29LV320ML101R 100 2.7–3.6 V
3.0– 3.6 V
Am29LV320MH112R,
Am29LV320ML112R 110 1.65–3.6 V
Am29LV320MH120R,
Am29LV320ML120R 120 1.65–3.6 V
Valid Combi na t ions for
Fortifie d BGA P ac ka ge Speed
(ns) VIO
Range VCC
Range
Order Number Pac kage
Marking
Am29LV320MH90R,
Am29LV320ML90R
PCI
L320MH90N,
L320ML90N
I
90 3.0–
3.6 V 3.0–
3.6 V
Am29LV320MH101,
Am29LV320ML101 L320MH01P,
L320ML01P 100 2.7–
3.6 V 2.7–
3.6 V
Am29LV320MH112,
Am29LV320ML112 L320MH11P,
L320ML11P 110 1.65–
3.6 V
Am29LV320MH120,
Am29LV320ML120 L320MH12P,
L320ML12P 120 1.65–
3.6 V
Am29LV320MH101R,
Am29LV320ML101R L320MH01N,
L320ML01N 100 2.7–
3.6 V 3.0–
3.6 V
Am29LV320MH112R,
Am29LV320ML112R L320MH11N,
L320ML11N 110 1.65–
3.6 V
Am29LV320MH120R,
Am29LV320ML120R L320MH12N,
L320ML12N 120 1.65–
3.6 V
10 Am29LV320MH/L February 12, 2004
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are i nitiated throug h
the internal comm and register. The command register
itself d oes not occ upy any addre ssable memor y loca-
tion. The register is a latch used to store the com-
mands, alo ng with the add ress and da ta info rmatio n
needed to exec ute the command. The con tents of the
regist er ser ve as inputs to the inter nal state machi ne.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Legend: L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5 –12. 5
V, V
HH
= 11.5–12.5
V, X = Don’t Care, SA = Sector Address,
A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A20:A0 in word mode; A20:A-1 in byte mode. Sector addresses are A20:A15 in both modes.
2. The sector protect and sector unprot ect f unctions may also be implemented via prog r amming equipment. See t he “Sect or Grou p
Protection and Un protect ion” sectio n.
3. If WP# = V
IL
, the first or l ast s ector remains protect ed. I f WP# = V
IH
, the first or las t sect or wi ll be protec ted or unprot ected as
determined by the met hod described i n “Sect or Gr oup Prot ection and Unpro tecti on”. All se ctors are unpr otecte d when shi pped
from the factory (The SecSi Sector may be factory protected dep ending on version ordered.)
4. D
IN
or D
OUT
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Word/Byte Configuration
The BYTE# pin controls whether the device da ta I/O
pins operate in the byte or word configurati on. If the
BYTE# pin is set at logic ‘1’, the dev ice is in word con-
figuration, DQ0–D Q15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
VersatileIO™ (VIO) Control
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is assert ed on VIO. See “Order ing Inform a-
tion” on page 9 for V IO options on this device.
Operation CE# OE# WE# RESET# WP# ACC Addresses
(Note 2) DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read L L H H XX AIN DOUT DOUT DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase) L H L H (Note 3) X AIN (Note 4) (Note 4)
Accelerated Program L H L H (Note 3) VHH AIN (Note 4) (Note 4)
Standby VCC ±
0.3 V XXVCC ±
0.3 V XH XHigh-Z High-Z High-Z
Output Disable L H H H XX XHigh-Z High-Z High-Z
Reset X X X L XX XHigh-Z High-Z High-Z
Sector Group Protect
(Note 2) LHL V
ID HX
SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L (Note 4) X X
Sector Grou p Unprotect
(Note 2) LHL V
ID HX
SA, A6=H,
A3=L, A2=L,
A1=H, A0=L (Note 4) X X
T emporary Sector Group
Unprotect XXX V
ID HX AIN (Note 4) (Note 4) High-Z
February 12, 2004 Am29LV320MH/L 11
PRELIMINARY
For examp le, a VI/O of 1.65–3.6 vo lts allows for I/O at
the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data
bus.
Requirements for Reading Array Data
To read array data from th e outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that asser t valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “ Reading Array Data” for more information. Refer
to the A C Read-Only Operations table for timing speci-
fications and to Figure 13 f or the timing diag r am. Refer
to the DC Character istics table for the active current
specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
atio n. This mo de provide s faster r ead acc ess spee d
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad-
dress bits A1–A0 in word mode (A1–A-1 in b yt e mode)
determine the specific word within a page. This is an
asynchr onous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to tACC or
tCE and subsequent page read ac cesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. W hen CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Fast page mode ac-
cesses are obtained by keeping the “read-page ad-
dresses ” constant a nd changing the “in tra-read page ”
addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
An erase oper at ion can er ase one se ctor, multiple s ec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies.
Refer to the DC Characteristics table for the active
current specification for the write mode. The AC Char-
acteristics se ction contai ns timing spec ificatio n tables
and timing diagrams for write operations.
Write Buffer
Write Buff er Programming all ows the system to write a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effec tive programming
time than the standard programming algorithms. See
“Write Buffer” for more information.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is pr ima-
ri ly intend ed to allow faster manufactur ing thro ughp ut
at the factory.
If the system asser t s VHH on this pin, the dev ice auto-
matically enters the aforementioned Unlock Bypass
mode, temporar ily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would us e a two-cycle program comman d sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP #/ACC pin retu rn s the device to no r-
mal operation.
Note that the WP#/A CC pin must not be
at V
HH
for operations other than accelerated program-
ming, or device damage may result. In addition, no ex -
ternal pullup is necessar y since the WP#/ACC pin has
internal pullup to V
CC.
A utoselect Functions
If the system writes the autoselect command se-
quence, the device enters th e autoselect mod e. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mo de. Refer to the Autoselect Mode and Autose-
lect Comm and Sequence sections for more informa -
tion.
Standby Mode
When the system is no t reading or wr iting to the de-
vice, it can place the device in the stan dby mode. In
this mode, current consumption is greatly reduced,
12 Am29LV320MH/L February 12, 2004
PRELIMINARY
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VIO ± 0.3 V.
(Note that this is a m ore restr icted voltage range than
VIH.) I f CE# and RESET# are held at VIH, but not within
VIO ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
If the devic e is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the DC Characteristics table for the standby
current specification.
Automatic Sleep Mode
The automatic sl eep mode minimiz es Flash device en-
ergy consumption. The device automatically enables
this mode whe n addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are change d. While in sleep mode, o utput
data is latched and always available to the system.
Refer to the DC Characteristics table for the automatic
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESE T# pin provides a hardware method of re-
setting the device to reading arr ay data. When the RE-
SET# pin is driven low for at least a period of tRP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/w rite command s for the duration of the RESET #
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept a nother com mand se quence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
dra ws CMOS stand b y cu rrent ( ICC4). If RE SET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitr y. A system re set would thus also r eset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 16 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output fr om the de v ice is
disabled. The output pins are placed in the high
impedance state.
February 12, 2004 Am29LV320MH/L 13
PRELIMINARY
Table 2. Sector Address Table
Sector A20-A15 Sector Size
(Kbytes/Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
SA0 0 0 0 0 0 0 64/32 000000–00FFFF 000000–007FFF
SA1 0 0 0 0 0 1 64/32 010000–01FFFF 008000–00FFFF
SA2 0 0 0 0 1 0 64/32 020000–02FFFF 010000–017FFF
SA3 0 0 0 0 1 1 64/32 030000–03FFFF 018000–01FFFF
SA4 0 0 0 1 0 0 64/32 040000–04FFFF 020000–027FFF
SA5 0 0 0 1 0 1 64/32 050000–05FFFF 028000–02FFFF
SA6 0 0 0 1 1 0 64/32 060000–06FFFF 030000–037FFF
SA7 0 0 0 1 1 1 64/32 070000–07FFFF 038000–03FFFF
SA8 0 0 1 0 0 0 64/32 080000–08FFFF 040000–047FFF
SA9 0 0 1 0 0 1 64/32 090000–09FFFF 048000–04FFFF
SA10 0 0 1 0 1 0 64/32 0A0000–0AFFFF 050000–057FFF
SA11 0 0 1 0 1 1 64/32 0B0000–0BFFFF 058000–05FFFF
SA12 0 0 1 1 0 0 64/32 0C0000–0CFFFF 060000–067FFF
SA13 0 0 1 1 0 1 64/32 0D0000–0DFFFF 068000–06FFFF
SA14 0 0 1 1 1 0 64/32 0E0000–0EFFFF 070000–077FFF
SA15 0 0 1 1 1 1 64/32 0F0000–0FFFFF 078000–07FFFF
SA16 0 1 0 0 0 0 64/32 100000–10FFFF 080000–087FFF
SA17 0 1 0 0 0 1 64/32 110000–11FFFF 088000–08FFFF
SA18 0 1 0 0 1 0 64/32 120000–12FFFF 090000–097FFF
SA19 0 1 0 0 1 1 64/32 130000–13FFFF 098000–09FFFF
SA20 0 1 0 1 0 0 64/32 140000–14FFFF 0A0000–0A7FFF
SA21 0 1 0 1 0 1 64/32 150000–15FFFF 0A8000–0AFFFF
SA22 0 1 0 1 1 0 64/32 160000–16FFFF 0B0000–0B7FFF
SA23 0 1 0 1 1 1 64/32 170000–17FFFF 0B8000–0BFFFF
SA24 0 1 1 0 0 0 64/32 180000–18FFFF 0C0000–0C7FFF
SA25 0 1 1 0 0 1 64/32 190000–19FFFF 0C8000–0CFFFF
SA26 0 1 1 0 1 0 64/32 1A0000–1AFFFF 0D0000–0D7FFF
SA27 0 1 1 0 1 1 64/32 1B0000–1BFFFF 0D8000–0DFFFF
SA28 0 1 1 1 0 0 64/32 1C0000–1CFFFF 0E0000–0E7FFF
SA29 0 1 1 1 0 1 64/32 1D0000–1DFFFF 0E8000–0EFFFF
SA30 0 1 1 1 1 0 64/32 1E0000–1EFFFF 0F0000–0F7FFF
SA31 0 1 1 1 1 1 64/32 1F0000–1FFFFF 0F8000–0FFFFF
SA32 1 0 0 0 0 0 64/32 200000–20FFFF 100000–107FFF
SA33 1 0 0 0 0 1 64/32 210000–21FFFF 108000–10FFFF
SA34 1 0 0 0 1 0 64/32 220000–22FFFF 110000–117FFF
SA35 1 0 0 0 1 1 64/32 230000–23FFFF 118000–11FFFF
SA36 1 0 0 1 0 0 64/32 240000–24FFFF 120000–127FFF
SA37 1 0 0 1 0 1 64/32 250000–25FFFF 128000–12FFFF
SA38 1 0 0 1 1 0 64/32 260000–26FFFF 130000–137FFF
SA39 1 0 0 1 1 1 64/32 270000–27FFFF 138000–13FFFF
SA40 1 0 1 0 0 0 64/32 280000–28FFFF 140000–147FFF
SA41 1 0 1 0 0 1 64/32 290000–29FFFF 148000–14FFFF
SA42 1 0 1 0 1 0 64/32 2A0000–2AFFFF 150000–157FFF
SA43 1 0 1 0 1 1 64/32 2B0000–2BFFFF 158000–15FFFF
14 Am29LV320MH/L February 12, 2004
PRELIMINARY
Notes: The address range is A20:A-1 in byte mode (BYTE# = VIL) or A20:A0 in word mode (BYTE# = VIH).
SA44 1 0 1 1 0 0 64/32 2C0000–2CFFFF 160000–167FFF
SA45 1 0 1 1 0 1 64/32 2D0000–2DFFFF 168000–16FFFF
SA46 1 0 1 1 1 0 64/32 2E0000–2EFFFF 170000–177FFF
SA47 1 0 1 1 1 1 64/32 2F0000–2FFFFF 178000–17FFFF
SA48 1 1 0 0 0 0 64/32 300000–30FFFF 180000–187FFF
SA49 1 1 0 0 0 1 64/32 310000–31FFFF 188000–18FFFF
SA50 1 1 0 0 1 0 64/32 320000–32FFFF 190000–197FFF
SA51 1 1 0 0 1 1 64/32 330000–33FFFF 198000–19FFFF
SA52 1 1 0 1 0 0 64/32 340000–34FFFF 1A0000–1A7FFF
SA53 1 1 0 1 0 1 64/32 350000–35FFFF 1A8000–1AFFFF
SA54 1 1 0 1 1 0 64/32 360000–36FFFF 1B0000–1B7FFF
SA55 1 1 0 1 1 1 64/32 370000–37FFFF 1B8000–1BFFFF
SA56 1 1 1 0 0 0 64/32 380000–38FFFF 1C0000–1C7FFF
SA57 1 1 1 0 0 1 64/32 390000–39FFFF 1C8000–1CFFFF
SA58 1 1 1 0 1 0 64/32 3A0000–3AFFFF 1D0000–1D7FFF
SA59 1 1 1 0 1 1 64/32 3B0000–3BFFFF 1D8000–1DFFFF
SA60 1 1 1 1 0 0 64/32 3C0000–3CFFFF 1E0000–1E7FFF
SA61 1 1 1 1 0 1 64/32 3D0000–3DFFFF 1E8000–1EFFFF
SA62 1 1 1 1 1 0 64/32 3E0000–3EFFFF 1F0000–1F7FFF
SA63 1 1 1 1 1 1 64/32 3F0000–3FFFFF 1F8000–1FFFFF
Table 2. Sector Address Table (Continued)
Sector A20-A15 Sector Size
(Kbytes/Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
February 12, 2004 Am29LV320MH/L 15
PRELIMINARY
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice i dentification, a nd sector pr otection verificatio n,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algori thm. However, the autoselect codes can als o be
accessed in-system through the command register.
When using programming equipmen t, the autoselect
mode requires VID on address pin A9. Address pins
A6, A3, A2, A1 , and A0 must be as shown in Table 3.
In addition, when v erifying sector protection, the sector
address must appear on the appropriate highest order
address bits (see Table 2). Table 3 shows the remain-
ing address bits that are don’t care. When all neces-
sar y bits have been set as required, the programming
equipment m ay then read the corresp onding identifier
code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as show n in Tables 10 and 11. This
method does not require VID. Refer to the Autoselect
Command Sequence section for more information.
Tab le 3. Autoselect Codes, (High Vol tage Method)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Description CE# OE# WE# A20
to
A15
A14
to
A10 A9 A8
to
A7 A6 A5
to
A4
A3
to
A2 A1 A0
DQ8 to DQ15
DQ7 to DQ0
BYTE#
= VIH
BYTE#
= VIL
Manufacturer ID: AMD L L H X X VID X L X L L L 00 X 01h
De vice ID
Cycle 1
LLHXX
VID XLX
LLH 22 X 7Eh
Cycle 2 H H L 22 X 1Dh
Cycle 3 H H H 22 X 00h
Sector Protection
Verification LLHSAX
VID XLX L H L X X 01h (protected),
00h (unprotected)
SecS i S e ctor Ind i cator
Bit (DQ7), WP#
protects highest
address sector
LLHXX
VID XLX L HH X X 98h (factory locked),
18h (not factory locked)
SecSi Sector Indicator
Bit (DQ7), WP#
protects lowest
address sector
LLHXX
VID XLX L HH X X 88h (factory locked),
08h (not factory locked)
16 Am29LV320MH/L February 12, 2004
PRELIMINARY
Sector Group Protection and
Unprotection
The hardware sector group protection feature disables
both program and erase operations in any sector
group. In this device, a sector group consists of four
adjacent sectors that are protected or unprotected at
the same time (see Table 4). The hardware sector
group unp rotection feature re-en ables both program
and erase operations in previously protected sector
groups. Sector group pro tection/unprotection can b e
implemented via two methods.
Sector protection/unprotection requires VID on the RE-
SET# pin only, and can be implemented either in-sys-
tem or via programming equipment. Figure 2 shows
the algorithms and F igure 24 shows the timing dia-
gram. This method uses standard microprocessor bus
cycle timing. For sector group unprotect, all unpro-
tected sector groups must first be protected prior to
the first sector g r oup unprotect write cycle.
The device is shipped with all sector groups unpro-
tected. AMD offers the option of prog r amming and pro-
tecting sector g roups at its factory prior to shipping the
device through AMD’s ExpressFlash™ Service. Con-
tact an AMD representative for details.
It is poss ible to deter mine whether a sector group is
protected or unprotected. See the Autoselect Mode
section for details.
Table 4. Sector Group Protection/Unprotection
Address Table
Sector Group A20–A15
SA0 000000
SA1 000001
SA2 000010
SA3 000011
SA4–SA7 0001xx
SA8–SA11 0010xx
SA12–SA15 0011xx
SA16–SA19 0100xx
SA20–SA23 0101xx
SA24–SA27 0110xx
SA28–SA31 0111xx
SA32–SA35 1000xx
SA36–SA39 1001xx
SA40–SA43 1010xx
SA44–SA47 1011xx
SA48–SA51 1100xx
SA52–SA55 1101xx
SA56–SA59 1110xx
SA60 111100
SA61 111101
SA62 111110
SA63 111111
February 12, 2004 Am29LV320MH/L 17
PRELIMINARY
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting the first or last sector without
using VID. Write Protect is one of two functions pro-
vided by the WP#/ACC input.
If th e system assert s V IL on the WP#/ACC pin, the de-
vice disables program and erase functions in the first
or last sector independently of whether those sectors
were protecte d or unprotected using the method de-
scribed in “Sector Group Pr otectio n and Unprote ction”.
Note that if W P#/ACC is at VIL w hen the device is in
the stan dby mode, the m aximum in put load curren t is
increased. See the table in “DC Characteristics”.
If the system a sserts VIH on the WP#/ACC pin, the de-
vice rever ts to whether the first or last sector was pre-
viously set to be protected or unprotected using the
method described in “Sector Group P rotection and
Unprotection”.
Note: No external pullup is necessar y
since the WP#/ACC pin has internal pullup to V
CC
.
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent
sectors that are protected or unprotected at the same time
(see Table 4).
This feature allows temporary unprotection of prev i-
ously protected sector groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated by
setting the RESET# pin to VID. During this mode, for-
mer ly protected sector groups can be pro grammed o r
erased by selecting the sector group addresses. Once
VID is remov ed from the RESET# pin, all the prev iously
protected sec tor groups are protected again. Figu re 1
shows the al gor ithm, and Fi gure 2 3 shows the tim ing
diagrams, for this feature.
Figure 1. Temporar y Sector Group
Unprotect Operation
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unp rotect
Complet ed (No te 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sector groups unprotected (If WP# = V
IL
,
the first or last sector will remain protected).
2. All previously protected sector groups are protected
once again.
18 Am29LV320MH/L February 12, 2004
PRELIMINARY
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up sector
group address
Wait 150 µs
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Read from
sector group address
with A6–A0
= 0xx0010
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Group
Protect complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No
Sector Group
Unprotect:
Write 60h to sector
group address with
A6–A0 = 1xx0010
Set up first sector
group address
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6–A0 = 1xx0010
Read from
sector group
address with
A6–A0 = 1xx0010
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
group
verified?
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Group Unprotect
Mode
No All sector
groups
protected?
Yes
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
Set up
next sector group
address
No
Yes
No
Yes
No
No
Yes
No
Sector Group
Protect
Algorithm
Sector Group
Unprotect
Algorithm
First Write
Cycle = 60h?
Protect
another
sector group?
Reset
PLSCNT = 1
February 12, 2004 Am29LV320MH/L 19
PRELIMINARY
SecSi (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Silicon) Sector fe ature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, an d
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a f actory locke d part. This ensures the secu-
rity of the ES N once the produc t is s hipped to the field.
AMD offers the device with the SecSi Sector either
custo mer lockable (standar d shipping optio n) or fac-
tory locked (contact an AMD sales representative for
ordering information). The customer-lockable version
is shipped with the SecSi Sector unprotected, allowing
customers to program the sector after receiving the
device. The customer-lockable version also has the
SecSi Sector Indicator Bit permanently set to a “0.”
The factory-lo cked versio n is always protected whe n
shipped from the factory, and has the SecSi (Secured
Silicon) Sector Indicator Bit permanently set to a “1.”
Thus, the SecSi Sector Indicator Bit prevents cus-
tomer-lockabl e devices from being used to replace de-
vices that are factory locked.
Note that the ACC
functi on and un lock bypass m odes are not ava ilable
when the SecSi Sector is enabled.
The SecSi sec tor address space in this device is allo-
cated as follows:
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After th e sys tem
has written the Enter SecSi Sector command se-
quence, it may read the SecSi Sector by using the ad-
dresse s nor mally oc cupied by the firs t sector (SA0 ).
This mode of operation continues until the system is-
sues the Exit SecSi S ector command sequence, or
until power is rem oved from the device. On power-up,
or following a hardware reset, the device rever ts to
sending commands to sector SA0.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
Unless otherwise specified, the device is s hipped such
that the customer may program and protect the
256-byte SecSi sector.
The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass meth-
ods, in addition to the standard programming com-
mand sequence. See Command Definitions.
Progr amming and pr otectin g th e SecSi Se ctor m ust be
used with caution since, once protected, there is no
proced ure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
The Sec Si Sector area can be pro tected using one of
the following procedures:
■Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, ex-
cept that
RESET# may be at either V
IH
or V
ID
. This
allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that thi s method is only applicable t o the SecSi
Sector.
■To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 3.
Once th e SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In devices with an ESN, the SecSi Sector is protected
when the de vice is shipped from the factory. The S ecSi
Sector canno t be m odified in any way. An ES N Factory
Locked device has an 16-byte random ESN at ad-
dresses 000000h–000007h. Please contact your local
AMD sales represe ntative for details on ordering ESN
Factory Locked devices.
Customers may opt to have their code programmed b y
AMD through the AMD ExpressFlash service (Express
Flash Fac tor y Locked). Th e devices are the n ship ped
from AMD’s fact ory with the SecSi Sector permanently
locked. Contact an AMD representative for details on
using AMD’s ExpressFlash service.
Table 5. SecSi Sector Contents
SecS i Sect or
Add r ess Range Customer
Lockable ESN Factory
Locked ExpressFlash
Factory Locked
000000h–000007h Determined by
customer
ESN ESN or
determined by
customer
000008h–00007Fh Unavailable Determined by
customer
20 Am29LV320MH/L February 12, 2004
PRELIMINARY
Figure 3. SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provide s data protectio n
against inadver tent writes (refer to Tables 10 and 11
for command definitions). In addition, th e following
hardware data protection measures pre vent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Low V CC Write Inhibit
When VCC is les s than VLKO, the device does not ac-
cept any write cycles. This protects data dur ing VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical In hibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE # = VIH. To initiate a write cycle,
CE# and WE # must be a logical zero while OE# is a
logical one.
Po wer-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH duri ng power up,
the device does not accept commands on the rising
edge of WE #. The inter nal state mac hine is automati-
cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI inf ormation at the addresses
given in Tables 6–9. To ter minate reading CFI data,
the system must write the reset command.
The system can als o write the CFI quer y command
when the device is in the autoselect mode. The device
enters the CFI quer y mode, and the system can read
CFI data at the addresses given in Tables 6–9. The
system must write the reset command to return the
device to reading array data.
For fur ther information, please refer to the CFI Specifi-
cation and CFI Pub licatio n 100, a vailable via the W orld
Wide Web at http://www.a md.com/f lash/cfi. A lterna-
tively, contact an AMD representative for copies of
these documents.
Write 60h to
any address
Write 40h to SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
START
RESET# =
V
IH
or V
ID
Wait 1 µs
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Remove V
IH
or V
ID
from RESET#
Write reset
command
SecSi Sector
Protect Verify
complete
February 12, 2004 Am29LV320MH/L 21
PRELIMINARY
Table 6. CFI Query Identification String
Table 7. System Interface String
Addresses
(x16) Addresses
(x8) Data Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h Query Unique ASCII string “QRY”
13h
14h 26h
28h 0002h
0000h Primary OEM Command Set
15h
16h 2Ah
2Ch 0040h
0000h Address for Primary Extended Table
17h
18h 2Eh
30h 0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah 32h
34h 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
Addresses
(x16) Addresses
(x8) Data Description
1Bh 36h 0027h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 38h 0036h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 3Eh 0007h Typical timeout per single byte/word write 2N µs
20h 40h 0007h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 42h 000Ah Typical timeout per individual block erase 2N ms
22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 46h 0001h Max. timeout for byte/word write 2N times typical
24h 48h 0005h Max. timeout for buffer write 2N times typical
25h 4Ah 0004h Max. timeout per individual block erase 2N times typical
26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
22 Am29LV320MH/L February 12, 2004
PRELIMINARY
Table 8. Device Geometry Definition
Addresses
(x16) Addresses
(x8) Data Description
27h 4Eh 0016h Device Size = 2N byte
28h
29h 50h
52h 0002h
0000h Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh 54h
56h 0005h
0000h Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch 58h 0001h Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
003Fh
0000h
0000h
0001h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
February 12, 2004 Am29LV320MH/L 23
PRELIMINARY
Table 9. Primary Vendor-Specific Extended Query
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates de vice op-
erations. Tables 10 and 11 define the va lid register
comm and sequences.
Writi ng incorrect ad dress and
data values or writing them in the improper sequence
may place the device in an unknown sta te. A reset
command is then required to return the device to read-
ing array data.
All addresses are latched on the falling edge of WE#
or CE#, whiche ver happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retri eve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
Addresses
(x16) Addresses
(x8) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 86h 0031h Major version number, ASCII
44h 88h 0033h Minor version number, ASCII
45h 8Ah 0008h Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit
46h 8Ch 0002h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h Sector Pro tect
0 = Not Supported, X = Number of sectors in per group
48h 90h 0001h Sector Temporar y Unprotect
00 = Not Supported, 01 = Supported
49h 92h 0004h Sector Pro tect /Un pro tec t schem e
04 = 29LV800 mode
4Ah 94h 0000h Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Bh 96h 0000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 98h 0001h Page Mode Type
00 = Not Supported, 01 = 4 Word/8 Byte Page, 02 = 8 Word/16 Byte Page
4Dh 9Ah 00B5h ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Vo lt, D3-D0: 100 mV
4Eh 9Ch 00C5h ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Vo lt, D3-D0: 100 mV
4Fh 9Eh 0004h/
0005h
Top/Bottom Boot Sector Flag
00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top
Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top
WP# protect
50h A0h 0001h Program Suspe nd
00h = Not Supported, 01h = Supported
24 Am29LV320MH/L February 12, 2004
PRELIMINARY
which the system can read data from any
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system
must
issue the reset command to retur n
the de vice to the read (or eras e-suspend-read) mode if
DQ5 goes high dur ing an active program or erase op-
eration, or if the device is in the autoselect mode. See
the next section, Reset Command, for more infor ma-
tion.
See also Requirements for R eading Array Data in the
Device Bus Operations section for more information.
The Read-Only Oper ation s table provides the read pa-
rameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the
read o r erase-sus pend-read mode. Addres s bits are
don’t cares for this command.
The rese t command may be written b etween the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to the read
mode. Once e rasure begin s, however, th e dev ice ig-
nores reset commands until the operation is complete .
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
the read mode. If the p rogram comm and seque nce is
written while the device is in the Eras e Su spend mode ,
writing the reset command retur ns the device to the
erase-suspend-read mode. Once programming be-
gins, however, the device ignores reset commands
until the operation is complete.
The rese t command may be written b etween the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice ente red the autoselec t mode whil e in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command retur ns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Note tha t if DQ 1 goes high dur ing a W rite Buffer Pro-
gramming operation, the system must write the
Write-to-Buffer-Abort Reset comm and sequence to
reset the device for the next operation.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to read several identifier codes at specific ad-
dresses:
Note: The device ID i s read o ver three cy cles. SA = Sector
Address
Tables 10 and 11 show the address requirements and
codes. This method is an alternative to that shown in
Table 3, which is intended for PROM programmers
and requires VID on address pin A9. The autoselect
command sequence may be written to an a ddress that
is either in the read or erase-suspend-read mode. The
autoselect com mand may not be written while the de-
vice is activ ely prog ramming or erasing.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autos elect command sequence:
The system must write the reset command to return to
the read mode (or erase-su spend-read mode if the de-
vice was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing an 8-word/16-byte r andom Electronic Serial
Number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector command sequence. The device continues to
access the SecSi Sector region until the system is-
sues the four-cycle Exit SecSi Sector command se-
quence. The Exit SecSi Sector command sequence
retur ns the device to nor mal operation. Tables 10 and
11 show the address and data requirements for both
command sequences. See also “SecS i (Secur ed Sili-
con) Sector Flash Memory Region” for furt her in fo rma -
tion.
Note that the ACC function and unlock bypass
modes are not available when the SecSi Sector is en-
abled.
Word/Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
comma nd. The program address and data are wr itten
Identifier Code A7:A0
(x16) A6:A-1
(x8)
Manufacturer ID 00h 00h
Device ID, Cycle 1 01h 02h
De vi ce ID, Cy cl e 2 0Eh 1Ch
De vi ce ID, Cy cl e 3 0Fh 1Eh
SecSi Sector Factory Protect 03h 06h
Sector Protect Verify (SA)02h (SA)04h
February 12, 2004 Am29LV320MH/L 25
PRELIMINARY
next, which in turn initiate the Embedded Program al-
gorithm. The system is
not
required to provide fur the r
controls or timings. The device automatically provides
inter nally generated program pulses an d verifies the
programmed cell margin. Tables 10 and 11 sh ow the
addres s and data re quiremen ts for the word/byte pro-
gram com mand se quence, re spectively.
Note th at the
SecSi Sector, autoselect, and CFI functions are un-
available when a program operat ion is in progress.
When the E mbedd ed Program a lgor ithm is comple te,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7 or DQ6. Refer to the Write Operation Status sec-
tion for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note tha t a
hardware res et immediately term inates the program
operation. The program command sequence should
be reinitiated once the dev ice has returned to the read
mode, to ensure data int egrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indic ate the operation was suc-
cessful. Howe ver , a succeeding read will show that the
data is still “0.” Only erase operatio ns can con vert a “0”
to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the stan-
dard progr am command sequence . Th e unloc k bypass
command sequenc e is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence c ontains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
comm and sequence, resu lting in faster total program-
ming time. Tables 10 and 11 show the r equirements
for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program a nd Unlock Bypass Reset c ommands
are valid. To ex it the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
Write Buffer Programming
Write Buff er Programming all ows the system write to a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effec tive programming
time than the standard programming algor ithms. The
Write Buffer Programming command sequence is initi-
ated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which pro-
gramming will occur. The fourth cycle writes the sector
address and the number of word locations, minus one,
to be programmed. For example , if the system will pro-
gram 6 uni que addre ss lo cations, then 05 h shoul d be
written to the device. This tells the device how many
write buffer addresses will be loaded with data and
therefore when to expect the Pro gram Buffe r to Flash
command. The number of locations to program cannot
exceed the size of the write buffer or the operation will
abort.
The fifth cycle writes the first address location and
data to be programmed. The write-buffer-page is se-
lected by address bits AMAX–A4. All subsequent ad-
dress/data pairs must fall within the
selected-write-buffer-page. The system then writes the
remaining address/data pairs into the write buffer.
Write buffer locations may be loaded in any order.
The wr ite-buffer -page address must b e the same for
all address/data pairs loaded into the write buffer.
(This means Write Buffer Programming cannot be per-
formed across multiple write-buffer pages. This also
mean s that W rite Buffer Programming cannot be per-
form ed across multiple sectors. If the system attempts
to load programming data outside of the selected
write-buffer page, the operation will abort.
Note that if a Write Buffer address location is loaded
multiple times, the address/data pair counter will be
decremented for every data load operation. The host
system must therefore account for loading a
write-buffer location more than once. The counter dec-
rements for each data load operation, not for each
unique write-buffer-address location. Note also that if
an address location is loaded more than onc e into the
buffer, the final data loaded for that address will be
programmed.
Once the specified number of write buffer locations
have been loaded, the system m ust then write t he Pro-
gram Buffer to Flash comman d at the sector addr ess.
Any other address and data combination aborts the
Write Buff er Progr amming ope rat ion. The device then
begins programming. Data polling should be used
while monito ring the last a ddress location loaded into
the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write
Buffer Programming.
26 Am29LV320MH/L February 12, 2004
PRELIMINARY
The wr ite-buffer programming o peration can be sus -
pended using the standard program suspend/resume
commands. Upon successful completion of the Write
Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be
aborted in the f ollowing ways:
■Load a value that is greater than the page buffer
size during the Number of Locations to Program
step.
■Write to an address in a sector different than the
one specified during the Write-Buffer-Load com-
mand.
■Write an Address/Data pair to a different
write-buffer-page than the one selected by the
Starting Address during the write buffer data load-
ing stage of the operation.
■Write data other than the Confirm Command after
the specified number of data load cycles.
The ab ort condition is indicated by DQ1 = 1, DQ7 =
DATA# (for the la st addres s location l oaded), DQ 6 =
toggle, and DQ5=0. A Write-to-Buffer-Abor t Reset
command sequen ce must be written to reset the de-
vice for the next operation. Note that the full 3-cycle
Write-to-Buffer-Abort Reset command sequence is re-
quired when using Wr ite-Buffer-Programming features
in Unlock Bypass mode.
Accelerated Program
The device offers accelerated program operations
through the WP#/ACC pin. When the system asser ts
VHH on the WP#/ACC pin, the device automatic ally en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC p in to acce lerate the operati on.
Note th at
the
WP#/
ACC pin must not be at V
HH
for operations
other than accelerated programming, or dev ice dam-
age may result. In addition, no external pullup is nec-
essary since the WP#/ACC pin has internal pullup to
V
CC
.
Figure 5 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 17 for timing diagrams.
February 12, 2004 Am29LV320MH/L 27
PRELIMINARY
Figure 4. Write Buffer Programming Operation
Write “Write to Buffer”
command and
Sector Address
Write number of addresses
to program minus 1(WC)
and Sector Address
Write program buffer to
flash sector address
Write first address/data
Write to a different
sector address
FAIL or ABORT PASS
Read DQ7 - DQ0 at
Last Loaded Address
Read DQ7 - DQ0 with
address = Last Loaded
Address
Write next address/data pair
WC = WC - 1
WC = 0 ?
Part of “Write to Buffer”
Command Sequence
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Abort Write to
Buffer Operation?
DQ7 = Data?
DQ7 = Data?
DQ5 = 1?DQ1 = 1?
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
to read mode.
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
2. DQ7 ma y change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3. If this flowchart location was reached because
DQ5= “1”, then the device F AILED. If this flowchart
location was reached because DQ1= “1”, then the
Write to Buff er operation w as ABOR TED. In either
case, the proper reset command must be written
before the device can begin another operation. If
DQ1=1, write the
Write-Buffer-Programming-Abort-Reset
command. if DQ5=1, write the Reset command.
4. See Table 11 for command sequences required for
write buffer programming.
(Note 3)
(Note 1)
(Note 2)
28 Am29LV320MH/L February 12, 2004
PRELIMINARY
Figure 5. Program Operation
Program Suspend/Program Resume
Command Sequence
The Program Suspend command allow s the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Sus-
pend command is written during a programm ing pro-
cess, the device halts the program operation within 15
µs (maximum) 5µs typical and updates the status bits.
Addresses are not requir ed when writing the Pro gram
Suspend command.
After the programming operation has been sus-
pended, the system can read array data from any
non- suspend ed sec tor. T he Program Susp end com-
mand may also be issued during a programming oper-
ation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Sus-
pend or Program Suspend. If a read is needed from
the SecSi Sector are a (One-time Program area), then
user must use the proper command sequences to
enter and exit this region.
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autos elect codes
as required. When the device exits the autoselect
mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.
After the Program Resume command is written, the
device rever ts to programming. The system can deter-
mine the status of the pro gram operation using the
DQ7 or DQ6 status bits, just as in the standard pro-
gram operat ion. See Wr ite Operation Status for mo re
information.
The system must write the Program Resume com-
mand (address bits are don’t care) to exit the Program
Suspend mod e and continue the programming opera-
tion. Fu rt her wr ites of the Res ume comm and are ig-
nored. Another Program Suspend command can be
written after the device has resume programming.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note: See Tables 10 and 11 for program command
sequence.
February 12, 2004 Am29LV320MH/L 29
PRELIMINARY
Figure 6. Program Suspend/P rogram Resume
Chip Erase Command Sequence
Chip erase is a si x b us cy cle oper ation. The chip er ase
command sequence is initiated by writing two unlock
cycles, fo llowed by a set-up command. Two additional
unlock write cycles ar e then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogr am prior to eras e. The Embedded Erase algo-
rithm automatically preprogr ams a nd v erifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not requ ired to provide any con-
trols or timings during these operations. Tables 10 and
11 show the address and data requirements for the
chip erase com mand sequence.
Note that the SecSi
Sector, autoselect, and CFI functions are unavailable
when a erase operation is in prog ress.
When the Embedded Erase algorithm is complete, the
device retu rns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2.
Refer to the Write Operation Status s ec t i on fo r in fo r-
mation on these status bits.
Any commands written during the chip er as e oper ation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device has re turned to reading
array data, to ensure data integrity.
Figure 7 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 19 section for timing diagr ams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector eras e command. Tab les 10 and 11 show the
address and data requirements for the sector erase
command sequence.
Note that the SecSi Sector, au-
toselect, an d CFI functions are unavailable when a
erase operation is in progress.
The device does
not
require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifi es the entire m emor y for
an all zero data patter n prior to electr ical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector er ase
time-out of 50 µs occurs. During the time-out period,
additio nal sector addre sses and secto r erase com -
mands may be written. Loading t he sector erase buffer
ma y be done in any sequence , and the number of sec-
tors may be from one sector to all sectors. The time
between these addition al cycles must be les s than 50
µs, ot herwise er asure may begin. Any sect or eras e ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disab led during this ti me to en-
sure all comm ands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out p eriod resets
the device to the read mode. The system must re-
write the command sequence and any additional ad-
dresses and commands.
The sy stem can mon itor DQ3 to deter mine if the s ec-
tor er ase ti mer has timed out (See the section o n DQ3:
Sector Erase Timer.). The time-out begins from the ris-
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- o
r
program-suspended sectors
Write Program Resume
Command Sequence
Read data as
required
Done
reading?
No
Yes
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Write address/data
XXXh/B0h
Wait 15 µs
30 Am29LV320MH/L February 12, 2004
PRELIMINARY
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can deter mine the
status of the erase operation by reading DQ7, DQ6, or
DQ2 in the erasing sector. Refer to the W rite Opera-
tion Status section for information on these status bits .
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately ter minates the erase op eration. If
that occurs, the sector erase command sequence
should be reinitiated once the dev ice has returned to
reading array data, to ensure data integrity.
Figure 7 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and Figure 19 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase oper ation and then read
data from, or program data to, any sector not selected
f or erasure . This command is valid only during the sec-
tor erase operation, includi ng the 50 µs time -out pe-
riod dur ing the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase ope ration, the device requires a typ i-
cal of 5 µs (maximum of 20 µs) to suspend the erase
operation. However, when the Erase Suspend com-
mand is written during the sector erase time-out, the
device immediately terminates the time-out period and
suspends the erase oper ation.
After the erase operation has been suspended, the
device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determ ine
if a sector i s actively erasing or is eras e-suspended.
Refer to th e Write Operation Status section for infor-
mation on these status bits.
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
mode. The system can deter mine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard word program operation.
Refer t o the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip
has resumed erasing.
Note: During an erase operation, this flash device per-
forms multiple inter nal operations w hich are invisible
to the syst em. When an eras e oper ation is susp ended,
any of the inter nal op erations that were n ot fully com-
pleted must be restarted. As such, if this flash device
is continually issued suspend/resume commands in
rapid succession, erase progress will be impeded as a
function of the number of suspends. The result will be
a longer cumulative erase time than without suspends.
Note that the additional suspends do not affect device
reliability or future performance. In most systems rapid
erase/suspend activity occurs only briefly. In such
cases, erase performance will not be significantly im-
pacted.
Figure 7. Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
Notes:
1. See Tables 10 and 11 for erase command sequence.
2. See the section on DQ3 for information on the se ctor
erase timer.
February 12, 2004 Am29LV320MH/L 31
PRELIMINARY
Command Definitions
Table 10. Command Definitions (x16 Mode, BYTE# = VIH)
Legend:
X = Don’t care
RA = Read Address of memory location to be rea d.
RD = R ead D a t a read fr om loc ation RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or CE#
pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of WE#
or CE # puls e, whic heve r happens firs t .
SA = Sector Address of sec tor to be verified (in autoselec t mode ) or
erased. Address bits A20–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write buffer
page as PA.
WC = Wo rd Co unt. Nu mber of write buff e r location s to load mi n u s 1.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in he x adecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when low er address bits are
555 or 2AA as shown in table , address bits above A11 and data
bits above DQ 7 are don’t care.
5. No unlock or command cycles required when de v ice is in read
mode.
6. Reset command is required to return to read mode (or to
erase-suspend-read mode if prev iously in Erase Suspend) when
dev ice is in autoselect mode, or if DQ5 goes high while device is
providing status information.
7. Fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD,
and WC. See Autoselect Command Sequence section for more
information.
8. Device ID must be read in three cycles.
9. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector , data is 88h for f ac tory locked and 08h for not
f actor loc k ed.
10. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
11. Total number of cycles in command sequence is determ ined by
number of words written to write buffer. Maximum number of
cycles in command sequence is 21.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. Unlock Bypass command is required prior to Unlock Bypass
Program command.
14. Unlock Bypass Reset command is required to return to read
mode when device is in unlock bypass mode.
15. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
16. Erase Resume command is valid only during Erase Suspend
mode.
17. Command is valid when device is ready to read array data or when
devic e is in auto s elect mode .
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Autoselect (Note 7)
Manufac turer ID 4 555 AA 2AA 55 555 90 X00 0001
Device ID (Note 8) 6 555 AA 2AA 55 555 90 X01 227E X0E XX1D X0F XX00
SecSi™ Sector Factory Protect
(Note 9) 4 555 AA 2AA 55 555 90 X03 (Note 9)
Sector Group Protect Verify
(Note 10) 4 555 AA 2AA 55 555 90 (SA)X02 00/01
Enter SecSi Sector Region 3 555 AA 2AA 55 555 88
Exit SecSi Sector Region 4 555 AA 2AA 55 555 90 XXX 00
Program 4 555 AA 2AA 55 555 A0 PA PD
Write to Buffer (Note 11) 6 555 AA 2AA 55 SA 2 5 SA WC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort Reset (Note 12) 3 555 AA 2AA 55 555 F0
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass Program (Note 13) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 14) 2 XXX 90 XXX 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Program/Erase Suspend (Note 15) 1 XXX B0
Program/Erase Resume (Note 16) 1 XXX 30
CFI Query (Note 17) 1 55 98
32 Am29LV320MH/L February 12, 2004
PRELIMINARY
Table 11. Command Definitions (x8 Mode, BYTE# = VIL)
Legend:
X = Don’t care
RA = Read Address of memory location to be rea d.
RD = R ead D a t a read fr om loc ation RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or CE#
pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of WE#
or CE # puls e, whic heve r happens firs t .
SA = Sector Address of sec tor to be verified (in autoselec t mode ) or
erased. Address bits A20–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write buffer
page as PA.
BC = Byte Count. Number of write buff e r loca tion s to load mi n u s 1.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in he x adecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when low er address bits are
555 or AAA as shown in table , address bits above A11 are don’t
care.
5. Unless otherwise noted, address bits A20–A11 are don’t cares.
6. No unlock or command cycles required when de v ice is in read
mode.
7. Reset command is required to return to read mode (or to
erase-suspend-read mode if prev iously in Erase Suspend) when
dev ice is in autoselect mode, or if DQ5 goes high while device is
providing status information.
8. Fourth cycle of autoselect command sequence is a read cycle.
Data bits DQ15–DQ8 are don’t care. See Autoselect Command
Sequence section or more information.
9. Device ID must be read in three cycles.
10. If WP# protects highest address sector , data is 98h for f ac tory
locked and 18h for not factory locked. If WP# protects lowest
address sector , data is 88h for f ac tory locked and 08h for not
f actor loc k ed.
11. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
12. Total number of cycles in command sequence is determ ined by
number of words written to write buffer. Maximum number of
cycles in command sequence is 21.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
14. Unlock Bypass command is required prior to Unlock Bypass
Program command.
15. Unlock Bypass Reset command is required to return to read
mode when device is in unlock bypass mode.
16. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
17. Erase Resume command is valid only during Erase Suspend
mode.
18. Command is valid when device is ready to read array data or when
devic e is in auto s elect mode .
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect (Note 8)
Manufac turer ID 4 AAA AA 555 55 AAA 90 X00 01
Device ID (Note 9) 6 AAA AA 555 55 AAA 90 X02 7E X1C 1D X1E 00
SecSi™ Sector Factory Protect
(Note 10) 4 AAA AA 555 55 AAA 90 X06 (Note 10)
Sector Group Protect Verify
(Note 11) 4 AAA AA 555 55 AAA 90 (SA)X04 00/01
Enter SecSi Sector Region 3 AAA AA 555 55 AAA 88
Exit SecSi Sector Region 4 AAA AA 555 55 AAA 90 XXX 00
Program 4 555 AA 2AA 55 555 A0 PA PD
Write to Buffer (Note 12) 6 AAA AA 555 55 SA 25 SA BC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort Reset (Note 13) 3 AAA AA 555 55 AAA F0
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass Program (Note 13) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 15) 2 XXX 90 XXX 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30
Program/Erase Suspend (Note 16) 1 XXX B0
Program/Erase Resume (Note 17) 1 XXX 30
CFI Query (Note 18) 1 AA 98
February 12, 2004 Am29LV320MH/L 33
PRELIMINARY
WRITE OPERATION STATUS
The de vice pro vides se ver al bits to det ermine the status of a
program o r erase operati on : DQ 2, D Q 3 , D Q5, D Q6, and
DQ7. Table 12 and the following subsect i ons de scribe the
function of these bits. DQ7 and DQ6 each off er a method f or
determining whether a progr am or erase operation is com-
plete or in progress. The device al s o provides a ha r d-
ware-based output signal, RY/BY#, to determine
whether an Em bedded Program or Erase operation is
in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whe t he r an Embe dd ed Pr ogram o r Erase algo rithm i s i n
progress or com pleted , or whe ther the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the c ommand sequence .
During the Embedded Program algorithm, th e device out-
puts on DQ7 the compleme nt of the datum pro g r ammed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The s ystem must provide the program address to
read v alid stat us inf ormation on DQ7. If a prog ram addres s
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, then the device returns to the
read mode .
Dur ing th e Embe dded Eras e alg orithm , Data# Po lling
produc es a “0” on DQ 7. When the Embed ded Erase
algorithm is complete, or if the de vice enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
secto rs select ed for erasur e to read valid s tatus infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active f or appro ximately 100 µs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected se ctors tha t are protec ted. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 out put, it may read
the status or valid data. Even if the device has c om-
pleted the program or erase ope ration and DQ7 h as
valid data, the data outputs on DQ0– DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on suc-
cessiv e read cycles.
Table 12 shows the outputs fo r Data# Po lling on DQ7 .
Figure 8 shows the Data# Polling algorithm. Figure 20
in the AC Characteristics secti on shows the Data#
Polling timing diagram.
Figure 8. Data# Polling Algorithm
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
34 Am29LV320MH/L February 12, 2004
PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Em bedded Algorith m is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output , sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or in the erase-suspend -read mode. Table 12
sho ws the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation ), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, succe ssive read cycles to any address caus e
DQ6 to toggle. The system may use either OE# or
CE# to control the read c ycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for eras ing ar e pr ot ect ed, DQ 6 tog gle s for approxi-
mately 100 µs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sector s, and ignores the se-
lected sec tors tha t are protec ted.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively er asing or is erase-suspended.
When the device is activ ely eras ing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the de-
vice enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine
which sectors are erasing or erase-suspended. Alterna-
tively, the system can use DQ7 (see the subsection on
DQ7: Data# Polling ).
If a program address falls with in a protected sect or,
DQ6 toggle s for approximately 1 µs after the p rogram
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 12 shows the outputs for Tog gle Bit I on DQ6 .
Figure 9 shows the toggle bit algorithm. Figure 21 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 22 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
February 12, 2004 Am29LV320MH/L 35
PRELIMINARY
Figure 9. Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the Embedded Er ase algo rithm is in progr ess),
or whether that s ector is erase-sus pended. Toggle Bit
II is valid afte r the risi ng edge of the final WE# pu lse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whet her the sector i s actively erasing or is erase-sus -
pended. D Q6, by comparis on, indicates whe ther the
device is actively erasing, or is in E rase Suspend, but
canno t distin guish whic h sectors are sel ected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 12 to compare out-
puts for DQ2 and DQ6.
Figure 9 shows the toggle bit algorithm in flowchart
form , and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the RY/BY#: Ready/Busy# sub-
section. Figure 21 sho ws t he togg le bit timing diag r am.
Figure 22 shows the differences between DQ2 and
DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 9 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note an d store the value of the tog-
gle bit after the first read. After the second re ad, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
deter mines that the toggle bi t is still tog gling, the sys-
tem also should note whether the v alue of DQ5 is high
(see the section on DQ5). If it is, the system should
then de termine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase oper ation . If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, deter mining the status as describ ed in the previ-
ous paragraph. Alternatively, it may choose to perfor m
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle? No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Note: The system should recheck the toggle bit even if
DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” S ee the sub sections on D Q6 and DQ 2 for
more informat ion .
36 Am29LV320MH/L February 12, 2004
PRELIMINARY
other system tasks. In this case, the system m ust start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 9).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse coun t limit . Under these condi tions DQ5 produces a
“1,” indicating that the program or erase cycle was not suc-
cessfully completed.
The de vice may output a “1” on DQ5 if the system tries
to program a “1” to a location that wa s previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and w hen the timing lim it
has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-prog ram mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies af ter each a dditional sector eras e com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector er ase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (D ata# Polling) or DQ 6
(Toggle Bit I) to ensure that the device has accepted
the command sequence , and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept a dditional secto r erase co mmands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If D Q3 is high on the seco nd status c heck, the
last command might not have been accepted.
Table 12 show s the status of DQ3 relative to the other
status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 produces a
“1”. The system must issue the
Write-to-Buff er-Abort-Reset command sequence to re-
turn the device to reading array data. See Write Buffer
Table 12. W rite Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a v ali d address when r eading s tatus information. Refer to the appropriate subse ction f o r further details.
3. The Data# P oll ing a lgorithm shoul d be use d to moni tor the l ast l oaded write-buffer addr ess loc ation.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
Status DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2) DQ1 RY/BY#
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0 0
Embedded Erase Algorithm 0 Toggle 0 1 Toggle N/A 0
Program
Suspend
Mode
Program-
Suspend
Read
Program-Suspended
Sector Invalid (not allowed) 1
Non-Program
Suspended Sector Data 1
Erase
Suspend
Mode
Erase-
Suspend
Read
Erase-Suspended
Sector 1 No toggle 0 N/A Toggle N/A 1
Non-Erase Suspended
Sector Data 1
Erase-Suspend-Program
(Embedded Program) DQ7# Toggle 0 N/A N/A N/A 0
Write-to-
Buffer Busy (Note 3) DQ7# Toggle 0 N/A N/A 0 0
Abort (Note 4) DQ7# Toggle 0 N/A N/A 1 0
February 12, 2004 Am29LV320MH/L 37
PRELIMINARY
ABSOLUTE MAXIM UM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150 °C
Ambient Temperat ure
with Power Applied. . . . . . . . . . . . . . –65°C to + 125°C
Voltage with Respec t to Ground
VCC ( N o te 1 ) . . . . . . . . . . . . . . . . .–0.5 V to +4. 0 V
VIO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, ACC, and RESET#
(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot V
SS
to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is V
CC
+0.5 V.
See Figure 10. During voltage transitions, input or I/O
pins may ov ershoot to V
CC
+2.0 V for periods up to 20 ns.
See Figure 11.
2. Minimum DC input voltage on pins A9, OE#, ACC, and
RESET# is –0.5 V. During voltage transitions, A9, OE#,
ACC, and RESET# may overshoot V
SS
to –2.0 V for
periods of up to 20 ns. See Figure 10. Maximum DC
input voltage on pin A9, OE#, ACC, and RESET# is
+12.5 V which may overshoot to +14.0 V for per iods up
to 20 ns.
3. No more tha n one outpu t may be shor te d to ground at a
time. Duration of the sh or t circuit s hould not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional op eration of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperat ure ( TA) . . . . . . . . . –40°C to +85°C
Su p p ly Volt ages
VCC full voltage range. . . . . . . . . . . . . . . . . . 2.7–3.6 V
VCC regulated voltage range . . . . . . . . . . . . 3.0–3.6 V
VIO (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1.65–3.6 V
Notes:
1. Operating ranges define those limits between which the
functionality of the device is guaranteed.
2. See Ordering Information section fo r valid V
CC
/V
IO
range
combinations. The I/Os will not operate at 3 V when V
IO
=
1.8 V.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 10.
Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 11.
Maximum Positive
Overshoot Waveform
38 Am29LV320MH/L February 12, 2004
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = V
IL
is ± 5.0 µA.
2. The I
CC
current listed is t ypical ly l ess t han 2 mA/MHz , wit h OE# at V
IH
.
3. Maximum I
CC
specifications ar e test ed wit h V
CC
= V
CC
max.
4. I
CC
active while Embedded Erase or Embedded Progr am is in progress.
5. Automatic sleep mode enables the low po w er mode when addr esses r emain st ab l e for t
ACC
+ 30 ns. TI f V
IO
< V
CC
, maximum V
IL
f or CE# and DQ I /Os is 0.3 V
IO
. If V
IO
< V
CC
, minimum V
IH
for CE# and DQ I/Os is 0. 7 V
IO
. Maximum V
IH
for these connectio ns is
V
IO
+ 0.3 V
6. V
CC
vol tage re quirement s .
7. V
IO
volt age requi rements.
8. Not 100% tested.
9. Includes RY/BY#
Parameter
Symbol Parameter Description
(Notes) Test Conditions Min Typ Max Unit
ILI Input Load Current (1) VIN = VSS to VCC,
VCC = VCC max ±1.0 µA
ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILR Reset Leakage Current VCC = VCC max; RESET# = 12.5 V 35 µA
ILO Output Lea ka ge Cur r en t VOUT = VSS to VCC,
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current
(2, 3) CE# = VIL, OE# = VIH, 5 MHz 3 34 mA
1 MHz 13 43
ICC2 VCC Initial Page Read Current (2, 3) CE# = VIL, OE# = VIH 1 MHz 4 50
mA10 MHz 40 80
ICC3 VCC Intra-Page Read Current (2, 3) CE# = VIL, OE# = VIH 10 MHz 3 20
33 MHz 6 40 mA
ICC4 VCC Active Write Current (3, 4) CE# = VIL, OE# = VIH 50 60 mA
ICC5 VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V,
WP# = VIH 15µA
ICC6 VCC Reset Current (3) RESET# = VSS ± 0.3 V, WP# = VIH 15µA
ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V, WP# = VIH 15µA
VIL1 Input Low Voltage 1(5, 6) –0.5 0.8 V
VIH1 Input High Voltage 1 (5, 6) 1.9 VCC + 0.5 V
VIL2 Input Low Voltage 2 (5, 7) –0.5 0.3 x VIO V
VIH2 Input High Voltage 2 (5, 7) 1.9 VIO + 0.5 V
VHH Voltage for ACC Program
Acceleration VCC = 2.7 –3.6 V 11.5 12.5 V
VID V oltage for Autoselect and T emporary
Sector Unp rot ect VCC = 2.7 –3.6 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min = VIO 0.15 x VIO V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V
VOH2 IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V
VLKO Low VCC Lock-Out Voltage (8) 2.3 2.5 V
VIL1 Input Low Voltage 1(5, 6) –0.5 0.8 V
February 12, 2004 Am29LV320MH/L 39
PRELIMINARY
TEST CONDITIONS
Table 13. Test Specifications
Note: If V
IO
< V
CC
, the reference level is 0.5 V
IO
.
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
3.3 V
Device
Under
Test
Note:
Diodes are IN3064 or equivalent
Figure 12. Test Setup
Test Condition All Speeds Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap acit anc e) 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–3.0 V
Input timing measurement
reference levels (See Note) 1.5 V
Output timing measurement
reference levels 0.5 VIO V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
3.0 V
0.0 V 1.5 V 0.5 VIO V OutputMeasurement LevelInput
Note: If V
IO
< V
CC
, the input measurement reference level is 0.5 V
IO
.
Figure 13. Input Waveforms and
Measurement Levels
40 Am29LV320MH/L February 12, 2004
PRELIMINARY
AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 13 for test specifications .
3. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation VIO
≠
VCC.
Parameter
Description Test Setup
Speed Op tion s
JEDE
C Std. 90R 101,
101R 112R 112 120R 120 Unit
tAVAV tRC Read Cycle Time (Note 1) Min 90 100 110 120 ns
tAVQV tACC Address to Output Delay CE#, OE# =
VIL Max 90 100 110 120 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 110 120 ns
tPACC Page Access Time Max 25 30 30 40 30 40 ns
tGLQV tOE Output Enable to Output Delay Max 25 30 30 40 30 40 ns
tEHQZ tDF Chip Enable to Output High Z (Note
1) Max 16 ns
tGHQZ tDF Output Enable to Output High Z
(Note 1) Max 16 ns
tAXQX tOH Output Hold Time From Addresses,
CE# or OE#, Whichev er Occurs First Min 0 ns
tOEH
Output Enable
Hold Time (Note
1)
Read Min 0 ns
Toggle and
Data# Polling Min 10 ns
tOH
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output V alid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tRH
tOE
tRH
0 V
RY/BY#
RESET#
tDF
Figure 14. Read Operation Timing
February 12, 2004 Am29LV320MH/L 41
PRELIMINARY
AC CHARACTERISTICS
* Figure shows device in word mode. Addresses are A1–A-1 for byte mode.
Figure 15. P age Read Timings
A20
-
A2
CE#
OE#
A1
-
A0*
Data Bus
Same Page
Aa Ab Ac Ad
Qa Qb Qc Qd
t
ACC
t
PACC
t
PACC
t
PACC
42 Am29LV320MH/L February 12, 2004
PRELIMINARY
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note:
1. Not 100% tested
2. AC spe c ific at i ons liste d ar e tested w it h VIO = VCC. Co ntact AMD for in formation on AC operatio n w ith VIO
≠
VCC..
Parameter
Descri ptio n All Speed Optio ns Un itJEDEC Std.
tReady RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note) Max 20 µs
tReady RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH Reset High Time Before Read (See Note) Min 50 ns
tRPD RESET# Low to Standby Mode Min 20 µs
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 16. Reset Timings
February 12, 2004 Am29LV320MH/L 43
PRELIMINARY
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Perf ormance” section f or more
information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a
16-word/32-byte write buffer operation.
5. Word/Byte programming specification is based upon a single
word/byte programming operation not utilizing the write buffer.
6. AC specifications listed are tested with VIO = VCC. Contact AMD
for information on AC operation with VIO
≠
VCC.
7. When using the program suspend/resume feat ure, if the suspend
command is issued within tPOLL, tPOLL must be fully re-applied
upon resuming the programming operation. If the suspend
command is issued after tPOLL, tPOLL is not required again prior to
reading the status bits upon resuming.
Parameter Speed Options
JEDEC Std. Description 90R 101,
101R 112,
112R 120,
120R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns
tWLAX tAH Address Hold Time Min 45 ns
tAHT Address Hold Time From CE# or OE# high
during toggle bit polling Min 0 ns
tDVWH tDS Data Setup Time Min 45 ns
tWHDX tDH Data Hold Time Min 0 ns
tOEPH Output Enable High during toggle bit polling Min 20 ns
tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns
tELWL tCS CE# Setup Time Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 35 ns
tWHDL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1
Write Buffer Program Operation (Notes 2, 3) Typ 240 µs
Effective Write Buffer Program Operation
(Notes 2, 4) Pe r B yte Typ 7.5 µ s
Pe r Word Typ 1 5 µ s
Accelerated Effectiv e Write Buff er Progr am
Operation (No tes 2, 5) Per B yte Typ 6. 25 µs
Per Word Typ 12.5 µs
Single Word/Byte Program Operation
(Notes 2, 5) Byte Typ 60 µs
Word 60
Accelerated Single Word/Byte
Programming Operation (Note 2) Byte Typ 54 µs
Word 54
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec
tVHH VHH Rise and Fall Time (Note 1) Min 250 ns
tVCS VCC Setup Time (Note 1) Min 50 µs
tVCS tBUSY WE# to RY/BY# Min 90 100 110 120 ns
tPOLL Program Valid Before Status Polling (Note 7) Max 4 µs
44 Am29LV320MH/L February 12, 2004
PRELIMINARY
AC CHARACTERISTICS
OE#
WE#
CE#
VCC
Data
Addresses
tDS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
555h PA PA
Read Status Data (last two cycles)
A0h
tCS
Status DOUT
Program Command Sequence (last two cycles)
RY/BY#
tRB
tBUSY
tCH
PA
tPOLL
N
otes:
1
. PA = program address, PD = program data, D
OUT
is the true data at the program address.
2
. Illustration shows device in word mode.
Figure 17. P rogram Operation Ti mi ng s
ACC tVHH
VHH
VIL or VIH VIL or VIH
tVHH
Figure 18. Accelerated Program Timi ng Dia gram
February 12, 2004 Am29LV320MH/L 45
PRELIMINARY
AC CHARACTERISTICS
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
tRB
tBUSY
Notes:
1. SA = sector address (f or Sector Er ase), VA = Valid Address f o r read ing st atus dat a (see “Write Operation Status”.
2. Illustration shows device in word mode .
Figure 19. Chip/Sector Erase Operation Timings
46 Am29LV320MH/L February 12, 2004
PRELIMINARY
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
t
OE
High Z
DQ15 and DQ7
DQ14–DQ8, DQ6–DQ0
RY/BY#
t
BUSY
Complement True
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
t
ACC
t
RC
t
POLL
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 20. Data# Polling Timing s (Du rin g Embedded Algo rithm s )
February 12, 2004 Am29LV320MH/L 47
PRELIMINARY
AC CHARACTERISTICS
OE#
CE#
WE#
Addresses
t
OEH
t
DH
t
AHT
t
ASO
t
OEPH
t
OE
Valid Data
(first read) (second read) (stops toggling)
t
CEPH
t
AHT
t
AS
DQ6/DQ2 Valid Data
Valid
Status Valid
Status Valid
Status
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 21. Toggle Bit Timings (During Embedded Algorithms)
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 22. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Pro gra m
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
48 Am29LV320MH/L February 12, 2004
PRELIMINARY
AC CHARACTERISTICS
Temporary Sector Unprotect
Note:
1. Not 100% tested.
2. AC spe c ific at i ons liste d ar e tested w it h VIO = VCC. Co ntact AMD for in formation on AC operatio n w ith VIO
≠
VCC.
Parameter
All Speed OptionsJEDEC Std Description Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tRSP RESET# Setup Time for Temporary Sector
Unprotect Min 4 µs
RESET#
tVIDR
VID
VSS, VIL,
or VIH
VID
VSS, VIL,
or VIH
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
tRRB
Figure 23. Temporary Sector Group Unprotect Timing Diagram
February 12, 2004 Am29LV320MH/L 49
PRELIMINARY
AC CHARACTERISTICS
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A3, A2,
A1, A0
Data
CE#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Group Protect or Unprotect Verify
VID
VIH
* For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
Figure 24. S ecto r Group Protect and Unprotect Timing Diagram
50 Am29LV320MH/L February 12, 2004
PRELIMINARY
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Pr og r amming Performance” section f o r more information.
3. For 1–16 words/1–32 byt es programmed.
4. Effective write buffer speci ficat ion i s based upon a 16-w ord/32- b yt e write b uf fer operation.
5. Word/Byte prog r amming s pecifi cati on is based upon a sin gle w ord/ b yt e prog r amming oper ation not ut ili zing the write buffer.
6. AC specificati ons l isted are t ested wi th V
IO
= V
CC
. Contact AMD for inf ormation on AC operation with V
IO
≠
V
CC.
7. When using the program suspend/r esume feature, if the su spend command is i ssued wi thin t
POLL
, t
POLL
must be full y re-a pplied
upon resuming the prog r amming ope r ation. If the sus pend command i s i ssued af ter t
POLL
, t
POLL
is not required again p rior to
reading the sta tus bi ts upon resumi ng.
Parameter S pe ed Op tion s
JEDEC Std. Description 90R 101,
101R 112,
112R 120,
120R Unit
tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns
tAVWL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 ns
tDVEH tDS Data Setup Time Min 45 ns
tEHDX tDH Data Hold Time Min 0 ns
tGHEL tGHEL Read Recovery Time Before Write
(OE# High to WE# Low) Min 0 ns
tWLEL tWS WE# Set u p Ti me Min 0 ns
tEHWH tWH WE# Hold Time Min 0 ns
tELEH tCP CE# P ul s e Widt h Min 45 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWH1 tWHWH1
Write Buffer Program Operation (Notes 2, 3) Typ 240 µs
Effective Write Buffer Program
Operation (Notes 2, 4) Per Byte Typ 7.5 µs
Per Word Typ 15 µs
Accelerated Effective Write Buff er
Program Operation (Notes 2, 4) Per Byte Typ 6.25 µs
Per Word Typ 12.5 µs
Single Word/Byte Program
Operation (Note 2, 5) Byte Typ 60 µs
Word 60
Accelerated Single Word/Byte
Programming Operation (Note 2) Byte Typ 54 µs
Word 54
tWHWH2 tWHWH2 Sector Erase Operation (Note 2, 5) Typ 0.5 sec
tRH RESET High Time Before Write (Note 1) Min 50 ns
tPOLL Program Valid before Status Polling (Note 7) Max 4 µs
February 12, 2004 Am29LV320MH/L 51
PRELIMINARY
AC CHARACTERISTICS
t
GHEL
t
WS
OE#
CE#
WE#
RESET#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7#,
D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
RH
t
WHWH1 or 2
RY/BY#
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
t
BUSY
DQ15
t
POLL
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = progr am addr ess , SA = sect or addr ess , PD = prog r am d ata.
3. DQ7# is the compl ement of the data written to the device. D
OUT
is the data written to t he device.
4. Illustration shows device in word mode.
Figure 25. A lternate CE# Controlled Write (Erase/Prog ram)
Operation Timings
52 Am29LV320MH/L February 12, 2004
PRELIMINARY
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V V
CC
, Programming specification assume that
all bits are programmed to 00h.
2. Maximum values are measured at V
CC
= 3.0, wor st ca se temper at ure . Maxim um values are val id up to and incl uding 1 00,000
progra m/er ase cy cles .
3. Word/Byte prog r amming s pecifi cati on is based upon a sin gle w ord/ b yt e prog r amming oper ation not ut ili zing the write buffer.
4. For 1-16 w ords or 1-32 b yte s prog r ammed i n a si ngle write b uffer progr amming oper at ion.
5. Effective write buffer speci ficat ion i s calculated on a p er-w ord/p er-byte basis f or a 16-w ord/32- b yt e write buffer oper ati on.
6. In the pre-programmi ng step of t he Embedded Er as e algorithm, all bits are pr ogr a mmed to 00h before erasure .
7. System-level over head is the t ime r equired to execute the command sequence (s) for the program command. See Tab les 12 and
13 for further information on command definitions.
8. The device has a minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Note: Includes all pins except V
CC
. Test conditions: V
CC
= 3.0 V, one pin at a time.
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.5 3.5 sec Excludes 00h programming
prior to erasure (Note 6)
Chip Erase Time 32 64 sec
Single Word/Byte Program Time (Note 3) 60 600 µs
Excludes system level
overhead (Note 7)
Accelerated Single Word/Byte Program Time (Note 3) 54 540 µs
Total Wr ite Buffer Program Time (Note 4) 240 1200 µs
Effective Write Buffer Program Time (Note 5) Per Byte 7.5 38 µs
Per Word 15 75 µs
Total Accelerated Write Buffer Program Time (Note 4) 200 1040 µs
Effective Accelerated Write Buffer Program Time
(Note 5)
Per Byte 6.25 33 µs
Per Word 12.5 65 µs
Chip Program Time 31.5 73 sec
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
(incl udi ng A9, OE#, and RESE T#) –1.0 V 12.5 V
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
February 12, 2004 Am29LV320MH/L 53
PRELIMINARY
TSOP PIN AND BGA PACKAGE CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 TSOP 6 7.5 pF
BGA 4.2 5 pF
COUT Output Capacitance VOUT = 0 TSOP 8.5 12 pF
BGA 5.4 6.5 pF
CIN2 Control Pin Capac ita nce VIN = 0 TSOP 7.5 9 pF
BGA 3.9 4.7 pF
Parameter Description Test Conditions Min Unit
Mini mum Pattern Data Ret ent ion Tim e 150°C10Years
125°C20Years
54 Am29LV320MH/L February 12, 2004
PRELIMINARY
PH YSICAL DIMENSI ONS
TS056/TSR056—56-Pin Standard and Rev ers e Pinout Thin Small Outline Pac ka ge (TSOP)
NOTES:
1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)
2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTUSION IS 0.15 mm PER SIDE.
6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.
7 THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10 mm AND 0.25 mm FROM THE LEAD TIP.
8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3160\38.10A
MO-142 (B) EC
TS/TSR 56
NOM.
---
---
1.00
1.20
0.15
1.05
MAX.
---
MIN.
0.95 0.20 0.230.17 0.22 0.270.17 --- 0.160.10 --- 0.210.10 20.00 20.2019.90
14.00 14.1013.90
0.60 0.700.50 3˚ 5˚0˚ --- 0.200.08 56
18.40 18.5018.30
0.05
0.50 BASIC
E
R
b1
JEDEC
PACKAGE
SYMBOL
A
A2
A1
D1
D
c1
c
b
e
L
N
O
February 12, 2004 Am29LV320MH/L 55
PRELIMINARY
PH YSICAL DIMENSI ONS
LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package
56 Am29LV320MH/L February 12, 2004
PRELIMINARY
REVISION SUMMARY
Revision A (May 30, 2002)
Initial release as Adv ance Information data sheet.
Revision A+1 (September 3, 2002)
Mirrorbit 32 Mbit Device Family
Changed the 48-pin TSOP to 40-pin TSOP.
Alternate CE# Controlled Erase and Program
Operations
Added tRH parameter to table.
Erase and Program Operations
Added tBUSY parameter to table.
Figure 16. Program Operation Timings
Added RY/BY# to wa veform.
TSOP and BGA PIN Capacitance
Added the FBGA packa g e.
Program Suspend/Program Resume Command
Sequence
Chan ged 15 µs typical to maximum and added 5 µs
typical.
Erase Suspend/Erase Resume Commands
Changed typical from 20 µs to 5 µs and added a maxi-
mum of 20 µs.
Product Selector Guide
Added Note 2.
Ordering Information
Added 101R, 112R, and 120R to Valid Combinations
Table.
Added Note 1.
Read-Only Operations
Alternate CE# Controlled Erase and Program
Operations
Erase and Program Operations
Added 101R, 112R, and 120R to Speed Options.
Revision A+2 (November 15, 2002)
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factor y
Added second bullet and figure
Product Selector Guide and Read-Only Operations
Added 30 ns to the 112R and 120R to Max page ac-
cess time and Max OE# Access time.
Changed the Chip Enable to Output High Z and Out-
put Enable to Output High Z to 16 ns.
Byte/Word Program Command Sequence, Sector
Erase Comman d Seque nce, a nd Chip E rase Co m-
mand Sequence
Noted that the SecSi Sector, autoselect, and CFI
functions are una vailable when a program or erase
operation is in progress.
Common Flash Memory Interface (CFI)
Changed CFI website address.
CMOS Compatable
Added ILR para me te r sy m b o l to ta ble.
Remov ed V IL, VIH, VOL, an d VOH and replaced with VIL,
VIH, VOL, VOH1 and VOH2.
Clarified note #5.
Removed note #6.
Read-Only Operations
Added note #3.
Absolute Maximum Rating
Chang ed the Ambient Temperature with Power Ap-
plied from –55°C to +125°C to –65°C to +125°C.
Revision A+3 (February 14, 2003)
Distinctive Characteristics
Corrected performance characteristics.
AC Characteristics
Added Note
Input values in the tWHWH1 and tWHWH2 parameters in
the Erase and Program Options table that were previ-
ously TBD. Also added notes 5 and 6.
Input values in the tWHWH1 and tWHWH2 parameters in
the Alter nate CE# Controlled Erase and Program Op-
tions tab l e that w ere p reviously TBD. Also added notes
5 and 6.
Erase and Programming Performance
Input v alues into tab l e that were previously TBD.
Added note 3 and 4.
February 12, 2004 Am29LV320MH/L 57
PRELIMINARY
Revision B (May 7, 2003)
Distinctive Characteristics
Added typical active read current
Global
Converted to full datasheet version.
Modified SecSi Sector Flash Memory Region section
to include ESN references .
CMOS Compatible
Corrected Typ and Max values for the ICC 1, 2, and 3 .
Erase and Program Operations and Alternate CE#
Controlled Erase and Pro gram Operations
Changed Accelerated Effective Write Buffer Program
Operation value.
Erase and Programming Performance
Input v alues into table that were previously TBD.
Modified notes.
Removed Word references.
Revision C + 3 (February 12, 2004)
Customer Lockable: SecSi Sector NOT
Programmed or Protected at the Factory
Removed second paragraph.
Table 10 & Table 11: Command Definitions
Replaced the Addr information for both Program/Er ase
Suspend and Program/Erase Resume from BA to
XXX.
Erase Suspend/Erase Resume Commands
Added note on flash device performance during
suspend/erase mode.
AC Characteristics - Erase and Pr ogram
Operations
Removed Byte information for tWHWH1 parameter.
Added tPOLL information and footnote.
AC Characteristics Figur es - Program Operation
Timi ngs, Data# Po lling Timi ngs (Durin g Embedded
Algorithms, and Alternate CE# Controlled Write
(Erase/Program) Operati on Timi ng s
Updated with tPOLL information.
AC Characteristics - Alternate CE# Controll ed
Erase and Program Operat ions
Added tPOLL information and footnote.
Erase and Programming Performance
Added tPOLL information and footnote.
Trademarks
Updated.
February 12, 2004 Am29LV320MH/L 58
PRELIMINARY
Trademarks
Copyright © 2004 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
©2003 Advanced Micro Devices, Inc.
01/03
Printed in USA
One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 408-732-2400
TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com
Advanced Micro Devices reserves the right to make changes in its product without notice
in order to improve design or performance characteristics.The performance
characteristics listed in this document are guaranteed by specific tests, guard banding,
design and other practices common to the industry. For specific testing details, contact
your local AMD sales representative.The company assumes no responsibility for the use of
any circuits described herein.
© Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD Arrow logo and combination thereof, are trademarks of
Advanced Micro Devices, Inc. Other product names are for informational purposes only
and may be trademarks of their respective companies.
North America
ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (256)830-9192
ARIZONA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(602)242-4400
CALIFORNIA,
Irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 949)450-7500
Sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(408)732-2400
COLORADO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (303)741-2900
CONNECTICUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (203)264-7800
FLORIDA,
Clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 2 7)793-0055
Miami (Lakes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (305)820-1113
GEORGIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (770)814-0224
ILLINOIS,
Chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(630)773-4422
MASSACHUSETTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (781)213-6400
MICHIGAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 48)471-6294
MINNESOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (612)745-0005
NEW JERSEY,
Chatham . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 73)701-1777
NEW YORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(716)425-8050
NORTH CAROLINA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (919)840-8080
OREGON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (503)245-0080
PENNSYLVANIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (215)340-1187
SOUTH DAKOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (605)692-5777
TEXAS,
Austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (512)346-7830
Dallas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 7 2)985-1344
Houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (281)376-8084
VIRGINIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (703)736-9568
International
AUSTRALIA, North Ryde . . . . . . . . . . . . . . . . . . . . . . . TEL(61)2-88-777-222
BELGIUM,Antwerpen . . . . . . . . . . . . . . . . . . . . . . . .TEL(32)3-248-43-00
BRAZIL, San Paulo . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(55)11-5501-2105
CHINA,
Beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(86)10-6510-2188
Shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)21-635-00838
Shenzhen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(86)755-246-1550
FINLAND, Helsinki . . . . . . . . . . . . . . . . . . . . . . TEL(358)881-3117
FRANCE, Paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(33)-1-49751010
GERMANY,
Bad Homburg . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(49)-6172-92670
Munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(49)-89-450530
HONG KONG, Causeway Bay . . . . . . . . . . . . . . . . . . . TEL(85)2-2956-0388
ITALY, Milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(39)-02-381961
INDIA, New Delhi . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(91)11-623-8620
JAPAN,
Osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(81)6-6243-3250
Tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(81)3-3346-7600
KOREA, Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(82)2-3468-2600
RUSSIA, Moscow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(7)-095-795-06-22
SWEDEN, Stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(46)8-562-540-00
TAIWAN,Taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(886)2-8773-1555
UNITED KINGDOM,
Frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(44)1276-803100
Haydock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(44)1942-272888
Representatives in U.S. and Canada
ARIZONA,
Tempe - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (480)839-2320
CALIFORNIA,
Calabasas - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (818)878-5800
Irvine - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 49)261-2123
San Diego - Centaur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(858)278-4950
Santa Clara - Fourfront. . . . . . . . . . . . . . . . . . . . . . . . . . . . (408)350-4800
CANADA,
Burnaby, B.C. - Davetek Marketing. . . . . . . . . . . . . . . . . . . . (604)430-3680
Calgary,Alberta - Davetek Marketing. . . . . . . . . . . . . . . . . (403)283-3577
Kanata, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . . . (613)592-9540
Mississauga, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . (905)672-2030
St Laurent, Quebec - J-Squared Tech. . . . . . . . . . . . . . . . (514)747-1211
COLORADO,
Golden - Compass Marketing . . . . . . . . . . . . . . . . . . . . . . (303)277-0456
FLORIDA,
Melbourne - Marathon Technical Sales . . . . . . . . . . . . . . . . (321)728-7706
Ft. Lauderdale - Marathon Technical Sales . . . . . . . . . . . . . . (954)527-4949
Orlando - Marathon Technical Sales . . . . . . . . . . . . . . . . . . (407)872-5775
St. Petersburg - Marathon Technical Sales . . . . . . . . . . . . . . ( 7 2 7)894-3603
GEORGIA,
Duluth - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . ( 6 78)584-1128
ILLINOIS,
Skokie - Industrial Reps, Inc. . . . . . . . . . . . . . . . . . . . . . . . . ( 84 7)967-8430
INDIANA,
Kokomo - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 765)457-7241
IOWA,
Cedar Rapids - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . (319)294-1000
KANSAS,
Lenexa - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . (913)469-1312
MASSACHUSETTS,
Burlington - Synergy Associates . . . . . . . . . . . . . . . . . . . . . (781)238-0870
MICHIGAN,
Brighton - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (810)227-0007
MINNESOTA,
St. Paul - Cahill, Schmitz & Cahill, Inc. . . . . . . . . . . . . . . . . . (651)699-0200
MISSOURI,
St. Louis - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . . (314)997-4558
NEW JERSEY,
Mt. Laurel - SJ Associates . . . . . . . . . . . . . . . . . . . . . . . . . (856)866-1234
NEW YORK,
Buffalo - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . .(716)741-7116
East Syracuse - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . (315)437-8343
Pittsford - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . (716)586-3660
Rockville Centre - SJ Associates . . . . . . . . . . . . . . . . . . . . (516)536-4242
NORTH CAROLINA,
Raleigh - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . . (919)846-5728
OHIO,
Middleburg Hts - Dolfuss Root & Co. . . . . . . . . . . . . . . . . (440)816-1660
Powell - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . . (614)781-0725
Vandalia - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . .(937)898-9610
Westerville - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . (614)523-1990
OREGON,
Lake Oswego - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . (503)670-0557
UTAH,
Murray - Front Range Marketing . . . . . . . . . . . . . . . . . . . . (801)288-2500
VIRGINIA,
Glen Burnie - Coherent Solution, Inc. . . . . . . . . . . . . . . . . (410)761-2255
WASHINGTON,
Kirkland - I Squared,Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(425)822-9220
WISCONSIN,
Pewaukee - Industrial Representatives . . . . . . . . . . . . . . . . ( 2 6 2)574-9393
Representatives in Latin America
ARGENTINA,
Capital Federal Argentina/WW Rep. . . . . . . . . . . . . . . . . . . .54-11)4373-0655
CHILE,
Santiago - LatinRep/WWRep. . . . . . . . . . . . . . . . . . . . . . . . . .(+562)264-0993
COLUMBIA,
Bogota - Dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(571)410-4182
MEXICO,
Guadalajara - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . ( 5 23)817-3900
Mexico City - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . ( 5 25)752-2727
Monterrey - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . .(528)369-6828
PUERTO RICO,
Boqueron - Infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . (787)851-6000
Sales Offices and Representatives
es
