SB 17: Early/Late Gate Synchronizer Megafunction
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1997 Altera Corporation. Altera, AMPP, FLEX, FLEX 10K, and FLEX 8000 are trademarks and/or service marks of Altera
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Ports
The master control logic uses the
ratio[7..0]
input to determine the number of
sample clocks per symbol, the number of sample clocks per early gate, and the number
of sample clocks per late gate. The integration time for the early and late gate
integrators is determined by the value of
ratio[7..0]
/2. The phase detector requires
equal integration times for the early and late gate integrators. Therefore, the
ratio[7..0]
value must be an even integer between 4 and 254. Table 1 describes the
ports for the early/late gate synchronizer megafunction.
Changes in the values of
ratio[7..0]
,
error_thresh[15..0]
, and
step_size[7..0]
must be synchronous to
sample_clk
. Specifically, these values
must be stable and correct when the rising edge of
sample_clk
occurs.
Device Utilization
The early/late gate synchronizer megafunction is designed for both FLEX 10K and
FLEX 8000 devices and does not require the use of the FLEX 10K embedded array
blocks (EABs). Therefore, this megafunction performs equally well in both device
families. Table 2 illustrates the device utilization and maximum clock frequency for the
synchronizer.
Applications
The early/late gate synchronizer megafunction is fundamentally a digital phase-
locked loop (DPLL). The synchronizer is designed to provide phase lock between an
internally generated data clock and an input data stream. Moreover, it can perform the
traditional task of providing phase lock between two clocks.
The synchronizer can be used as a PLL by connecting the reference clock to the data
input. The reference clock appears as an alternating one and zero data pattern (i.e.,
101010) to the synchronizer. Again, a high-speed sampling clock is needed to generate
the internal timing and control. Because the data clock is twice the frequency of the
reference clock, it is necessary to divide the output data clock by two.
Table 1. Early/Late Gate Synchronizer Megafunction Ports
Name Type Width (Bits) Description
data
Input 1 Binary input data with a bit period equal to one cycle of the data clock.
sample_clk
Input – Sample clock.
reset
Input – Asynchronous reset, active high.
ratio[7..0]
Input 8 Defines the number of sample clocks per data clock.
error_thresh[15..0]
Input 16 Defines the error threshold at which a phase correction occurs.
step_size[7..0]
Input 8 Defines the magnitude of the phase corrections.
data_clk
Output – Output clock, phase aligned to input data.
Table 2. Typical Device Utilization
Implementation Clock (f
MAX
) Logic Cells EABs
error_thresh[15..0]
= arbitrary
ratio[7..0]
= arbitrary
step_size[7..0]
= arbitrary
35 MHz 260 0