WM8775SEDS/V - Cirrus Logic Inc.

w WM8775

24-bit, 96kHz ADC with 4 Channel I/P Multiplexer

WOLFSO N MICROELE CTRONICS plc

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Production Dat a, Oc tober 2008, Rev 4.4

DESCRIPTION

The WM8775 is a high performance, stereo audio ADC

with a 4 channel input mixer. The WM8775 is ideal for

digitising multiple analogue sources for surround sound

processing applications for home hi-fi, automotive and

other audio visual equipment.

A stereo 24-bit multi-bit sigma delta ADC is used with a

four stereo channel input selector. Each channel has

programmable gain control. Digital audio output word

lengths from 16-32 bits and sampling rates from 32kHz

to 96kHz are supported.

The audio data interface supports I2S, left justified, right

justified and DSP digital audio formats.

The device i s controlled via a 2 or 3 wire seri al interface.

The interface provides access to all features including

channel selection, volume controls, mutes, de-emphasis

and power managem ent facilities .

The device i s available in a 28-lead SSOP pack age. The

WM 8775 is software compatible with the WM8776.

FEATURES

• Audio Performance

− 102dB SNR (‘A’ weighted @ 48kHz)

− -90dB THD

• ADC Sampling Frequency: 32kHz – 96kHz

• Four stereo ADC inputs with analogue gain adjust from

+24dB to –21dB in 0.5dB steps

• Digital gain adjust from -21.5dB to -103dB.

• Programmabl e Aut om at ic Level Control (ALC) or Limiter on

ADC input

• 3-Wire S P I Com pati ble or 2-wire Serial Control I nterfac e

• Master or Slave Clock i ng Mode

• Programmable Audio Data Interface Modes

− I

2S, Left , Right J ustified or DSP

− 16/20/24/32 bit Word Lengths

• 2.7V to 5.5V Analogue, 2.7V to 3.6V Digit al s upply Operation

APPLICATIONS

• Surround Sound AV P rocess or s and Hi-Fi sys tems

• Automotive Audio

BLOCK DIAG RAM

AGND

AVDD

VMIDADC

AUDIO INTERFACE

AND

DIGITAL FILTERS

ADCREFP

DVDD

DGND

CONTROL INTERFACE

WM8775

ADCLRC

BCLK

DOUT

MCLK

ADCREFGND

STEREO

ADC ALC

AIN2R

AIN3L

AIN3R

AIN4L

AIN4R

AINOPR

AINOPL

AINVGR

AINVGL

AIN2L

AIN1R

AIN1L

INPUT MIXER

VMID

MODE

WM8775 Production Data

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TABLE OF CONTENTS

DESCRIPTION ................................................................................................................1

FEATURES......................................................................................................................1

BLOCK DIAGRAM......... ............... .... .... .... .... .... .... .... .... .... .... .... ................ .... .... ... .... .... ...1

PIN CONFIGURATION... .... ... ................ .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... ..............3

ORDERING INFORMATION .......... ............... .... .... .... .... .... .... .... .... .... .... .... .... ... .... ...........3

PIN DESCRIPTION ........... ................ .... .... .... .... .... .... .... .... .... .... .... .... .... .... ............... .... ...4

ABSOLUTE MAXIMUM RATINGS..................................................................................5

RECOMMENDED OPERATI NG CONDITIONS ........ .... .... .... .... .... .... .... .... ... .... .... .... .... ...5

ELECTRICAL CHARACTERISTICS ...............................................................................6

TERMINOLOGY......................................................................................................................7

MASTER CLOCK TIMING...............................................................................................7

DIGITAL AUDIO INTERFACE – MASTER MODE...................................................................8

DIGITAL AUDIO INTERFACE – SLAVE MODE................... ............. ............. ............. ............9

3-WIRE MPU INTERFACE TIMING ........................... ............. ............. ............. ....................10

2-WIRE MPU INTERFACE TIMING ........................... ............. ............. ............. ....................10

INTERNAL POWER ON RESE T CIRCUIT ....................... .... .... .... .... .... .... ............... .... .12

DEVICE DESCRIPTION................................................................................................14

INTRODUCTION...................................................................................................................14

AUDIO DATA SAMPLING RATES........................................... ............. ............. .............. ......14

POWERDOW N MODES ......... ... ... ... ....... ... ... .... ... ... ... .... ...... ... .... ... ... .... ... ...... .... ... ... ... .... ... ...15

DIGITAL AUDIO INTERFACE.......... ........................................................................... ..........16

CONTROL INTERFACE OPERATION. ... ... ... ....... ... ... .... ... ... ... .... ...... .... ... ... ... .... ... ...... .... ... ...20

CONTROL INTERFACE REGISTERS ....... ....... ... ... ... .... ... ... ....... ... ... .... ... ... ... .... ...... ... .... ... ...21

LIMITER / AUTOMATIC LEVEL CONTROL (ALC).. ... .... ... ... ....... ... ... ... .... ... ... ....... ... ... ... .... ...26

REGISTER MAP ........... ............. ........................................................................... ................31

DIGITAL FILTER CHARACTERISTICS........................................................................35

ADC FILTER RESPONSES.... ....... ... .... ... ... ... ....... ... ... .... ... ... ... ....... ... ... .... ... ... ... ....... ... .... ... ...35

ADC HIGH PASS FILTER....... ... ... ... .... ... ... ....... ... ... ... .... ... ... ....... ... ... ... .... ... ... .... ...... ... .... ... ...35

APPLICATIONS INFORMATION ..................................................................................36

EXTERNAL CIRCUIT CONFIGURATION ......................................... ............. ............. ..........36

RECOMMENDED EXTERNAL COMPONENTS.................................................... ............. ...37

PACKAGE DIMENSIONS .............................................................................................38

IMPORTANT NOTICE...................................................................................................39

ADDRESS:............................................................................................................................39

Product ion Data WM8775

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PIN CONFIGURATION

AVDDVMIDADC

AGND

AINOPL

AINVGL

AINVGR

AIN1R

AIN4L

AIN3R

AIN3L

AIN2R

AIN2L

AIN1L

AIN4R

BCLK

ADCLRC

DOUT

MCLK

14 15

ADCREFGND

MODE

ADCREFP

DGND

DVDD

AINOPR

ORDERING INFORMATION

DEVICE TEMPERATURE

RANGE PACKAGE MOISTURE

SENSITIVITY LEVEL PEAK SOLDERING

TEMPERATURE

W M8775SE DS /V -25 to +85oC 28-lead SSOP

(Pb-free) MSL2 260°C

WM8775SEDS/RV -25 to +85oC 28-lead SSO P

(Pb-free, tape and reel) MSL2 260°C

Note:

Reel quantity = 2,000

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PIN DESCRIPTION

PIN NAME TYPE DESCRIPTION

1 AIN1L Analogue Input

Channel 1 left input multiplexor virtual ground

2 BCLK Digital input/output

ADC audio interfac e bit cl ock

3 MCLK Digital input

Master ADC cloc k; 256, 384, 512 or 768fs (fs = word clock frequency)

4 DOUT Digital output

ADC data output

5 ADCLRC Digital input/output

ADC left/right word clock

6 DGND Supply

Digital negati ve supply

7 DVDD Supply

Digital pos it ive s uppl y

8 MODE Digital Input

Serial Int erf ace Mode selec t

9 CE Digital Input

Serial Int erf ace Latc h s ignal

10 DI Digital input/output

Serial interf ac e data

11 CL Digital input

Serial interf ac e c lock

12 NC

No connection

13 VMIDADC Analogue Output

ADC midrail divider decoupling pin; 10uF external decoupling

14 ADCREFGND Supply ADC negative supply and substrate connection

15 ADCREFP Analogue Output

ADC positive reference decoupling pin; 10uF external decoupling

16 AVDD Supply

Analogue posi ti ve sup ply

17 AGND Supply

Analogue negative supply and substr ate c onnecti on

18 AINVGR Analogue Input

Right channel multiplexor virtual ground

19 AINOPR Analogue Output

Right channel multiplexor output

20 AINVGL Analogue Input

Left channel m ul ti pl exor virtual ground

21 AINOPL Analogue Output

Left channel m ul ti pl exor output

22 AIN4R Analogue Input

Channel 4 right input multiplexor virtual ground

23 AIN4L Analogue Input

Channel 4 left input multiplexor virtual ground

24 AIN3R Analogue Input

Channel 3 right input multiplexor virtual ground

25 AIN3L Analogue Input

Channel 3 left input multiplexor virtual ground

26 AIN2R Analogue Input

Channel 2 right input multiplexor virtual ground

27 AIN2L Analogue Input

Channel 2 left input multiplexor virtual ground

28 AIN1R Analogue Input

Channel 1 right input multiplexor virtual ground

Note : Digital input pins have Schmitt trigger input buffers.

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ABSOLUTE MAXIMUM RATINGS

Absolut e Maximum Ratings ar e stress ratings only. Perm anen t damage to the dev ic e m ay be c aused by continuousl y oper ating at

or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD S ensitive Device. This device is manuf actured on a CMOS process . It is theref ore generically susc eptible

to dam age fr om excessi ve stati c voltages. Proper E SD precaut ions mus t b e tak en during handling and s torage

of this devic e.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage

conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity . Suppl ied in m ois t ure barrier bag.

MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Hum idity . Suppl i ed in mois t ure barrier bag.

The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION MIN MAX

Digital supply voltage -0.3V +3.63V

Analogue supply voltage -0.3V +7V

Voltage range digital inputs (MCLK, ADCLRC, BCLK, DI, CL, CE and

MODE) DGND -0.3V DVDD + 0.3V

Voltage range analogue inputs AGND -0.3V AVDD +0.3V

Master Clock Frequenc y 37MHz

Operating temperature range, TA -25°C +85°C

Junction Temperature, TJ -25°C +125°C

Storage temperature -65°C +150°C

Notes:

1. Analogue and digital grounds must always be within 0.3V of each other.

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digita l supply range DVDD 2.7 3.6 V

Analogue supply range AVDD 2.7 5.5 V

Ground AGND, DGND 0 V

Differenc e DGND to AGND -0.3 0 +0.3 V

Note: Digital supply DVDD must never be more than 0.3V greater than AVDD.

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ELECTRICAL CHARACTERISTICS

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +2 5oC, fs = 48kHz, MCLK = 25 6fs unless other wise stat ed.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Digital Logic Levels (TTL Levels)

Input LOW level VIL 0.8 V

Input HIGH level VIH 2.0 V

Output LOW VOL IOL=1mA 0.1 x DVDD V

Output HIGH VOH IOH=1mA 0.9 x DVDD V

Analogue Reference Levels

Reference voltage VVMID AVDD/2 V

Potenti al divi der resi s t anc e RVMID 50k Ω

ADC Performance

Input Signal Level (0dB) 1.0 x

AVDD/5 Vrms

SNR (Note 1,2) A-weighted, 0dB gain

@ fs = 48kHz 93 102 dB

SNR (Note 1,2) A-weighted, 0dB gain

@ fs = 96kHz

64xOSR

99 dB

Dynamic Range (note 2) A-weighted, -60dB

full scal e input 102 dB

1 kHz, 0dBFs -92 dB

Total Harm onic Dis tor tion (THD) 1kHz, -1dBFs -95 -85 dB

ADC Channel Separation 1kHz Input 90 dB

Programmable Gain St ep Size 0.25 0.5 0.75 dB

Programmable Gain Range

(Analogue) 1kHz Input -21 +24 dB

Programmable Gain Range

(Digital) 1kHz Input -82 +0 dB

Analogue Mute Attenuation

(Note 5) 1kHz Input, 0dB gain 76 dB

1kHz 100mVpp 50 dB

Power Supply Reject ion Rati o PSRR 20Hz to 20kHz

100mVpp 45 dB

Supply Current

Analogue supply current AVDD = 5V 48 mA

Digita l supply cur rent DVDD = 3.3V 4.5 mA

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’

weighted.

2. All perform anc e m easur em ent s done with 20kHz low pass filter, and where noted an A-weight filter. F ail ure to use

such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical

Characteris ti c s. T he low pass fil ter rem oves out of band noise; alt hough it is not audible it may aff ect dynamic

specification values.

3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).

4. All perform anc e m easur em ent done using c ert ai n timing conditions (pleas e refer to s ect i on ‘Digital Audio Interfac e’) .

5. A full digital MUTE can be achieved if the ADC gain (LAG/RAG) is set to minimum.

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TERMINOLOGY

1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output

with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).

2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.

Normall y a T HD+N meas urem ent at 60dB below full scal e. The m eas ured si gnal is then c orrected by adding the 60dB

to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4. Stop band attenuat ion (dB) - Is the degree to which the frequency s pectr um is att enuated (out side audio band).

5. Channe l Separation ( dB) - Als o known as Cross -Talk. This is a m easure of the amount one channel is isolated f rom

the other. Normally measured by sending a full scale signal down one channel and measuring the other.

6. Pass-B and Ripple - Any variation of the frequenc y respons e in the pass - band region.

MASTER CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGN D = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless other wise stat ed.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

System Clock Timing Information

MCLK System clock pulse widt h

high tMCLKH 11 ns

MCLK System clock pulse widt h

low tMCLKL 11 ns

MCLK System clock cycle time tMCLKY 28 1000 ns

MCLK Duty cycle 40:60 60:40

Power-saving mode act ivat ed After MCLK stopped 2 10 µs

Normal m ode resumed After MCLK re-started 0.5 1 MCLK

cycle

Table 1 Master Clock Timing Requirements

Note:

If MCLK period is longer than maximum specified above, power-saving mode is entered. In this power-saving mode, all

registers w ill retain their values and can be accessed in the normal manner through the control interface.

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DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

DOUT

ADCLRC

WM8775

ADC DVD

Controller

Figure 2 Au di o In terface - Mast er M od e

BCLK

(Output)

DOUT

ADCLRC

(Output)

DDA

Figure 3 Digital Audio Data Timing – Master Mode

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND=0V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise

stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Audio Data Input Timing Information

ADCLRC propagation delay

from BCLK fal l ing edge tDL 0 10 ns

DOUT propagation delay

from BCLK fal l ing edge tDDA 0 10 ns

Table 2 Digital Audio Data Timing – Master Mode

Product ion Data WM8775

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DIGITAL AUDIO INTERFACE – SLAVE MODE

BCLK

DOUT

ADCLRC

WM8775

ADC DVD

Controller

Figure 4 Au di o In terface – Sl ave M ode

BCLK

ADCLRC

BCH

BCL

BCY

DOUT

LRSU

LRH

Figure 5 Digital Audio Data Timing – Slave M ode

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +2 5oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise

stated.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Audio Data Input Timing Information

BCLK cycle tim e tBCY 50 ns

BCLK puls e width high tBCH 20 ns

BCLK puls e width low tBCL 20 ns

ADCLRC set-up time to

BCLK risi ng edge tLRSU 10 ns

ADCLRC hold time from

BCLK risi ng edge tLRH 10 ns

DOUT propagation delay

from BCLK fal l ing edge tDD 0 10 ns

Table 3 Digit al Audio Data T iming – Slave Mode

Note:

ADCLRC should be synchronous with MCLK, although the WM8775 interface is tolerant of phase variations or jitter on

these si gnals.

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3-WIRE MPU INTERFACE TIMING

CSL

DHO

DSU

CSH

SCY

SCH

SCL

SCS

LSB

CSS

Figure 6 SP I Compatible Control Interface Input Timing (MODE=1)

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = + 2 5 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated

PARAMETER SYMBOL MIN TYP MAX UNIT

CL rising edge to CE rising edge tSCS 60 ns

CL pulse cycle time tSCY 80 ns

CL pulse width low tSCL 30 ns

CL pulse width high tSCH 30 ns

DI to CL set-up time tDSU 20 ns

CL to DI hold time tDHO 20 ns

CE pulse width low tCSL 20 ns

CE pulse width high tCSH 20 ns

CE rising to CL rising tCSS 20 ns

Table 4 3-Wire SPI Compatible Control Interface Input Timing Information

2-WIRE MPU INTERFACE TIMING

Figure 7 Control Int erface Timin g – 2-Wire Serial Contro l M od e (M ODE =0)

Product ion Data WM8775

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Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = + 2 5 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated

PARAMETER SYMBOL MIN TYP MAX UNIT

Program Register Input Information

CL Frequency 0 526 kHz

CL Low Pulse-Width t1 1.3 us

CL High Pulse-Width t2 600 ns

Hold Time (Start Condition) t3 600 ns

Setup Tim e (Star t Conditi on) t4 600 ns

Data Setup Time t5 100 ns

DI, CL Rise Time t6 300 ns

DI, CL Fall Time t7 300 ns

Setup Tim e (S top Condit ion) t8 600 ns

Data Hold Time t9 900 ns

Pulse width of spikes that will be suppressed tps 0 5 ns

Table 5 2-Wire Contro l Int erface Timi ng Information

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INTERNAL POWER ON RESET CIRCUIT

Figur e 8 Internal Pow er o n Reset Circui t Schematic

The W M8775 includes an internal Power on Res et Circuit which is used reset t he digital logi c into a

default state after power up.

Figure 8 shows a schematic of the internal P OR ci rc uit . The P OR cir cuit is powered from AVDD. The

circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the minimum

threshold Vpor_off.

On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until

AVDD and DVDD and VMID are established. When AVDD, DVDD, and VMID have been established,

PORB is released high, all registers are in their default state and writes to the digital interface may

take place.

On power down, PO RB is asser ted low whenever DVDD or VMID drop below the mini mum threshold

Vpor_off.

If AV DD is removed at any tim e, the internal Power on Reset circuit is powered down and PORB will

follo w AVDD.

In m ost applications the ti me required for the device to release PO RB high will be determ ined by the

charge time of the VMID node.

Figure 9 Typical Power up Sequence where DVDD is Powered before AVDD

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Figure 10 Typical Power up Sequence where AVDD is Powered before DVDD

Typi cal PO R Operatio n (typical values, not tested)

SYMBOL MIN TYP MAX UNIT

Vpora 0.5 0.7 1.0 V

Vporr 0.5 0.7 1.1 V

Vpora_off 1.0 1.4 2.0 V

Vpord_off 0.6 0.8 1.0 V

In a real application the designer is unlikely to have control of the relative power up sequence of

AVDD and DVDD. Using the POR circuit to monitor VMID ensures a reasonable delay between

applying power to the device and Device Ready.

Figure 9 and Figure 10 show typical power up scenarios in a real system. Both AVDD and DVDD

must be established and VMID must have reached the threshold Vporr before the device is ready

and can be written to. Any writes to the device before Device Ready will be ignored.

Figure 9 shows DVDD powering up before AVDD. Figure 10 shows AVDD powering up before

DVDD. In both cases, the time from applying power to Device Ready is dominated by the charge

time of VMID.

A 10uF cap is recommended for decoupling on VMID. The charge time for VMID will dominate the

time required for the device to become ready after power is applied. The time required for VMID to

reach the threshold is a function of the VMID resistor string and the decoupling capacitor. The

Resistor string has an typical equivalent resistance of 50kΩ (+/-20%). Assuming a 10uF capacitor,

the time required for VMID to reach threshold of 1V is approx 110ms.

WM8775 Production Data

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DEVICE DESCRIPTION

INTRODUCTION

WM8775 is a stereo audio ADC, with a flexible four input multiplexor. It is available in a single

package and cont roll ed by either a 3-wire or a 2- wire interfac e.

The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC,

using external resi stors to reduce the am plitude of larger signal s to within the normal operating range

of the ADC. The ADC has an analogue input PGA and a digital gain control, accessed by one

21dB in 0.5dB steps. The digital gain control allows attenuation from -21.5dB to -103dB in 0.5dB

steps . This allows the user maximum flexibilit y in the use of the ADC.

The Audio Interface may be configured to operate in either master or slave mode. In Slave mode

ADCLRC and BCLK ar e all inp uts. I n Master mode ADCLRC and BCLK are out puts. The audio data

interface supports right, left and I2S interface formats along with a highly flexible DSP serial port

interface. Operation using system clock of 256fs, 384fs, 512fs or 768fs is provided. In Slave mode

select ion between clock rates i s aut om at ic a ll y cont rol l ed. In master m ode the master clock to s am pl e

rate ratio i s set by cont rol bit ADCRATE. Master clock sam ple rates (f s) from les s than 32kHz up to

96kHz are allowed, provided the appropriate system clock is input.

Control of internal functionality of the device is by 3-wire SPI compatible or 2-wire serial control

interface. E ither i nterface may be asynchronous to t he audio dat a interfac e as contr ol data will be re-

synchronised to the audio processing internally.

AUDIO DATA SAMPLING RATES

In a t ypical digit al audio sys tem there is only one c entral cloc k sour ce produc ing a r eference cl ock to

which all audio data process ing i s s ynchronised. Thi s cl ock is often referred to as the audi o system ’s

Master Clock. The external master syst em clock can be applied directly through the MCLK input pin

with no software configuration nec essary. In a system where there are a number of possibl e sources

for the reference clock it is recommended that the clock source with the lowest jitter be used to

optimise the performance of the ADC.

The master clock for W M8775 supports ADC audio sam pling rates from 256fs to 768fs, where fs is

the audio sampling frequency (ADCLRC) typically 32kHz, 44.1kHz, 48kHz or 96kHz. The master

cloc k is us ed to operate the digita l fi lt ers and the noise s haping c i rcui ts .

In Slave mode, the WM8775 has a master detection circuit that automatically determines the

relationship between the master clock frequency and the sampling rate (to within +/- 32 system

clocks). If there is a greater than 32 clocks error the interface is disabled and m aintains the output

level at the last sample. The master clock must be synchronised with ADCLRC, although the

W M8775 i s tol erant of phas e v ariations or j itter on thi s cl ock. Tabl e 6 shows the typical m aster cloc k

frequency input s for the WM8775.

The s ignal process ing for the W M8775 t ypically operates at an overs ampli ng rate of 128fs . For ADC

operation at 96kHz, it is recommended that the user set the ADCOSR bit. This changes the ADC

signal processing oversample rate to 64fs.

System Clock Frequency (MHz )

SAM PLING

RATE

(ADCLRC) 256fs 384fs 512fs 768fs

32kHz 8.192 12.288 16.384 24.576

44.1kHz 11.2896 16.9340 22.5792 33.8688

48kHz 12.288 18.432 24.576 36.864

96kHz 24.576 36.864 Unavailable Unavailable

Table 6 System Clock Frequencies Versus Sampling Rate

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In Master mode BCLK and ADCLRC are generated by the W M8775. The frequency of ADCLRC is

set by setting the required ratio of MCLK to ADCLRC using the ADCRATE control bit (Table 7).

ADCRATE[2:0] MCLK:ADCLRC RATIO

010 256fs

011 384fs

100 512fs

101 768fs

Table 7 Master Mode MCLK:ADCLRC Ratio Select

Table 8 shows the settings for AD CRATE for common sample rates and MCLK frequencies.

System Clo ck Freq uency (MHz)

256fs 384fs 512fs 768fs

SAM PLING

RATE

(ADCLRC)

ADCRATE

=010 ADCRATE

=011 ADCRATE

=100 ADCRATE

=101

32kHz 8.192 12.288 16.384 24.576

44.1kHz 11.2896 16.9340 22.5792 33.8688

48kHz 12.288 18.432 24.576 36.864

96kHz 24.576 36.864 Unavailable Unavailable

Table 8 Master Mode ADCLRC Frequency Selection

BCLK is also generated by the WM8775. The frequency of BCLK depends on the mode of operat ion.

If using 256, 384, 512 or 768fs (ADCRATE=010, 011 ,100 or 101) BCLK = MCLK/4. However if DSP

mode is selec t ed as the audio int erf ac e m ode then BCLK =MCLK.

POWERDOWN MODES

The W M8775 has powerdown control bits allowing specific parts of the WM8775 to be powered off

when not being used. The 4-channel input source selector and input buffer may be powered down

using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN4L/R)

are switched to a buffered VMIDADC. Control bit ADC PD pow ers off the ADC and also the ADC input

PGAs. Setting AINPD and ADCPD will powerdown everything except the references VMIDADC and

ADCREFP. These may be powered down by setting PDWN. Setting PDWN will override all other

powerdown control bits. It is recommended that the 4-channel input mux and buffer AINPD and

ADCPD are powered down before setting PDWN. The default is for all powerdown bits to be 0 i.e.

enabled.

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DIGITAL AUDIO INTERFACE

MASTER AND SLAVE MOD ES

The audi o interface operat es in either S lave or Master m ode, select able using the MS control bit. In

both Master and Slave modes ADCDAT is always an output. The default is Slave mode.

In Slave mode (MS=0) ADCLRC and BCLK are inputs to the WM8775 (Figure 11). ADCLRC is

sam pled by t he WM8775 on the ris ing edge o f BCLK . A DC data is output on DOUT and c hanges on

the falling edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so

that ADCLRC is sampled on the falling edge of BCLK and DOUT changes on the rising edge of

BCLK.

BCLK

DOUT

ADCLRC

WM8775

ADC DVD

Controller

Figure 11 Slave Mode

In Master mode (MS=1) ADCLRC and BCLK are outputs from the WM8775 (Figure 12). ADCLRC

and BI TCLK are generated by the W M8775. A DCDAT is output on DOUT and changes on the falling

edge of BCLK . By set ting control bit BCLKINV , the polarity of BCLK may be reversed so that DOUT

changes on the rising edge of BCLK.

BCLK

DOUT

ADCLRC

WM8775

ADC DVD

Controller

Figure 12 Master Mode

Product ion Data WM8775

w PD, Rev 4.4, October 2008

AUDIO INTERFACE FORMATS

Audio dat a out put from the A DC f il ter s, via the Digital A udio I nterfac e. 5 popular interfa c e formats are

supported:

• Left Justi fi ed m ode

• Right Justified mode

• I

2S mode

• DSP Mode A

• DSP Mode B

All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the

exception of 32 bit right justified mode, which is not supported.

In left justifi ed, right just ified and I2S modes, the digital a udio interface out puts ADC dat a on DOUT.

Audio Data for each stereo channel is time multiplexed with ADCLRC indicating whether the left or

right c hannel i s present. A DCLRC is als o used as a t i m i ng r eferenc e t o i ndic at e the beginning or end

of the data words.

In left justifi ed, right justifi ed and I 2S modes, the minimum number of BCLKs per ADCLRC period is 2

tim es t he sel ected word length. ADCLRC must be high for a mini mum of word length BCLKs and low

for a minimum of word length BCLKs. Any mark to space ratio on ADCLRC is acceptable provided

the above requirements are met.

In DSP Mode A or B, the ADC data may also be output, with ADCLRC used as a frame sync to

identify the MSB o f t he f i rs t word. The m i nimum number of BCLKs per ADCLRC period is 2 times t he

selec ted word length

LEFT JUSTIFIED MODE

In left justi fied m ode, the MSB of the AD C data is output on DOUT and changes on the same falli ng

edge of BCLK as A DCLRC and m ay be s ampled on the r isi ng edge of BCLK. ADCLRC is high during

the left samples and low during the right samples (Figure 13).

LEFT CHANNEL RIGHT CHANNEL

ADCLRC

BCLK

DOUT

1/fs

n321 n-2 n-1

LSBMSB

n321 n-2 n-1

LSBMSB

Figure 13 Left Justified Mode Timing Diagram

RIGHT JUSTIFIED MODE

In right justif ied mode, the LSB of the ADC dat a is output on DOUT and changes on the fall ing edge

of BCLK precedi ng a ADCLRC t ransiti on and m ay be sam pled on the rising edge of BCLK. ADCLRC

is high during the left samples and low during the right samples (Fi gure 14).

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LEFT CHANNEL RIGHT CHANNEL

ADCLRC

BCLK

DOUT

1/fs

n321 n-2 n-1

LSBMSB

n321 n-2 n-1

LSBMSB

Figure 14 Right Justified Mode Timing Diagram

I2S MODE

In I2S mode, the MSB of the ADC data is output on DOUT and changes on the first falling edge of

BCLK fol lowing an A DCLRC transiti on and m ay be sam pled on the r ising edge of B CLK. ADCLRC is

low during the left sam ples and high during the right sam pl es .

LEFT CHANNEL RIGHT CHANNEL

ADCLRC

BCLK

DOUT

1/fs

n321 n-2 n-1

LSB

MSB

n321 n-2 n-1

LSB

MSB

1 BCLK

Figure 15 I2S Mode Timing Diagram

DSP MODE

In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A)

rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data

imm ediately fol lows left c hannel data. Depending on word l ength, BCLK frequency and sam ple rate,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In devic e m aster m ode, the LRC output will resem ble the fram e pulse shown in Figure 16 and Figure

17. In device slave mode, Figure 18 and Figure 19, it is possible to use any length of frame pulse

less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period

before the rising edge of the next frame pulse.

Product ion Data WM8775

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Figure 16 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)

Figure 17 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)

Figure 18 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)

WM8775 Production Data

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Figure 19 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave)

CONTROL INTERFACE OPERATION

The WM8775 is c ontrol led using a 3-wire serial interfac e in a SPI com pati ble confi guration or

a 2-wire serial i nterface m ode. The int erface t ype is selec ted by the MODE pin as shown in

Table 9.

MODE Control Mode

0 2 wire interface

1 3 wire interface

Table 9 Control Interface Selectio n via M O DE pin

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

DI is used for the program dat a, CL is used to c lock in the program data and CE is used to lat ch the

program data. DI is sampled on the rising edge of CL. The 3-wire interface protocol is shown in

Figure 20.

Figure 20 3-Wire SPI Compatible Interface

1. B[15:9] are Control Address Bits

2. B[8:0] are Control Data Bits

3. CE is edge sensitive – the data is latched on the risi ng edge of CE.

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Product ion Data WM8775

w PD, Rev 4.4, October 2008

2-WIRE SERIAL CONTROL MODE

The WM8775 supports software control via a 2-wire serial bus. Many devices can be controlled by

the sam e bus, and each device has a unique 7-bit address (t his is not the sam e as the 7- bit address

of each register in the WM8775).

The W M8775 operates as a sl ave device only. The contr oller indic ates t he start of data transfer with

a high to low transition on DI while CL remains high. This indicates that a device address and data

will foll ow. All devices on the 2-wire bus respond to the start condit ion and shift in the next eight bits

on DI (7-bit address + Read/Write bit, MSB first ). If the devic e address recei ved matches the address

of t he WM8775 and the R/W bit is ‘0’ , indi c at ing a write, then the WM8775 responds by pulling DI low

on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’, the WM8775

returns to the idle condition and wait for a new start condition and valid address.

Once t he W M8775 h as ack nowledged a correc t address , t he cont roller sends the first byte of co ntrol

data (B15 to B8, i.e. the WM8775 register address plus the first bit of register data). The WM8775

then ack nowledges the firs t data byte by pulling DI low for one clock pulse. The controller then s ends

the sec ond byte of c ontrol data (B 7 to B0, i . e. the remaini ng 8 bit s of r egis t er data) , and the WM8775

acknowledges again by pulling DI low.

The transfer of data is complete when there is a low to high transition on DI while CL is high. After

receiving a compl ete address and data s equence the W M8775 retur ns to the idle stat e and wai ts for

another start condition. If a start or stop condition is detected out of sequence at any point during

data transfer (i.e. DI changes while CL is high), the device jumps to the idle condition.

Figure 21 2-Wire Serial Interface

1. B[15:9] are Control Addr ess Bits

2. B[8:0] are Control Data Bits

The WM8775 has two possible device addresses, which can be selected using the CE pin.

CE STATE DEVICE ADDRESS

Low 0011010 (0 x 34h)

High 0011011 (0 x 36h)

Table 10 2-Wi re M P U Interface Address Selection

CONTRO L INTERFACE REGISTERS

DIG ITAL AUDIO IN TE RFACE CONT R OL REGIST ER

Interface format is selected via the FMT[1:0] register bits:

R11(0Bh)

0001011

ADC Interfac e Control

1:0 ADCFMT

[1:0] 10 Interface format Select

00 : right just if ied m ode

01: left justified m ode

10: I2S mode

11: DSP mode A or B

In left justified, right justified or I2S modes, the LRP register bit controls the polarity of ADCLRC. If

this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown Figure 13,

Figure 14 and Figure 15. Note that if this feature is used as a means of swapping the left and right

channels, a 1 s am ple phas e diff erence will be int roduced. In DSP m odes, the LRP register bit is us ed

to selec t between modes A and B.

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In left/right/ I2S modes:

ADCLRC Polarity (normal)

0 : normal A DCLRC polarity

1: inverted ADCLRC polarity

R11(0Bh)

0001011

Interfac e Control

2 ADCLRP 0

In DSP mode:

0 : DSP mode A

1: DSP mode B

By default , ADCLRC is s ampl ed on th e risi ng edge of BCLK and should ideall y change on the falling

edge. Data sources t hat change ADCLRC on the rising edge of BCLK can be supported by set ting

the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in

Figures 12, 13, 14, and 15.

R11(0Bh)

0001011

Interfac e Control

3 ADCBCP 0 BCLK Polarity (DSP modes)

0 : normal B CLK polar it y

1: inverted BCLK polar it y

The WL[1:0] bits are used to control the input word length.

R11(0Bh)

0001011

Interfac e Control

5:4 ADCWL

[1:0] 10 Word Length

00 : 16 bit data

01: 20 bit data

10: 24 bit data

11: 32 bit data

Note:

1. If 32-bit mode is selected in right justified mode, the WM8775 defaults to 24 bits.

2. In 24 bit I2S mode, any width of 24 bits or l es s i s supported provided that ADCLRC is high for a

minimum of 24 BCLKs and low for a minim um of 24 BCLK s .

W hen operating the A DC digital interfac e in slave mode, to opti mi se the performanc e of the A DC it is

recomm ended that t he ADCMCLK and ADCBCLK input signals do not have coinciding r ising edges .

The ADCMCLK bit provides the option to internally inv ert the ADCMCLK input signal when the input

signals have coinciding rising edges.

R11(0Bh)

0001011

Interfac e Control

6 ADCMCLK 0 ADCMCLK Polarity

0 : non-inverted

1: inverted

ADC MASTE R MODE

Control bit MS selects between audio interface Master and Slave Modes. In Master m ode ADCLRC

and BCLK are outputs and are generated by the WM8775. In Slave mode ADCLRC and BCLK are

inputs to WM8775.

R12(0Ch)

0001100

Interfac e Control

8 ADCMS 0 Audio Interface Master/Slave Mode

select:

0 : Slave Mode

1: Master Mode

Product ion Data WM8775

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MASTER MODE ADCLRC FREQUENCY SELECT

In Master mode the WM8775 generates ADCLRC and BCLK. These clocks are derived from the

mas ter cl ock . The ratio of MCLK to ADCLRC is set by ADCRATE.

R12(0Ch)

0001100

ADCLRC Frequency

Select

2:0 ADCRATE[2:0] 010 Master Mode MCLK:ADCLRC

ratio select:

010: 256fs

011: 384fs

100: 512fs

101: 768fs

ADC OVERSAMPLING RATE SELECT

For ADC operati on at 96kHz it is recom mended that the user set the ADCOSR bit. This c hanges the

ADC signal proces s i ng oversample rate to 64fs.

R12(0Ch)

0001100

ADC Oversam pli ng Rate

3 ADCOSR 0 ADC oversam pl ing rate sel ect

0: 128x oversampling

1: 64x oversampling

POWERDOWN MODE AND ADC DISABLE

Setting the PDWN register bit immediately powers down the WM8775, including the references,

overriding all other powerdown control bits. Al l trace of the previous input sampl es is removed, but all

control register sett ings are preserved. W hen PDW N is cleared, the digi tal filt ers will be re-initialis ed.

It is recommended that the 4-channel input mux and buffer, and ADC are powered down before

setting PDWN.

The ADC m ay also be powered down by setti ng the ADCPD disable bit. Sett ing ADCPD will disabl e

the AD C and select a low power m ode. The A DC digit al filt ers will be reset and will reinitial ise when

ADCPD is reset.

0 PDWN 0 Power Down Mode Selec t:

0 : Normal Mode

1: Power Down Mode

1 ADCPD 0 ADC Disable:

0 : Normal Mode

1: Power Down Mode

R13(0Dh)

0001101

Powerdown Control

6 AINPD 0 Analogue Input Disable:

0 : Normal Mode

1 : Power Down Mode

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w PD, Rev 4.4, October 2008

ADC GAIN CONTROL

The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the

analogue and digital gains are adjust ed by the same regis ter, LAG for the left and RAG for the ri ght.

The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows

further attenuation (after t he ADC) from -21.5dB t o -103dB in 0.5dB st eps. Table 11 shows how the

regist er maps the analogue and digi tal gains.

LAG/RAG[7:0] ATTENUATION

LEVEL ANALOGU E PGA DIGITAL

A TTENTUATION

00(hex) -∞ dB (mute) -21dB Digital mute

01(hex) -103dB -21dB -82dB

: : : :

A4(hex) -21.5dB -21dB -0.5dB

A5(hex) -21dB -21dB 0dB

: : : :

CF(hex) 0dB 0dB 0dB

: : : :

FE(hex) +23.5dB +23.5dB 0dB

FF(hex) +24dB +24dB 0dB

Table 11 Analogue and Digital Gain Mapping for AD C

Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to

write the same attenuation value to both left and right volume control registers, saving on software

writes. The ADC volume and mute also applies to the bypass signal path.

In additi on a zero cross detect circui t is provided for the input PGA. W hen ZCLA/ZCRA is set wit h a

write, the gain will update only when the input signal approaches zero (midrail). This minimises

audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which

will generate an update aft er a mini mum of 131072 master cloc ks (= ~10.5ms with a mast er clock of

12.288MHz). The timeout clock may be disabled by setting TOD.

R7 (07h)

0000111

Timeout Clock Disable

3 TOD 0

Analogue PGA Z ero cross detec t

tim eout dis abl e

0 : Tim eout enabled

1: Timeout disabled

Product ion Data WM8775

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ADDRESS BIT LABEL DEFAULT DESCRIPTION

7:0 LAG[7:0] 11001111

(0dB) Attenuation data for Left channel ADC gain in 0.5dB steps. See

Table 11.

R14(0Eh)

0001110

Attenuation

ADC L 8 ZCLA 0

Left channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

7:0 RAG[7:0] 11001111

(0dB) Attenuati on data for right c hannel A DC gain in 0.5dB st eps. See

Table 11.

R15(0Fh)

0001111

Attenuation

ADCR 8 ZCRA 0

Right channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

R21(15h)

0010101

ADC Input Mux

8 LRBOTH 0 Right channel input PGA controlled by left channel register

0 : Right channel uses RAG .

1 : Right channel uses LA G.

7 MUTELA 0 Mute for lef t c hannel ADC

0: Normal Operation

1: Mute ADC left

R21(15h)

0010101

ADC Mut e

6 MUTERA 0 Mute for right c hannel A DC

0: Normal operation

1: Mute ADC right

ADC HIGHPASS FILTER DISABLE

The ADC digit al fi lters c ontain a di gital high pass f ilter. This def aults t o enabled and can be disabled

using software control bit ADCHPD.

R11(0Bh)

0001011

ADC Control

8 ADCHPD 0 ADC High pass filter disable:

0: High pass filter enabled

1: High pass filter disabled

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LIMITER / AUTOMATIC LEVEL CONTROL (ALC)

The WM8775 has an automatic pga gai n c ont rol ci rcui t, which can f unc ti on as a peak li miter or as an

automatic level control (ALC). In peak limiter mode, a digital peak detector detects when the input

signal goes a bove a predefined level and will ram p the pga gain down to prevent the signal becom i ng

too large f or the input range of t he ADC. W hen the signal returns to a level below the threshold, the

pga gain is slowly returned t o its starting level . The peak limit er cannot increase the pga gain above

its static level.

Figure 22 Limiter Operation

In ALC mode, the circuit aims to keep a constant recording volume irrespective of the input signal

level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC

input rem ains cons tant. A di gital peak detector m onitors the ADC output and changes the P GA gain

if necess ary.

Figure 23 ALC Operation

hold

time decay

time attack

time

input

signal

after

ALC

PGA

gain

ALC

target

level

input

signal

after

PGA

gain

Limiter

threshold

attack

time decay

time

Product ion Data WM8775

w PD, Rev 4.4, October 2008

The gain control circuit is enabled by setting the LCEN control bit. The user can select between

Limiter mode and three different ALC modes using the LCSEL control bits.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R17(11h)

0010001

ALC Control 2

8 LCEN 0 Enable the PGA gain control cir cuit.

0 = Disabled

1 = Enabled

R16(10h)

0010000

ALC Control 1

8:7 LCSEL 00 LC function select

00 = Limiter

01 = ALC Right channel only

10 = ALC Left channel only

11 = ALC Stereo

The lim iter f unction only oper ates in s tereo, which means that the peak detector takes the m aximum

of left and right c hannel peak values, and any new gai n sett ing is appl ied to both left and right PGAs ,

so that the stereo image is preserved. However, the ALC function can also be enabled on one

channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other

channel runs independently with its PGA gain set through the control register.

W hen enabled, t he threshol d for the limiter or target l evel for t he ALC is program med us ing the LCT

control bits. This allows the threshold/target level to be programmed between - 1dB and -16dB in 1dB

steps. Note that for the ALC, target levels of -1dB and -2dB give a threshold of -3dB. This is

because the ALC can give erroneous operati on if the target lev el is s et too high.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R16(10h)

0010000

ALC Control 1

3:0 LCT[3:0] 1011

(-5dB) Lim i ter Thres hold/ A LC target lev el in

1dB steps .

0000: -16dB FS

0001: -15dB FS

…

1101: -3dB FS

1110: -2dB FS

1111: -1dB FS

ATTACK AND DECAY TIMES

The lim i ter and ALC have di ff erent at tac k and decay times which determ ine thei r operation. However,

the attack and decay times are defined slightly differently for the limiter and for the ALC. DCY and

ATK control the decay and attack times, respectively.

Decay time (Gain Ramp-Up). When in ALC mode, this is defined as the time that it takes for the

PGA gain to ramp up across 90% of its range ( e.g. f rom –21dB up to +20 dB ). When i n l i m i ter m od e,

it is defined as the time it takes for the gain to ramp up by 6dB.

The decay time can be programmed in power-of-two (2n) steps. For the ALC this gives times from

33.6ms , 67. 2ms, 134. 4m s etc . t o 34. 41s. F or the l im iter thi s gi ves ti mes from 1.2m s , 2.4m s etc ., up

to 1.2288s.

Attack time (Gain Ra mp-Down) W hen i n ALC m ode, this is defined as t he time t hat it tak es for the

PGA gain to ramp down across 90% of its range (e.g. from +20dB down to -21dB gain). When in

limiter mode, it is defined as the time it takes for the gain to ramp down by 6dB.

The at tack t ime c an be programm ed in power-of-two (2n) s teps, fr om 8.4m s, 16. 8ms , 33.6ms etc. t o

8.6s for the ALC and from 250us, 500us, etc. up to 256ms.

The time it takes for the recording level to return to its target value or static gain value therefore

depends on bot h the attack/ dec ay ti m e and on the gain adjustment required. If the gain adjus t m ent is

small, it will be shorter than the attack/decay time.

WM8775 Production Data

w PD, Rev 4.4, October 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

LC attack (gain ramp-down) time 3:0 ATK[3:0] 0010 ALC mode

0000: 8.4ms

0001: 16.8ms

0010: 33.6ms …

(time doubles with

every step)

1010 or higher:

8.6s

Limiter Mode

0000: 250us

0001: 500us… 0010:

1ms

(time doubles with

every step)

1010 or higher: 256ms

LC decay (gain ramp-up) time

R18(12h)

0010010

ALC

Control 3

7:4 DCY [3:0] 0011 ALC mode

0000: 33.5ms

0001: 67.2ms

0010: 134.4ms

….(time doubles for

every step)

1010 or higher:

34.3ms

Limiter mode

0000: 1.2ms

0001: 2.4ms

0010: 4.8ms ….( ti m e

doubles for every

step)

1010 or higher:

1.2288s

TRANSIENT WINDOW (LIMITER ONLY)

To prevent the lim iter responding to to short duration high am pitude signals (such as hand-claps i n a

live performance), the limiter has a programmable transient window preventing it responding to

signals above the thres hold until their duration exceeds the window period. The Transi ent window i s

set in register TRANWIN.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R20(14h)

0010100

Limi ter Control

6:4 TRANWIN

[2:0] 010 Length of Transient Window

000: 0us (disabled)

001: 62.5us

010: 125us

…..

111: 4ms

ZERO CR OSS

The PGA has a zero c ross det ector to prevent g ain changes introducing noise to the signal. In ALC

mode the register bit ALCZC allows this to be turned off if desired.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R17(11h)

0010001

ALC Control 2

7 ALCZC 0

(disabled) PG A zero cros s enable

0 : disabled

1: enabled

MAXIMUM GAIN (ALC ONLY ) AND MAXIMUM ATTENUATION

To prevent low level signals being amplified too much by the ALC, the MAXGAIN register sets the

upper limit for the gain. This prevents low level noise being over-amplified. The MAXGAIN register

has no effect on the limiter operation.

The MAXATTEN register has different operation for the limiter and for the ALC. For the limiter it

defines the maximum attenuation below the static (user programmed) gain. For the ALC, it defines

the lower limit for the gain.

Product ion Data WM8775

w PD, Rev 4.4, October 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R16(10h)

0010000

ALC Control 1

6:4 MAXGAIN 111 (+24dB) Set maximum gain for the PGA (ALC

only)

111 : +24dB

110 : +20dB

…..(-4dB s teps )

010 : +4dB

001 : 0dB

000 : 0dB

Maximum att enuat ion of PG A R20(14h)

0010100

Limi ter Control

3:0 MAXATTEN 0110 Limiter

(attenuation

below static)

0011 or lower:

-3dB

0100: -4dB

…. (-1dB

steps)

1100: -12dB

ALC (lower PGA

gain limit)

1010 or lower

: -1dB

1011 : -5dB

….. (-4dB steps)

1110 : -17dB

1111 : -21dB

HOLD TIME (ALC ONLY)

The A LC also has a hold t ime, which is the time delay between the peak level det ected being below

target and the P G A gai n beginni ng to ramp up. I t c an be program med in power -of -two (2n) steps, e.g.

2.67ms , 5. 33m s, 10.67ms etc . up to 43.7m s. A lternat ively, the hold tim e can als o be set to zero. The

hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the

signal l evel is above tar get.

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R17(11h)

0010001

ALC Control 2

3:0 HLD[3:0] 0000 ALC hold time before gain is

increased.

0000: 0ms

0001: 2.67ms

0010: 5.33ms

… (time doubles with every step)

1111: 43.691s

OVERLOAD DETECTOR (ALC ONLY)

To prevent c l ippi ng when a l arge s ignal o c curs jus t af ter a period of quiet, t he A LC c ircuit includes an

overload detector. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is

ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below

87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.

(Note: If AT K = 0000, then the overload detector m akes no difference to the operation of the ALC. I t

is designed to prevent clippi ng when long attack ti m es are us ed).

NOISE GATE (ALC ONLY)

When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise

pumping” , i.e. loud hiss ing noise during silenc e periods. The W M8775 has a noise gate functi on that

prevents noise pumping by comparing the signal level at the AINL1/2/3/4 and/or AINR1/2/3/4 pins

against a noise gate thr eshold, NGTH. The noise gate cuts in when:

• Signal lev el at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boos t gain [dB ]

This is equivalent to:

• Signal lev el at input pin [dB ] < NGTH [dB]

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W hen the noise gate is triggered, the PGA gain i s held constant (preventing it from ramping up as it

would normally when the signal is quiet).

The table below summarises the noise gate control register. The NGTH control bits set the noise

gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps.

Levels at t he extrem es o f the range may cause inappropriate oper ati on, s o c are s hou ld be t ak en with

set–up of the func tion. Note that the noise gate only works in conjunct ion with the ALC functi on, and

always operates on the same channel(s) as the ALC (left, right, both, or none).

ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 NG AT 0 Nois e gate func t ion enable

1 = enable

0 = disable

R19(13h)

0010011

Noi se Gate

Control 4:2 NGTH[2:0] 000 Nois e gate thr eshold (with respec t to

analogue input level)

000: -78dBFS

001: -72dBfs

… 6 dB steps

110: -42dBFS

111: -36dBFS

ADC INPUT MU X AND POWERDOWN CO NTROL

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R21(15h)

0010101

ADC Mux and

Powerdown

Control

3:0 AMX[3:0] 0001

ADC input m ixer control bits (see

Table 12)

AIN1. One bit of AMX is allocated to each stereo input pair to allow the signals to be mixed before

being digitised by the ADC. For example, if AMX[3:0] is 0101, the input signal to the ADC will be

(AIN1L+AIN3L) on the left channel and (AIN1R+AIN3R) on the right channel.

However if the analogue input buffer is powered down, by setting AINPD, then all 4-channel mux

inputs are switched to buffered VMIDADC.

AMX[3:0] LEFT ADC INPUT

RIGH T ADC INPU T

0001 AIN1L AIN1R

0010 AIN2L AIN2R

0100 AIN3L AIN3R

1000 AIN4L AIN4R

Table 12 ADC Input Mixer Control

AIN1L/R

AIN2L/R

AIN3L/R

AIN4L/R

AMX[0]

AMX[1]

AMX[2]

AMX[3]

Figure 24 ADC Input Mixer

Product ion Data WM8775

w PD, Rev 4.4, October 2008

SOFTWARE REGISTER RES ET

Writing to register 0010111 will cause a register reset, resetting all register bits to their default

values.

REGI STER MAP

The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The

WM8775 can be configured using the Control Interface. All unused bits should be set to ‘0’.

B8 B7 B6 B5 B4 B3 B2 B1 B0

DEFAULT

(HEX)

R7 (07h) 0 0 0 0 1 1 1 0 0 0 0 0 TOD 0 0 0 000

R11 (0Bh) 0 0 0 1 0 1 1 ADCHPD 0 ADCMCLK ADCWL[1:0] ADCBCP ADCLRP ADCFMT[1:0] 022

R12 (OCh) 0 0 0 1 1 0 0 ADCMS 0 0 1 0 ADCOSR ADCRATE[2:0] 022

R13 (0Dh) 0 0 0 1 1 0 1 0 0 AINPD 0 0 1 0 ADCPD PWDN 008

R14 (0Eh) 0 0 0 1 1 1 0 ZCLA LAG[7:0] 0CF

R15 (0 F h) 0 0 0 1 1 1 1 ZCRA RAG[7:0] 0CF

R16 (10h) 0 0 1 0 0 0 0 LCSEL[1:0] MAXGAIN[2:0] LCT[3:0] 07B

R17 (11h) 0 0 1 0 0 0 1 LCEN ALCZC 0 0 0 HLD[3:0] 000

R18 (12h) 0 0 1 0 0 1 0 0 DCY[3:0] ATK[3:0] 032

R19 (13h) 0 0 1 0 0 1 1 0 0 0 0 NGTH[2:0] 0 NGAT 000

R20 (14h) 0 0 1 0 1 0 0 0 1 TRANWIN [2:0] MAXATTEN [3:0] 0A6

R21 (15h) 0 0 1 0 1 0 1 LRBOTH MUTELA MUTERA 0 AMX[3:0] 001

R23 (17h) 0 0 1 0 1 1 1 SOFTWARE RESET not reset

WM8775 Production Data

w PD, Rev 4.4, October 2008

ADDRESS BIT LABEL DEFAULT DESCRIPTION

R7 (07h)

0000111

Tim eout Clock

Disable

3 TOD 0

ADC Analogue PGA Zero cr oss detec t timeout disable

0 : Tim eout enabled

1: Timeout disabled

1:0 ADCFMT[1:0] 10 Interface format select

00: right justified mode

01: left justified mode

10: I2S mode

11: DSP mode

ADC LRC Polarity or DSP mod e A/B select 2 ADCLRP 0

In left/right/ I2S m odes :

ADCLRC Polarity (normal)

0 : normal ADCLRC polarit y

1: inverted ADCLRC polarity

DSP Mode

0: DSP mode A

1: DSP mode B

3 ADCBCP 0 BITCLK Polarity

0: Normal - ADCLRC sampled on rising edge of BCLK;

DOUT changes on fall in g edge of BCLK.

1: Inverted - ADCLRC sampled on falling edge of BCLK;

DOUT changes on rising edge of BCLK.

5:4 ADCWL[ 1:0] 10 Input Word Length

00: 16-bit Mode

01: 20-bit Mode

10: 24-bit Mode

11: 32-bit Mode (not supported in right jus t i fi ed m ode)

6 ADCMCLK 0 ADCMCLK Polarit y

0 : non-inverted

1: inverted

R11 (0Bh)

0001011

Interface

Control

8 ADCHPD 0 A DC High pass Filt er Dis abl e:

0: High pass Filter enabled

1: High pass Filter disabled

2:0 ADCRATE[2:0] 010 Master Mode MCLK:ADCLRC ratio select:

010: 256fs

011: 384fs

100: 512fs

101: 768fs

3 ADCOSR 0 ADC oversample rate select

0: 128x oversampl i ng

1: 64x oversampl ing

12 (0Ch )

0001100

Master Mode

Control

8 ADCMS 0 Maser /Slave interface mode select

0: Slave Mode – ADCLRC and BCLK are inputs

1: Master Mode – ADCLRC and BCLK are outputs

0 PWDN 0 Chip Powerdown Control (works together with ADCD):

0: All circuits running, outputs are active

1: All circuits in power save mode, outputs muted

1 ADCPD 0 ADC powerdown:

0: ADC enabled

1: ADC disabled

R13 (0Dh)

0001101

Powerdown

Control

6 AINPD 0 Input m ux and buffer powerdown

0: Input mux and buffer enabled

1: Input mux and buffer powered down

Product ion Data WM8775

w PD, Rev 4.4, October 2008

7:0 LAG[7:0] 11001111

(0dB) Attenuation data for left channel ADC gain in 0.5dB steps R14 (0Eh)

0001110

Attenuation

ADCL 8 ZCLA 0

Left channel A DC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

7:0 RAG[7:0] 11001111

(0dB) Attenuation data for right channel ADC gain in 0.5dB steps R15 (0Fh)

0001111

Attenuation

ADCR 8 ZCRA 0

Right channel ADC zero cross enable:

0: Zero cross disabled

1: Zero cross enabled

3:0 LCT[3:0] 1011

(-5dB) Lim iter Thres hold/ A LC target level in 1dB s t eps .

0000: -16dB FS

0001: -15dB FS

…

1101: -3dB FS

1110: -2dB FS

1111: -1dB FS

6:4 MAXG A IN[ 2:0] 111 (+24dB) Set Maximum Gain of PGA

111 : +24dB

110 : +20dB

….(-4dB steps)

010 : +4dB

001 : 0dB

000 : 0dB

R16 (10h)

0010000

ALC Control 1

8:7 LCSEL[1:0] 00

ALC/Limiter function select

00 = Limiter

01 = ALC Right channel only

10 = ALC Left channel only

11 = ALC Stereo (PGA registers unused)

3:0 HLD[3:0] 0000

(0ms) ALC hold time before gain is increased.

0000: 0ms

0001: 2.67ms

0010: 5.33ms

… (time doubles with every step)

1111: 43.691s

7 ALCZC 0 (zero

cross off) ALC uses zero cross detection circuit.

R17 (11h)

0010001

ALC Control 2

8 LCEN 0 E nable Gain c ontr ol ci rc ui t.

0 = Disable

1 = Enable

ALC/Limiter attack (gain ramp-down) time 3:0 ATK[3:0] 0010

(24ms) ALC mode

0000: 8.4ms

0001: 16.8ms

0010: 33.6ms…

(tim e doubles with every step)

1010 or higher: 8.6s

Limiter Mode

0000: 250us

0001: 500us…

0010: 1ms

(time doubles with every step)

1010 or higher: 256ms

ALC/Lim i ter decay (gain ramp up) tim e

R18 (12h)

0010010

ALC Control 3

7:4 DCY[3:0] 0011

(268ms/

9.6ms) ALC mode

0000: 33.5ms

0001: 67.2ms

0010: 134.4ms ….(time

doubles for every step)

1010 or higher: 34.3ms

Limiter mode

0000: 1.2ms

0001: 2.4ms

0010: 4.8ms ….(time doubles

for every step)

1010 or higher: 1.2288s

WM8775 Production Data

w PD, Rev 4.4, October 2008

0 NGAT 0 Noise gate enable (ALC only)

0 : disabled

1 : enabled

R19 (13h)

0010011

Noise Gate

Control 4:2 NGTH 000 Noise gate threshold

000: -78dBFS

001: -72dBfs

… 6 dB steps

110: -42dBFS

111: -36dBFS

Maximum attenuation of PGA 3:0 MAXATTEN

[3:0] 0110 Limiter

(attenuation below static)

0011 or lower: -3dB

0100: -4dB

…. (-1dB steps)

1100 or higher: -12dB

ALC

(lower PGA gain lim i t )

1010 or lower: -1dB

1011 : -5dB

….. (-4dB st eps )

1110 : -17dB

1111 : -21dB

R20 (14h)

0010100

Limiter

Control

6:4 TRANWIN [2:0] 010 Length of Transient Window

000: 0us (disabled)

001: 62.5us

010: 125us

…..

111: 4ms

3:0 A MX[3:0] 0001 ADC left channel input m i xer control bits

AMX[3:0] ADC LEFT IN ADC RIGHT IN

0001 AIN1L AIN1R

0010 AIN2L AIN2L

0100 AIN3L AIN3R

1000 AIN4L AIN4R

6 MUTERA 0

Mute for right channel ADC

0: Mute off

1: Mute on

7 MUTELA 0

Mute for left channel ADC

0: Mute off

1: Mute on

R21 (15h)

0010101

ADC Mixer

Control

8 LRBOTH 0 Setting LRBOTH will write the same gain value to RAG[7:0] and

LAG[7:0].

R23 (17h)

0010111

Software

Reset

[8:0] RESET Not reset W riting to this register will apply a reset to the device registers.

Table 13 Register Map Descript ion

Product ion Data WM8775

w PD, Rev 4.4, October 2008

DIGITAL FILTER CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC Filt er

±0.01 dB 0 0.4535fs

Passband -6dB 0.4892fs

Pass band ripple ±0.01 dB

Stopband 0.5465fs

Stopband Attenuation f > 0.5465fs -65 dB

Group Delay 22 fs

Table 14 Digital Filter Characteristics

ADC FILTER RESPONSES

-80

-60

-40

-20

0 0.5 1 1.5 2 2.5 3

Response (dB)

Frequency (Fs)

Figure 25 ADC Digital Filter Frequency Response

-0.02

-0.015

-0.01

-0.005

0.005

0.01

0.015

0.02

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Response (dB)

Frequency (Fs)

Figure 26 ADC Digital Filter Ripple

ADC HIGH PASS FILTER

The WM8775 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the

following polynomial.

Figure 27 ADC Highpass Filter Response

1 - z

-1

1 - 0.9995z

-1

H(z) =

-15

-10

-5

0 0.0005 0.001 0.0015 0.002

Response (dB)

Frequency (Fs)

WM8775 Production Data

w PD, Rev 4.4, October 2008

APPLICATIONS INFORMATION

EXTERNAL CIRCUIT CONFIGURATION

In order t o allow the use of 2V rm s and larger inputs to the A DC inputs , a s truct ure is us ed that uses

external resistors to drop these larger voltages. This also increases the robustness of the circuit to

external abuse such as ESD pulse. Figure 28 shows the ADC input multiplexor circuit with external

com ponents all owing 2Vrm s inputs to be appli ed.

AIN1L

10K10uF

AIN2L

10K10uF

AIN3L

10K10uF

AIN4L

10K10uF

AIN1R

10K10uF

AIN2R

10K10uF

AIN3R

10K10uF

AIN4R

10K10uF

SOURCE

SELECTOR

INPUTS

AINVGR

AINOPR

AINVGL

AINOPL

Figure 28 ADC Input Multiplexor Configuration

Product ion Data WM8775

w PD, Rev 4.4, October 2008

RECOMMENDED EXTERNAL COMPONENTS

Figure 29 Recommended External Component Di agram

WM8775 Production Data

w PD, Rev 4.4, October 2008

PACKAGE DIMENSIONS

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.

B . THIS DRAWING IS SUBJECT TO CHAN GE WITHOUT NOTICE.

C . BODY D IMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0 .20MM.

D. MEETS JED EC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

DM007.EDS: 28 P IN SSO P (10 .2 x 5.3 x 1.75 mm)

Symbols Dimensions

(mm)

MIN NOM MAX

A----- ----- 2.0

A10.05 ----- 0.25

A21.65 1.75 1.85

b0.22 0.30 0.38

c0.09 ----- 0.25

D9.90 10.20 10.50

E7.40 7.80 8.20

5.00 5.30 5.60

L0.55 0.75 0.95

AA2 A1

E1 E

GAUGE

PLANE

0.25

SEATING PLANE

-C-

0.10 C

REF: JED E C.95, M O-150

L11.25 REF

0.65 BSC

0o4o8o

Product ion Data WM8775

w PD, Rev 4.4, October 2008

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Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.

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safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer

product desi gn. T he c ustom er is s olely respons ibl e for it s s elec tion and use of W olf son products . W ol fson i s not liable for

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