Data Sheet 09.94
Microcomputer Components
C165
16-Bit CMOS Single-Chip Microcontroller
Semiconductor Group 1 09.94
●High Performance 16-bit CPU with 4-Stage Pipeline
●100 ns Instruction Cycle Time at 20-MHz CPU Clock
●500 ns Multiplication (16 × 16 bits), 1 µs Division (32 / 16 bit)
●Enhanced Boolean Bit Manipulation Facilities
●Additional Instructions to Support HLL and Operating Systems
●Register-Based Design with Multiple Variable Register Banks
●Single-Cycle Context Switching Support
●Up to 16 MBytes Linear Address Space for Code and Data
●2 KBytes On-Chip RAM
●4 KBytes On-Chip ROM (RM types only)
●Programmable External Bus Characteristics for Different Address Ranges
●8-Bit or 16-Bit External Data Bus
●Multiplexed or Demultiplexed External Address/Data Buses
●Five Programmable Chip-Select Signals
●Hold- and Hold-Acknowledge Bus Arbitration Support
●1024 Bytes On-Chip Special Function Register Area
●Idle and Power Down Modes
●8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event
Controller (PEC)
●16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 50 ns
●Two Multi-Functional General Purpose Timer Units with 5 Timers
●Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
●Programmable Watchdog Timer
●Up to 77 General Purpose I/O Lines
●Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,
Programming Boards
●On-Chip Bootstrap Loader
●100-Pin MQFP Package (EIAJ)
●100-Pin TQFP Package (Thin QFP)
09.94 Data Sheet Addendum – Attention
The C165 is offered in two different packages:
P-MQFP-100: rectangular package
P-TQFP-100: square package.
For the pin configurations please refer to page 3 (P-MQFP-100) and page 8 (P-TQFP-100) of the
09.94 C165 Data Sheet. Please note that the table “Pin Definition and Functions” on pages 9
through 12 lists the pin numbers for the MQFP package only.
The pin numbers for the TQFP package are different and should be taken from the pin
configuration on page 3.
C16x-Family of
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
C165 16-Bit Microcontroller
C165
C165
Semiconductor Group 2
Introduction
The C165 is a new derivative of the Siemens SAB 80C166 family of full featured single-chip CMOS
microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with
high peripheral functionality and enhanced IO-capabilities.
Figure 1
Logic Symbol
Ordering Information
Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product
after verification of the respective ROM code.
Type Ordering Code Package Function
SAB-C165-RM Q67121-D... P-MQFP-100-2 16-bit microcontroller with
2 KByte RAM and 4 KByte ROM
Temperature range 0 to +70 ˚C
SAB-C165-LM Q67121-C862 P-MQFP-100-2 16-bit microcontroller with
2 KByte RAM
Temperature range 0 to +70 ˚C
SAF-C165-LM Q67121-C923 P-MQFP-100-2 16-bit microcontroller with
2 KByte RAM
Temperature range -40 to +85 ˚C
C165
C165
Semiconductor Group 3
Ordering Information
Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product
after verification of the respective ROM code.
Pin Configuration TQFP Package
(top view)
Figure 2
Type Ordering Code Package Function
SAB-C165-RF Q67121-D... P-TQFP-100-3 16-bit microcontroller with
2 KByte RAM and 4 KByte ROM
Temperature range 0 to +70 ˚C
SAB-C165-LF Q67121-C941 P-TQFP-100-3 16-bit microcontroller with
2 KByte RAM
Temperature range 0 to +70 ˚C
C165
C165
Semiconductor Group 4
Pin Configuration MQFP Package
(top view)
Figure 3
C165
C165
Semiconductor Group 5
Pin Definitions and Functions
Symbol Pin
No. Input (I)
Output (O) Function
P5.10 –
P5.15 100
1 - 5
100
1
2
3
4
5
I
I
I
I
I
I
I
I
Port 5 is a 6-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as timer inputs:
P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input
P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input
P5.12 T6IN GPT2 Timer T6 Count Input
P5.13 T5IN GPT2 Timer T5 Count Input
P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input
P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input
XTAL1
XTAL2
7
8
I
O
XTAL1: Input to the oscillator amplifier and input to the
internal clock generator
XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC Characteristics
must be observed.
P3.0 –
P3.13,
P3.15
10 –
23,
24
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O
I/O
I/O
O
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
O
Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is
bit-wise programmable for input or output via direction bits.
For a pin configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers.
The following Port 3 pins also serve for alternate functions:
P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output
P3.2 CAPIN GPT2 Register CAPREL Capture Input
P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output
P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input
P3.5 T4IN GPT1 Timer T4 Input for
Count/Gate/Reload/Capture
P3.6 T3IN GPT1 Timer T3 Count/Gate Input
P3.7 T2IN GPT1 Timer T2 Input for
Count/Gate/Reload/Capture
P3.8 MRST SSC Master-Rec./Slave-Transmit I/O
P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I
P3.10 T×D0 ASC0 Clock/Data Output (Asyn./Syn.)
P3.11 R×D0 ASC0 Data Input (Asyn.) or I/O (Syn.)
P3.12 BHE Ext. Memory High Byte Enable Signal,
WRH Ext. Memory High Byte Write Strobe
P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp.
P3.15 CLKOUT System Clock Output (=CPU Clock)
C165
Semiconductor Group 6
P4.0 –
P4.7 25 - 28,
31 - 34
25
...
34
I/O
O
...
O
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0 A16 Least Significant Segment Addr. Line
... ... ...
P4.7 A23 Most Significant Segment Addr. Line
RD 35 O External Memory Read Strobe. RD is activated for every
external instruction or data read access.
WR/
WRL 36 O External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a 16-
bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.
READY 37 I Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
ALE 38 O Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
EA 39 I External Access Enable pin. A low level at this pin during and
after Reset forces the C165 to begin instruction execution out
of external memory. A high level forces execution out of the
internal ROM. The C165 must have this pin tied to ‘0’.
Pin Definitions and Functions (cont’d)
Symbol Pin
No. Input (I)
Output (O) Function
C165
Semiconductor Group 7
PORT0:
P0L.0 –
P0L.7,
P0H.0 -
P0H.7
43 –
50
53 –
60
I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed bus
modes and as the data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 - D7
P0H.0 – P0H.7: I/O D8 - D15
Multiplexed bus modes:
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7: A8 - A15 AD8 - AD15
PORT1:
P1L.0 –
P1L.7,
P1H.0 -
P1H.7
61 -
68
69 - 70,
73 - 78
I/O PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after
switching from a demultiplexed bus mode to a multiplexed
bus mode.
RSTIN 81 I Reset Input with Schmitt-Trigger characteristics. A low level at
this pin for a specified duration while the oscillator is running
resets the C165. An internal pullup resistor permits power-on
reset using only a capacitor connected to VSS.
RSTOUT 82 O Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or a
watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
NMI 83 I Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C165 to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Pin Definitions and Functions (cont’d)
Symbol Pin
No. Input (I)
Output (O) Function
C165
Semiconductor Group 8
P6.0 –
P6.7 84 -
91
84
...
88
89
90
91
I/O
O
...
O
I
O
O
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 6 outputs can be configured as push/
pull or open drain drivers.
The following Port 6 pins also serve for alternate functions:
P6.0 CS0 Chip Select 0 Output
... ... ...
P6.4 CS4 Chip Select 4 Output
P6.5 HOLD External Master Hold Request Input
P6.6 HLDA Hold Acknowledge Output
P6.7 BREQ Bus Request Output
P2.8 –
P2.15 92 -
99
92
...
99
I/O
I
...
I
Port 2 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 2 outputs can be configured as push/
pull or open drain drivers.
The following Port 2 pins also serve for alternate functions:
P2.8 EX0IN Fast External Interrupt 0 Input
... ... ...
P2.15 EX7IN Fast External Interrupt 7 Input
VPP 42 -Flash programming voltage. This pin accepts the
programming voltage for flash versions of the C165.
Note: This pin is not connected (NC) on non-flash versions.
VCC 9, 30,
40, 51,
71, 80
-Digital Supply Voltage:
+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode
VSS 6, 29,
41, 52,
72, 79
-Digital Ground.
Pin Definitions and Functions (cont’d)
Symbol Pin
No. Input (I)
Output (O) Function
C165
Semiconductor Group 9
Functional Description
The architecture of the C165 combines advantages of both RISC and CISC processors and of
advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an
overview of the different on-chip components and of the advanced, high bandwidth internal bus
structure of the C165.
Note: All time specifications refer to a CPU clock of 20 MHz
(see definition in the AC Characteristics section).
Figure 4
Block Diagram
C165
Semiconductor Group 10
Memory Organization
The memory space of the C165 is configured in a Von Neumann architecture which means that
code memory, data memory, registers and I/O ports are organized within the same linear address
space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bit addressable.
The C165 is prepared to incorporate on-chip mask-programmable ROM for code or constant data.
Currently no ROM is integrated.
2 KBytes of on-chip RAM are provided as a storage for user defined variables, for the system stack,
general purpose register banks and even for code. A register bank can consist of up to 16 wordwide
(R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers
(GPRs).
1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
future members of the C165 family.
In order to meet the needs of designs where more memory is required than is provided on chip, up
to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on
PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-
State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user
the adaption of a wide range of different types of memories. In addition, different address ranges
may be accessed with different bus characteristics. Up to 5 external CS signals can be generated
in order to save external glue logic. Access to very slow memories is supported via a particular
‘Ready’ function. A HOLD/HLDA protocol is available for bus arbitration.
For applications which require less than 16 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.
C165
Semiconductor Group 11
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C165’s instructions can be executed in just one
machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast
as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 5
CPU Block Diagram
C165
Semiconductor Group 12
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.
A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack
is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient C165 instruction set which includes the following instruction
classes:
– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.
C165
Semiconductor Group 13
Interrupt System
With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal
program execution), the C165 is capable of reacting very fast to the occurrence of non-deterministic
events.
The architecture of the C165 supports several mechanisms for fast and flexible response to service
requests that can be generated from various sources internal or external to the microcontroller. Any
of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by
the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data. The C165
has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling
edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
The following table shows all of the possible C165 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
Note: Four nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from
integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used
to generate software controlled interrupt requests by setting the respective XPnIR bit. Also
the three listed Software Nodes can be used for this purpose.
C165
Semiconductor Group 14
Source of Interrupt or
PEC Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
External Interrupt 0 CC8IR CC8IE CC8INT 00’0060H18H
External Interrupt 1 CC9IR CC9IE CC9INT 00’0064H19H
External Interrupt 2 CC10IR CC10IE CC10INT 00’0068H1AH
External Interrupt 3 CC11IR CC11IE CC11INT 00’006CH1BH
External Interrupt 4 CC12IR CC12IE CC12INT 00’0070H1CH
External Interrupt 5 CC13IR CC13IE CC13INT 00’0074H1DH
External Interrupt 6 CC14IR CC14IE CC14INT 00’0078H1EH
External Interrupt 7 CC15IR CC15IE CC15INT 00’007CH1FH
GPT1 Timer 2 T2IR T2IE T2INT 00’0088H22H
GPT1 Timer 3 T3IR T3IE T3INT 00’008CH23H
GPT1 Timer 4 T4IR T4IE T4INT 00’0090H24H
GPT2 Timer 5 T5IR T5IE T5INT 00’0094H25H
GPT2 Timer 6 T6IR T6IE T6INT 00’0098H26H
GPT2 CAPREL Register CRIR CRIE CRINT 00’009CH27H
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8H2AH
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011CH47H
ASC0 Receive S0RIR S0RIE S0RINT 00’00ACH2BH
ASC0 Error S0EIR S0EIE S0EINT 00’00B0H2CH
SSC Transmit SCTIR SCTIE SCTINT 00’00B4H2DH
SSC Receive SCRIR SCRIE SCRINT 00’00B8H2EH
SSC Error SCEIR SCEIE SCEINT 00’00BCH2FH
X-Peripheral Node 0 XP0IR XP0IE XP0INT 00’0100H40H
X-Peripheral Node 1 XP1IR XP1IE XP1INT 00’0104H41H
X-Peripheral Node 2 XP2IR XP2IE XP2INT 00’0108H42H
X-Peripheral Node 3 XP3IR XP3IE XP3INT 00’010CH43H
Software Node CC29IR CC29IE CC29INT 00’0110H44H
Software Node CC30IR CC30IE CC30INT 00’0114H45H
Software Node CC31IR CC31IE CC31INT 00’0118H46H
C165
Semiconductor Group 15
The C165 also provides an excellent mechanism to identify and to process exceptions or error
conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate
non-maskable system reaction which is similar to a standard interrupt service (branching to a
dedicated vector table location). The occurrence of a hardware trap is additionally signified by an
individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise during run-
time:
Exception Condition Trap
Flag Trap
Vector Vector
Location Trap
Number Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008H
00’0010H
00’0018H
02H
04H
06H
II
II
II
Class B Hardware Traps:
Undefined Opcode
Protected Instruction
Fault
Illegal Word Operand
Access
Illegal Instruction Access
Illegal External Bus
Access
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028H
00’0028H
00’0028H
00’0028H
00’0028H
0AH
0AH
0AH
0AH
0AH
I
I
I
I
I
Reserved [2CH – 3CH] [0BH – 0FH]
Software Traps
TRAP Instruction Any
[00’0000H –
00’01FCH]
in steps
of 4H
Any
[00H – 7FH]Current
CPU
Priority
C165
Semiconductor Group 16
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which may be used
for many different time related tasks such as event timing and counting, pulse width and duty cycle
measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1
and GPT2. Each timer in each module may operate independently in a number of different modes,
or may be concatenated with another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three
basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the
input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while
Counter Mode allows a timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of
a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has
one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the
timers in module GPT1 is 400 ns (@ 20-MHz CPU clock).
The count direction (up/down) for each timer is programmable by software or may additionally be
altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking.
Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer over-
flow/underflow. The state of these latches may be output on port pins (TxOUT) e.g. for time out
monitoring of external hardware components, or may be used internally to clock timers T2 and T4
for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated without software intervention.
With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event
control and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via
a programmable prescaler or with external signals. The count direction (up/down) for each timer is
programmable by software or may additionally be altered dynamically by an external signal on a
port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of
timer T6, which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The
overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1,
and to cause a reload from the CAPREL register. The CAPREL register may capture the contents
of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer
T5 may optionally be cleared after the capture procedure. This allows absolute time differences to
be measured or pulse multiplication to be performed without software overhead.
C165
Semiconductor Group 17
Figure 6
Block Diagram of GPT1
C165
Semiconductor Group 18
Figure 7
Block Diagram of GPT2
Parallel Ports
The C165 provides up to 77 I/O lines which are organized into six input/output ports and one input
port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when configured as inputs. The output drivers of three
I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control
registers. During the internal reset, all port pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with them. PORT0
and PORT1 may be used as address and data lines when accessing external memory, while Port
4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is
enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals
(BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial
interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is
used for timer control signals. All port lines that are not used for these alternate functions may be
used as general purpose I/O lines.
C165
Semiconductor Group 19
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).
They are upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family
and support full-duplex asynchronous communication up to 625 KBaud and half-duplex
synchronous communication up to 5 Mbaud (2.5 Mbaud on the ASC0) @ 20-MHz system clock.
Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning.
For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for
each serial channel.
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit
and terminated by one or two stop bits. For multiprocessor communication, a mechanism to
distinguish address from data bytes has been included (8-bit data + wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length
synchronously to a shift clock which can be generated by the SSC (master mode) or by an external
master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0
always shifts the LSB first.
A loop back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 25 µs and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval
after reset is 6.55 ms (@ 20 MHz).
C165
Semiconductor Group 20
Instruction Set Summary
The table below lists the instructions of the C165 in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation of the
instructions, parameters for conditional execution of instructions, and the opcodes for each
instruction can be found in the “C16x Family Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Instruction Set Summary
Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte operands) 2 / 4
OR(B) Bitwise OR, (word/byte operands) 2 / 4
XOR(B) Bitwise XOR, (word/byte operands) 2 / 4
BCLR Clear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/L Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data 4
CMP(B) Compare word (byte) operands 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR 2
SHL / SHR Shift left/right direct word GPR 2
ROL / ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
C165
Semiconductor Group 21
MOV(B) Move word (byte) data 2 / 4
MOVBS Move byte operand to word operand with sign extension 2 / 4
MOVBZ Move byte operand to word operand. with zero extension 2 / 4
JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clear bit if direct bit is set 4
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call
absolute subroutine 4
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and update
register with word operand 4
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct
word register from system stack 2
RETI Return from interrupt service subroutine 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode
(supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
NOP Null operation 2
Instruction Set Summary (cont’d)
Mnemonic Description Bytes
C165
Semiconductor Group 22
Special Function Registers Overview
The following table lists all SFRs which are implemented in the C165 in alphabetical order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended
SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected addressing
mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its
short 8-bit address (without using the Data Page Pointers).
Special Function Registers Overview
Name Physical
Address 8-Bit
Address Description Reset
Value
ADDRSEL1 FE18H0CHAddress Select Register 1 0000H
ADDRSEL2 FE1AH0DHAddress Select Register 2 0000H
ADDRSEL3 FE1CH0EHAddress Select Register 3 0000H
ADDRSEL4 FE1EH0FHAddress Select Register 4 0000H
BUSCON0 b FF0CH86HBus Configuration Register 0 0XX0H
BUSCON1 b FF14H8AHBus Configuration Register 1 0000H
BUSCON2 b FF16H8BHBus Configuration Register 2 0000H
BUSCON3 b FF18H8CHBus Configuration Register 3 0000H
BUSCON4 b FF1AH8DHBus Configuration Register 4 0000H
CAPREL FE4AH25HGPT2 Capture/Reload Register 0000H
CC8IC b FF88HC4HEX0IN Interrupt Control Register 0000H
CC9IC b FF8AHC5HEX1IN Interrupt Control Register 0000H
CC10IC b FF8CHC6HEX2IN Interrupt Control Register 0000H
CC11IC b FF8EHC7HEX3IN Interrupt Control Register 0000H
CC12IC b FF90HC8HEX4IN Interrupt Control Register 0000H
CC13IC b FF92HC9HEX5IN Interrupt Control Register 0000H
CC14IC b FF94HCAHEX6IN Interrupt Control Register 0000H
CC15IC b FF96HCBHEX7IN Interrupt Control Register 0000H
CC29IC b F184HEC2HSoftware Node Interrupt Control Register 0000H
CC30IC b F18CHEC6HSoftware Node Interrupt Control Register 0000H
CC31IC b F194HECAHSoftware Node Interrupt Control Register 0000H
CP FE10H08HCPU Context Pointer Register FC00H
C165
Semiconductor Group 23
CRIC b FF6AHB5HGPT2 CAPREL Interrupt Control Register 0000H
CSP FE08H04HCPU Code Segment Pointer Register (read only) 0000H
DP0L b F100HE80HP0L Direction Control Register 00H
DP0H b F102HE81HP0H Direction Control Register 00H
DP1L b F104HE82HP1L Direction Control Register 00H
DP1H b F106HE83HP1H Direction Control Register 00H
DP2 b FFC2HE1HPort 2 Direction Control Register 0000H
DP3 b FFC6HE3HPort 3 Direction Control Register 0000H
DP4 b FFCAHE5HPort 4 Direction Control Register 00H
DP6 b FFCEHE7HPort 6 Direction Control Register 00H
DPP0 FE00H00HCPU Data Page Pointer 0 Register (10 bits) 0000H
DPP1 FE02H01HCPU Data Page Pointer 1 Register (10 bits) 0001H
DPP2 FE04H02HCPU Data Page Pointer 2 Register (10 bits) 0002H
DPP3 FE06H03HCPU Data Page Pointer 3 Register (10 bits) 0003H
EXICON b F1C0HEE0HExternal Interrupt Control Register 0000H
MDC b FF0EH87HCPU Multiply Divide Control Register 0000H
MDH FE0CH06HCPU Multiply Divide Register – High Word 0000H
MDL FE0EH07HCPU Multiply Divide Register – Low Word 0000H
ODP2 b F1C2HEE1HPort 2 Open Drain Control Register 0000H
ODP3 b F1C6HEE3HPort 3 Open Drain Control Register 0000H
ODP6 b F1CEHEE7HPort 6 Open Drain Control Register 00H
ONES FF1EH8FHConstant Value 1’s Register (read only) FFFFH
P0L b FF00H80HPort 0 Low Register (Lower half of PORT0) 00H
P0H b FF02H81HPort 0 High Register (Upper half of PORT0) 00H
P1L b FF04H82HPort 1 Low Register (Lower half of PORT1) 00H
P1H b FF06H83HPort 1 High Register (Upper half of PORT1) 00H
P2 b FFC0HE0HPort 2 Register 0000H
P3 b FFC4HE2HPort 3 Register 0000H
P4 b FFC8HE4HPort 4 Register (8 bits) 00H
Special Function Registers Overview (cont’d)
Name Physical
Address 8-Bit
Address Description Reset
Value
C165
Semiconductor Group 24
P5 b FFA2HD1HPort 5 Register (read only) XXXXH
P6 b FFCCHE6HPort 6 Register (8 bits) 00H
PECC0 FEC0H60HPEC Channel 0 Control Register 0000H
PECC1 FEC2H61HPEC Channel 1 Control Register 0000H
PECC2 FEC4H62HPEC Channel 2 Control Register 0000H
PECC3 FEC6H63HPEC Channel 3 Control Register 0000H
PECC4 FEC8H64HPEC Channel 4 Control Register 0000H
PECC5 FECAH65HPEC Channel 5 Control Register 0000H
PECC6 FECCH66HPEC Channel 6 Control Register 0000H
PECC7 FECEH67HPEC Channel 7 Control Register 0000H
PSW b FF10H88HCPU Program Status Word 0000H
RP0H b F108HE84HSystem Startup Configuration Register (Rd. only) XXH
S0BG FEB4H5AHSerial Channel 0 Baud Rate Generator Reload
Register 0000H
S0CON b FFB0HD8HSerial Channel 0 Control Register 0000H
S0EIC b FF70HB8HSerial Channel 0 Error Interrupt Control Register 0000H
S0RBUF FEB2H59HSerial Channel 0 Receive Buffer Register
(read only) XXH
S0RIC b FF6EHB7HSerial Channel 0 Receive Interrupt Control
Register 0000H
S0TBIC b F19CHECEHSerial Channel 0 Transmit Buffer Interrupt Control
Register 0000H
S0TBUF FEB0H58HSerial Channel 0 Transmit Buffer Register
(write only) 00H
S0TIC b FF6CHB6HSerial Channel 0 Transmit Interrupt Control
Register 0000H
SP FE12H09HCPU System Stack Pointer Register FC00H
SSCBR F0B4HE5AHSSC Baudrate Register 0000H
SSCCON b FFB2HD9HSSC Control Register 0000H
SSCEIC b FF76HBBHSSC Error Interrupt Control Register 0000H
Special Function Registers Overview (cont’d)
Name Physical
Address 8-Bit
Address Description Reset
Value
C165
Semiconductor Group 25
SSCRB F0B2HE59HSSC Receive Buffer (read only) XXXXH
SSCRIC b FF74HBAHSSC Receive Interrupt Control Register 0000H
SSCTB F0B0HE58HSSC Transmit Buffer (write only) 0000H
SSCTIC b FF72HB9HSSC Transmit Interrupt Control Register 0000H
STKOV FE14H0AHCPU Stack Overflow Pointer Register FA00H
STKUN FE16H0BHCPU Stack Underflow Pointer Register FC00H
SYSCON b FF12H89HCPU System Configuration Register 0xx0H*)
T2 FE40H20HGPT1 Timer 2 Register 0000H
T2CON b FF40HA0HGPT1 Timer 2 Control Register 0000H
T2IC b FF60HB0HGPT1 Timer 2 Interrupt Control Register 0000H
T3 FE42H21HGPT1 Timer 3 Register 0000H
T3CON b FF42HA1HGPT1 Timer 3 Control Register 0000H
T3IC b FF62HB1HGPT1 Timer 3 Interrupt Control Register 0000H
T4 FE44H22HGPT1 Timer 4 Register 0000H
T4CON b FF44HA2HGPT1 Timer 4 Control Register 0000H
T4IC b FF64HB2HGPT1 Timer 4 Interrupt Control Register 0000H
T5 FE46H23HGPT2 Timer 5 Register 0000H
T5CON b FF46HA3HGPT2 Timer 5 Control Register 0000H
T5IC b FF66HB3HGPT2 Timer 5 Interrupt Control Register 0000H
T6 FE48H24HGPT2 Timer 6 Register 0000H
T6CON b FF48HA4HGPT2 Timer 6 Control Register 0000H
T6IC b FF68HB4HGPT2 Timer 6 Interrupt Control Register 0000H
TFR b FFACHD6HTrap Flag Register 0000H
WDT FEAEH57HWatchdog Timer Register (read only) 0000H
WDTCON FFAEHD7HWatchdog Timer Control Register 0000H
XP0IC b F186HEC3HX-Peripheral 0 Interrupt Control Register 0000H
XP1IC b F18EHEC7HX-Peripheral 1 Interrupt Control Register 0000H
XP2IC b F196HECBHX-Peripheral 2 Interrupt Control Register 0000H
Special Function Registers Overview (cont’d)
Name Physical
Address 8-Bit
Address Description Reset
Value
C165
Semiconductor Group 26
*) The system configuration is selected during reset.
Note: The Interrupt Control Registers XPnIC are prepared to control interrupt requests from
integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used
to generate software controlled interrupt requests by setting the respective XPnIR bit.
XP3IC b F19EHECFHX-Peripheral 3 Interrupt Control Register 0000H
ZEROS b FF1CH8EHConstant Value 0’s Register (read only) 0000H
Special Function Registers Overview (cont’d)
Name Physical
Address 8-Bit
Address Description Reset
Value
C165
Semiconductor Group 27
Absolute Maximum Ratings
Ambient temperature under bias (TA):
SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF .....................................0 to + 70 ˚C
SAF-C165-LM............................................................................................................ – 40 to + 85 ˚C
Storage temperature (TST) ....................................................................................... – 65 to + 150 ˚C
Voltage on VCC pins with respect to ground (VSS) ...................................................... –0.5 to + 6.5 V
Voltage on any pin with respect to ground (VSS).................................................– 0.5 to VCC + 0.5 V
Input current on any pin during overload condition.................................................. – 10 to + 10 mA
Absolute sum of all input currents during overload condition ..............................................|100 mA|
Power dissipation..................................................................................................................... 1.5 W
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the
voltage on pins with respect to ground (VSS) must not exceed the values defined by the
Absolute Maximum Ratings.
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C165 and partly its
demands on the system. To aid in interpreting the parameters right, when evaluating them for a
design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C165 will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to the C165.
DC Characteristics
VCC = 5 V ± 10 %; VSS = 0 V; fCPU = 20 MHz; Reset active
TA = 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF
TA = -40 to +85 ˚C for SAF-C165-LM
Parameter Symbol Limit Values Unit Test Condition
min. max.
Input low voltage VIL SR – 0.5 0.2 VCC
– 0.1 V–
Input high voltage
(all except RSTIN and XTAL1) VIH SR 0.2 VCC
+ 0.9 VCC + 0.5 V –
Input high voltage RSTIN VIH1 SR 0.6 VCC VCC + 0.5 V –
Input high voltage XTAL1 VIH2 SR 0.7 VCC VCC + 0.5 V –
C165
Semiconductor Group 28
Output low voltage
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)
VOL CC – 0.45 V IOL = 2.4 mA
Output low voltage
(all other outputs) VOL1 CC – 0.45 V IOL1 = 1.6 mA
Output high voltage
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)
VOH CC 0.9 VCC
2.4 –VI
OH = – 500 µA
IOH = – 2.4 mA
Output high voltage 1)
(all other outputs) VOH1 CC 0.9 VCC
2.4 –V
V
I
OH = – 250 µA
IOH = – 1.6 mA
Input leakage current (Port 5) IOZ1 CC – ±200 nA 0 V < VIN < VCC
Input leakage current (all other) IOZ2 CC – ±500 nA 0 V < VIN < VCC
RSTIN pullup resistor RRST CC 50 150 kΩ–
Read/Write inactive current 4) IRWH 2) – -40 µAVOUT = 2.4 V
Read/Write active current 4) IRWL 3) -500 – µAVOUT = VOLmax
ALE inactive current 4) IALEL 2) –40µAV
OUT = VOLmax
ALE active current 4) IALEH 3) 500 – µAVOUT = 2.4 V
Port 6 inactive current 4) IP6H 2) – -40 µAVOUT = 2.4 V
Port 6 active current 4) IP6L 3) -500 – µAVOUT = VOL1max
PORT0 configuration current 4) IP0H 2) – -10 µAVIN = VIHmin
IP0L 3) -100 – µAVIN = VILmax
XTAL1 input current IIL CC – ±20 µA 0 V < VIN < VCC
Pin capacitance 5)
(digital inputs/outputs) CIO CC – 10 pF f = 1 MHz
TA = 25 ˚C
Power supply current ICC – 10 +
4 * fCPU
mA RSTIN = VIL2
fCPU in [MHz] 6)
Idle mode supply current IID –2 +
1.2 * fCPU
mA RSTIN = VIH1
fCPU in [MHz] 6)
Power-down mode supply current IPD – 100 µAVCC = 5.5 V 7)
Parameter Symbol Limit Values Unit Test Condition
min. max.
C165
Semiconductor Group 29
Notes
1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
2) The maximum current may be drawn while the respective signal line remains inactive.
3) The minimum current must be drawn in order to drive the respective signal line active.
4) This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if
they are used for CS output and the open drain function is not enabled.
5) Not 100% tested, guaranteed by design characterization.
6) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.
These parameters are tested at VCCmax and 20 MHz CPU clock with all outputs disconnected and all inputs at
VIL or VIH.
7) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VCC – 0.1 V to VCC, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
Figure 8
Supply/Idle Current as a Function of Operating Frequency
C165
Semiconductor Group 30
Testing Waveforms
Figure 9
Input Output Waveforms
Figure 10
Float Waveforms
AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
For timing purposes a port pin is no longer floating when a 100 mV change from load
voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs
(IOH/IOL = 20 mA).
C165
Semiconductor Group 31
AC Characteristics
External Clock Drive XTAL1
VCC = 5 V ± 10 %; VSS = 0 V
TA = 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF
TA = -40 to +85 ˚C for SAF-C165-LM
Figure 11
External Clock Drive XTAL1
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1/2TCL = 1 to 20 MHz Unit
min. max. min. max.
Oscillator period TCL SR 25 25 25 500 ns
High time t1SR6–6–ns
Low time t2SR6–6–ns
Rise time t3SR–5–5ns
Fall time t4SR–5–5ns
Description Symbol Values
ALE Extension tATCL * <ALECTL>
Memory Cycle Time Waitstates tC2TCL * (15 - <MCTC>)
Memory Tristate Time tF2TCL * (1 - <MTTC>)
C165
Semiconductor Group 32
AC Characteristics (cont’d)
Multiplexed Bus
VCC = 5 V ± 10 %; VSS = 0 V
TA = 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF
TA = -40 to +85 ˚C for SAF-C165-LM
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1/2TCL = 1 to 20 MHz Unit
min. max. min. max.
ALE high time t5CC 15 + tA– TCL - 10 + tA–ns
Address setup to ALE t6CC 10 + tA– TCL - 15 + tA–ns
Address hold after ALE t7CC 15 + tA– TCL - 10 + tA–ns
ALE falling edge to RD,
WR (with RW-delay) t8CC 15 + tA– TCL - 10 + tA–ns
ALE falling edge to RD,
WR (no RW-delay) t9CC -10 + tA– -10 + tA–ns
Address float after RD,
WR (with RW-delay) t10 CC–5–5ns
Address float after RD,
WR (no RW-delay) t11 CC – 30 – TCL + 5 ns
RD, WR low time
(with RW-delay) t12 CC 40 + tC– 2TCL - 10
+ tC
–ns
RD, WR low time
(no RW-delay) t13 CC 65 + tC– 3TCL - 10
+ tC
–ns
RD to valid data in
(with RW-delay) t14 SR – 30 + tC– 2TCL - 20
+ tC
ns
RD to valid data in
(no RW-delay) t15 SR – 55 + tC– 3TCL - 20
+ tC
ns
ALE low to valid data in t16 SR – 55
+ tA + tC
– 3TCL - 20
+ tA + tC
ns
Address to valid data in t17 SR – 70
+ 2tA + tC
– 4TCL - 30
+ 2tA + tC
ns
Data hold after RD
rising edge t18 SR0–0–ns
Data float after RD t19 SR – 35 + tF– 2TCL - 15
+ tF
ns
Data valid to WR t22 SR 35 + tC– 2TCL - 15
+ tC
–ns
C165
Semiconductor Group 33
Data hold after WR t23 CC 35 + tF– 2TCL - 15
+ tF
–ns
ALE rising edge after RD,
WR t25 CC 35 + tF– 2TCL - 15
+ tF
–ns
Address hold after RD,
WR t27 CC 35 + tF– 2TCL - 15
+ tF
–ns
ALE falling edge to CS t38 CC -5 - tA10 - tA-5 - tA10 - tAns
CS low to Valid Data In t39 SR – 55
+ tC + 2tA
– 3TCL - 20
+ tC + 2tA
ns
CS hold after RD, WR t40 CC 60 + tF– 3TCL - 15
+ tF
–ns
ALE fall. edge to RdCS,
WrCS (with RW delay) t42 CC 20 + tA– TCL - 5
+ tA
–ns
ALE fall. edge to RdCS,
WrCS (no RW delay) t43 CC -5 + tA–-5
+ tA
–ns
Address float after RdCS,
WrCS (with RW delay) t44 CC–0–0ns
Address float after RdCS,
WrCS (no RW delay) t45 CC – 25 – TCL ns
RdCS to Valid Data In
(with RW delay) t46 SR – 25 + tC– 2TCL - 25
+ tC
ns
RdCS to Valid Data In
(no RW delay) t47 SR – 50 + tC– 3TCL - 25
+ tC
ns
RdCS, WrCS Low Time
(with RW delay) t48 CC 40 + tC– 2TCL - 10
+ tC
–ns
RdCS, WrCS Low Time
(no RW delay) t49 CC 65 + tC– 3TCL - 10
+ tC
–ns
Data valid to WrCS t50 CC 35 + tC– 2TCL - 15
+ tC
–ns
Data hold after RdCS t51 SR0–0–ns
Data float after RdCS t52 SR – 30 + tF– 2TCL - 20
+ tF
ns
Address hold after
RdCS, WrCS t54 CC 30 + tF– 2TCL - 20
+ tF
–ns
Data hold after WrCS t56 CC 30 + tF– 2TCL - 20
+ tF
–ns
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1/2TCL = 1 to 20 MHz Unit
min. max. min. max.
C165
Semiconductor Group 34
Figure 12-1
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE
Data In
Data OutAddress
Address
t
38
t
44
t
10
Address
ALE
CSx
A23-A16
(A15-A8)
BHE
BUS
Read Cycle
RD
RdCSx
BUS
Write Cycle
WR,
WRL, WRH
WrCSx
t
5
t
16
t
17
t
6
t
7
t
39
t
40
t
25
t
27
t
18
t
19
t
14
t
46
t
12
t
48
t
10
t
22
t
23
t
44
t
12
t
48
t
8
t
42
t
42
t
8
t
50
t
51
t
54
t
52
t
56
C165
Semiconductor Group 35
Figure 12-2
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE
Data OutAddress
Data InAddress
t
38
t
44
t
10
Address
ALE
CSx
A23-A16
(A15-A8)
BHE
BUS
Read Cycle
RD
RdCSx
BUS
Write Cycle
WR,
WRL, WRH
WrCSx
t
5
t
16
t
17
t
6
t
7
t
39
t
40
t
25
t
27
t
18
t
19
t
14
t
46
t
12
t
48
t
10
t
22
t
23
t
44
t
12
t
48
t
8
t
42
t
42
t
8
t
50
t
51
t
54
t
52
t
56
C165
Semiconductor Group 36
Figure 12-3
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE
Data OutAddress
Address Data In
t
38
Address
ALE
CSx
A23-A16
(A15-A8)
BHE
BUS
Read Cycle
RD
RdCSx
BUS
Write Cycle
WR,
WRL, WRH
WrCSx
t
5
t
16
t
17
t
6
t
7
t
39
t
40
t
25
t
27
t
18
t
19
t
15
t
47
t
13
t
49
t
22
t
23
t
13
t
49
t
9
t
43
t
43
t
9
t
11
t
45
t
11
t
45
t
50
t
51
t
54
t
52
t
56
C165
Semiconductor Group 37
Figure 12-4
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE
Data OutAddress
Data InAddress
t
38
Address
ALE
CSx
A23-A16
(A15-A8)
BHE
BUS
Read Cycle
RD
RdCSx
BUS
Write Cycle
WR,
WRL, WRH
WrCSx
t
5
t
16
t
17
t
6
t
7
t
39
t
40
t
25
t
27
t
18
t
19
t
15
t
47
t
13
t
49
t
22
t
23
t
13
t
49
t
9
t
43
t
43
t
9
t
11
t
45
t
11
t
45
t
50
t
51
t
54
t
52
t
56
C165
Semiconductor Group 38
AC Characteristics (cont’d)
Demultiplexed Bus
VCC = 5 V ± 10 %; VSS = 0 V
TA = 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF
TA = -40 to +85 ˚C for SAF-C165-LM
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1/2TCL = 1 to 20 MHz Unit
min. max. min. max.
ALE high time t5CC 15 + tA– TCL - 10 + tA–ns
Address setup to ALE t6CC 10 + tA– TCL - 15 + tA–ns
ALE falling edge to RD,
WR (with RW-delay) t8CC 15 + tA– TCL - 10
+ tA
–ns
ALE falling edge to RD,
WR (no RW-delay) t9CC -10 + tA– -10
+ tA
–ns
RD, WR low time
(with RW-delay) t12 CC 40 + tC– 2TCL - 10
+ tC
–ns
RD, WR low time
(no RW-delay) t13 CC 65 + tC– 3TCL - 10
+ tC
–ns
RD to valid data in
(with RW-delay) t14 SR – 30 + tC– 2TCL - 20
+ tC
ns
RD to valid data in
(no RW-delay) t15 SR – 55 + tC– 3TCL - 20
+ tC
ns
ALE low to valid data in t16 SR – 55
+ tA + tC
– 3TCL - 20
+ tA + tC
ns
Address to valid data in t17 SR – 70
+ 2tA + tC
– 4TCL - 30
+ 2tA + tC
ns
Data hold after RD
rising edge t18 SR0–0–ns
Data float after RD rising
edge (with RW-delay) t20 SR – 35 + tF– 2TCL - 15
+ tF
ns
Data float after RD rising
edge (no RW-delay) t21 SR – 15 + tF– TCL - 10
+ tF
ns
Data valid to WR t22 CC 35 + tC– 2TCL - 15
+ tC
–ns
Data hold after WR t24 CC 15 + tF– TCL - 10 + tF–ns
ALE rising edge after RD,
WR t26 CC -10 + tF– -10
+ tF
–ns
C165
Semiconductor Group 39
Address hold after RD,
WR t28 CC 0 + tF–0
+ tF
–ns
ALE falling edge to CS t38 CC -5 - tA10 - tA-5 - tA10 - tAns
CS low to Valid Data In t39 SR – 55
+ tC + 2tA
– 3TCL - 20
+ tC + 2tA
ns
CS hold after RD, WR t41 CC 10 + tF– TCL - 15
+ tF
–ns
ALE falling edge to RdCS,
WrCS (with RW-delay) t42 CC 20 + tA– TCL - 5
+ tA
–ns
ALE falling edge to RdCS,
WrCS (no RW-delay) t43 CC -5 + tA–-5
+ tA
–ns
RdCS to Valid Data In
(with RW-delay) t46 SR – 25 + tC– 2TCL - 25
+ tC
ns
RdCS to Valid Data In
(no RW-delay) t47 SR – 50 + tC– 3TCL - 25
+ tC
ns
RdCS, WrCS Low Time
(with RW-delay) t48 CC 40 + tC– 2TCL - 10
+ tC
–ns
RdCS, WrCS Low Time
(no RW-delay) t49 CC 65 + tC– 3TCL - 10
+ tC
–ns
Data valid to WrCS t50 CC 35 + tC– 2TCL - 15
+ tC
–ns
Data hold after RdCS t51 SR0–0–ns
Data float after RdCS
(with RW-delay) t53 SR – 30 + tF– 2TCL - 20
+ tF
ns
Data float after RdCS
(no RW-delay) t68 SR – 5 + tF– TCL - 20
+ tF
ns
Address hold after
RdCS, WrCS t55 CC -5 + tF–-5
+ tF
–ns
Data hold after WrCS t57 CC 10 + tF– TCL - 15
+ tF
–ns
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1/2TCL = 1 to 20 MHz Unit
min. max. min. max.
C165
Semiconductor Group 40
Figure 13-1
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE
Data Out
Data In
t
38
Address
ALE
CSx
A23-A16
A15-A0
BHE
BUS
(D15-D8)
D7-D0
Read Cycle
RD
RdCSx
Write Cycle
WrCSx
t
5
t
16
t
17
t
6
t
39
t
41
t
26
t
28
t
18
t
20
t
14
t
46
t
12
t
48
t
22
t
24
t
12
t
48
t
8
t
42
t
42
t
8
t
50
t
51
t
55
t
53
t
57
BUS
(D15-D8)
D7-D0
WR,
WRL, WRH
C165
Semiconductor Group 41
Figure 13-2
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE
Data Out
Data In
t
38
Address
ALE
CSx
A23-A16
A15-A0
BHE
Read Cycle
RD
RdCSx
Write Cycle
WrCSx
t
5
t
16
t
17
t
6
t
39
t
41
t
26
t
28
t
18
t
20
t
14
t
46
t
12
t
48
t
22
t
24
t
12
t
48
t
8
t
42
t
42
t
8
t
50
t
51
t
55
t
53
t
57
BUS
(D15-D8)
D7-D0
BUS
(D15-D8)
D7-D0
WR,
WRL, WRH
C165
Semiconductor Group 42
Figure 13-3
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE
Data Out
Data In
t
38
Address
ALE
CSx
A23-A16
A15-A0
BHE
Read Cycle
RD
RdCSx
Write Cycle
WrCSx
t
5
t
16
t
17
t
6
t
39
t
41
t
26
t
28
t
18
t
21
t
15
t
47
t
13
t
49
t
22
t
24
t
13
t
49
t
9
t
43
t
43
t
9
t
50
t
51
t
55
t
68
t
57
BUS
(D15-D8)
D7-D0
BUS
(D15-D8)
D7-D0
WR,
WRL, WRH
C165
Semiconductor Group 43
Figure 13-4
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE
Data Out
Data In
t
38
Address
ALE
CSx
A23-A16
A15-A0
BHE
Read Cycle
RD
RdCSx
Write Cycle
WR,
WRL, WRH
WrCSx
t
5
t
16
t
17
t
6
t
39
t
41
t
26
t
28
t
18
t
21
t
15
t
47
t
13
t
49
t
22
t
24
t
13
t
49
t
9
t
43
t
43
t
9
t
50
t
51
t
55
t
68
t
57
BUS
(D15-D8)
D7-D0
BUS
(D15-D8)
D7-D0
C165
Semiconductor Group 44
AC Characteristics (cont’d)
CLKOUT and READY
VCC = 5 V ± 10 %; VSS = 0 V
TA = 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF
TA = -40 to +85 ˚C for SAF-C165-LM
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
Notes
1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2tA refer to the next following bus cycle.
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1/2TCL = 1 to 20 MHz Unit
min. max. min. max.
CLKOUT cycle time t29 CC 50 50 2TCL 2TCL ns
CLKOUT high time t30 CC 20 – TCL – 5 – ns
CLKOUT low time t31 CC 15 – TCL – 10 – ns
CLKOUT rise time t32 CC–5–5ns
CLKOUT fall time t33 CC–5–5ns
CLKOUT rising edge to
ALE falling edge t34 CC 0 + tA10 + tA0 + tA10 + tAns
Synchronous READY
setup time to CLKOUT t35 SR 10 – 10 – ns
Synchronous READY
hold time after CLKOUT t36 SR0–0–ns
Asynchronous READY
low time t37 SR 65 – 2TCL + 15 – ns
Asynchronous READY
setup time 1) t58 SR 15 – 15 – ns
Asynchronous READY
hold time 1) t59 SR0–0–ns
Async. READY hold time
after RD, WR high
(Demultiplexed Bus) 2)
t60 SR 0 0
+ 2tA + tF
2)
0 TCL - 25
+ 2tA + tF
2)
ns
C165
Semiconductor Group 45
Figure 14
CLKOUT and READY
Notes
1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2) The leading edge of the respective command depends on RW-delay.
3) READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill
t
37 in order to be safely synchronized. This is guaranteed,
if READY is removed in response to the command (see Note 4)).
6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
7) The next external bus cycle may start here.
CLKOUT
ALE
t
30
t
34
Sync
READY
t
35
t
36
t
35
t
36
Async
READY
t
58
t
59
t
58
t
59
waitstate
READY MUX/Tristate 6)
t
32
t
33
t
29
Running cycle 1)
t
31
t
37
3) 3)
5)
Command
RD, WR
t
60 4)
see 6)
2)
7)
3) 3)
C165
Semiconductor Group 46
AC Characteristics (cont’d)
External Bus Arbitration
VCC = 5 V ± 10 %; VSS = 0 V
TA = 0 to +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF
TA = -40 to +85 ˚C for SAF-C165-LM
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1/2TCL = 1 to 20 MHz Unit
min. max. min. max.
HOLD input setup time
to CLKOUT t61 SR 20 – 20 – ns
CLKOUT to HLDA high
or BREQ low delay t62 CC – 20 – 20 ns
CLKOUT to HLDA low
or BREQ high delay t63 CC – 20 – 20 ns
CSx release t64 CC – 20 – 20 ns
CSx drive t65 CC -5 25 -5 25 ns
Other signals release t66 CC – 20 – 20 ns
Other signals drive t67 CC -5 25 -5 25 ns
C165
Semiconductor Group 47
Figure 15
External Bus Arbitration, Releasing the Bus
Notes
1) The C165 will complete the currently running bus cycle before granting bus access.
2) This is the first possibility for BREQ to get active.
3) The CS outputs will be resistive high (pullup) after
t
64.
CLKOUT
HOLD
t
61
HLDA
t
63
Other
Signals
t
66
1)
CSx
(On P6.x)
t
64
1)
2)
BREQ
t
62
3)
C165
Semiconductor Group 48
Figure 16
External Bus Arbitration, (Regaining the Bus)
Notes
1) This is the last chance for BREQ to trigger the indicated regain-sequence.
Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.
Please note that HOLD may also be deactivated without the C165 requesting the bus.
2) The next C165 driven bus cycle may start here.
CLKOUT
HOLD
HLDA
Other
Signals
t
62
CSx
(On P6.x)
t
67
t
62
1)
2)
t
65
t
61
BREQ
t
63
t
62
