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1. General description
The 74LV4052 is a low-voltage CMOS device and is pin and function comp atible with the
74HC/HCT4052.
The 74LV4052 is a d ual 4-channel an alog multiplexer/demultiplexer with a common select
logic. Each multiplexer has four independent inputs/outputs (nY0 to nY3) and a common
input/output (nZ). The common channel select logics include two digital select inputs (S0
and S1) and an active LOW enable input (E). With E LOW, one of the four switches is
selected (low impedance ON-state) by S0 and S1. With E HIGH, all switches are in the
high impedance OFF-state, independent of S0 and S1. VCC and GND are the supply
voltage p ins for the digita l control inputs ( S0, S1 and E). The VCC to GND ranges are 1.0 V
to 6.0 V. The analog inputs/outputs (nY0, to nY3, and nZ) can swing between VCC as a
positive limit and VEE as a negative limit. VCC - VEE may no t exceed 6.0 V. For operat i on
as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground).
2. Features and benefits
Optimized for low-volta ge applications: 1.0 V to 6.0 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Low ON resistance:
145 (typical) at VCC VEE = 2.0 V
90 (typical) at VCC VEE = 3.0 V
60 (typical) at VCC VEE = 4.5 V
Logic level translation:
To enable 3 V logic to communicate with 3 V anal og signals
Typical ‘break before make’ built in
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115 -A ex ce eds 20 0 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
74LV4052
Dual 4-channel analog multiplexer/demultiplexer
Rev. 5 — 17 March 2016 Product data sheet
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 2 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV4052D 40 C to +125 C SO16 plastic small outline package; 16 leads; body
width 3.9 mm SOT109-1
74LV4052DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm SOT338-1
74LV4052PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body wid t h 4.4 mm SOT403-1
Fig 1. Functional diag ram
(
DDD
6
6
/2*,&
/(9(/
&219(56,21
2)
'(&2'(5
*1'
9
((
=
<
<
<
<
<
<
<
<
9
&&
=
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 3 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
Fig 2. Logic symbol Fig 3. IEC logic symbol
DDK
=
6
6
(
=
<
<
<
<
<
<
<
<
DDK
*
0';
î
Fig 4. Schematic diagram (one switc h)
PQE
IURP
ORJLF
9
&&
9
((
9
((
9
&&
9
&&
9
((
Q<Q
Q=
9
&&
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 4 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration for SO16 and (T)SSOP16
/9
< 9&&
< <
=
<
< =
< <
(
<
9
((
6
*1' 6
DDD
Table 2. Pin description
Symbol Pin Description
2Y0 1 independent input or outp ut
2Y2 2 independent input or outp ut
2Z 3 common input or output
2Y3 4 independent input or outp ut
2Y1 5 independent input or outp ut
E6 enable input (active LOW)
VEE 7 negative supply voltage
GND 8 ground (0 V)
S1 9 select logic input
S0 10 select logic input
1Y3 11 independent input or outp ut
1Y0 12 independent input or outp ut
1Z 13 common input or output
1Y1 14 independent input or outp ut
1Y2 15 independent input or outp ut
VCC 16 positive supply voltage
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 5 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
[1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current flows out of terminals nYn. In this case, there is
no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.
[2] The minimum input voltage rating may be exceeded if the input current rating is observed.
[3] For SO16 package: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Function table[1]
Input Channel on
ES1 S0
L L L nY0 and nZ
L L H nY1 and nZ
L H L nY2 and nZ
L H H nY3 and nZ
HXXnone
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage [1] 0.5 +7.0 V
IIK input clamping current VI<0.5 V or VI> V CC + 0.5 V [2] -20 mA
ISK switch clamping current VSW < 0.5 V or VSW > VCC + 0.5 V [2] -20 mA
ISW switch current VSW >0.5 V or VSW < VCC + 0.5 V ;
source or sink current [2] -25 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[3]
SO16 package - 500 mW
SSOP16 and TSSOP16 package - 500 mW
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 6 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
8. Recommended operating conditions
[1] The static characteristics are guaranteed from VCC = 1.2 V to 6.0 V. However, LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
Table 5. Recommended operating con ditions[1]
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage see Figure 6 13.36V
VIinput voltage 0 - VCC V
VSW switch voltage 0 - VCC V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V
VCC = 2.0 V to 2.7 V - - 200 ns/V
VCC = 2.7 V to 6.0 V - - 100 ns/V
Fig 6. Guaranteed operating area as a function of the supply voltages
9&&9((9
DDN
9&&*1'
9
RSHUDWLQJDUHD
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 7 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
9. Static characteristics
[1] Typical values are measured at Tamb = 25 C.
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level input voltage VCC = 1.2 V 0.9 - - 0.9 - V
VCC = 2.0 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V 3.15 - - 3.15 - V
VCC = 6.0 V 4.20 - - 4.20 - V
VIL LOW-level input voltage VCC = 1.2 V - - 0.3 - 0.3 V
VCC = 2.0 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V - - 1.35 - 1.35 V
VCC = 6.0 V - - 1.80 - 1.80 V
IIinput leakage current VI=V
CC or GND
VCC = 3.6 V - - 1.0 - 1.0 A
VCC = 6.0 V - - 2.0 - 2.0 A
IS(OFF) OFF-state leakage current VI = VIH or VIL; see Figure 7
VCC = 3.6 V - - 1.0 - 1.0 A
VCC = 6.0 V - - 2.0 - 2.0 A
IS(ON) ON-state leakage current VI = VIH or VIL; see Figure 8
VCC = 3.6 V - - 1.0 - 1.0 A
VCC = 6.0 V - - 2.0 - 2.0 A
ICC supply current VI = VCC or GND; IO = 0 A
VCC = 3.6 V - - 20 - 40 A
VCC = 6.0 V - - 40 - 80 A
ICC additional supply current per input; VI = VCC 0.6 V;
VCC = 2.7 V to 3.6 V --500-850A
CIinput capacitance - 3.5 - - - pF
Csw switch capacitance independent pins nYn - 5 - - - pF
common pins nZ - 12 - - - pF
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 8 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
9.1 Test circuits
9.2 ON resistance
VI = VCC or VEE and VO = VEE or VCC.V
I = VCC or VEE and VO = open circuit.
Fig 7. Test circuit for measuring OFF-state leakage
current Fig 8. Test circuit for measuring ON-state leakage
current
DDD
,
6
VZLWFK
9
&&
Q<Q
6WR6
Q=
Q<Q
9,
,
6
92
(
*1' 9
((
9
,+
RU9
,/
9
&&
DDD
,
6
VZLWFK
9
&&
Q<Q
6WR6
Q=
Q<Q
92
9,
(
*1' 9
((
9
,+
RU9
,/
*1'
Table 7. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 and
Figure 10.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
RON(peak) ON resistance (peak) VI = 0 V to VCC VEE
VCC =1.2V; I
SW = 100 A[2] --- - -
VCC =2.0V; I
SW = 1000 A - 145 325 - 375
VCC =2.7V; I
SW = 1000 A - 90 200 - 235
VCC = 3.0 V to 3.6 V;
ISW = 1000 A- 80 180 - 210
VCC =4.5V; I
SW = 1000 A - 60 135 - 160
VCC =6.0V; I
SW = 1000 A - 55 125 - 145
RON ON resistance mismatch
between channels VI = 0 V to VCC VEE
VCC =1.2V; I
SW = 100 A[2] --- - -
VCC =2.0V; I
SW = 1000 A-5- - -
VCC =2.7V; I
SW = 1000 A-4- - -
VCC = 3.0 V to 3.6 V;
ISW = 1000 A-4- - -
VCC =4.5V; I
SW = 1000 A-3- - -
VCC =6.0V; I
SW = 1000 A-2- - -
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 9 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
[1] Typical values are measured at Tamb = 25 C.
[2] When supply voltages (VCC VEE) near 1.2 V the analog switch ON resistance becomes extremely non-linear. When using a supply of
1.2 V, only use these devices for transmitting digital signals.
RON(rail) ON resistance (rail) VI = GND
VCC =1.2V; I
SW = 100 A[2] - 225 - - -
VCC =2.0V; I
SW = 1000 A - 110 235 - 270
VCC =2.7V; I
SW = 1000 A - 70 145 - 165
VCC = 3.0 V to 3.6 V;
ISW = 1000 A- 60 130 - 150
VCC =4.5V; I
SW = 1000 A - 45 100 - 115
VCC =6.0V; I
SW = 1000 A - 40 85 - 100
RON(rail) ON resistance (rail) VI = VCC VEE
VCC =1.2V; I
SW = 100 A[2] - 250 - - -
VCC =2.0V; I
SW = 1000 A - 120 320 - 370
VCC =2.7V; I
SW = 1000 A - 75 195 - 225
VCC = 3.0 V to 3.6 V;
ISW = 1000 A- 70 175 - 205
VCC =4.5V; I
SW = 1000 A - 50 130 - 150
VCC =6.0V; I
SW = 1000 A - 45 120 - 135
Table 7. ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 and
Figure 10.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 10 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
9.3 On resistance waveform and test circuit
RON =V
SW /I
SW.
Fig 9. Test circuit for measuring RON
DDD
9
96:
VZLWFK
9
&&
Q<Q
6WR6
Q=
Q<Q
9,
,6:
(
*1' 9
((
9
,+
RU9
,/
*1'
Vi = 0 V to VCC VEE
Fig 10. Typical RON as a function of input voltage
DDN
9,9
521
ȍ
9&& 9
9&& 9
9&& 9
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 11 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
10. Dynamic characteristics
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+((CL Csw VCC2fo)where:
fi= input frequency in MHz, fo= output fr equency in MHz
CL= output load capacitance in pF
Csw = maximum switch capacitance in pF;
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs.
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 13.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay nYn to nZ, nZ to nYn; see Figure 11 [2]
VCC =1.2V - 25 - - - ns
VCC = 2.0 V - 9 17 - 20 ns
VCC = 2.7 V - 6 13 - 15 ns
VCC = 3.0 V to 3.6 V [3] -510- 12ns
VCC =4.5V - 4 9 - 10 ns
VCC =6.0V - 3 7 - 8 ns
ten enable time E, Sn to nYn, nZ; see Figure 12 [2]
VCC = 1.2 V - 190 - - - ns
VCC = 2.0 V - 65 121 - 146 ns
VCC = 2.7 V - 48 89 - 108 ns
VCC = 3.0 V to 3.6 V; CL=15pF [3] -30- - -ns
VCC = 3.0 V to 3.6 V [3] - 36 71 - 86 ns
VCC =4.5V - 32 60 - 73 ns
VCC =6.0V - 25 46 - 56 ns
tdis disable time E, Sn to nYn, nZ; see Figure 12 [2]
VCC = 1.2 V - 125 - - - ns
VCC =2.0V - 43 80 - 95 ns
VCC =2.7V - 33 59 - 71 ns
VCC = 3.0 V to 3.6 V; CL=15pF [3] -22- - -ns
VCC = 3.0 V to 3.6 V [3] - 26 48 - 57 ns
VCC =4.5V - 23 41 - 49 ns
VCC =6.0V - 18 32 - 38 ns
CPD power dissipation
capacitance CL=50pF; f
i = 1 MHz;
VI=GNDtoV
CC
[4] -57- - -pF
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 12 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
10.1 Waveforms
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11 . nYn, nZ to nZ, nYn propa ga t i on dela y s
DDN
Q<QRUQ=
LQSXW
Q=RUQ<Q
RXWSXW
W3/+ W3+/
9&&
9((
90
90
92
9((
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 12. Enable and disable times
DDN
W3/=
W3+=
VZLWFK2)) VZLWFK21VZLWFK21
Q<QRUQ=RXWSXW
/2:WR2))
2))WR/2:
Q<QRUQ=RXWSXW
+,*+WR2))
2))WR+,*+
6Q(LQSXW
92
92
9((
9((
9&&
966
90
W3=/
W3=+
Table 9. Measurement points
Supply voltage Input Output
VCC VMVM
< 2.7 V 0.5VCC 0.5VCC
2.7 V to 3.6 V 1.5 V 1.5 V
> 3.6 V 0.5VCC 0.5VCC
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 13 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Test circuit for measuring switching times
9090
W:
W:
9
9,
9,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9090
WI
WU
WU
WI
DDN
9(;7
9&&
9((
9,92
'87
&/
57
5/
5/
*
Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
< 2.7 V VCC 6 ns 50 pF 1 kopen VEE 2VCC
2.7 V to 3.6 V 2.7 V 6 ns 15 pF, 50 pF 1 kopen VEE 2VCC
> 3.6 V VCC 6 ns 50 pF 1 kopen VEE 2VCC
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 14 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
10.2 Additional dynamic parameters
[1] To obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 50 ), adjust fi voltage.
[2] To obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 600 ), adjust fi voltage.
10.2.1 Test circuits
Table 11. Additional dynamic characteristics
At recommended operating conditions; voltages are refe renced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specifie d ); tr = tf
6.0 ns; Tamb = 25
C.
Symbol Parameter Conditions Min Typ Max Unit
THD total harmonic
distortion fi= 1 kHz; CL= 50 pF; RL=10k; see Figure 18
VCC =3.0V; V
I=2.75V(p-p) - 0.8 - %
VCC =6.0V; V
I=5.5V(p-p) - 0.4 - %
fi= 10 kHz; CL= 50 pF; RL=10k; see Figure 18
VCC =3.0V; V
I=2.75V(p-p) - 2.4 - %
VCC =6.0V; V
I=5.5V(p-p) - 1.2 - %
f(3dB) 3 dB frequency
response CL= 50 pF; RL=50; see Figure 14 [1]
VCC = 3.0 V - 180 - MHz
VCC = 6.0 V - 200 - MHz
iso isolation (OFF-state) fi= 1 MHz; CL=50 pF; R
L=600; see Figure 16 [2]
VCC =3.0V - 50 - dB
VCC =6.0V - 50 - dB
Vct crosstalk voltage between digital inputs and switch;
fi= 1 MHz; CL=50 pF; R
L=600; see Figure 19
VCC =3.0V - 0.11 - V
VCC = 6.0 V - 0.12 - V
Xtalk crosst alk between switches; fi= 1 MHz; CL= 50 pF;
RL= 600 ;seeFigure 20 [2]
VCC =3.0V - 60 - dB
VCC =6.0V - 60 - dB
Fig 14. Test circuit for measuring frequency response
DDD
VZLWFK
9
&&
9
&&
Q<Q
6WR6
Q=
Q<Q
IL
5/
5/&/
) (
*1' 9((
9,+
RU9,/
*
1'
G%
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 15 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
VCC = 3.0 V; GND = 0 V; VEE = - 3.0 V; RL=50; RSOURCE =1k.
Fig 15. Typical frequency response
DDN
G%
IN+]
Fig 16. Test circuit for measuring isolation (OFF -state)
DDD
VZLWFK
9
&&
9
&&
Q<Q
6WR6
Q=
Q<Q
IL
5/
5/&/
)
(
*1' 9
((
9
,+
RU9
,/
9
&&
G%
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 16 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
VCC = 3.0 V; GND = 0 V; VEE = - 3.0 V; RL=50; RSOURCE =1k.
Fig 17. Typical isolation (OFF-state) as function of frequency
DDN
G%
IN+]
Fig 18. Test circuit for measuring total harmonic disto rtion
DDD
VZLWFK
9
&&
9
&&
Q<Q
6WR6
Q=
Q<Q
IL
5/
5/&/
)
(
*1' 9
((
9
,+
RU9
,/
*1'
'
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 17 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
a. Test circuit
b. Input and output pulse definitions
VI may be connected to Sn or E.
Fig 19. Test circuit for measuring crosstalk voltage between digital inputs and switch
DDD
VZLWFK
9
&&
9
&
&
9
&&
Q<Q
6WR6
Q=
Q<Q
5/
5/&/
92
(
*1' 9
((
9
,+
RU9
,/
5/
5/
9
*
DDM
RQ
929FW
RIIRII
ORJLF
LQSXW6Q(
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 18 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
a. Switch on channel.
b. Switch off channel.
Fig 20. Test circuit for measuring crosstalk between switches
DDD
9
&&
9
&&
Q<Q
6WR6
Q=
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74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 19 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
11. Package outline
Fig 21. Package outline SOT109-1 (SO16)
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74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 20 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
Fig 22. Package outline SOT338-1 (SSOP16)
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74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 21 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
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74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 22 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
12. Abbreviations
13. Revision history
Table 12. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LV40 52 v.5 20160317 Product data sheet - 74LV40 52 v.4
Modifications: •Type number 74LV4052N (SOT38-4) removed.
74LV40 52 v.4 20130701 Product data sheet - 74LV40 52 v.3
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate .
74LV4052 v.3 19980623 Product specification - 74LV4052 v.2
74LV4052 v.2 19970715 Product specification - -
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 23 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full informatio n see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
14.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe propert y or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whet her the NXP
Semiconductors product is suit able and fit for t he customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This docu ment contains the product specification.
74LV4052 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 17 March 2016 24 of 25
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LV4052
Dual 4-channel analog multiplexer/demultiplexer
© NXP Semiconductors N.V. 2016. All right s reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 March 2016
Document identifier: 74LV4052
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional de scription . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
9.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
9.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 8
9.3 On resistance waveform and test circuit. . . . . 10
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 11
10.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10.2 Additional dynamic parameters . . . . . . . . . . . 14
10.2.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
12 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15 Contact information. . . . . . . . . . . . . . . . . . . . . 24
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
