73M1
822/ 73M19 22 MicroDAA
Silicon DAA with Serial Interface
Simplifying System Integration™ DATA SH EE T
DS_1x22_001 April 2010
Rev. 1.6 © 2010 Teridian Semic onductor C or porat i on 1
DESCRIPTION
The 73M1822 MicroDAA is the world ’s firs t
single-package silicon Data A cc ess Arrangement
(DAA ) for data/fax modem an d voice applications.
It provides a ser ial M odem Analog Front End
(MAFE) i nter fac e to pop ular D SP/host proces sors to
implement a gl obally comp liant l ow-cost soft mod em
solution.
The 73M1822 MicroDAA is avail able as a
two-chip configuration (the 73M1922) that consists
of a 73M1902 Host-Si de Device and a 73M1912
Line-Side Device. The MicroDAA integrat es all
codec and DA A functions nec essary to achi eve
reli able PSTN c onnection worl dwide.
The MicroDAA uses a small pulse transformer ,
which can achieve mor e than 6 kV isolati on. Power
may be supp l ied along with data thr ough this bar r ier
interface to achieve superior per for mance in weak
loop curr ent conditions . Inherently immun e to RFI
and other forms of c ommon mode interference, the
patented Mi croDAA tec hnology achi eves g lobal DAA
com plianc e with un paralleled fle xibilit y, re liab ility,
and c ost str ucture and requires l ess than 2 square
inches of a single sided PC B.
The MicroDAA s upport s Caller ID Type I and II, ri ng
detection, tip/ring pol ar i ty reversal detection, hook
switc h contr ol , puls e di aling, r egulat ion of loop
current (DC mask), configurable line impedance
matc hing, line in use and parallel pick up d etection.
The MicroDAA integrates billin g tone filt ers, external
cl ock reference, audio moni tor output, and r equires
only a small number of low c ost and common l y
avai lable external componen ts.
The Mic r oDAA incorpor ates a c onfig urable sample
rate c i r cui t to suppor t soft mod em and
DSP-b ased implement ations of al l speeds up to
V .92 (56 Kbps ) . Sam pling r ates from 7.2 kHz to
16 k Hz can be easil y s upport ed.
APPLICATIONS
• V.92 modems
• S atelli te Set Top Boxes
• Fax/Multifunction Peripherals (MFP)
• P oint of Sale T er minal s
• V oic email Sys tems
• I ndustri al and medical telemetr y
FEATURES
• Meets FCC , ETSI ES 203 021 -2, JATE, NET4
and other PTT standards
• Configu r able PSTN t er minati on
• Up to 8 mA m inim um line curr ent operat i on
• 0 dBm Trans mit/Receive full scale
• THD –80 dB
• 16-bit codec up to 16 kHz sam p le rate
• Up to 56 Kbps (V.92) per formanc e
• Configu r able sample r ates (7.2 – 16 kHz)
• Reference clock ran ge of 9-40 MHz
• Crystal frequency range of 9-27 MHz
• MAF E I/F with Master, Sl ave and Dais y
Chaining
• Billing tone reject filter
• P olari ty reve r sal detection on -chip
• GPIO for use r-configurable I/O port
• Call Progr ess M onit or
• 3.3 V Operation
• I ndustri al temper atur e r ang e ( -40° to +85° C)
• 6 kV isolation (73M1922)
• 4-5 kV isolation (73M1822)
• 8 x8 mm 42-pin Q FN (73M1822)
• 20-pin TSSOP or 5x5 mm 32-pin QFN
(73M1922)
• RoHS compliant (6/6) l ead-free pack age
73M1822/73M1922 Data Sheet DS_1x22_001
2 Rev 1.6
Table of Contents
1 Introduction ...................................................................................................................................... 6
2 Pinout ................................................................................................................................................ 8
2.1 73M19 02 20-Pin TSSOP Pinout ............................................................................................... 8
2.2 73M19 12 20-Pin TSSOP Pinout ............................................................................................. 10
2.3 73M19 02 32-Pin QFN Pinout ................................................................................................. 11
2.4 73M19 12 32-Pin QFN Pinout ................................................................................................. 13
2.5 73M18 22 P inout..................................................................................................................... 15
2.6 Exp osed Bottom P ad on 73M1x66B QFN Pack ages .............................................................. 16
3 Electrical Characteristics and Specifications................................................................................ 17
3.1 Is ol ation Barr i er Characteri stics.............................................................................................. 17
3.2 Electrical Specifications ......................................................................................................... 17
3.2.1 Absolute M aximum Rati ngs .......................................................................................... 17
3.2.2 R ecommended Operati ng C ondit ions ........................................................................... 17
3.2.3 DC Characteristics........................................................................................................ 18
3.3 Serial Interface Ti ming Speci fication ...................................................................................... 19
3.4 Anal og Specifi cations............................................................................................................. 19
3.4.1 DC Sp ecifications ......................................................................................................... 19
3.4.2 C all Pr ogr ess Moni tor ................................................................................................... 20
3.5 73M1x22 Line -Side Electrical Specifications (73M1912) ......................................................... 22
3.6 Refer ence and Regul ati on ..................................................................................................... 22
3.7 AC Signal Levels ................................................................................................................... 22
3.8 DC Tran sfer Character istics ................................................................................................... 23
3.9 T ransmit Path ........................................................................................................................ 24
3.10 Receive Path ......................................................................................................................... 25
3.11 Trans mit Hybrid Cancellation ................................................................................................. 26
3.12 Receive Notch F i lter............................................................................................................... 26
3.13 Detectors ............................................................................................................................... 27
3.13.1 Over-V olt age Det ector................................................................................................. 27
3.13.2 Over-Current Detect or ................................................................................................. 27
3.13.3 Under-V olt age Det ector............................................................................................... 27
3.13.4 Over-L oad Det ector..................................................................................................... 27
4 Applications Information ................................................................................................................ 28
4.1 Exampl e Schematic of the 73M 1922 and 73 M1 822 ................................................................ 28
4.2 Bill of Mate rials ...................................................................................................................... 30
4.3 Over-Volt age an d EM I Protection ........................................................................................... 31
4.4 Is ol ation Barr i er Puls e Transformer ........................................................................................ 32
5 Control and Status Registers ......................................................................................................... 33
5.1 Line-Side Device Register Polling .......................................................................................... 36
6 Hardware Control Functi ons .......................................................................................................... 37
6.1 Device Re vision ..................................................................................................................... 37
6.2 Interr upt Control ..................................................................................................................... 37
6.3 Power M anag emen t ............................................................................................................... 38
6.4 Device C l ock M anag emen t .................................................................................................... 38
6.5 GPIO Registers...................................................................................................................... 39
6.6 Call Pr ogr ess M onitor ............................................................................................................ 40
7 Clock and Sample Rate Management ............................................................................................ 41
7.1 Clock Gener ation wit h HIC (73M1902) ................................................................................... 41
7.2 Crystal Osc illator.................................................................................................................... 41
7.3 PLL Pr esc al er ........................................................................................................................ 42
7.4 PLL Circuit ............................................................................................................................. 42
7.5 PLL System Timing Contr ol.................................................................................................... 45
8 MA F E S erial In t erf a ce ..................................................................................................................... 46
8.1 Data and Control Frame Formats ........................................................................................... 46
8.2 Data and Control Frame Timing ............................................................................................. 47
8.3 Serial Clock Operation ........................................................................................................... 48
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 3
8.4 Micr oD AA IN M aster/Sl ave Confi gurat ion ............................................................................... 49
8.5 73M1x22 Reset ..................................................................................................................... 49
8.6 73M1x22 in Daisy Chain Configuration................................................................................... 50
8.7 MAFE Confi gur ation Register s ............................................................................................... 51
8.8 Slave Regis ters...................................................................................................................... 51
9 Sig nal Pro cessing........................................................................................................................... 52
9.1 T ransmit Path Signal Processing ........................................................................................... 52
9.1.1 General Descript ion ...................................................................................................... 52
9.1.2 Total Tr ansmit Path R esponse...................................................................................... 52
9.1.3 73M 1x22 T r a ns mi t Spe c trum ........................................................................................ 53
9.2 Receive Path Si gnal Proces sing ............................................................................................ 53
9.2.1 Gener al Desc r i pti on ...................................................................................................... 53
9.2.2 Total Receive Path R esponse....................................................................................... 54
9.3 Sign al Control Func tions ........................................................................................................ 55
9.3.1 Transmit and Receive Level Contr ol ............................................................................. 55
10 Bar r i er Informa tion ......................................................................................................................... 57
10.1 Isol ati on Barrier...................................................................................................................... 57
10.2 B ar r i er Powered Opti ons ........................................................................................................ 57
10.2.1 Bar r i er Powered Oper ati on .......................................................................................... 57
10.2.2 Li ne P owered Operati ons ............................................................................................ 57
10.3 S ync hron iz ati on of the Bar r i er ................................................................................................ 57
10.4 Auxiliary A/D Con vert er .......................................................................................................... 58
10.5 Auto-Poll ................................................................................................................................ 58
10.6 B ar r i er Control Functions ....................................................................................................... 59
10.7 Line-S ide Device Operati ng M odes ........................................................................................ 60
10.8 Fail-Safe Operation of the Line-S ide Device ........................................................................... 60
11 Configura ble Direct Acc ess Arrangement (DAA) .......................................................................... 61
11.1 Pulse Dialing.......................................................................................................................... 61
11.2 DC Termination ...................................................................................................................... 61
11.2.1 Cu r r ent Limi t D etection................................................................................................ 63
11.3 A C Termination ...................................................................................................................... 63
11.4 Billing Tone Reject ion ............................................................................................................ 64
11.5 Trans-Hyb rid Canc ellation ...................................................................................................... 65
11.6 Dir ect Ac ces s Arr ang em ent Cont r ol Functions ....................................................................... 65
11.7 Inter nati onal Regi ster Setti ngs Tab l e for DC and AC Terminati ons ......................................... 69
12 Line Sensing and Status ................................................................................................................ 70
12.1 Auxiliary A/D Con vert er .......................................................................................................... 70
12.2 Ring Detect ion ....................................................................................................................... 70
12.3 Line In Use Detection (LIU) .................................................................................................... 70
12.4 Parallel P ic k Up (PPU) ........................................................................................................... 70
12.5 P ol ar ity Reversal Detect ion .................................................................................................... 70
12.6 Off-hook D etection of Caller ID Type II ................................................................................... 70
12.7 V ol tage an d Current D etection ............................................................................................... 71
12.8 Under Vol tage Det ection (UV D) ............................................................................................. 71
12.9 Over Vol tage Detection (OVD ) ............................................................................................... 71
12.10 A C Signal Over Load Detection.............................................................................................. 71
12.11 Over Current Detection (OID) ................................................................................................. 71
12.12 L ine Stat us Fu nctions Contr ol Functions ................................................................................ 72
13 Loopback and Testing Mod es ........................................................................................................ 75
14 Performance ................................................................................................................................... 77
14.1 DC VI Characteristics ............................................................................................................. 77
14.2 Receive ................................................................................................................................. 78
15 Package Layout .............................................................................................................................. 79
16 Ordering Information ...................................................................................................................... 81
17 Contac t Information ........................................................................................................................ 81
Revisio n Hist or y ..................................................................................................................................... 82
73M1822/73M1922 Data Sheet DS_1x22_001
4 Rev. 1.6
Figures
Figure 1: Simple 73M1x22 Reference Block Diagram .................................................................................. 6
Figure 2: 73M1902 20-Pin T SS OP Pi no u t ................................................................................................... 8
Figure 3: 73M1912 20-Pin T SS OP Pi no u t ................................................................................................. 10
Figure 4: 73M1902 32-Pin QFN Pi no ut ..................................................................................................... 11
Figure 5: 73M1912 32-Pin QFN Pi no ut ..................................................................................................... 13
Figure 6: 73M1822 42-Pin Pinout .............................................................................................................. 15
Fig ure 7: MAFE Timin g Diagram ............................................................................................................... 19
Fi gur e 8: Call Pr ogress Monitor F r equency Res ponse ............................................................................... 20
Fi gur e 9: Demo Board Circui t C onnecting AOU T t o a Speaker .................................................................. 20
Fi gur e 10: Recom mended Circuit for the 73M1922 ................................................................................... 28
Fi gur e 11: Recom mended Circuit for the 73M1822 ................................................................................... 29
Fi gur e 12: Suggested Over-voltage Pr otection and EM I Suppr ession Circui t ............................................. 31
Fi gur e 13: Clock Generati on B l ock Diagr am (as sumes 8 kHz sam ple rate) ............................................... 41
Fig ure 14: Crystal Os c illator with Con figurable Load Cu rrent ..................................................................... 41
Fi gur e 15: Prescaler Block Diagram .......................................................................................................... 42
Figure 16: PLL Block Diagram .................................................................................................................. 42
Fig ure 17: Serial Port Timin g Diagram ...................................................................................................... 46
Fi gur e 18: Dat a and Control Frames Timi ng Diagr am ................................................................................ 47
Fi gur e 19: Cont r ol Fr ame P osi ti on versus SPOS ....................................................................................... 48
Fi gur e 20: SC LK and FS with SCK M = 0 ................................................................................................... 48
Fi gur e 21: Exampl e Connections for Master and Slave Oper ati on ............................................................. 49
Fi gur e 22: M aster/Sl ave Seri al Timing Diagr am ........................................................................................ 49
Fi gur e 23: Daisy Chaining a Master and Two Sl aves ................................................................................ 50
Figure 24: Timi ng Diagr am with One M aster and Two Slaves .................................................................... 50
Fi gur e 25: Transmi t Path Overall Frequency Res pon se to Fs (8 kHz) ........................................................ 52
Figure 26: Pass-Band Respon se of t he Transmit Path .............................................................................. 52
Figure 27: Transmit Spectrum to 32 kHz ................................................................................................... 53
Figure 28: Overall Frequency Response of the R eceive Path .................................................................... 54
Figure 29: Pass-b and Respon se of t he Overall Receive Path .................................................................... 54
Fi gur e 30: Line-Side Device AC an d DC Circuits ....................................................................................... 60
Figure 31: DC-IV Char acteri stics ............................................................................................................... 61
Figure 32: Tip-Ring Voltage versus Cur r ent U sing Different D CI V Setti ngs ................................................ 62
Fi gur e 33: Vol tage versus Curr ent in the Seize Mode is the Same for A l l DC IV Settings ............................ 63
Fi gur e 34: M agnit ude Respon se of I PM F, ACZ=01 ( ETSI ES 203 021-2) .................................................. 64
Fi gur e 35: M agnit ude Respon se of Bil l ing Ton e Notch Fil ter ..................................................................... 64
Fi gur e 36: Loopback Modes Hi ghlighted ................................................................................................... 75
Fi gur e 37: Of f-Hook Tip and R i ng DC Ch ar acteri stics ................................................................................ 77
Fi gur e 38: ES 2 03 0 21-2 DC Mask with Cu rrent Limit En abled .................................................................. 77
Fi gur e 39: Australian Hold State Characteris ti cs ....................................................................................... 78
Figure 40: Return Loss ............................................................................................................................. 78
Fi gur e 4 1: 20-Pin TSSOP Pac kage D imensi ons ........................................................................................ 79
Fi gur e 42: 32-P i n QFN Pack age Dim ensi ons ............................................................................................ 79
Fi gur e 43: 42-P i n QFN Pack age Dim ensi ons ............................................................................................ 80
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 5
Tables
Table 1: 73M1902 20-P in TSSOP Pin Definitions ........................................................................................ 8
Table 2: 73M1912 20-P in TSSOP Pin Definitions ...................................................................................... 10
Table 3: 73M1902 32-Pin QFN Pin Def initions .......................................................................................... 11
Table 4: 73M1912 32-Pin QFN Pin Def initions .......................................................................................... 13
Table 5: 73M1822 Pin Definitions ............................................................................................................. 15
Tabl e 6: Isolati on B ar r i er Characteri stics at 8 kH z Sample Rate ................................................................ 17
Tabl e 7: Absol ute M aximum Device Rati ng s ............................................................................................. 17
Tabl e 8: Recommended Oper ati ng C ondit ions .......................................................................................... 17
Table 9 : DC Ch aracteristic s ...................................................................................................................... 18
Table 10: Serial D ata Por t Timing at 8 k Hz Sample Rate ........................................................................... 19
Tabl e 11: Reference Voltage Specifi cations .............................................................................................. 19
Tabl e 12: Component Val ues for the Speaker Driver ................................................................................. 20
Tabl e 13: Call Pr ogress Monit or Sp ecification ........................................................................................... 21
Table 14: Line-Sid e Absol ute M aximu m Rat ings ....................................................................................... 22
Tabl e 15: VBG Specifications ................................................................................................................... 22
Table 16: Maximum Transmit Levels ......................................................................................................... 22
Tabl e 17: M aximu m DC Transmit Levels ................................................................................................... 23
Tabl e 18: Transmi t Path ............................................................................................................................ 24
Tabl e 19: Receiv e Path ............................................................................................................................ 25
Table 2 0: Tran s mit Hybrid Cancellation Characteristics ............................................................................. 26
Tabl e 21: Receiv e N otch F ilter .................................................................................................................. 26
Tabl e 22: Over-V oltage Detector ............................................................................................................... 27
Tabl e 23: Over-Cur r ent D etector ............................................................................................................... 27
Tabl e 24: Under-Voltage Detector ............................................................................................................. 27
Tabl e 25: Over-Load Detector ................................................................................................................... 27
Tabl e 26: Reference Bil l of Materials for 73 M 1822/73M 1922 ..................................................................... 30
Tabl e 27: Reference Bil l of Materials for Figure 12 .................................................................................... 31
Tabl e 28: Compatib le Pul se Tran sformer S ources .................................................................................... 32
Tabl e 29: Transf or mer Characteris ti cs ...................................................................................................... 32
Tabl e 30: Control and S tatus Regi ster M ap ............................................................................................... 33
Tabl e 31: Alphabeti cal Bit M ap ................................................................................................................. 34
Tabl e 32: Clock Gener ati on Register Setti ngs for F xtal = 27 M H z ............................................................. 43
Tabl e 33: Clock Gener ati on Register Setti ngs for F xt al = 24.576 MHz ....................................................... 43
Tabl e 34: Clock Gener ati on Register Setti ngs for Fxtal = 9.216 M H z ......................................................... 43
Tabl e 35: Clock Gener ati on Register Setti ngs for F xt al = 24.000 MHz ....................................................... 44
Tabl e 36: Clock Gener ati on Register Setti ngs for Fxtal = 25.35 MHz ......................................................... 44
Table 37: PLL System Timing Controls ..................................................................................................... 45
Table 38: Behavior of SCLK under SCKM ................................................................................................. 48
Tabl e 39: Signal Control Func tions ........................................................................................................... 55
Tabl e 40: Transmi t Gai n Cont r ol ............................................................................................................... 55
Tabl e 41: Receiv e Gai n Control ................................................................................................................ 56
Tabl e 42: Bar r ier C ontr ol Functions ........................................................................................................... 59
Table 43: Trans-Hybrid Cancellation ......................................................................................................... 65
Tabl e 44: DAA Control Functions .............................................................................................................. 65
Tabl e 45: Recommended Regist er Setti ngs for Internati onal Comp atib ili ty ................................................ 69
Tabl e 46: Line Sensing Cont r ol Fun ctions ................................................................................................. 72
Tabl e 47: Loop back M odes ....................................................................................................................... 75
Tabl e 48: Loop back Controls .................................................................................................................... 76
Table 49: Order Numbers and Pac kagi ng Mark s ....................................................................................... 81
73M1822/73M1922 Data Sheet DS_1x22_001
6 Rev. 1.6
1 Introduction
The 73M19 22 MicroDAA is a two-device chip set that consists of a 73M1 902 Hos t-Side Device and a
73M19 12 Line-S ide Device that c an be u sed in any voice-band PSTN tel ephone interfac e application
requiring a CODEC. The 73M1822 is a single-pack age M ic r oD AA with the same int er faces . Each connect s
dir ectly between a host proces sor and the tel ephon e network with a l ow-cos t pu l se transformer to pr ovide
the re qui r e d hi g h-voltage isol ation. A few low-c ost c omp onen ts c om plet e the i nter fac e to the network . Th e
pulse transformer t r ansmits encoded digital data r ather than anal og sign al s as with other t r ansformer
des i gn s. Dat a is transmi tted and recei ved without the usual degrad ation from common mode nois e and
magneti c c oup l ing typ i cal of other capacitive and voice-b and tr ansformer t echni ques. Th e data stream
pas sed between the Hos t-Side and Line -Side Devices includ es the media stream dat a, control , status and
cl ocking informati on.
The data sheet desc r i bes both the 73M1 922 an d 73M 1822 , wh i ch will be col l ectively refer r ed to as the
73M1x22 in this document.
The H ost-S i de Devic e uses a serial data port for transferring tr ansmi t and recei ve data, s tatus and control
information to a host . This inter face is comp ati ble with m ost DSP and high-p er formanc e pr ocess or
sync hronous seri al COD EC inter fac es.
A ll med ia s tream data and c ontr ol information between the Host-Side Device and Line-S ide Device of t he
73M1822 and 73M1922 are transferred across the pulse trans former. Cl ocking i nformation used by t he
Line-S ide Device is embedd ed i n the b it stream received from t he Host-Side Device and reconstructed by
the Line-S i de Device of the 73M1822 or 73M19 22.
O n start up, the H ost-S i de Device pr ovi des pow er to the Line-S ide Device through the tr ansformer. After
going off-hook, the Line-S i de Device is capable of being powered from t he PSTN networ k. Th e only
physi cal connections betwe en the devices are the p r i mary si de of the puls e transformer t hat is connected to
t he Host-Side Device and the secondary s i de to the Line-S ide Device.
Figure 1 s hows a r efer ence bl ock diagram of the 73M1922 c onn ected by a p ulse tran sformer an d examp l e
external line interface circuitry shown for clarification.
PRM
Modem
Side
Barrier
Interface
(MSBI)
MAFE
Interface
Transmit
Interpolation
Filter (TIF)
Receive
Decimation
Filter (RDF)
TxData
RxData
PRP
TxD
RxD
CTL
STA
Host-Side Device
TBS
Digital
Sigma
Delta
Modulator
(DSDM)
SCM
Line
Side
Barrier
Interface
(LSBI) Receive
Analog
Front End
(RxAFE)
SinC3
Filter
On-Chip
Line
Interface
Circuit
Transmit
Analog
Front End
(TxAFE)
RBS
Tip
Ring
SCP
Aux A/D
STA
TxA
RxA
Off-Chip
Line
Interface
Circuit
Ring
Buffer
Line-Side Device
73M1902 73M1912
Figure 1: Simple 73M1x22 Reference Block Diagram
The H ost-Side Device (73M1902) consists of:
1. Modem Analog F r ont End ( M AFE) Interface B loc k
2. Transmit Inter polation Fil ter ( TI F)
3. Rec eive D eci mation F i lt er ( RDF)
4. Modem-S i de Barrier Int erface Circuit (MS BI)
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 7
The Line-Side Device (7 3M1912 / 73M1822) consi sts of:
1. Digit al S igma Delta Modulat or (DSDM)
2. Transmit Analog Front End (TxAFE)
3. Rec eive Anal og Front End (RxA FE) i ncluding Si gma Delta M odulat or ( ASDM)
4. Sinc^3 Filt er (S i nc3)
5. On-chip Line Interface Circuit (ONLIC)
6. Line-S i de B ar r i er Inter face Ci r cui t ( LSBI)
The transmit data (TxData) is interpol ated u p withi n TI F (Trans mit Interpol ation F i lter) from the sampling
frequency (Fs) to twi ce the sampling frequency res ult ing in TxD.
Cont rol in formation (CTL) is time-di vision multi plexed with T xD, serialized withi n MS BI, and sent acr oss t he
barrier to 73M1912 LIC (Line Interface Circuitry). This is then received and processed within LSBI and
separat ed into TxD and CTL. TxD is d igit ally sigma-d el ta modulated to form a ser i alized Transmit Bi t
S tr eam (TBS) . The TBS i s D /A c onverted for fi nal transmissi on to the l ine. CTL is us ed to control vari ous
features of the Line-Side Device.
O n the recei ve s ide, the received analog s i gn al from t he line is sigma-delt a modulated to form a ser i alized
Rec eive Bit Str eam (RBS) . R BS i s dec imated down t o twic e the sampling frequ ency as RxD an d
time-d ivisi on multip lexed with s tatus Informati on (S TA ) from t he Auxiliary A/D r egarding line condit ion in
LSBI block and trans mitted to the Host-Side D evice. The M SBI process es thi s data and separates i t i nto
RxD and STA . Rxd is further decimat ed to down t o Fs and sent to the hos t through the MA FE interface.
S TA is s ent to the hos t thr ough the M AFE inter fac e using a di fferent ti me sl ot.
73M1822/73M1922 Data Sheet DS_1x22_001
8 Rev. 1.6
2 Pinout
The 73M1922 consists of two devices, the 73M1902 and the 73M1912, which are available as 20-pin
TSSOP packages and as 32-pin QF N pac kage sets .
2.1 73M190 2 20-Pin TSSOP Pinout
Figure 2 shows the 73M1902 20-pin T SS O P pinou t.
73M1902
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
FSD
FS
VND
VPD/VPPLL
OSCIN/MCLK
OSCOUT
VNPLL/VNA
AOUT
TYPE
VPA/VPM VNMVNT
SDOUT
SCLK
INT/RGDT
VND
VPT/VPD
M/S
PRM
PRP
SDIN
Figure 2: 73M1902 20-Pin TSSOP Pinout
Tabl e 1 describes the pin functions for the device. Dec oupling capacitor s on the power supplies should be
included for each pair of supply pins.
Table 1: 73M1902 20-Pin TSSOP Pin Definitions
Pin
Number Pin
Name Type Description
1 FSD O Frame sync hronization ( FS) delayed
2
FS O
Frame sync hronization
3 VND GND Negative digital ground
4 VPD/VPPLL PWR P ositive digit al/ PL L sup ply
5 OSCIN/MCLK I Cryst al oscillator circuit inpu t p in.
I nput from an external clock sour ce. Cryst al frequency range
is 9 MHz – 27 MHz.
6
OSCOUT
O
Cryst al oscillator outp ut pin. (N.C. with exter nal os cillator)
7
VNA/VNPLL
GND
Negative analog/PLL ground
8 AOUT O Call pr ogr ess audi o output
9 TYPE I Type of frame syn c. 0 = l ate ( mode0), 1 = ear ly (mode1) .
Weak-pulled high – default = ear ly.
10
VPA/VPM
PWR
P osi ti ve analog suppl y
11 VNM/VNT GND Negative barr ier i nter face sup ply / negati ve transformer sup ply
12 M/S I Mas ter/slave con tr ol, r eset at a transiti on.
13 PRM I/O Pul se transformer primary minus
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 9
14 PRP I/O Pulse transformer primary pl us
15 VPD PWR P ositive digital supply, posit i ve transformer sup ply
16 INT/RGDT O Ring detection indicator or other Inter r up ts
Ope n dr a i n
17 SCLK O Serial interface cloc k. With conti nuous SCLK selected,
Frequency = 256∗Fs (=1.8432MHz for Fs=7.2kHz, 2.048MH z
for Fs=8kHz)
18 VND GND Negativ e dig ital ground
19 SDIN I S er ial data input (or output from the contr ol ler to 73M 1902)
20 SDOUT O Serial data outpu t (or i np ut to the c ontr ol ler from 73M1902)
73M1822/73M1922 Data Sheet DS_1x22_001
10 Rev. 1.6
2.2 73M191 2 20-Pin TSSOP Pinout
Figure 3 shows the 73M1912 20-pin T SS O P pi no u t.
73M1912
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DCI
RGN
RGP
OFH
VND/VNX
SCP
MID
VPX
SRE
SRB VBG
DCS
DCD
TXM
RXM
RXP
ACS
VNX/VNS
VPD/VPS
DCG
Figure 3: 73M1912 20-Pin TSSOP Pinout
Tabl e 2 describes the pin functions for the device. Decoupling capacitors on the power supplies should be
included for each pair of supply pins.
Table 2: 73M1912 20-Pin TSSOP Pin Definitions
Pin
Number Pin Na me Type Description
1 DCI I DC loop input
2 RGN I Ring detect negati ve voltag e input
3 RGP I Ring detect pos it ive vol tage input
4 OFH O Off-h ook c ontr ol
5 VND/VNX GND Digit al/ analog negati ve s upp l y volt age
6 SCP I/O Pos i ti ve s i de o f the sec ondary puls e transformer win ding
7 MID I/O C ha r ge pum p mi d po i nt
8 VPX PWR S upply from the b ar r i er , connect to VPD
9
SRE
I
V oltage regulat or sense
10 SRB O V oltage regulat or drive
11 VBG O VBG bypass, connect to 0.1 μF capacitor to VNS
12 ACS I AC curren t sense
13 VNX/VNS GND Di gital/anal og n egative supply voltage
14 VPD/VPS PWR Dig ital/analog positive supp ly voltage
15 RXP I Receive plus – signal input
16 RXM I Rec eive minus – si gnal input
17 TXM O T ra ns mit minus – signal output
18
DCD
O
DC loop drive
19 DCS I DC loop c urrent s ense
20 DCG O DC loop drive
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 11
2.3 73M190 2 32-Pin QFN Pinout
Figure 4 shows the 73M1902 32-pin QF N pino ut.
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
VND
GPIO5
GPIO4
VPD/VPPLL
OSCIN/MCLK
OSCOUT
VNPLL
VNA
VND
SCLK
INT/RGDT
LEV
VPT/VPD
RST
PRP
PRM
VBG
AOUT
TOUT
TYPE
VPA/VPM
SCLKM
VNM/VNT
M/S
73M1902
SDIN
GPIO6
VND
FS
FSD
VPD
SDOUT
GPIO7
Figure 4: 73M1902 32-Pin QFN Pinout
Table 3 describes the pin funct i ons for the device. Decoupl i ng capacitor s on the power supplies should be
included for each pair of supply pins.
Table 3: 73M1902 32-Pin QFN Pin Definitions
Pin
Number Pin Na me Type Description
1 VND GND Negative digital ground
2 GPIO5 I/O Configurable digital input/output pins
3 GPIO4 I/O Configurable digital input/output pins
4
VPD/VPPLL
PWR
Posit ive dig ital/P LL supply
5 OSCIN/MCLK I Cryst al oscillator circuit inpu t p in.
I nput from an external clock sour ce.
Crystal frequency range supported is 9 MHz – 27 MHz.
6
OSCOUT
O
Cryst al oscillator outp ut pin. (N.C. with external osci llat or)
7 VNA/VNPLL GND Negative analog/PLL ground
8 VNA/VNPLL GND Negative analog/PLL ground
9 VBG O Ba nd ga p voltage r eference mon i tor
10 AOUT O Call progr ess audi o output
11 TOUT O Dig ital test output
12 TYPE I Type of frame syn c. 0 = l ate ( mode0), 1 = ear ly (mode1) .
Weak-pulled high – default = ear ly.
13 VPA/VPM PWR P osi ti ve analog suppl y
73M1822/73M1922 Data Sheet DS_1x22_001
12 Rev. 1.6
Pin
Number Pin Na me Type Description
14 SCKM I Controls the SCLK behavior after FS. Weak-p ul l e d hi gh –
default = continuous SCLK
15 VNM/VNT GND Negati ve barr ier i nter face/ tr ansformer supp l y
16 M/S I Mas ter/slave con tr ol, r eset at a transiti on
17 PRM I/O Pul se transformer primary minus
18 PRP I/O Pulse transformer primary pl us
19 RST I Fac tory tes t mode – leav e open
20 VPD PWR Positive digital supply, positive transformer supply
21 LEV O Test output ( C M OS l evel)
22 INT/RGDT O Ring detect ion indicator or other I nter r up ts.
Ope n dr a i n
23 SCLK O Seri al inter face c l ock. With c ontinuous SCLK selected,
Frequency = 256∗Fs (=1.8432MHz for Fs=7.2kH z , 2.0 4 8M H z
for Fs=8kHz)
24 VND GND Negative digital ground
25 SDIN I Serial data i np ut (or ou tput from the contr ol ler to 73M 1902)
26 SDOUT O Seri al data output (or input to the control l er from 73M1902 )
27 VPD PWR P ositive digital supply, posit ive transformer supply
28 FSD O F S delayed
29 FS O Frame syn chronization
30 VND GND Negative digital ground
31 GPIO7 I/O Configurable digital input/output pins
32 GPIO6 I/O Configurable digital input/output pins
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 13
2.4 73M191 2 32-Pin QFN Pinout
Figure 5 shows the 73M1912 32-pin QF N pino ut.
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
CKO
OFH
CKI
VND/VNX
SCP
MID
SCM
VPX
RST
DCD
TST
TXM
SACIN
RXM
RXP
VPS
RCT
BYP
SRE
SRB
VNS
VBG
ACS
VNS
73M1912
DCS
GPO
GPI
VNS
RGP
RGN
DCI
DCG
Figure 5: 73M1912 32-Pin QFN Pinout
Table 4 describes the pin functions for the device. Dec oupling capacitor s on the power supp l ies should be
included for each pair of supply pins.
Table 4: 73M1912 32-Pin QFN Pin Definitions
Pin
Number
Pin
Name Type Description
1 CKO O Test point for recovered c loc k
2 OFH O Off-h ook c ontr ol
3
CKI
I
Test input for clock
4 VND/VNX GND Digit al/ analog negati ve s upp l y volt age
5 SCP I/O Pos i ti ve s i de o f the sec ondary puls e transformer win ding
6 MID I/O C ha r ge pum p mi d po i nt
7 SCM I/O Neg ati ve s ide of t he sec ond ar y pul se transformer winding
8 VPX PWR S upply from the b ar r i er side, connect to VPD
9 RCT I E xternal r ectification – di sabl es inter nal rect ifier when low, leave
open
10 BYP I Factory t est mode – leave open
11 SRE I V oltage regulat or sense
12 SRB O V oltage regulat or drive
13 VNS GND Analog/digital negati ve s upply voltage
14 VBG O VBG bypass, connect to 0.1μF capacitor to VPS
15 ACS I AC curren t sense
16 VNS GND Analog/digital negati ve s upply voltage
73M1822/73M1922 Data Sheet DS_1x22_001
14 Rev. 1.6
Pin
Number Pin
Name Type Description
17 VPS PWR Analog/digital positive supply voltage
18 RXP I Receive plus – sig nal input
19 RXM I Rec eive minus – si gnal input
20 SACIN I Caller ID mode AC i m ped ance connec ti on
21 TXM O T ra ns mit minus – transhybri d cancell ati on ou tput
22 TST I Factory tes t mod e – leave open
23 RST I Fac tory tes t mode – leav e open
24 DCD O DC loop drive
25 DCS I DC loop c urrent s ense
26 DCG O DC loop drive
27
DCI
I
DC loop input
28 RGN I Ri ng detect negati ve voltage input
29 RGP I Ring detect positive voltage input
30
VNS
GND
A nalog/dig i tal neg ati ve s upply voltage
31 GPI I General purpose input (test pin)
32 GPO O Gener al pu r pose output (test pin)
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 15
2.5 73M182 2 P inout
Figure 6 shows the 73M1822 42-pin pi no ut.
73M1822
PRM
PRP
VPD/VPT
INT/RGDT
SCLK
SDIN
SDOUT
FSD
FS
VND
GPIO
VND
VPD/VPPLL
OSCIN/MCLK
OSCOUT
VNA
VNA/VNPLL
AOUT
VPA/VPM
VNA
M/S
SRE
SRB
VBG
ACS
VNS
VPS
RXP
RXM
TXM
DCD
DCS
DCG
DCI
RGN
RGP
OFH
M20BP
SCP
MID
VPX
VND/VNX
1
2
3
4
5
6
7
8
9
10
20
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
29
30
31
32
33
35
34
36
37
38
39
40
41
42
Figure 6: 73M1822 42-Pin Pinout
Table 5 describes the pin functions for the device. Decoupling capacitors on the power supplies should be
included for each pair of supply pins.
Table 5: 73M1822 Pi n Defini t ion s
Pin
Number Pin Na me Type Description
1 PRP I/O Pulse transformer pri mary plus
2 PRM I/O Pul se transformer p r imar y mi nus
3 VPD/VPT PWR Positi ve digit al/t r ansformer supp l y
4 INT/RGDT O Ring detect ion indicator or other Inter r upts
Ope n dr a i n
5 SCLK O S er ial i nter face c l ock . With c onti nuou s SCLK sel ected,
Frequency = 256∗Fs (=1.8432 MHz for Fs=7.2 kHz, 2.048 MHz
for Fs=8 kHz)
6 SDIN I S er ial data input (or output from the contr ol ler to the 73M1 822 )
7 SDOUT O S er ial data output (or input to the control ler from the 7 3M1822)
8 FSD O F S delayed
9 FS O F r ame sync hronization
10 VND GND Negative digital ground
11 GPIO I/O Configurable digital input/output pins
12 VND GND Negative digital ground
13 VPD/VPPLL PWR P ositive digit al supp ly
73M1822/73M1922 Data Sheet DS_1x22_001
16 Rev. 1.6
Pin
Number Pin Na me Type Description
14 OSCIN/MCLK I Cryst al oscillator circui t inp ut pin.
I nput from an external clock sour ce. Cryst al frequency range
supported is 9 MHz – 27 M H z.
15 OSCOUT O Crystal os cillator output pin . ( N. C. with exter nal os cil lator)
16 VNA/VNPLL GND N egative PL L gr ound
17 VNA GND Negative anal og ground
18 AOUT O Call progr ess audi o output
19 VPA/VPM PWR P osi ti ve analog suppl y
20 VNM/VNT GND Negative tr ansformer supp l y
21 M/S I Mas ter or slave s election / reset - active during transition
22 SRE I S /Sh r egu l ator sense
23 SRB O S/Sh regulator drive
24 VBG O VBG bypas s, c onnect to 0.1uF capacitor to VPS
25 ACS I AC curren t sense
26 VNS GND LIC analog/digital negative ground
27 VPS PWR L IC analog/dig i tal positive suppl y v ol tage
28 RXP I Rec eive p l us -si gn al input
29 RXM I Rec eive minus - signal input
30 TXM O T ra ns mit minus - signal output
31 DCD O DCD for integrated Darlin gt on
32
DCS
I
DC loop c urrent s ense
33 DCG O DC loop drive
34 DCI I DC loop input
35 RGM I Ring minus voltage input
36 RGP I Ring plus voltage input
37 OFH O Off-ho ok control
38 M20BP I S ubstrate connection. C onnect to VNX.
39 VND/VNX GND LIC digital/analog negative ground
40 SCP I/O Pos i ti ve s i de o f the sec ondary puls e transformer win ding
41 MID I/O Charge pump -nor mally left open
42
VPX
PWR
LIC supply from the barrier side
2.6 E xpo s ed Bo ttom Pad o n 73M1x 66 B QF N Pa ck ages
The 73M18 22 and 73M19 22 QFN pack ages have exposed pads on the undersi de that are intended
for devic e man ufact uring purpos es. These exp osed pads are not intended for thermal relief (heat
dissipation) and shoul d not be soldered t o the PCB . Sol dering of the expos ed pad could als o
compromise electr ical isolation/insul ati on requir ement s for pr oper voltage is ol ation. Avoid any P CB
t r aces or throu gh -hol e vias on the PC B beneath the expos ed p ad ar ea.
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 17
3 Electrical Characteristics and Specifications
3.1 Isolation Barrier Characteristics
Table 6 prov ides the characteri stics of the 7 3M1x22 Isolation Barr i er .
Table 6: Isolation Barrier Characteristics at 8 kHz Sample Rate
Parameter
Rating
B arrier freq u en cy 768 kHz
Data transfer rate across the b ar r i er 1.536 Mbps
3.2 Ele ctr ic al Sp ecif ic ati ons
Thi s s ection p r ovides the absolute maximum ratings , the r ecommend ed op er ati ng condi tions and the D C
characteristics.
3.2.1 Absolute Maxim u m Ratings
Table 7 lists the maximum operat ing conditi ons for the 73M 1x22. Perman ent device damage may occ ur if
abs ol ute maximum r ati ngs are exceed ed. Exposure to the extr emes of the absolute m aximu m r ati ng for
extended period s may affect devi ce reliabi l ity.
Table 7: Absolute Maxim um Devic e Ratings
Parameter Min Max Unit
S upp l y volt age -0.5 4.0 V
Pin input voltage (except OSCIN)
-0.5
6.0
V
P in input voltage ( OSC IN) -0.5 to VDD 0.5 V
3.2.2 Recommended Operating Conditions
Function oper ation s hou l d be restr i cted to the recommen ded op er ati ng condi ti ons sp eci fied in Table 8.
Table 8: Recommended Ope r ating Conditions
Parameter Min Max Unit
S upp l y volt age (VDD ) with respect to VSS 3. 0 V 3.6 V
Operating temperature 0 85 °C
73M1822/73M1922 Data Sheet DS_1x22_001
18 Rev. 1.6
3.2.3 DC Characteristics
Table 9 lists the 73M 1x22 DC ch ar acteri stics .
Table 9: DC Characteristics
Parameter
Condition
Min
Nom
Max
Unit
Input low voltage VIL
–
-0.5
–
0.2 ∗ VDD V
Input high voltage
(except OSCIN) VIH1
–
0.7 VDD
–
5.5 V
I nput H i gh V ol tage
OSCIN VIH2
–
0.7 VDD
–
VDD + 0.5 V
O utput l ow vol tage
(except OXCOUT, FS,
SCLK, SDOUT)
VOL IOL= 4 mA
–
–
0.45 V
O utput l ow vol tage
OSCOUT VOLOSC IOL=3 mA
–
–
0.7 V
O utput Low V ol tage
FS, SCLK, SDOUT VOL I OL = 1mA
–
–
0.45 V
Output high voltage
(except OSCOUT, FS,
FSD, SC LK , SDOU T )
VOH IOH=-4 mA VDD - 0.45
–
–
V
Output High Voltage
OSCOUT VOHOSC IOH =-3. 0 mA VDD - 0.9
–
–
V
Output high voltage
FS, FSD, SCLK, SDOUT VOH IOH=-1 mA VDD - 0.45
–
–
V
I nput l ow leakage c urrent
IIL1 VSS < Vin < VIL1 10
–
40 μA
I nput high leakage curr ent IIH1 VIH1 < Vi n < 5.5
–
1 μA
I nput Leakage C urrent
OSCIN IIL2 VSS < Vin < VIL2 1
–
30 μA
I nput H i gh L eakage C ur r ent
OSCIN IIH2 VI H2 < V in < VDD 1
–
10 μA
ID D current at 3.0 V – 3.6 V Nominal at 3.3 V
Ac tive d igit al current IDD1dig
–
–
1.0 1.5 mA
A ctive PLL curr ent IDD1pll
–
–
1.0 1.5 mA
A ctive anal og cur r ent IDD1ana
–
–
12 17 mA
IDD total current* IDD1
–
–
15 20 mA
IDD total current*
IDD2
–
–
20
30
mA
IDD c urrent
PWDN=1
IDD2
–
–
1.0
5
μA
IDD c urrent
SLEEP=1 (Ext Ref Clk) IDD3
–
–
0.5 1.0 mA
IDD c urrent
IDL2 =1 (Ext Ref Clk) IDD4
–
–
10 15 mA
IDD c urrent
ENFEH=0 (Ext Ref Clk) IDD5
–
–
1.0 1.5 mA
*Note: IDD1 is with the secondary of the barrier left open.
IDD2 is with the secondary of the barrier connected to the 73M1912 fully powered.
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 19
3.3 Serial Interface Timing Specification
The 73M1 x22 has a s ync hron ous serial interface, cal led t he MAFE i nter fac e, to tran sfer data to and from a
host. Table 10 provides the tim ing s pecifi cation for the M AFE inter face.
Table 10: Serial Data Port Tim ing at 8 kHz Sam ple Rate
Parameter Min Nom Max Unit
SCLK period (Tsclk) – 1/1. 536 MHz – ns
SCLK t o FS delay (td1) – mode1 – – 20 ns
SCLK t o FS delay (td2) – mode1 –
–
20 ns
SCLK to SDOUT delay (td3) with 10 pf load
–
–
20 ns
Setup tim e SDIN to SCLK (tsu) 15
–
– ns
Hold t ime S DIN to S CLK (th ) 10
–
– ns
SCLK t o
FS
delay (td4) – mode 0
–
–
20
ns
SCLK t o
FS
delay (td5) – mode 0
–
–
20
ns
Figure 7: MA FE Ti ming Di agram
3.4 Analog Specifications
Thi s s ection p r ovides the electri cal char acteri zations of the 73M 1x22 anal og cir cui try.
3.4.1 DC S pecification s
V BG is to be connected to an ext er nal byp ass capacitor with a minimu m value of 0.1 μF. Th is pin is not
intended for any other external us e.
Table 11: Reference Voltage Specifications
Parameter
Test Condition
Min
Nom
Max
Units
VBG VDD=3.0 V – 3.6 V 0.9 1.19 1.4 V
VBG Noise 300 Hz – 3.3 kHz – -86 -80 dBm600
VBG PSRR 300 Hz – 30 kHz 40 – – dB
FS
(mode1)
FS
(mode0)
SDIN
SDOut
SCLK
73M1822/73M1922 Data Sheet DS_1x22_001
20 Rev. 1.6
3.4.2 Call Progress Monit or
The C al l Progr ess Monitor monitor s ac ti viti es on the l ine. The aud i o output contains both transmit and
receive data with a configurable level individually set by Register 0x10.
Figure 8 s hows the frequ ency respon se of t he Call Pr ogress Monit or Fil ter based up on the char acteri stics of
t he device pl us the extern al circuitry as shown .
Figure 8: Call Progress Monitor Frequency Response
U1 NJM2135
CD
1-VIN
4
V+ 6
GND 7
VOUT1 5
VOUT2 8
VREF1
2
VREF2
3
AOUT
VCC
VCC
R3 120K
+
C2
2.2uF
LS1
INTERVOX
AT-2308
C4
1uF
R2 120KR1 120K
C3
1uF
C1 0.1uF
Figure 9: Demo Boa r d Circui t Connecting AOUT to a Speaker
Table 12: Com ponent Va l ues for the Speaker Driver
Quantity
Reference
Part Description
Part
1 C1 Ceramic capacitor 0.1 μF
1 C2 Ceramic capacitor 2.2 μF (optional)
2 C3, C4 C er amic capacitor 1 μF
1 LS1 Sound transducer Speaker ( Inter vox)
3 R1, R2, R3 1/8 W resistor 120 kΩ
1 U1 Audio amplifier NJ M 213 5 (New Japan R adio)
A ll measur ement s are at the AOU T p in wit h CMVSEL=0. Note that wh en CMVSEL=1, the peak signal at
A OUT is i ncreased to appr oximately 1.11 Vpk.
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 21
Table 13: Call Progress Monitor S pecification
Parameter Test Condition Min Nom Max Units
AOUT for tran sm it
1 kHz full swing code word at
SDIN p in
CMRXG=11(Mute)
O bserve AO UT pi n
– – – –
CMTXG=00 – 0.98 – Vpk
CMTXG=01 relati v e
to CMTXG =00 – -6 – dB
CMTXG=10 relati ve
to CMTXG =00 – -12 – dB
CMTXG=11(Mute) – Mute – dB
AOUT t ran s mit THD CMTXG=00 – 40 – dB
A OUT for r eceive
1.0 Vpk, 1 kHz at the line or 0.5
Vpk at RXP/RX M with
RXG=10 (+6 dB)
CMTXG=11(Mute)
O bserve AO UT pi n
– – – –
CMRXG=00 – 0.96 – Vpk
CMRXG =01 relative
t o C M RXG=00 – -6 – dB
CMRXG =10 relative
t o C M RXG=00 – -12 – dB
CMRXG=11(Mute) – Mute – dB
AOUT r ec ei ve THD
CMRXG=00
–
40
–
dB
AOUT output
impedance – – 10 – kΩ
73M1822/73M1922 Data Sheet DS_1x22_001
22 Rev. 1.6
3.5 73M1x2 2 L in e-Side Electrical Specifications (73M1912)
Table 14 li sts the absol ute maximum r ati ngs for the l ine s id e. Oper ati on ou tside these rating l imi ts may
cause permanent damage to thi s devic e.
Table 14: L ine-S i de Absolute Maxim um Ratings
Parameter Min Max Unit
P in input voltage from VPX to VNX -0.5 6.0 V
P in input voltage ( al l other pins ) to VN S -0.5 4.0 V
3.6 Reference and Regulation
Table 15 list s th e V BG specifications. VBG should be c onn ected to an exter nal by pass capacitor with a
minimum value of 0.1μF. This pin is not intended for any other external use.
The following conditions apply: V PX=5 V; Barr i er Powered Mod e; Bar r ier D ata R ate across the Bar r ier=1.5
Mbps; VBG connected to 0.1 μF external c ap.
Table 15: VBG Specifica tions
Parameter Test Condition Min Nom Max Units
VBG S ee condi tions above. – 1.19 – V
VBG Noise 300 Hz – 3.3 kHz – -86* -80 dBm600
VBG PSRR 300 Hz – 30 kHz 40 – – dB
VPS VPX=5.5 V – 3.15 – V
VPS PSRR VPX=4.5 V to 5.5 V – 40 – dB
3.7 AC Signal Levels
Table 16 s hows the maximum tr ansmit l evels that the 73M 1912 L i ne-Si de Device is capable of deliver i ng .
Table 16: Maximum Tr ansmit L ev els
Transmit Type
Maximum
Level at th e
Line (dBm)
Peak to
RMS
Ratio
RMS V ol tage
on the Line
(V)
Peak
Vol ta ge on
the Line (V )
V.90 -12.0 4 0.195 0.778
QAM -7.3 2.31 0.334 0.772
DPSK -5.1 1.81 0.431 0.779
FSK -3.0 1.41 0.548 0.775
DTMF (high tone) -7.8 1.41 0.316 0.446
DTMF (low tone) -9.8 1.41 0.251 0.354
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 23
3.8 DC Transfer Characteri stics
Table 17 list s th e maximum DC output levels. All tests ar e driven at pin DC I and measur ed at pin DCS .
DCEN=1 and p in DCI is sh orted to pin DCS. ILM=0 unl ess stat ed otherwise.
Table 17: Maximum DC Tr an smit L ev els
Parameter Test Condition Min Nom Max Units
V
DCON
(DC "On" Voltage) DCIV=00 0.69 0.73 0.78 V
DCIV=01 0.89 0.94 0.99 V
DCIV=10 1.01 1.06 1.11 V
DCIV=11 1.13 1.18 1.23 V
W ith ENAC=0 DCIV=XX 0.27 0.31 0.35 V
DC Gain VDCON<VDCI<0.4V+VDCON -0.25 0 .0 +0.25 dB
IDCI before ILIM ILM=1 VDCI=0.28V+VDCON – – 1 µA
IDCI after ILIM ILM=1 VDCI=0.44V+VDCON 20 – – µA
*Noise At the line with 300 Ω(ac) (0.15 - 4.0 kHz) – -85 -80 dBm
73M1822/73M1922 Data Sheet DS_1x22_001
24 Rev. 1.6
3.9 Transm i t P ath
Table 18 li sts the transmit path char acteri sti cs . A pattern for a sinu soid of 1 kHz, ful l scale (code word of
+/- 32,767) from the 73M1x22 is forced and A CS is m easur ed with R 10=255 Ω. Test condit i ons are:
ACZ=00 (600 Ω termination), THEN=1, ATEN=1, DAA=01, TXBST=0.
Table 18: Trans mit Path
Parameter
Test Condition
Min
Nom
Max
Units
O ffset volt age 50% 1’s density relative to 1.4 V
Nom – 25 – mV
T x ga in DAA=00
–
+2
–
dB
DAA=01
–
0
–
dB
DAA=10
–
-4
–
dB
DAA=11
–
-8
–
dB
AC s wing DAA=01 0.39 0.425 0.45 Vpk
DAA=00
–
0.535
–
Vpk
TXBST=1, DAA=xx
–
0.850
–
Vpk
ACZ=01
–
0.2751
–
Vpk
ACZ=10
–
0.295
–
Vpk
ACZ=11
–
0.265
–
Vpk
I dle noise 300 Hz – 4 k Hz
–
-81
–
dBm
THD 300 Hz – 4 kHz
–
-80
–
dB
I nter mod d istor ti on
1.0 kHz and 1.2 kHz
summed
300 Hz – 4 kHz – -85 – dB
PSRR -30 dBm signal at VPX in Mixed
Mode; 300 Hz – 30 kHz – – 40* dB
P ass band ripple 150 Hz – 3.3 kHz -0.125 – +0.125 dB
G ai n relative to 1 kHz
–
–
–
dB
0.5 kHz
–
0.17
–
dB
1.0 kHz
–
0
–
dB
2.0 kHz
–
0.193
–
dB
3.3 kHz
–
-0.12
–
dB
A liased i mag e Fs +/ - 1 kHz, r elative t o 1 kHz
–
-75
–
dB
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 25
3.10 R ec eive Path
Table 19 list th e rec ei ve path characteri stics . All test inputs are dri ven by a si gnal generator at the collector
of Q5.
Table 19: Receive Pat h
Parameter
Test Condition
Min
Nom
Max
Units
Differen tial inpu t
resistance RXP/RXM
–
1000 – kΩ
Input level Differential, RX P/ RXM
–
1.0 1.16 Vpk
Input level Common mode, R XP/R XM
–
1.37 V
Overall ΣΔ ADC
modul ation gai n inc l usive
of 73M1902 processing
Normalized to VR ef=1.40 V.
RXG=00 ; RXM=0 43 47 51 µV/bit
O ffset volt age
–
13
70
mV
Rx g ain RXG=00
–
0 – dB
RXG=01 2 3 4 dB
RXG=10 5 6 7 dB
RXG=11 8 9 10 dB
RXBST=1, RXG=00 17.5 19.5 21.0 dB
O veral l receive
frequency response
inclusive of 73M1902
processing
Relative to 1 kHz
–
–
–
0.3 kHz – 3.3 kHz -0.25 0 +0.25 dB
Fs (8 kHz)
–
-75
–
dB
I dle noise 300 Hz – 4 k Hz
–
-81
–
dBm
THD RXG[1:0]=00
–
-80
–
dB
RXBST=1
–
-60
–
I nter mod d istor ti on
1.0 kHz and 1.2 kHz
summed
300 Hz – 4 kHz
–
-80
–
dB
Crosstalk 1 Vpk 1 kHz sine wave at
TXP; F FT on Rx A DC
samples, first fou r harmoni cs
reflected to the l i ne.
–
-85
–
dBm
CMRR RXP =R XM 1 Vpk 40 –
–
dB
PSRR
-30 dBm signal at VPX in
B ar r ier Powered Mode;
300 Hz – 30 kHz.
–
–
40*
dB
73M1822/73M1922 Data Sheet DS_1x22_001
26 Rev. 1.6
3.11 Transmit Hybrid Cancellation
Table 20 li sts the transmit hyb r i d cancell ation c haracter i stics . Unless stated otherwise, t est c ond i tions ar e:
ACZ=00 (600 Ω termination), THEN=1, ATEN=1, DAA=01, TXBST=0. TXM is externally fed back into the
73M1912 to effect cancellation of transmit signal.
Table 20: Transmit Hy brid Cancellation Characteristics
Parameter
Test Condition
Min
Nom
Max
Units
Transmit hybrid cancellation M easure RxD in H IC – 26 – dB
O ffset volt age 50% 1’s Density – 25 50 mV
AC s wing
1 kHz sinusoid at Tip
and Ring 0.85 0.95 1.05 Vpk
I dle noise 300 Hz – 4 kHz at Tip
and Ring – -81 – dBm
3.12 Receive Notch Filter
Table 21 lists the receive notch filter characteristics. All measurements taken w ith RLPNEN= 1, TXEN=0,
RXG=00, ATEN=1. RXP is driven with 1 Vpk signal.
Table 21: Receive Notch Filter
Parameter Test Condition Min Nom Max Unit
Magni tude response
RLPNH=0 (12 kHz Notch)
300 Hz
–
0.0
–
dB
1 k Hz
–
+0.03
–
dB
3 k Hz
–
+0.04
–
dB
16 kHz -20 -50
–
dB
P assband R i pple (0.3 kHz – 3.4 kHz)
–
+/- 0.15
–
dB
Delay
–
28.8
–
μs
300 Hz
–
28.93
–
μs
1 k Hz
–
30.25
–
μs
3 k Hz
–
41.62
–
μs
12 kH z
–
9.95
–
μs
Magni tude response
RLPNH=1 (16 kHz Notch)
300 Hz
–
0.0
–
dB
1 k Hz
–
+0.04
–
3 k Hz
–
+0.11
–
dB
12 kH z -20 -50
–
dB
P assband R i pple (0.3 kHz – 3.4 kHz)
–
+/- 0.15
–
dB
Delay
–
30.53
–
μs
300 Hz
–
30.66
–
μs
1 k Hz
–
31.93
–
μs
3 k Hz
–
42.26
–
μs
16 kH z 4.74
–
μs
DS_1x22_001 73M1822/73M1922 Data Sheet
Rev. 1.6 27
3.13 Detectors
Thi s s ection p r ovides electri cal char acteri stics fo r the following detectors:
• Over-Voltage.
• Over-Current.
• Under-Voltage.
• Over-Load.
3.13.1 Over-Voltage Detector
The values in Table 22 wer e measur ed in IDL2 m ode between RGP and R GN.
Table 22: Over -Voltage Detector
Parameter Test Condition Min Nom Max Unit
O ver voltage l evels OVDTH=0 0.52 0.6 0.68 V
OVDTH=1 0.59 0.7 0.77 V
3.13.2 Over-Current Detector
The values in Table 23 wer e measur ed in Barr i er Powered M ode.
Table 23: Over -Curr ent Detector
Parameter Test Condition Min Nom Max Unit
Over current level
Meas ured at DCS.
0.85
0.96
1.10
V
3.13.3 Under-Voltage Detector
The values in Table 24 wer e measur ed in Barr i er Powered M ode. In the recommended sc hem atic ( see
Figure 10 and Figure 11), dis connect Q5 collector and connect to an exter nal powe r suppl y, VPE, thr ough a
600 Ω resistor.
Table 24: Under-Vo ltage Detecto r
Parameter
Test Condition
Min
Nom
Max
Unit
Under voltage detect
Meas ure V PE when UVD is
detected as VPE is dec r eased. 5.6 – 6.5 V
3.13.4 Over-Load Detector
The values in Table 25 wer e measur ed in Barr i er Powered M ode.
Table 25: Over -Loa d Detector
Parameter Test Condition Min Nom Max Unit
O ver load level Meas ured at DCI wit h 1 kHz. 0.6 0.75 0.9 Vpk
73M1822/73M1922 Data Sheet DS_1x22_017
28 R ev 1.6
4 Applications Information
Thi s s ection p r ovides gener al usage i nformat ion for the design an d impl emen tati on of the 73M1x2 2. The doc uments lis ted in Section Error!
Reference source not found. provide more detai l ed informati on. Always cons ult with Teri dian Semicondu ctor for the l atest recommendat ions before
finalizing a design.
4.1 E xa mp l e Sch emat ic o f t he 73M19 22 an d 73M182 2
Figure 10 shows a reference schematic for the 73M1922. Figure 11 shows a referen ce s chemati c of the 73M1 822. N ote that minor changes may
occur to the r eference mater i al from ti me t o time and the reader is encour aged to contac t Teridian for the l atest information. For more informat i on
about s chematic and layout design, see the 73M1822/73M1922 Sc hema ti c and Layout Guidelines.
Figure 10: Recommended Circuit for the 73M1922
R69
100K*
OPTIONAL
C13
15pF
FSBD
C31
1nF
C33
0.1uF
FS
INTB
C28
1nF
C15
0.1uF
SDOUT
C30
1nF
VCCVCCVCC
C17
0.1uF
SDIN
C19
27pF
C18
27pF
Y1
24.576MHz
1
3
24
C25
1nF
SCLK
C14
15pF
* R 69 opt ional
TIP
RING
+
C4
10uF
+
C7
1uF
R4
100K, 1%
+C8
4.7uF
R2
10M
R6
100K, 1%
C12
0.1uF
U2 73M1912
OFH
4
VND/VNX
5
SCP
6
MID
7
VPX
8
SRE
9
SRB
10 VBG 11
ACS 12
VNS 13
VPS 14
RXP 15
RXM 16
TXM 17
DCD 18
DCE 19
DCB 20
DCI
1
RGN
2
RGP
3
R5
8.2
+C21
3.3uF
-+
BR1
HD04
4
1
3
2
C43
1nF
T11 4
2 3
Q4
MMBTA92
1
32
C26
1nF
C48
0.01uF
+C22
3.3uF C38
0.1uF
C24
NC (1nF, 3kV)
R12
5.1K
C3 0. 022 (200V, 1206)
C37
0.01uF
C9
0.47uF
+C32
3.3uF
R11
3K
R8
100K, 1%
Q2
MMBTA42
1
32
R18
1K
C5
100pF
R3 412K, 1%
Q3
MMBTA42 1
32
R52 200
R67 1M
R66 1M
U1 73M1902
FSBD
1
AOUT
8VPT/VPD 15
TYPE
9
OSCIN
5
OSCOUT
6
VPA/VPM
10 VNM/VNT 11
SCLK 17
SDOUT 20
SDIN 19
VND
3FS
2
VPD/VPPLL
4
VNPLL
7
M/S 12
PRM 13
PRP 14
INT 16
VND 18
R9 100K, 1%
VNS
C10
0.47uF
R10
255, 1%
Q5
MMBTA06
1
32
D1
MMSZ4710T1
Q6
BCP56
1
2
34
C49
0.1uF
C1 0. 022(200V, 1206)
VCC
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 29
Figure 11: Recommend ed Circu it for the 73M1822
C48
0.01uF
D1
MMSZ4710T1*
VNS
C13
15pF
C14
15pF
R12 5.1K
-+
BR1
HD04
4
1
3
2
C1
0. 022uF (200V, 1206)
R3
412K, 1%
C25
1nF
R11
3K
R18 1K
Q3
MMBTA42
1
3
2
Q6
BCP56
1
2
34
Q4
MMBTA92
1
32
R8
100K, 1%
R10
255, 1%
R4
100K, 1%
R6
100K, 1%
Q5
MMBTA06
1
32
VPS
AFEOUT
Q2
MMBTA42
1
3
2
Y1 24.576MHz
13
24
R52
200
C49
0.1uF
+C4
10uF
C33
0.1uF
FSBD
+C21
3.3uF
T1
14
23
+
C32
3.3uF
C19
27pF
C15
0.1uF
+
C22
3.3uF
C37
0.01uF
AFEIN
SCLK
R66 1M
RINGD
C31
1nF
I solation B ar r ier
+
C7
1uF
C12
0.1uF C38
0.1uF
C43
1nF
+C8
4.7uF
U1
73M1822
PRM
1PRP
2VPD
3INT
4SCLK
5SDIN
6SDOUT
7FSBD
8FS
9VND
10
GPIO6
11 VND
12 VPD
13 OSCIN
14 OSCOUT
15 VNPLL
16 VNA
17 AOUT
18 VPA
19 VNM/VNT
20 M/S
21
SRE 22
SRB 23
VBG 24
ACS 25
VNS 26
VPD/VPS 27
RXP 28
RXM 29
TXM 30
DCD 31
DCE 32
DCB 33
DCI 34
RGN 35
RGP 36
OFH 37
M20BP 38
VND/VNX 39
SCP 40
MID 41
VPX 42
C3
0. 022uF (200V, 1206)
C28
1nF
R67 1M
C9
0.47uF
VCC
C24
NC (1nF, 3kV)
R5
8.2
C17
0.1uF
C5
100pF
C30
1nF
FS
C10
0.47uF
C18
27pF
R2
10M RING
TIP
R9
100K, 1%
VNS
VNS
C26
1nF
OPTIONAL
VCC
73M1822/73M1922 Data Sheet DS_1x22_017
30 R ev 1.6
4.2 Bill of Materials
Table 26 provides the 73M1x22 bill of materials for the reference schem atics provided in Figure 10 and Figure 11.
Table 26: Refe rence Bi ll o f M ater ials f or 73M182 2/73M1922
Reference
Part Description
Example Source
Example MFR P/N
BR1 HD04 rectifier bridge, 0.8A, 400V Di odes Inc. HD04-T
C1, C3 0.022μF 200V, X7R, 1206 Panasonic ECJ-3FB2D223K
C4 10μF 6.3V, tantalum, 0805 AVX, Panasonic TCP0J106M8RA
C5
100pF 50V, ceramic, 0603
Taiyo Yuden
UMK107CH101JZ-T
C7
1μF 6.3V, tantalum, 0805
Rohm
TCP0J105M8R
C8 4.7μF, 6.3V, X5R, ±10%, ceramic, 0805 Panasonic ECJ-2YB0J475K
C9, C10 0.47μF, 6.3V, X5R, ±10%, ceramic, 0603 Panasonic ECJ-1VB0J474K
C12, C15, C17,
C33, C38, C49 0.1μF, 16V, X7R, ±10%, ceramic, 603 Panasoni c, Kemet C0603C104K8RACTU
C13, C14 15pF 50V, ceramic, 0603 Panasonic ECJ-1VC1H150J
C18, C19 27pF 50V, ceramic, 0603 Panasonic ECJ-1VC1H270J
C21, C22, C32
3.3μF, 6.3V, X5R, ±10%, ceramic, 0805
Panasonic
ECJ-2YB0J335K
C24
NC (1nF, 3kV)
C25, C26, C28,
C30, C31, C43
1nF 10V, X7R, ceramic, 0603
Panasonic
C0603C102K8RACTU
C37, C48
0.01μF, 50V, X7R, ±10%, ceramic, 603
AVX, P an ason ic , UTC
06035C103KAT2A
D1
25V, 500mW Zener diode
ON Semi, D i odes, Inc .
MMSZ4710T1
Q2, Q3
A 42, NP N 300 V transistor SOT23
Diodes, Centr al Semi
MMBTA42LT1G
Q4 A9 2, PNP 30 0 V tra nsi sto r SOT 23 Diodes, On Semi MMBTA92LT1G
Q5 A06, NPN 80 V transi stor SOT23 F airchild , On S emi MMBTA06LT1G
Q6
NPN 80 V transistor SOT223
Fairchild, On Semi
BCP56
R2 10 M 1%, 1/8W resistor 0805 Panasoni c, Yageo RC0603FR-0710ML
R3
412 K, 1%, 1/16W resistor 0603
Panasonic
ERJ-3EKF4123V
R4, R6, R8, R9 100K, 1%, 1/16W r esistor 0603 Panasonic ERJ-3EKF1003V
R5 8.2, 1%, 1/8W resistor 080 5 Vishay CRCW08058R20FNEA
R10
255, 1%, 1/16W resistor 0603
Panasonic
RC0603FR-07255RL
R11
3 K, 1/16 W r esistor 0603
P anasoni c, Yageo
RC0603FR-073K0L
R12
5.1 K, 1/ 16 W r esistor 0603
P anasoni c, Yageo
RC0603FR-075K1L
R18 1 K, 1/16W r esistor 0603 Panasonic ERJ-3EKF1001V
R52 200, 1/16W resi stor 0603 Panasonic ERJ-3EKF2000V
R66, R67 1 M,1/8W resi stor 0805 Panasoni c, Yageo RC0805FR-071ML
R69* 100K typ. 5%, 1/10W r esistor 0603 Yageo RC0603JR-07100KL
T1 Pu l se transformer See Table 28.
Y1
24.576 MHz crystal (fundamental)
ECS/Abracon
–
* Opti onal – see the 73M1822/73M1922 Sc hemati c an d Layou t Gui deli n es for detai ls.
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 31
4.3 Over-Voltage and EMI Protection
Over-voltage/over-current prot ection is r equired to meet wors t-case condi ti ons for target countr i es.
UL1950, EN 6 09 50 , I EC 60 95 0, ITU-T K .20/K.21 and GR -1089-CORE spec i fi cations define the prot ection
requi r ements for many countr i es. A s in gle des i gn can be i m plemented to m eet al l these requiremen ts.
Figure 12 sh ows a r ecommended protection ci r cui t topology. Fuse (F1) should b e rated for 6 00 V op er ati on
and the bidirectional thyristor (E1) should have a minimum break-over of 275 V and be ab l e to survive a 100
A fast t r ansi ent. In addit ion to over-voltage and current protection, the line-inter face des i gn er should m ake
provis ions to pr event EMI emis sions and s uscep ti bili ty. Figure 12 also illustrates how L1, L2, C35, C36 and
C42 can pr ovide this suppr ess i on. The ferri te beads, L1 and L2, should be capable of passing 200 mA and
have an impedance of 2000 Ω at 100 MHz. C35, C36 and C42 shoul d be 220 pF and rated for a
breakdown voltage gr eater than the highes t i sol ati on voltage that i s requ i r ed for countr y com pati bili ty. C35
and C36 should be returned to an earth ground. EMI suppression is dependent on the physical design of
t he overall cir cui t and n ot all t he suppr ession componen ts may be needed in ever y design and app l ic ati on.
The values s hown are typical and shoul d be op timized for a par ti cul ar design.
R
T
C35
220 pF, 3000 V
C36
220 pF, 3000 V
L1
2000 Ω @ 100 MHz
F1
TR600-150
L2
2000 Ω @ 100 MHz
J1
RJ-11
1
2
3
4
5
6
E1
P3100SBRP
220 pF,
300 V
C42
Figure 12: Suggested Over -voltage Prote ction and EMI Suppression Ci rcuit
Table 27: Reference Bill of Materials for Figure 12
Reference
Part Description
Source
Example MFR P/N
E1
B idir ectional t hyristor, 27 5V/ 100A
Diodes, Inc.
TB3100H-13-H
F1
150mA, 600V PTC resettabl e fuse
Bourns
MF-R015/600 or equivalent
L1,L2
2 KΩ @ 100 MHz, 200 mA min, 0805
Steward/TDK
MPZ2012S601A
C36, C35
220 pF , 3000 V
TDK
C4532COG3F221K
C42
22 0 p F , 30 0 V
Vishay
VJ1206Y221KXEAT5Z
73M1822/73M1922 Data Sheet DS_1x22_017
32 Rev. 1.6
4.4 Iso l ation B arr ier Pu ls e Tr an sf ormer
The isolation element used by the 73M1x22 is a standard digital pulse transformer. Several vendors supply
compat ible tr ansformer s wit h u p to 6000 V rat i ngs. Since the transformer is the only componen t cross i ng
t he isolat ion barr ier other than EM I capacitors that may be required, i t solely determi nes the isolation
between the PSTN and the 73M1922 di gital i nter face. This method of i solation is significantly superior to
ot her is olat ion tec hniques with major advantages in high c ommon mode voltage op er ati on, lower r adiat ed
noise (EM I) and improved oper ati on in noisy en vironments. Table 28 lists s ome p uls e transformers
com patible with the 73M1x22. The tabl e al so i nclud es lower-v ol tage tr ansformers that offer l ow-cost
alternatives if suc h voltages are sufficient.
Table 28: Com patible Pulse Transformer Source s
Company Number
Sumida
ESMIT 4180
Wurth Electronics Midcom Inc. 750110001
UMEC TG-UTB01543S
Datatronics PT79280
AAsupreme P95003
Tabl e 29 lists some of the typical transformer speci fication s used b y t he 731 x22. Contact the manufacturer
dir ectly f or produc t i nformation.
Table 29: Transformer Characteristics
Parameter
Test Condition
Min
Nom
Max
Tolerance
Unit
Inductance
10 0 kH z , 10 mV AC , 1-2, Ls.
54
60
200
–
μH
Interwinding
Capacitance – – – 6 – pF
Tu rn Ratio – – 1:1 – ±2 % N/A
DC Resistan c e
Primary
–
–
0.25
–
Ω
Secondary – – 0.25 – Ω
Dielec tric Br eakdown
Voltage 1 sec 2000 3750 – – Vrms
E T Constant – – 1.2 – – Vμs
S urge Test
1.2 x 50 μs
2800
6000
–
–
Vpeak
O perat i ng Temperature
–
-40
–
85
–
°C
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 33
5 Control and Status Registers
Table 30 s hows the r egister map of ad dressabl e r egister s for the 73M 1822 and 73M 192 2. Th e shaded
cel ls i n the r egis ter m ap indicate read only and cannot be modified. Reserved bits should be left in their
defau lt state. Acc ess ing unspec i fi ed r egister s s hou l d b e avoided. Each register and b it is desc r i bed i n
det ail in th e followin g sect ions.
For r egis ters 0x12 through 0 x1F , wh i ch are located in the Lin e-Side Device, there is a minimum tim e
between consec utive wri te transac tions of 300 µs.
Table 30: Control and Status Regis ter Map
Address
(hex) Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
01 00h/9Ch DSYEN NSLAVE2 NSLAVE1 NSLAVE0 MSIDEN MSID SCK32 Reserved
02 00h TMEN Reserved Reserved Reserved Reserved ENLPW SPOS HC
03 F0h GPIO7 GPIO6 GPIO5 GPIO4 RGMON DET SYNL RGDT
04 F7h DIR7 DIR6 DIR5 DIR4 REVHSD3 REVHSD2 REVHSD1 REVHSD0
05 0Bh ENGPIO7 ENGPIO6 ENGPIO5 ENGPIO4 ENAPOL ENDET ENSYNL ENRGDT
06 00h POL7 POL6 POL5 POL4 Reserved Reserved Reserved Reserved
07 00h Reserved Reserved Reserved Reserved DTST3 DTST2 DTST1 DTST0
08 DAh PSEQ7 PSEQ6 PSEQ5 PSEQ4 PSEQ3 PSEQ2 PSEQ1 PSEQ0
09 EFh PRST2 PRST1 PRST0 PDVSR4 PDVSR3 PDVSR2 PDVSR1 PDVSR0
0A 31h ICHP3 ICHP2 ICHP1 ICHP0 Reserved KVCOH2 KVCOH1 KVCOH0
0B 2Ah Reserved NDVSR6 NDVSR5 NDVSR4 NDVSR3 NDVSR2 NDVSR1 NDVSR0
0C 06h NSEQ7 NSEQ6 NSEQ5 NSEQ4 NSEQ3 NSEQ2 NSEQ1 NSEQ0
0D 42h LOKDET SLHS Reserved Reserved CHNGFS NRST2 NRST1 NRST0
0E 00h FRCVCO PWDNPLL Reserved Reserved Reserved Reserved RGTH1 RGTH0
0F 2Ch ENFEH PWDN SLEEP Reserved XIB1 XIB0 Reserved Reserved
10 00h Reserved Reserved Reserved CMVSEL CMTXG1 CMTXG0 CMRXG1 CMRXG0
12 00h OFH ENDC ENAC ENSHL ENLVD ENFEL ENDT ENNOM
13 00h DCIV1 DCIV0 ILM ACCEN PLDM OVDTH IDISPD1 IDISPD0
14 00h TXBST DAA1 DAA0 Reserved RXBST RLPNH RXG1 RXG0
15 00h Reserved DISNTR Reserved CIDM THEN ENUVD ENOVD ENOID
16 01h TXEN RXEN RLPNEN ATEN FSCTR3 FSCTR2 FSCTR1 FSCTR0
17 00h APWS Reserved Reserved ACZ1 ACZ0 Reserved Reserved Reserved
18 01h TEST3 TEST2 TEST1 TEST0 Reserved Reserved Reserved Reserved
19 00h POLL MATCH Reserved IDL2 INDX3 INDX2 INDX1 INDX0
1A 00h RNG7 RNG6 RNG5 RNG4 RNG3 RNG2 RNG1 RNG0
1B 00h LV7 LV6 LV5 LV4 LV3 LV2 LV1 Reserved
1C 00h LC6 LC5 LC4 LC3 LC2 LC1 LC0 Reserved
1D 90h REVLSD3 REVLSD2 REVLSD1 REVLSD0 Reserved Reserved Reserved Reserved
1E 00h ILMON UVDET OVDET OIDET SLLS Reserved Reserved Reserved
1F 00h POLVAL7 POLVAL6 POLVAL5 POLVAL4 POLVAL3 POLVAL2 POLVAL1 POLVAL0
73M1822/73M1922 Data Sheet DS_1x22_017
34 Rev. 1.6
Throug hout thi s doc ument, type W i s read/write, typ e WO i s write only and type R i s read only. R egister s
and bits are defined as 0x16[3:0 ], wh er e 0x16 i s the register address and the numbers in s quare b r ackets
specify t he add r ess bit s. The bit order i s [msb – ls b] for a field. For examp l e, [3:0] means bits 3 through 0
of a p ar ti cul ar field.
Table 31: Alphabe tical B it Map
Bit Name Register Page Default Type Category
ACCEN 0x13[4] 68 0 W DAA Control Function
ACZ1/0
APWS
ATEN
CHNGFS
CIDM
CMRXG1/0
CMTXG1/0
CMVSEL
DAA1/0
DCIV1/0
DET
DIR4
DIR5
DIR6
DIR7
DISNTR
DTST0
DTST1
DTST2
DTST3
DSYEN
ENAC
ENAPOL
ENDC
ENDET
ENDT
ENFEH
ENFEL
ENGPIO7
ENGPIO6
ENGPIO5
ENGPIO4
ENLPW
ENLVD
ENNOM
ENOID
ENOVD
ENRGDT
ENSHL
ENSYNL
ENUVD
FRCVCO
FSCTR
GPIO4
GPIO5
GPIO6
GPIO7
HC
ICHP
IDL2
0x17[4:3]
0x17[7]
0x16[4]
0x0D[3]
0x15[4]
0x10[1:0]
0x10[3:2]
0x10[4]
0x14[6:5]
0x13[7:6]
0x03[2]
0x04[4]
0x04[5]
0x04[6]
0x04[7]
0x15[6]
0x07[0]
0x07[1]
0x07[2]
0x07[3]
0x01[7]
0x12[5]
0x05[3]
0x12[6]
0x05[2]
0x12[1]
0x0F[7]
0x12[2]
0x05[7]
0x05[6]
0x05[5]
0x05[4]
0x02[2]
0x12[3]
0x12[0]
0x15[0]
0x15[1]
0x05[0]
0x12[4]
0x05[1]
0x15[2]
0x0E[7]
0x16[3:0]
0x03[4]
0x03[5]
0x03[6]
0x03[7]
0x02[0]
0x0A[7:4]
0x19[4]
67
67
66
45
72
40
40
40
55
66
73
39
39
39
39
59
76
76
76
76
51
68
59
68
73
73
38
68
39
39
39
39
59
68
65
74
74
72
68
59
73
38
67
39
39
39
39
51
45
38
00
0
0
0
0
00
00
0
00
00
0
1
1
1
1
0
0
0
0
0
0/1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0001
1
1
1
1
0
1100
0
W
W
W
W
W
W
W
W
WO
WO
R
W
W
W
W
WO
W
W
W
W
W
WO
W
WO
W
WO
W
WO
W
W
W
W
W
WO
WO
WO
WO
W
WO
W
WO
W
W
W
W
W
W
W
W
W
DAA Control Function
DAA Control Function
DAA Control Function
PLL System Timing Control
DAA Control Function
Call Progress Monitor
Call Progress Monitor
Call Progress Monitor
Signal Control Function
DAA Control Function
Line Sensing Control
GPIO Control
GPIO Control
GPIO Control
GPIO Control
Barrier Control Function
Loopback Control
Loopback Control
Loopback Control
Loopback Control
Slave Control
Current Limi ting Detection Control and Status
Barrier Control Function
Current Limi ting Detection Control and Status
Line Sensing Control
Line Sensing Control
Power Control Function
Current Limi ting Detection Control and Status
GPIO Control
GPIO Control
GPIO Control
GPIO Control
Barrier Control Function
DAA Control Function
DAA Control Function
Over-Current Detection Control and Status
Over-Voltage Detection Control and Status
Ring Detection Status Function
DAA Control Function
Barrier Control Function
Under-Voltage Detection Control and Status
Device Clock Management
DAA Control Function
GPIO Control
GPIO Control
GPIO Control
GPIO Control
MAFE Configuration
PLL System Timing Control
Power Control Function
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 35
Bit Name
Register
Page
Default
Type
Category
IDISPD0
IDISPD1
ILM
ILMON
INDX
KVCOH
LC
LOKDET
LV
MATCH
MSID
MSIDEN
NDVSR
NRST
NSEQ
NSLAVE
OFH
OIDET
OVDET
OVDTH
PDVSR
PLDM
POL7
POL6
POL5
POL4
POLL
POLVAL
PRST
PSEQ
PWDN
PWDNPLL
REVHSD
REVLSD
RGDT
RGMON
RGTH1/0
RLPNEN
RLPNH
RNG
RXBST
RXEN
RXG0
RXG1
SCK32
SLEEP
SLHS
SLLS
SPOS
SYNL
THEN
TMEN
TEST
TXBST
TXEN
UVDET
XIB
0x13[0]
0x13[1]
0x13[5]
0x1E[7]
0x19[3:0]
0x0A[2:0]
0x1C[7:1]
0x0D[7]
0x1B[7:1]
0x19[6]
0x01[2]
0x01[3]
0x0B[6:0]
0x0D[2:0]
0x0C[7:0]
0x01[6:4]
0x12[7]
0x1E[4]
0x1E[5]
0x13[2]
0x09[4:0]
0x13[3]
0x06[7]
0x06[6]
0x06[5]
0x06[4]
0x19[7]
0x1F[7:0]
0x09[7:5]
0x08[7:0]
0x0F[6]
0x0E[6]
0x04[3:0]
0x1D[7:4]
0x03[0]
0x03[3]
0x0E[1:0]
0x16[5]
0x14[2]
0x1A[7:0]
0x14[3]
0x16[6]
0x14[0]
0x14[1]
0x01[1]
0x0F[5]
0x0D[6]
0x1E[3]
0x02[1]
0x03[1]
0x15[3]
0x02[7]
0x18[7:4]
0x14[7]
0x16[7]
0x1E[6]
0x0F[3:2]
65
65
66
66
36
45
73
45
73
36
51
51
45
45
45
51
65
74
74
74
45
65
39
39
39
39
36
36
45
45
38
38
37
37
72
72
72
67
67
73
55
55
55
55
51
38
59
59
51
59
67
76
76
55
55
73
38
0
0
0
0
0
001
0
0
0
0
0/1
0/1
101010
000
0000110
0/1
0
0
0
0
01111
0
0
0
0
0
0
0
111
11011010
0
0
0111
1001
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
11
WO
WO
WO
R
W
W
R
R
R
R
W
W
W
W
W
W
WO
R
R
WO
W
WO
W
W
W
W
W
R
W
W
W
R
R
R
R
R
W
W
W
R
WO
WO
WO
WO
W
W
R
W
W
R
W
W
W
WO
WO
R
W
DAA Control Function
DAA Control Function
DAA Control Function
DAA Control Function
Line-Side Device Register Polling
PLL System Timing Control
Auxiliary A/D Converter Status
PLL System Timing Control
Auxiliary A/D Converter Status
Line-Side Device Register Polling
Slave Control
Slave Control
PLL System Timing Control
PLL System Timing Control
PLL System Timing Control
Slave Control
DAA Control Function
Over-Current Detection Control and Status
Over-Voltage Detection Control and Status
Over-Voltage Detection Control and Status
PLL System Timing Control
DAA Control Functi on
GPIO Control
GPIO Control
GPIO Control
GPIO Control
Line-Side Device Register Polling
Line-Side Device Register Polling
PLL System Timing Control
PLL System Timing Control
Power Control Function
Device Clock Management
Device Revisi on
Device Revisi on
Ring Detection Status Function
Ring Detection Status Function
Ring Detection Status Function
DAA Control Function
DAA Control Function
Auxiliary A/D Converter Status
Signal Control Function
Signal Control Function
Signal Control Function
Signal Control Function
Slave Control
Power Control Function
Barrier Control Function
Barrier Control Function
MAFE Configuration
Barrier Control Function
DAA Control Function
Loopback Controls
Loopback Controls
Signal Control Function
Signal Control Function
DAA Control Function
Device Clock Management
73M1822/73M1922 Data Sheet DS_1x22_017
36 Rev. 1.6
5.1 Line-S id e D ev ice Register Pollin g
The R egis ter M ap as read from a 7 3M1x22 Hos t-Side Device cons is ts of t w o groups . Th e fi r st is the
Host-Si de Device registers ( 0x00 thr ough 0x11) and the sec ond is a copy of the L i ne-Si de Dev i ce register s
(0x12 through 0x1F).
A s an ext r a deg r ee of i ntegr it y the 73M 1x22 supports the abi l ity to manu ally moni tor the r egis ters of its Line-
Side Device. This is achieved by using the Manual Poll Function. The Line-Side register s that can be pol l ed
are 0x12 through 0x18.
The method i s to write t he offset add r ess of the Line-S i de Device r egister to be r ead i nto the INDX fiel d. Th e
val ue of this is the offset from 0x12; that is, Register 0x12 is 0x0, 0x13 is 0x1, etc. The next step is to set
the POLL bit, which cau ses th e device to read the reques ted r egister from t he Line-S ide Device. The value
of the requested Line-Side Device register i s wr i tten into POLVAL (0x1F). This value is compared with that
of the Host-Side copy and if they are the s ame t hen the MATCH bit is set .
The values pr esented at MATCH and POLVAL ar e valid appr oximately 600 μs (depend i ng up on the clock)
after a p oll r equest, and ar e vali d only after the POLL bit h as been r eset by the Hos t-Side Device.
Function
Mnemonic
Register
Location Type Description
INDX 0x19[3:0] W Index
A ddress of t he register to be manu ally poll ed with the results placed in
P OLVAL. Th is address sh ould be c l ear ed after the poll. D efault = 0.
MATCH 0x19[6] R Polling Match
0 = No m atch. (D efaul t)
1 = Th i s read-onl y bit i nd i cates that there is mat ch wit h the
corresponding polled register in the Host-Si de Device. The resul t of
t he polli ng function can be r ead only after the POLL bit is r eset to z er o
by the 73M1x22.
POLL 0x19[7] W Pollin g Enab le
0 = Pol l ing di sabl ed. (Default)
1 = Manually polls the control register in the Line-Side Device whos e
address is given by INDX . T he PO LL bi t re ma i ns hi g h unt il the
MATCH resul t i s avail able at whi ch ti me it will be r eset to 0 and the
MATCH bi t status can be r ead.
POLVAL 0x1F[7:0] R P ollin g Value
When 73M 1x22 i s pol l ed, the content of the Li ne-Si de Device Register
given by the offset address in INDX is placed in this register.
Defaul t = 0. This register can be r ead after the POLL bi t has been
res et to zero, ind i cati ng the r esul t i s ready.
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 37
6 Hardware Control Functions
This section describes the 73M1x22 capabil i ties with respect to its c onfi gurat ion and har dware pi n control.
Thi s includ es feat ures suc h as Interr upt Con tr ol, Power Management, Cl ock Contr ol , Gener al Purpose
I nput/Output (GPIO) and control of the Call Pr ogress Monitor.
6.1 Device Revision
The 73M1922 p r ovides the device revision num ber for t he Host-Side Device and the Li ne-Side Device.
For the 73M1822B07 and 73M1922A01 (73M1902B04) Host-Si de Device, the cur ren t revision i s 0111.
For the 73M1822B07 and 73M1922A01 (73M1912B07) Line-Side Device, the current revision is 1001.
Function
Mnemonic
Register
Location Type Description
REVHSDn 0x04[3:0] R Revision Host -S ide Device
These read only status bits indicate the revision of the 73M1x22
Host-Si de Device.
REVLSDn 0x1D[7:4] R Revision L ine-Side Device
These read-only status bits provide the Device ID for the 73M1x22
Line-S ide Device.
B efore the b ar r i er syn chr oniz ati on, the value i s 0000.
A fter the bar r ier synchr oniz ati on, the value r epresents the D evice ID
of the Line-Side Device (73M1912).
6.2 Interrupt Control
The 73M1 x22 supports a s ingle i nter r upt that can be as serted und er several configur able cond i tions . Th ese
include status of GPIOs, RGMON, DET, SYNL and RGDT.
A ll i nter r upt sour ces that are enab l ed are O R ’ed together to create the IN T out put signal. GPIO ports that
are c onfi gu r ed to be output will not gener ate i nter r up ts .
When the INT pin goes active (low), the host should read the interrupt source Register 0x03, which is then
cl eared aft er the r ead oper ation. An inter r upt during wake-on-ring should be interpreted as the detection of
a valid rin g signal.
Address 0x03
Res et State E0h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
GPIO7 GPIO6 GPIO5 GPIO4 RGMON DET SYNL RGDT
73M1822/73M1922 Data Sheet DS_1x22_017
38 Rev. 1.6
6.3 Power Management
The 73M1 x22 supports three mod es of power control for the device.
Normal mode The 73M1x22 operates normally.
S leep mode The device PLL is turned off and the internal clock is driven by Xtal.
S CK=1/8 Xtal. Control and status r egister s maintain thei r content.
Power Down The devi ce is s hu t down al together . In thi s mode the MA FE is
disabled together with the Xtal osc ill ator . To res tar t the nor mal
operations, RESET or powe r on r eset is requ i r ed.
Function
Mnemonic Register
Location Type Description
SLEEP 0x0F[5] W S leep Mode
0 = Dis able Sleep M ode.
1 = Enabl e Sleep Mode. ( D efaul t)
PWDN 0x0F[6] W Power Down Mode
0 = Dis able Power Down M ode. ( D efaul t)
1 = Enabl e Power Down Mode.
IDL2 0x19[4] W Ring Detect Functions
0 = Dis able ri ng detect monit or ing A/D fun ction. (Default)
1 = Enable ring detect monitoring A/D function.
ENFEH 0x0F[7] W Enab l e Front End Host
1 = Enabl e Front End of the 73M 1902 Host-Sid e D evice.
0 = Dis able Fr ont End of the 73M 1902 Host-Sid e D evice. (D efault )
6.4 Device Clock Management
Function
Mnemonic Register
Location Type Description
FRCVCO 0x0E[7] W Force VCO
0 = Th e system clock is dr iven from t he Xtal osc ill ator . (Default)
1 = Th e system clock is der ived from locked P LL. This is s et to 0
upon reset, Sleep or Power Down mode enabled.
PWDNPLL 0x0E[6] R PLL Powered Down
0 = PLL is not powered down. (Default)
1 = PLL is powered down.
XIB 0x0F[3:2] W Cryst al O s c illator Bias Current Cont rol
00 = Crystal oscillator bias current at 120 μA
01 = Crystal oscillator bias current at 180 μA
10 = Crystal oscillator bias current at 270 μA
11 = Crystal oscillator bias current at 450 μA (Default)
I f OSCIN is us ed as a c loc k input, XIB = 00 sett ing sh ould be used to
save power (=167 μA at 27.648 MHz).
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 39
6.5 GPIO Registers
The 73M1922 32-pin QFN package provides four I/O pins (GPIO7, GPIO6, GPIO5 and GPIO4). The
73M1822 (42-pin QFN package) provides one user GPIO pin (GPIO6).
G PIO pin s are not available on the 20-pin package version of the 73M1922.
E ach pi n can be configur ed independentl y as ei ther an input or an output.
A t power on and after a r eset, the GPIO pins ar e i nit iali zed to a hi gh impedan ce s tate to av oid unwan ted
current c ontenti on and consumpti on. The input struc tures ar e pr otected from float ing inputs, and n o output
levels are driven by any of the GPIO pins.
The GPIO pins are configured as inputs or outputs by writing to the I/O Direction register (DIR).
The mapping of GPIO pi ns is designed to corr espond to the bit location in thei r control and stat us register s.
The 73M19 22 suppor ts the abi l it y to generate an interrupt on the IN T pin. The s our ce c an b e configured to
generate on a r ising or a tr aili ng edg e. Onl y G PIO ports that are configur ed as i nputs c an be used to
generate i nter r upts.
Function
Mnemonic
Register
Location Type Description
DIR 0x04[7:4] W I/O Direction
These c ontr ol bits ar e used to designate the GPIO[7:4] pins as ei ther
inputs or outputs.
0 = GPI O pin is programmed to be an output.
1 = GPIO p in is programmed to be an input. (D efaul t)
GPIOn 0x03[7:4] W GPIO Status
Th ese b its reflect the status of the GPIO7, GPIO6, GPIO5 and GPIO4
pins.
If DIR bit is reset, reading this field will return th e logic al value of t he
appropr iate G PIOn pi n as an i nput.
If DIR bit is set the pins will outp ut the logical value as writt en.
ENGPIOn 0x05[7:4] W GPIO Interrupt Enable
E ach of the GPIO enable bit s in thi s register enab l es the
corresponding GPIO bit as an edge-trigger ed interrup t sourc e. If a
G PIO bit is set to one, an edge ( wh ich ed ge depen ds on the value in
t he GIP regis ter) of the corr esponding GPIO pin will caus e the IN T pin
t o go active low, and the edg e detectors will be r earmed wh en the
G PIO data register is r ead.
POLn 0x06[7:4] W GPIO Int e rrupt Edge Selection
Define the interr upt source as being ei ther on a rising or a falling ed ge
of the corresponding GPIO pin.
0 = A rising edge will trigger an interrupt from the corresponding pin.
(Default)
1 = A fallin g edge will trigger an interrupt from the corresponding pin.
73M1822/73M1922 Data Sheet DS_1x22_017
40 Rev. 1.6
6.6 Call Progress Monitor
For t he p urp ose of monitori ng activiti es on the l ine, a Cal l Progr ess M onit or is pr ovided i n the 73 M1 x22.
Thi s audi o output contains both transmit and recei ve data w i th configurable levels.
Function
Mnemonic Register
Location Type Description
CMVSEL 0x10[4] W Call Progr ess M onit or Volt age Reference Select
Q uiescent D C voltage select at AOUT.
0 = 1.5 Vdc . (Defau lt)
1 = VCC/2 Vdc.
CMTXG
0x10[3:2]
W T ransmit Path Gain Setting
00 0 dB (for TBS full swing, AOUT =1.08 Vpk) (Default)
01 -6 dB
10 -12 dB
11
MUTE
CMRXG 0x10[1:0]
W Receive Path Gain Settin g
00
0 dB (for RBS full swing, AOUT =1.08 Vpk) (Default)
01 -6 dB
10 -12 dB
11
MUTE
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 41
7 Clock and S am ple R ate Man agemen t
The H ost-S i de Devic e has an on-c hip c r ys tal osc ill ator , pr esc aler and PLL/NCO to all ow a choic e of a wide
range of s ample r ates and crystal choi ces . N ote the following acronyms are used in thi s s ection:
FS Sampling frequency
NCO Numerically-Control led Os cillator
7.1 Clock Generation with HIC (73M1902)
The clock generat ion for the entire c hip c onsists of c r ys tal osc illat or , Pr esc aler NCO , NCO based PLL and a
clock divider as shown in Figure 13.
PLL
Prescalar
NCO
Xtal
Oscillator
OSCIN
OSCOUT
M/SB
PwdnPLL
Sysclk
= 36.864 MHz
or Xtal Freq
XIB(1:0) 2
FrcVco
4608 Fs= 36.864 MHz
Fref
Figure 13: Clock Generation Block Diagram (assumes 8 kHz sam ple rate)
7.2 C rystal O sc il l at or
The crystal osci l lat or is desi gned to oper ate with a wide c hoic e of crystals (from 9 MHz to 27 MHz ) . It is a
com m on source configuration with current source loading to reduce power consumption. The current
source levels are configurable in 4 steps by using the XIB bits ( Register 0x0F[3:2]) for optimum power
performan ce. On reset th e oscil l ator runs at its full current level. The Host can then step down the current
level by setti ng the XIB bi ts t o an app r opr iate value that is adequate to achieve s table oscillati on with
mi nimal EM I gener ation.
OSCIN
OSCOUT
XIB(1:0)
Figure 14: Cry stal Oscillator with Configurable Loa d Current
Table 5: C rystal Oscillator Lo ad Cu rren t versu s XIB
XIB
Load Current
00 120 μA
01 180 μA
10 270 μA
11 450 μA
73M1822/73M1922 Data Sheet DS_1x22_017
42 Rev. 1.6
7.3 P LL Pr es caler
The pr esc aler c onverts the crystal osc i llator freq uency, Fxtal, to a convenient frequ ency t o be used as a
reference frequency, Fref, for the PLL. A set of three numbers must be entered through the s er ial por t –
PDVSR (5 bit), PRST (3 bit) and PSEQ (8 bit) as follows:
Fxtal
mux
count ctrl
overflow
Counter
Pdvsr
Pdvsr + 1
Sequence
Register Rst
Sequence
Counter
Fref
Pseq] Prst
Figure 15: Prescaler Block Diagram
PDVSR = Integ er [Fref/Fxtal];
P RST = Denominator of t he rat io (F r ef/Fxtal) minus 1 wh en it is expr ess ed as a ratio of two smallest
integer s = N nco1/Dnco1;
PSEQ = Divide Sequence
The pr esc aler s hou l d b e designed such that the output frequency, Fref, is in the range of 2 ~ 4 MHz.
7.4 PLL Circuit
Figure 16 i llustrates a block diagram of t he on -chip PL L ci r cui t.
The architecture of the 73M1x22 requires that the PLL output frequency, Fvco, be rel ated to the sampling
rate, Fs, by Fvco = 2 x 2304 x Fs. The NCO must function as a divider whose divide ratio equals Fref/Fvco.
Just as in the N CO presc al er , a set of three numbers must be entered throug h a serial por t to affect this
divide – NDVSR (7 bits), NRST (3 bits) and NSEQ (8 bits) as follows:
NDVSR = Integer [Fref/Fxtal];
NRST = Denominator of the rati o ( Fvco/Fref ) , D nco1, minus 1, when it is expres sed as a rati o of two
smallest integer s = Nnco1/D nco1;
NSEQ = Divide Sequence
VCO
Kvco
NCO
Prescaler
PFD Charge
Pump
NCO
Kd
Up
Dn
R1
C1 C2
Ichp Control 33
Fref
Kvco Control
PLL output =36.864 MHz
Figure 16: PLL Bl ock Diagram
Upon the system reset, the s ys tem cl ock is equal t o Fxtal/9. The system clock will r emain at F xtal unti l th e
hos t forces the tr ansi ti on no sooner the second Fr ame Synch peri od after the wri te to R egister 0D. W hen
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 43
this happens, the system clock will transition to PLLclk without any glitches through a specially designed
de-gl i tch m ux.
The fol lowin g tables show the register values f or several common c lock or crystal frequencies and sample
rates . By us i ng these tabl es, c om puti ng the values for the r egister s is not neces sary in most cas es.
Table 32: Clock Generation Register Settings for Fxtal = 27 MHz
Bit,
Reg Address
Fs (kHz) PSEQ
0x08
PRST,
PDVSR
0x09
ICHP,
KVCO_H
0x0A NDVSR
0x0B NSEQ
0x0C NRST
0x0D Ichp
(μA) KVCO
(2:0)
7.2
0xDA 0xEF 0x20 0x13 0x10 0x04 8 0
8.0
0xDA 0xEF 0x31 0x15 0x04 0x02 10 1
9.6 0xDA 0xEF 0x32 0x19 0x1A 0x04 10 2
12.0 0xDA 0xEF 0x24 0x20 XX 0x00 8 4
14.4
0xDA 0xEF 0x46 0x26 0x14 0x04 12 6
16.0
0xA4 0xE9 0x17 0x19 0x1A 0x04 6 7
Table 33: Clock Generation Register Settings for Fxtal = 24.576 MHz
Bit,
Reg Address
Fs (kHz ) PSEQ
0x08
PRST,
PDVSR
0x09
ICHP,
KVCO_H
0x0A NDVSR
0x0B NSEQ
0x0C NRST
0x0D Ichp
(μA) KVCO
(2:0)
7.2
XX 0x0A 0x10 0x0D 0x02 0x01 6 0
8.0 XX 0x0A 0x11 0x0F XX 0x00 6 1
9.6 XX 0x0A 0x22 0x12 XX 0x00 8 2
12.0
XX 0x0A 0x14 0x16 0x02 0x01 6 4
14.4
XX 0x0A 0x26 0x1B XX 0x00 8 6
16.0
XX 0x08 0x17 0x18 XX 0x00 6 7
Table 34: Cloc k Generatio n Regi st er Set t in gs for Fxtal = 9.216 MHz
Bit,
Reg Address
Fs (kHz ) PSEQ
0x08
PRST,
PDVSR
0x09
ICHP,
KVCO_H
0x0A NDVSR
0x0B NSEQ
0x0C NRST
0x0D Ichp
(μA) KVCO
(2:0)
7.2 XX 0x04 0x20 0x0E 0x14 0x04 8 0
8.0 XX 0x04 0x31 0x10 XX 0x00 10 1
9.6 XX 0x04 0x32 0x13 0x10 0x04 10 2
12.0
XX 0x04 0x24 0x18 XX 0x00 8 4
14.4
XX
0x08
0x66
0x39
0x1A
0x04
16
6
16.0 XX 0x03 0x17 0x18 XX 0xC0 6 7
73M1822/73M1922 Data Sheet DS_1x22_017
44 Rev. 1.6
Table 35: Clock Generation Register Settings for Fxtal = 24.000 MHz
Bit,
Reg Address
Fs (kHz) PSEQ
0x08
PRST,
PDVSR
0x09
ICHP,
KVCO_H
0x0A NDVSR
0x0B NSEQ
0x0C NRST
0x0D Ichp
(μA) KVCO
(2:0)
7.2
0xDA 0xEF 0x30 0x 5 0x1A 0x04 10 0
8.0
0x02 0x2C 0x31 0x13 0x10 0x04 10 1
9.6 0xDA 0xEF 0x42 0x1C 0x1E 0x04 12 2
12 0x08 0x66 0x14 0x0E 0x14 0x04 6 4
14.4
0x54 0xCA 0x46 0x1C 0x3E 0x05 12 6
16.0
0xA4 0xE9 0x17 0x1C 0x1E 0xC4 6 7
Table 36: Cl ock Genera ti on Register Settings for Fxt al = 25.35 MHz
Bit,
Reg Address
Fs(kHz) PSEQ
0x08
PRST,
PDVSR
0x09
ICHP,
KVCO_H
0x0A NDVSR
0x0B NSEQ
0x0C NRST
0x0D Ichp
(μA) KVCO
(2:0)
7.2 0x92 0xF4 0x50 0x1A 0x06 0x02 14 0
16 0x40 0xCA 0x17 0x1D 0x02 0xC1 6 7
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 45
7.5 PLL System Timing Control
Table 48 des cri bes the regis ters used for PLL system timing contr ol .
Table 37: PLL Syste m Timing Contro ls
Function
Mnemonic
Register
Location Type Description
PSEQ 0x08[7:0] W Sequence of the divisor. If PRST=0, this register is ignored.
PRST 0x09[7:5] W Rate at which the sequence register is r eset.
PDVSR 0x09[4:0] W Divisor value. D efault is 01111 .
ICHP 0x0A[7:4] W The sizes of the charge pump current in the PLL.
KVCOH 0x0A[2:0] W
The magnitude of KVCO associated with the VCO within PLL.
The fol lowin g table shows proper KVCOH values per each
desired PLL VOC frequency.
KVCOH2 KVCOH1 KVCOH0 Fvco Kvco
0 0 0 33 MHz 38 MHz/V
0 0 1 36 MHz 38 MHz/V
0 1 0 44 MHz 40 MHz/V
0 1 1 48 MHz 40 MHz/V
1
0
0
57 MHz
63 MHz/V
1 0 1 61 MHz 63 MHz/V
1 1 0 69 MHz 69 MHz/V
1 1 1 73 MHz 69 MHz/V
NDVSR 0x0B[6:0] W Divisor valu e. If NRST=0 , t his r egister is ignored.
NSEQ 0x0C[7:0] W Divisor s equence.
LOKDET 0x0D[7] R P hase Lock ed Loop Lock Detect
0 = PLL i s not locked. (D efaul t)
1 = PLL i s lock ed to PC LK.
CHNGFS 0x0D[3] W Sample R ate C hang e Sequen ce Enabl e
0 = No Fs change sequence generated. ( D efault )
1 = F s ch ange sequence is enabl ed.
S etti ng thi s bit to 1 m i nimizes the barr ier power loss period
duri ng the sample rate c han ges. This bit is r ecommended to
be s et to 1 for the applications requiring d ynamic sample rate
changes such as V.34 and V.90 m odems, etc.
NRST 0x0D[2:0] W Repr esents t he rat e at wh ic h the N CO sequen ce regis ter is
reset.
73M1822/73M1922 Data Sheet DS_1x22_017
46 Rev. 1.6
8 MAFE Serial Interfa ce
The serial data port is a bi-d i r ectional port that i s sup port ed by most hos t pr oces sors. Th i s is a simple fou r-
wire inter face c onsi sting of a clock , frame sync, data i n an d data out. Th e typical I2S ( Inter-IC Sound, NX P
semic ondu ctor) bus c an b e easily convert ed into a MAFE-comp atib l e interfac e. Alt hou gh the 73M1x22 is a
peri pheral to the host proces sor, the device c an b e ei ther a mast er or sl ave to the hos t. The M/S pin
dictates what is in control of the seri al port. If t he M/S p in is a logic 1 (d efaul t) , the device is the master; i f a
logi c 0, then it is a sl ave.
The 73M1 x22 chip set c an be configured t o use one of two framing m odes. Th e act ive low frame
synchronization (FS) signal is pin config urable by the TYPE pi n. Wh en the TYP E pin is unc onnected or
pulled up to l ogic “ 1” (mode 1 ) , an ear l y FS is generat ed in the bit c loc k prior to the fir st data bi t transmi tted
or received. When thi s pi n is pulled down to ground (mode 0), a lat e FS oper ates as a chip sel ect; the FS
si gn al is active fo r all bi ts that are tr ansmitt ed or r ecei ved. Th e TYP E i np ut i s s am pled dur i ng the device
res et and is ignored at all other ti mes. The final state of the TYPE pi n as the TEST! pi n is de-asserted
determines the frame syn chr onizati on mode us ed. In master mod e, FS is an output and gener ated b y t he
MicroD AA at the frame sync ( or sample) rate, Fs. In dai sy chain/s l ave mode, r egardless of the typ e, the
mast er device will only support ear l y mode. Th e sl ave device c an be of either an early or late t ype. F or
every data F s, 16 bit s are transmit ted and 16 b i ts are r eceived.
The standard 73 M 1822 device s up por ts the late frame sync mod e only. If a need for a frame sync
early mode is r equired, contac t the Teridi an Mark eti ng depar tmen t for details.
8.1 Data and Control Frame Formats
The serial bit stream of a data frame from the SDO UT pin ar e defin ed as follo ws:
Bit 15 Bi t 1 4 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3
RX2
RX1 RX0
Figure 17 shows data and c ontrol frames with early and late frame synch.
TX15 TX12 TX11 TX10 TX9
TX13 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1TX14
RX15 RX12 RX11 RX10 RX9RX13 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0RX14
Data Frame With Early/Late Frame Sync
R/W A4 A3 A2 A1A5 A0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0A6
zero zero zero zero zerozero zero DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0zero
Control Frame With Early/Late Frame Sync
SCLK
SCLK
FS(early)
SDIN
SDOUT
SDIN
SDOUT
FS(early)
FS(late)
FS(late)
CTL/TX0
Figure 17: Serial Port Timing Diagram
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 47
I f the H C bit (Register 0x02[0]) is r eset to 0 (defaul t) , CTL ( Bi t 0 of TX data) is used for the host to request a
contr ol frame. The 16-bit seri al data bit stream received on the SDI N is defined as foll ows:
Bit 15 Bit 14 Bi t 1 3 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 CTL
If the CTL bit in the TX data stream is set high by the h ost, a control frame will be initiated before the n ext
data frame. A control frame all ows the host c ontr ol ler to read or wri te stat us and control to the 73M1x2 2.
I f the H C bit (Register 0x02[0]) is set to 1, a control frame is init iated between every pai r of data frames.
The 16-bit seri al data bi t st r eam rec ei ved on the SDIN i s defined as follows:
Bit 15 Bi t 1 4 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
I n both cases, Bi t 15 i s transmitt ed/r eceived fir st in ti me. Bi ts RX[15:0] are the r ecei ve c ode word. Bi ts
TX[17:0] are the tr ansmit code word.
The serial bit stream of a control frame on the SDIN pin is defined as:
Bit 15 Bit 14 Bi t 1 3 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
The serial bit stream of a control frame on the SDOUT pin is defined as:
Bit 15 Bit 14 Bi t 1 3 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
I f the R /W ( Bit 15 of t he control word) bit is set to a 0, th e data byte transmi tted on the SD OUT pi n is al l
zer os and the data r eceived on the SDI N pin i s written to the regis ter pointed to by the received ad dr ess bits
(A6-A0). If the R/W bi t i s set to a 1, there is no write to any regi ster and the data byte transmitt ed on the
SDOUT pin is the data contained in the register pointed to by address bits A6-A0 . Onl y one control frame
can occ ur bet ween any two data frames.
8.2 Data and Control Frame Timing
Figure 18 i llustrates data and control frames ti ming of 8 kHz s am ple rate.
SCLK
FS
SDIN
SDOUT
TX TX TX TX TX 1
RX RX RX RX RX RX
T
R
X
X
RA A DI DI DI
000 DO DO DO
A
0
I
O
TX TX TX TX TX 0
RX RX RX RX RX RX
T
R
X
X
8 KHz
Data Frame Control Frame Data Frame
Figure 18: Data and Control Frames Timing Diagr am
The positi on of a control data frame is contr ol led by t he SPOS bit (R egister 0x02[1]). If SPOS is zer o, the
contr ol frames occ ur midway b etwe en data frames, i .e., the time bet ween data frames ar e equal. If SPOS
is set to 1, the contr ol frame i s ¼ of the w ay between consec utive data frames , i .e., the c ontr ol frame is
cl oser to the fi r st data frame. This is illustrated in Figure 19. The SPOS bit has no effect i n Slave or Daisy
Chain mo de
73M1822/73M1922 Data Sheet DS_1x22_017
48 Rev. 1.6
SPOS = 0
SPOS = 1
CONTROL FRAMES
DATA FRAMES
Figure 19: Control Frame Position ver sus SPOS
The SDOUT and FS pins change values following a rising edge of SCLK. The SDIN pin is sampled on the
falling edge of SC LK.
8.3 Serial Clock Operation
SCLK is a continuous clock running at 256∗Fs (Fs = Sample rate frequency). On the 32-pin versi on of
73M1922, the SCKM (Pin 14), which is weakly pulled high internally, can be connected to ground to stop
the SCLK after 32 clock cycles. Th is is illustrated in Figure 20.
The 73M1822 and 73M1922 20-pin TSSOP packages only support the continuous SCLK
configuration.
Table 38: Behavior of SCLK under SCKM
SC KM Pin Number of SCLK Cy cles before Being S hut Off
High Continuous
Low 32
SCLK and FS in Mode 1 (early FS)
SCLK
FS (Mode1)
32 Cycles of SCLK
SCLK and FS in Mode 0 (late FS)
FS (Mode0)
SCLK 32 Cycles of SCLK
Figure 20: SCLK and FS w ith SCKM = 0
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 49
8.4 MicroDAA IN Master/Slave Configuration
The 73M1x22 can be configured as a Slave by resetting the M /S pi n to 0. In t hi s m o de , FS of the sl ave
device(s) becomes an i nput from FSD output of t he Master or pr evious slave device. FSD is FS delayed by
16 SCLK cycles. This delay can be adjusted between 16 and 32 by setting the SCK32 bit (Register 0x01[1]
bit for the num ber of total devices less than or equal to 4. For mor e slaves , the SCK32 bit shoul d be r eset.
Th is is illustrated in Figure 21 and Figure 22. FSD is alw ays of Late Typ e ( or “ Framed”).
HOST
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
73M1902
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
(Slave)
(Master)
TYPE
M/S"1"
"1"
FS
SCLK
SDIN
SDOUT
MCLK
73M1822/
73M1902
MODE "1"
TYPE
M/S"0"
"0"
MODE "X"
HOST
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
73M1902
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
(Slave)
(Slave)
TYPE
M/S"0"
"0"
FS
SCLK
SDIN
SDOUT
73M1822/
73M1902
MODE "X"
TYPE
M/S"0"
"0"
MODE "X"
Note: Gray signals are optional pins depend on package type.
Figure 21: Example Connections for Master and Slave Opera ti on
FS
128 cycles of sclk
SCLK
FSD(Master)
and FS(Slave)
Data Frame Control Frame
128 cycles of sclk
16 cycles of
sclk 16 cycles of
sclk
if requested by bit0 of SDIN (Slave)
if requested by bit0 of SDIN(Master)
Figure 22: Mas t er/Sl av e Serial Ti m in g Di ag ram
8.5 73M1x22 Reset
The 73M1x22 ca n be ini ti alized to a defaul t state by p ulli ng the RST pin low for 100 ns or longer. The
device will be ready within 100 μs after the removal of reset pulse. The M/S pin is used to provide reset in
t he 73M 1822 and 72 M1 902 20-pi n TS SOP pack aged par ts. Th e r eset s i gn al is als o bi-d i r ecti onal and edge
t r i gg er ed, so either a low-to-high or high-to-low t r ansiti on wil l generate a reset. Ensure the fi nal state of M/S
is the master or slave mod e that i s des ired. M /S is used as follows:
Slave Mode
Transi ti on the M/S pin hi gh to low after the power s up ply has reached the minim um VDD l evel. If active
res et signal is used on power up, only a hi gh-to-low trans i ti on is needed ; if a reset is needed after power up,
a low-to-high-to-low toggle of M/S is used. Th e seri al port shoul d be ignored during this time.
Master Mode
Transi ti on the M/S p in low to hi gh. Th e tr ansition from low to hi gh shoul d be after the minim um VDD l evel i s
reac hed. If an active reset sign al is used on power up only a low-to-high transition is needed; if a reset is
needed after power up, a high-to-low-to-high toggle of M/S is required. The serial port should be ignored
during this time.
73M1822/73M1922 Data Sheet DS_1x22_017
50 Rev. 1.6
8.6 73M1x22 in Daisy Chain Configuration
A n internal regi ster control s the daisy c hain mode. FS pin of a slave devic e is an input from the FSD pin of
the preceding device. In this arrangement, the HC bit (Re gi s te r 0x02[ 0]) is i gnored and the Softwar e control is
automati cally enabled. Setting CTL ( bit 0 of the SDIN data st r eam) to 1 does the control frame request. The
delayed FS, FSD, is fed to the subs equen t slave d evice as FS. FSD is delayed from FS and always 16 SCLK
peri ods wide. There are 256 SCLK pulses between frame sync s. A maximu m of 7 slaves can be suppor ted.
To aid the host in id enti fying the master data frame, the leas t signific ant bit of the 16 -bit word (from SDOUT)
from the master can be forced to “1” and the l east s i gnific ant bit of the 1 6-bit word from the slave(s) to “0”
by controlling the MSID bits (Register 0x01[2]) of eac h device. In the cascade m ode, the number of slav es
supported must be specified in the NSLAVE bits (Register 0x01[6:4]).
It is important to note that slave dev ices OSC IN comes from the SCLK pin of the M aster device. I f a device
is configu r ed as a Sl ave (M/S= 0) , the internal PLL is automat i cal l y progr ammed for the corr ect operation
regardless of the external PLL programming. Figure 23 and Figure 24 ill ustrate the daisy c hain
configuration.
HOST
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
(Slave0)
(Master)
FS
SCLK
SDIN
SDOUT
MCLK
SCLK
FSD
FS
OSCIN
SDIN
SDOUT
(Slave1)
73M1902
73M1822/
73M1902
73M1822/
73M1902
TYPE
M/S"1"
"1"
MODE "1"
TYPE
M/S"0"
"0"
MODE "x"
TYPE
M/S"0"
"0"
MODE "x"
Gray pins are optional depending on the package type.
Figure 23: Daisy Chaining a Mast er and Two Slaves
FS
128 cycles of sclk
SCLK
FSD(Master)
andFS(Slave0)
Data Frame Control Frame
128 cycles of sclk
16 cycles of
sclk 16 cycles of
sclk
If requested by setting t he CT L(bit0 of SDIN str eam ( Master) )
16 cycles of
sclk
FSD(Slave0)
and FS(Slave1) 16 cycles of
sclk
Figure 24: Timing Diagram with One Master and Two Sl aves
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 51
8.7 MAFE Configuration Registers
The 73M1 x22 al lows MAF E control frame generat i on vi a software control or aut omat ically by t he hardwar e.
Us i ng the so f t ware -con tr ol led c ontr ol frame, hos t r esources can be saved by rem oving the redundant
contr ol frame generated by the har dware control .
Function
Mnemonic Register
Location Type Description
SPOS 0x02[1] W SPOS
0 = C ontr ol frames occ ur half way between data frames. (Default)
1 = C ontr ol frames occ ur after one quart er of the ti me b etwe en d ata
frames has elaps ed.
HC 0x02[0] W Hardware Con tr ol led Contr ol Frame E nable
0 = Contr ol frame i s under host s oftwar e control, the lsb of SDIN data
str eam b ecomes a c ontr ol frame request bi t and control frames
happen onl y on requ est. The actual value of bit 0 of SD IN data stream
is forced to 0. (Default)
1 = Contr ol frame generat i on is und er hard ware c ontr ol , bit 0 of SD IN
data str eam becomes bit 0 of the transmit word and control frames
occur automat i cally a fter every data frame.
8.8 Slave Registers
The 73M1x22 allows a daisy chain of up to seven slave devices on the same bus. In this configuration, only
one devic e on the bu s can be a mas ter and the rest are sl aves.
Function
Mnemonic Register
Location Type Description
DSYEN 0x01[7] W Daisy Ch ain Configuration Enable
0 = Dis ab le Daisy Chain.
1 = Enable Daisy Chain .
NSLAVE
0x01[6:4]
W
Num ber of Sl aves in Daisy Chain Mode
S peci fies the num ber of slaves support ed. The maximu m number is
7. Ther e ar e tw o default values. The default in M aster M ode is 000.
The default in Slave Mod e is 001.
MSIDEN 0x01[3] W Master/Sl ave Identi fication Enab l e
When enabled in a dais y chain c onfig urat i on, the MSID control bit
forces the l east s i gn i fi cant bi t of t he S D OU T data s tream.
0 = MSI D featur e disabled.
1 = MSID feature enab l ed. ( D efaul t)
MSID 0x01[2] W Mas ter /Slave Identific ati on
When MSIDEN = 1, in a daisy chain configuration (DSYEN = 1), this
bit al l ows selecting the value of bi t 0 of the SDOUT data stream.
0 = The least significant bit of SDOU T is forced to 0.
1 = Th e l east s igni ficant bit of SD OUT is forced to 1. (Default)
I f DSYEN = 0, MSID has no im pact on the least signi fi cant bi t of the
S DOUT d ata stream. ( Default)
SCK32 0x01[1] W Daisy Ch ain FSD Latency Control
0 = FS to FSD delay is 32 SC LK periods. (Defaul t)
1 = FS to FSD delay is 16 SCLK periods. This bit must be set when
t here are four or more s lav e devices .
When a master i s dri ving a sl ave, only E ar ly Type i s al lowed.
73M1822/73M1922 Data Sheet DS_1x22_017
52 Rev. 1.6
9 Signal Processing
9.1 Transm i t P ath S ig n al Pro cess ing
9.1.1 General Description
I n the transmit path, data i s fir st s ent by t he h ost DSP through a seri al inter fac e to the 73 M1 822 / 73M 1922
t hen interpol ated by a transmit interpolat ion fil ter, seri alized and tr ansmitt ed across to the Line-S i de Device,
whic h is float i ng r el ative to the H ost-S i de Device ea r th ground. The data r eceived on the Line-S ide Device
is the n de-serializ ed and dig itally sigma-del ta modulated to a one-bi t data stream of 1.536 M bps (for a
sam ple frequency of 8 kHz). The signal is further filter ed firs t by a switched capacitor fil ter and then a
continuous anti-aliasing circuit.
The frequency response and bandwidth of the transmit path is dependent on the sampling frequency (Fs).
Fi gur e 22 and Figur e 23 show the normaliz ed frequ ency respon se of t he tr ansmit path. F or Fs = 8 kHz, th e
0.2 dB pass-band ripple frequency is from DC to 3.422 kHz. The 3 dB bandwidth is 3.65 kHz.
9.1.2 T otal Transm it Path Resp onse
012345678
100
90
80
70
60
50
40
30
20
10
0
10
Transmit Path Over all Freque ncy Response
Freq(kHz)
Gain (dB)
10
100−
composite x( )
80 x 16⋅
com
iplo
xou
xou
Figure 25: Transmit Path Overall Frequency Response to Fs (8 kHz)
0 0.5 1 1.5 2 2.5 3 3.5 4
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
Transmit Passband Re sponse
Freq(kHz)
Gain (dB)
1.
1.0−
composite x( )
40 x 16⋅
Figure 26: Pass-Band Re sponse of the Tr ansmit Path
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 53
9.1.3 73M1x22 Transmit Spectrum
Figure 27 shows t he tr ansmit spectrum observed on the l i ne from dc t o 32 kHz for a sample frequency (Fs)
of 8 kHz. The transmit signal is band-limi ted ( by default) to Fs/2=4 kHz and is flat ( with 0.2 dB r i pple) to
3.65 kHz and is marked as Txdb(x) in the figure.
A ls o shown, and m ar ked as signaldb(x), i s the baseband sig nal from 1 kH z t o 2 kHz. The aliases of
si gn al db(x) are s hown as al iasdb ( x) and ar e attenuated signific antly with better than 80 dB attenuati on at 8
kH z, better than 60 dB at 16 kHz, better than 100 dB at 24 kH z, etc.
0 4 8 12 16 20 24 28 32
140
120
100
80
60
40
20
0
20 Transmit Spectr um
Freq
Spectrum (dB)
20
140−
signaldb x( )
aliasdb x( )
Txdb x( )
320 16x
Figure 27: Transmit Spectrum to 32 kHz
9.2 R eceiv e Path Signa l Pr oc es sin g
9.2.1 General Description
I n the recei ve path, the s ignal from t he tel eph one line is in put to the anti-ali asi ng filter and passed through a
sel ectabl e low pass ( notch) fi l ter , which can be used to attenuate in-band Bill ing Tones. Th e analog s ignal
is digiti zed by a sigma-delta analog to digital converter. The resulting high frequency one-bit data stream is
dec i mat ed and sent to the Host-Side Device v ia t he b ar r i er . Another decimati on FIR fil ter in the H ost-Side
Dev ic e filt er s the r eceived data and sends it to the host DSP for proces si ng.
The frequ ency respon se and band width of the receive path is dependent on the sampling frequency (Fs).
Figure 28 and Figure 29 show the nor mali zed frequency res ponse of t he receive p ath, i ncluding the effect of
the decimation filter in the 73M1902/73M1822 HIC.
For Fs = 8 kHz, the 0.2 dB pass -band ripple frequency is from DC to 3.342 kHz. The 3 dB bandwidth is
3.56 kHz.
73M1822/73M1922 Data Sheet DS_1x22_017
54 Rev. 1.6
9.2.2 T otal Receive Path Response
Figure 28: Overall Frequency Response of the Receive Path
Figure 29: Pass-band Response of the Ove r all Rec eive Path
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 55
9.3 Signal Control Functions
Table 39: Signal Control Functions
Function
Mnemonic Register
Location Type Description
TXBST 0x14[7] WO Transmit Boost
Used in conjunction with DAA to manage transmit level. If set to 1,
Transmit signal is increased by 6 dB. S ee Section 9.3.1.
DAA 0x14[6:5] WO DAA Tx Gain
Us ed in c onjunct i on with TX BST to manage tr ansmit level. See
Section 9.3.1.
RXBST 0x14[3] W Rec eived Boost
If set to 1, Receive signal is increased by 20 dB.
Default is 0.
RXG 0x14[1:0] WO R eceive Gain
S ets the receive path gain/attenuation. See Table 41.
TXEN 0x16[7] WO T ra ns mit Pa th Enabl e
1 = Enable Transmit Path.
0 = Dis ab le Trans mit Path. (Default)
RXEN 0x16[6] WO Receive Path Enable
1 = Enabl e Receiv e Path.
0 = Dis able Receive Path. (Defau lt )
9.3.1 T ransmit and Receive Level Contr ol
O n the tr ansmi t side, 0 dBm tr ansmi t pr ogrammi ng at the M AFE interface result s i n ~0 dBm on the line. On
t he recei ve s ide, 0 dBm r ecei ve signal on the line r esul ts in ~ 0 dBm at the MAFE interface.
On the transmit side there are three bits to adjust the transmit level: TXBST (Register 0x14[7]), DAA(1:0)
(Register 0x14[6:5]).
Table 40: Transmit Gain Control
TXBST
DAA1
DAA0
Gain, nom.
Units
0 0 0 +2.0 dB
0 0 1 0.0 dB
0 1 0 -4.0 dB
0 1 1 -8.0 dB
1 0 0 +8.0 dB
1 0 1 +6.0 dB
1 1 0 +2.0 dB
1 1 1 -2.0 dB
73M1822/73M1922 Data Sheet DS_1x22_017
56 Rev. 1.6
On the receive side, there are two RXG bits RXG(1:0) (Register 0x14[1:0]) to c ontr ol the receive gai n. The
RXG bits need to be set to 00. When the r eceived l ine s ignal exceeds the voltage specified in ITU-T
Recommendation G.712 (2001), the recei ve gain must be redu ced to prevent s aturat i on an d cl i pping wit hin
t he recei ve s ignal pro c e ss i ng pa th.
Table 41: Receive Gain Control
RXG1
RXG0
Gain nom
Units
0 0 0.0 dB
0 1 +3.0 dB
1 0 +6.0 dB
1 1 +9.0 dB
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 57
10 Barri er Information
10.1 I sol at i on Bar r i er
The 73M1 x22 uses the Teridian Mi croD AA prop r ietary isolation method b ased upon low cost pulse
t r ansformer coupling. This tec hnique provides several advantages ov er other methods, including l ower
B OM cos t, redu ced c om ponent count, and s ignifi cantly enhances com mon mode nois e i mmuni ty, lower
radi ated noise ( EM I) , and improved operation in n oi sy en viron ments. The MicroDAA tec hnology h as
additional and enhanced functionality such as the support of powering the Line-S ide DAA cir cuit from the
Host-Si de Device. This all ows operation on leased lines c ircuits and on l ow current c ond i ti ons commonly
enc ounter ed in long loops . The Mi croD AA can al so oper ate enti r ely from li ne power wh en suffic ient loop
current is available.
S inc e the tr ansformer is the on l y c omp onent cross i ng the i sol ati on bar r ier, i t solely deter mines th e is ol ation
between the PSTN and the 73M1x22 digital interfac e. Several vendors can s upp l y c omp ati ble transformer s
with ratings up to 6000 V.
10.2 B ar ri er Po w ered Opti o n s
The 73M1x22 has the ability to be used either in a Line Powered Mode or one where the Line-Side D evice
can be powered across the barrier fr om the Host-Side Device. The power on default for the 73M1x22 is
B ar r ier Powered Mode.
10.2.1 Barrier P ow er ed Operation
In this default mode of operation the 73M1x22 Host-Side Device drives the puls e transformer in suc h a way
t hat powe r puls es are ti me d ivision mult iplexed into the transmit b it stream (hal f the time) th at i s rectifi ed by
circuitry in the Line-Side Device and u ses thi s energy to power itself.
10.2.2 Line Pow ered Operations
If there is sufficient current available fr om the PSTN l i ne, the 73M1x22 can be pr ogr ammed to use li ne
power i nstead of ac ross the barr ier.
10.3 S y nchro niz at ion of the B arri er
S inc e the commun ic ati on across the bar r ier is di git al, synchronization of data acr oss t he b ar r i er is of
abs ol ute i m port ance. To that end, the devices implement spec i al procedur es to ens ur e r eliabili ty across the
barrier.
When l oss of synchr oniz ati on is detected, the SLHS bit is set to 1 and likewise SYN L is als o set to 1 and
ini ti ates an i nter r upt to the host. On ce the SYNL bi t is ass er ted a new barr ier s ynchroni zation sequence will
automati cally begin.
O nce read, the SLH S bit is reset , but will be set agai n if the syn chr onization loss continues.
73M1822/73M1922 Data Sheet DS_1x22_017
58 Rev. 1.6
Upon power up, the following sequence should be used to ensure barrier synchronization:
1. The Line-Side Device (7 3M1902) starts in Bar r i er Powered Mode an d tr ansmits a preambl e to ai d the
P LL loc king of the
Line-S ide Device.
2. When PLL Lock detect is achi eved, the Li ne-Side Device tr ansmits status data to the H ost-Side Device.
3. When the Line-S ide status Data i s detected by t he Host-Side Device, the barrier i s cons idered to be in
synchronization by the Host-S ide Device.
4. If the auto-pol l mode is enabled, the Devic e ID is transmit ted, wh ic h is followed b y t r ansmit data.
5. Upon detection of the D evice ID, the Li ne-Si de Device consider s the Bar r i er to be in s ync hron iz ati on in
host-to-lin e side direct ion .
6. Line-S i de Device starts s ending Receive D ata.
7. If the Auto-P oll bit is en abled, the Host-S ide Device will ha ve polled the Device ID of the Line-Side
Device. If the barrier is synchronized, then Register 0x1D[7:4], will be 1100. If not synchronized, then
0000.
10.4 Auxiliary A/D Converter
Line monitoring and sensing is performed with an 8-b i t auxiliary A/D converter i ntegrat ed in the
73M1922/73M1822. The input signals ar e connected to RGP and RGN pin s. In c ertain appl ic ati ons, this
A /D can b e used to sample s i gnals unrelated to PSTN DAA functions. In this type of applicat ion, it i s
nec ess ary to isolate the input s i gnal with op ti cal or other means since the 73M1x22 is c onn ected di r ectly t o
the PSTN and is susceptible to high voltage surge. Under normal con dit ions, RGP and RGN are AC
coupled to the line through high-voltage (250 V ) capac itors .
10.5 Auto-Poll
O nce the MSBI ac quires syn chr onizati on, the M SBI s tate m achi ne automatic al ly sends a polling comm and
t o the 73M1x12 LIC. M or e specifi cally, the H ost-Side Device (73M1902) requests that the Line-Side Device
(73M 1912) t r ansmits it s revision ID to the contents of Register 0x1D[7:4] in the 73M1902. The “revision ID”
part of t hat specific register i s cleared upon power up or up on l oss of sync hr onization. Aft er this au to-poll
sequence, the host should read Register 0x1D[7:4] and d eter mine if the “ r evision ID” fiel d is al l zer os or not.
I f it is not all zeros, this implies syn chronization is es tablished between the H ost-Side Device and Line-Side
Device.
The auto-po ll me c ha ni sm can be disable d by se t ti ng the ENAPOL bit (R egis ter 0x05[3]).
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 59
10.6 Barrier Control Functions
Table 42: Barrier Control Functions
Function
Mnemonic Register
Location Type Description
ENLPW 0x02[2] W Enabl e Line Power
0 = Barr ier Pow er ed M ode is sel ected. (Default)
1 = Lin e Powered Mode is selected.
Bit ENLVD must have the value of 0 before switching from Line
P owered M ode to Bar r ier Powered M ode. Otherwise level
detection is di sabl ed and the tr ansition to Barr i er Powered M ode
will not occ ur.
SYNL 0x03[1] R B ar r i er Sync hronization Loss
0 = Indi cates syn chronization of data ac r oss the barrier .
1 = Indi cates a l oss of synchronization of data across the barrier .
Thi s s tatus bit is r eset when read. Thi s is a maskable i nter r up t. It i s
enabled by the ENSYNL bit.
ENAPOL 0x05[3] W En ab le Automat ic Polling
0 = Dis ables automat i c polling.
1 = Initiates automatic polling of the 73M1x22 Line-S ide Device ID
upon the es tablishment of the barr ier SYN . (Defau lt)
I f SYN is los t, the D evice ID will be reset to 0000 .
ENSYNL 0x05[1] W Enable Synchronization Loss D etection Interr upt
0 = Dis ables Sync h Loss Det ection Inter r upt.
1 = Enabl es Synch Loss Detec ti on Interr up t. (D efaul t) Wh en the
73M1x22 detects a loss of synchronization in the Host-Side Barrier
Interface, SYNL 0x03[1] will be set and reset when read.
SLHS 0x0D[6] R Synchronization Loss Host Side
Thi s bi t i ndicates the st atus of t he Barrier Inter face as seen from t he
Host-Side.
0 = Host-S ide Barrier Interface is synchr oniz ed.
1 = Host-S ide Barrier Interface lost synchronization. (Default)
O nce read, the SLH S bit is reset , but will be set agai n if the
sync hronization l oss c onti nues.
DISNTR 0x15[6] WO Disable No-Transi ti on Timer
I f enabled, the No-Transition Timer is a safety featur e. If the bar r i er
fails, i.e. no tr ansiti on is detected for 400 µs, the Line-Side Devic e
res ets itself and g oes on hook t o prevent l ine hol ding in a failure
condition.
0 = Enables No-Transition Timer of 400 µs. (Default)
1 = Dis ab les No-Transi ti on Timer.
SLLS
0x1E[2]
W
Synchr o ni za t i o n Lo ss Li ne Si de
0 = TXRDY will continuously be generated following Synchronization
Los s s o as to all ow SLLS i nformation to be tr ansferred across the
barrier. This causes an au tomatic transfer of 1Eh. (Defau l t)
1 = Synchronization is lost in the Line-Side Device due to Header.
73M1822/73M1922 Data Sheet DS_1x22_017
60 Rev. 1.6
10.7 Line-Side Dev i c e Op er at in g M od es
The architecture of the 73M1x22 is unique in that the isolation barrier device, an inexpensive pulse
t r ansformer , is used to provide po wer and al so bi direc tional data between t he Host-Si de Device and the
Line-S ide Device. When the 73M1x22 is on hook, all the power for the Line-Si de Devi ce i s provided over
t he bar r ier i nter face. After the L i ne-Side Device goes off hook, the tel co line s upp l ies approximately 8 mA
to the Line-Si de Device whil e the h ost provides the remainder across the barrier . It i s also poss i ble t o
power the Line-Si de Device enti r ely from t he line provid ed ther e is at leas t 17 m A of loop curr ent available.
S etti ng the ENLPW bi t enables this m ode an d turns off t he power s up plied across the bar r i er . There is a
penalty in using this m ode in that th e noise and dynamic r ange ar e abou t 6 dB wors e than with the Bar r i er
P owered M ode. It i s therefore r ecommended that the Line Powered M ode b e r eserved for applications
where the absolute minim um power from t he h ost s id e is a pr iori ty and the reduction in performan ce c an b e
tolerated.
Figure 30 shows the AC and DC circuits of the Line-Side D evice.
Q5
MMBTA06
1
32
U2
73M1912
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
201
2
3
OFH
VND/VNX
SCP
MID
VPX
SRE
SRB VBG
ACS
VNS
VPS
RXP
RXM
TXM
DCD
DCE
DCBDCI
RGN
RGP
C23 2.2uF
R18 240
R9 8. 2, 1%
R10 5.1K
Q3
MMBTA42
1
32
R4 255, 1%
R4
100K, 1%
Q6
BCP56
1
23 4
RING
-+
BR1
HD04
4
1
3
2
Q4
MMBTA92
1
3 2
R2
10M
R7 5.1K
Q7
MMBTA42
1
32
R12 200
R3
412K, 1%
TIP
Figure 30: Line-Side Device AC an d DC Circui ts
The D C VI bit s cont r ol the voltage v er sus c ur r ent characteri stics of the 73M1 x22 by monit or ing the voltage at
the line divided down by the ratios of (R3+R4)/R4 (5:1) during off-hook and (R2+R4)/R4 (101:1) during on-
hook per iod measur ed at the D CI pin. This volt age d oes not include the voltage across the Q4 and the
bri dge. Wh en both the EN AC and ENDC bit s are set (the hold mode) , the D CVI charact erist ic s follo w
approximately a 50 Ω load li ne offset by a factor deter mined by the DCVI bits. If ENDC = 1 and E N AC=0, the
73M1x22 is in the seize mode and the D C voltage char acteri stic will be reduced to meet the Austral i an
sei ze voltage req uiremen ts regar dless of t he setting of the D C VI bi ts.
10.8 Fail-Safe Operation of the Line-Si d e D ev ic e
The 73M1x22 provides additional protection against improper operation during error and har mfu l external
events. These include p ower or comm un i cation failure with the Line-S ide Device and the detection of
abnormal volt ages and cur r ents on the l in e. The bas is of thi s protection is to ensure that under these
conditions the device is in the On-Hook state and the isol ati on is provid ed.
The following events will cause the 73M1x22 Line-S i de Device to go to the On-Hook s tate i f i t i s Off-Hook:
1. A Power-On Res et occ ur s wh i le O ff-Hook.
2. The non-transiti on ti mer function (see DISNTR) is tr iggered b y th e absence of an y signal t r ansitions for
more than 400 µs on the bar r i er interface, indicati ng a p r oblem wit h comm unicati ons.
3. The power supply to the Line-S ide Device is bel ow normal operating l evels.
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 61
11 Configurable Direct Access Arrangement (DAA)
The 73M1x22 line-side device integr ates most of the c i r cui tr y to implement a PSTN line inter fac e or DAA
t hat i s c apab l e of bei ng globall y c omp liant with a s ingle bill of mater i als. The 73M1x22 supports the
following DAA functions:
• Pulse d ialing
• O n and Off Hook s witc h control
• Loop current (DC-IV) regulati on
• Line im pe da nc e ma tching
• Ring detection
• Tip and Ring voltage polari ty rev er sal detection
• Billing tone rejection
• Trans-hyb r i d cancell ati on
The device is abl e to support Barr ier-powered m ode in which the PSTN loop curr ent may be as low as 8
mA.
11.1 P uls e Dial ing
The 73M1x22 supports Pulse Dialing. See Section 11.6 for the desc r iption app l icable contr ol and st atus
bits and Sec tion Error! Refe r enc e source not found. for a d esc r iption of a r ecommended pr ocedure.
11.2 DC Termination
DC Termination or Loop C urrent (DC-IV) regulation is managed by the 73M1x22 Line-Si de Device by
config uring the appr opriate register s. No add i ti onal c omp onents are neces sary.
The 73M1x22 provides a DC transconductance circuit that regulates the tip to ring voltage depending on the
DC cur r ent suppl ied by the line. There are four settings that c an be used to s et the voltage to curr ent r ati o.
Figure 31 shows t he DC-IV ch ar acteri stics of the 73M 1x22 with sp ecial regi ons of inter est.
V
I
41 Ω *
Programmable
Turn-on Voltage
Current Limit Turn-on=42 mA
2.2 kΩ
Current Limit Turned on
* ~50 Ω with 8 Ω fuse resistance
Seize Voltage
Figure 31: DC -IV Characteristics
73M1822/73M1922 Data Sheet DS_1x22_017
62 Rev. 1.6
The 73M1x22 ca n:
• S hift the characteri stics by s etti ng the tur n-on voltage.
• E nab l e a cur r ent lim i t of 42 m A.
The 73M1 x22 m eets a wid e r ang e of di fferent countr i es’ r equirements under software control. See Section
11.7.
There are two oper ati ng states for the DC-I V ci r cui ts: H old and Seize.
0
2
4
6
8
10
12
14
5
9
15
20
30
40
50
60
70
80
90
96
110
Tip/ Ri ng Vol tage
DC Current, mA
DCVI Performance
DCIV=00
DCIV=01
DCIV=10
DCIV=11
Figure 32: Tip-Ring Voltage versus Current Using Different DCIV Settings
The H ol d state is the nom i nal operati onal point for the DC-IV circuits. The response shown in Figure 31 is
for t he Hold state (both DC and AC t r ansconduct ance circui ts are enabled). Th e slope of the D C-IV
characteristics is approximately 50 Ω when the series resistance of a typical PPTC resettable fuse is taken
into acc ount.
The Sei ze s tate i s a condi ti on that i s used by some central offices t o deter mine an off-h ook c ond i ti on. In
t his state an addi ti onal load is added to the nom i nal operati onal DC -IV c haracter i stics us ed during the H old
state
I n the Sei ze s tate ( only the D C transc onductanc e cir cui t is enabled), the turn-on voltage i s reduced on the
line independent of the D C-IV control bits. See the des cription of the DCIV bit in Section 11.6.
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 63
A n example of the u se of t he Seize state is that of A ustral ia in wh ic h r equ i r es this stat for the first 300 ms
immediatel y aft er going off hook .
0
2
4
6
8
10
12
14
0
10
20
30
40
50
60
70
80
90
100
Tip/Ring Voltage
DC current, mA
DCVI Performance
DCIV=xx
Austral ian Not Recommended Region
Australian
Prohibi ted Regi on
Figure 33: Voltage versus Current in the Seize Mode is the Same for Al l DCI V Settings
To fac ili tate the quick cap ture of the loop, the bandwidth of the DC loop is high upon power up. On the
completi on of D C loop c aptur e, it should be lowered to avoid the interac tion of DC and AC loops. See the
description of the ENNOM bit in Section 11.6.
11.2.1 Current Limit Detection
I f the D AA C urrent Limiti ng feature is enab l ed an d the device detec ts a limi ted condi ti on, then a stat us bit is
set to give an indi cation of thi s event .
11.3 AC Termination
International DAA functionality is supported without any ext ernal termination components through the
following functions:
• E nab l e/Disable AC t erminati on ATEN bit at Register 0x16[4].
• S elec t AC ter minati on impedance us ing the ACZ bits at Register 0x17[4:3]
A CZ Active Ter mination L oop Settin g
00 = 600Ω (USA, Japan)
01 = 270Ω + 750Ω || 150nF (ETSI ES 203 021-2)
10 = 200Ω + 680Ω || 100nF (China)
11 = 220Ω + 820Ω || 115nF (Australia)
The AC impedance pr esented to the line c an be alt er ed as desc r ibed in the AC Termination Regist er
(Register 0x17) . Th is i s a par t of a feedbac k loop that mon itors the line and feeds an appropriate AC
current back to l i ne, suc h that the desired impedance looki ng int o the RXP pin ( of the 73M1 912 LIC) is
reali zed. Figure 34 s hows magnitude r esponse of t he impedance matchin g fi l ter for the cas e of ETSI ES
203 021-2. It is approximately equal to t he inverse of the frequ ency char acteri stics of the impedan ce bei ng
realized.
73M1822/73M1922 Data Sheet DS_1x22_017
64 Rev. 1.6
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
4
5
6
7
8
9
10 Fr e q Response of I PMF, AZ =01
kHz
10
0
F1db f 1000⋅( )
50 f
Figure 34: Ma gni tude Response of IPMF, ACZ=0 1 (ETSI ES 2 03 021-2)
11.4 Billing Tone Rejection
S ome countr i es use a large amplitude out-of-band tone to measur e call durati on to allow remote central
of fices t o deter mine the duration of a call for bill i ng purp oses. To avoid s aturat i on an d distortion of t he input
caused by th ese tones, it i s imp or tant to be able to reject them. Typi cal values of frequency are
12 kHz or16 kHz.
The 73M1x22 has an integrated notch filter that attenuates eit her of these tones. By enabling this filter and
selecting the position of the notch frequency such tones will be attenuated.
Figure 35 shows t he magni tude r esponse of t he filter with a notch at either 12 kHz or 16 kHz.
0 2 4 6 8 10 12 14 16 18 20
50
40
30
20
10
0
10
Spans 20kHz
10
50−
F1db f 1000⋅( )
F2db f 1000⋅( )
200 f
Figure 35: Ma gni tude Response of Bill i ng Tone Notch Filter
In addition to the notch filter, the 73M1x22 can indicate the presence of an overload condition when a line’s
AC voltage exceeds 3.5 Vpk.
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 65
11.5 Trans-Hybrid Cancellation
A Transmit Bi t Stream (TBS) emulati ng a sinusoid of 1 kHz, full scale (code wo r d of + /- 32,767) is applied to
S DIN and the r esidual s i gnal is measured a t SDOU T. Unless stated otherwise, test c ond i ti ons are: ACZ= 00
(600 Ω termination), THEN=1, ATEN=0, DAA=01, TXBST=0. TX M is external ly fed back into t he L i ne-Side
Dev ic e ( 73M1912) to effec t canc ellati on of transmit signal.
Table 43: Trans-Hybri d Cancellation
Parameter Test Condition Min Nom Max Units
Trans mit hybr id
cancellation M easure RxD in H IC 26 dB
O ffset volt age 50% 1’s Density 25 50 mV
AC s wing 1kHz sinusoid at Tip and Ring 0.85 0.95 1.05 Vpk
I dle noise 300 Hz – 4 kH z at Tip and Ring -81 dBm
11.6 Dir ect Acce ss Arra ng em ent C ont r ol Fun ctions
These Trans mit Contr ol Registers c ontai n control informat i on to set up the l ine s id e of the 73M1x2 2.
I ncluded ar e D C-IV ch aracteristics, off-hook control, et c.
Table 44: DAA Control Functions
Function
Mnemonic Register
Location Type Description
OFH
0x12[7]
WO
Off-Hook Enable
Thi s bi t control s the s tate of the Hook signal.
0 = On-Hook. (D efaul t)
1 = Off-Hook.
PLDM 0x13[3] WO P ulse Dialing Mode Enable
A lleviates the s tr ict timing requir ement s for the H ost having to c ontr ol
ENDC and OFH during pulse dialing. With PLDM = 1, the Host only has
t o toggle O FH to per form p uls e di al ing.
0 = Pu ls e Dialing Mode is disabled . (Default)
1 = Pul se Di aling Mode is enabl ed.
IDISPD
0x13[1:0]
WO
Discharge and P ulse Dialing
Controls the DC discharge current and how fast the loop turns off. Affects
pulse dialing waveform. Controls the amount of discharge current during
hook switch t ransitions.
0 = Minimum c urrent . (Default )
1 = Maximum cur r ent.
I t i s recommen ded to set IDISPD to 1 pr ior to hook s witching operations .
ENNOM 0x12[0] WO Enabl e N ominal Oper ati on
0 = Speeds up the on and off hook transitions tim e by increasing the DC
loop band width of the DC transc onductanc e ci r cuit in the 73M1x22. This
can be used for puls e diali ng. In addi tion, ENN OM =0 prevents the reset
of al l bit s in Reg ister 0x12 . (Default )
1 = Enter N ominal Oper ati on. R educes th e loop bandwidth of the DC
t r ansc ondu ctanc e cir cuit . Allows reset of Regis ter 0x12 caused by bits
UVDT, OVDT or OIDT.
73M1822/73M1922 Data Sheet DS_1x22_017
66 Rev. 1.6
Function
Mnemonic Register
Location Type Description
DCIV 0x13[7:6] WO D C Cur r ent Vol tage Characteristic C ontr ol
Hold state wit h ENDC and ENA C=1, 20 mA DC loop curr ent except i f the
DC-IV curve is s hifted to a value given by thes e bits. This as sumes that
t here is a 5:1 attenuati on of off-hook.
DCIV1
DCIV0
Description
0 0 DC Loop On Vol tage of 0.73V
(5.60 V at Tip/Ri ng ass uming a 5:1
step down of of f-hook vol tage)
0 1 DC Loop On Vol tage of 0.977 V
(6.75 V at Tip/Ri ng ass uming a 5:1
step down of of f-hook vol tage)
1 0 DC Loop On Vol tage of 1.232 V
(7.65 V at Tip/Ri ng ass uming a 5:1
step down of of f-hook vol tage)
1 1 DC Loop On Vol tage of 1.488 V
(9.35 V at Tip/Ri ng ass uming a 5:1
step down of of f-hook vol tage)
*sei ze s tate w i th ENDC = 1 and EN AC=0, 20 mA l oop curr ent.
xx=DC Loop On Voltage of 0.281V (3.9 V at Tip/Ri ng ass uming 5:1 st ep
down of off-h ook vo lt age)
Curre nt Limiting Detec tion Control and Status
ILM 0x13[5] WO Cur r ent Li mi t Ena bl e
Thi s c ontr ol enab l es or disables loop c urrent limi t.
0 = No current limit. (Default)
1 = 42 mA current limit enabled.
ILMON 0x1E[7] R Current Lim it Mode On
This status bit is effective only when the ILM bit is set to 1.
0 = Loop current is lower than 42 m A.
1 = Loop curr ent is hi gher t han 42 m A an d the curr ent l imi ti ng mode is
active.
THDCEN 0x13[4] W Enab les the can c ellation of AC signals within DCGM circuit
0 = Dis ab les AC can c ellation.
1 = Enabl es the c ancellation of AC from DCGM cir cui t.
ATEN
0x16[4] W Ac tive Termination Loop Enable
E nab l es or disables Active Ter mination L oop.
0 = Dis ab le. (Default)
1 = Enabl e Active Terminati on L oop.
Normal operation requires this bi t to be set to alwa ys enable a t er minati on
circuit.
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 67
Function
Mnemonic
Register
Location
Type Description
FSCTR 0x16[3:0] W Fi l ter Sample R ate Selec ti on.
S inc e impedance matching is done thru the use of a switc hed capacitor
filter, the r ealized impedance is exact onl y if Sample Rate F r equ ency (Fs)
matc hes to the Sample Rate spec ified i n FSCTR(3:0). When the actual
sample rate is not any one of the follo wings in the table, a settin g closest
t o the actual Fs should be chos en to m inim i ze mismat ching errors. These
setti ng wil l affec t both in AC Impedan ce Matching Fil ter ( IPM F) and
Rec eive r Low P ass Notch Fil ter ( RLPN) both.
Control Bits
Fs A ssumed ( kHz)
FSCTR3
FSCTR2
FSCTR 1
FSCTR 0
IPMF
RLPN
0 0 0 0
7.2 7.2
0 0 0 1
8 8
0 0 1 0
9 9.6
0 0 1 1
9.6 9.6
0 1 0 0
10.286 9.6
0 1 0 1
11.2 12
0 1 1 0
12 12
0 1 1 1
12.8 12
1 0 0 0
14.4 14.4
1 0 0 1
16 16
1 0 1 X
Not allowed
1 1 X X
Not allowed
ACZ 0x17[4:3] W Ac ti ve Ter mination L oop
Controls the selection of the active termination loops per t he table shown
below. ATE N must be s et to 1 for selection to be enabled.
ACZ Field Acti ve Term i nation Loop Setting
00 600 Ω (Default)
01 270 Ω + 750 Ω || 150 nF(ETSI ES 203 02 1-2)
10 200 Ω + 680 Ω || 100 nF (China)
11 220 Ω + 820 Ω || 115 nF (Australia)
APWS 0x17[7] W A nalog Power Save Enable
0 = Saves analog pow er i n L IC of 73M1 822 or 73M1912.
1 = Full analog power in LIC of 73M1822 or 73M1912.
RLPNEN 0x16[5] W Receive Low P ass Not ch Enable
0 = Billing Tone Receive Low P ass N otch ( R LPN) fil ter bypassed.
(Default)
1 = RLPN Fi lt er Enabled. See RLP N H for n otch frequen cy selecti on.
RLPNH 0x14[2] W R eceive Low P ass Notch
0 = Sel ects R eceive Low P ass Not ch ( R LPN) at 12 k Hz . (D efaul t)
1 = Sel ects RL PN at 16 kHz. S ee RLPNEN at regi st er add r ess 0x16[5] to
enable fi l ter.
THEN 0x15[3] W Enable Transhybrid Circuit
The rejec ti on of the tr ansmit signal from the r eceive s i gn al path.
0 = Transhybrid Circuit disabled. (Default)
1 = Transhybrid Circuit enabled.
This bit should always be set for optimal performance.
73M1822/73M1922 Data Sheet DS_1x22_017
68 Rev. 1.6
Function
Mnemonic Register
Location Type Description
ACCEN 0x13[4] W AC Canc ellation Enable
Cancels the AC signals from th e D C t r ansconduct ance circui t.
0 = No A C c an c ellation. (Default)
1 = Enabl es the c ancellation of AC from the DC transc ondu ctance circuit.
Thi s s hou l d be set for normal oper ati on.
ENAC 0x12[5] WO Enable AC Transconductance Circuit
0 = Shut Down AC Transconductance Circuit. Aux A/D input = Ring
Detec t Buffer ( R GN ) / Line Voltage (DCI) . Sei ze s tate for going off hook .
(Default)
1 = Enable AC Transconductance Circuit. Aux A/D input = Line Current
(DCS) / Line Voltage (DCI).
ENDC 0x12[6] WO Enable DC Transconductance Circuit
0 = Shut down Transconductance Circuit. (Default)
1 = Enable Transconductance Circuit.
ENSHL 0x12[4] WO Enable Shunt Loading
0 = Dis able s hunt loading. ( D efaul t)
1 = Enabl e shunt l oading of t he line.
ENFEL
0x12[2]
WO
Ena bl e Front En d Li ne -Sid e Circu it
0 = Power down Front End Line-S ide circuit s . (Default)
1 = Enable Front End blocks excluding DCGM, ACGM, shunt regulator.
ENLVD 0x12[3] WO L eV Det ect ion (OVDT, UVDT, OI DT mon itors)
0 = Enabl e LeV detection. (Defau lt )
1 = Disable LeV detection (used in line-p owe r ed mode to s ave power).
This bit will be 0 when Line Powered Mode is detected (ENLPW is set in
Register 0x02[2]) and set to 1 when an interrupt occurs within the Line-
Side Device. This bi t must be reset pri or to swit chi ng back t o Bar r i er
P owered M ode.
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 69
11.7 International Register Settings Table for DC and AC Terminations
Table 45 lists the r ecommended ACZ and D C IV regis ter settings for v ar ious countr ies. Other parameters
can also be set in addition to the AC an d DC termination. These settings along with the reference
schematic ( see Figure 10 and Figure 11) can realiz e a single des ign for global usage wit hou t country-
specifi c modific ati ons. For more informat ion on worldwide approvals, r efer to the 73M 1 922 Worl d-Wide
Design Guide Application Note.
Table 45: Recommended Register Settings for International Compatibility
Country ACZ DCIV Country ACZ DCIV Country ACZ DCIV
Argentina 00 10 Hungary1 01 10 Pakistan 00 10
Australia 11 11 Iceland2 01 10 Peru 00 10
Austria1 01 10 India 00 10 Philippines 00 10
Bahrain 00 10 Indonesia 00 10 Poland1 01 10
Belgium1 01 10 Ireland1 01 10 Portugal1 01 10
Bolivia 00 10 Israel 00 10 Romania1 01 10
Brazil 00 10 Italy1 01 10 Russia 00 10
Bulgaria1 01 10 Japan 00 00 Saudi Arabia 00 10
Canada 00 10 Jordan 00 10 Singapore 00 10
Chile 00 10 Kazakhstan 00 10 Slovakia1 01 10
China 00 10 Kuwait 00 10 Slovenia1 01 10
Columbia 00 10 Latvia1 01 10 South Africa 11 10
Croatia
01 10 Lebanon 00 10 South Korea 00 10
Cyprus1 01 10 Leichtenstein2 01 10 Spain1 01 10
Czech Rep1 01 10 Lithuania1 01 10 Sweden1 01 10
Denmark1 01 10 Luxembourg1 01 10 Switzerland2 01 10
Ecuador 00 10 Macao 00 10 Syria 00 10
Egypt 00 10 Malaysia 00 10 Taiwan 00 10
El Salvador 00 10 Malta1 01 10 ES 203 021-2 01 10
Estonia1 01 10 Mexico 00 10 Thailand 00 10
Finland1 01 10 Morocco 00 10 Turkey 00 10
France1 01 10 Netherlands1 01 10 UAE 00 10
Germany1 01 10 New Zealand 11 10 UK1 01 10
Greece1 01 10 Nigeria 00 10 Ukraine 00 00
Guam 00 10 Norway2 01 10 USA 00 10
Hong Kong 00 10 Oman 00 10 Yemen 00 10
1 These countri es are member s of t he Eur opean U nion, where ther e are no longer any reg ulat ory
requi r ements for AC imped ance. Th e suggested s etti ng complies with ETSI ES 20 3 021-2. Othe r
setti ngs c an be u sed if desir ed.
2 These c ountr i es are member s of t he Eur opean Free Trade Ass ociation, and thei r r egulations gener ally
follow t he E ur opean U nion model. The suggested s ettin g complies with ETSI E S 2 03 021-2.
73M1822/73M1922 Data Sheet DS_1x22_017
70 Rev. 1.6
12 Line Sensing and Status
12.1 Auxiliary A/D Converter
An 8-b it au xil iary A/ D c onverter integrated in the 73M1x22 provides line m onitoring and sensing capabilities.
The A/D converter inp ut signals ar e connected to the RGP and RG N pins of the devic e. It i s poss i ble t o use
t his A/D converter to s ample signals unr elat ed to PSTN DAA functions. Howe ver, i n thi s applic at ion , it is
nec ess ary to isolate the input s i gnal with op ti cal or other means since the 73M1x22 is c onn ected di r ectly t o
t he PSTN. Under normal condi tions, RGP and RGN are AC coup l ed to the line throu gh hi gh voltage ( 25 0
V ) capacitor s.
Through the use of t his auxil iary A/D convert er , the fol lowin g line status sensing featur es are suppor ted by
the 73M1x22:
• Ri ng dete cti o n.
• P STN l ine alr eady in use detection.
• Off-h ook detect ion that a paral lel phon e has been picked-up – p arallel pick-up de te c ti o n ( PPU).
• On-h ook detection of D C loop volt age p ol arity reversals .
• On-h ook detection of Type II Cal ler ID .
12.2 R ing Det ecti on
Ring D etection is pr ovided throu gh ci r cuitr y conn ected to the devic e pins RGP and RGN. Any large voltage
t r ansiti on (ringing or l ine reversal) wil l be a source for the “ Wake up” si gnal t o the 73M1x22. Up on recepti on
of a w ake-up s ignal , the 73M 1x22 passes the detected s i gnal to t he h ost wher e i t is to be qu al ified for
frequency and cadence (on an d off t imi ng of the ring tone bursts ) as a valid ring signal.
12.3 Line In Use Detection (LIU)
I f the 73M 1x22 i s preparing to go off-h ook and dial, i t i s required to be aware whether the p hone line i s
already in use by another device. If the 73M1x22 determines that the phone line is presently in use, it ca n
avoi d g oi ng off-hook and interrupting the call in progress. The tim ing of the 73M1x22 off-hook transiti on can
be delayed until the 73M1x22 determines that the phone line is available. LIU sensing is done at pin DCIN
with the Au x A/D.
12.4 P ara lle l Pi ck Up (PPU)
P ar allel Pick U p is a m eans for the 73M 1x22 to determine and n oti fy a h ost in the case when the D AA i s off-
hook and a sec ond or paral l el conn ected device during the c ourse of a connect ion is al so made to go off-
hook.
12.5 Polarity Reversal Detection
A third type of line sensing r equ i r ement is ass ociated with C aller ID prot ocols found i n Japan and some
E uropean c ountr i es. In thes e countri es, the C al ler ID si gnals ar e sent pr i or to the start of normal ri nging. A
polar i ty revers al is used to indic ate to the 73M1 x22 that transmis sion of C al ler ID i nformat ion is about to
begin. The detec ti on of a pol ar ity re versal takes place whil e the 7 3M 1x22 is in the on-hook s tate.
12.6 Off-hook Detection of Caller ID Type II
I t i s also poss ible to r eceive Caller ID signal s whi le the telephone is i n use, referred to as Type II CID . This
requi r es the 73M 1x12 to c onstantly monit or the l ine for s ignal s, s uch as special in-band or CA S tones, while
t he 73M 1x22 is i n the off-h ook s tate. Th is i s done throug h the normal r eceive path.
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 71
12.7 Voltage and Current Detection
The 73M1x22 is capable of detecting the following circumstances:
• Under voltage on the line
• O ver voltage on the line
• Over cu rrent
Thes e 73M1x22 buil t-in mechanisms pr ovide prot ection to both the device itself and the ext er nal li ne
circuitry.
I f enabled, Over V olt age an d Over Current detec tion will cause the 73M 1x22 to go on-hook without the
intervention of the host.
I f c onfig ured in Line Powered mode, t he d etection of an Under-voltage condition causes the 73M1x22 to
switc h automat i cal l y to Barrier Powered Oper ati on (see Section 10.2.1). This is done without the
intervention of the host.
For each of the detection functions there ar e enable c ontr ol and detection status. For eac h of the functions
t here is a master detection function enab l e bit that i s to be s et in order for the functions to work.
12.8 Under Voltage Detection (UVD )
Under Voltage Detection is an important feature of 73M 1x22. It is intended to deter mine i f the phone line is
not capab l e of suppl ying the curr ent that the 73M1x22 requires from the l ine for pr oper operat i on. If thi s
function is enabled and If the line is not capable of providing this current, the UVD condition will be asserted
and c an become a source of inter r up t from 73 M 1x22 to i ts connected host.
12.9 Over Voltage Detection (OVD )
I f enabled, Over V olt age Detection is ind i cated i f the devic e senses that the line voltage exc eeds a defined
t hreshold. The device all ows the selection of c hoic e of ei ther 60 Vpk or 70 Vpk (depending upon the
at tenuati on rat io, typical l y this is 100:1) .
I f enabled the 73M 1x22 will automat i cally g o on-hook if over voltage i s detected.
12.10 AC S ignal Ov er L oad Det e ction
Thi s is the same feature as used for the detection of bill i ng tones (see Section 11.4) . In this most generic
sense, this detec tor provid es an i ndic ator that the AC si gnal on the li ne exceed s a value of
3.5 Vpk.
12.11 Over Current Detection (OID)
When the line c urrent exceeds the safe op er ating rang e of the 73M1x22 or the external transistors, the
device indi cates this condi ti on. If enabl ed, the 73M 1x22 will automat i cal ly go on-hook if an over curr ent
event i s detect ed.
73M1822/73M1922 Data Sheet DS_1x22_017
72 Rev. 1.6
12.12 Line Status Functions Control Functions
These regis ters contain control informati on to set up and use the 73M1x22 line sensing functions.
Table 46: Line Sensing Control Functions
Function
Mnemonic
Register
Location Type Description
RXBST 0x14[3] WO Received Boost
I f s et to 1, R eceive s i gn al is i ncreased by 20 dB. Default is 0. This is
us ed to am plify sign al s that are pass ed thr ough the auxil iary A/D
when On-Hook.
CIDM 0x15[4] W Caller ID Mode
0 = Dis ab le Caller ID Mode. (Default)
1 = Enabl es Caller ID M ode b y coup l ing the s ignal from th e
RGN/RGP pins to th e receive filter input. A 20 dB gain boost is
included in the signal path. The RXBST bit should also be set to allow
t he total nominal gain of 40 dB in the C aller ID path. The norm al
signal path is disconnected.
Rin g D etecti o n Status Bi ts
RGTH 0x0E[1:0] W R i ng D etect Thr eshol d
Controls the R ing Detect Th r eshold assumi ng a 10 0:1 redu ction of
Ring Voltage into RGP/RGN pins.
RGTH1 RGTH0 Description
0 0 Ring D etect di sabl ed. For ring
detection to oc cur, these bits
must be programmed to a
non-zer o state.
0 1 0.15 Vpk equivalent to ±15
Vpk at Auxiliary A/D input.
1 0 0.30 Vpk equivalent to ±30
Vpk at Auxiliary A/D input.
1 1 0.45 Vpk equivalent to ±45
Vpk at Auxiliary A/D input.
RGMON
0x03[3]
R
Ringing Mon itor
B it 3 monitors the activity of Ringing for further cadence c heck by the
host:
0 = Silent (Default)
1 = Ring ing
This bit is not latched. This s tatus bit i s reset when read.
RGDT 0x03[0] R Ri ng or Line R eversal D etection
V oltage greater than the Ring D etect Thr eshol d was detected at
RGP/RGN. This value is latched upon the event and clear ed on r ead.
The thr eshol d is deter mined by RGTH. Thi s i s a mask able inter r upt.
It is enabled by th e E NRGDT b it.
0 = No Latched R i ng or Line R eversal D etection event. (D efault)
1 = A Latch ed Ring or Line Reversal D etection event.
ENRGDT
0x05[0] W E nab l e Ring Det ection Inter r upt
This control bit enables the ring detection interrupt.
0 = Ring Detection Interr upt Disabled.
1 = Ring Detection Interr upt Enabled. (Default)
When 73M1922 detects an incoming ring signal, this bit will be set, if
enabled, and r eset when read.
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 73
Auxiliary A/D Converter Status Bits
RNG 0x1A[7:0] R Result of Auxil iary A/D measur i ng the attenuated ring voltage.
Note: 1 lsb=1.31/128=~10.23 mV; 1’s complim ent.
E xample: 00100 000 327 mV or Ring Voltage=32.7 V
LV 0x1B[7:1] R Li ne Voltage On and Off Hook
LV contains the seven most significant bits of an 8-bit A/D
representation of the voltage of the i npu t of pi n DCI. The voltage at
the DCI pin is equal to the decimal value of LV bits [7:1] x 2 1.87
mV. For example, if t he value of 0100000 is r ead from LV bits
[ 7:1], this has a decim al value of 32, therefore DCI voltage equals
32 x 21.87 = 700 mV.
Note that the voltage at the D C I pi n is the voltage divided by 5 (off
hook ) or 100 ( on hook). When offhook the di ode bridge, switch
satur ation volt age, etc. s hould also be added to calcul ate the
vol tage at ti p and r ing.
LC 0x1C[7:1] R Loop Current in DC Path
Res ult of A uxil iary A/D measur i ng the Loop Current (7-bit
res ol ution, least significant bits only).
Note LC0=1 lsb=1.31/128=~10.23 mV=1.25 mA; magnitude only.
The value of the resi stor betw een the r ectifier bri dg e and the DCS
pin is assumed to be 8.2 Ω.
E xample: 00000 11 30.7 mV/ R E=3.7 4 m A; 0010000 20 mA
Note: The AC path also has ~7 mA of loop current that should be
added to get the total l oop curr ent pr ovided by the line.
Line Sensing Contro l
DET 0x03[2] R Detection of Voltage or Current Fault
0 = None of the thr ee condit ions i s detec ted. (Default)
1 = Indi cates the detection of one of thr ee condi ti ons:
Under Voltage, Over V olt age an d Over Current.
Thi s s tatus bit is r eset when read. Thi s is a maskable i nter r up t. It
is enabled by the ENDET bit.
ENDET 0x05[2] W Enables Line Sensing Interrupt on Host Side Device
Th is bit c on trols whether an interrupt i s generated b ased upon the
detection of Under Volt age, Over Voltage and Over C ur r ent.
0 = Dis able detec tor i nter r upt. (Default)
1 = Enabl e detector i nterr upt.
ENDT 0x12[1] WO E nab l e Detec tors on Line Side Device
0 = UVDT, OV DT and OI DT condi ti ons are i gn or ed. ( Defau lt)
1 = Enables UVDT, OVDT and OIDT in the Line-S ide Device and
allows them t o be used in the H ost-S ide Device.
Under-V ol tage Detec ti on Control and Status
ENUVD 0x15[2] WO Enable Under Volt age Det ector on Line Side Device
1 = Under Voltage D etector Enabled. When enabled, the EN NOM
bit is temporarily set to the wide bandwidth mode if an
under-v ol tage condi tion detect ed to al low fast reacqui siti on of the
line.
UVDET 0x1E[6] R Under-Voltage Det ecti on on Line Side Device
0 = Under Voltage condition is not detect ed at VPS. (Default)
1 = Under Voltage condition is detec ted at VPS.
73M1822/73M1922 Data Sheet DS_1x22_017
74 Rev. 1.6
Over-V ol tage Detection Control a nd Status
ENOVD 0x15[1] WO E nab l e Over-V oltage Detector on Line Side Device
1 = Over Voltage D etector Enabled (not lat ched) . Over volt age
detector is enab l ed if E N OVD, ENFEL and ENNOM all equal 1.
OVDET 0x1E[5] R Over-V olt age Det ected on Line Side Device
0 = Over Voltage condi tion is not detec ted at R GP/R GN inputs .
(Default)
1 = Over Voltage C ond i tion is detec ted at RGP /RGN inputs.
OVDTH 0x13[2] WO Over-V olt age Threshol d Setting
0 = Over Voltage Threshold is 0.6 Vpk at the ch ip or 60 Vp on the
line. (Default)
1 = Over Voltage Threshold is 0.7 Vpk at the ch ip or 70 Vp on the
line.
Over-Current Detection Control and Status
ENOID 0x15[0] WO Enab l e Over-Cur r ent Det ector on Line Side Device
0 = Over -Current Detector i s not enabled. (D efaul t)
1 = Over -Current Detector i s enabled.
OIDET 0x1E[4] R Over-Curren t (I) Det ector on Line Sid e D evice
0 = Over -Curren t (I) cond i tion is not detect ed. (Default)
1 = Over -Current (I) condition is detected at the DCS pin when
L oop C urrent i s > 125 mA if ILM=0, or > 55 mA if ILM=1.
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 75
13 Loopback and Testing Modes
Figure 36 show the five loopb ack modes available in the 73M1x22.
TBS
DSDM
PRM SCM
MSBI LSBI
RxAFE
SinC3
Filter
Onchip
LIC
MAFE
Interface
TxAFE
Interp.
Filter
Decim.
Filter
TxData
RxData
RBS
Tip
Ring
PRP SCP
TxD
RxD
CTL
STA
External
LIC
73M1822 HIC/
73M1902 73M1822 LIC/
73M1912
Aux A/D
STA
ALB
INTLB1 DIGLB2
DIGLB1
INTLB2
RxA
TxA
TxD
RxD
Ring
Buffer
Figure 36: Loopback Modes Highli ghte d
Table 47 des cri bes how the ab ove contr ol bits interact to provide each of the s i x lo opback m odes.
Table 47: Loopb ack Modes
TEST
TMEN
DTST
Loopback Mode
Mnemonic
0000 0 00 Normal mode. ( Defau lt)
No Loops
0000 1 10 Digital Loopback mode. Interpolated
TxData (TxD) i s looped b ack to the
Decim ated RxData in put (RxD).
DIGLB1
0000 1 11
Remote Analog Loopback . R eceived RxD
is looped back as TxD an d tr ansmitt ed
bac k to th e 73M1922
Line-S ide Device; RxD i s D/A converted to
yi eld the anal og tr ansmit signal ( TxA) .
INTLB1
0001 0 00 Di gital Loopback mode. Transmi t Bit
S tr eam (TBS) is looped back to receive
digit al c hannel and received (DIG LB2) .
DIGLB2
0010 0 00
Remote Analog Loopback . R eceive
analog sign al is converted to Received Bit
S tr eam (RBS) and is looped back to TB S
and the analog transmit channel (INTLB2).
INTLB2
0011 0 00 Analog L oopback . The transmi t data i s
connected to the receiver at the analog
interface and recei ved (ALB) .
ALB
73M1822/73M1922 Data Sheet DS_1x22_017
76 Rev. 1.6
13.1 Loopback Controls
Table 48 des cri bes the regis ters used for loopback contr ol.
Table 48: Loopback Controls
Function
Mnemonic
Register
Location Type Description
TMEN 0x02[7] W Test M ode En able
Us ed to enab l e the activation of the test loops control l ed b y
t he DTST b i ts (D IGLB1 and IN TLB1).
0 = No DTST loops enabl e. ( Defau lt)
1 = DTST loops enab l e.
TM EN has to be set to 1 before the setting of the D TST
bits.
DTST 0x07[3:0] W These c ontr ol bits enabl e DIGLB1 and INTLB1.
P r ior to wr iting to these bits, TMEN must be s et to 1.
DTST1
DTST0
Sel ected Test Mode
0 0 N or mal (D efault )
1 0 DIGLB1
1 1 INTLB1
TEST 0x18[7:4] W This four-bit field i s us ed to enab l e the loopback m ode per th e
following table:
TEST
Loopback M ode
0000 Normal mod e. (Default)
Transmit and recei ve c hannels ar e i nd epend ent.
0001 Dig ital loopbac k mode. Transmi t Bit S tr eam (TBS)
is looped back to r eceive di git al c hannel and
received (DIGLB2).
0010 Remote Analog loopback. Receive analog si gnal
is converted to Received Bit St r eam (RBS) and is
looped back to TBS and the anal og tr ansmit
channel (INTLB2).
0011 Analog loopback. The transmi t data i s c onnected
t o the r ecei ver at the analog inter face and
rec eived (A LB).
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 77
14 Performance
Thi s s ection p r ovides an overview of t ypical performance characteri stics measur ed u sing a 73 M 1x22
production device on a T er idian Ref erenc e Boar d. The measurements were mad e at the ti p and r ing pin s.
14.1 DC VI Characteristics
14.1.1 Off-H ook Tip and Ring DC Characteristics
Figure 37: Off-Hook Tip and Ring DC Characteristics
TBR21
Not allowed
0
1
0
2
0
3
0
4
0
5
0
0 2 4 6 8 9 1
01
52
02
53
03
54
04
55
05
56
0
Tip and Ring DC Current (mA)
Tip and Ting DC Voltage (volt)
DCIV=00, ILM=1
DCIV=01, ILM=1
DCIV=10, ILM=1
Not allowed
Figure 38: ES 203 02 1-2 DC Mask with Current Limit Enabled
73M1822/73M1922 Data Sheet DS_1x22_017
78 Rev. 1.6
0
2
4
6
8
10
12
14
0
4
8
15
25
35
45
55
65
75
85
95
Loop current
Tip and Ring DC voltage
Australian not recommended
Region
Australian
Prohibited
Region
DCIV=11
Figure 39: Australian Hold State Characteristics
14.2 Receive
0
5
10
15
20
25
30
35
40
45
50
100
200
300
400
500
600
700
800
900
1000
1500
2000
2500
3000
3500
4000
4500
5000
5500
Frequency
Return Loss dB
US
TBR21
China
Australia
Australia Limit USA Limit
TBR21 Limit
Figure 40: Return Loss
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 79
15 Pack age L ay out
Figure 41: 20-Pin TSSOP Package Dimensions
2.5
5
2.5
5
TOP VIEW
1
2
3
0.2 MIN.
0.35 / 0.45
1.5 / 1.875
3.0 / 3.75
0.18 / 0.3
BOTTOM VIEW
1
2
3
0.25
0.5
0.5
0.25
3.0 / 3.75
1.5 / 1.875
0.35 / 0.45
CHAMFERED
0.30
Figure 42: 32-Pin QFN Package Dime nsions
0.85 NOM.
/
0.9MAX. 0.00 / 0.005
0.20 REF.
SEATING
PLANE
SIDE VIEW
73M1822/73M1922 Data Sheet DS_1x22_017
80 Rev. 1.6
Figure 43: 42-Pin QFN Package Dime nsions
DS_1x22_017 73M1822/73M1922 Data Sheet
Rev. 1.6 81
16 Ordering Information
Table 49 lists the order numbers and packaging marks used to identify 73M1822 and 73M1922 products.
Table 49: Order Numbers and Packaging Marks
Part Description
Order Number
Packaging Mar k
Host/Line
73M19 22 3 2-Pin QFN, Lead free 73M1922-IM/F 73M1912-M
73M1902-M Line-Side IC
Host-Si de IC
73M19 22 3 2-Pin QFN, Lead free,
Tape and Reel
73M1922-IMR/F
73M1912-M
73M1902-M
Line-S ide IC
Host-Si de IC
73M19 22 2 0-Pin TSSOP, Lead free 73M1922-IVT/F 73M1912VT
73M1902A Line-Si de IC
Host-Si de IC
73M19 22 2 0-Pi n TSSO P, Lead free
Tape and Reel 73M1922-IVTR/F 73M1912VT
73M1902A Line-Si de IC
Host-Si de IC
73M18 22 4 2-Pin QFN, Lead free 73M1822-IM/F 73M1822A-IM
73M18 22 4 2-Pin QFN, Lea d free,
Tape and Reel 73M1822-IMR/F 73M1822A-IM
17 Contact Infor matio n
For more information about Teri dian Semic onductor produ ct s or to check the availab i lity of the 73M1822 or
73M1922, contact us at:
6440 Oak C anyon Road
Suite 100
I r vine, C A 92618 -5201
Telephone: (714) 508-8800
FAX : (71 4) 50 8-8878
Email: mode m.support@teridian.com
For a comp l ete list of worldwide sales offices, go to http://www.teridian.com.
73M1822/73M1922 Data Sheet DS_1x22_017
82 Rev. 1.6
Revis ion History
Revision Date Description
1.0 10/26/2007 First p ub lic at ion .
1.1 11/7/2007
1.1.1 4/11/2008
1.2 8/28/2008
1.3 3/23/2009
1.4 8/6/2009
1.5 10/16/2009
1.6 4/7/2010 Changed the values i n Table 17.
Repl aced the sc hemat ics i n Figure 10 and Figure 11.
Updated the Bill of Mater i als in Table 27.
Added the ACCEN bit to Table 30 and Table 31.
Corr ected the T ypes (R, W, W O) in Table 31.
A dded clar ific ation to t he d esc r iption of the PLDM bit.
A dded clar ific ation to t he d esc r iption of the RGDT bit.
Teridian Semiconduct or Corpor ati on is a r egister ed tr ademark of Teridian Semic onductor Cor porat ion.
S impl ifyin g Sys tem Integr ation is a trademark of Teridian Semicondu ct or Corpor ation.
MicroD AA is a r egister ed tr ademark of T er i dian Semicondu ctor C or por ation.
A ll other tr ademark s are the property of their respective owners.
Teridian Semiconduct or Corpor ati on makes no warranty fo r the u se of its products, other than express ly
contai ned i n the Company’s warranty det ailed in the Teridi an Semiconductor Cor porat i on standar d Terms
and Condit ions . The c omp any assumes no r esponsibility for any errors which may appear in this
doc umen t, reserves the r ight to c hange d evices or specifications detai led herein at any t i me withou t noti ce
and does not make any commi tment to update the i nformation contai ned h er ei n. Accor dingl y, the r eader is
cauti oned to verify t hat this document i s cu r r ent by compari ng it t o the lat est version on
http://www.teridian.com or by check i ng with your sales repr esentati ve.
Teridian Semiconduct or Corp., 6440 Oak Canyon , Suit e 100, Irvine, C A 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
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73M1822-IM/F 73M1822-IMR/F 73M1902-IM/F 73M1902-IVT/F 73M1912-IVT/F 73M1912-IM/F 73M1922-IM/F
73M1922-20IVT-EVM 73M1922-IVTR/F 73M1922-IMR/F 73M1822-EVM 73M1922-IVT/F 73M1912-IMR/F 73M1902-
IMR/F 73M1912-IVTR/F 73M1902-IVTR/F 73M1922-KEYCHN
