SEROCCO-D
PEB 20542, PEF 20542
Correction of Errata
Preliminary Delta Sheet 2/3 2003-11-24
2 Correction of Errata
The following erratas known and documented in the Errata Sheet of SEROCCO-D
Version V1.2 have been corrected:
•DTACK
/READY-Controlled Cycles
• DMA in Motorola Interface Mode
• DPLL in Bus Configuration
• HDLC Auto Mode: RNR not clearable
• HDLC Mode: 1-Byte Frames with ITF=1
• Extended Transparent Mode: XDU recovery
• Extended Transparent Mode: Octet alignment in CM5a/b
• CD Status Change Interrupt
• Disable Reception of CRC
• Interframe Time Fill in Combination with Flow Control using CTS
• Using Continuous FLAGs as Interframe Time Fill
3 Electrical Characteristics
3.1 Changed AC Characteristics
Table 1 Infineon/Intel Bus Interface Timing (Slave Access)
No. Parameter Limit Values Unit
Min. Max.
10 active RD to valid data delay 24 ns
Table 2 Motorola Bus Interface Timing (Slave Access)
No. Parameter Limit Values Unit
Min. Max.
40 active address to active DS setup time 8 ns
48 active DS (read) to valid data delay 25 ns
Table 3 Infineon/Intel Bus Interface Timing (Master Access)
No. Parameter Limit Values Unit
Min. Max.
60a clock to valid address delay 9 22 ns