SC28L198A1BE,557 - NXP





SC28L198

Octal UART for 3.3 V and 5 V supply

voltage

Product data sheet

Supersedes data of 1999 Jan 14 2006 Aug 10

INTEGRATED CIRCUITS

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2

2006 Aug 10

Table of Contents

Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Uses 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Features 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Configurations 4. . . . . . . . . . . . . . . . . . . . . . . . .

Pinout 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Description 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 6. . . . . . . . . . . . . . . . .

Block Diagram 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description 7. . . . . . . . . . . . . . . . . . . . .

Conceptual Overview 7. . . . . . . . . . . . . . . . . . . . . . .

Host Interface 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Asynchronous bus cycle 7. . . . . . . . . . . . . . . . . . . . . . . . . . .

Synchronous bus cycle 7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Circuits 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Crystal Oscillator 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sclk – System Clock 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Baud Rate Generator BRG 8. . . . . . . . . . . . . . . . . . . . . . . .

BRG Counters (Used for random baud rate generation) 8

Channel Blocks 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Character Recognition 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Control 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Global Registers 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Ports 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Detailed Descriptions 9. . . . . . . . . . . . . . . . . . . . . . .

Receiver and Transmitter 9. . . . . . . . . . . . . . . . . . .

Transmitter 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Status Bits 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T ransmission of ”break” 10. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1x and 16x modes, T ransmitter 10. . . . . . . . . . . . . . . . . . . . .

Transmitter FIFO 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1x and 16x mode, Receiver 10. . . . . . . . . . . . . . . . . . . . . . . . .

Receiver Status Bits 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver FIFO 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RxFIFO Status: Status reporting modes 11. . . . . . . . . . . . . .

I/O ports 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Purpose Pins 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Global Registers 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Character Recognition 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Xon Xoff Characters 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multi-drop or Wake up or 9 bit mode 12. . . . . . . . . . . . . . . . .

Character Stripping 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Arbitration and IRQN generation 12. . . . . . . . . . . . . . . .

IACKN Cycle, Update CIR 13. . . . . . . . . . . . . . . . . . . . . . . . . .

Polling 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Enabling and Activating Interrupt sources 13. . . . . . . . . . . . .

Setting Interrupt Priorities 13. . . . . . . . . . . . . . . . . . . . . . . . . .

Modes of Operation 14. . . . . . . . . . . . . . . . . . . . . . . .

Major Modes 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Minor Modes 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Watch-dog Timer Time–out Mode 15. . . . . . . . . . . . . . . . . . .

W ake Up Mode 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Xon/Xof f Operation 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REGISTER DEFINITIONS 18. . . . . . . . . . . . . . . . . . . .

MR – Mode Registers 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UCIR – Update CIR 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Purpose Output Pin Control 30. . . . . . . .

Register Maps 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Register Map Summary 31. . . . . . . . . . . . . . . . . . . . .

Register Map Detail 32. . . . . . . . . . . . . . . . . . . . . . . .

Reset Conditions 41. . . . . . . . . . . . . . . . . . . . . . . . . . .

Device Configuration after Hardware Reset or CRa cmd=x1F 41

Cleared registers: 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clears Modes for: 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Disables: 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Halts: 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Limitations: 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC Electrical Specifications (5V) 42. . . . . . . . . . . .

AC Electrical Characteristic (5V) 43. . . . . . . . . . . .

DC Electrical Specifications (3.3V) 45. . . . . . . . . .

AC Electrical Characteristics (3.3V) 46. . . . . . . . . .

INDEX 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DESCRIPTION

The Philips 28L198 Octal UART is a single chip CMOS–LSI

communications device that provides 8 full-duplex asynchronous

channels with significantly deeper 16 byte FIFOs, Automatic

in–band flow control using Xon/Xoff characters defined by the user

and address recognition in the wake up mode. Synchronous bus

interface is used for all communication between host and OCTART.

It is fabricated using Philips 1.0 micron CMOS technology that

combines the benefits of low cost, high density and low power

consumption.

The operating speed of each receiver and transmitter can be

selected independently from one of 22 fixed baud rates, a 16X clock

derived from one of two programmable baud rate counters or one of

three external 16X clocks (1 available at 1x clock rate). The baud

rate generator and counter can operate directly from a crystal or

from seven other external or internal clock inputs. The ability to

independently program the operating speed of the receiver and

transmitter makes the Octal UART particularly attractive for dual

speed full duplex channel applications such as clustered terminal

systems. The receivers and transmitters are buffered with FIFOs of

16 characters to minimize the potential for receiver overrun and to

reduce interrupt overhead. In addition, a handshaking capability and

in–band flow control are provided to disable a remote UART

transmitter when the receiver buffer is full or nearly so.

To minimize interrupt overhead an interrupt arbitration system is

included which reports the context of the interrupting UART via

direct access or through the modification of the interrupt vector. The

context of the interrupt is reported as channel number, type of

device interrupting (receiver COS etc.) and, for transmitters or

receivers, the fill level of the FIFO.

The Octal UART provides a power down mode in which the

oscillator is stopped but the register contents are maintained. This

results in reduced power consumption of several orders of

magnitudes. The Octal UART is fully TTL compatible when

operating from a single +5V power supply. Operation at 3.3 volts is

maintained with CMOS interface levels.

The device also offered in a version which maintains TTL input and

output levels while operating with a 3.3 volt power supply.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 3

Uses

Statistical Multiplexers

Data Concentrators Packet–switching networks

Process Control

Building or Plant Control

Laboratory data gathering

ISDN front ends

Computer Networks

Point–of–Sale terminals

Automotive, cab and engine controls

Entertainment systems

MIDDI keyboard control music systems

Theater lighting control

Terminal Servers Computer–Printer/Plotter links

FEATURES

•Single 3.3V and 5V power supply

•Eight Philips industry standard full duplex UART channels

•Sixteen byte receiver FIFOs for each UART

•Sixteen byte transmit FIFOs for each UART

•In band flow control using programmable Xon/Xoff characters

•Flow control using CTSN RTSN hardware handshaking

•Automatic address detection in multi-drop mode

•Three byte general purpose character recognition

•Fast data bus, 30 ns data bus release time, 125 ns bus cycle time

•Programmable interrupt priorities

•Automatic identification of highest priority interrupt pending

•Global interrupt and control registers ease setup and interrupt

handling

•Vectored interrupts with programmable interrupt vector formats

–Interrupt vector modified with channel number

–Interrupt vector modified with channel number and channel type

–Interrupt vector not modified

•IACKN and DACKN signal pins

•W atch dog timer for each receiver (64 receive clock counts)

•Programmable Data Formats:

–5 to 8 data bits plus parity

–Odd, even force or no parity

–1, 1.5 or 2 stop bits

•Flexible baud rate selection for receivers and transmitters:

–22 fixed rates; 50 – 230.4K baud or 100 to 460.8K baud

–Additional non–standard rates to 500K baud with internal

generators

–Two reload–counters provide additional programmable baud

rate generation

–External 1x or 16x clock inputs

–Simplified baud rate selection

•1 MHz 1x and 16x data rates full duplex all channels.

•Parity, framing and overrun error detection

•False start bit detection

•Line break detection and generation

•Programmable channel mode

–Normal(full duplex)

–Diagnostic modes

automatic echo

local loop back

remote loop back

•Four I/O ports per UART for modem controls, clocks, RTSN, I/O

etc.

–All I/O ports equipped with ”Change of State Detectors”

•Two global inputs and two global outputs for general purpose I/O

•Power down mode

•On chip crystal oscillator, 2–8 MHz

•TTL input levels. Outputs switch between full VCC and VSS

•High speed CMOS technology

•84 pin PLCC

•100 pin LQFP

ORDERING INFORMATION

VCC = 3.3 V ±10 % VCC = 5 V ±10 %

PACKAGES Industrial

1

Industrial

1

DWG #

Industrial

–40 °C to +85 °C

Industrial

–40 °C to +85 °C

84-Pin Plastic Leaded Chip Carrier (PLCC) SC28L198A1A SC28L198A1A SOT189-2

100-Pin Plastic Low–Profile Quad Flat Pack (LQFP) SC28L198A1BE SC28L198A1BE SOT407–1

NOTES:

1. For availability, please contact factory.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 4

PLCC84 PIN CONFIGURATION

11 175

12

32

33 53

54

74

84-PIN PLCC

TOP VIEW

84

PLCC84 PINOUT

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Function

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Function

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Function

ÁÁÁÁÁÁ

1

ÁÁÁÁÁÁÁ

VSS

ÁÁÁÁÁÁ

29

ÁÁÁÁÁÁÁ

I/O1d

ÁÁÁÁÁÁ

57

ÁÁÁÁÁÁÁ

I/O2g

ÁÁÁÁÁÁ

2

ÁÁÁÁÁÁÁ

VCC

ÁÁÁÁÁÁ

30

ÁÁÁÁÁÁÁ

I/O2d

ÁÁÁÁÁÁ

58

ÁÁÁÁÁÁÁ

I/O1g

ÁÁÁÁÁÁ

3

ÁÁÁÁÁÁÁ

CEN

ÁÁÁÁÁÁ

31

ÁÁÁÁÁÁÁ

I/O3d

ÁÁÁÁÁÁ

59

ÁÁÁÁÁÁÁ

I/O0g

ÁÁÁÁÁÁ

4

ÁÁÁÁÁÁÁ

W_RN

ÁÁÁÁÁÁ

32

ÁÁÁÁÁÁÁ

RxDd

ÁÁÁÁÁÁ

60

ÁÁÁÁÁÁÁ

RxDg

ÁÁÁÁÁÁ

5

ÁÁÁÁÁÁÁ

A2

ÁÁÁÁÁÁ

33

ÁÁÁÁÁÁÁ

Vss

ÁÁÁÁÁÁ

61

ÁÁÁÁÁÁÁ

TxDg

ÁÁÁÁÁÁ

6

ÁÁÁÁÁÁÁ

A1

ÁÁÁÁÁÁ

34

ÁÁÁÁÁÁÁ

TxDd

ÁÁÁÁÁÁ

62

ÁÁÁÁÁÁÁ

VSS

ÁÁÁÁÁÁ

7

ÁÁÁÁÁÁÁ

A0

ÁÁÁÁÁÁ

35

ÁÁÁÁÁÁÁ

RESETN

ÁÁÁÁÁÁ

63

ÁÁÁÁÁÁÁ

X1

ÁÁÁÁÁÁ

8

ÁÁÁÁÁÁÁ

DACKN

ÁÁÁÁÁÁ

36

ÁÁÁÁÁÁÁ

Gin0

ÁÁÁÁÁÁ

64

ÁÁÁÁÁÁÁ

X2

ÁÁÁÁÁÁ

9

ÁÁÁÁÁÁÁ

I/O0a

ÁÁÁÁÁÁ

37

ÁÁÁÁÁÁÁ

Gout0

ÁÁÁÁÁÁ

65

ÁÁÁÁÁÁÁ

TxDf

ÁÁÁÁÁÁ

10

ÁÁÁÁÁÁÁ

I/O1a

ÁÁÁÁÁÁ

38

ÁÁÁÁÁÁÁ

D0

ÁÁÁÁÁÁ

66

ÁÁÁÁÁÁÁ

I/O3f

ÁÁÁÁÁÁ

11

ÁÁÁÁÁÁÁ

RxDa

ÁÁÁÁÁÁ

39

ÁÁÁÁÁÁÁ

D1

ÁÁÁÁÁÁ

67

ÁÁÁÁÁÁÁ

I/O2f

ÁÁÁÁÁÁ

12

ÁÁÁÁÁÁÁ

RxDb

ÁÁÁÁÁÁ

40

ÁÁÁÁÁÁÁ

D2

ÁÁÁÁÁÁ

68

ÁÁÁÁÁÁÁ

I/O1f

ÁÁÁÁÁÁ

13

ÁÁÁÁÁÁÁ

I/O2a

ÁÁÁÁÁÁ

41

ÁÁÁÁÁÁÁ

D3

ÁÁÁÁÁÁ

69

ÁÁÁÁÁÁÁ

I/O0f

ÁÁÁÁÁÁ

14

ÁÁÁÁÁÁÁ

I/O3a

ÁÁÁÁÁÁ

42

ÁÁÁÁÁÁÁ

VSS

ÁÁÁÁÁÁ

70

ÁÁÁÁÁÁÁ

TxDe

ÁÁÁÁÁÁ

15

ÁÁÁÁÁÁÁ

TxDa

ÁÁÁÁÁÁ

43

ÁÁÁÁÁÁÁ

VCC

ÁÁÁÁÁÁ

71

ÁÁÁÁÁÁÁ

I/O3e

ÁÁÁÁÁÁ

16

ÁÁÁÁÁÁÁ

I/O0b

ÁÁÁÁÁÁ

44

ÁÁÁÁÁÁÁ

D4

ÁÁÁÁÁÁ

72

ÁÁÁÁÁÁÁ

I/O2e

ÁÁÁÁÁÁ

17

ÁÁÁÁÁÁÁ

I/O1b

ÁÁÁÁÁÁ

45

ÁÁÁÁÁÁÁ

D5

ÁÁÁÁÁÁ

73

ÁÁÁÁÁÁÁ

I/O1e

ÁÁÁÁÁÁ

18

ÁÁÁÁÁÁÁ

I/O2b

ÁÁÁÁÁÁ

46

ÁÁÁÁÁÁÁ

D6

ÁÁÁÁÁÁ

74

ÁÁÁÁÁÁÁ

RxDf

ÁÁÁÁÁÁ

19

ÁÁÁÁÁÁÁ

I/O3b

ÁÁÁÁÁÁ

47

ÁÁÁÁÁÁÁ

D7

ÁÁÁÁÁÁ

75

ÁÁÁÁÁÁÁ

RxDe

ÁÁÁÁÁÁ

20

ÁÁÁÁÁÁÁ

TxDb

ÁÁÁÁÁÁ

48

ÁÁÁÁÁÁÁ

Gin1

ÁÁÁÁÁÁ

76

ÁÁÁÁÁÁÁ

I/O0e

ÁÁÁÁÁÁ

21

ÁÁÁÁÁÁÁ

I/O0c

ÁÁÁÁÁÁ

49

ÁÁÁÁÁÁÁ

I/O3h

ÁÁÁÁÁÁ

77

ÁÁÁÁÁÁÁ

IRQN

ÁÁÁÁÁÁ

22

ÁÁÁÁÁÁÁ

Vss

ÁÁÁÁÁÁ

50

ÁÁÁÁÁÁÁ

I/O2h

ÁÁÁÁÁÁ

78

ÁÁÁÁÁÁÁ

A7

ÁÁÁÁÁÁ

23

ÁÁÁÁÁÁÁ

I/O1c

ÁÁÁÁÁÁ

51

ÁÁÁÁÁÁÁ

I/O1h

ÁÁÁÁÁÁ

79

ÁÁÁÁÁÁÁ

A6

ÁÁÁÁÁÁ

24

ÁÁÁÁÁÁÁ

I/O2c

ÁÁÁÁÁÁ

52

ÁÁÁÁÁÁÁ

I/O0h

ÁÁÁÁÁÁ

80

ÁÁÁÁÁÁÁ

A5

ÁÁÁÁÁÁ

25

ÁÁÁÁÁÁÁ

I/O3c

ÁÁÁÁÁÁ

53

ÁÁÁÁÁÁÁ

Vss

ÁÁÁÁÁÁ

81

ÁÁÁÁÁÁÁ

A4

ÁÁÁÁÁÁ

26

ÁÁÁÁÁÁÁ

TxDc

ÁÁÁÁÁÁ

54

ÁÁÁÁÁÁÁ

RxDh

ÁÁÁÁÁÁ

82

ÁÁÁÁÁÁÁ

A3

ÁÁÁÁÁÁ

27

ÁÁÁÁÁÁÁ

RxDc

ÁÁÁÁÁÁ

55

ÁÁÁÁÁÁÁ

TxDh

ÁÁÁÁÁÁ

83

ÁÁÁÁÁÁÁ

IACKN

ÁÁÁÁÁÁ

28

ÁÁÁÁÁÁÁ

I/O0d

ÁÁÁÁÁÁ

56

ÁÁÁÁÁÁÁ

I/O3g

ÁÁÁÁÁÁ

84

ÁÁÁÁÁÁÁ

SCLK

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 5

LQFP100 PIN CONFIGURATION

100 76

1

25

26 50

51

75

100–PIN LQFP

TOP VIEW

LQFP100 PINOUT

ÁÁÁÁÁ

Function

ÁÁÁÁÁ

Function

ÁÁÁÁÁ

ÁÁÁÁÁÁ

Function

ÁÁÁÁÁ

Function

ÁÁÁÁÁ

1

ÁÁÁÁÁ

N/C

ÁÁÁÁÁ

26

ÁÁÁÁÁ

VSS

ÁÁÁÁÁ

51

ÁÁÁÁÁÁ

N/C

ÁÁÁÁÁ

76

ÁÁÁÁÁ

N/C

ÁÁÁÁÁ

2

ÁÁÁÁÁ

RxDb

ÁÁÁÁÁ

27

ÁÁÁÁÁ

TxDd

ÁÁÁÁÁ

52

ÁÁÁÁÁÁ

N/C

ÁÁÁÁÁ

77

ÁÁÁÁÁ

RxDe

ÁÁÁÁÁ

3

ÁÁÁÁÁ

I/02a

ÁÁÁÁÁ

28

ÁÁÁÁÁ

RESETN

ÁÁÁÁÁ

53

ÁÁÁÁÁÁ

RxDh

ÁÁÁÁÁ

78

ÁÁÁÁÁ

I/O0e

ÁÁÁÁÁ

4

ÁÁÁÁÁ

I/03a

ÁÁÁÁÁ

29

ÁÁÁÁÁ

GIN0

ÁÁÁÁÁ

54

ÁÁÁÁÁÁ

TxDh

ÁÁÁÁÁ

79

ÁÁÁÁÁ

IRQN

ÁÁÁÁÁ

5

ÁÁÁÁÁ

TxDa

ÁÁÁÁÁ

30

ÁÁÁÁÁ

GOUT0

ÁÁÁÁÁ

55

ÁÁÁÁÁÁ

I/O3g

ÁÁÁÁÁ

80

ÁÁÁÁÁ

A7

ÁÁÁÁÁ

6

ÁÁÁÁÁ

I/O0b

ÁÁÁÁÁ

31

ÁÁÁÁÁ

D0

ÁÁÁÁÁ

56

ÁÁÁÁÁÁ

I/O2g

ÁÁÁÁÁ

81

ÁÁÁÁÁ

A6

ÁÁÁÁÁ

7

ÁÁÁÁÁ

I/O1b

ÁÁÁÁÁ

32

ÁÁÁÁÁ

D1

ÁÁÁÁÁ

57

ÁÁÁÁÁÁ

I/O1g

ÁÁÁÁÁ

82

ÁÁÁÁÁ

A5

ÁÁÁÁÁ

8

ÁÁÁÁÁ

I/O2b

ÁÁÁÁÁ

33

ÁÁÁÁÁ

D2

ÁÁÁÁÁ

58

ÁÁÁÁÁÁ

I/O0g

ÁÁÁÁÁ

83

ÁÁÁÁÁ

A4

ÁÁÁÁÁ

9

ÁÁÁÁÁ

I/O3b

ÁÁÁÁÁ

34

ÁÁÁÁÁ

D3

ÁÁÁÁÁ

59

ÁÁÁÁÁÁ

RxDg

ÁÁÁÁÁ

84

ÁÁÁÁÁ

A3

ÁÁÁÁÁ

10

ÁÁÁÁÁ

TxDb

ÁÁÁÁÁ

35

ÁÁÁÁÁ

VSS

ÁÁÁÁÁ

60

ÁÁÁÁÁÁ

TxDg

ÁÁÁÁÁ

85

ÁÁÁÁÁ

IACKN

ÁÁÁÁÁ

11

ÁÁÁÁÁ

I/O0c

ÁÁÁÁÁ

36

ÁÁÁÁÁ

VSS

ÁÁÁÁÁ

61

ÁÁÁÁÁÁ

VSS

ÁÁÁÁÁ

86

ÁÁÁÁÁ

Sclk

ÁÁÁÁÁ

12

ÁÁÁÁÁ

VSS

ÁÁÁÁÁ

37

ÁÁÁÁÁ

VCC

ÁÁÁÁÁ

62

ÁÁÁÁÁÁ

VSS

ÁÁÁÁÁ

87

ÁÁÁÁÁ

VSS

ÁÁÁÁÁ

13

ÁÁÁÁÁ

VSS

ÁÁÁÁÁ

38

ÁÁÁÁÁ

VCC

ÁÁÁÁÁ

63

ÁÁÁÁÁÁ

X1

ÁÁÁÁÁ

88

ÁÁÁÁÁ

VSS

ÁÁÁÁÁ

14

ÁÁÁÁÁ

I/O1c

ÁÁÁÁÁ

39

ÁÁÁÁÁ

D4

ÁÁÁÁÁ

64

ÁÁÁÁÁÁ

X2

ÁÁÁÁÁ

89

ÁÁÁÁÁ

VCC

ÁÁÁÁÁ

15

ÁÁÁÁÁ

I/O2c

ÁÁÁÁÁ

40

ÁÁÁÁÁ

D5

ÁÁÁÁÁ

65

ÁÁÁÁÁÁ

TxDf

ÁÁÁÁÁ

90

ÁÁÁÁÁ

VCC

ÁÁÁÁÁ

16

ÁÁÁÁÁ

I/O3c

ÁÁÁÁÁ

41

ÁÁÁÁÁ

D6

ÁÁÁÁÁ

66

ÁÁÁÁÁÁ

I/O3f

ÁÁÁÁÁ

91

ÁÁÁÁÁ

CEN

ÁÁÁÁÁ

17

ÁÁÁÁÁ

TxDc

ÁÁÁÁÁ

42

ÁÁÁÁÁ

D7

ÁÁÁÁÁ

67

ÁÁÁÁÁÁ

I/O2f

ÁÁÁÁÁ

92

ÁÁÁÁÁ

W_RN

ÁÁÁÁÁ

18

ÁÁÁÁÁ

RxDc

ÁÁÁÁÁ

43

ÁÁÁÁÁ

GIN1

ÁÁÁÁÁ

68

ÁÁÁÁÁÁ

I/O1f

ÁÁÁÁÁ

93

ÁÁÁÁÁ

A2

ÁÁÁÁÁ

19

ÁÁÁÁÁ

I/O0d

ÁÁÁÁÁ

44

ÁÁÁÁÁ

GOUT1

ÁÁÁÁÁ

69

ÁÁÁÁÁÁ

I/O0f

ÁÁÁÁÁ

94

ÁÁÁÁÁ

A1

ÁÁÁÁÁ

20

ÁÁÁÁÁ

I/O1d

ÁÁÁÁÁ

45

ÁÁÁÁÁ

I/O3h

ÁÁÁÁÁ

70

ÁÁÁÁÁÁ

TxDe

ÁÁÁÁÁ

95

ÁÁÁÁÁ

JA0

ÁÁÁÁÁ

21

ÁÁÁÁÁ

I/O2d

ÁÁÁÁÁ

46

ÁÁÁÁÁ

I/O2h

ÁÁÁÁÁ

71

ÁÁÁÁÁÁ

I/O3e

ÁÁÁÁÁ

96

ÁÁÁÁÁ

DACKN

ÁÁÁÁÁ

22

ÁÁÁÁÁ

I/O3d

ÁÁÁÁÁ

47

ÁÁÁÁÁ

I/O1h

ÁÁÁÁÁ

72

ÁÁÁÁÁÁ

I/O2e

ÁÁÁÁÁ

97

ÁÁÁÁÁ

I/O0a

ÁÁÁÁÁ

23

ÁÁÁÁÁ

RxDd

ÁÁÁÁÁ

48

ÁÁÁÁÁ

I/O0h

ÁÁÁÁÁ

73

ÁÁÁÁÁÁ

I/O1e

ÁÁÁÁÁ

98

ÁÁÁÁÁ

I/O1a

ÁÁÁÁÁ

24

ÁÁÁÁÁ

N/C

ÁÁÁÁÁ

49

ÁÁÁÁÁ

VSS

ÁÁÁÁÁ

74

ÁÁÁÁÁÁ

RxDf

ÁÁÁÁÁ

99

ÁÁÁÁÁ

RxDa

ÁÁÁÁÁ

25

ÁÁÁÁÁ

N/C

ÁÁÁÁÁ

50

ÁÁÁÁÁ

VSS

ÁÁÁÁÁ

75

ÁÁÁÁÁÁ

N/C

ÁÁÁÁÁ

100

ÁÁÁÁÁ

N/C

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 6

Pin Description

ÁÁÁÁÁ

MNEMONIC

ÁÁÁ

TYPE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DESCRIPTION

ÁÁÁÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

SClk

ÁÁÁ

ÁÁ

Á

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Host system clock. Used to time operations in the Host Interface and clock internal logic. Must be greater

than twice the frequency of highest X1, Counter/T imer, TxC (1x) or RxC (1x) input frequency.

ÁÁÁÁÁ

CEN

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Chip select: Active low. When asserted, allows I/O access to OCTART registers by host CPU. W_RN signal

indicates direction. (Must not be active in IACKN cycle)

ÁÁÁÁÁ

A(7:0)

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address lines (A[6] is NOT used. See ”Host Interface” )

ÁÁÁÁÁ

D(7:0)

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8–bit bi–directional data bus. Carries command and status information between 28L198 and the host CPU.

Used to convey parallel data for serial I/O between the host CPU and the 28L198

ÁÁÁÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

W_RN

ÁÁÁ

ÁÁ

Á

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write Read not control: When high indicates that the host CPU will write to a 28L198 register or transmit FIFO.

When low, indicates a read cycle. 0 = Read; 1 = Write

ÁÁÁÁÁ

DACKN

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data Acknowledge: Active low. When asserted, it signals that the last transfer of the D lines is complete.

Open drain.

ÁÁÁÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

IRQN

ÁÁÁ

ÁÁ

Á

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Request: Active low. When asserted, indicates that the 28L198 requires service for pending inter-

rupt(s). Open drain.

ÁÁÁÁÁ

IACKN

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Acknowledge: Active low. When asserted, indicates that the host CPU has initiated an interrupt ac-

knowledge cycle. (Do not use CEN in an IACKN cycle)

ÁÁÁÁÁ

TD(a–h)

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmit Data: Serial outputs from the 8 UARTs.

ÁÁÁÁÁ

RD(a–h)

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receive Data: Serial inputs to the 8 UARTs

ÁÁÁÁÁ

I/O0(a–h)

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input/Output 0: Multi–use input or output pin for the UART.

ÁÁÁÁÁ

I/O1(a–h)

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input/Output 1: Multi–use input or output pin for the UART.

ÁÁÁÁÁ

I/O2(a–h)

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input/Output 2: Multi–use input or output pin for the UART.

ÁÁÁÁÁ

I/O3(a–h)

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input/Output 3: Multi–use input or output pin for the UART.

ÁÁÁÁÁ

GIN(1:0)

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Global general purpose inputs, available to any/all channels.

ÁÁÁÁÁ

GOUT0

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Global general purpose outputs, available from any channel.

ÁÁÁÁÁ

RESETN

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Master reset: Active Low. Must be asserted at power up and may be asserted at other times to reset and re-

start the system. See “Reset Conditions” at end of register map. Minimum width 10 SCLK.

ÁÁÁÁÁ

X1/CCLK

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Crystal 1 or Communication Clock: This pin may be connected to one side of a 2–8 MHz crystal. It may alter-

natively be driven by an external clock in this frequency range. Standard frequency = 3.6864 MHz

ÁÁÁÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁ

X2

ÁÁÁ

ÁÁ

Á

ÁÁÁ

O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Crystal 2: If a crystal is used, this is the connection to the second terminal. If a clock signal drives X1, this pin

must be left unconnected.

ÁÁÁÁÁ

Power Supplies

ÁÁÁ

I

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 pins total 6 pins for Vss, 2 pins for VCC

NOTE: Many output pins will have very fast edges, especially when lightly loaded (less than 20 pf.) These edges may move as fast as 1 to 3 ns

fall or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See

previous note on Sclk noise under pin assignments.

ABSOLUTE MAXIMUM RATINGS1

ÁÁÁÁÁÁ

SYMBOL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁÁ

RATING

ÁÁÁÁÁÁ

UNIT

ÁÁÁÁÁÁ

TA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Operating ambient temperature range2

ÁÁÁÁÁÁÁÁÁ

See Note 3

ÁÁÁÁÁÁ

ºC

ÁÁÁÁÁÁ

TSTG

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Storage temperature range

ÁÁÁÁÁÁÁÁÁ

–65 to +150

ÁÁÁÁÁÁ

ºC

ÁÁÁÁÁÁ

VCC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Voltage from VCC to Vss4

ÁÁÁÁÁÁÁÁÁ

–0.5 to +7.0

ÁÁÁÁÁÁ

V

ÁÁÁÁÁÁ

VSS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Voltage from any pin to Vss

ÁÁÁÁÁÁÁÁÁ

–0.5 to Vcc + 0.5

ÁÁÁÁÁÁ

V

ÁÁÁÁÁÁ

PD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Package Power Dissipation (PLCC)

ÁÁÁÁÁÁÁÁÁ

3.78

ÁÁÁÁÁÁ

W

ÁÁÁÁÁÁ

PD

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Package Power Dissipation (LQFP)

ÁÁÁÁÁÁÁÁÁ

2.08

ÁÁÁÁÁÁ

W

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Derate above 25 °C (PLCC pkg.)

ÁÁÁÁÁÁÁÁÁ

30

ÁÁÁÁÁÁ

mW/°C

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Derate above 25 °C (LQFP pkg.)

ÁÁÁÁÁÁÁÁÁ

17

ÁÁÁÁÁÁ

mW/°C

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is

not implied.

2. For operating at elevated temperatures, the device must be derated based on +150 °C maximum junction temperature.

3. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating

supply range.

4. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static

charge.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 7

BLOCK DIAGRAM

Block Diagram SC28C/28L198

HOST INTERFACE

TIMING AND BAUD RATE

GENERATOR

INTERRUPT ARBITRATION

I/O PORT TIMING AND

INTERFACE

FULL DUPLEX UART CHANNEL

INPUT BUFFERS AND OUTPUT DRIVERS

DATA DRIVERS AND MODEM INTERFACE

SD00193

As shown in the block diagram, the Octal UART consists of: an

interrupt arbiter, host interface, timing blocks and eight UART

channel blocks. The eight channels blocks operate independently,

interacting only with the timing, host I/F and interrupt blocks.

FUNCTIONAL DESCRIPTION

The SC28L198 is composed of several functional blocks:

•Synchronous host interface block

•A timing block consisting of a common baud rate generator

making 22 industry standard baud rates and 2 16–bit counters

used for non–standard baud rate generation

•4 identical independent full duplex UART channel blocks

•Interrupt arbitration system evaluating 24 contenders

•I/O port control section and change of state detectors.

CONCEPTUAL OVER VIEW

Host Interface

The Host interface is comprised of the signal pins CEN, W/RN,

IACKN, DACKN, IRQN Sclk and provides all the control for data

transfer between the external and internal data buses of the host

and the OCTART. The host interface operates in a synchronous

mode with the system (Sclk) which has been designed for a nominal

operating frequency of 33 MHz. The interface operates in either of

two modes; synchronous or asynchronous to the Sclk However

the bus cycle within the OCTART always takes place in four Sclk

cycles after CEN is recognized. These four cycles are the C1, C2,

C3, C4 periods shown in the timing diagrams. DACKN always

occurs in the C4 time and occurs approximately 18 ns after the

rising edge of C4.

Addressing of the various functions of the OCTART is through the

address bus A(7:0). The 28L198 is compatible with the SC28L198

OCTAL UART in software and function. A[7], in a general sense, is

used to separate the data portion of the circuit from the control

portion.

Asynchronous bus cycle

The asynchronous mode requires one bus cycle of the chip select

(CEN) for each read or write to the chip. No more action will occur

on the bus after the C4 time until CEN is returned high.

Synchronous bus cycle

In the synchronous mode a read or write will be done every four

cycles of the Sclk. CEN does not require cycling but must remain

low to keep the synchronous accesses active. This provides a burst

mode of access to the chip.

In both cases each read or write operation(s) will be completed in

four (4) Sclk cycles. The difference in the two modes is only that the

asynchronous mode will not begin another bus cycle if the CEN

remains active after the four internal Sclk have completed. Internally

the asynchronous cycle will terminate after the four periods of Sclk

regardless of how long CEN is held active

In all cases the internal action will terminate at the withdrawal of

CEN. Synchronous CEN cycles shorter than multiples of four Sclk

cycles minus 1 Sclk and asynchronous CEN cycles shorter than four

Sclk cycles may cause short read or write cycles and produce

corrupted data transfers.

Timing Circuits

The timing block consists of a crystal oscillator, a fixed baud rate

generator (BRG), a pair of programmable 16 bit register based

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 8

counters. A buffer for the System Clock generates internal timing for

processes not directly concerned with serial data flow.

Crystal Oscillator

The crystal oscillator operates directly from a crystal, tuned between

1.0 and 8.0 MHz, connected across the X1/CCLK and X2 inputs with

a minimum of external components. BRG values listed for the clock

select registers correspond to a 3.6864 MHz crystal frequency. Use

of a 7.3728 MHz crystal will double the Communication Clock

frequencies.

An external clock in the 100 KHz to 10 MHz frequency range may

be connected to X1/CCLK. If an external clock is used instead of a

crystal, X1/CCLK must be driven and X2 left floating. The X1 clock

serves as the basic timing reference for the baud rate generator

(BRG) and is available to the BRG timers . The X1 oscillator input

may be left unused if the internal BRG is not used and the X1 signal

is not selected for any counter input.

Sclk – System Clock

A clock frequency, within the limits specified in the electrical

specifications, must be supplied for the system clock Sclk. To

ensure the proper operation of internal controllers, the Sclk

frequency provided, must be strictly greater than twice the frequency

of X1 crystal clock, or any external 1x data clock input. The system

clock serves as the basic timing reference for the host interface and

other internal circuits.

Baud Rate Generator BRG

The baud rate generator operates from the oscillator or external

X1/CCLK clock input and is capable of generating 22 commonly

used data communications baud rates ranging from 50 to 230.4K

baud. These common rates may be doubled (up to 460.8 and 500K

baud) when faster clocks are used on the X1/X2 clock inputs. (See

Receiver and T ransmitter Clock Select Register descriptions.) All of

these are available simultaneously for use by any receiver or

transmitter. The clock outputs from the BRG are at 16X the actual

baud rate.

BRG Counters (Used for random baud rate generation)

The two BRG Timers are programmable 16 bit dividers that are used

for generating miscellaneous clocks. These clocks may be used by

any or all of the receivers and transmitters in the Octart or output on

the general purpose output pin GPO.

Each timer unit has eight different clock sources available to it as

described in the BRG T imer Control Register. (BRGTCR). Note

that the timer run and stop controls are also contained in this

register. The BRG Timers generate a symmetrical square wave

whose half period is equal in time to the division of the selected

BRG Timer clock source by the number loaded to the BRG Timer

Reload Registers ( BRGTRU and BRGTRL). Thus, the output

frequency will be the clock source frequency divided by twice the

value loaded to the BRGTRU and BRGTRL registers. This is the

result of counting down once for the high portion of the output wave

and once for the low portion.

Whenever the these timers are selected via the receiver or

transmitter Clock Select register their output will be configured as a

16x clock for the respective receiver or transmitter. Therefore one

needs to program the timers to generate a clock 16 times faster than

the data rate. The formula for calculating ’n’, the number loaded to

the BRGTRU and BRGTRL registers, is shown below.

n+ǒBRG Timer Input frequency

2@16 @desired baud rate Ǔ–1

Note: ’n’ may assume values of 0 and 1. In previous Philips data

communications controllers these values were not allowed.

The BRG timer input frequency is controlled by the BRG T imer

control register (BRGTCR)

The frequency generated from the above formula will be at a rate 16

times faster than the desired baud rate. The transmitter and

receiver state machines include divide by 16 circuits which provide

the final frequency and provide various timing edges used in the

qualifying the serial data bit stream. Often this division will result in

a non–integer value; 26.3 for example. One may only program

integer numbers to a digital divider. There for 26 would be chosen.

If 26.7 was the result of the division then 27 would be chosen. This

gives a baud rate error of 0.3/26.3 or 0.3/26.7. which yields a

percentage error of 1.14% or 1.12% respectively; well within the

ability of the asynchronous mode of operation.

One should be cautious about the assumed benign effects of small

errors since the other receiver or transmitter with which one is

communicating may also have a small error in the precise baud rate.

In a ”clean” communications environment using one start bit, eight

data bits and one stop bit the total difference allowed between the

transmitter and receiver frequency is approximately 4.6%. Less

than eight data bits will increase this percentage.

Channel Blocks

There are eight channel blocks, each containing an I/O port control,

a data format control, and a single full duplex UART channel

consisting of a receiver and a transmitter with their associated 16

byte FIFOs. Each block has its own status register, interrupt status

and interrupt mask registers and their interface to the interrupt

arbitration system.

A highly programmable character recognition system is also

included in each block. This system is used for the Xon/Xoff flow

control and the multi-drop (”9 bit mode”) address character

recognition. It may also be used for general purpose character

recognition.

Four I/O pins are provided for each channel. These pins are

configured individually to be inputs or outputs. As inputs they may

be used to bring external data to the bus, as clocks for internal

functions or external control signals. Each I/O pin has a ”Change of

State” detector. The change detectors are used to signal a change

in the signal level at the pin (Either 0 to 1 or 1 to 0). The level

change on these pins must be stable for 25 to 50 Us (two edges of

the 38.4 KHz baud rate clock) before the detectors will signal a valid

change. These are typically used for interface signals from modems

to the OCTART and from there to the host. See the description of

the ”UART channel” under detailed descriptions below.

Character Recognition

Character recognition is specific to each of the eight UARTs. Three

programmable characters are provided for the character recognition

for each channel. The three are general purpose in nature and may

be set to only cause an interrupt or to initiate some rather complex

operations specific to ”Multi-drop” address recognition or in–band

Xon/Xof f flow control.

Character recognition is accomplished via CAM memory. The

Content Addressable Memory continually examines the incoming

data stream. Upon the recognition of a control character appropriate

bits are set in the Xon/Xoff Interrupt Status Register (XISR) and

Interrupt Status Register (ISR). The setting of these bit(s) will

initiate any of the automatic sequences or and/or an interrupt that

may have enabled via the MR0 register.

The characters of the recognition system are not controlled by the

software or hardware reset. They do not have a pre-defined “reset

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 9

value”. They may, however , be loaded by a “Gang White” or “Gang

Load” command as described in the “Xon Xoff Characters”

paragraph.

Note: Character recognition is further described in the

Minor Modes

of Operation.

Interrupt Control

The interrupt system determines when an interrupt should be

asserted thorough an arbitration (or bidding) system. This

arbitration is exercised over the several systems within the OCTART

that may generate an interrupt. These will be referred to as

”interrupt sources”. There are 64 in all. In general the arbitration is

based on the fill level of the receiver FIFO or the empty level of the

transmitter FIFO. The FIFO levels are encoded into a four bit

number which is concatenated to the channel number and source

identification code. All of this is compared (via the bidding or

arbitration process) to a user defined ”threshold”. When ever a

source exceeds the numerical value of the threshold the interrupt

will be generated.

At the time of interrupt acknowledge (IACKN) the source which has

the highest bid (not necessarily the source that caused the interrupt

to be generated) will be captured in a ”Current Interrupt Register”

(CIR). This register will contain the complete definition of the

interrupting source: channel, type of interrupt (receiver, transmitter,

change of state, etc.), and FIFO fill level. The value of the bits in the

CIR are used to drive the interrupt vector and global registers such

that controlling processor may be steered directly to the proper

service routine. A single read operation to the CIR provides all the

information needed to qualify and quantify the most common

interrupt sources.

The interrupt sources for each channel are listed below.

•T ransmit FIFO empty level for each channel

•Receive FIFO Fill level for each channel

•Change in break received status for each channel

•Receiver with error for each channel

•Change of state on channel input pins

•Receiver W atch-dog Time–out Event

•Xon/Xof f character recognition

•Address character recognition

Associated with the interrupt system are the interrupt mask register

(IMR) and the interrupt status register (ISR) resident in each UART.

Programming of the IMR selects which of the above sources may

enter the arbitration process. Only the bidders in the ISR whose

associated bit in the IMR is set to one (1) will be permitted to enter

the arbitration process. The ISR can be read by the host CPU to

determine all currently active interrupting conditions. For

convenience the bits of the ISR may be masked by the bits of the

IMR. Whether the ISR is read unmasked or masked is controlled by

the setting of bit 6 in MR1.

Global Registers

The “Global Registers”, 19 in all, are driven by the interrupt system.

These are not real hardware devices. They are defined by the

content of the CIR (Current Interrupt Register) as a result of an

interrupt arbitration. In other words they are indirect registers

contained in the Current Interrupt Register (CIR) which the CIR uses

to point to the source and context of the OCTART sub circuit

presently causing an interrupt. The principle purpose of these

”registers” is improving the efficiency of the interrupt service.

The global registers and the CIR update procedure are further

described in the

Interrupt Arbitration

system

I/O Ports

Each of the eight UART blocks contains an I/O section of four ports.

These ports function as a general purpose post section which

services the particular UART they are associated with. External

clocks are input and internal clocks are output through these ports.

Each of the four pins has a change of state detector which will signal

a change (0 to 1 or 1 to 0) at the pin. The change of state detectors

are individually enabled and may be set to cause and interrupt.

These pins will normally be used for flow control hand–shaking and

the interface to a modem. Their control is further described in

I/O

Ports

section and the I/OPCR register.

DETAILED DESCRIPTIONS

RECEIVER AND TRANSMITTER

The Octal UART has eight full-duplex asynchronous

receiver/transmitters. The operating frequency for the receiver and

transmitter can be selected independently from the baud rate

generator, the counter , or from an external input. Registers that are

central to basic full-duplex operation are the mode registers (MR0,

MR1 and MR2), the clock select registers (RxCSR and TxCSR), the

command register (CR), the status register (SR), the transmit

holding register (TxFIFO), and the receive holding register

(RxFIFO).

Transmitter

The transmitter accepts parallel data from the CPU and converts it

to a serial bit stream on the TxD output pin. It automatically sends a

start bit followed by the programmed number of data bits, an

optional parity bit, and the programmed number of stop bits. The

least significant bit is sent first. Each character is always ”framed”

by a single start bit and a stop bit that is 9/16 bit time or longer. If a

new character is not available in the TxFIFO, the TxD output

remains high, the ”marking” position, and the TxEMT bit in the SR is

set to 1.

Transmitter Status Bits

The SR (Status Register, one per UART) contains two bits that show

the condition of the transmitter FIFO. These bits are TxRDY and

TxEMT. TxRDY means the TxFIFO has space available for one or

more bytes; TxEMT means The TxFIFO is completely empty and

the last stop bit has been completed. TxEMT can not be active

without TxRDY also being active. These two bits will go active upon

initial enabling of the transmitter. They will extinguish on the disable

or reset of the transmitter.

T ransmission resumes and the TxEMT bit is cleared when the CPU

loads at least one new character into the TxFIFO. The TxRDY will

not extinguish until the TxFIFO is completely full. The TxRDY bit will

always be active when the transmitter is enabled and there is at

lease one open position in the TxFIFO.

The transmitter is disabled by reset or by a bit in the command

register (CR). The transmitter must be explicitly enabled via the CR

before transmission can begin. Note that characters cannot be

loaded into the TxFIFO while the transmitter is disabled, hence it is

necessary to enable the transmitter and then load the TxFIFO. It is

not possible to load the TxFIFO and then enable the transmission.

Note the difference between transmitter disable and transmitter

reset. The transmitter may by reset by a hardware or software. The

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 10

software reset is issued through command 3x of the Command

register (CR). The disable is done by setting the transmitter disable

bit also in the command register. If the transmitter is disabled, it

continues operating until the character currently being transmitted, if

any, is completely sent, including the stop bit. When reset the

transmitter stops immediately, drives the transmitter serial data out

put to a high level and discards any data in the TxFIFO.

Transmission of “break”s

T ransmission of a break character is often needed as a

synchronizing condition in a data stream. The “break” is defined as a

start bit followed by all zero data bits by a zero parity bit (if parity is

enabled) and a zero in the stop bit position. The forgoing is the

minimum time to define a break. The transmitter can be forced to

send a break (continuous low condition) by issuing a start break

command via the CR. This command does not have any timing

associated with it. Once issued the TxD output will be driven low

(the spacing condition) and remain there until the host issues a

command to “stop break” via the CR or the transmitter is issued a

software or hardware reset. In normal operation the break is usually

much longer than one character time.

1x and 16x modes, Transmitter

The transmitter clocking has two modes: 16x and 1x. Data is

always sent at the 1x rate. However the logic of the transmitter may

be operated with a clock that is 16 times faster than the data rate or

at the same rate as the data i.e. 1x. All clocks selected internally

for the transmitter (and the receiver) will be 16x clocks. Only when

an external clock is selected may the transmitter logic and state

machine operate in the 1x mode. The 1x or 16x clocking makes

little dif ference in transmitter operation. (this is not true in the

receiver) In the 16X clock mode the transmitter will recognize a byte

in the TxFIFO within 1/16 to 2/16 bit time and thus begin

transmission of the start bit; in the 1x mode this delay may be up to

2 bit times.

Transmitter FIFO

The transmitter buffer memory is a 16 byte by 8 bit ripple FIFO. The

host writes characters to this buffer. This buffer accepts data only

when the transmitter is enabled. The transmitter state machine

reads them out in the order they were received and presents them to

the transmitter shift register for serialization. The transmitter adds

the required start, parity and stop bits as required the MR2 register

programming. The start bit (always one bit time in length) is sent

first followed by the least significant bit (LSB) to the most significant

bit (MSB) of the character, the parity bit (if used) and the required

stop bit(s).

Logic associated with the FIFO encodes the number of empty

positions available in a four bit value. This value is concatenated

with the channel number and type interrupt type identifier and

presented to the interrupt arbitration system. The encoding of the

”positions empty” value is always 1 less than the number of

available positions. Thus, an empty TxFIFO will bid with the value

or 15; when full it will not bid at all; one position empty bids with the

value 0. A full FIFO will not bid since a character written to it will be

lost

Normally a TxFIFO will present a bid to the arbitration system when

ever it has one or more empty positions. The MR0[5:4] allow the

user to modify this characteristic so that bidding will not start until

one of four levels (empty, 3/4 empty, 1/2 empty, not full) have been

reached. As will be shown later this feature may be used to make

slight improvements in the interrupt service efficiency. A similar

system exists in the receiver.

Receiver

The receiver accepts serial data on the RxD pin, converts the serial

input to parallel format, checks for start bit, stop bit, parity bit (if

any),framing error or break condition, and presents the assembled

character and its status condition to the CPU via the RxFIFO. Three

status bits are FIFOed with each character received. The RxFIFO is

really 11 bits wide; eight data and 3 status. Unused FIFO bits for

character lengths less than 8 bits are set to zero. It is important to

note that receiver logic considers the entire message to be

contained within the start bit to the stop bit. It is not aware that a

message may contain many characters. The receiver returns to its

idle mode at the end of each stop bit! As described below it

immediately begins to search for another start bit which is normally,

of course, immediately forth coming.

1x and 16x mode, Receiver

The receiver operates in one of two modes; 1x and 16x. Of the two,

the 16x is more robust and the preferred mode. Although the 1x

mode may allow a faster data rate is does not provide for the

alignment of the receiver 1x data clock to that of the transmitter.

This strongly implies that the 1x clock of the remote transmitter is

available to the receiver; the two devices are physically close to

each other.

The 16x mode operates the receiver logic at a rate 16 times faster

than the 1x data rate. This allows for validation of the start bit,

validation of level changes at the receiver serial data input (RxD),

and a stop bit length as short as 9/16 bit time. Of most importance

in the 16x mode is the ability of the receiver logic to align the phase

of the receiver 1x data clock to that of the transmitter with an

accuracy of less than 1/16 bit time.

When the receiver is enabled ( via the CR register) it begins looking

for a high to low (mark to space) transition on the RxD input pin. If a

transition is detected, an internal counter running at 16 times the

data rate is reset to zero. If the RxD remains low and is still low

when the counter reaches a count of 7 the receiver will consider this

a valid start bit and begin assembling the character. If the RxD input

returns to a high state the receiver will reject the previous high to low

(mark to space) transition on the RxD input pin. This action is the

”validation” of the start bit and also establishes the phase of the

receiver 1x clock to that of the transmitter The counter operating at

16x the data rate is the generator for the 1x data rate clock. With

the phase of the receiver 1x clock aligned to the falling of the start

bit (and thus aligned to the transmitter clock) AND with a valid start

bit having been verified the receiver will continue receiving bits by

sampling the RxD input on the rising edge of the 1x clock that is

being generated by the above mentioned counter running 16 times

the data rate. Since the falling edge of the 1x clock was aligned to

falling edge of the start bit then the rising of the clock will be in the

”center” of the bit cell.

This action will continue until a full character has been assembled.

Parity , framing, and stop bit , and break status is then assembled

and the character and its status bits are loaded to the RxFIFO At

this point the receiver has finished its task for that character and will

immediately begin the search for another start bit.

Receiver Status Bits

There are five (5) status bits that are evaluated with each byte (or

character) received: received break, framing error, parity error,

overrun error, and change of break. The first three are appended to

each byte and stored in the RxFIFO. The last two are not

necessarily related to the a byte being received or a byte that is in

the RxFIFO. They are however developed by the receiver state

machine

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 11

. The ”received break” will always be associated with a zero byte in

the RxFIFO. It means that zero character was a break character

and not a zero data byte. The reception of a break condition will

always set the ”change of break” (see below) status bit in the

Interrupt Status Register(ISR).

A framing error occurs when a non zero character was seen and

that character has a zero in the stop bit position.

The parity error indicates that the receiver generated parity was not

the same as that sent by the transmitter.

The overrun error occurs when the RxFIFO is full, the receiver shift

register is full and another start bit is detected. At this moment the

receiver has 17 valid characters and the start bit of the 18th has

been seen. At this point the host has approximately 7/16 bit time to

read a byte from the RxFIFO or the overrun condition will be set and

the 18th character will overrun the 17th and the 19th the 18th and so

on until an open position in the RxFIFO is seen. The meaning of the

overrun is that data has been lost. Data in the RxFIFO remains

valid. The receiver will begin placing characters in the RxFIFO as

soon as a position becomes vacant.

Note: Precaution must be taken when reading an overrun FIFO.

There will be 16 valid characters. Data will begin loading as soon as

the first character is read. The 17th. character will have been

received as valid but it will not be known how many characters were

lost between the two characters of the 16th. and 17th. reads of the

RxFIFO

The ”Change of break” means that either a break has been detected

or that the break condition has been cleared. This bit is available in

the ISR. The beginning of a break will be signaled by the break

change bit being set in the ISR AND the received break bit being set

in the SR. At the termination of the break condition only the change

of break in the ISR will be set. After the break condition is detected

the termination of the break will only be recognized when the RxD

input has returned to the high state for two successive edges of the

1x clock; 1/2 to 1 bit time.

The receiver is disabled by reset or via CR commands. A disabled

receiver will not interrupt the host CPU under any circumstance in

the normal mode of operation. If the receiver is in the multi-drop or

special mode, it will be partially enabled and thus may cause an

interrupt. Refer to section on W ake–Up and minor modes and the

register description for MR1 for more information.

Receiver FIFO

The receiver buffer memory is a 16 byte ripple FIFO with three

status bits appended to each data byte. (The FIFO is then 16 11 bit

”words”). The receiver state machine gathers the bits from the

receiver shift register and the status bits from the receiver logic and

writes the assembled byte and status bits to the RxFIFO. Logic

associated with the FIFO encodes the number of filled positions for

presentation to the interrupt arbitration system. The encoding is

always 1 less than the number of filled positions. Thus, a full

RxFIFO will bid with the value or 15; when empty it will not bit at all;

one position occupied bids with the value 0. An empty FIFO will not

bid since no character is available. Normally RxFIFO will present a

bid to the arbitration system when ever it has one or more filled

positions. The MR2[3:2 bits allow the user to modify this

characteristic so that bidding will not start until one of four levels

(one or more filled, 1/2 filled, 3/4 filled, full) have been reached. As

will be shown later this feature may be used to make slight

improvements in the interrupt service efficiency. A similar system

exists in the transmitter.

RxFIFO Status: Status reporting modes

The description below applies to the upper three bits in the ”Status

Register” These three bits are not ”in the status register”; They are

part of the RxFIFO. The three status bits at the top of the RxFIFO

are presented as the upper three bits of the status register included

in each UART.

The error status of a character , as reported by a read of the SR

(status register upper three bits) can be provided in two ways, as

programmed by the error mode control bit in the mode register:

”Character mode ” or the ”Block Mode”. The block mode may be

further modified (via a CR command) to set the status bits as the

characters enter the FIFO or as they are read from the FIFO.

In the ’character’ mode, status is provided on a character by

character basis as the characters are read from the RxFIFO: the

”status” applies only to the character at the top of the RxFIFO – The

next character to be read

In the ’block’ mode, the status provided in the SR for these three bits

is the logical OR of the status for all characters coming to the top of

the RxFIFO, since the last reset error command was issued. In this

mode each of the status bits stored in the RxFIFO are passed

through a latch as they are sequentially read. If any of the

characters has an error bit set then that latch will set and remain set

until reset with an ”Reset Error” command from the command

register or a receiver reset. The purpose of this mode is indicating

an error in the data block as opposed to an error in a character

The latch used in the block mode to indicate ”problem data” is

usually set as the characters are read out of the RxFIFO. Via a

command in the CR the latch may be configured to set the latch as

the characters are pushed (loaded to) the RxFIFO. This gives the

advantage of indicating ”problem data” 16 characters earlier .

In either mode, reading the SR does not affect the RxFIFO. The

RxFIFO is ’popped’ only when the RxFIFO is read. Therefore, the

SR should be read prior to reading the corresponding data

character.

If the RxFIFO is full when a new character is received, that

character is held in the receive shift register until a RxFIFO position

is available. At this time there are 17 valid characters in the

RxFIFO. If an additional character is received while this state exists,

the contents of the RxFIFO are not affected: the character

previously in the shift register is lost and the overrun error status bit,

SR[4], will be set upon receipt of the start bit of the new

(overrunning) character .

I/O ports

Each of the eight UARTs includes four I/O ports equipped with

”change of state” detectors. The pins are individually programmable

for an input only function or one of three output functions. These

functions are controlled by the ”I/O Port Configuration Register

(I/OPCR)) They will normally be used for the RTSN–CTSN, DTR

hardware signals, RxD or TxD input or output clocks or switch inputs

as well as data out put from the I/OPIOR register.

It is important to note that the input circuits are always active. That

is the signal on a port, whether it is derived from an internal or

external source is always available to the internal circuits associated

with an input on that port.

The ”Change of State” (COS) detectors are sensitive to both a 1 to 0

or a 0 to 1 transition. The detectors are controlled by the internal

38.4 KHz baud rate and will signal a change when a transition has

been stable for two rising edges of this clock. Thus a level on the

I/O ports must be stable for 26 s to 52 s. Defining a port as an

output will disable the COS detector at that port. The condition of

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 12

the four I/O pins and their COS detectors is available at any time in

the IPR (Input Port Register)

The control of data and COS enable for these ports is through the

I/OPIOR register. This is a read/write register and gives individual

control to the enabling of the change of state detectors and also to

the level driven by I/O pins when programmed to drive the logic level

written to the four lower bits of the I/OPIOR. A read of this register

will indicate the data on the pin at the time of the read and the state

of the enabled COS detectors.

General Purpose Pins

In addition to the I/O ports for each UART four other ports are

provided which service the entire chip. Two are dedicated as inputs

and one as an output. The GIN1 and GIN0 are the input pins; GOUT0

the output. These ports are multiplexed to nearly every functional

unit in the chip. See the registers which describe the multitude of

connections available for these pins. The GOUT0 pin is highly

multiplexed output and is controlled by four (4) registers: GPOSR,

GPOR, GPOC and GPOD. The GIN0 and GIN1 pins are available to

the receivers and transmitters, BRG counters and the GOUT0 pin.

Global Registers

The ”Global Registers”, 19 in all, are driven by the interrupt system.

These are not real hardware devices. They are defined by the

content of the CIR (Current Interrupt Register) as a result of an

interrupt arbitration. In other words they are indirect registers

pointed to by the content of the CIR. The list of global register

follows:

GIBCR The byte count of the interrupting FIFO

GICR Channel number of the interrupting channel

GITR Type identification of interrupting channel

GRxFIFO Pointer to the interrupting receiver FIFO

GTxFIFO Pointer to the interrupting transmitter FIFO

A read of the GRxFIFO will give the content of the RxFIFO that

presently has the highest bid value. The purpose of this system is

to enhance the efficiency of the interrupt system. The global

registers and the CIR update procedure are further described in the

Interrupt Arbitration

system

Character Recognition

The character recognition circuits are basically designed to provide

general purpose character recognition. Additional control logic has

been added to allow for Xon/Xoff flow control and for recognition of

the address character in the multi-drop or ”wake–up” mode. This

logic also allows for the generation of an interrupts in either the

general purpose recognition mode or the specific conditions

mentioned above.

Xon Xoff Characters

The programming of these characters is usually done individually.

However a method has been provided to write to all of registers in

one operation. There are ”Gang Load” and a ”Gang Write”

commands provided in the channel A Command Register. When

these commands are executed all registers are programmed with

the same characters. The ”write” command loads a used defined

character; the ’load” command loads the standard Xon/Xoff

characters. Xon is x’11; Xoff x’13’. Any enabling of the Xon/Xof f

functions will use the contents of the Xon and Xoff character

registers as the basis on which recognition is predicated.

Multi-drop or W ake up or 9 bit mode

This mode is used to address a particular UART among a group

connected to the same serial data source. Normally it is

accomplished by redefining the meaning of the parity bit such that it

indicates a character as address or data. While this method is fully

supported in the SC28L198 it also supports recognition of the

character itself. Upon recognition of its address the receiver will be

enabled and data pushed onto the RxFIFO.

Further the Address recognition has the ability, if so programmed, to

disable (not reset) the receiver when an address is seen that is not

recognized as its own. The particular features of ”Auto W ake and

Auto Doze” are described in the detail descriptions below.

Note: Care should be taken in the programming of the character

recognition registers. Programming x’00, for example, may result in

a break condition being recognized as a control character. This will

be further complicated when binary data is being processed.

Character Stripping

The MR0 register provides for stripping the characters used for

character recognition. Recall that the character recognition may be

conditioned to control several aspects of the communication.

However this system is first a character recognition system. The

status of the various states of this system are reported in the XISR

and ISR registers. The character stripping of this system allows for

the removal of the specified control characters from the data stream:

two for the Xon /Xoff and one for the wake up. Via control in the

MR0 register these characters may be discarded (stripped) from the

data stream when the recognition system “sees” them or they may

be sent on the RxFIFO. Whether they are stripped or not the

recognition will process them according to the action requested: flow

control, wake up, interrupt generation, etc. Care should be

exercised in programming the stripping option if noisy environments

are encountered. If a normal character was corrupted to an Xoff

character turned off the transmitter and it was then stripped, then the

stripping action could make it difficult to determine the cause of

transmitter stopping.

Interrupt Arbitration and IRQN generation

Interrupt arbitration is the process used to determine that an

interrupt request should be presented to the host. The arbitration is

carried out between the ”Interrupt Threshold” and the ”sources”

whose interrupt bidding is enabled by the IMR. The interrupt

threshold is part of the ICR (Interrupt Control Register) and is a

value programmed by the user. The ”sources” present a value to

the interrupt arbiter. That value is derived from four fields: the

channel number, type of interrupt source, FIFO fill level, and

programmable value. . Only when one or more of these values

exceeds the threshold value in the interrupt control register will the

interrupt request (IRQN) be asserted.

Following assertion of the IRQN the host will either assert

IACKN(Interrupt Acknowledge) or will use the command to ”Update

the CIR”. At the time either action is taken the CIR will capture the

value of the source that is prevailing in the arbitration process. (Call

this value the winning bid)

The value in the CIR is the central quantity that results from the

arbitration. It contains the identity of the interrupting channel, the

type of interrupt in that channel (RxD, TxD, COS etc.) the fill levels

of the RxD or TxD FIFOs and , in the case of an RxD interrupt an

indicator of error data or good data. It also drives the Global

Registers associated with the interrupt. Most importantly it drives

the modification of the Interrupt Vector.

The arbitration process is driven by the Sclk. It scans the 10 bits of

the arbitration bus at the Sclk rate developing a value for the CIR

every 22 Sclk cycles. New arbitration values presented to the

arbitration block during an arbitration cycle will be evaluated in the

next arbitration cycle.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 13

For sources other than receiver and transmitters the user may set

the high order bits of an interrupt source’s bid value, thus tailoring

the relative priority of the interrupt sources. The priority of the

receivers and transmitters is controlled by the fill level of their

respective FIFOs. The more filled spaces in the RxFIFO the higher

the bid value; the more empty spaces in the TxFIFO the higher its

priority. Channels whose programmable high order bits are set will

be given interrupt priority higher than those with zeros in their high

order bits , thus allowing increased flexibility. The transmitter and

receiver bid values contain the character counts of the associated

FIFOs as high order bits in the bid value. Thus, as a receiver’s

RxFIFO fills, it bids with a progressively higher priority for interrupt

service. Similarly, as empty space in a transmitter’s TxFIFO

increases, its interrupt arbitration priority increases.

IACKN Cycle, Update CIR

When the host CPU responds to the interrupt, it will usually assert

the IACKN signal low. This will cause the OCTART to generate an

IACKN cycle in which the condition of the interrupting device is

determined. When IACKN asserts, the last valid interrupt number is

captured in the CIR. The value captured presents most of the

important details of the highest priority interrupt at the moment the

IACKN (or the ”Update CIR” command) was asserted.

The Octal UART will respond to the IACKN cycle with an interrupt

vector. The interrupt vector may be a fixed value, the content of the

Interrupt Vector Register , or ,when ”Interrupt Vector Modification is

enabled via ICR, it may contain codes for the interrupt type and/or

interrupting channel. This allows the interrupt vector to steer the

interrupt service directly to the proper service routine. The interrupt

value captured in the CIR remains until another IACKN cycle occurs

or until an ”Update CIR” command is given to the OCTART. The

interrupting channel and interrupt type fields of the CIR set the

current ”interrupt context” of the OCTART. The channel component

of the interrupt context allows the use of Global Interrupt Information

registers that appear at fixed positions in the register address map.

For example, a read of the Global RxFIFO will read the channel B

RxFIFO if the CIR interrupt context is channel b receiver. At another

time read of the GRxFIFO may read the channel D RxFIFO (CIR

holds a channel D receiver interrupt) and so on. Global registers

exist to facilitate qualifying the interrupt parameters and for writing to

and reading from FIFOs without explicitly addressing them.

The CIR will load with x’00 if IACKN or Update CIR is asserted when

the arbitration circuit is NOT asserting and interrupt. In this

condition there is no arbitration value that exceeds the threshold

value.

Polling

Many users prefer polled to interrupt driven service where there are

a large number of fast data channels and/or the host CPU’s other

interrupt overhead is low. The Octal UART is functional in this

environment.

The most efficient method of polling is the use of the ”update CIR”

command (with the interrupt threshold set to zero) followed by a

read of the CIR. This dummy write cycle will perform the same CIR

capture function that an IACKN falling edge would accomplish in an

interrupt driven system. A subsequent read of the CIR, at the same

address, will give information about an interrupt, if any. If the CIR

contains 0s, no interrupt is awaiting service. If the value is

non–zero, the fields of the CIR may be decoded for type, channel

and character count information. Optionally, the global interrupt

registers may be read for particular information about the interrupt

status or use of the global RxD and TxD registers for data transfer

as appropriate. The interrupt context will remain in the CIR until

another update CIR command or an IACKN cycle is initiated by the

host CPU occurs. The CIR loads with x’00 if Update CIR is asserted

when the arbitration circuit has NOT detected arbitration value that

exceeds the threshold value.

T raditional methods of polling status registers may also be used.

They of course are less efficient but give the most variable and

quickest method of changing the order in which interrupt sources

are evaluated and interrogated.

Enabling and Activating Interrupt sources

An interrupt source becomes enabled when its interrupt capability is

set by writing to the Interrupt Mask Register, IMR. An interrupt

source can never generate an IRQN or have its ”bid” or interrupt

number appear in the CIR unless the source has been enabled by

the appropriate bit in an IMR.

An interrupt source is active if it is presenting its bid to the interrupt

arbiter for evaluation. Most sources have simple activation

requirements. The watch-dog timer, break received, Xon/Xoff or

Address Recognition and change of state interrupts become active

when the associated events occur and the arbitration value

generated thereby exceeds the threshold value programmed in the

ICR (Interrupt Control Register).

The transmitter and receiver functions have additional controls to

modify the condition upon which the initiation of interrupt ”bidding”

begins: the TxINT and RxINT fields of the MR0 and MR2 registers.

These fields can be used to start bidding or arbitration when the

RxFIFO is not empty, 50% full, 75% full or 100% full. For the

transmitter it is not full, 50% empty, 75% empty and empty.

Example: To increase the probability of transferring the contents of a

nearly full RxFIFO, do not allow it to start bidding until 50% or 75%

full. This will prevent its relatively high priority from winning the

arbitration process at low fill levels. A high threshold level could

accomplish the same thing, but may also mask out low priority

interrupt sources that must be serviced. Note that for fast channels

and/or long interrupt latency times using this feature should be used

with caution since it reduces the time the host CPU has to respond

to the interrupt request before receiver overrun occurs.

Setting Interrupt Priorities

The bid or interrupt number presented to the interrupt arbiter is

composed of character counts, channel codes, fixed and

programmable bit fields. The interrupt values are generated for

various interrupt sources as shown in the table below: The value

represented by the bits 9 to 3 in the table below are compared

against the value represented by the “Threshold. The “Threshold”

,bits 6 to 0 of the ICR (Interrupt Control Register), is aligned such

that bit 6 of the threshold is compared to bit 9 of the interrupt value

generated by any of the sources. When ever the value of the

interrupt source is greater than the threshold the interrupt will be

generated.

The channel number arbitrates only against other channels. The

threshold is not used for the channel arbitration. This results in

channel D having the highest arbitration number. The decreasing

order is H to A. If all other parts of an arbitration are equal then the

channel number will determine which channel will dominate in the

arbitration process

.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 14

Table 1. Interrupt Arbitration Priority

ÁÁÁÁÁÁÁÁÁÁ

Type

ÁÁÁÁ

B9

ÁÁÁ

B8

ÁÁÁÁ

B7

ÁÁÁ

B6

ÁÁÁÁ

B5

ÁÁÁ

B4

ÁÁÁÁ

B3

ÁÁÁÁÁÁÁ

Bits 2:0

ÁÁÁÁÁÁÁÁÁÁ

Receiver w/o error

ÁÁÁÁÁÁÁÁÁÁÁ

RxFIFO Byte Count –1

ÁÁÁÁ

0

ÁÁÁ

0

ÁÁÁÁ

1

ÁÁÁÁÁÁÁ

Channel No

ÁÁÁÁÁÁÁÁÁÁ

Receiver w/ error

ÁÁÁÁÁÁÁÁÁÁÁ

RxFIFO Byte Count –1

ÁÁÁÁ

1

ÁÁÁ

0

ÁÁÁÁ

1

ÁÁÁÁÁÁÁ

Channel No

ÁÁÁÁÁÁÁÁÁÁ

Transmitter

ÁÁÁÁ

0

ÁÁÁÁÁÁÁÁÁÁÁ

TxFIFO Byte Count –1

ÁÁÁ

0

ÁÁÁÁ

0

ÁÁÁÁÁÁÁ

Channel No

ÁÁÁÁÁÁÁÁÁÁ

Change of Break

ÁÁÁÁÁÁÁÁÁ

Programmed Field

ÁÁÁ

0

ÁÁÁÁ

0

ÁÁÁ

1

ÁÁÁÁ

0

ÁÁÁÁÁÁÁ

Channel No

ÁÁÁÁÁÁÁÁÁÁ

Change of State

ÁÁÁÁÁÁÁÁÁ

Programmed Field

ÁÁÁ

0

ÁÁÁÁ

1

ÁÁÁ

1

ÁÁÁÁ

0

ÁÁÁÁÁÁÁ

Channel No

ÁÁÁÁÁÁÁÁÁÁ

Xon/Xoff

ÁÁÁÁÁÁÁÁÁ

Programmed Field

ÁÁÁ

0

ÁÁÁÁ

1

ÁÁÁ

1

ÁÁÁÁ

1

ÁÁÁÁÁÁÁ

Channel No

ÁÁÁÁÁÁÁÁÁÁ

Address Recognition

ÁÁÁÁÁÁÁÁÁ

Programmed Field

ÁÁÁ

0

ÁÁÁÁ

0

ÁÁÁ

1

ÁÁÁÁ

1

ÁÁÁÁÁÁÁ

Channel No

ÁÁÁÁÁÁÁÁÁÁ

Receiver W atch-dog

ÁÁÁÁÁÁÁÁÁÁÁ

RxFIFO Byte Count –1

ÁÁÁÁÁÁÁÁÁ

As RxFIFO Above

ÁÁÁÁÁÁÁ

Channel No

ÁÁÁÁÁÁÁÁÁÁ

Threshold

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 6:0 of Interrupt Control Register

ÁÁÁÁÁÁÁ

000

Note several characteristics of the above table in bits 6:3. These

bits contain the identification of the bidding source as indicated

below:

x001 Receiver without error

x101 Receiver with error

xx00 Transmitter

0010 Change of Break

0110 Change of State on I/O Ports

0111 Xon/Xof f Event

0011 Address Recognition

The codes form bits 6:3 drive part of the interrupt vector modification

and the Global Interrupt Type Register. The codes are unique to

each source type and Identify them completely. The channel

numbering progresses from ”a” to ”d” as the binary numbers 000 to

011 and identify the interrupting channel uniquely. As the channels

arbitrate ”d” will have the highest bidding value and ”a” the lowest

Note that the transmitter byte count is off–set from that of the

receiver by one bit. This is to give the receiver more authority in the

arbitration since and over–run receiver corrupts the message but an

under–run transmitter is not harmful. This puts some constraints on

how the threshold value is selected. If a threshold is chosen that

has its MSB set to one then a transmitter can never generate an

interrupt! Of course the counter point to this is the desire to set the

interrupt threshold high so interrupts occur only when a maximum or

near maximum number of characters may be transferred.

To give some control over this dilemma control bits have been

provided in the MR0 and MR2 registers of each channel to

individually control when a receiver or transmitter may interrupt. The

use of these bits will prevent a receiver or a transmitter from

entering the arbitration process even though its FIFO fill level is

above that indicated by the threshold value set. The bits in the MR0

and MR2 register are named TxINT (MR0[5:4]) and RxINT

(MR2[3:2])

The watch-dog is included in the table above to show that it affects

the arbitration. It does not have an identity of its own. A barking

watch-dog will prevent any other source type from entering the

arbitration process except enabled receivers. The threshold is

effectively set to zero when any watch-dog times out. The receivers

arbitrate among them selves and the one with the highest fill level

will win the process. Note that the receiver wining the bid may not

be the one that caused the watch-dog to bark.

The fields labeled ”Programmed Field” are the contents of the

Bidding Control Registers, BCRs, for these sources. Setting these

bits to high values can elevate the interrupt importance of the

sources they represent to values almost as high as a full receiver.

For example a COS event may be very important when it represents

the DSR (Data Set Ready) signal from the modem. In this case its

arbitration value should be high. Once the DSR is recognized then

its arbitration value could be reduced or turned off.

There is a single arbiter interrupt number that is not associated with

any of the UART channels. It is the ”Threshold Value” and is

comprised of 7 bits from the Interrupt Control Register, ICR, and

three zeros in the channel field. It is only when one or more of

the enabled interrupt sources generates a arbitration value

larger than the threshold value that the IRQN will be asserted.

When the threshold bidding value is larger than any other bidding

value then the IRQN will be withdrawn. In this condition the CIR will

be loaded with if the IRQN or ”Update CIR” command is asserted.

Because the channels are numbered from 0 to 3 ( A to D) channel 3

will win the bid when all other parts of the bid are equal.

Note: Based on this coding for the receiver and transmitter, a

transmitter would not win a bid in the situation where the Count

Field = 0 unless the threshold value is equal or less than

0000011. A single empty slot is left in the TxFIFO or a single

filled slot in the RxFIFO will bid with a value of zero.

MODES OF OPERATION

Major Modes

Four major modes of operation (normal, auto echo, local loop back

and remote loop back) are provided and are controlled by MR2[7:6].

Three of these may be considered diagnostic. See the MR2 register

description.

The normal mode is the usual mode for data I/O operation. Most

reception and transmission will use the normal mode.

In the auto echo mode, the transmitter automatically re-transmits

any character captured by the channel’s receiver. The receiver 1x

clock is used for the transmitter. This mode returns the received

data back to the sending station one bit time delayed from its

departure. Receiver to host communication is normal. Host to

transmitter communication has no meaning.

In the local loop back mode (used for diagnostic purposes) the

transmitter is internally connected to the receiver input. The

transmitter 1x clock used for the receiver. The RxD input pin is

ignored and the transmitter TxD output pin is held high. This

configuration allows the transmitter to send data to the receiver

without any external parameters to affect the transmission of data.

All status bits, interrupt conditions and processor interface operate

normally. It is recommended that this mode be used when

initially verifying processor to UART interface. The

communication between the transmitter and receiver is entirely

within the UART – it is essentially ”talking to itself”.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 15

The remote loop back mode (also used for diagnostic purposes) is

similar to auto echo except that the characters are not sent to the

local CPU, nor is the receiver status updated. The received data is

sent directly to the transmitter where it is sent out on the TxD output.

The received data is not sent to the receive FIFO and hence the

host will not normally be participating in any diagnostics.

Minor Modes

The minor modes provide additional features within the major

modes. In general the minor modes provide a reduction in the

control burden and a less stringent interrupt latency time for the host

processor. These modes could be invoked in all of the major

modes.. However it may not be reasonable in many situations.

W atch-dog T imer T ime–out Mode

Each receiver in the Octal UART is equipped with a watch-dog timer

that is enabled by the ”W atch-dog Timer Enable Register (WTER).

The watch-dog ”barks” (times out) if 64 counts of the receiver clock

(64 bit times) elapse with no RxFIFO activity. RxFIFO events are a

read of the RxFIFO or GRxFIFO, or the push of a received character

into the RxFIFO. The timer resets when the (G)RxFIFO is read or if

another character is pushed into the RxFIFO. The receiver

watch-dog timer is included to allow detection of the very last

character(s) of a received message that may be waiting in the

RxFIFO, but are too few in number to successfully initiate an

interrupt. The watch-dog timer is enabled for counting if the

channel’s bit in the Watch Dog Timer Control Register (WDTCR) is

set. Note: a read of the GRxFIFO will reset the watch-dog timer of

only the channel specified in the current interrupt context. Other

watch-dogs are unaffected.

The watch-dog timer may generate an input to the interrupt arbiter if

IMR[6] is set. The status of the W atch-dog timer can be seen as Bit

6 of the Interrupt Status Register, ISR[6]. When a W atch-dog timer

that is programmed to generate an interrupt times out it enters the

arbitration process. It will then only allow receivers to enter the

enter the arbitration. All other sources are bidding sources are

disabled. The receivers arbitrate only amongst themselves.. The

receiver only interrupt mode of the interrupt arbiter continues until

the last watch-dog timer event has been serviced. While in the

receiver only interrupt mode, the control of the interrupt threshold

level is also disabled. The receivers arbitrate only between

themselves. The threshold value is ignored. The receiver with the

most FIFO positions filled will win the bid. Hence the user need not

reduce the bidding threshold level in the ICR to see the interrupt

from a nearly empty RxFIFO that may have caused the watch-dog

time–out.

Note: When any watch-dog times our only the receivers arbitrate.

There is no increase in the probability of receiver being serviced

causing the overrun of another receiver since they will still have

priority based upon received character count.

The interrupt will be cleared automatically upon the push of the next

character received or when the RxFIFO or GRxFIFO is read. The

ICR is unaffected by the watch-dog time–out interrupt and normal

interrupt threshold level sensing resumes after the last watch-dog

timer event has been processed. If other interrupt sources are

active, the IRQN pin may remain low.

W ake Up Mode

The SC28L198 provides two modes of this common asynchronous

“party line” protocol: the new automatic mode with 3 sub modes and

the default Host operated mode. The automatic mode has several

sub modes (see below). In the full automatic the internal state

machine devoted to this function will handle all operations

associated with address recognition, data handling, receiver enables

and disables. In both modes the meaning of the parity bit is

changed. It is often referred to as the A/D bit or the address/data

bit. It is used to indicate whether the byte presently in the receiver

shift register is an ”address” byte or a ”data” byte. ”1” usually means

address; ”0” data.

Its purpose is to allow several receivers connected to the same data

source to be individually addressed. Of course addressing could be

by group also. Normally the ”Master” would send an address byte to

all receivers ”listening” The receiver would then recognize its

address and enable itself receiving the following data stream. Upon

receipt of an address not its own it would then disable itself. As

descried below appropriate status bits are available to describe the

operation.

Enabling the W ake Up mode

This mode is selected by programming bits MR1[4:3] to ’11’. The

sub modes are controlled by bits 6, 1, 0 in the MR0 register. Bit 6

controls the loading of the address byte to the RxFIFO and MR0[1:0]

determines the sub mode as shown in the following table.

MR0[1:0] = 00 Normal W ake Up Mode (default). Host controls

operation via interrupts and commands written to

the command register (CR).

MR0[1:0] = 01 Auto wake. Enable receiver on address

recognition for this station. Upon recognition of

its assigned address, in the Auto W ake mode,

the local receiver will be enabled and normal

receiver communications with the host will be

established.

MR0[1:0] = 10 Auto Doze. Disable receiver on address

recognition, not for this station. Upon recognition

of an address character that is not its own, in the

Auto Doze mode, the receiver will be disabled

and the address just received either discarded or

pushed to the RxFIFO depending on the

programming of MR0[6].

MR0[1:0] = 11 Auto wake and doze. Both modes above. The

programming of MR0[1:0] to 11 will enable both

the auto wake and auto doze features.

The enabling of the wake–up mode executes a partial enabling

of the receiver state machine. Even though the receiver has

been reset the wake up mode will over ride the disable and

reset condition.

Normal W ake up (The default configuration)

In the default configuration for this mode of operation, a ’master’

station transmits an address character followed by data characters

for the addressed ’slave’ station. The slave stations, whose

receivers are normally disabled (not reset), examine the received

data stream and interrupts the CPU (by setting RxRDY) only upon

receipt of an address character. The CPU (host) compares the

received address to its station address and enables the receiver if it

wishes to receive the subsequent data characters. Upon receipt of

another address character, the CPU may disable the receiver to

initiate the process again

. A transmitted character consists of a start bit, the programmed

number of data bits, an address/data (A/D) bit, and the programmed

number of stop bits. The polarity of the transmitted A/D bit is

selected by the CPU by programming bit MR1[2]. MR1[2] = 0

transmits a zero in the A/D bit position which identifies the

corresponding data bits as data. MR1[2] = 1 transmits a one in the

A/D bit position which identifies the corresponding data bits as an

address. The CPU should program the mode register prior to

loading the corresponding data bytes into the TxFIFO.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 16

While in this mode, the receiver continuously looks at the received

data stream, whether it is enabled or disabled. If disabled, it sets

the RxRDY status bit and loads the character into the RxFIFO if the

received A/D bit is a one, but discards the received character if the

received A/D bit is a zero. If the receiver is enabled, all received

characters are transferred to the CPU via the RxFIFO. In either

case, the data bits are loaded into the data FIFO while the A/D bit is

loaded into the status FIFO position normally used for parity error

(SR[5]). Framing error, overrun error, and break detect operate

normally whether or not the receiver is enabled.

Automatic operation, Wake Up & Doze

The automatic configuration for this mode uses on-board

comparators to examine incoming address characters. Each UART

channel may be assigned a unique address character. See the

address register map and the description of the Address

Recognition Character Register (ARCR). The device may be

programmed to automatically awaken a sleeping receiver and/or

disable an active receiver based upon address characters received.

The operation of the basic receiver is the same as described above

for the default mode of wake–up operation except that the CPU

need not be interrupted to make a change in the receiver status.

Three bits in the Mode Register 0, (MR0), control the address

recognition operation. MR0[6] controls the RxFIFO operation of the

received character; MR0[1:0] controls the wake up mode options. If

MR0[6] is set the address character will be pushed onto the

RxFIFO, otherwise the character will be discarded. (The charter is

stripped from the data stream) The MR0[1:0] bits set the options as

follows: A b’00 in this field, the default or power–on condition, puts

the device in the default (CPU controlled) wake up mode of

operation as described above. The auto–wake mode, enabled if

MR0[0] is set, will cause the dedicated comparators to examine

each address character presented by the receiver. If the received

character matches the reference character in ARCR, the receiver

will be enabled and all subsequent characters will be FIFOed until

another address event occurs or the host CPU disables the receiver

explicitly. The auto doze mode, enabled if MR0[1] is set, will

automatically disable the receiver if an address is received that does

not match the reference character in the ARCR.

The UART channel can present the address recognition event to the

interrupt arbiter for IRQN generation. The IRQN generation may be

masked by setting bit 5 of the Interrupt Mask Register, IMR. The bid

level of an address recognition event is controlled by the Bidding

Control Register, BCRA, of the channel.

Note: To ensure proper operation, the host CPU must clear any

pending Address Recognition interrupt before enabling a disabled

receiver operating in the Special or W ake–up mode. This may be

accomplished via the CR commands to clear the Address Interrupt

or by resetting the receiver.

Xon/Xoff Operation

Receiver Mode

Since the receiving FIFO resources in the Octal UART are limited,

some means of controlling a remote transmitter is desirable in order

to lessen the probability of receiver overrun. The Octal UART

provides two methods of controlling the data flow. A hardware

assisted means of accomplishing control, the so–called out–of–band

flow control, and an in–band flow control method.

The out–of–band flow control is implemented through the

CTSN–RTSN signaling via the I/O ports. The operation of these

hardware handshake signals is described in the receiver and

transmitter discussions.

In–band flow control is a protocol for controlling a remote transmitter

by embedding special characters within the message stream, itself.

Two characters, Xon and Xoff, which do not represent normal

printable characters take on flow control definitions when the

Xon/Xof f capability is enabled. Flow control characters received

may be used to gate the channel transmitter on and off. This activity

is referred to as Auto–transmitter mode. To protect the channel

receiver from overrun, fixed fill levels (hardware set at 12

characters) of the RxFIFO may be employed to automatically insert

Xon/Xof f characters in the transmitter’s data stream. This mode of

operation is referred to as auto–receiver mode. Commands issued

by the host CPU via the CR can simulate all these conditions.

Auto–transmitter mode

When a channel receiver pushes an Xoff character into the RxFIFO,

the channel transmitter will finish transmission of the current

character and then stop transmitting. A transmitter so idled can be

restarted by the receipt of an Xon character by the receiver, or by a

hardware or software reset. The last option results in the loss of the

un–transmitted contents of the TxFIFO. When operating in this

mode the Command Register commands for the transmitter are not

effective.

While idle data may be written to the TxFIFO and it continues to

present its fill level to the interrupt arbiter and maintains the integrity

of its status registers.

Use of ’00’ as an Xon/Xoff character is complicated by the Receiver

break operation which pushes a ’00’ character on the RxFIFO. The

Xon/Xof f character detectors do not discriminate this case from an

Xon/Xof f character received through the RxD pin.

Note: To be recognized as an Xon or Xoff character, the receiver

must have room in the RxFIFO to accommodate the character. An

Xon/Xof f character that is received resulting in a receiver overrun

does not effect the transmitter nor is it pushed into the RxFIFO,

regardless of the state of the Xon/Xoff transparency bit, MR0(7).

Note: Xon /Xoff characters

The Xon/Xof f characters with errors will be accepted as valid. The

user has the option sending or not sending these characters to the

FIFO. Error bits associated with Xon/Xoff will be stored normally to

the receiver FIFO.

The channel’ s transmitter may be programmed to automatically

transmit an Xoff character without host CPU intervention when the

RxFIFO fill level exceeds a fixed limit (12). In this mode, it will

conversely transmit an Xon character when the RxFIFO level drops

below a second fixed limit (8). A character from the TxFIFO that has

been loaded into the TxD shift register will continue to transmit.

Character(s) in the TxFIFO that have not been popped are

unaf fected by the Xon or Xoff transmission. They will be transmitted

after the Xon/Xoff activity concludes.

If the fill level condition that initiates Xon activity negates before the

flow control character can begin transmission, the transmission of

the flow control character will not occur, i.e. either of the following

sequences may be transmitted depending on the timing of the FIFO

level changes with respect to the normal character times:

Character Xoff Xon Character

Character Character

Hardware keeps track of Xoff characters sent that are not rescinded

by an Xon. This logic is reset by writing MR0(3) to ’0’. If the user

drops out of Auto–receiver mode while the XISR shows Xon as the

last character sent, the Xon/Xoff logic will not automatically send the

negating Xon.

Host mode

When neither the auto–receiver nor auto–transmitter modes are set,

the Xon/Xof f logic is operating in the host mode. In host mode, all

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 17

activity of the Xon/Xoff logic is initiated by commands to the CRx

command forces the transmitter to disable exactly as though an Xoff

character had been received by the RxFIFO. The transmitter will

remain disabled until the chip is reset or the CR(7:3) = 10110 (Xoff

resume) command is given. In particular, reception of an Xon or

disabling or re–enabling the transmitter will NOT cause resumption

of transmission. Redundant CRTXon/off commands, i.e. CRTXon

CRTXon, are harmless, although they waste time. A CR TXon may

be used to cancel a CRTXoff (and vice versa), but both may be

transmitted depending on the timing with the transmit state machine.

The kill CRTX command can be used to cleanly terminate any

CRTX commands pending with the minimum impact on the

transmitter.

Note: In no case will an Xon/Xoff character transmission be aborted.

Once the character is loaded into the TX Shift Register, transmission

continues until completion or a chip reset is encountered.

The kill CRTX command has no effect in either of the Auto modes.

Mode control

Xon/Xof f mode control is accomplished via the MR0. Bits 3 and 2

reset to zero resulting in all Xon/Xoff processing being disabled. If

MR0[2] is set, the transmitter may be gated by Xon/Xoff characters

received. If MR0[3] is set, the transmitter will transmit Xon and Xoff

when triggered by attainment of fixed fill levels in the channel

RxFIFO. The MR0[7] bit also has an Xon/Xoff function control. If

this bit is set, a received Xon or Xoff character is not pushed into the

RxFIFO. If cleared, the power–on and reset default, the received

Xon or Xoff character is pushed onto the RxFIFO for examination by

the host CPU. The MR0(7) function operates regardless of the

value in MR0(3:2)

Xon/Xoff Interrupts

The Xon/Xof f logic generates interrupts only in response to

recognizing either of the characters in the XonCR or XoffCR (Xon or

Xoff Character Registers). The transmitter activity initiated by the

Xon/Xof f logic or any CR command does not generate an interrupt.

The character comparators operate regardless of the value in

MR0(3:2). Hence the comparators may be used as general purpose

character detectors by setting MR0(3:2)=’00’ and enabling the

Xon/Xof f interrupt in the IMR.

The Octal UART can present the Xon/Xoff recognition event to the

interrupt arbiter for IRQN generation. The IRQN generation may be

masked by setting bit 4 of the Interrupt Mask Register, IMR. The bid

level of an Xon/Xoff recognition event is controlled by the Bidding

Control Register X, BCRX, of the channel. The interrupt status can

be examined in ISR[4]. If cleared, no Xon/Xoff recognition event is

interrupting. If set, an Xon or Xoff recognition event has been

detected. The X Interrupt Status Register, XISR, can be read for

details of the interrupt and to examine other, non–interrupting, status

of the Xon/Xof f logic. Refer to the XISR in the Register

Descriptions.

The character recognition function and the associated interrupt

generation is disabled on hardware or software reset.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 18

REGISTER DEFINITIONS

The operation of the Octal UART is programmed by writing control

words into the appropriate registers. Operational feedback is

provided via status registers which can be read by the host CPU.

The Octal UART addressing is loosely divided, by the address bit

A(7), into two parts:

1) That part which is concerned with the configuration of the chip

interface and communication modes.

This part controls the elements of host interface setup, interrupt

arbitration, I/O Port Configuration that part of the UART channel

definitions that do not change in normal data handling. This section

is listed in the ”Register Map, Control”.

2) That part concerned with the transmission and reception of the bit

streams.

This part concerns the data status, FIFO fill levels, data error

conditions, channel status, data flow control (hand shaking). This

section is listed in the ”Register Map, Data”.

The Global Configuration Control Register (GCCR) sets the type of

bus cycle, interrupt vector modification and the power up or down

mode.

Table 2. GCCR – Global Configuration Control Register

THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION.

ÁÁÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁ

Bit 6

ÁÁÁÁÁ

Bit 5:3

ÁÁÁÁÁÁÁÁÁÁÁÁ

Bit 2:1

ÁÁÁÁÁÁÁÁ

Bit 0

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

Sync bus cycles

ÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁ

IVC, Interrupt Vector Control

ÁÁÁÁÁÁÁÁ

Power Down Mode

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Reserved

Must be set to 0

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

0 – async cycles

1 – Sync, non–pipe–

lined cycle

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Reserved

Set to 0

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

00 – no interrupt vector

01 – IVR

10 – IVR + channel code

11 – IVR + interrupt type + channel code

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

0 – Device enabled

1 – Power down

GCCR(7): This bit is reserved for future versions of this device. If

not set to zero most internal addressing will be disabled!

GCCR(6): Bus cycle selection

Controls the operation of the host interface logic. If reset, the power

on/reset default, the host interface can accommodate arbitrarily long

bus I/O cycles. If the bit is set, the Octal UART expects four Sclk

cycle bus I/O operations similar to those produced by an i80386

processor in non–pipelined mode. The major differences in these

modes are observed in the DACKN pin function. In Sync mode, no

negation of CEN is required between cycles.

GCCR(2:1): Interrupt vector configuration

The IVC field controls if and how the assertion of IACKN (the

interrupt acknowledge pin) will form the interrupt vector for the Octal

UART. If b’00, no vector will be presented during an IACKN cycle.

The bus will be driven high (xFF). If the field contains a b’01, the

contents of the IVR, Interrupt Vector Register, will be presented as

the interrupt vector without modification. If IVC = b’10, the channel

code will replace the 3 LSBs of the IVR; if IVC = b’11 then a modified

interrupt type and channel code replace the 5 LSBs of the IVR.

Note: The modified type field IVR(4:3) is:

10 Receiver w/o error

11 Receiver with error

01 Transmitter

00 All remaining sources

GCCR(0): Power down control

Controls the power down function. During power down the internal

oscillator is disabled, interrupt arbitration and all data

transmission/reception activities cease, and all processing for input

change detection, BRG counter/timers and Address/Xon./Xoff

recognition is disabled.

Note: For maximum power savings it is recommended that all

switching inputs be stopped and all input voltage levels be within 0.5

volt of the Vcc and Vss power supply levels.

To switch from the asynchronous to the synchronous bus cycle

mode, a single write operation to the GCCR, terminated by a

negation of the CEN pin, is required. This cycle may be 4 cycles

long if the setup time of the CEN edge to Sclk can be guaranteed.

The host CPU must ensure that a minimum of two Sclk cycles

elapse before the initiation of the next (synchronous) bus cycle(s).

A hardware or software reset is recommended for the unlikely

requirement of returning to the asynchronous bus cycling mode.

MR – Mode Registers

The user must exercise caution when changing the mode of running

receivers, transmitters or BRG counter/timers. The selected mode

will be activated immediately upon selection, even if this occurs

during the reception or transmission of a character. It is also

possible to disrupt internal controllers by changing modes at critical

times, thus rendering later transmission or reception faulty or

impossible. An exception to this policy is switching from auto–echo

or remote loop back modes to normal mode. If the deselection

occurs just after the receiver has sampled the stop bit (in most

cases indicated by the assertion of the channel’s RxRDY bit) and

the transmitter is enabled, the transmitter will remain in auto–echo

mode until the end of the transmission of the stop bit.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 19

Table 3. MR0– Mode Register 0

ÁÁÁÁÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁ

Bit 6

ÁÁÁÁÁÁ

Bit 5:4

ÁÁÁÁÁÁÁÁÁÁ

Bit 3:2

ÁÁÁÁÁÁÁ

Bit 1:0

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Xon/Xof f * transparency

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Address Recognition *

transparency

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

TxiNT

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

In–band flow control mode

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Address Recognition

control

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

0 – flow control characters

received are pushed onto

the

RxFIFO

1 – flow control characters

received are not pushed

onto the RxFIFO

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

0 – Address characters

received are pushed to

RxFIFO

1 – Address characters

received are not pushed

onto the RxFIFO

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

TxFIFO

interrupt

level

control

00 – empty

01 – 3/4 empty

10 – 1/2 empty

11 – not full

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

00 – host mode, only the host CPU

may initiate flow control actions

through the CR

01 – Auto T ransmitter flow control

10 – Auto Receiver flow control

11 – Auto Receiver and Transmitter

flow control

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

00 – none

01 – Auto wake

10 – Auto doze

11 – Auto wake and

auto doze

* If these bits are not 0 the characters will be stripped regardless of

bits (3:2) or (1:0)

MR0[7:6] – Control the handling of recognized Xon/Xoff or Address

characters. If set, the character codes are placed on the RxFIFO

along with their status bits just as ordinary characters are. If the

character is not pushed onto the RxFIFO, its received status will be

lost unless the receiver is operating in the block error mode, see

MR1[5] and the general discussion on receiver error handling.

Interrupt processing is not effected by the setting of these bits. See

Character recognition section.

MR0[5:4] – Controls the fill level at which a transmitter begins to

present its interrupt number to the interrupt arbitration logic. Use of

a low fill level minimizes the number of interrupts generated and

maximizes the number of transmit characters per interrupt cycle. It

also increases the probability that the transmitter will go idle for lack

of characters in the TxFIFO.

MR0[3:2] – Controls the Xon/Xoff processing logic. Auto

T ransmitter flow control allows the gating of Transmitter activity by

Xon/Xof f characters received by the Channel’s receiver. Auto

Receiver flow control causes the T ransmitter to emit an Xoff

character when the RxFIFO has loaded to a depth of 12 characters.

Draining the RxFIFO to a level of 8 or less causes the T ransmitter to

emit an Xon character. All transmissions require no host

involvement. A setting other than b’00 in this field precludes the use

of the command register to transmit Xon/Xoff characters.

Note: Interrupt generation in Xon/Xoff processing is controlled by the

IMR (Interrupt Mask Register) of the individual channels. The

interrupt may be cleared by a read of the XISR, the Xon/Xoff

Interrupt Status Register. Receipt of a flow control character will

always generate an interrupt if the IMR is so programmed. The

MR0[3:2] bits have effect on the automatic aspects of flow control

only, not the interrupt generation.

MR0[1:0] – This field controls the operation of the Address

recognition logic. If the device is not operating in the special or

“wake–up” mode, this hardware may be used as a general purpose

character detector by choosing any combination except b’00.

Interrupt generation is controlled by the channel IMR. The interrupt

may be cleared by a read of the XISR, the Xon/Xoff Interrupt Status

Register. See further description in the section on the Wake Up

mode.

Table 4. MR1 – Mode Register 1

ÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁ

Bit 6

ÁÁÁÁÁÁÁ

Bit 5

ÁÁÁÁÁÁÁÁ

Bit 4:3

ÁÁÁÁÁÁ

Bit 2

ÁÁÁÁÁÁ

Bit 1:0

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

RxRTS

Control

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

ISR Read Mode

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Error Mode

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Parity Mode

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Parity Type

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Bits per Charac-

ter

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0 – off

1 – on

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

0 – ISR unmasked

1 – ISR masked

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

0 = Character

1 = Block

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

00 – With Parity

01 – Force parity

10 – No parity

11 – Special Mode

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

0 = Even

1 = Odd

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

00 – 5

01 – 6

10 – 7

11 – 8

MR1[7]: Receiver Request to Send Control

This bit controls the deactivation of the RTSN output (I/O2) by the

receiver. This output is asserted and negated by commands applied

via the command register. MR1[7] = 1 causes RTSN to be

automatically negated upon receipt of a valid start bit if the receiver

FIFO is full or greater . R TSN is reasserted when an the FIFO fill

level falls below full. This constitutes a change from previous

members of Philips (Signets)’ UART families where the R TSN

function triggered on FIFO full. This behavior caused problems with

PC UARTs that could not stop transmission at the proper time. .

The RTSN feature can be used to prevent overrun in the receiver, by

using the RTSN output signal, to control the CTSN input of the

transmitting device.

MR1[6]: Interrupt Status Masking

This bit controls the readout mode of the Interrupt Status Register,

ISR. If set, the ISR reads the current status masked by the IMR, i.e.

only interrupt sources enabled in the IMR can ever show a ’1’ in the

ISR. If cleared, the ISR shows the current status of the interrupt

source without regard to the Interrupt Mask setting.

MR1[5]: Error Mode Select

This bit selects the operating mode of the three FIFOed status bits

(FE, PE, received break). In the character mode, status is provided

on a character by character basis; the status applies only to the

character at. the bottom of the FIFO. In the block mode, the status

provided in the SR for these bits is the accumulation (logical OR) of

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 20

the status for all characters coming to the top of the FIFO, since the

last reset error command was issued.

MR1[4:3]: Parity Mode Select

If ’with parity’ or ’force parity’ is selected, a parity bit is added to the

transmitted character and the receiver performs a parity check on

incoming data. MR1[4:3] = 11 selects the channel to operate in the

special wake up mode.

MR1[2]: Parity Type Select

This bit sets the parity type (odd or even) if the ’with parity’ mode is

programmed by MR1[4:3], and the polarity of the forced parity bit if

the ’force parity’ mode is programmed. It has no effect if the ’no

parity’ mode is programmed. In the special ’wake up’ mode, it

selects the polarity of the A/D bit. The parity bit is used to an

address or data byte in the ’wake up’ mode.

MR1[1:0]: Bits per Character Select

This field selects the number of data bits per character to be

transmitted and received. This number does not include the start,

parity, or stop bits.

Table 5. MR2 – Mode Register 2

The MR2 register provides basic channel setup control that may need more frequent updating.

ÁÁÁÁÁÁÁ

Bits 7:6

ÁÁÁÁÁÁÁÁ

Bit 5

ÁÁÁÁÁÁÁÁ

Bit 4

ÁÁÁÁÁÁÁ

Bit 3:2

ÁÁÁÁÁÁÁÁ

Bit 1:0

ÁÁÁÁÁÁÁ

Channel Mode

ÁÁÁÁÁÁÁÁ

TxRTS Control

ÁÁÁÁÁÁÁÁ

CTSN Enable Tx

ÁÁÁÁÁÁÁ

RxINT

ÁÁÁÁÁÁÁÁ

Stop Length

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

00 = normal

01 = Auto echo

10 = Local loop

11 = Remote loop

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

0 = No

1 = Yes

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

0 = No

1 = Yes

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

00 = RRDY

01 = Half Full

10 = 3/4 Full

11 = Full

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

00 = 1.0

01 = 1.5

10 = 2.0

11 = 9/16

MR2[7:6] – Mode Select

The Octal UART can operate in one of four modes: MR2[7:6] = b’00

is the normal mode, with the transmitter and receiver operating

independently.

MR2[7:6] = b’01 places the channel in the automatic echo mode,

which automatically re transmits the received data. The following

conditions are true while in automatic echo mode:

Received data is re–clocked and re–transmitted on the TxD

output.

The receive clock is used for the transmitter.

The receiver must be enabled, but the transmitter need not be

enabled.

The TxRDY and TxEMT status bits are inactive.

The received parity is checked, but is not regenerated for

transmission,

i.e., transmitted parity bit is as received.

Character framing is checked, but the stop bits are re-transmitted

as received.

A received break is echoed as received until the next valid start

bit is detected

. CPU to receiver communication continues normally, but the CPU

to transmitter link is disabled.

Two diagnostic modes can also be selected.

MR2[7:6] = b’10 selects local loop back mode. In this mode:

The transmitter output is internally connected to the receiver

input.

The transmit clock is used for the receiver.

The TxD output is held high.

The RxD input is ignored.

The transmitter must be enabled, but the receiver need not be

enabled.

CPU to transmitter and receiver communications continue

normally.

The second diagnostic mode is the remote loop back mode,

selected by MR2[7:6] = b’11. In this mode:

Received data is re–clocked and re–transmitted on the TxD

output.

The receive clock is used for the transmitter.

Received data is not sent to the local CPU, and the error status

conditions are inactive.

The received parity is not checked and is not regenerated for

transmission, i.e., the transmitted parity bit is as received.

The receiver must be enabled, but the transmitter need not be

enabled.

Character framing is not checked, and the stop bits are

re-transmitted as received.

A received break is echoed as received until the next valid start

bit is detected.

MR2[5] – Transmitter Request to Send Control

This bit controls the deactivation of the RTSN output (I/O2) by the

transmitter. This output is manually asserted and negated by

appropriate commands issued via the command register. MR2[5] =

1 causes RTSN to be reset automatically one bit time after the

characters in the transmit shift register and in the TxFIFO (if any)

are completely transmitted (includes the programmed number of

stop bits if the transmitter is not enabled). This feature can be used

to automatically terminate the transmission of a message as follows:

Program auto reset mode: MR2[5]= 1.

Enable transmitter .

Assert RTSN via command.

Send message.

After the last character of the message is loaded to the TxFIFO,

disable the transmitter. Before disabling the transmitter be sure

the Status Register TxEMT bit is NOT set (i.e., the transmitter is

not underrun). The underrun condition is indicated by the

TxEMT bit in the SR being set. The condition occurs

immediately upon enabling the transmitter and persists until a

character is loaded to the TxFIFO. The Underrun condition will

not be a problem as long as the controlling processor keeps up

with the transmitter data flow. The proper operation of this

feature assumes that the transmitter is busy (not underrun) when

the disable is issued.

The last character will be transmitted and RTSN will be reset one

bit time after the last stop bit.

NOTE: When the transmitter controls the RTSN pin, the meaning of

the pin is COMPLETELY changed. It has nothing to do with the

normal RTSN/CTSN “handshaking”. It is usually used to mean “end

of message” and to “turn the line around” in simplex

communications.

MR2[4] – Clear to Send Control

The state of this bit determines if the CTSN input (I/O0) controls the

operation of the transmitter. If this bit is 0, CTSN has no effect on

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 21

the transmitter. If this bit is a 1, the transmitter checks the state of

CTSN each time it is ready to begin sending a character. If it is

asserted (low), the character is transmitted. If it is negated (high),

the TxD output remains in the marking state and the transmission is

delayed until CTSN goes low. Changes in CTSN, while a character

is being transmitted, do not affect the transmission of that character.

This feature can be used to prevent overrun of a remote receiver.

MR2[3:2] – RxINT control field

Controls when interrupt arbitration for a receiver begins based on

RxFIFO fill level. This field allows interrupt arbitration to begin when

the RxFIFO is full, 3/4 full, 1/2 full or when it contains at least 1

character.

MR2[1:0] – Stop Bit Length Select

This field programs the length of the stop bit appended to the

transmitted character. Stop bit lengths of 9/16, 1, 1.5 and 2 bits can

be programmed for character lengths of 6, 7, and 8 bits. For a

character length of 5 bits, 1, 1.5 and 2 stop bits can be programmed.

In all cases, the receiver only checks for a mark condition at the

center of the first stop bit position (one bit time after the last data bit,

or after the parity bit if parity is enabled). If an external 1X clock is

used for the transmitter, MR2[1] = 0 selects one stop bit and MR2[1]

= 1 selects two stop bits to be transmitted.

Table 6. RxCSR and TxCSR – Receiver and Transmitter Clock Select Registers

Both registers consist of single 5 bit field that selects the clock source for the receiver and transmitter, respectively. The unused bits in this

register read b’111. The baud rates shown in the table below are based on the x1 crystal frequency of 3.6864MHz. The baud rates shown

below will vary as the X1 crystal clock varies. For example, if the X1 rate is changed to 7.3728 MHz all the rates below will double.

ÁÁÁÁÁÁÁÁÁÁÁ

Bits 7:5

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 4:0

ÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter/Receiver Clock select code, (see Clock Mux Table below)

Table 7. Data Clock Mux

CCLK maximum rate is 8MHz. Data clock rates will follow exactly the ratio of CCLK to 3.6864MHz.

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Clock Select Code

CSR (4:0)

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Clock selection,

CCLK = 3.6864 MHz

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Clock Select Code

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Clock selection,

CCLK = 3.6864 MHz

ÁÁÁÁÁÁÁ

00000

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 50

ÁÁÁÁÁÁÁ

10000

ÁÁÁÁÁÁÁÁÁÁÁÁ

BRG – 19.2K

ÁÁÁÁÁÁÁ

00001

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 75

ÁÁÁÁÁÁÁ

10001

ÁÁÁÁÁÁÁÁÁÁÁÁ

BRG – 28.8K

ÁÁÁÁÁÁÁ

00010

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 150

ÁÁÁÁÁÁÁ

10010

ÁÁÁÁÁÁÁÁÁÁÁÁ

BRG – 38.4K

ÁÁÁÁÁÁÁ

00011

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 200

ÁÁÁÁÁÁÁ

10011

ÁÁÁÁÁÁÁÁÁÁÁÁ

BRG – 57.6K

ÁÁÁÁÁÁÁ

00100

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 300

ÁÁÁÁÁÁÁ

10100

ÁÁÁÁÁÁÁÁÁÁÁÁ

BRG – 115.2K

ÁÁÁÁÁÁÁ

00101

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 450

ÁÁÁÁÁÁÁ

10101

ÁÁÁÁÁÁÁÁÁÁÁÁ

BRG – 230.4K

ÁÁÁÁÁÁÁ

00110

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 600

ÁÁÁÁÁÁÁ

10110

ÁÁÁÁÁÁÁÁÁÁÁÁ

GIN0

ÁÁÁÁÁÁÁ

00111

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 900

ÁÁÁÁÁÁÁ

10111

ÁÁÁÁÁÁÁÁÁÁÁÁ

GIN1

ÁÁÁÁÁÁÁ

01000

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 1200

ÁÁÁÁÁÁÁ

11000

ÁÁÁÁÁÁÁÁÁÁÁÁ

BRG C/T 0

ÁÁÁÁÁÁÁ

01001

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 1800

ÁÁÁÁÁÁÁ

11001

ÁÁÁÁÁÁÁÁÁÁÁÁ

BRG C/T 1

ÁÁÁÁÁÁÁ

01010

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 2400

ÁÁÁÁÁÁÁ

11010

ÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01011

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 3600

ÁÁÁÁÁÁÁ

11011

ÁÁÁÁÁÁÁÁÁÁÁÁ

I/O2 rcvr, I/O3 xmit –16x

ÁÁÁÁÁÁÁ

01100

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 4800

ÁÁÁÁÁÁÁ

11100

ÁÁÁÁÁÁÁÁÁÁÁÁ

I/O2 rcvr, I/O3 xmit–1x

ÁÁÁÁÁÁÁ

01101

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 7200

ÁÁÁÁÁÁÁ

11101

ÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01110

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 9600

ÁÁÁÁÁÁÁ

11110

ÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01111

ÁÁÁÁÁÁÁÁÁÁÁ

BRG – 14.4K

ÁÁÁÁÁÁÁ

11111

ÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 22

Table 8. CR – Command Register

CR is used to write commands to the Octal UART.

ÁÁÁÁÁ

Bits 7:3

ÁÁÁÁÁ

Bit 2

ÁÁÁÁÁ

Bit 1

ÁÁÁÁÁ

Bit 0

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Channel Com-

mand codes

see “Command

Register Table”

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Lock TxD and

RxFIFO en-

ables

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Enable Tx

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Enable Rx

CR[2] – Lock TxD and RxFIFO enables

If set, the transmitter and receiver enable bits, CR[1:0] are not

significant. The enabled/disabled state of a receiver or transmitter

can be changed only if this bit is at zero during the time of the write

to the command register. WRITES TO THE UPPER BITS OF THE

CR WOULD USUALLY HAVE CR[2] AT 1 to maintain the condition

of the receiver and transmitter. The bit provides a mechanism for

writing commands to a channel, via CR[7:3], without the necessity of

keeping track of or reading the current enable status of the receiver

and transmitter .

CR[1] – Enable Transmitter

A one written to this bit enables operation of the transmitter. The

TxRDY status bit will be asserted. When disabled by writing a zero

to this bit, the command terminates transmitter operation and resets

the TxRDY and TxEMT status bits. However, if a character is being

transmitted or if characters are loaded in the TxFIFO when the

transmitter is disabled, the transmission of the all character(s) is

completed before assuming the inactive state.

CR[0] – Enable Receiver

A one written to this bit enables operation of the receiver. If not in

the special wake up mode, this also forces the receiver into the

search for start bit state. If a zero is written, this command

terminates operation of the receiver immediately – a character being

received will be lost. The command has no effect on the receiver

status bits or any other control registers. If the special wake–up

mode is programmed, the receiver operates even if it is disabled

(see W ake–up Mode).

CR[7:3] – Miscellaneous Commands ( See Table below)

The encoded value of this field can be used to specify a single

command as follows:

00000 No command.

00001 Reserved

00010 Reset receiver. Resets the receiver as if a hardware reset

had been applied. The receiver is disabled and the FIFO

pointer is reset to the first location effectively discarding all

unread characters in the FIFO.

00011 Reset transmitter. Resets the transmitter as if a hardware

reset had been applied.

00100 Reset error status. Clears the received break, parity error,

framing error, and overrun error bits in the status register

(SR[7:4]). Used in character mode to clear overrun error

status (although RB, PE and FE bits will also be cleared),

and in block mode to clear all error status after a block of

data has been received.

00101 Reset break change interrupt. Causes the break detect

change bit in the interrupt status register (ISR[2]) to be

cleared to zero.

00110 Start break. Forces the TxD output low (spacing). If the

transmitter is empty, the start of the break condition will be

delayed up to two bit times. If the transmitter is active, the

break begins when transmission of the current character

is completed. If there are characters in the TxFIFO, the

start of break is delayed until those characters, or any

others loaded after it have been transmitted (TxEMT must

be true before break begins). The transmitter must be

enabled to start a break.

00111 Stop break. The TxD line will go high (marking) within two

bit times. TxD will remain high for one bit time before the

next character, if any, is transmitted.

01000 Assert RTSN. Causes the RTSN output to be asserted

(low).

01001 Negate RTSN. Causes the RTSN output to be negated

(high).

Note: The two commands above actually reset and

set, respectively, the I/O2 or I/O1 pin associated with

the I/OPIOR register.

01010 Reserved

01011 Reserved

01100 Reserved

01101 Block error status mode. Upon reset of the device or an

individual receiver, the block mode of receiver error status

accumulates as each character moves to the bottom of

the RxFIFO, the position from which it will be read. In this

mode of operation, the RxFIFO may contain a character

with non–zero error status for some time. The status will

not reflect the error character’s presence until it is ready to

be popped from the RxFIFO. Command 01101 allows the

error status to be updated as each character is pushed

into the RxFIFO. This allows the earliest detection of a

problem character, but complicates the determination of

exactly which character is causing the error. This mode of

block error accumulation may be exited only by resetting

the chip or the individual receiver.

01111 Reserved.

10000 T ransmit an Xon Character

10001 T ransmit an Xoff Character

10010 Reserved for channels b–h, for channel a: enables a

Gang Write of Xon Character Registers. After this

command is issued, a write to the channel A Xon

Character Register will result in a write to all channel’s

Xon character registers. This command provides a

mechanism to initialize all the Xon Character registers

with one write. A write to channel A Xon Character

Register returns the Octal UART to the individual Xon

write mode.

10011 Reserved for channels b–h, for channel a: enables Gang

Write of Xoff Character Registers. After this command is

issued, a write to the channel A Xoff Character Register

will result in a write to all channel’s Xoff character

registers. This command provides a mechanism to

initialize all the Xoff Character registers with one write. A

write to channel A Xoff Character Register returns the

Octal UART to the individual Xof f write mode.

Note: Gang writing of Xon/Xoff Character Commands: Issuing

command causes the next write to Xon/Xoff Character Register

A to effect a simultaneous write into the other 3 Xon/Xoff

character registers. After the Xon/Xoff Character Register A is

written, the 28L198 returns to individual write mode for the

Xon/Xoff Character Registers. Other intervening reads and

writes are ignored. The device resets to individual write mode.

10100 Reserved for channels b-h, for channel a: executes a Gang

Load of Xon Character Registers. Executing this

command causes a write of the value x’11 to all channel’s

Xon character registers. This command provides a

mechanism to initialize all the Xon Character registers to a

default value with one write. Execution of this command

is immediate and does not effect the timing of subsequent

host I/O operations.

10101 Reserved for channels b-h, for channel a: executes a

Gang Load of Xoff Character Registers. Executing this

command causes a write of the value x’13 to all channel’s

Xoff character registers. This command provides a

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 23

mechanism to initialize all the Xoff Character registers to a

default value with one write. Execution of this command

is immediate and does not effect the timing of subsequent

host I/O operations.

10110 Xoff resume command (CRXoffre; not active in

“Auto-Transmit Mode”). A command to cancel a previous

Host Xoff command. Upon receipt, the channel’ s

transmitter will transfer a character, if any, from the

TxFIFO and begin transmission.

10111 Host Xoff command (CRXoff). This command allows tight

host CPU control of the flow control of the channel

transmitter. When interrupted for receipt of an Xoff

character by the receiver, the host may stop transmission

of further characters by the channel transmitter by issuing

the Host Xoff command. Any character that has been

transferred to the TxD shift register will complete its

transmission, including the stop bit.

11000 Cancel Host transmit flow control command. Issuing this

command will cancel a previous transmit command if the

flow control character is not yet loaded into the TxD Shift

Register. If there is no character waiting for transmission

or if its transmission has already begun, then this

command has no effect.

11001–11011

Reserved

11011 Reset Address Recognition Status. This command clears the

interrupt status that was set when an address character

was recognized by a disabled receiver operating in the

special mode.

11100–11101

Reserved

11110 Resets all UART channel registers. This command

provides a means to zero all the UART channels that are

not reset to x’00 by a reset command or a hardware reset.

11111 Reserved for channels b-h, for channel a: executes a chip

wide reset. Executing this command in channel a is

equivalent to a hardware reset with the RESETN pin.

Executing in channel b-h, has no effect.

Table 9. Command Register Code

Commands x’12, x13, x’14, x’15, x’1f (marked with*) are global and exist only in channel A’s register space.

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Channel Command

Code

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Channel

Command

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Channel Command

Code

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Channel

Command

ÁÁÁÁÁÁ

CR[7:3]

ÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁÁÁÁ

CR[7:3]

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Description

ÁÁÁÁÁÁ

00000

ÁÁÁÁÁÁÁÁÁÁÁ

NOP

ÁÁÁÁÁÁÁ

10000

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmit Xon

ÁÁÁÁÁÁ

00001

ÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

10001

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmit Xof f

ÁÁÁÁÁÁ

00010

ÁÁÁÁÁÁÁÁÁÁÁ

Reset Receiver

ÁÁÁÁÁÁÁ

10010

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Gang Write Xon Character Registers *

ÁÁÁÁÁÁ

00011

ÁÁÁÁÁÁÁÁÁÁÁ

Reset T ransmitter

ÁÁÁÁÁÁÁ

10011

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Gang Write Xoff Character Registers *

ÁÁÁÁÁÁ

00100

ÁÁÁÁÁÁÁÁÁÁÁ

Reset Error Status

ÁÁÁÁÁÁÁ

10100

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Gang Load Xon Character Registers DC1 *

ÁÁÁÁÁÁ

00101

ÁÁÁÁÁÁÁÁÁÁÁ

Reset Break Change Interrupt

ÁÁÁÁÁÁÁ

10101

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Gang Load Xoff Character Registers DC3 *

ÁÁÁÁÁÁ

00110

ÁÁÁÁÁÁÁÁÁÁÁ

Begin T ransmit Break

ÁÁÁÁÁÁÁ

10110

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Resume Command

ÁÁÁÁÁÁ

00111

ÁÁÁÁÁÁÁÁÁÁÁ

End T ransmit Break

ÁÁÁÁÁÁÁ

10111

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Host Xoff Command

ÁÁÁÁÁÁ

01000

ÁÁÁÁÁÁÁÁÁÁÁ

Assert RTSN (I/O2 or I/O1)

ÁÁÁÁÁÁÁ

11000

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Cancel T ransmit X Char command

ÁÁÁÁÁÁ

01001

ÁÁÁÁÁÁÁÁÁÁÁ

Negate RTSN (I/O2 or I/O1)

ÁÁÁÁÁÁÁ

11001

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁ

01010

ÁÁÁÁÁÁÁÁÁÁÁ

Set time–out mode on

ÁÁÁÁÁÁÁ

11010

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁ

01011

ÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11011

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Address Recognition Status

ÁÁÁÁÁÁ

01100

ÁÁÁÁÁÁÁÁÁÁÁ

Set time–out mode off

ÁÁÁÁÁÁÁ

11100

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁ

01101

ÁÁÁÁÁÁÁÁÁÁÁ

Block Error Status configure

ÁÁÁÁÁÁÁ

11101

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁ

01110

ÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11110

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset All UART channel registers

ÁÁÁÁÁÁ

01111

ÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11111

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Device *

Table 10. SR – Channel Status Register

ÁÁÁÁÁ

Bit 7

ÁÁÁÁÁ

Bit 6

ÁÁÁÁÁ

Bit 5

ÁÁÁÁÁ

Bit 4

ÁÁÁÁÁ

Bit 3

ÁÁÁÁÁÁ

Bit 2

ÁÁÁÁÁ

Bit 1

ÁÁÁÁÁ

Bit 0

ÁÁÁÁÁ

Received

Break

ÁÁÁÁÁ

Framing Error

ÁÁÁÁÁ

Parity

Error

ÁÁÁÁÁ

Overrun Error

ÁÁÁÁÁ

TxEMT

ÁÁÁÁÁÁ

TxRDY

ÁÁÁÁÁ

RxFULL

ÁÁÁÁÁ

RxRDY

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 – No

1 – Yes

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 – No

1 – Yes

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 – No

1 – Yes

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 – No

1 – Yes

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 – No

1 – Yes

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

0 – No

1 – Yes

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 – No

1 – Yes

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

0 – No

1 – Yes

SR[7] – Received Break

This bit indicates that an all zero character of the programmed

length has been received without a stop bit. Only a single FIFO

position is occupied when a break is received; further entries to the

FIFO are inhibited until the RxD line returns to the marking state for

at least one half bit time (two successive edges of the internal or

external 1x clock). When this bit is set, the change in break bit in

the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break

condition, as defined above, is detected. The break detect circuitry

is capable of detecting breaks that originate in the middle of a

received character. However , if a break begins in the middle of a

character, it must last until the end of the next character in order for

it to be detected.

SR[6] – Framing Error (FE)

This bit, when set, indicates that a stop bit was not detected when

the corresponding data character in the FIFO was received. The

stop bit check is made in the middle of the first stop bit position.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 24

SR[5] – Parity Error (PE)

This bit is set when the ’with parity’ or ’force parity’ mode is

programmed and the corresponding character in the FIFO was

received with incorrect parity. In the special ’wake up mode’, the

parity error bit stores the received A/D bit.

SR[4] – Overrun Error (OE)

This bit, when set, indicates that one or more characters in the

received data stream have been lost. It is set upon receipt of a new

character when the RxFIFO is full and a character is already in the

receive shift register waiting for an empty FIFO position. When this

occurs, the character in the receive shift register (and its break

detect, parity error and framing error status, if any) is lost. This bit is

cleared by a reset error status command.

SR[3] – Transmitter Empty (TxEMT)

This bit is set when the transmitter underruns, i.e., both the TxFIFO

and the transmit shift register are empty.

It is set after transmission of the last stop bit of a character, if no

character is in the TxFIFO awaiting transmission. It is reset when

the TxFIFO is loaded by the CPU, or when the transmitter is

disabled.

SR[2] – Transmitter Ready (TxRDY)

This bit, when set, indicates that the TxFIFO is ready to be loaded

with a character. This bit is cleared when the TxFIFO is loaded by

the CPU and is set when the last character is transferred to the

transmit shift register. TxRDY is reset when the transmitter is

disabled and is set when the transmitter is first enabled, e.g.,

characters loaded in the TxFIFO while the transmitter is disabled will

not be transmitted.

SR[1] – RxFIFO Full (RxFULL)

This bit is set when a character is transferred from the receive shift

register to the receive FIFO and the transfer causes the FIFO to

become full, i.e., all sixteen RxFIFO positions are occupied. It is

reset when the CPU reads the RxFIFO and that read leaves one

empty byte position. If a character is waiting in the receive shift

register because the RxFIFO is full, RxFULL is not reset until the

second read of the RxFIFO since the waiting character is

immediately loaded to the RxFIFO.

SR[0] – Receiver Ready (RxRDY)

This bit indicates that a character has been received and is waiting

in the RxFIFO to be read by the CPU. It is set when the character is

transferred from the receive shift register to the RxFIFO and reset

when the CPU reads the RxFIFO, and no more characters are in the

RxFIFO.

Table 11. ISR – Interrupt Status Register

ÁÁÁÁ

Bit 7

ÁÁÁÁ

Bit 6

ÁÁÁÁÁÁ

Bit 5

ÁÁÁ

Bit 4

ÁÁÁÁÁ

Bit 3

ÁÁÁÁÁ

Bit 2

ÁÁÁÁÁÁ

Bit 1

ÁÁÁÁÁÁÁÁ

Bit 0

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

I/O Port

change of

state

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Receiver

Watch-dog

Time–out

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Address recogni-

tion event

ÁÁÁ

Á

ÁÁÁ

Xon/off

event

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Always 0

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Change of

Break State

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

RxRDY

Receiver has entered

arbitration process

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

TxRDY

T ransmitter has entered

arbitration process

This register provides the status of all potential interrupt sources for

a UART channel. When generating an interrupt arbitration value,

the contents of this register are masked by the interrupt mask

register (IMR). If a bit in the ISR is a ’1’ and the corresponding bit in

the IMR is also a ’1’, interrupt arbitration for this source will begin. If

the corresponding bit in the IMR is a zero, the state of the bit in the

ISR can have no affect on the IRQN output. Note that the IMR may

or may not mask the reading of the ISR as determined by MR1[6].

If MR1[6] is cleared, the reset and power on default, the ISR is read

without modification. If MR1[6] is set, the a read of the ISR gives a

value of the ISR ANDed with the IMR.

ISR[7] – Input Change of State

This bit is set when a change of state occurs at the I/O1 or I/O0

input pins. It is reset when the CPU reads the Input Port Register,

IPR.

ISR[6] W atch-dog Time–out

This bit is set when the receiver’s watch-dog timer has counted

more than 64 bit times since the last RxFIFO event. RxFIFO events

are a read of the RxFIFO or GRxFIFO, or the push of a received

character into the FIFO. The interrupt will be cleared automatically

upon the push of the next character received or when the RxFIFO or

GRxFIFO is read. The receiver watch-dog timer is included to allow

detection of the very last characters of a received message that may

be waiting in the RxFIFO, but are too few in number to successfully

initiate an interrupt. Refer to the watch-dog timer description for

details of how the interrupt system works after a watch-dog

time–out.

ISR[5] – Address Recognition Status Change

This bit is set when a change in receiver state has occurred due to

an Address character being received from an external source and

comparing to the reference address in ARCR. The bit and interrupt

is negated by a write to the CR with command x11011, Reset

Address Recognition Status.

ISR[4] – Xon/Xoff Status Change

This bit is set when an Xon/Xoff character being received from an

external source. The bit is negated by a read of the channel Xon

Interrupt Status Register, XISR.

ISR[3] – Reserved Always reads a 0

ISR[2] – Change in Channel Break Status

This bit, when set, indicates that the receiver has detected the

beginning or the end of a received break. It is reset when the CPU

issues a reset break change interrupt command via the CR.

ISR[1] – Receiver Ready

The general function of this bit is to indicate that the RxFIFO has

data available. The particular meaning of this bit is programmed by

MR2[3:2]. If programmed as receiver ready(MR2[3:2] = 00), it

indicates that at least one character has been received and is

waiting in the RxFIFO to be read by the host CPU. It is set when the

character is transferred from the receive shift register to the RxFIFO

and reset when the CPU reads the last character from the RxFIFO.

If MR2[3:2] is programmed as FIFO full, ISR[1] is set when a

character is transferred from the receive holding register to the

RxFIFO and the transfer causes the RxFIFO to become full, i.e. all

sixteen FIFO positions are occupied. It is reset when ever RxFIFO

is not full. If there is a character waiting in the receive shift register

because the FIFO is full, the bit is set again when the waiting

character is transferred into the FIFO.

The other two conditions of these bits, 3/4 and half full operate in a

similar manner. The ISR[1] bit is set when the RxFIFO fill level

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 25

meets or exceeds the value; it is reset when the fill level is less.

See the description of the MR2 register.

Note: This bit must be at a one (1) for the receiver to enter the

arbitration process. It is the fact that this bit is zero (0) when the

RxFIFO is empty that stops an empty FIFO from entering the

interrupt arbitration. Also note that the meaning if this bit is not quite

the same as the similar bit in the status register (SR).

ISR[0] – Transmitter Ready

The general function of this bit is to indicate that the TxFIFO has an

at least one empty space for data. The particular meaning of the bit

is controlled by MR0[5:4] indicates the TxFIFO may be loaded with

one or more characters. If MR0[5:4] = 00 (the default condition) this

bit will not set until the TxFIFO is empty – sixteen bytes available. If

the fill level of the TxFIFO is below the trigger level programmed by

the TxINT field of the Mode Register 0, this bit will be set. A one in

this position indicates that at least one character can be sent to the

TxFIFO. It is turned off as the TxFIFO is filled above the level

programmed by MR0[5:4. This bit turns on as the FIFO empties; the

RxFIFO bit turns on as the FIFO fills. This often a point of confusion

in programming interrupt functions for the receiver and transmitter

FIFOs.

Note: This bit must be at a one (1) for the transmitter to enter the

arbitration process. It is the fact that this bit is zero (0) when the

RxFIFO is full that stops a full FIFO from entering the interrupt

arbitration. Also note that the meaning if this bit is not quite the

same as the similar bit in the status register (SR).

Table 12. IMR – Interrupt Mask Register

ÁÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁ

Bit 6

ÁÁÁÁÁÁ

Bit 5

ÁÁÁÁÁ

Bit 4

ÁÁÁ

Bit 3

ÁÁÁÁÁ

Bit 2

ÁÁÁÁÁ

Bit 1

ÁÁÁÁÁ

Bit 0

ÁÁÁÁÁ

I/O Port change

of state

ÁÁÁÁÁÁÁ

Receiver W atch-dog

Time–out

ÁÁÁÁÁÁ

Address recogni-

tion event

ÁÁÁÁÁ

Xon/of f event

ÁÁÁ

Set to 0

ÁÁÁÁÁ

Change of

Break State

ÁÁÁÁÁ

RxRDY inter-

rupt

ÁÁÁÁÁ

TxRDY inter-

rupt

The programming of this register selects which bits in the ISR cause

an interrupt output. If a bit in the ISR is a ’1’ and the corresponding

bit in the IMR is a ’1’, the interrupt source is presented to the internal

interrupt arbitration circuits, eventually resulting in the IRQN output

being asserted (low). If the corresponding bit in the IMR is a zero,

the state of the bit in the ISR has no affect on the IRQN output.

IMR[7] – Controls if a change of state in the inputs equipped with

input change detectors will cause an interrupt.

IMR[6] – Controls the generation of an interrupt by the watch-dog

timer event. If set, a count of 64 idle bit times in the receiver will

begin interrupt arbitration.

IMR[5] – Enables the generation of an interrupt in response to

changes in the Address Recognition circuitry of the Special Mode

(multi-drop or wake–up mode).

IMR[4] – Enables the generation of an interrupt in response to

recognition of an in–band flow control character.

IMR[3] – Reserved

IMR[2] – Enables the generation of an interrupt when a Break

condition has been detected by the channel receiver.

IMR[1] – Enables the generation of an interrupt when servicing for

the RxFIFO is desired.

IMR[0] – Enables the generation of an interrupt when servicing for

the TxFIFO is desired.

Table 13. RxFIFO Receiver FIFO

ÁÁÁÁ

Bit[10]

ÁÁÁÁ

Bit[9]

ÁÁÁÁ

Bit[8]

ÁÁÁÁÁÁÁÁ

Bits [7:0]

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Break

Received

Status

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Framing

Error Sta-

tus

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Parity

Error Sta-

tus

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

8 data bits

MSBs =0 for 7,6,5 bit

data

The FIFO for the receiver is 11 bits wide and 16 ”words” deep. The

status of each byte received is stored with that byte and is moved

along with the byte as the characters are read from the FIFO. The

upper three bits are presented in the STATUS register and they

change in the status register each time a data byte is read from the

FIFO. Therefor the status register should be read BEFORE the byte

is read from the RxFIFO if one wishes to ascertain the quality of the

byte

The forgoing applies to the ”character error” mode of status

reporting. See MR1[5] and ”RxFIFO Status” descriptions for ”block

error” status reporting. Briefly ”Block Error” gives the accumulated

error of all bytes received in the RxFIFO since the last “Reset Error”

command was issued. (CR = x’04)

Table 14. TxFIFO – Transmitter FIFO

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 7:0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 data bits. MSBs set to 0 for 7, 6, 5 bit data

The FIFO for the transmitter is 8 bits wide by 16 bytes deep. For

character lengths less than 8 bits the upper bits will be ignored by

the transmitter state machine and thus are effectively discarded.

Table 15. BCRBRK – Bidding Control Register –

Break Change

ÁÁÁÁÁÁÁ

Bits 7:3

ÁÁÁÁÁÁÁÁÁÁÁ

Bits 2:0

ÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁ

MSB of break change interrupt bid

This register provides the 3 MSBs of the Interrupt Arbitration number

for a break change interrupt.

Table 16. BCRCOS – Bidding Control Register –

Change of State

ÁÁÁÁÁÁÁ

Bits 7:3

ÁÁÁÁÁÁÁÁÁÁÁ

Bits 2:0

ÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁ

MSB of a COS interrupt bid

ÁÁÁÁÁÁÁ

Read as x’0

ÁÁÁÁÁÁÁÁÁÁÁ

This register provides the 3 MSBs of the Interrupt Arbitration number

for a Change of State, COS, interrupt.

Table 17. BCRx – Bidding Control Register – Xon

ÁÁÁÁÁÁÁ

Bits 7:3

ÁÁÁÁÁÁÁÁÁÁÁ

Bits 2:0

ÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁ

MSB of an Xon/Xoff interrupt bid

This register provides the 3 MSBs of the Interrupt Arbitration number

for an Xon/Xoff interrupt.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 26

Table 18. BCRA – Bidding Control Register –

Address

ÁÁÁÁÁÁ

Bits 7:3

ÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 2:0

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁ

MSB of an address recognition event in-

terrupt bid

This register provides the 3 MSBs of the Interrupt Arbitration number

for an address recognition event interrupt.

Table 19. XonCR – Xon Character Register

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 7:0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 Bits of the Xon Character Recognition

An 8 bit character register that contains the compare value for an

Xon character.

Table 20. XoffCR – Xoff Character Register

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 7:0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 Bits of the Xoff Character Recognition

An 8 bit character register that contains the compare value for an

Xoff character.

Table 21. ARCR – Address Recognition Character

Register

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 7:0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 Bits of the Multi–Drop Address Character Recognition

An 8 bit character register that contains the compare value for the

wake–up address character

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 27

Table 22. XISR – Xon–Xoff Interrupt Status Register

ÁÁÁÁÁÁÁÁ

Bits 7:6

ÁÁÁÁÁÁÁÁÁÁ

Bits 5:4

ÁÁÁÁÁÁÁÁ

Bits 3:2

ÁÁÁÁÁÁÁÁÁÁÁ

Bits 1:0

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Received X Character Sta-

tus

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Automatic X Character transmis-

sion status

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

TxD flow status

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

TxD character status

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

00 – none

01 – Xoff received

10 – Xon received

11 – both received

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

00 – none

01 – Xon transmitted

10 – Xoff transmitted

11 – Illegal, does not occur

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

00 – normal

01 – TxD halt pending

10 – re–enabled

11 – flow disabled

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

00 – normal TxD data

01 – wait on normal data

10 – Xoff in pending

11 – Xon in pending

XISR[7:6] – Received X Character Status. This field can be read to

determine if the receiver has encountered an Xon or Xoff character

in the incoming data stream. These bits are maintained until a read

of the XISR. The field is updated by X character reception

regardless of the state of MR0(7, 3:2) or IMR(4). The field can

therefore be used as a character detector for the bit patterns stored

in the Xon and Xoff Character Registers.

XISR[5:4] – Automatic transmission Status. This field indicates the

last flow control character sent in the Auto Receiver flow control

mode. If Auto Receiver mode has not been enabled, this field will

always read b’00. It will likewise reset to b’00 if MR0(3) is reset. If

the Auto Receiver mode is exited while this field reads b’10, it is the

user’s responsibility to transmit an Xon, when appropriate.

XISR[3:2] – TxD flow Status. This field tracks the transmitter’s flow

status as follows:

00 – normal. The flow control is under host control.

01 – TxD halt pending. After the current character finishes the

transmitter will stop. The status will then change to b’00.

10 – re–enabled. The transmitter had been halted and restarted.

It is sending data characters. After a read of the XISR, it will

return to ”normal” status.

11 – disabled. The transmitter is flow controlled.

XISR[1:0] – TxD character Status. This field allows determination of

the type of character being transmitted. If XISR(1:0) is b’01, the

channel is waiting for a data character to transfer from the TxFIFO.

This condition will only occur for a bit time after an Xon or Xoff

character transmission unless the TxFIFO is empty.

Table 23. WDTRCR – Watch-dog Timer Enable

Register

ÁÁÁ

Bit 7

ÁÁÁ

Bit 6

ÁÁÁ

Bit 5

ÁÁÁ

Bit 4

ÁÁÁ

Bit 3

ÁÁÁ

Bit 2

ÁÁÁ

Bit 1

ÁÁÁ

Bit 0

ÁÁÁ

WDT

h

ÁÁÁ

WDT

g

ÁÁÁ

WDT

f

ÁÁÁ

WDT

e

ÁÁÁ

WDT

d

ÁÁÁ

WDT

c

ÁÁÁ

WDT

b

ÁÁÁ

WDT

a

ÁÁÁ

Á

ÁÁÁ

1 on

0 off

ÁÁÁ

Á

ÁÁÁ

1 on

0 off

ÁÁÁ

Á

ÁÁÁ

1 on

0 off

ÁÁÁ

Á

ÁÁÁ

1 on

0 off

ÁÁÁ

Á

ÁÁÁ

1 on

0 off

ÁÁÁ

Á

ÁÁÁ

1 on

0 off

ÁÁÁ

Á

ÁÁÁ

1 on

0 off

ÁÁÁ

Á

ÁÁÁ

1 on

0 off

This register enables the watch-dog T imer for each of the 8

receivers on the Octal UART.

Table 24. BRGTRU – BRG Timer Reload

Registers, Upper

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 7:0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 MSB of the BRG T imer divisor.

This is the upper byte of the 16 bit value used by the BRG timer in

generating a baud rate clock

Table 25. BRGTRL – BRG Timer Reload

Registers, Lower

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 7:0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 LSB of the BRG T imer divisor.

This is the lower byte of the 16 bit value used by the BRG timer in

generating a baud rate clock.

Table 26. BRGTCR – BRG Timer Control Register (BRGTCR)

ÁÁÁÁÁÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁÁ

Bit 6:4

ÁÁÁÁÁÁÁÁÁÁ

Bit 3

ÁÁÁÁÁÁÁÁÁ

Bit 2:0

ÁÁÁÁÁÁÁÁÁ

BRGTCR b, Register control

ÁÁÁÁÁÁÁÁÁ

BRGTCR b, Clock selection

ÁÁÁÁÁÁÁÁÁÁ

BRGTCR a, Register control

ÁÁÁÁÁÁÁÁÁ

BRGTCR a, Clock selection

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

0 – Resets the timer register and

holds it stopped

1 – Allows the timer register to

run.

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

000 – Sclk / 16

001 – Sclk / 32

010 – Sclk/ 64

011 – Sclk / 128

100 – X1

101 – X1 / 2

110 – I/O1b

111 – GIN(1)

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

0 – Resets the timer register and

holds it stopped.

1 – Allows the timer register to

run.

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

000 – Sclk / 16

001 – Sclk / 32

010 – Sclk / 64

011 – Sclk / 128

100 – X1

101 – X1 / 2

110 – I/O1a

111 – GIN(0)

Start/Stop control and clock select register for the two BRG

counters. The clock selection is for the input to the counters. It is

that clock divided by the number represented by the BRGTU and

BRGTL the will be used as the 16x clock for the receivers and

transmitters. When the BRG timer Clock is selected for the

receiver(s) or transmitter(s) the receivers and transmitters will

consider it as a 16x clock and further device it by 16. In other words

the receivers and transmitters will always be in the 16x ode of

operation when the internal BRG timer is selected for their clock.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 28

Table 27. ICR – Interrupt Control Register

ÁÁÁÁÁÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 6:0

ÁÁÁÁÁÁÁÁÁ

Reserved. Set to 0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Upper seven bits of the Arbitration Threshold

This register provides a single 7 bit field called the interrupt

threshold for use by the interrupt arbiter. The field is interpreted as a

single unsigned integer. The interrupt arbiter will not generate an

external interrupt request, by asserting IRQN, unless the value of

the highest priority interrupt exceeds the value of the interrupt

threshold. If the highest bidder in the interrupt arbitration is lower

than the threshold level set by the ICR, the Current Interrupt

Register, CIR, will contain x’00. Refer to the functional description of

interrupt generation for details on how the various interrupt source

bid values are calculated.

Note: While a watch-dog T imer interrupt is pending, the ICR is not

used and only receiver codes are presented for interrupt arbitration.

This allows receivers with very low count values (perhaps below the

threshold value) to win interrupt arbitration without requiring the user

to explicitly lower the threshold level in the ICR. These bits are the

upper seven (7) bits of the interrupt arbitration system. The lower

three (3) bits represent the channel number.

UCIR – Update CIR

A command based upon a decode of address x’8C. ( UCIR is not a

register!) A write (the write data is not important; a “don’t care”) to

this ’register’ causes the Current Interrupt Register to be updated

with the value that is winning interrupt arbitration. The register

would be used in systems that poll the interrupt status registers

rather than wait for interrupts. Alternatively, the CIR is normally

updated during an Interrupt Acknowledge Bus cycle in interrupt

driven systems.

Table 28. CIR – Current Interrupt Register

ÁÁÁÁÁÁ

Bits 7:6

ÁÁÁÁÁÁÁ

Bits 5:3

ÁÁÁÁÁÁ

Bits 2:0

ÁÁÁÁÁÁ

Type

ÁÁÁÁÁÁÁ

Current byte count/type

ÁÁÁÁÁÁ

Channel number

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

00 – other

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

000 – no interrupt

001 – Change of State

010 – Address

Recognition

011 – Xon/Xoff status

100 – Not used

101 – Break change

110, 111 do not occur

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

000 = a

001 = b

010 = c

011 = d

111 = h

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

01 – T ransmit

11– Receive w/

errors

10 – Receive w/o

errors

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Current count code

0 => 9 or less

characters

1 => 10 characters

.

5 => 14 characters

6 => 15 characters

7 => 16

(See also GIBCR)

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

000 = a

001 = b

010 = c

011 = d

111 = h

The Current Interrupt Register is provided to speed up the

specification of the interrupting condition in the Octal UART. The

CIR is updated at the beginning of an interrupt acknowledge bus

cycle or in response to an Update CIR command. (see immediately

above) Although interrupt arbitration continues in the background,

the current interrupt information remains frozen in the CIR until

another IACKN cycle or Update CIR command occurs. The LSBs of

the CIR provide part of the addressing for various Global Interrupt

registers including the GIBCR, GICR, GITR and the Global RxFIFO

and TxFIFO FIFO. The host CPU need not generate individual

addresses for this information since the interrupt context will remain

stable at the fixed addresses of the Global Interrupt registers until

the CIR is updated. For most interrupting sources, the data

available in the CIR alone will be sufficient to set up a service

routine.

The CIR may be processed as follows:

If CIR[7] = 1, then a receiver interrupt is pending and the count is

CIR[5:3], channel is CIR[2:0]

Else If CIR[6] = 1 then a transmitter interrupt is pending and the

count is CIR[5:3], channel is CIR[2:0]

Else the interrupt is another type, specified in CIR[5:3]

Note: The GIBCR, Global Interrupting Byte Count Register, may be

read to determine an exact character count if 9 or less characters

are indicated in the count field of the CIR.

Table 29. IVR – Interrupt Vector Register

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 7:0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 data bits of the Interrupt Vector (IVR)

The IVR contains the byte that will be placed on the data bus during

an IACKN cycle when the GCCR bits (2:1) are set to binary ‘01’.

This is the unmodified form of the interrupt vector.

Table 30. Modification of the IVR

ÁÁÁÁÁÁ

Bits 7:5

ÁÁÁÁÁÁ

Bits 4:3

ÁÁÁÁÁÁÁ

Bits 2:0

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Always contains

bits (7:5) of the IVR

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

Will be replaced

with current inter-

rupt type if IVC field

of GCCR > 1

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Replaced with inter-

rupting channel num-

ber if IVC field of

GCCR > 0

The table above indicates how the IVR may be modified by the

interrupting source. The modification of the IVR as it is presented to

the data bus during an IACK cycle is controlled by the setting of the

bits (2:1) in the GCCR (Global Chip Configuration Register)

Table 31. GICR – Global Interrupting Channel

Register

ÁÁÁÁÁÁÁ

Bits 7:3

ÁÁÁÁÁÁÁÁÁÁÁ

Bits 2:0

ÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁ

Channel code

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

100 = e 000 = a

101 = f 001 = b

110 = g 010 = c

111 = h 011 = d

A register associated with the interrupting channel as defined in the

CIR. It contains the interrupting channel code for all interrupts.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 29

Table 32. GIBCR – Global Interrupting Byte Count

Register

ÁÁÁÁÁÁ

Bits 7:4

ÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 3:0

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁ

Channel byte count code

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

0000 = 1 AND RxRDY status set for RxFIFO

0000 = 1 AND TxRDY status set for TxD

0001 = 2

0010 = 3

.

1111 = 16

A register associated with the interrupting channel as defined in the

CIR. Its numerical value equals

the number of bytes minus 1 (count – 1) ready for transfer to the

transmitter or transfer from the receiver. It is undefined for other

types of interrupts

Table 33. Global Interrupting Type Register

ÁÁÁÁÁÁÁÁÁ

Bit 7:6

ÁÁÁÁÁÁÁÁÁ

Bit 5

ÁÁÁÁÁÁÁÁÁÁ

Bit 4:3

ÁÁÁÁÁÁÁÁÁ

Bit 2:0

ÁÁÁÁÁÁÁÁÁ

Receiver Interrupt

ÁÁÁÁÁÁÁÁÁ

T ransmitter Interrupt

ÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁ

Other types

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

0x – not receiver

10 – with receive errors

11 – w/o receive errors

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

0 – not transmitter

1 – transmitter interrupt

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

read b’00

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

000 – not ”other” type

001 – Change of State

010 – Address Recognition

Event

011 – Xon/Xoff status

100 – Not used

101 – Break Change

11x – do not occur

A register associated with the interrupting channel as defined in the

CIR. It contains the type of interrupt code for all interrupts.

Table 34. GRxFIFO – Global RxFIFO Register

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 7:0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 data bits of RxFIFO. MSBs set to 0 for 7, 6, 5 bit data

The RxFIFO of the channel indicated in the CIR channel field.

Undefined when the CIR interrupt context is not a receiver interrupt.

Global TxFIFO Register

Table 35. GTxFIFO – Global TxFIFO Register

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 7:0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

8 data bits of TxFIFO. MSBs not used for 7, 6, 5 bit data

The TxFIFO of the channel indicated in the CIR channel field.

Undefined when the CIR interrupt context is not a transmitter

interrupt. Writing to the GTxFIFO when the current interrupt is not a

transmitter event may result in the characters being transmitted on a

different channel than intended.

Table 36. IPR – Input Port Register,

ÁÁÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁ

Bit 6

ÁÁÁÁÁÁ

Bit 7

ÁÁÁÁÁÁÁ

Bit 6

ÁÁÁÁ

Bit 3

ÁÁÁ

Bit 2

ÁÁÁÁ

Bit 1

ÁÁÁÁ

Bit 0

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

I/O3

change

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

I/O2

change

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

I/O1

change

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

I/O0

change

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

I/O3

state

ÁÁÁ

Á

ÁÁÁ

I/O2

state

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

I/O1

state

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

I/O0

state

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

0 – no change

1 – change

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

0 – no change

1 – change

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

0 – no change

1 – change

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

0 – no change

1 – change

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

The actual logic level at the I/O pin.

1 = high level; 0 =– low level.

This register may be read to determine the current level of the I/O

pins and examine the output of the change detectors assigned to each pin. If the change detection is not enabled or if the pin is

configured as an output, the associated change field will read b’0.

Table 37. I/OPIOR – I/O Port Interrupt and Output Register

ÁÁÁÁÁ

Bit 7

ÁÁÁÁÁÁ

Bit 6

ÁÁÁÁÁ

Bit 5

ÁÁÁÁÁ

Bit 4

ÁÁÁÁÁ

Bit 3

ÁÁÁÁÁ

Bit 2

ÁÁÁÁÁ

Bit 1

ÁÁÁÁÁ

Bit 0

ÁÁÁÁÁ

I/O3 enable

ÁÁÁÁÁÁ

I/O2 enable

ÁÁÁÁÁ

I/O1 enable

ÁÁÁÁÁ

I/O0 enable

ÁÁÁÁÁ

I/O3 output

ÁÁÁÁÁ

I/O2 output

ÁÁÁÁÁ

I/O1 output

ÁÁÁÁÁ

I/O0 output

ÁÁÁÁÁ

0 – disable

1 – enable

ÁÁÁÁÁÁ

0 – disable

1 – enable

ÁÁÁÁÁ

0 – disable

1 – enable

ÁÁÁÁÁ

0 – disable

1 – enable

ÁÁÁÁÁ

OPR[3]

ÁÁÁÁÁ

OPR[2]

ÁÁÁÁÁ

OPR[1]

ÁÁÁÁÁ

OPR[0]

I/OPIOR[7:4] bits activate the input change of state detectors. If a

pin is configured as an output, a b’1 value written to a I/O field has

no effect.

I/OPIOR[3:0] bits hold the datum which is the inverse of the datum

driven to its associated I/O pin when the I/OPCR control bits for that

pin are programmed to b’01.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 30

Table 38. I/OPCR – I/O Port Configuration Register

ÁÁÁÁÁÁÁÁÁ

Bits 7:6

ÁÁÁÁÁÁÁÁÁ

Bits 5:4

ÁÁÁÁÁÁÁÁÁÁ

Bits 3:2

ÁÁÁÁÁÁÁÁÁ

Bits 1:0

ÁÁÁÁÁÁÁÁÁ

I/O3 control

ÁÁÁÁÁÁÁÁÁ

I/O2 control

ÁÁÁÁÁÁÁÁÁÁ

I/O1 control

ÁÁÁÁÁÁÁÁÁ

I/O0 control

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

00 – GPI/TxC input

01 – I/OPIOR[3] output

10 – TxC16x output

11 – TxC1x output

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

00 – GPI/RxC input

01 – I/OPIOR[2]/RTSN *

10 – RxC1x output

11 – RxC16x output

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

00 – GPI input

01 – I/OPIOR[1]/RTSN *

10 – Reserved

11 – RxC1x output

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

00 – GPI/CTSN input

01 – I/OPIOR[0]output

10 – TxC1x output

11 – TxC16x output

* If I/OPCR(5:4) is programmed as ’01’ then the RTSN functionality

is assigned to I/O2, otherwise, this function can be implemented on

I/O1. (This allows for a lower pin count package option)

This register contains 4, 2 bit fields that set the direction and source

for each of the I/O pins associated with the channel. The I/O2

output may be RTSN if MR1[7] is set, or may signal ”end of

transmission” if MR2[5] is set.(Please see the descriptions of these

functions under the MR1 and MR2 register descriptions) If this

control bit is cleared, the pin will use the OPR[2] as a source if

I/OPCR[5:4] is b’01. The b’00 combinations are always inputs. This

register resets to x’0, effectively configuring all I/O pins as inputs on

power up or reset. Inputs may be used as RxC, TxC inputs or

CTSN and General Purpose Inputs simultaneously. All inputs are

equipped with change detectors that may be used to generate

interrupts or can be polled, as required.

NOTE: To ensure that CTSN, RTSN and an external RxC are

always available, if I/O2 is not selected as the RTSN output, the

RTSN function is automatically provided on I/O1.

GENERAL PURPOSE OUTPUT PIN CONTROL

The following four registers control the function of the GOUT0 pin.

These output pins have a unique control matrix which includes a

clocking mechanism that will allow the pin to change synchronously

with an internal or external stimulus. See diagram below.

Table 39. GPOSR – General Purpose Output

Select Register

GPOSR selects the signal or data source for the GOUT0 pin. The Tx

and Rx clock selection is straight forward. The selection of the

GPOR allows a more flexible timing control of when the GOUT0 pin

changes.

ÁÁÁÁÁÁ

Bits 7:4

ÁÁÁÁÁÁÁÁÁÁÁÁ

Bits 3:0

ÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁ

Global General Purpose Output 0 Selection

ÁÁÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁ

0000 – 0111 reserved

1000 = TxC1x a

1001 = TxC16x a

1010 = RxC16x a

1011 = TxC16x b

1100 = GGPOR(3)

1101 = GGPOR(2)

1110 = GGPOR(1)

1111 = GGPOR(0)

Table 40. GPOR – General Purpose Output

Register

This register is a read/write register. Its contents may be altered by

a GPOR Write or by the GPOC and GPOD registers shown below.

The GPOD and GPOC may be programmed to cause the individual

bits of the GPOR to change synchronously with internal or external

events. The cells of this register may be thought of as a “Two Port

flip-flop”; one port is controlled by a D input and clock, the other by a

data load strobe. A read of the GPOR always returns its current

value regardless of the port from which it was loaded.

ÁÁÁÁ

Bits 7:4

ÁÁÁÁ

Bit 3

ÁÁÁÁÁ

Bit 2

ÁÁÁÁ

Bit 1

ÁÁÁÁ

Bit 0

ÁÁÁÁ

Reserved

ÁÁÁÁ

GPOR(3)

ÁÁÁÁÁ

GPOR(2)

ÁÁÁÁ

GPOR(1)

ÁÁÁÁ

GPOR(0)

Table 41. GPOC – General Purpose Output Clk

Register

This controls the clock source for GPOR that will clock and/or toggle

the data from the selected GPOD source. When code b’00 is

selected, no clock will be provided, thereby preventing any change

through the D port.

ÁÁÁÁÁ

Bits 7:6

ÁÁÁÁÁ

Bits 5:4

ÁÁÁÁÁ

Bits 3:2

ÁÁÁÁÁ

Bits 1:0

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Clk Sel

GPOR(3)

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Clk Sel

GPOR(2)

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Clk Sel

GPOR(1)

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

Clk Sel

GPOR(0)

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

00 = none

01 = GIN0

10 = GIN1

11 = reserved

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

00 = none

01 = GIN0

10 = GIN1

11 = reserved

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

00 = none

01 = GIN0

10 = GIN1

11 = I/O3c

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

00 = none

01 = GIN0

10 = GIN1

11 = I/O3a

Table 42. GPOD – General Purpose Output Data

Register

This register selects the data that will be presented to the GPOR “D”

input. Note that selection b’10 selects the inverted GPOR data as

the input. In this case, the GPOR output will toggle synchronously

with the clock selected in the GPOC.

ÁÁÁÁÁ

Bits 7:6

ÁÁÁÁÁ

Bits 5:4

ÁÁÁÁÁ

Bits 3:2

ÁÁÁÁÁ

Bits 1:0

ÁÁÁÁÁ

Data Sel

GPOR(3)

ÁÁÁÁÁ

Data Sel

GPOR(2)

ÁÁÁÁÁ

Data Sel

GPOR(1)

ÁÁÁÁÁ

Data Sel

GPOR(0)

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

00 = ’1’

01 = ’0’

10 = GPOR3N

11 = reserved

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

00 = ’1’

01 = ’0’

10 = GPOR2N

11 = reserved

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

00 = ’1’

01 = ’0’

10 = GPOR1N

11 = I/O3d

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

00 = ’1’

01 = ’0’

10 = GPOR0N

11 = I/O3b

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 31

4:1 MULTIPLEX

“1”

“0”

NONE

1/O3a

D CLOCK

QN

D INPUT

DATA READ/WRITE

DATA IN/OUT

GPORQN

DATA BUS 3:0

GPOR R/W

GPOR

GPOD GPOSR

1/O3b

GIN0

GIN1

4:1 MULTIPLEX

GPO PIN

8:1 MULTIPLEX

TxC1Xa

TxC16Xa

RxC16Xa

TxC16Xb

GPOR(0)

GPOR(1)

GPOR(2)

GPOR(3)

SD00526

GPOC

4

Figure 1. General Purpose Pin Control Logic

REGISTER MAPS

The registers of the SC28L198 are partitioned into two groups: those

used in controlling data channels and those used in handling the

actual data flow and status. Below is shown the general

configuration of all the register addressed. The ”Register Map

Summary” shows the configuration of the lower four bits of the

address that is the same for the individual UARTs. It also shows the

addresses for the several in the address space of UART A and

UART B that apply to the total chip configuration. The ”Register

Map Detail” shows the use of every address in the 8 bit address

space.

NOTE: The register maps for channels A and B (UARTs A and B)

contain some control registers that configure the entire chip. These

are denoted by a ♣ symbol.

REGISTER MAP SUMMARY

Table 43. Summary Register Map, Control

ÁÁÁÁÁÁÁÁÁÁÁ

Address (hex) ccc = channel

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Register Name

ÁÁÁÁÁ

Acronym

ÁÁÁÁÁ

Read / Write

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 0000 (x00)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0a

ÁÁÁÁÁ

MR0

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 0001 (x01)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1a

ÁÁÁÁÁ

MR1

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 0010 (x02)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Configuration Reg a I/OPCRa

ÁÁÁÁÁ

IOPCR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 0011 (x03)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bid Control, Break Change

ÁÁÁÁÁ

BCRBRK

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 0100 (x04)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bid Control, Change of State

ÁÁÁÁÁ

BCRCOS

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 0110 (x06)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bid Control, Xon/Xoff

ÁÁÁÁÁ

BCRX

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 0111 (x07)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bid Control, Address recognition

ÁÁÁÁÁ

BCRA

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 1000 (x08)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Register

ÁÁÁÁÁ

XonCR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 1001 (x09)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Register

ÁÁÁÁÁ

XoffCR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 1010 (x0A)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Character

ÁÁÁÁÁ

ARCR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 1100 (x0C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register

ÁÁÁÁÁ

RxCSR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0000 1101 (x0D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Test Register

ÁÁÁÁÁÁÁÁÁ

Reserved, set to 0

ÁÁÁÁÁÁÁÁÁÁÁ

0ccc 1110 (x0E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter Clock Select Register

ÁÁÁÁÁ

TxCSR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0000 1111 (x0F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Chip Configuration Register

ÁÁÁÁÁ

GCCR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0001 1011 (x1B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Interrupt Control Register

ÁÁÁÁÁ

ICR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0001 1101 (x1D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣W atch-dog T imer Run Control

ÁÁÁÁÁ

WDTRCR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁÁ

0001 1111 (x1F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Interrupt Vector Register

ÁÁÁÁÁ

IVR

ÁÁÁÁÁ

R/W

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 32

Table 44. Summary Register Map, Data

ÁÁÁÁÁÁÁÁÁÁ

Address (hex) ccc = Channel

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Register Name

ÁÁÁÁÁÁÁ

Acronym

ÁÁÁÁÁ

Read/Write

ÁÁÁÁÁÁÁÁÁÁ

1ccc 0000 (x80)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 2

ÁÁÁÁÁÁÁ

MR2

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁ

1ccc 0001 (x81)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Status Register

ÁÁÁÁÁÁÁ

SR

ÁÁÁÁÁ

R

ÁÁÁÁÁÁÁÁÁÁ

1ccc 0001 (x81)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Command Register

ÁÁÁÁÁÁÁ

CR

ÁÁÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁ

1ccc 0010 (x82)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Status Register

ÁÁÁÁÁÁÁ

ISR

ÁÁÁÁÁ

R

ÁÁÁÁÁÁÁÁÁÁ

1ccc 0010 (x82)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Mask Register

ÁÁÁÁÁÁÁ

IMR

ÁÁÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁ

1ccc 0011 (x83)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter FIFO Register

ÁÁÁÁÁÁÁ

TxFIFO

ÁÁÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁ

1ccc 0011 (x83)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver FIFO Reg

ÁÁÁÁÁÁÁ

RxFIFO

ÁÁÁÁÁ

R

ÁÁÁÁÁÁÁÁÁÁ

1ccc 0100 (x84)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Port Reg

ÁÁÁÁÁÁÁ

IPR

ÁÁÁÁÁ

R

ÁÁÁÁÁÁÁÁÁÁ

1000 0100 (x84)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣BRG Timer Reg Upper a

ÁÁÁÁÁÁÁ

BRGTRUa

ÁÁÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁ

1ccc 0101 (x85)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output

ÁÁÁÁÁÁÁ

I/OPIOR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁ

1ccc 0110 (x86)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon/Xof f Interrupt Status Reg

ÁÁÁÁÁÁÁ

XISR

ÁÁÁÁÁ

R

ÁÁÁÁÁÁÁÁÁÁ

1000 0111 (x87)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣GP Out Select Reg

ÁÁÁÁÁÁÁ

GPOSR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁ

1000 1011 (x8B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣GP Out Clk Reg

ÁÁÁÁÁÁÁ

GPOC

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁ

1000 1100 (x8C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Update Current Interrupt Reg

ÁÁÁÁÁÁÁ

UCIR

ÁÁÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁ

1000 1100 (x8C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Current Interrupt Reg

ÁÁÁÁÁÁÁ

CIR

ÁÁÁÁÁ

R

ÁÁÁÁÁÁÁÁÁÁ

1001 1101 (x9D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣BRG Timer Reg Upper b

ÁÁÁÁÁÁÁ

BRGTRUb

ÁÁÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁ

1000 1110 (x8E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Receive FIFO Reg

ÁÁÁÁÁÁÁ

GRxFIFO

ÁÁÁÁÁ

R

ÁÁÁÁÁÁÁÁÁÁ

1000 1110 (x8E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global T ransmit FIFO Reg

ÁÁÁÁÁÁÁ

GTxFIFO

ÁÁÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁ

1000 1111 (x8F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Chip Configuration Reg

ÁÁÁÁÁÁÁ

GCCR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁ

1001 0100 (x94)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣BRG Timer Reg Lower a

ÁÁÁÁÁÁÁ

BGRTRLa

ÁÁÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁ

1001 0111 (x97)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣GP Output Reg

ÁÁÁÁÁÁÁ

GPOR

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁ

1001 1011 (x9B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣GP Out Data Reg

ÁÁÁÁÁÁÁ

GPOD

ÁÁÁÁÁ

R/W

ÁÁÁÁÁÁÁÁÁÁ

1001 1100 (x9C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣BRG Timer Control Reg

ÁÁÁÁÁÁÁ

BRGTCR

ÁÁÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁ

1001 1100 (x9C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Interrupt Channel Reg

ÁÁÁÁÁÁÁ

GICR

ÁÁÁÁÁ

R

ÁÁÁÁÁÁÁÁÁÁ

1001 1101 (x9D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣BRG Timer Reg Lower b

ÁÁÁÁÁÁÁ

BRGTRLb

ÁÁÁÁÁ

W

ÁÁÁÁÁÁÁÁÁÁ

1001 1101 (x9D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Interrupt Byte Count

ÁÁÁÁÁÁÁ

GIBCR

ÁÁÁÁÁ

R

ÁÁÁÁÁÁÁÁÁÁ

1001 1111 (x9F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Interrupt Type Register

ÁÁÁÁÁÁÁ

GITR

ÁÁÁÁÁ

R

REGISTER MAP DETAIL

Table 45. Register Map, Control

NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip. These are

denoted by a ♣symbol

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART A

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

0000 0000 (x00)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0a

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0a

ÁÁÁÁÁÁÁ

0000 0001 (x01)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1a

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1a

ÁÁÁÁÁÁÁ

0000 0010 (x02)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Configuration Reg a I/OPCRa

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Configuration Reg a I/OPCRa

ÁÁÁÁÁÁÁ

0000 0011 (x03)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKa

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKa

ÁÁÁÁÁÁÁ

0000 0100 (x04)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSa

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSa

ÁÁÁÁÁÁÁ

0000 0101 (x05)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

0000 0110 (x06)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXa

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXa

ÁÁÁÁÁÁÁ

0000 0111 (x07)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAa

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAa

ÁÁÁÁÁÁÁ

0000 1000 (x08)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg a (XonCRa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg a (XonCRa)

ÁÁÁÁÁÁÁ

0000 1001 (x09)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg a (XoffCRa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg a (XoffCRa)

ÁÁÁÁÁÁÁ

0000 1010 (x0A)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Character a (ARCRa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Character a (ARCRa)

ÁÁÁÁÁÁÁ

0000 1011 (x0B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

0000 1100 (x0C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register a (RxCSRa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register a (RxCSRa)

ÁÁÁÁÁÁÁ

0000 1101 (x0D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Test Register

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Test Register

ÁÁÁÁÁÁÁ

0000 1110 (x0E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register a TxCSRa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register a TxCSRa)

ÁÁÁÁÁÁÁ

0000 1111 (x0F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Chip Configuration Reg(GCCR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Global Chip Configuration Reg GCCR)

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 33

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART B

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

0001 0000 (x10)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0b

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0b

ÁÁÁÁÁÁÁ

0001 0001 (x11)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1b

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1b

ÁÁÁÁÁÁÁ

0001 0010 (x12)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Configuration Reg b I/OPCRb

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Configuration Reg b I/OPCRb

ÁÁÁÁÁÁÁ

0001 0011 (x13)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKb

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKb

ÁÁÁÁÁÁÁ

0001 0100 (x14)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSb

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSb

ÁÁÁÁÁÁÁ

0001 0101 (x15)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

0001 0110 (x16)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXb

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXb

ÁÁÁÁÁÁÁ

0001 0111 (x17)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAb

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAb

ÁÁÁÁÁÁÁ

0001 1000 (x18)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg b (XonCRb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg b (XonCRb)

ÁÁÁÁÁÁÁ

0001 1001 (x19)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg b (XoffCRb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg b (XoffCRb)

ÁÁÁÁÁÁÁ

0001 1010 (x1A)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Character b (ARCRb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Character b (ARCRb)

ÁÁÁÁÁÁÁ

0001 1011 (x1B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Interrupt Control Register (ICR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Control Register (ICR)

ÁÁÁÁÁÁÁ

0001 1100 (x1C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register b (RxCSRb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register b (RxCSRb)

ÁÁÁÁÁÁÁ

0001 1101 (x1D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣W atch-dog Timer Run Control (WDTRCR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

W atch-dog Timer Run Control (WDTRCR)

ÁÁÁÁÁÁÁ

0001 1110 (x1E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register b (TxCSRb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register b (TxCSRb)

ÁÁÁÁÁÁÁ

0001 1111 (x1F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Interrupt Vector Register (IVR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Vector Register (IVR)

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART C

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

0010 0000 (x20)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0c

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0c

ÁÁÁÁÁÁÁ

0010 0001 (x21)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1c

ÁÁÁÁÁÁÁ

0010 0010 (x22)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Configuration Reg c I/OPCRc

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Configuration Reg c I/OPCRc

ÁÁÁÁÁÁÁ

0010 0011 (x23)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKc

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKc

ÁÁÁÁÁÁÁ

0010 0100 (x24)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSc

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSc

ÁÁÁÁÁÁÁ

0010 0101 (x25)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

0010 0110 (x26)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXc

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXc

ÁÁÁÁÁÁÁ

0010 0111 (x27)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAc

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAc

ÁÁÁÁÁÁÁ

0010 1000 (x28)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg c (XonCRc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg c (XonCRc)

ÁÁÁÁÁÁÁ

0010 1001 (x29)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg c (XoffCRc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg c (XoffCRc)

ÁÁÁÁÁÁÁ

0010 1010 (x2A)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Character c (ARCRc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Character c (ARCRc)

ÁÁÁÁÁÁÁ

0010 1011 (x2B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

0010 1100 (x2C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register c (RxCSRc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register c (RxCSRc)

ÁÁÁÁÁÁÁ

0010 1101 (x2D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

0010 1110 (x2E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register c (TxCSRc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register c (TxCSRc)

ÁÁÁÁÁÁÁ

0010 1111 (x2F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 34

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART D

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

0011 0000 (x30)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0d

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0d

ÁÁÁÁÁÁÁ

0011 0001 (x31)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1d

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1d

ÁÁÁÁÁÁÁ

0011 0010 (x32)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Configuration Reg d I/OPCRd

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Configuration Reg d I/OPCRd

ÁÁÁÁÁÁÁ

0011 0011 (x33)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKd

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKd

ÁÁÁÁÁÁÁ

0011 0100 (x34)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSd

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSd

ÁÁÁÁÁÁÁ

0011 0101 (x35)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

0011 0110 (x36)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXd

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXd

ÁÁÁÁÁÁÁ

0011 0111 (x37)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAd

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAd

ÁÁÁÁÁÁÁ

0011 1000 (x38)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg d (XonCRd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg d (XonCRd)

ÁÁÁÁÁÁÁ

0011 1001 (x39)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg d (XoffCRd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg d (XoffCRd)

ÁÁÁÁÁÁÁ

0011 1010 (x3A)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Character d (ARCRd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Character d (ARCRd)

ÁÁÁÁÁÁÁ

0011 1011 (x3B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

0011 1100 (x3C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register d (RxCSRd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register d (RxCSRd)

ÁÁÁÁÁÁÁ

0011 1101 (x3D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

0011 1110 (x3E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register d (TxCSRd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register d (TxCSRd)

ÁÁÁÁÁÁÁ

0011 1111 (x3F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART E

ÁÁÁÁÁÁÁ

01000000 (x40)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0e

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0e

ÁÁÁÁÁÁÁ

01000001 (x41)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1e

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1e

ÁÁÁÁÁÁÁ

01000010 (x42)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/OPort Configuration Reg e I/OPCRe

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/OPort Configuration Reg e I/OPCRe

ÁÁÁÁÁÁÁ

01000011 (x43)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKe

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKe

ÁÁÁÁÁÁÁ

01000100 (x44)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSe

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSe

ÁÁÁÁÁÁÁ

01000101 (x45)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01000110 (x46)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXe

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXe

ÁÁÁÁÁÁÁ

01000111 (x47)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAe

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAe

ÁÁÁÁÁÁÁ

01001000 (x48)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg e (XonCRe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg e (XonCRe)

ÁÁÁÁÁÁÁ

01001001 (x49)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg e (XoffCRe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg e (XoffCRe)

ÁÁÁÁÁÁÁ

01001010 (x4A)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Char e (ARCRe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Char e (ARCRe)

ÁÁÁÁÁÁÁ

01001011 (x4B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01001100 (x4C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register e (RxCSRe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register e (RxCSRe)

ÁÁÁÁÁÁÁ

01001101 (x4D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01001110 (x4E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register e (TxCSRe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register e (TxCSRe)

ÁÁÁÁÁÁÁ

01001111 (x4F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 35

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART F

ÁÁÁÁÁÁÁ

01010000 (x50)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0f

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0f

ÁÁÁÁÁÁÁ

01010001 (x51)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1f

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1f

ÁÁÁÁÁÁÁ

01010010 (x52)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/OPort Configuration Reg f I/OPCRf

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/OPort Configuration Reg f I/OPCRf

ÁÁÁÁÁÁÁ

01010011 (x53)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKf

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKf

ÁÁÁÁÁÁÁ

01010100 (x54)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSf

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSf

ÁÁÁÁÁÁÁ

01010101 (x55)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01010110 (x56)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXf

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXf

ÁÁÁÁÁÁÁ

01010111 (x57)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAf

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAf

ÁÁÁÁÁÁÁ

01011000 (x58)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg f (XonCRf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg f (XonCRf)

ÁÁÁÁÁÁÁ

01011001 (x59)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg f (XoffCRf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg f (XoffCRf)

ÁÁÁÁÁÁÁ

01011010 (x5A)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Char f (ARCRf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Char f (ARCRf)

ÁÁÁÁÁÁÁ

01011011 (x5B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01011100 (x5C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register f (RxCSRf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register f (RxCSRf)

ÁÁÁÁÁÁÁ

01011101 (x5D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01011110 (x5E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register f (TxCSRf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register f (TxCSRf)

ÁÁÁÁÁÁÁ

01011111 (x5F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART G

ÁÁÁÁÁÁÁ

01100000 (x60)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0g

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0g

ÁÁÁÁÁÁÁ

01100001 (x61)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1g

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1g

ÁÁÁÁÁÁÁ

01100010 (x62)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/OPort Configuration Reg g I/OPCRg

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/OPort Configuration Reg g I/OPCRg

ÁÁÁÁÁÁÁ

01100011 (x63)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKg

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKg

ÁÁÁÁÁÁÁ

01100100 (x64)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSg

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSg

ÁÁÁÁÁÁÁ

01100101 (x65)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01100110 (x66)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXg

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXg

ÁÁÁÁÁÁÁ

01100111 (x67)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAg

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAg

ÁÁÁÁÁÁÁ

01101000 (x68)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg g (XonCRg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg g (XonCRg)

ÁÁÁÁÁÁÁ

01101001 (x69)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg g (XoffCRg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg g (XoffCRg)

ÁÁÁÁÁÁÁ

01101010 (x6A)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Char g (ARCRg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Char g (ARCRg)

ÁÁÁÁÁÁÁ

01101011 (x6B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01101100 (x6C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register g (RxCSRg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register g (RxCSRg)

ÁÁÁÁÁÁÁ

01101101 (x6D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01101110 (x6E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register g (TxCSRg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register g (TxCSRg)

ÁÁÁÁÁÁÁ

01101111 (x6F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 36

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART H

ÁÁÁÁÁÁÁ

01110000 (x70)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 0 MR0h

ÁÁÁÁÁÁÁ

01110001 (x71)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1h

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register 1 MR1h

ÁÁÁÁÁÁÁ

01110010 (x72)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/OPort Configuration Reg h I/OPCRh

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/OPort Configuration Reg h I/OPCRh

ÁÁÁÁÁÁÁ

01110011 (x73)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKh

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRBRKh

ÁÁÁÁÁÁÁ

01110100 (x74)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSh

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRCOSh

ÁÁÁÁÁÁÁ

01110101 (x75)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01110110 (x76)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXh

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRXh

ÁÁÁÁÁÁÁ

01110111 (x77)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAh

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

BCRAh

ÁÁÁÁÁÁÁ

0111 1000 (x78)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg h (XonCRh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon Character Reg h (XonCRh)

ÁÁÁÁÁÁÁ

0111 1001 (x79)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg h (XoffCRh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xoff Character Reg h (XoffCRh)

ÁÁÁÁÁÁÁ

0111 1010 (x7A)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Char h (ARCRh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Recognition Char h (ARCRh)

ÁÁÁÁÁÁÁ

01111011 (x7B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01111100 (x7C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register h (RxCSRh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Clock Select Register h (RxCSRh)

ÁÁÁÁÁÁÁ

01111101 (x7D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

01111110 (x7E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register h (TxCSRh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xmit Clock Select Register h (TxCSRh)

ÁÁÁÁÁÁÁ

01111111 (x7F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 37

Table 46. Register Map, Data

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART A

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

1000 0000 (x80)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register a (MR2a)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register a (MR2a)

ÁÁÁÁÁÁÁ

1000 0001 (x81)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Status Register a (SRa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Command Register a (CRa)

ÁÁÁÁÁÁÁ

1000 0010 (x82)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Status Register a (ISRa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Mask Register a (IMRa)

ÁÁÁÁÁÁÁ

1000 0011 (x83)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver FIFO Reg a (RxFIFOa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter FIFO Reg a (TxFIFOa)

ÁÁÁÁÁÁÁ

1000 0100 (x84)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣BRG Timer Reg Upper a (BRGTRUa)

ÁÁÁÁÁÁÁ

1000 0100 (x84)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Port Reg a (IPRa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1000 0101 (x85)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output a I/OPIORa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output a (I/OPIORa)

ÁÁÁÁÁÁÁ

1000 0110 (x86)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon/Xof f Interrupt Status Reg a (XISRa)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1000 0111 (x87)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣GP Out Select Reg (GPOSR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

GP Out Select Reg (GPOSR)

ÁÁÁÁÁÁÁ

1000 1011 (x8B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣GP Out Clk Reg (GPOC)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

GP Out Clk Reg (GPOC)

ÁÁÁÁÁÁÁ

1000 1100 (x8C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Current Interrupt Reg (CIR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Update CIR

ÁÁÁÁÁÁÁ

1000 1101 (x8D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣BRG Timer Reg Upper b (BRGTRUb)

ÁÁÁÁÁÁÁ

1000 1110 (x8E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Receive FIFO Reg (GRxFIFO)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Transmit FIFO Reg (GTxFIFO)

ÁÁÁÁÁÁÁ

1000 1111 (x8F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Chip Configuration Reg (GCCR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Chip Configuration Reg (GCCR)

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART B

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

1001 0000 (x90)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register b (MR2b)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register b (MR2b)

ÁÁÁÁÁÁÁ

1001 0001 (x91)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Status Register b (SRb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Command Register b (CRb)

ÁÁÁÁÁÁÁ

1001 0010 (x92)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Status Register b (ISRb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Mask Register b (IMRb)

ÁÁÁÁÁÁÁ

1001 0011 (x93)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver FIFO Reg b (RxFIFOb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter FIFO Reg b (TxFIFOb)

ÁÁÁÁÁÁÁ

1001 0100 (x94)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣BRG Timer Reg Lower a (BRGTRLa)

ÁÁÁÁÁÁÁ

1001 0100 (x94)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Port Reg b (IPRb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1001 0101 (x95)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output b (I/OPIORb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output b (I/OPIORb)

ÁÁÁÁÁÁÁ

1001 0110 (x96)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon/Xof f Interrupt Status Reg b (XISRb)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1001 0111 (x97)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣GP Output Reg (GPOR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣GP Output Reg (GPOR)

ÁÁÁÁÁÁÁ

1001 1010 (x9A)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1001 1011 (x9B)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣GP Out Data Reg (GPOD)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣GP Out Data Reg (GPOD)

ÁÁÁÁÁÁÁ

1001 1100 (x9C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣BRG Timer Control Reg (BRGCTCR)

ÁÁÁÁÁÁÁ

1001 1100 (x9C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Interrupt Channel Reg (GICR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1001 1101 (x9D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣BRG Timer Reg Lower b (BRGTRLb)

ÁÁÁÁÁÁÁ

1001 1101 (x9D)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Interrupt Byte Count (GIBCR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1001 1110 (x9E)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1001 1111 (x9F)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

♣Global Interrupt Type Register (GITR)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 38

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART C

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

1010 0000 (xA0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register c (MR2c)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register c (MR2c)

ÁÁÁÁÁÁÁ

1010 0001 (xA1)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Status Register c (SRc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Command Register c (CRc)

ÁÁÁÁÁÁÁ

1010 0010 (xA2)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Status Register c (ISRc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Mask Register c (IMRc)

ÁÁÁÁÁÁÁ

1010 0011 (xA3)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver FIFO Reg c (RxFIFOc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter FIFO Reg c (TxFIFOc)

ÁÁÁÁÁÁÁ

1010 0100 (xA4)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Port Reg c (IPRc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1010 0101 (xA5)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output c (I/OPIORc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output c (I/OPIORc)

ÁÁÁÁÁÁÁ

1010 0110 (xA6)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon/Xof f Interrupt Status Reg c (XISRc)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1010 0111 (xA7)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1010 1000 (xA8)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1010 1001 (xA9)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1010 1010 (xAA)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1010 1011 (xAB)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1010 1100 (xAC)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1010 1101 (xAD)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1010 1110 (xAE)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1010 1111 (xAF)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART D

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

1011 0000 (xB0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register d (MR2d)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register d (MR2d)

ÁÁÁÁÁÁÁ

1011 0001 (xB1)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Status Register d (SRd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Command Register d (CRd)

ÁÁÁÁÁÁÁ

1011 0010 (xB2)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Status Register d (ISRd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Mask Register d (IMRd)

ÁÁÁÁÁÁÁ

1011 0011 (xB3)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver FIFO Reg d (RxFIFOd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter FIFO Reg d (TxFIFOd)

ÁÁÁÁÁÁÁ

1011 0100 (xB4)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Port Reg d (IPRd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1011 0101 (xB5)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output d (I/OPIORd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output d (I/OPIORd)

ÁÁÁÁÁÁÁ

1011 0110 (xB6)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon/Xof f Interrupt Status Reg d (XISRd)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1011 0111 (xB7)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1011 1000 (xBB)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1011 1001 (xB9)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1011 1010 (xBA)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1011 1011 (xBB)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1011 1100 (xBC)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1011 1101 (xBD)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1011 1110 (xBE)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

1011 1111 (xBF)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 39

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART E

ÁÁÁÁÁÁÁ

11000000 (xC0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register e (MR2e)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register e (MR2e)

ÁÁÁÁÁÁÁ

11000001 (xC1)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Status Register e (SRe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Command Register e (CRe)

ÁÁÁÁÁÁÁ

11000010 (xC2)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Status Register e (ISRe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Mask Register e (IMRe)

ÁÁÁÁÁÁÁ

11000011 (xC3)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver FIFO Reg e (RxFIFOe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter FIFO Reg e (TxFIFOe)

ÁÁÁÁÁÁÁ

11000100 (xC4)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Port Reg e (IPRe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11000101 (xC5)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output e (I/OPIORe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output e (I/OPIORe)

ÁÁÁÁÁÁÁ

11000110 (xC6)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon/Xof fInterrupt Status Reg e (XISRe)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11000111 (xC7)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11001000 (xC8)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11001001 (xC9)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11001010 (xCA)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11001011 (xCB)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11001100 (xCC)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11001101 (xCD)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11001110 (xCE)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11001111 (xCF)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART F

ÁÁÁÁÁÁÁ

11010000 (xD0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register f (MR2f)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register f (MR2f)

ÁÁÁÁÁÁÁ

11010001 (xD1)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Status Register f (SRf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Command Register f (CRf)

ÁÁÁÁÁÁÁ

11010010 (xD2)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Status Register f (ISRf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Mask Register f (IMRf)

ÁÁÁÁÁÁÁ

11010011 (xD3)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver FIFO Reg f (RxFIFOf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter FIFO Reg f (TxFIFOf)

ÁÁÁÁÁÁÁ

11010100 (xD4)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Port Reg f (IPRf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11010101 (xD5)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output f (I/OPIORf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output f (I/OPIORf)

ÁÁÁÁÁÁÁ

11010110 (xD6)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon/Xof fInterrupt Status Reg f (XISRf)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11010111 (xD7)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11011000 (xD8)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11011001 (xD9)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11011010 (xDA)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11011011 (xDB)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11011100 (xDC)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11011101 (xDD)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11011110 (xDE)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11011111 (xDF)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 40

ÁÁÁÁÁÁÁ

A(7:0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART G

ÁÁÁÁÁÁÁ

11100000 (xE0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register g (MR2g)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register g (MR2g)

ÁÁÁÁÁÁÁ

11100001 (xE1)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Status Register g (SRg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Command Register g (CRg)

ÁÁÁÁÁÁÁ

11100010 (xE2)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Status Register g (ISRg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Mask Register g (IMRg)

ÁÁÁÁÁÁÁ

11100011 (xE3)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver FIFO Reg g (RxFIFOg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter FIFO Reg g (TxFIFOg)

ÁÁÁÁÁÁÁ

11100100 (xE4)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Port Reg g (IPRg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11100101 (xE5)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output g (I/OPIORg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output g (I/OPIORg)

ÁÁÁÁÁÁÁ

11100110 (xE6)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon/Xof fInterrupt Status Reg g (XISRg)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11100111 (xE7)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11101000 (xE8)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11101001 (xE9)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11101010 (xEA)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11101011 (xEB)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11101100 (xEC)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11101101 (xED)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11101110 (xEE)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11101111 (xEF)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

UART H

ÁÁÁÁÁÁÁ

11110000 (xF0)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register h (MR2h)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Mode Register h (MR2h)

ÁÁÁÁÁÁÁ

11110001 (xF1)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Status Register h (SRh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Command Register h (CRh)

ÁÁÁÁÁÁÁ

11110010 (xF2)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Status Register h (ISRh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Mask Register h (IMRh)

ÁÁÁÁÁÁÁ

11110011 (xF3)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver FIFO Reg h (RxFIFOh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

T ransmitter FIFO Reg h (TxFIFOh)

ÁÁÁÁÁÁÁ

11110100 (xF4)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input Port Reg h (IPRh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11110101 (xF5)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output h (I/OPIORh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Interrupt and Output h (I/OPIORh)

ÁÁÁÁÁÁÁ

11110110 (xF6)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Xon/Xof fInterrupt Status Reg h (XISRh)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11110111 (xF7)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11111000 (xF8)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11111001 (xF9)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11111010 (xFA)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11111011 (xFB)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11111100 (xFC)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11111101 (xFD)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11111110 (xFE)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁ

11111111 (xFF)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reserved

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 41

RESET CONDITIONS

Device Configuration after Hardware Reset or CRa

cmd=x1F

Cleared registers:

Channel Status Registers (SR)

Channel Interrupt Status Registers (ISR)

Channel Interrupt Mask Registers (IMR)

Channel Interrupt Xon Status Register (XISR)

Interrupt Control Register (ICR)

Global Configuration Control Register (GCCR)

Hence the device enters the asynchronous bus cycling mode.

Current Interrupt Register (CIR)

BRG Timer Run Control Register (BRGTCR)

W atch-dog Timer Run Control Register (WDTRCR)

Channel Input/Output Port Configuration Registers (I/OPCR)

Hence all I/O pins have direction = Input after reset

BRG Counter/T imer Registers

Clears Modes for:

Power down

Test modes

Input Port Changed bits

Gang write to Xon or Xoff

Xon/Xof f/Address detection

Receiver error status

Disables:

Transmitters

Receivers

Interrupts, current and future

Halts:

BRG Counters

Bus cycle in progress (hardware RESET only)

Limitations:

Minimum RESETN pin pulse width is 10 SClk cycles after Vcc

reaches operational range

The user must allow a minimum of 6 SClk cycles to elapse after

a reset (RESETN pin or CRa initiated) of the device terminates

before initiating a new bus cycle.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 42

DC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (5V)

VCC = 5.0 volts  10%; TA = –40 °C to +85°C; unless otherwise specified

ÁÁÁÁÁ

SYMBOL

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁ

TEST

ÁÁÁÁÁÁÁÁÁ

LIMITS

ÁÁÁÁ

UNIT

ÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

CONDITIONS

ÁÁÁÁ

MIN

ÁÁÁÁ

TYP1

ÁÁÁ

MAX

ÁÁÁÁ

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

VIL

VIH

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input low voltage2

Input high voltage (except X1/CLK)

Input high voltage (X1/CLK)

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

VSS

2.0

0.8VCC

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

Á

ÁÁÁ

0.8

Vcc

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

V

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

VOL3

VOH

VOL3

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output low voltage4

Output high voltage (except OD outputs)

Open Drain low voltage

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

IOL = 4.0mA

IOH = –400 mA

IOH = –100 mA

IOL = 14.0 mA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0.8VCC

0.9VCC

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0.15

<0.25

ÁÁÁ

Á

ÁÁÁ

0.4

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

V

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

IIL

IIH

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input current low, I/O pins

Input current high, I/O pins

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

VIN = 0

ViN = Vcc

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

–10

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

<0.1

ÁÁÁ

Á

ÁÁÁ

10

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

mA

ÁÁÁÁÁ

IL

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input leakage current

ÁÁÁÁÁÁÁ

VIN = 0 to Vcc

ÁÁÁÁ

–5

ÁÁÁÁ

<1

ÁÁÁ

5

ÁÁÁÁ

mA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

IILCKX1

IIHCKX1

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/CLK input low current

X1/CLK input high current

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

VIN=Vss,X2=Open

VIN=Vcc, X2=Open

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

–450

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

Á

ÁÁÁ

450

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

mA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

IOZH

IOZL

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output off current high, 3–state data bus

Output off current low, 3–state data bus

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

VIN = VCC

VIN = 0

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

–10

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

<.1

ÁÁÁ

Á

ÁÁÁ

10

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

mA

ÁÁÁÁÁ

IODL

IODH

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Open–drain output low current in off state

Open drain output high current in off state

ÁÁÁÁÁÁÁ

VIN = 0

VIN = VCC

ÁÁÁÁ

–10

ÁÁÁÁ

<.1

ÁÁÁ

10

ÁÁÁÁ

mA

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

ICC

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power supply current

Operating mode 33 MHz

Static Power down (No clocks, Open–drains off,

inputs at VSS or VCC)

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

TTL Input levels

CMOS input levels

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

100

26

0.6

ÁÁÁ

Á

ÁÁÁ

150

40

5

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

mA

NOTES:

1. Typical values are at +25 °C, typical supply voltage and typical processing parameters.

2. All voltage measurements are referenced to VSS. For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of 10 ns

maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. all time measurements are referenced at input voltages of VIL and VIH as

appropriate.

3. Test conditions for itnerrupt and I/O outputs: CL = 50 pF. Test conditions for the rest of the outputs: CL = 60 pF.

4. Simultaneous switching more than 6 I/O port pins from 5 volts to 0 volts at full capacitive load may ground bounce on the output pins up to

0.95 volts.

5. All RX, TX, Brg Timer, I/O pins operating at 16 MHz. Sclk at 35 MHz and VCC at 5.6 volts. A worst–case environment.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 43

AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (5V)

VCC = 5.0 volts  10%; TA = –40 °C to +85°C; unless otherwise specified

ÁÁÁÁÁ

SYMBOL

ÁÁÁ

FIG #

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁ

LIMIT

ÁÁÁÁ

UNIT

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁ

MIN

ÁÁÁÁ

TYP

ÁÁÁ

MAX

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Timing

ÁÁÁÁÁ

tRES1

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RESET pulse width

ÁÁÁ

10

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

Sclk

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bus Timing

ÁÁÁÁÁ

tAS

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0–A7 setup time before Sclk C3 rising edge

ÁÁÁ

10

ÁÁÁÁ

2

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tAH

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0–A7 hold time after Sclk C3 rising edge

ÁÁÁ

18

ÁÁÁÁ

8

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tCS

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN setup time before Sclk C1 high (Sync)

ÁÁÁ

5

ÁÁÁÁ

3

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN setup time before Sclk C2 high (Async)

ÁÁÁ

5

ÁÁÁÁ

3

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tCH

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN hold time after Sclk C3 high (Sync)

ÁÁÁ

14

ÁÁÁÁ

1½Sclk

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN hold time after Sclk C4 high (Async)

ÁÁÁ

25

ÁÁÁÁ

1½Sclk

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tSTP

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN high before next C2 to stop next cycle (Sync Mode)2

ÁÁÁ

18

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tRWS

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

W–Rn setup time before Sclk C2 rising edge

ÁÁÁ

5

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tRWH

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

W–Rn hold time after Sclk C3 rising edge

ÁÁÁ

14

ÁÁÁÁ

1½Sclk

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tDD

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read cycle Data valid after Sclk C3 rising edge

ÁÁÁ

ÁÁÁÁ

12

ÁÁÁÁ

25

ÁÁÁ

ns

ÁÁÁÁÁ

tDF

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read cycle data bus floating after CEN high (Sync)

ÁÁÁ

ÁÁÁÁ

10

ÁÁÁÁ

16

ÁÁÁ

ns

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read cycle data bus floating after C4 end high (Async)

ÁÁÁ

ÁÁÁÁ

10

ÁÁÁÁ

15

ÁÁÁ

ns

ÁÁÁÁÁ

tDS

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write cycle data setup time before Sclk C4 rising edge

ÁÁÁ

25

ÁÁÁÁ

14

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tDH

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write cycle data hold time after Sclk C4 rising edge

ÁÁÁ

15

ÁÁÁÁ

8

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tRWD

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High time between CEN low (Async)

ÁÁÁ

12

ÁÁÁÁ

½ Sclk

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Pin Timing

ÁÁÁÁÁ

tPS

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O input setup time before Sclk C3 rising edge

ÁÁÁ

18

ÁÁÁÁ

4

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tPH

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O input hold time after Sclk C4 rising edge

ÁÁÁ

12

ÁÁÁÁ

1

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tPD

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O output valid from:

Write Sclk C4 rising edge (write to IOPIOR)

ÁÁÁ

ÁÁÁÁ

32

ÁÁÁÁ

50

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Timing

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

tIR

ÁÁÁ

Á

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IRQN from:

Internal interrupt source active bid

Reset to IRQN inactive

Write IMR (set or clear IMR bit)3

ÁÁÁ

Á

ÁÁÁ

22

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

26

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

43

75

45

ÁÁÁ

Á

ÁÁÁ

Sclk

ns

ÁÁÁÁÁ

tDD

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IACKN cycle Data valid after Sclk C3 rising edge

ÁÁÁ

ÁÁÁÁ

12

ÁÁÁÁ

25

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Tx/Rx Clock Timing

ÁÁÁÁÁ

tRX

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC high or low time

ÁÁÁ

15

ÁÁÁÁ

8

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

FRX4

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC frequency (16 X)

(1 X)

ÁÁÁ

0

ÁÁÁÁ

16

1

ÁÁÁ

Mhz

ÁÁÁÁÁ

tTX

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC high or low time

ÁÁÁ

15

ÁÁÁÁ

7

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

FTX4

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC frequency (16 X)

(1 X)

ÁÁÁ

0

ÁÁÁÁ

16

1

ÁÁÁ

Mhz

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmitter Timing

ÁÁÁÁÁ

tTXD

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxD output delay from TxC low

ÁÁÁ

ÁÁÁÁ

32

ÁÁÁÁ

60

ÁÁÁ

ns

ÁÁÁÁÁ

ttcs

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC output delay from TxD output data

ÁÁÁ

–15

ÁÁÁÁ

4

ÁÁÁÁ

15

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Timing

ÁÁÁÁÁ

tRXS

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data setup time to RxC high (data)

ÁÁÁ

20

ÁÁÁÁ

–4

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

tRXH

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data hold time from RxC high (data)

ÁÁÁ

20

ÁÁÁÁ

6

ÁÁÁÁ

ÁÁÁ

ns

ÁÁÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁÁÁ

tsSTRT

ÁÁÁ

Á

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data low time for receiving a valid Start Bit

ÁÁÁ

Á

ÁÁÁ

17/32

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

Á

ÁÁÁ

bit

time

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 44

AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (5 V) (Continued)

VCC = 5.0 volts  10 %; TA = –40 °C to +85 °C; unless otherwise specified

ÁÁÁÁÁ

SYMBOL

ÁÁÁ

FIG#

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁ

LIMITS

ÁÁÁ

UNIT

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁ

MIN

ÁÁÁÁ

TYP

ÁÁÁ

MAX

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sclk Timing

ÁÁÁÁÁ

tsclkl

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Min low time at VIL (0.8V)

ÁÁÁ

11

ÁÁÁÁ

5

ÁÁÁ

ns

ÁÁÁÁÁ

tsclkh

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Min high time at VIH (2.0V)

ÁÁÁ

11

ÁÁÁÁ

5

ÁÁÁ

ns

ÁÁÁÁÁ

Fsclk

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sclk frequency

ÁÁÁ

0.1

ÁÁÁÁ

ÁÁÁ

33

ÁÁÁ

MHz

ÁÁÁÁÁ

t/RFsck

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sclk rise and fall time (0.8 to 2.0Volts)

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

3

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/X2 Communication Crystal Clock

ÁÁÁÁÁ

Fx15

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1 clock frequency

ÁÁÁ

1

ÁÁÁÁ

3.6864

ÁÁÁ

8.0

ÁÁÁ

MHz

ÁÁÁÁÁ

X1 L / H

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1 Low / High time

ÁÁÁ

32

ÁÁÁÁ

135

ÁÁÁ

ns

ÁÁÁÁÁ

T/RFx1

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1 Rise and Fall time

ÁÁÁ

ÁÁÁÁ

ÁÁÁ

10

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Counter/Timer Baud Rate Clock (External Clock Input)

ÁÁÁÁÁ

FC/T4

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Clock frequency

ÁÁÁ

0

ÁÁÁÁ

ÁÁÁ

8

ÁÁÁ

MHz

ÁÁÁÁÁ

TC/TLH

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

C/T high and low time

ÁÁÁ

15

ÁÁÁÁ

11

ÁÁÁ

ns

ÁÁÁÁÁ

TC/TO

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Delay C/T clock external to output pin

ÁÁÁ

ÁÁÁÁ

48

ÁÁÁ

60

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DTACK Timing

ÁÁÁÁÁ

DAKdly

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACK low from Sclk C4 rising edge

ÁÁÁ

ÁÁÁÁ

10

ÁÁÁ

18

ÁÁÁ

ns

ÁÁÁÁÁ

DAKdlya

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACK high from CEN high (Async)

ÁÁÁ

ÁÁÁÁ

11

ÁÁÁ

20

ÁÁÁ

ns

ÁÁÁÁÁ

DAKdlys

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACK high from C4 end rising edge (Sync)

ÁÁÁ

ÁÁÁÁ

11

ÁÁÁ

20

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port External Clock

ÁÁÁÁÁ

tgpirtx

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

GPI to Rx/Tx clock out

ÁÁÁ

ÁÁÁÁ

32

ÁÁÁ

50

ÁÁÁ

ns

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD setup to I/OP rising edge 1X mode

ÁÁÁ

20

ÁÁÁÁ

2

ÁÁÁ

ns

ÁÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/OP falling edge to TxD out 1X mode

ÁÁÁ

ÁÁÁÁ

32

ÁÁÁ

60

ÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Gout Timing

ÁÁÁÁÁ

GPOtdd

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

GPO valid after write to GPOR

ÁÁÁ

ÁÁÁÁ

100

ÁÁÁ

ns

NOTES:

1. T iming is illustrated and referenced with respect to W–RN and CEN inputs. Internal read and write activities are controlled by the Sclk as it

generates the several “C” timing as shown in the timing diagrams.

2. The minimum time before the rising edge of the next C2 time to stop the next bus cycle. CEN must return high after midpoint of C4 time and

before the C2 time of the next cycle.

3. Delay is from CEN high in Async mode to IRQN inactive, from end of C4 to IRQN inactive in Sync mode.

4. The minimum frequency values are not tested, but are guaranteed by design.

5. 1MHz specification is for crystal operation.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 45

DC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (3.3 V)

VCC = 3.3 volts  10%; TA = –40 °C to +85°C; unless otherwise specified

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁ

LIMITS

ÁÁÁÁ

SYMBOL

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁ

TEST CONDITIONS

ÁÁÁÁ

MIN

ÁÁÁ

TYP1

ÁÁÁÁ

MAX

ÁÁÁÁ

UNIT

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

VIL

VIH

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input low voltage2

Input high voltage (except X1/CLK)

Input high voltage (X1/CLK)

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

VSS

0.8 * VCC

ÁÁÁ

ÁÁ

Á

ÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0.2 * VCC

VCC

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

V

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

VOL3

VOH

VOL3

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output low voltage4

Output high voltage (except OD outputs)

Open Drain low voltage

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

IOL = 3.2mA

IOH = –400mA

IOH = –100mA

IOL = 10.0mA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0.8VCC

0.9VCC

ÁÁÁ

ÁÁ

Á

ÁÁ

Á

ÁÁÁ

0.15

<0.25

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0.4

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

V

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

IIL

IIH

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input current low, I/O pins

Input current high, I/O pins

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

VIN = 0

VIN = VCC

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

–5

ÁÁÁ

ÁÁ

Á

ÁÁÁ

<0.1

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

+5

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

mA

ÁÁÁÁ

IL

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input leakage current

ÁÁÁÁÁÁÁÁ

VIN = 0 to VCC

ÁÁÁÁ

–5

ÁÁÁ

<1

ÁÁÁÁ

5

ÁÁÁÁ

mA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

IILCKX1

IIHCKX1

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1/CLK input low current

X1/CLK input high current

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

VIN=VSS,X2=Open

VIN=VCC, X2=Open

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

–300

ÁÁÁ

ÁÁ

Á

ÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

300

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

mA

ÁÁÁÁ

IOZH

IOZL

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output off current high, 3–state data bus

Output off current low, 3–state data bus

ÁÁÁÁÁÁÁÁ

VIN = Vcc

VIN = 0

ÁÁÁÁ

–5

ÁÁÁ

<.1

ÁÁÁÁ

5

ÁÁÁÁ

mA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

IODL

IODH

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Open–drain output low current in off state

Open drain output high current in off state

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

VIN = 0

VIN = VCC

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

–5

ÁÁÁ

ÁÁ

Á

ÁÁÁ

<.1

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

5

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

mA

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ICC

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power supply current

Operating mode 33 MHz

Static Power down (No clocks, Open drains off,

inputs at Vss or Vcc)

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

TTL Input levels

CMOS input levels

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

ÁÁ

Á

ÁÁ

Á

ÁÁÁ

22

12

0.6

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

35

20

5

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

mA

NOTES:

1. Typical values are at +25 °C, typical supply voltage and typical processing parameters.

2. All voltage measurements are referenced to VSS. For testing, all inputs swing between 0.4 V and 2.4 V with a transition time of 10 ns

maximum. For X1/CLK this swing is between 0.2V and 2.88V. all time measurements are referenced at input voltages of VIL and VIH as

appropriate.

3. Test conditions for itnerrupt and I/O outputs: CL = 50 pF. Test conditions for the rest of the outputs: CL = 60 pF.

4. Simultaneous switching more than 6 I/O port pins from 5 volts to 0 volts at full capacitive load may ground bounce on the output pins up to

0.95 volts.

5. All RX, TX, Brg Timer, I/O pins operating at 16 MHz. Sclk at 35 MHz and VCC at 5.6 volts. A worst–case environment.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 46

AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (3.3 V)

VCC = 3.3 volts  10%; TA = –40 °C to +85°C; unless otherwise specified

ÁÁÁÁ

SYMBOL

ÁÁÁÁ

FIGURE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁÁ

LIMITS

ÁÁÁÁ

UNIT

ÁÁÁÁ

SYMBOL

ÁÁÁÁ

FIGURE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁ

MIN

ÁÁÁÁ

TYP

ÁÁÁ

MAX

ÁÁÁÁ

UNIT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset Timing

ÁÁÁÁ

tRES1

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RESET pulse width

ÁÁÁÁ

10

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

Sclk

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bus Timing

ÁÁÁÁ

tAS

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0-A7 setup time before Sclk C3 rising edge

ÁÁÁÁ

22

ÁÁÁÁ

3

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tAH

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

A0-A7 hold time after Sclk C3 rising edge

ÁÁÁÁ

30

ÁÁÁÁ

12

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tCS

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN setup time before Sclk C1 high (ASYNC)

ÁÁÁÁ

8

ÁÁÁÁ

3

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t

CS

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN setup time before Sclk C2 high (SYNC)

ÁÁÁÁ

8

ÁÁÁÁ

3

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tCH

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN hold time after Sclk C3 high (SYNC)

ÁÁÁÁ

25

ÁÁÁÁ

1½ Sclk

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

t

CH

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

CEN hold time after Sclk C4 high (ASYNC)

ÁÁÁÁ

50

ÁÁÁÁ

1½ Sclk

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tSTP

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Cen high befoe next C2 to stop next cycle (Sync Mode)2

ÁÁÁÁ

30

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tRWS

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

W-Rn setup time before Sclk C2 rising edge

ÁÁÁÁ

7

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tRWH

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

W-Rn hold time after Sclk C3 rising edge

ÁÁÁÁ

25

ÁÁÁÁ

1½ Sclk

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tDD

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read cycle Data valid after Sclk C3 falling edge

ÁÁÁÁ

20

ÁÁÁ

40

ÁÁÁÁ

ns

ÁÁÁÁ

tDF

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read cycle data bus floating after CEN high (ASYNC)

ÁÁÁÁ

17

ÁÁÁ

30

ÁÁÁÁ

ns

ÁÁÁÁ

t

DF

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read cycle data bus floating after C4 end (SYNC)

ÁÁÁÁ

11

ÁÁÁ

20

ÁÁÁÁ

ns

ÁÁÁÁ

tDS

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write cycle data setup time before Sclk C4 rising edge

ÁÁÁÁ

25

ÁÁÁÁ

14

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tDH

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Write cycle data hold time after Sclk C4 rising edge

ÁÁÁÁ

25

ÁÁÁÁ

14

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tRWD

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High time between CEN low (ASYNC)

ÁÁÁÁ

15

ÁÁÁÁ

½ Sclk

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O Port Pin Timing

ÁÁÁÁ

tPS

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O input setup time before Sclk C3 falling edge (Read IPR)

ÁÁÁÁ

18

ÁÁÁÁ

4

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tPH

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O input hold time after Sclk C4 rising edge (Read IPR)

ÁÁÁÁ

12

ÁÁÁÁ

4

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tPD

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O output valid from:

Write Sclk C4 rising edge (write to I/OPIOR)

ÁÁÁÁ

50

ÁÁÁ

80

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Timing

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

tIR

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

IRQN from:

Internal interrupt source active bid

Software reset to IRQN inactive

Write IMR (set or clear IMR bit))3 to IRQN inactive

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

22

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

26

60

40

ÁÁÁ

Á

ÁÁÁ

43

90

60

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

Sclk

ns

ÁÁÁÁ

tDD

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt vector valid after C3 rising edge

ÁÁÁÁ

20

ÁÁÁ

30

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Tx / Rx Clock Timing, External

ÁÁÁÁ

tRX

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC high or low time

ÁÁÁÁ

25

ÁÁÁÁ

8

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

fRX4

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxC frequency (16 X)

(1 X)

ÁÁÁÁ

0

ÁÁÁÁ

ÁÁÁ

8

1

ÁÁÁÁ

MHz

ÁÁÁÁ

tTX

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC high or low time

ÁÁÁÁ

20

ÁÁÁÁ

7

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

fTX4

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC frequency (16 X)

(1 X)

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

0

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

Á

ÁÁÁ

8.0

1

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

MHz

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmitter Timing

ÁÁÁÁ

tTXD

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxD output delay from TxC low

ÁÁÁÁ

50

ÁÁÁ

90

ÁÁÁÁ

ns

ÁÁÁÁ

tTCS

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

TxC output delay from TxD output data

ÁÁÁÁ

-15

ÁÁÁÁ

4

ÁÁÁ

15

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Timing

ÁÁÁÁ

tRXS

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data setup time to RxC high (data)

ÁÁÁÁ

25

ÁÁÁÁ

14

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tRXH

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data hold time from RxC high (data)

ÁÁÁÁ

25

ÁÁÁÁ

14

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

tsSTRT

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD data low time to for receiving a valid Start Bit

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

17

32

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

ÁÁÁ

Á

ÁÁÁ

ÁÁÁÁ

Á

ÁÁ

Á

ÁÁÁÁ

bit time

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sclk Timing

ÁÁÁÁ

tSCLKL

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Min low time at Vil (0.8V)

ÁÁÁÁ

15

ÁÁÁÁ

10

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

tSCLKH

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Min high time at Vih (2.0V)

ÁÁÁÁ

15

ÁÁÁÁ

10

ÁÁÁ

ÁÁÁÁ

ns

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 47

AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (3.3 V) (Continued)

ÁÁÁÁ

SYMBOL

ÁÁÁÁ

FIGURE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁÁ

LIMITS

ÁÁÁÁ

UNIT

ÁÁÁÁ

SYMBOL

ÁÁÁÁ

FIGURE

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁ

MIN

ÁÁÁÁ

TYP

ÁÁÁ

MAX

ÁÁÁÁ

UNIT

ÁÁÁÁ

Fsclk

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sclk frequency

ÁÁÁÁ

0.1

ÁÁÁÁ

ÁÁÁ

20

ÁÁÁÁ

MHz

ÁÁÁÁ

T/RFsclk

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Sclk rise/fall time (0.8 to 2.0Volts)

ÁÁÁÁ

ÁÁÁ

5

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1 / X2 Communication Crystal Clock

ÁÁÁÁ

Fx15

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1 clock frequency

ÁÁÁÁ

1

ÁÁÁÁ

3.6864

ÁÁÁ

4

ÁÁÁÁ

MHz

ÁÁÁÁ

X1 L / H

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1 Low / High time

ÁÁÁÁ

80

ÁÁÁÁ

52

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

T/RFx1

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

X1 Rise / Fall time

ÁÁÁÁ

ÁÁÁ

10

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Counter/Timer Baud Rate Clock (External Clock Input)

ÁÁÁÁ

FC/T4

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Clock frequency

ÁÁÁÁ

0

ÁÁÁÁ

ÁÁÁ

8

ÁÁÁÁ

MHz

ÁÁÁÁ

TC/TLH

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

C/T high and low time

ÁÁÁÁ

20

ÁÁÁÁ

15

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

TC/TO

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Delay C/T clock external to output pin

ÁÁÁÁ

48

ÁÁÁ

110

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACKN Timing

ÁÁÁÁ

DAKDLY

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACK low from Sclk C4 rising edge

ÁÁÁÁ

18

ÁÁÁ

30

ÁÁÁÁ

ns

ÁÁÁÁ

DAKDLYA

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACK high from CEN high (ASYNC)

ÁÁÁÁ

18

ÁÁÁ

30

ÁÁÁÁ

ns

ÁÁÁÁ

DAKDLY

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

DACK high from C4 end rising edge (SYNC)

ÁÁÁÁ

20

ÁÁÁ

30

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/O PORT External Clock

ÁÁÁÁ

TGPIRTX

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

GPI to Rx/Tx clock out

ÁÁÁÁ

50

ÁÁÁ

80

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

RxD setup to I/OP rising edge 1X mode

ÁÁÁÁ

20

ÁÁÁÁ

2

ÁÁÁ

ÁÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

I/OP falling edge to TxD out 1X mode

ÁÁÁÁ

32

ÁÁÁ

70

ÁÁÁÁ

ns

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

GOUT Timing

ÁÁÁÁ

GPOTDD

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

GPO valid after write to GPOR

ÁÁÁÁ

100

ÁÁÁ

ÁÁÁÁ

ns

NOTES:

1. T iming is illustrated and referenced with respect to W–RN and CEN inputs. Internal read and write activities are controlled by the Sclk as it

generates the several “C” timing as shown in the timing diagrams.

2. The minimum time before the rising edge of the next C2 time to stop the next bus cycle. CEN must return high after midpoint of C4 time and

before the C2 time of the next cycle.

3. Delay is from CEN high in Async mode to IRQN inactive, from end of C4 to IRQN inactive in Sync mode.

4. The minimum frequency values are not tested, but are guaranteed by design.

5. 1MHz specification is for crystal operation.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 48

SCLK

CEN

W_RN

ADDRESS

DATA

DACKN

INVALID VALID

C1 C2 C3 C4

tCS

INVALID

INVALID VALID INVALID

tRWS tAS tAH

tDS DAKDLY

tDH

C4 DAKDLY

CEN HIGH

tCH

tRWD

tRWH

SD00194

Figure 2. Basic Write Cycle, ASYNC

SCLK

CEN

W_RN

ADDRESS

DATA

DACKN

INVALID VALID

C1 C2 C3 C4

tCS

INVALID

INVALID VALID INVALID

tRWS tAS tAH tDS

DAKDLY

tDH

C4 DAKDLY

C4 END

tCH tSTP

tRWH

SD00195

C1 C2

Figure 3. Basic Write Cycle, SYNC

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 49

tRWD

SCLK

CEN

W_RN

ADDRESS

DATA

DACKN

INVALID VALID

C1 C2 C3 C4

tCS

INVALID

INVALID VALID INVALID

tRWS tAS tAH

tDD

DAKDLY

tDF

C4 DAKDLY

CEN

tCH

tRWH

DATA=00

SD00196

Figure 4. Basic Read Cycle, ASYNC

tCH tSTP

SCLK

CEN

W_RN

ADDRESS

DATA

DACKN

INVALID VALID

C1 C2 C3 C4

tCS

INVALID

INVALID VALID INVALID

tRWS tAS tAH

tDD

DAKDLY

tDF

C4 DAKDLY

C4 END

tRWH

DATA=00

SD00197

C1 C2

Figure 5. Basic Read Cycle, SYNC

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 50

SCLK

IACKN

CEN

W_RN

ADDRESS

DATA

DACKN

INVALID

DON’T CARE

C1 C2 C3 C4

VALID

tCS tRWS

tAS tAH

tDD

DAKDLY

C4

DAKDLY

CEN

HIGH

tDF

INVALID

INVALIDINVALID

DON’T CARE

NOTE: CEN must not be active during an IACKN cycle. If CEN is active, IACKN will be ignored

and a normal read or write will be executed according to W_RN. In the synchronous

mode, extended IACKN signal will start another IACKN. (This may not be desired, but

is allowed.)

SD00525

Figure 6. Basic IACKN Cycle, ASYNC/SYNC

C1 and C2 should be chosen according to the

crystal manufacturer’s specification.

C1 and C2 values will include any parasitic

capacitance of the wiring.

fX1

+5V

1K required for

TTL gate.

X1

X2

C1 = C2 = 24pF FOR CL = 20PF

X1

X2

3.6864MHz

3pF

4pF

50 KOHMs

TO

150 KOHMs

28C198

NOTES:

C1 and C2 should be based on manufacturer’s specification.

X1 and X2 parasitic capacitance IS 1-2pF AND 3-5pF, respectively.

GAIN: at 4MHz 8 to 14db; at 8MHz 2 to 6db

PHASE: at 4MHz 272° to 276°; at 8MHz 272° to 276°

The above figures for 5V operation. Operation at 3V is to be determined.

TYPICAL CRYSTAL SPECIFICATION

FREQUENCY : 2 – 4MHZ

LOAD CAPACITANCE (CL): 12 – 32pF

TYPE OF OPERATION: PARALLEL RESONANT, FUNDAMENTAL MODE

NC

C1

C2

MUX To

remainder

of circuit

÷ 2

38.4kHz CLOCK

BRG

TO I/O CHANGE-OF-STATE DETECTORS

22 STANDARD

BAUD

RATES

X1 L/H

T/R fX1

SD00198

Figure 7. X1/X2 Communication Crystal Clock

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 51

fSCLK

tSCLKL

T/RFSCLK

tSCLKH

SD00199

Figure 8. SCLK Timing

FC/T

TC/TL

T/RFSCLK

TC/TH

TC/TO

SD00200

Figure 9. Counter/Timer Baud Rate Clock, External

Frx

Trx

T/RF

TC/TH

TC/TO

Ttx

Ftx

SD00201

Figure 10. Tx/Rx Clock Timing, External

1X DATA CLOCK

tRXS

tRXH

tTXD

RxD

TxD

SD00202

Figure 11. T ransmitter and Receiver Timing

Note: CEN must not be active during an IACKN cycle. If CEN is

active IACKN will be ignored and a normal read or write will be

executed according to W_RN.

In the synchronous mode extended IACKN signal cycle will start

another IACKN. (This may not be desired but is allowed)

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 52

INDEX

Numbers

1x and 16x modes, Receiver, 9

1x and 16x modes, T ransmitter, 9

A

Address Recognition Character Register, 25

ARCR, 25

Asynchronous bus cycle, 6

B

Baud Rate Generator , 7

BCRA, 25

BCRBRK, 24

BCRCOS, 24

BCRx, 24

Bidding Control Register – Address, 25

Bidding Control Register – Break Change, 24

Bidding Control Register – Change of State, 24

Bidding Control Register – Xon, 24

Block diagram, 6

Break, transmission of, 9

BRG Timer Control Register, 26

BRG Timer Reload Registers, Lower, 26

BRG Timer Reload Registers, Upper, 26

BRGCTCR , 26

BRGTRL, 26

BRGTRU, 26

C

CEN, 6

Channel Blocks, 7

Channel Status Register, 22

Character Recognition, 7

CharacterStripping, 11

CIR, 27

Clock Register, Rx & Tx, 20

Command Register , 21

COMMAND REGISTER TABLE, 22

CR , 21

Crystal oscillator, 7

Current Interrupt Register, 27

D

Description, 2

DESCRIPTION, over all, 6

F

Framing error, 10

G

GCCR, 17

General Purpose Output Clk Register, 29

General Purpose Output Data Register, 29

General Purpose Output Register, 29

General Purpose Output Select Register, 29

General Purpose Pins, 11

GIBCR, 28

GICR, 27

GITR, 28

Global Configuration Control Register (GCCR), 17

Global Interrupting Byte Count Register, 28

Global Interrupting Channel Register, 27

Global Registers, 8, 11

Global RxFIFO Register, 28

Global TxFIFO Register, 28

GPOC , 29

GPOD, 29

GPOR, 29

GPOSR, 29

GRxFIFO, 28

GTxFIFO, 28

H

Host Interface, 6

Host interface, 6

I

I/O Port Configuration Register, 29

I/O Port Interrupt and Output Register, 28

I/O ports, 10

I/OPCR, 10, 29

I/OPIOR, 28

IACKN, 8

IACKNCycle, 12

ICR, 27

IMR, 8, 24

INDEX, 51

Input Port Register, 28

Interrupt Arbitration, 11

Interrupt Control, 8

Interrupt Mask Register, 24

Interrupt priorities, Setting, 12

Interrupt sources, Enabling, 12

Interrupt Status Register, 23

Interrupt Vector Register, 27

Interrupts, Xon/Xoff, 16

IOPIOR register, 11

IPR , 28

ISR, 8, 23

IVR, 27 M

Minor Modes, 14

Mode control, Xon/Xoff, 16

Mode Register 0, 18

Mode Register 1, 18

Mode Register 2, 19

Mode Registers, Initialization, 17

Modes of Operation, 13

MR0 , 18

MR1, 18

MR2, 19

Multidrop mode, 11

O

Overrun error, 10

P

Parity error, 10

Pin Description, 5

Pinout, 4

Polling, 12R

Receiver, 9

Receiver FIFO, 10, 24

Receiver Status Bits, 9

REGISTER DESCRIPTIONS, 17

Register Map, 30

Register Map, Control, 30, 31

Register Map, Data, 31, 36

Reset Conditons, 40

RxCSR , 20

RxFIFO, 24

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 53

S

Sclk, 6

SR , 22

Synchronous bus cycle, 6

System Clock, 7

T

T iming Circuits, 6

T ransmitter, 8

T ransmitter FIFO, 9, 24

Tx, Status Bits , 8

TxCSR , 20

TxEMT, 8

TxFIFO, 24

TxRDY, 8

U

UCIR, 27

Update CIR, 12, 27

W

W ake Up Mode, 14

W ake up mode, 11

W ake Up modes, 14

W ake up. Default, 14

W atch–dog Timer , 14

W atch–dog Timer Enable Register, 26

WDTRCR, 26

X

XISR, 26

Xoff Character Register, 25

XoffCR, 25

Xon /Xoff characters , 15

Xon Character Register, 25

Xon–Xof f Interrupt Status Register, 26

Xon/Xof f modes, 15

Xon/Xof f Operation, 15

XonCR , 25

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 54

PLCC84: plastic leaded chip carrier; 84 leads SOT189-2

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 55

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

2006 Aug 10 56

REVISION HISTORY

Rev Date Description

_6 20060810 Product data sheet (9397 750 14852). Supersedes data of 1999 Jan 14 (9397 750 04754).

Modifications:

•Ordering information table: changed DWG # SOT189–3 to SOT189–2

•Package outline drawing SOT189–3 replaced with SOT189–2

_5 19990114 Product specification (9397 750 04754). ECN #853–2047 20654.

Supersedes data of 1998 Nov 04.

_4 19981104 Preliminary specification (9397 750 04754). Supersedes data of 1998 Sep 21.

_3 19980921 Preliminary specification (9397 750 04366).

Replaces data sheet SC28C198_SC28L198_2 of of 1998 Feb 06.

Philips Semiconductors Product data sheet

SC28L198Octal UART for 3.3 V and 5 V supply voltage

yyyy mmm dd 57

This document contains data from the preliminary specification.

Development

Preliminary [short] data sheet

Data sheet status

Document status[1][2]

Objective [short] data sheet

Product status[3] Definition

This document contains data from the objective specification for product development.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this data sheet was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.semiconductors.philips.com.

Qualification

Product [short] data sheet Production This document contains the product specification.

Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Philips Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local Philips

Semiconductors sales of fice. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, Philips Semiconductors does not give any representations

or warranties, expressed or implied, as to the accuracy or completeness of

such information and shall have no liability for the consequences of use of

such information.

Right to make changes — Philips Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

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authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a Philips Semiconductors product can reasonably be

expected to result in personal injury, death or severe property or

environmental damage. Philips Semiconductors accepts no liability for

inclusion and/or use of Philips Semiconductors products in such equipment

or applications and therefore such inclusion and/or use is at the customer’s

own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Philips Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause

permanent damage to the device. Limiting values are stress ratings only and

operation of the device at these or any other conditions above those given in

the Characteristics sections of this document is not implied. Exposure to

limiting values for extended periods may affect device reliability.

Terms and conditions of sale — Philips Semiconductors products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.semiconductors.philips.com/profile/terms,

including those pertaining to warranty, intellectual property rights

infringement and limitation of liability, unless explicitly otherwise agreed to in

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Notice: All referenced brands, product names, service names and

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Date of release: 20060810

Document identifier: SC28L198_6

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