DS36277TMX/NOPB - NATIONAL SEMICONDUCTOR

DS36277

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SNLS086E –JULY 1998–REVISED APRIL 2013

Dominant Mode Multipoint Transceiver

Check for Samples: DS36277

1FEATURES DESCRIPTION

The DS36277 Dominant Mode Multipoint Transceiver

2• FAILSAFE Receiver, RO = HIGH for: is designed for use on bi-directional differential

– OPEN Inputs busses. It is optimal for use on Interfaces that utilize

– Terminated Inputs Society of Automotive Engineers (SAE) J1708

Electrical Standard.

– SHORTED Inputs

• Optimal for Use in SAE J1708 Interfaces The device is similar to standard TIA/EIA-485

transceivers, but differs in enabling scheme. The

• Compatible with Popular Interface Standards: Driver's Input is normally externally tied LOW, thus

– TIA/EIA-485 and TIA/EIA-422-A providing only two states: Active (LOW), or Disabled

– CCITT Recommendation V.11 (OFF). When the driver is active, the dominant mode

is LOW, conversely, when the driver is disabled, the

• Bi-Directional Transceiver bus is pulled HIGH by external bias resistors.

– Designed for Multipoint Transmission The receiver provides a FAILSAFE feature that

• Wide Bus Common Mode Range ensures a known output state when the Interface is in

– (−7V to +12V) the following conditions: Floating Line, Idle Line (no

• Available in PDIP and SOIC Packages active drivers), and Line Fault Conditions (open or

short). The receiver output is HIGH for the following

conditions: Open Inputs, Terminated Inputs (50Ω), or

Shorted Inputs. FAILSAFE is a highly desirable

feature when the transceivers are used with

Asynchronous Controllers such as UARTs.

Connection and Logic Diagram

See Package Number D (R-PDSO-G8)

P (R-PDIP-T8)

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS36277

SNLS086E –JULY 1998–REVISED APRIL 2013

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Truth Table

Driver

Inputs Outputs

DE DI DO/RI DO /RI

L L L H

L H H L

H X Z Z

Receiver

Inputs Output

RE DO/RI–DO /RI RO

L≥0 mV H

L≤ −500 mV L

L SHORTED H

L OPEN H

H X Z

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)

Value Unit

Supply Voltage (VCC) 7 V

Input Voltage (DE , RE , and DI) 5.5 V

Driver Output Voltage/Receiver Input Voltage −10V to +15 V

Receiver Output Voltage (RO) 5.5 V

Maximum Package Power Dissipation @ +25°C P Package

(derate 9.3 mW/°C above +25°C) 1168 mW

D Package

(derate 5.8 mW/°C above +25°C) 726 mW

Storage Temperature Range −65°C to +150 °C

Lead Temperature (Soldering 4 sec.) 260 °C

ESD Rating (HBM, 1.5 kΩ, 100 pF) 7.0 kV

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply

that the devices should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

Recommended Operating Conditions Min Max Units

Supply Voltage, VCC 4.75 5.25 V

Bus Voltage −7 +12 V

Operating Temperature (TA) DS36277T −40 +85 °C

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SNLS086E –JULY 1998–REVISED APRIL 2013

Electrical Characteristics(1)(2)

Over recommended Supply Voltage and Operating Temperature ranges, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

DRIVER CHARACTERISTICS

VOD Differential Output Voltage IO= 0 mA (No Load) 1.5 3.6 6 V

VoDO Output Voltage IO= 0 mA (Output to GND) 0 6 V

VoDO Output Voltage 0 6 V

VT1 Differential Output Voltage RL= 54Ω(485) (Figure 1) 1.3 2.2 5.0 V

(Termination Load) RL= 100Ω(422) 1.7 2.6 5.0 V

ΔVT1 Balance of VT1 RL= 54ΩSee(3) −0.2 0.2 V

|VT1 −VT1 |RL= 100Ω −0.2 0.2 V

VOS Driver Common Mode RL= 54Ω(Figure 1) 0 2.5 3.0 V

Output Voltage RL= 100Ω0 2.5 3.0 V

ΔVOS Balance of VOS RL= 54ΩSee(3) −0.2 0.2 V

|VOS −VOS |RL= 100Ω −0.2 0.2 V

VOH Output Voltage High IOH =−22 mA (Figure 2) 2.7 3.7 V

VOL Output Voltage Low IOL = +22 mA 1.3 2 V

IOSD Driver Short-Circuit VO= +12V (Figure 3) 92 290 mA

Output Current VO=−7V −187 −290 mA

RECEIVER CHARACTERISTICS

VTH Differential Input High VO= VOH, IO=−0.4 mA −0.150 0 V

Threshold Voltage(4) −7V ≤VCM ≤+12V

VTL Differential Input Low VO= VOL, IO= 8.0 mA −0.5 −0.230 V

Threshold Voltage(4) −7V ≤VCM ≤+12V

VHST Hysteresis(5) VCM = 0V 80 mV

IIN Line Input Current Other Input = 0V VI= +12V 0.5 1.5 mA

(VCC = 4.75V, 5.25V, 0V) DE = VIH(6) VI=−7V −0.5 −1.5 mA

IOSR Short Circuit Current VO= 0V RO −15 −32 −85 mA

IOZ TRI-STATE Leakage Current VO= 0.4 to 2.4V −20 1.4 +20 μA

VOH Output High Voltage VID = 0V, IOH =−0.4 mA 2.3 3.7 V

(Figure 12)VID = OPEN, IOH =−0.4 mA 2.3 3.7 V

VOL Output Low Voltage VID =−0.5V, IOL = +8 mA 0.3 0.7 V

(Figure 12)VID =−0.5V, IOL = +16 mA 0.3 0.8 V

RIN Input Resistance 10 20 kΩ

DEVICE CHARACTERISTICS

VIH High Level Input Voltage DE , 2.0 VCC V

RE ,

VIL Low Level Input Voltage GND 0.8 V

IIH High Level Input Current VIH = 2.4V 20 μA

IIL Low Level Input Current VIL = 0.4V −100 μA

VCL Input Clamp Voltage ICL =−18 mA −0.7 −1.5 V

ICC Output Low Voltage DE = 0V, RE = 0V, DI = 0V 39 60 mA

Supply Current

ICCR DE = 3V, RE = 0V, DI = 0V 24 50 mA

(No Load)

ICCD DE = 0V, RE = 3V, DI = 0V 40 75 mA

ICCX DE = 3V, RE = 3V, DI = 0V 27 45 mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground

unless otherwise specified.

(2) All typicals are given for VCC = 5.0V and TA= +25°C.

(3) Δ|VT1| and Δ|VOS| are changes in magnitude of VT1 and VOS, respectively, that occur when the input changes state.

(4) Threshold parameter limits specified as an algebraic value rather than by magnitude.

(5) Hysteresis defined as VHST = VTH −VTL.

(6) IIN includes the receiver input current and driver TRI-STATE leakage current.

Product Folder Links: DS36277

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SNLS086E –JULY 1998–REVISED APRIL 2013

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Switching Characteristics(1)

Over recommended Supply Voltage and Operating Temperature ranges, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

DRIVER CHARACTERISTICS

tPLHD Diff. Prop. Delay Low to High RL= 54Ω8 17 60 ns

tPHLD Diff. Prop. Delay High to Low CL= 50 pF 8 19 60 ns

tSKD Diff. Skew (|tPLHD–tPHLD|) CD= 50 pF 2 10 ns

trDiff. Rise Time (Figure 4 and Figure 5) 11 60 ns

tfDiff. Fall Time 11 60 ns

tPLH Prop. Delay Low to High RL= 27Ω, CL= 15 pF 22 85 ns

(Figure 6 and Figure 7)

tPHL Prop. Delay High to Low 25 85 ns

tPZH Enable Time Z to High RL= 110Ω25 60 ns

CL= 50 pF

tPZL Enable Time Z to Low 30 60 ns

(Figure 8 –Figure 11 )

tPHZ Disable Time High to Z 16 60 ns

tPLZ Disable Time Low to Z 11 60 ns

RECEIVER CHARACTERISTICS

tPLH Prop. Delay Low to High VID =−1.5V to +1.5V 15 37 90 ns

CL= 15 pF

tPHL Prop. Delay High to Low 15 43 90 ns

(Figure 13 and Figure 14)

tSK Skew (|tPLH–tPHL|) 6 15 ns

tPZH Enable Time Z to High CL= 15 pF 12 60 ns

(Figure 15 and Figure 16)

tPZL Enable Time Z to Low 28 60 ns

tPHZ Disable Time High to Z 20 60 ns

tPLZ Disable Time Low to Z 10 60 ns

(1) All typicals are given for VCC = 5.0V and TA= +25°C.

Product Folder Links: DS36277

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SNLS086E –JULY 1998–REVISED APRIL 2013

PARAMETER MEASUREMENT INFORMATION

Figure 1. Driver VT1 and VOS Test Circuit

Figure 2. Driver VOH and VOL Test Circuit

Figure 3. Driver Short Circuit Test Circuit

CLincludes probe and stray capacitance

The input pulse is supplied by a generator having the following characteristics: f=1.0 MHz, 50% duty cycle, Trand

tf<6.0 ns, Zo=50Ω

Figure 4. Driver Differential Propagation Delay and Transition Time Test Circuit

Product Folder Links: DS36277

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SNLS086E –JULY 1998–REVISED APRIL 2013

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Figure 5. Driver Differential Propagation Delays and Transition Times

CLincludes probe and stray capacitance

The input pulse is supplied by a generator having the following characteristics: f=1.0 MHz, 50% duty cycle, Trand

tf<6.0 ns, Zo=50Ω

Figure 6. Driver Propagation Delay Test Circuit

Figure 7. Driver Propagation Delays

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SNLS086E –JULY 1998–REVISED APRIL 2013

S1 to DO for DI = 3V

S1 to DO for DI = 0V

CLincludes probe and stray capacitance

The input pulse is supplied by a generator having the following characteristics: f=1.0 MHz, 50% duty cycle, Trand

tf<6.0 ns, Zo=50Ω

Figure 8. Driver TRl-STATE Test Circuit (tPZH, tPHZ)

Figure 9. Driver TRI-STATE Delays (tPZH, tPHZ)

S1 to DO for DI = 0V

S1 to DO for DI = 3V

CLincludes probe and stray capacitance

The input pulse is supplied by a generator having the following characteristics: f=1.0 MHz, 50% duty cycle, Trand

tf<6.0 ns, Zo=50Ω

Figure 10. Driver TRI-STATE Test Circuit (tPZL, tPLZ)

Figure 11. Driver TRl-STATE Delays (tPZL, tPLZ)

Product Folder Links: DS36277

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SNLS086E –JULY 1998–REVISED APRIL 2013

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Figure 12. Receiver VOH and VOL

CL includes probe and stray capacitance

The input pulse is supplied by a generator having the following characteristics: f=1.0 MHz, 50% duty cycle, Trand

tf<6.0 ns, Zo=50Ω

Figure 13. Receiver Propagation Delay Test Circuit

Figure 14. Receiver Propagation Delays

CLincludes probe and stray capacitance

The input pulse is supplied by a generator having the following characteristics: f=1.0 MHz, 50% duty cycle, Trand

tf<6.0 ns, Zo=50Ω

Diodes are 1N916 or equivalent.

Figure 15. Receiver TRI-STATE Delay Test Circuit

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SNLS086E –JULY 1998–REVISED APRIL 2013

S1 1.5V

S2 OPEN

S3 CLOSED

S1 1.5V

S2 CLOSED

S3 CLOSED

S1 −1.5V

S2 CLOSED

S3 OPEN

S1 −1.5V

S2 CLOSED

S3 CLOSED

Figure 16. Receiver Enable and Disable Timing

Product Folder Links: DS36277

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SNLS086E –JULY 1998–REVISED APRIL 2013

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Typical Performance Characteristics

Differential Output Voltage Differential Output Voltage

vs Output Current vs Output Current

Figure 17. Figure 18.

Driver VOH Driver VOH

vs vs

IOH IOH

vs vs

VCC Temperature

Figure 19. Figure 20.

Driver VOL Driver VOL

vs vs

IOL IOL

vs vs

VCC Temperature

Figure 21. Figure 22.

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SNLS086E –JULY 1998–REVISED APRIL 2013

Typical Performance Characteristics (continued)

Receiver VOH Receiver VOH

vs vs

IOH IOH

vs vs

VCC Temperature

Figure 23. Figure 24.

Receiver VOL Receiver VOL

vs vs

IOL IOL

vs vs

VCC Temperature

Figure 25. Figure 26.

Supply Current Supply Current

vs vs

Supply Voltage Temperature

Figure 27. Figure 28.

Product Folder Links: DS36277

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SNLS086E –JULY 1998–REVISED APRIL 2013

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Typical Performance Characteristics (continued)

Voltage Output

Voltage Input (Hysteresis)

Figure 29.

TYPICAL APPLICATIONS INFORMATION

Figure 30. SAE J1708 Node with External Bias Resistors and Filters

Product Folder Links: DS36277

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SNLS086E –JULY 1998–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision D (April 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 12

Product Folder Links: DS36277

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DS36277TMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS362

77TM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DS36277TMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS36277TMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

Pack Materials-Page 2

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PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

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EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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