DSPIC30F5015-30I/PT - Microchip Technology, Inc.

dsPIC30F5015/5016

Data Sheet

High-Performance, 16-Bit

Digital Signal Controllers

Information contained in this publication regarding device

applications a nd the like is p ro vid ed only f or yo ur c o n ve nience

and may be supers eded by updates. It is y our res po nsibilit y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accur on,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MX DEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrit y of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violat ion of the Digital Millennium Copyright Act. If suc h a c t s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

High-Performance Modified RISC CPU:

• Modified Harvard architecture

• C compiler optimized in struction set architecture

with flexible Addressing modes

• 83 base instructions

• 24-bit wide instructions, 16-bit wide data path

• 66 Kbytes on -chip Flash p rogr am spac e

(Instruction words)

• 2 Kbytes of on-chip data RAM

• 1 Kbyte of nonvolatile data EEPROM

• Up to 30 MIPS operation:

- DC to 40 MHz external clock input

- 4 MHz-10 MHz oscillator input with

PLL active (4x, 8x, 16x)

• 36 interrupt sources:

- 5 external interrupt sources

- 8 user-selectable priority levels for each

inter rupt so urc e

- 4 processo r trap sources

• 16 x 16-bit working register array

DSP Engine Features:

• Dual data fetch

• Accumulator write back for DSP operations

• Modulo and Bit-Reversed Addressing modes

• Two 40-bit wide accumulators with optional

saturati on log ic

• 17-bit x 17-bit si ngl e-c ycle hard w are frac tio nal /

integer multiplier

• All DSP instructions single cycle

• ±16-bit single-cycle shift

Peripheral Feat ures:

• High-current sink/source I/O pins: 25 mA/25 mA

•Timer module with programmable prescaler:

- Five 16-bit timers/counters; optionally pair

16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions

• 3-wire SPI modules (supports 4 Frame modes)

•I

2C™ module supports Multi-Master/Slave mode

and 7-bit/10-bit addressing

• 1 UART modules with FIFO Buffers

• 1 CAN modules, 2.0B compliant

Motor Control PWM Module Features:

• 8 PWM output channels

- Complement ary or Indepe ndent Outpu t

modes

- Edge and Center-Aligned modes

• 4 duty cycle generators

• Dedicated time base

• Programmable output polarity

• Dead-Time control for Complementary mode

• Manual output control

• Trigger for A/D conversions

Quadrature Encoder Interface Module

Features:

• Phase A, Phase B and Index Puls e input

• 16-bit up/down position counter

• Count direction status

• Position Measurement (x2 and x4) mode

• Programmable digital noise filters on inputs

• Alternate 16-bit Timer/Counter mode

• Interrupt on position counter roll over/underflow

Note: This data sheet summarizes features of this

group o f ds PIC 30 F dev ic es a nd is n ot in tended to b e

a complete reference source. For more information

on the CPU, peripherals, register descriptions and

general device functionality, refer to the “dsPIC30F

Family Reference Manual” (DS70046). For more

information on the device instruction set and pro-

gramming, refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

dsPIC30F5015/5016

dsPIC30F5015/5016 Enhanced Flash

16-bit Digital Signal Contr oller

dsPIC30F5015/5016

Analog Features:

• 10-bit Analog-to-Digital Converter (ADC) with

4 S/H Inputs:

- 1 Msps conversion rate

- 16 input channels

- Conversion available during Sleep and Idle

• Programmable Brown-out Reset

Special Microcontroller Features:

• Enhanced Flash program memory:

- 10,000 erase/write cycle (min.) for

industrial temperature range, 100K (typical)

• Data EEPROM memory:

- 100,000 erase/write cycle (min.) for

industrial temperature range, 1M (typical)

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWR T )

and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with on-chip,

low-power RC oscillator for reliable operation

• Fail-Safe Clock Monitor operation detects clock

failure and switches to on-chip, low-power RC

oscillator

• Programmable code protection

• In-Circuit Serial Programming™ (ICSP™)

programming capabil ity

• Selectable Power Ma nag em ent mo des :

- Sleep, Idle and Alternate Clock modes

CMOS Technology:

• Low-power, high-speed Flash technology

• Wide operating voltage range (2.5V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption

dsPIC30F Motor Control and Powe r Conversion Family*

Device Pins Program

Mem. Bytes/

Instructions

SRAM

Bytes EEPROM

Bytes Timer

16-bit Input

Cap

Output

Comp/Std

PWM

Motor

Control

PWM

A/D 10 -bit

1 Ms ps Quad

Enc

UART

SPI

I2CTM

CAN

dsPIC30F2010 28 12K/4K 512 1024 3 4 2 6 ch 6 ch Yes 1 1 1 -

dsPIC30F3010 28 24K/8K 1024 1024 5 4 2 6 ch 6 ch Yes 1 1 1 -

dsPIC30F4012 28 48K/16K 2048 1024 5 4 2 6 ch 6 ch Yes 1 1 1 1

dsPIC30F3011 40/44 24K/8K 1024 1024 5 4 4 6 ch 9 ch Yes 2 1 1 -

dsPIC30F4011 40/44 48K/16K 2048 1024 5 4 4 6 ch 9 ch Yes 2 1 1 1

dsPIC30F5015 64 66K/22K 2048 1024 5 4 4 8 ch 16 ch Yes 1 2 1 1

dsPIC30F5016 80 66K/22K 2048 1024 5 4 4 8 ch 16 ch Yes 1 2 1 1

dsPIC30F6010 80 144K/48K 8192 4096 5 8 8 8 ch 16 ch Yes 2 2 1 2

*This table provides a summary of the dsPIC30F5015/5016 peripheral features. Other available devices in the dsPI C30F Motor

Control and Power Conversion Family are shown for feature comparison.

dsPIC30F5015/5016

Pin Diagram

dsPIC30F5016

RD12

OC4/RD3

OC3/RD2

EMUD2/OC2/RD1

PWM2L/RE2

PWM1H/RE1

PWM1L/RE0

RG0

RG1

C1TX/RF1

C1RX/RF0

PWM3L/RE4

PWM2H/RE3

CN16/UPDN/RD7

CN14/RD5

EMUC2/OC1/RD0

IC4/RD11

IC2/RD9

IC1/RD8

INT4/RA15

IC3/RD10

INT3/RA14

VSS

OSC1/CLKI

VDD

SCL/RG2

U1RX/RF2

U1TX/RF3

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

VREF+/RA10

VREF-/RA9

AVDD

AVSS

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

VDD

CN17/RF4

CN21/RD15

CN18/RF5

AN6/OCFA/RB6

AN7/RB7

PWM4H/RE7

T2CK/RC1

T4CK/RC3

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

SS2/CN11/RG9

AN4/QEA/CN6/RB4

AN3/INDX/CN5/RB3

AN2/SS1/CN4/RB2

PGC/EMUC/AN1/CN3/RB1

PGD/EMUD/AN0/CN2/RB0

VSS

VDD

PWM3H/RE5

PWM4L/RE6

FLTB/INT2/RE9

FLTA/INT1/RE8

AN12/RB12

AN13/RB13

AN14/RB14

AN15/CN12/RB15

VDD

VSS

CN13/RD4

CN19/RD13

SDA/RG3

SDI1/RF7

EMUD3/SDO1/RF8

AN5/QEB/CN7/RB5

VSS

OSC2/CLKO/RC15

CN15/RD6

EMUC3/SCK1/INT0/RF6

CN20/ R D14

80- Pin TQFP

dsPIC30F5015/5016

Pin Diagram

dsPIC30F5015

64- Pin TQFP

13 36

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/T4CK/CN1/RC13

EMUC2/OC1/RD0

IC4/INT4/RD11

IC2/FLTB/INT2/RD9

IC1/FLTA/INT1/RD8

VSS

OSC2/CLKO/RC15

OSC1/CLKI

VDD

SCL/RG2

EMUC3/SCK1/INT0/RF6

U1RX/SDI1/RF2

EMUD3/U1TX/SDO1/RF3

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS

VDD

AN3/INDX/CN5/RB3

AN2/SS1/CN4/RB2

AN1/VREF-/CN3/RB1

AN0/VREF+/CN2/RB0

UPDN/CN16/RD7

PWM3L/RE4

PWM2H/RE3

PWM2L/RE2

VSS

PWM1L/RE0

C1TX/RF1

PWM1H/RE1

EMUD2/OC2/RD1

OC3/RD2

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

AVDD

AVSS

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

VSS

VDD

AN12/RB12

AN13/RB13

AN14/RB14

AN15/CN12/RB15

CN18/RF5

CN17/RF4

SDA/RG3

SS2/CN11/RG9

AN5/QEB/CN7/RB5

AN4/QEA/CN6/RB4

IC3/INT3/RD10

VDD

C1RX/RF0

OC4/RD3

CN15/RD6

IC6/CN14/RD5

IC5/CN13/RD4

© 2006 Microchip Technology Inc. DS70149B-page 5
dsPIC30F5015/5016
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 CPU Architecture Overview........................................................................................................................................................ 15
3.0 Memory O rganization................................................................................................................................................................. 23
4.0 Address Generato r Units............................................................................................................................................................ 35
5.0 Interrupts.................................................................................................................................................................................... 41
6.0 Flash Pro g ram Memory............................ ............................ ........................... ..................... ...................................................... 49
7.0 Data EEPR OM Mem o ry........... ........................... ........................... ..................... ....................................................................... 55
8.0 I/O Ports.............................. ............................ ........................... ................................................................................................ 59
9.0 Timer1 Module ........................................................................................................................................................................... 65
10.0 Timer2/3 Module ......... .. .. .. .... ..... .. .. .... .. .. .. .. ....... .. .. .... .. .. .. ....... .. .. .. .. .... .. ..... .. .... .. .. .. .. ....... ............................................................ 69
11.0 Timer4/5 Module  ............ .. .. ....... .. .. .. .... .. .. .. ....... .. .. .. .... .. .. ..... .... .. .. .. .. .... ..... .. .. .... .. .. .. .. ................................................................. 75
12.0 Input Capture Module ...................... .... .. .. .. ....... .... .. .. .... .. ....... .. .. .... .. .. ....... .. .... .. .. .... .. ....... .......................................................... 79
13.0 Output Compa re Module........................ ............................ ..................... ..................... .............................................................. 83
14.0 Quadrature Encoder Interface (QEI ) Module ............................................................................................................................. 87
15.0 Mot or Control PWM Module....................................................................................................................................................... 93
16.0 SP I Module............................................................................................................................................................................... 103
17.0 I2C Module............................................................................................................................................................................... 107
18.0 U nivers al Asynchr onous Receiver  Transmi tter (UART) Module .............................................................................................. 115
19.0 CAN Module............................................................................................................................................................................. 123
20.0 System Inte g r a tion ...... ..................... ..................... ..................... ........................... ................................................................... 133
21.0 10-bit High-Speed Analog-to-Digital Converter (ADC) Module........................... .... .. ......... .. .... .... .. ......... ................................. 149
22.0 Instruction Set Summary.......................................................................................................................................................... 161
23.0 Development Support............................................................................................................................................................... 169
24.0 Electrical Characteristics.......................................................................................................................................................... 173
25.0 Packagin g  In fo rmation.............................. ..................... ............................ ............................................................................... 213
Appendix A: Revision History . ............................................................................................................................................................ 217
Index .................................................................................................................................................................................................  219
The Micro chip Web Site................ .................................. ........................... ........................................................................................ 225
Customer Change Notification Service....................................................................... ...... ............. .................................................... 225
Customer Support............................................................. .... ............. ...... ...... ............. .... ................................................................... 225
Reader Response.............................................................................................................................................................................. 226
Product Identification System ............................................................................................................................................................ 227
TO OUR VALUED CUSTOMERS
It is our intention to  provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our pu blications to better s uit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced. 
If you have  any questions o r c omm ents regarding this publication, please c ontact the M arketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of an y page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet  and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To deter mine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microc hip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include  literature number) you are
using.
Customer Noti fic atio n Syst em
Register on our web site at www.microchip.com to receive the most current information on all of our products.

dsPIC30F5015/5016

NOTES:

dsPIC30F5015/5016

1.0 DEVICE OVERVIEW

This document contains device specific information for

the dsPIC30F5015 and dsPIC30F5016 devices. The

dsPIC30F devices contain extensive Digital Signal

Processor (DSP) functionality within a high-performance

16-bit microcontroller (MCU) architecture.

Figure 1-1 is a block diagram of the dsPIC30F5015

device. Following the block diagram, Table 1-1

provi des a brief descript ion of the device I/O pinout and

the functions that are multiplexed to the port pins on the

dsPIC30F5015.

Figure 1-2 is a block diagram of the dsPIC30F5016

device. Following the block diagram, Table 1-2

provi des a brief descript ion of the device I/O pinout and

the functions that are multiplexed to the port pins on the

dsPIC30F5016.

Note: This data sheet summarizes features of this

group of ds PIC30 F devi ces and is not intende d to be

a complete reference source. For more information

on the CPU, peripherals, register descriptions and

general device functionality, refer to the “dsPIC30F

Family Reference Manual” (DS70046). For more

information on the device instruction set and pro-

gramming, refer to the “dsPIC30F/33F Program-

mer’s Reference Manual” (DS70157).

dsPIC30F5015/5016

FIGURE 1-1: dsPIC30F5015 BLOCK DIAGRAM

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

VDD, VSS

AN4/QEA/CN6/RB4

AN12/RB12

AN13/RB13

AN14/RB14

AN15/CN12/RB15

Low-Voltage

Detect

UART1

SPI1, Motor Control

PWM

Timing

Generation

CAN1

AN5/QEB/CN7/RB5

PCH PCL

Program Counter

ALU<16>

Address Latch

Prog ram Memory

(66 Kbytes)

Data Latch

X Data Bus

I2C™

QEI

PGC/EMUC/AN6/OCFA/RB6

PGD/EMUD/AN7/RB7

PCU

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

10-bit ADC

Timers

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

SS2/CN11/RG9 CN18/RF5

EMUC3/SCK1/INT0/RF6

Input

Capture

Module

Output

Compare

Module

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/T4CK/CN1/RC13

PORTB

C1RX/RF0

C1TX/RF1

U1RX/SDI1/RF2

EMUD3/U1TX/SDO1/RF3

SCL/RG2

SDA/RG3

PORTG PORTF

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU

AN0/VREF+/CN2/RB0

AN1/VREF-/CN3/RB1

AN2/SS1/CN4/RB2

AN3/INDX/CN5/RB3

OSC2/CLKO/RC15

CN17/RF4

AVDD, A VSS

SPI2

PORTC

PORTE

Interrupt

Controller

PSV & Table

Data Access

Control Bl ock

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(1 Kbyte)

RAM X Data

(1 Kbyte)

RAM

Address

Latch

Address

Latch

Control Signals

to Various Blocks

EMUC2/OC1/RD0

EMUD2/OC2/RD1

OC3/RD2

OC4/RD3

IC5/CN13/RD4

IC6/CN14/RD5

CN15/RD6

UPDN/CN16/RD7

IC1/FLTA/INT1/RD8

IC2/FLTB/INT2/RD9

IC3/INT3/RD10

IC4/INT4/RD11

Data EEP ROM

(1 Kbyt e)

dsPIC30F5015/5016

Table 1-1 provides a brief description of the device I/O

pinout a nd the fun ctions t hat are multiple xed to th e port

pins on the dsPIC30F5015 device. Multiple functions

may exist on one port pin. When multiplexing occurs,

the peripheral module’s functional requirements may

force an override of the data direction of the port pin.

TABLE 1-1: I/O PIN DESCRIPTIONS FOR dsPIC30F5015

Pin Name Pin

Type Buffer

Type Description

AN0-AN15 I Analog Analog input channels.

AN0 and AN1 are also used for device programming data and clock inputs,

respectively.

AVDD P P Positive supply for analog module.

AVSS P P Ground reference for analog module.

CLKI

CLKO I

OST/CMOS

—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always

associated with OSC2 pin function.

CN0-CN18 I ST Input change notification inputs.

Can be software programmed for internal weak pull-ups on all inputs.

C1RX

C1TX I

OST

—CAN1 bus recei ve pi n.

CAN1 bus transmit pin.

EMUD

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

EMUD3

EMUC3

I/O

ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data input/output pin.

ICD Secondary Communication Channel clock input/output pin.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary Communication Channel clock input/output pin.

ICD Quaternary Communication Channel data input/output pin.

ICD Quaternary Communication Channel clock input/output pin.

IC1-IC4 I ST Capture inputs 1 through 4.

INDX

QEA

QEB

UPDN

CMOS

Quadratu re Enco der Inde x Puls e inpu t.

Quadrature Encoder Phase A input in QEI mode.

Auxiliary Timer External Clock/Gate input in Timer mode.

Quadrature Encoder Phase A input in QEI mode.

Auxiliary Timer External Clock/Gate input in Timer mode.

Position Up/Down Counter Direction State.

INT0

INT1

INT2

INT3

INT4

External interrupt 0.

External interrupt 1.

External interrupt 2.

External interrupt 3.

External interrupt 4.

FLTA

FLTB

PWM1L

PWM1H

PWM2L

PWM2H

PWM3L

PWM3H

PWM4L

PWM4H

—

PWM Fault A input.

PWM Fault B input.

PWM 1 Low output.

PWM 1 High output.

PWM 2 Low output.

PWM 2 High output.

PWM 3 Low output.

PWM 3 High output.

PWM 4 Low output.

PWM 4 High output.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F5015/5016

MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active-

low Reset to the device.

OCFA

OC1-OC4 I

OST

—Compare Fault A input (for Compare channels 1, 2, 3 and 4).

Compar e outputs 1 thro ugh 4.

OSC1

OSC2

I/O

ST/CMOS

—

Oscillator crystal input. ST buffer when configured in RC mode; CMOS

otherwise.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator

mode. Optionally functions as CLKO in RC and EC modes.

PGD

PGC I/O

IST

ST In-Circuit Serial Programming™ data input/output pin.

In-Circuit Serial Programming clock input pin.

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.

RC13-RC15 I/O ST PORTC is a bidirectional I/O port.

RD0-RD11 I/O ST PORTD is a bidirectional I/O port.

RE0-RE7 I/O ST PORTE is a bidirectional I/O port.

RF0-RF6 I/O ST PORTF is a bidirectional I/O port.

RG2-RG3

RG6-RG9 I/O

I/O ST

ST PORTG is a bidirectional I/O port.

SCK1

SDI1

SDO1

SS1

SCK2

SDI2

SDO2

SS2

I/O

—

Synchronous serial clock input/output for SPI #1.

SPI #1 Data In.

SPI #1 Data Out.

SPI #1 Slave Synchronization.

Synchronous serial clock input/output for SPI #2.

SPI #2 Data In.

SPI #2 Data Out.

SPI #2 Slave Synchronization.

SCL

SDA I/O

I/O ST

ST Synchronous serial clock input/output for I2C™.

Synchronous serial data input/output for I2C.

SOSCO

SOSCI O

I—

ST/CMOS 32 kHz low-power oscillator crystal output.

32 kHz low-power oscillator crystal input. ST buffer when configured in RC

mode; CMOS otherwise.

T1CK

T4CK I

IST

ST Timer1 external clock input.

Timer4 external clock input.

U1RX

U1TX I

OST

—UART1 Receive.

UART1 Transmit.

VDD P — Positive supply for logic and I/O pins.

VSS P — Ground reference for logic and I/O pins.

VREF+ I Analog Analog Voltage Reference (High) input.

VREF- I Analog Analog Voltage Reference (Low) input.

TABLE 1-1: I/O PIN DESCRIPTIONS FOR dsPIC30F5015 (CONTINUED)

Pin Name Pin

Type Buffer

Type Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F5015/5016

FIGURE 1-2: dsPIC30F5016 BLOCK DIAGRAM

AN8/RB8

AN9/RB9

AN10/RB10

AN11/RB11

Power-up

Timer

Oscillator

Start-up Timer

POR/BOR

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKI

MCLR

VDD, VSS

AN4/QEA/CN6/RB4

AN12/RB12

AN13/RB13

AN14/RB14

AN15/CN12/RB15

Low-Voltage

Detect

UART1

SPI1, Motor Control

PWM

INT4/RA15

INT3/RA14

VREF+/RA10

VREF-/RA9

Timing

Generation

CAN1

AN5/QEB/CN7/RB5

PCH PCL

Program Counter

ALU<16>

Address Latch

Prog ram Memory

(66 Kbytes)

Data Latch

X Data Bus

I2C™

QEI

AN6/OCFA/RB6

AN7/RB7

PCU

PWM1L/RE0

PWM1H/RE1

PWM2L/RE2

PWM2H/RE3

PWM3L/RE4

10-bit ADC

Timers

PWM3H/RE5

PWM4L/RE6

PWM4H/RE7

FLTA/INT1/RE8

FLTB/INT2/RE9

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

SS2/CN11/RG9

CN18/RF5

EMUC3/SCK1/INT0/RF6

SDI1/RF7

EMUD3/SDO1/RF8

Input

Capture

Module

Output

Compare

Module

EMUC1/SOSCO/T1CK/CN0/RC14

EMUD1/SOSCI/CN1/RC13

T4CK/RC3

T2CK/RC1

PORTB

C1RX/RF0

C1TX/RF1

U1RX/RF2

U1TX/RF3

RG0

RG1

SCL/RG2

SDA/RG3

PORTG PORTF

PORTD

16 16

16 x 16

W Reg Array

Divide

Unit

Engine

DSP

Decode

ROM Latch

Y Data Bus

Effective Address

X RAGU

X WAGU

Y AGU

PGD/EMUD/AN0/CN2/RB0

PGC/EMUC/AN1/CN3/RB1

AN2/SS1/CN4/RB2

AN3/INDX/CN5/RB3

OSC2/CLKO/RC15

CN17/RF4

AVDD, A VSS

SPI2

PORTA

PORTC

PORTE

Interrupt

Controller

PSV & Table

Data Access

Control Bl ock

Stack

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

(1 Kbyte)

RAM X Data

(1 Kbyte)

RAM

Address

Latch

Address

Latch

Control Signals

to Various Blocks

EMUC2/OC1/RD0

EMUD2/OC2/RD1

OC3/RD2

OC4/RD3

CN13/RD4

CN14/RD5

CN15/RD6

CN16/UPDN/RD7

IC1/RD8

IC2/RD9

IC3/RD10

IC4/RD11

RD12

CN19/RD13

CN20/RD14

CN21/RD15

Data EEP ROM

(1 Kbyt e)

dsPIC30F5015/5016

Table 1-1 provides a brief description of the device I/O

pinout a nd the fun ctions t hat are multiple xed to th e port

pins on the dsPIC30F5016. Multiple functions may

exist on one port pin. When multiplexing occurs, the

periphe ral mo dule’s functional requir ements may force

an override of the data direction of the port pin.

TABLE 1-2: I/O PIN DESCRIPTIONS FOR dsPIC30F5016

Pin Name Pin

Type Buffer

Type Description

AN0-AN15 I Analog Analog input channels.

AN0 and AN1 are also used for device programming data and clock inputs,

respectively.

AVDD P P Positive supply for analog module.

AVSS P P Ground reference for analog module.

CLKI

CLKO I

OST/CMOS

—External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always

associated with OSC2 pin function.

CN0-CN21 I ST Input change notification inputs.

Can be software programmed for internal weak pull-ups on all inputs.

C1RX

C1TX I

OST

—CAN1 bus recei ve pi n.

CAN1 bus transmit pin.

EMUD

EMUC

EMUD1

EMUC1

EMUD2

EMUC2

EMUD3

EMUC3

I/O

ICD Primary Communication Channel data input/output pin.

ICD Primary Communication Channel clock input/output pin.

ICD Secondary Communication Channel data input/output pin.

ICD Secondary Communication Channel clock input/output pin.

ICD Tertiary Communication Channel data input/output pin.

ICD Tertiary Communication Channel clock input/output pin.

ICD Quaternary Communication Channel data input/output pin.

ICD Quaternary Communication Channel clock input/output pin.

IC1-IC4 I ST Capture inputs 1 through 8.

INDX

QEA

QEB

UPDN

CMOS

Quadratu re Enco der Inde x Puls e inpu t.

Quadrature Encoder Phase A input in QEI mode.

Auxiliary Timer External Clock/Gate input in Timer mode.

Quadrature Encoder Phase A input in QEI mode.

Auxiliary Timer External Clock/Gate input in Timer mode.

Position Up/Down Counter Direction State.

INT0

INT1

INT2

INT3

INT4

External interrupt 0.

External interrupt 1.

External interrupt 2.

External interrupt 3.

External interrupt 4.

FLTA

FLTB

PWM1L

PWM1H

PWM2L

PWM2H

PWM3L

PWM3H

PWM4L

PWM4H

—

PWM Fault A input.

PWM Fault B input.

PWM 1 Low output.

PWM 1 High output.

PWM 2 Low output.

PWM 2 High output.

PWM 3 Low output.

PWM 3 High output.

PWM 4 Low output.

PWM 4 High output.

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F5015/5016

MCLR I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active-

low Reset to the device.

OCFA

OCFB

OC1-OC4

—

Compare Fault A input (for Compare channels 1, 2, 3 and 4).

Compare Fault B input (for Compare channels 5, 6, 7 and 8).

Compar e outputs 1 thro ugh 4.

OSC1

OSC2

I/O

ST/CMOS

—

Oscillator crystal input. ST buffer when configured in RC mode; CMOS

otherwise.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator

mode. Optionally functions as CLKO in RC and EC modes.

PGD

PGC I/O

IST

ST In-Circuit Serial Programming™ data input/output pin.

In-Circuit Serial Programming clock input pin.

RA9-RA10

RA14-RA15 I/O

I/O ST

ST PORTA is a bidirectional I/O port.

RB0-RB15 I/O ST PORTB is a bidirectional I/O port.

RC1

RC3

RC13-RC15

I/O

PORTC is a bidirectional I/O port.

RD0-RD15 I/O ST PORTD is a bidirectional I/O port.

RE0-RE9 I/O ST PORTE is a bidirectional I/O port.

RF0-RF8 I/O ST PORTF is a bidirectional I/O port.

RG0-RG3

RG6-RG9 I/O

I/O ST

ST PORTG is a bidirectional I/O port.

SCK1

SDI1

SDO1

SS1

SCK2

SDI2

SDO2

SS2

I/O

—

Synchronous serial clock input/output for SPI #1.

SPI #1 Data In.

SPI #1 Data Out.

SPI #1 Slave Synchronization.

Synchronous serial clock input/output for SPI #2.

SPI #2 Data In.

SPI #2 Data Out.

SPI #2 Slave Synchronization.

SCL

SDA I/O

I/O ST

ST Synchronous serial clock input/output for I2C™.

Synchronous serial data input/output for I2C.

SOSCO

SOSCI O

I—

ST/CMOS 32 kHz low-power oscillator crystal output.

32 kHz low-power oscillator crystal input. ST buffer when configured in RC

mode; CMOS otherwise.

T1CK

T2CK

T4CK

Timer1 external clock input.

Timer2 external clock input.

Timer4 external clock input.

U1RX

U1TX I

OST

—UART1 Receive.

UART1 Transmit.

VDD P — Positive supply for logic and I/O pins.

VSS P — Ground reference for logic and I/O pins.

VREF+ I Analog Analog Voltage Reference (High) input.

VREF- I Analog Analog Voltage Reference (Low) input.

TABLE 1-2: I/O PIN DESCRIPTIONS FOR dsPIC30F5016 (CONTINUED)

Pin Name Pin

Type Buffer

Type Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input

ST = Schmitt Trigger input with CMOS levels O = Output

I = Input P = Power

dsPIC30F5015/5016

NOTES:

dsPIC30F5015/5016

2.0 CPU ARCHITECTURE

OVERVIEW

This document provides a summary of the

dsPIC30F5015/5016 CP U and perip heral function . For

a compl ete descrip tion of this func tionality, please refer

to the “dsPIC30F Family Reference Manual”

(DS70046).

2.1 Core Overview

The core has a 24-bit instruction word. The Program

Counter (PC) is 23 bits wide with the Least Significant

bit (LSb) always clear (see Section 3.1 “Program

Address Space”), and the Most Significant bit (MSb)

is ign ored du ring no rmal program executi on, ex cept for

certain specialized instructions. Thus, the PC can

address up to 4M instruction words of user program

space. An instruction prefetch mechanism is used to

help maintain throughput. Program loop constructs,

free from loop count management overhead, are

supported using the DO and REPEAT inst ru cti on s, b oth

of which are int errup tib le at any point.

The working register array consists of 16x16-bit

set registers. One working register (W15) operates as

a software Stack Pointer for interrupts and calls.

The data space is 64 Kbytes (32K words) and is split

into two blocks, referred to as X and Y data memory.

Each block has its own independent Address Genera-

tion Unit (AGU). Most instructions operate solely

through the X memory AGU, which provides the

appearance of a single unified data space. The

Multiply-Accumulate (MAC) class of dual source DSP

instructions operate through both the X and Y AGUs,

splitting the data address space into two parts (see

Section 3.2 “Data Address Space”). The X and Y

data space boundary is device specific and cannot be

alter ed by the user . Each dat a word consis ts of 2 bytes,

and mos t instruction s can address data eith er as words

or bytes.

There are two methods of accessing data stored in

program memory:

•

The upper 32 Kbytes of data sp ace memory can b e

mapped into the lower half (user space) of program

space a t any 16K program w ord boundary, defined

by the 8-bit Program Space V isibility Page

(PSVPAG) register. This lets any instruction

access program space as if it were data space,

with a limitation that the access requires an addi-

tional cycle. Moreover, only the lower 16 bits of

each instruction word can be access ed using this

method.

• Linear indirect access of 32K word pages within

progra m spac e is also possibl e using any w orking

Table read and write instructions can be used to

access all 24 bits of an instruction word.

Overhead-free circular buffers (Modulo Addressing)

are supported in both X and Y address spaces. This is

primarily intended to remove the loop overhead for

DSP algorithms.

The X AGU also supports Bit-Reversed Addressing on

destination effective addresses, to greatly simplify

input or output data reordering for radix-2 FFT algo-

rithms. Refer to Section 4.0 “Address Generator

Units” for details on Modulo and Bit-Reversed

Addressing.

The core s up ports Inherent (n o op era nd), Re lat iv e, Lit-

eral, Memory Direct, Register Direct, Register Indirect,

Instruct ion s are associ ated wi th predefi ned addr essin g

modes, depending upon their functional requirements.

For m os t i ns tru c ti o ns , the c or e i s c apa bl e of e xe c ut i ng

a data (or program data) memory read, a working reg-

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, 3-operand instructions are supported, allowing

C = A + B operations to be executed in a single cycle.

A DSP engine has been included to significantly

enhance the core arithmetic capab ility and throughput.

It features a high-speed 17-bit by 17-bit multiplier, a

40-bit ALU, two 40-bit saturating accumulators and a

40-bit b idi rec tio nal b arrel shifter. Dat a in th e a cc umul a-

tor or any worki ng r egist er can be shif ted up to 16 bits

right or 16 bits left in a single cycle. The DSP instruc-

tions ope rate sea mles sly with all other in struct ions an d

have be en desi gned for o ptimal re al-time p erforma nce.

The MAC class of instructions can concurrently fetch

two data operands from memory, while multiplying two

W registers. To enable this concurrent fetching of data

operands, the data space has been split for these

instructions and linear for all others. This has been

achiev ed in a tran sp a r en t and fle xib le mann er, by ded-

icating cert ain worki ng registe rs to e ach addre ss spac e

for the MAC class of instructions.

Note: This data sheet summarizes features of this

group of ds PIC30 F devi ces and is not intende d to be

a complete reference source. For more information

on the CPU, peripherals, register descriptions and

general device functionality, refer to the “dsPIC30F

Family Reference Manual” (DS70046). For more

information on the device instruction set and pro-

gramming, refer to the “dsPIC30F/33F Program-

mer’s Reference Manual” (DS70157).

dsPIC30F5015/5016

The core does not support a multi-stage instruction

pipeline. However, a single stage instruction prefetch

mechanism is used, which accesses and partially

decodes instructions a cycle ahead of execution, in

order to maximize available execution time. Most

instructions execute in a single cycle, with certain

exceptions.

The core features a vectored exception processing

structure for traps and interrupts, with 62 independent

vectors. The exceptions consist of up to 8 traps (of

which 4 are re served ) a nd 54 interrupts . Ea ch in terru pt

is priorit ized based on a use r assigned prio rity between

1 and 7 (1 being the lowest priority and 7 being the

highest) in conjunction with a predetermined ‘natural

order’. T raps ha ve fixed prio rities, rang ing from 8 to 15.

2.2 Programmer’s Model

The programmer’s model is shown in Figure 2-1 and

consists of 16x16-bit working registers (W0 through

W15), 2x40-bit accumulators (ACCA and ACCB),

STATUS register (SR), Data Table Page register

(TBLPAG), Program Space Visibility Page register

(PSVPAG), DO and REPEAT registers (DOSTART,

DOEND, DCOUNT and RCOUNT) and Program

Counter (PC). The working registers can act as data,

address or offset registers. All registers are memory

mapped. W0 acts as the W register for file register

addressing.

Some of these registers have a shadow register asso-

ciated with each of them, as shown in Figure 2-1. The

shadow register is used as a temporary h olding register

and can tr ansfer its con tents to or fro m i t s hos t reg is ter

upon the occurrence of an event. None of the shadow

registers are accessible directly. The following rules

apply for transfer of registers into and out of shadows.

•PUSH.S and POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits

only) are transferred.

•DO instruction

DOSTART, DOEND, DCOUNT shadows are

pushed on loop start, and popped on loop end.

When a byte operation is performed on a working

get r egis ter i s affec ted. H owever, a be nefit of m emory

mapped working registers is that both the Least and

Most Significant Bytes (MSBs) can be manipulated

through byte-wide data memory space accesses.

2.2.1 SOFTWARE STACK POINTER/

FRAM E POIN TE R

The dsPIC® DSC devices contain a software stack.

W15 is the dedicated software Stack Pointer (SP), and

will be automatically modified by exception processing

and subroutine calls and returns. However, W15 can

be referenced by any instruction in the same manner

as all other W registers. This simplifies the reading,

writing and mani pulati on of the Stack Poi nter (e .g., cre-

ating stack frames).

W15 is initialized to 0x0800 during a Reset. The user

may reprogram the SP during initialization to any

location within data space.

W14 has been dedicated as a Stack Frame Pointer as

defined by the LNK and ULNK instructions. However,

W14 can be referenced by any instruction in the same

manner as all other W registers.

2.2.2 STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS register

(SR), the LSB of which is referred to as the SR Low

Byte (SRL) and the MSB as the SR High Byte (SRH).

See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation Status flags

(includ ing the Z bit ), as well as the CPU Inter rupt Prior-

ity Level Status bits, IPL<2:0>, and the Repeat Active

Status bit, RA. During exception processing, SRL is

concatenated with the MSB of the PC to form a

complete word value which is then stacked.

The upper byte of the SR register contains the DSP

Adder/Subtracter Status bits, the DO Loop Active bit

(DA) and the Digit Carry (DC) Status bit.

2.2.3 PROGRAM COUNT ER

The Program Counter is 23 bits wide. Bit 0 is always

clear. Therefore, the PC can address up to 4M

instruction words.

Note: In order to protect against misaligned

stack accesses, W15<0> is always clear.

dsPIC30F5015/5016

FIGURE 2-1: dsPIC30F5015/5016 PROGRAMMER’S MODEL

TABPAG

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP Operand

Registers

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address

Registers

AD39 AD0AD31

DSP

Accumulators ACCA

ACCB

PSVPAG

7 0Program Space Visibility Page Address

OA OB SA SB

RCOUNT

15 0

REPEAT Loop Counter

DCOUNT

15 0

DO Loop Counter

DOSTART

22 0

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0 Core Configuration Register

Legend

CORCON

DA DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

dsPIC30F5015/5016

2.3 Divide Support

The dsPIC DSC devices feature a 16/16-bit signed

fractional divide operation, as well as 32/16-bit and

16/16-bit signed and unsigned integer divide

operations, in the form of single instruction iterative

divides. The follo wing in stru ctions a nd data sizes a re

supported:

1. DIVF – 16/16 signed fractional divide

2. DIV.sd – 32/16 signed divide

3. DIV.ud – 32/16 unsigned divide

4. DIV.sw – 16/16 signed divide

5. DIV.uw – 16/16 unsigned divide

The divide instructions must be executed within a

REPEAT loop. Any other form of execution (e.g. a s eries

of discrete divide instructions) will not function correctly

because the instructio n flow depends on RC OUNT. The

divide instruction does not automatically set up the

RCOUNT value, a nd it m ust, therefore, b e expl icitly and

correctly specified in the REPEAT instruction, as shown

in Table 2-1 (REPEAT will execute the target instruction

{operand value+1} times). The REPEAT loop count must

be set up for 18 iterations of the DIV/DIVF instruction.

Thus, a complete divide op eration requires 19 c ycles .

TABLE 2-1: DIVIDE INSTRUCTIONS

2.4 DSP Engine

The DSP engine consis ts of a hi gh-speed 17-bit x 17-bit

multiplier, a barrel shifter, and a 40-bit adder/subtracter

(with two target accumulators, round and saturation

logic).

The dsPIC30F devices have a single instruction flow

which can execute either DSP or MCU instructions.

Many of the hardware resources are shared between

the DSP and MCU instructions. For example, the

instruction set has both DSP and MCU multiply

instructions which use the same hardware multiplier.

The DSP engine also has the capability to perform inher-

ent accumulator-to-accumulator operations, which

require no additional data. These instructions are ADD,

SUB and NEG.

The DSP engine has various options selected through

various bits in the CPU Core Configuration register

(CORCON), as listed below:

1. Fractional or Integer DSP Multiply (IF).

2. Signed or Unsigned DSP Multiply (US).

3. Convention al or Convergent Round i ng (RND).

4. Automatic Saturation On/Off for ACCA (SATA).

5. Automatic Saturation On/Off for ACCB (SATB).

6. Automatic Saturation On/Off for Writes to Data

Memory (SATDW).

7. Accumulator Saturation mode Selection

(ACCSAT).

A block diagram of the DSP engine is shown in

Figure 2-2.

Note: The divide flow is interruptible. However,

the user needs to save the context as

appropriate.

Instruction Function

DIVF Signed fractional divide: Wm/Wn → W0; Rem → W1

DIV.sd Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.ud Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1

DIV.sw Signed divide: Wm/Wn → W0; Rem → W1

DIV.uw Unsigned divide: Wm/Wn → W0; Rem → W1

Note: For CORCON layout, see Table 3-3.

TABLE 2-2: DSP INSTRUCTION

SUMMARY

Instruction Algebraic Operation

CLR A = 0

ED A = (x – y)2

EDAC A = A + (x – y)2

MAC A = A + (x * y)

MOVSAC No change in A

MPY A = x * y

MPY.N A = – x * y

MSC A = A – x * y

dsPIC30F5015/5016

FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM

Zero Backfill

Sign-Extend

Barrel

Shifter

40-bit Accumulator A

40-bit Accumulator B Round

Logic

X Data Bus

To/From W Array

Adder

Saturate

Negate

16 16

40 40

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-bit

dsPIC30F5015/5016

2.4.1 MULTIPLIER

The 17x17-bit multiplier is capable of signed or

unsigned operations and can multiplex its output using

a scale r to support eit her 1.31 fracti onal (Q31) or 32-bit

integer results. Unsigned operands are zero-extended

into the 17th bit of the multiplier input value. Signed

operands are sign-extended into the 17th bit of the

multiplier input value. The output of the 17x17-bit

multiplier/scaler is a 33-bit value, which is sign-

extended to 40 bits. Integer data is inherently

represented as a signed two’s complement value,

where the MSB is defined as a sign bit. Generally

speaking, the range of an N-bit two’s complement

integer is -2N-1 to 2N-1 – 1. For a 16-bit integer , the data

range is -3276 8 (0x8 000) to 32767 (0x7F FF), inc ludin g

0. For a 32 -bit intege r , the data r ange is -2, 147,483,648

(0x8000 0000) to 2,147,483,645 (0x7FFF FFFF).

When the multiplier is configured for fractional multipli-

cation, the data is represented as a two’s complement

fraction , where the M SB is define d as a sign b it and the

radix point is implied to lie just after the sign bit

(QX format). The range of an N-bit two’s complement

fraction with th is impl ied ra dix p oint i s -1.0 to (1 – 21-N).

For a 16-bit fraction, the Q15 data range is -1.0

(0x8000) to 0.999969482 (0x7FFF), including 0 and

has a precision of 3.01518x10-5. In Fractional mode, a

16x16 multiply operation generates a 1.31 product,

which has a precision of 4.65661x10-10.

The same multiplier is used to support the MCU multi-

ply instructions, which include integer 16-bit signed,

unsigned and mixed sign multiplies.

The MUL instruction may be directed to use byte or

word-size d operands . Byte operan ds will dire ct a 16-bit

result, and word operands will direct a 32-bit result to

the specified register(s) in the W array.

2.4.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/sub-

tracter wi th automatic si gn extension logi c. It can select

one of two accumulators (A or B) as its pre-

accumulation source and post-accumulation destina-

tion. For the ADD and LAC instructions, the data to be

accum ulated or l oaded ca n be optio nally sca led via th e

barrel shifter, prior to accumulation.

2.4.2.1 Adder/Subtracter, Overflow and

Saturation

The adder/subtracter is a 40-bit adder with an optional

zero input into one side and either true or complement

data into the other input. In the case of addition, the

carry/borrow input is active-high and the other input is

true data (not complemented), whereas in the case of

subtraction, the carry/borrow input is active-low and the

other input is complemented. The adder/subtracter

generates Overflow Status bits, SA/SB and OA/OB,

which are latched and reflected in the STATUS

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is

destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all

the guard bits are not identical to each other.

The adder has an additional saturation block which

controls accumulator data saturation, if selected. It

uses the result of the adder, the Overflow Status bits

described above, and the SATA/B (CORCON<7:6>)

and ACCSAT (CORCON<4>) mode control bits to

determine when and to what value to saturate.

Six STATUS register bits have been provided to

support saturation and overflow; they are:

1. OA:

ACCA overflowed into guard bits

2. OB:

ACCB overflowed into guard bits

3. SA:

ACCA saturated (bit 31 overflo w and saturatio n)

ACCA overflowed into guard bits and saturated

(bit 39 overflow and saturation)

4. SB:

ACCB saturated (bit 31 overflo w and saturatio n)

ACCB overflowed into guard bits and saturated

(bit 39 overflow and saturation)

5. OAB:

Logical OR of OA and OB

6. SAB:

Logical OR of SA and SB

The OA and OB bits are modified each time data

passes through the adder/subtracter. When set, they

indicate that the most recent operation has overflowed

into the accumulator guard bits (bits 32 through 39).

The OA and OB bits can also optionally generate an

arithmetic warning trap when set and the correspond-

ing overflow trap flag enable bit (OVATE, OVBTE) in

the INTCON1 register (refer to Section 5.0 “Inter-

rupts”) is set. This allows the user to take immediate

action, for example, to correct system gain.

dsPIC30F5015/5016

The SA and SB bit s are modified each ti me data pass es

through the adder/subtracter, but can only be cleared by

the user. When set, they indicate that the accumulator

has overflowed its maximum range (bit 31 for 32-bit

saturation, or bit 39 for 40-bit saturation) and wi ll be sat-

urated (if saturation is enabled). When saturation is not

enabled, SA and SB default to bit 39 overflow and thus

indicate that a cat astrophic overfl ow has occurred. If the

COVTE bit in the INTCON1 register is set, SA and SB

bits will generate an arithmetic warning trap when

saturation is disabled.

The Overflow and Saturation Status bits can optionally

be viewed in the STATUS register (SR) as the logical

OR of OA an d OB (in bit OAB) and the logical OR of SA

and SB (in bit SAB). Th is allows programm ers to check

one bit in the STATUS register to determine if either

accumulator has overflowed, or one bit to determine if

either a ccum ulator has satu rated. T his w ould be usefu l

for complex number arithmetic which typically uses

both the accu mul ators.

The device supports three Saturation and Overflow

modes.

1. Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the

saturation logic load s the maximally positive 9.31

(0x7FFFFFFFFF) or maximally negative 9.31

value (0 x8000000 000) into th e target accumul a-

tor. The SA or SB bit is set and remains set until

cleared by the user. This is referred to as ‘super

saturation’ and provides protection against erro-

neous data or unexpected algorithm problems

(e.g., gain calculations).

2. Bit 31 Overflow and Saturation:

When bit 31 overflow and saturation occurs, the

saturation logic then loads the maximally posi-

tive 1.31 value (0x007FFFFFFF) or maximally

negative 1.31 value (0x0080000000) into the

target accumulator. The SA or SB bit is set and

remains set until cleared by the user. When this

Saturation mode is in effect, the guard bits are not

used (so the OA, OB or OAB bits are never set).

3. Bit 39 Catastrophic Overflow

The bit 39 Overflow Status bit from the adder is

used to set the SA or SB bit, which remain set

until cleared by the user. No saturation opera-

tion is performed and the accumulator is allowed

to overflow (destroying its sign). If the COVTE

bit in the INTCON1 register i s set, a cat astrophic

ove rflow can initiate a trap exception.

2.4.2.2 Accumulat or ‘Write Back’

The MAC class of instructions (with the exception of

MPY, MPY.N, ED and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16)

of the acc umulator that is not t argeted by the instruction

into dat a spac e memory. The write is performe d across

the X bus into combined X and Y address space. The

following addressing modes are supported:

1. W13, Register Direct:

The rounded contents of the non-target accumula-

tor are written into W13 as a 1.15 fraction.

2. [W13]+ = 2, Register Indirect with Post-Incre ment:

The rounded contents of the non-target accu-

mulator are written into the address pointed to

by W13 as a 1.15 fraction. W13 is then

incremented by 2 (fo r a wo rd wr ite).

2.4.2.3 Round Logic

The round logic is a combinational block, which per-

forms a conventional (biased) or convergent (unbiased)

round function during an accumulator write (store). The

Round mode is det ermined by the state of the RND bit

in the CORCON register. It generates a 16-bit, 1.15

data value which is passed to the data space writ e sat-

uration log ic. I f ro undi ng is not indi cate d by the instr uc-

tion, a truncated 1.15 data value is stored and the least

significant word (lsw) is simply discarded.

Conventional rounding takes bit 15 of the accumulator,

zero-extends it and ad ds it to the AC CxH word (bi t s 16

through 31 of the accum ulator). I f the AC CxL word ( bits

0 through 15 of the accumulator) is between 0x8000

and 0xFFFF (0x8000 included), ACCxH is incre-

mented. If ACCxL is between 0x0000 and 0x7FFF,

ACCxH is left un ch ang ed. A consequenc e of thi s alg o-

rithm is that over a succession of random rounding

operations, the value will tend to be biased slightly

positive.

Convergent (or unbiased) rounding operates in the

same manner as conventional rounding, except when

ACCxL equals 0x8000. If this is the case, the LSb (bit

16 of the accumulator) of ACCxH is examined. If it is ‘1’,

ACCxH is inc remen ted. If it is ‘0’, ACCxH is not modi-

fied. Assuming that bit 16 is effectively random in

nature, th is s c hem e w i ll re mo ve any rou ndi ng b ias th at

may accumulate .

The SAC and SAC.R instructions store either a trun-

cated (SAC) or rounded (SAC.R) version of the cont ents

of the t arget accumul ator to data mem ory , via the X bu s

(subject to data saturation, see Section 2.4.2.4 “Data

Space Write Saturation”). Note that for the MAC cl as s

of instructions, the accumulator write back operation

will fu nction in th e same mann er , a ddressing combine d

MCU (X and Y) data space though the X bus. For this

class of instructions, the data is always subject to

rounding.

dsPIC30F5015/5016

2.4.2.4 Data Space Write Saturation

In ad dition to add er/subtr acter sat uration , writes to data

space may also be saturated, but without affecting the

contents of the source accumulator. The data space

write saturation logic block accepts a 16-bit, 1.15 frac-

tional value from the round logic block as its input,

together with overflow status from the original source

(accumulator) and the 16-bit round adder. These are

comb in ed an d used to s el ec t the a pp r op ria te 1.15

fraction al va lue as outp ut to writ e to dat a sp ace m emor y.

If the SATDW bit in the CORCON register is set, data

(after roundi ng or trun ca tio n) is tes te d for ove rflo w and

adjusted accordingly. For input data greater than

0x007FF F, dat a written to me mory is forced to the max-

imum posit ive 1. 15 val ue, 0x7FFF. F or inp ut da ta less

than 0x FF8000, dat a wri tten to memo ry is f orced to the

maximum negative 1.15 value, 0x8000. The MSb of the

source (bit 39) is used to determine the sign of the

operand bei ng tes ted.

If the SATDW bit in the CORCON register is n ot set, the

input data is always passed through unmodified under

all conditions.

2.4.3 BARREL SHIFTER

The barrel shifter is capable of performing up to 16-bit

arithmetic or logic right shifts, or up to 16-bit left shifts

in a single cycle. The source can be either of the two

DSP accumulators or the X bus (to support multi-bit

shifts of register or memory data).

The sh ifter requires a s ign ed bi nary v al ue to de term in e

both the magnitude (number of bits) and direction of the

shift operation. A positive value will shift the operand

right. A negative value will shift the operand left. A

value of ‘0’ will not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a

40-bit res ult for DSP shift ope rations an d a 16-bit resu lt

for MCU shift operations. Data from the X bus is pre-

sented to the barrel shifter between bit positions 16 to

31 for right sh ifts, and bit positio ns 0 to 15 for left sh ifts.

dsPIC30F5015/5016

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

The program address space is 4M instruction words. It

is addressable by the 23-bit PC, table instruction

Effective Address (EA), or data space EA, when

program space is mapped into data space, as defined

by Table 3-1. Note that the program space address is

incremented by two between successive program

words, in orde r to pro vide c omp atibi lity w ith d ata sp ace

addressing.

User program space access is restricted to the lower

4M instruction word address range (0x000000 to

0x7FFFFE) , for all access es other than TBLRD/TBLWT,

which use TBLPAG<7> to dete rmine user or c onfigura-

tion space access. In TABLE 3-1: “Program Space

Address Construction”, bit 23 allows access to the

Device ID, the User ID and the Configuration bits.

Otherwise, bit 23 is always clear.

FIGURE 3-1:

PROGRAM SP AC E

MEMORY MAP FOR

dsPIC30F5015/5016

Note: This data sheet summarizes features of this

group of ds PIC30 F devi ces and is not intende d to be

a complete reference source. For more information

on the CPU, peripherals, register descriptions and

general device functionality, refer to the “dsPIC30F

Family Reference Manual” (DS70046). For more

information on the device instruction set and pro-

grammi ng, refe r to the “dsPIC30F/33F

Programmer’s Reference Manual” (DS70157).

Reset - Target Address

User Memor y

Space

000000

00007E

000002

000080

Device Configuration

User Flash

Program Memory

00B000

00AFFE

Configuration Memory

Space

Data EEPROM

(22K instructions)

(1 Kbyte)

800000

F80000

Registers F8000E

F80010

DEVID (2) FEFFFE

FF0000

FFFFFE

Reserved F7FFFE

Reserved

7FFC00

7FFBFE

(Read ‘0’s)

8005FE

800600

UNITID (32 instr.)

8005BE

8005C0

Reset - GOTO Instruction

000004

Reserved

7FFFFE

Reserved

000100

0000FE

000084

Alterna te Vector Table

Reserved

Interrupt Vector Table Vector Tables

dsPIC30F5015/5016

TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Access Type Access

Space Program Spac e Address

<23> <22:16> <15> <14:1> <0>

Instruction Access User 0 PC<22:1> 0

TBLRD/TBLWT User

(TBLPAG<7> = 0)TBLPAG<7:0> Data EA<15:0>

TBLRD/TBLWT Configuration

(TBLPAG<7> = 1)TBLPAG<7:0> Data EA<15:0>

Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>

0Program Counter

23 bits

PSVPAG Reg

8 bits

15 bits

Program

Using

Select

TBLPAG Reg

8 bits

16 bits

Using

Byte

24-bit EA

1/0

Select

User/

Configuration

Table

Instruction

Program

Space

Counter

Using

Space

Select

Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory.

Visibility

dsPIC30F5015/5016

3.1.1 DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

This arc hit ec ture f etc hes 24 -bi t w ide prog ram me mo ry.

Consequently, instructions are always aligned. How-

ever, as the architecture is modified Harvard, data can

also be present in prog ram space.

There are two methods by which program space can

be accessed; via special table instructions, or through

the rema ppi ng of a 16K w ord prog ram space page into

the u pp e r half o f da ta space (s ee Section 3.1.2 “Data

Access From Program Memory Using Program

Space Visibility”). The TBLRDL and TBLWTL instruc-

tions of fer a direct method of reading or writing the least

significant word of any address within program space,

without going through data space. The TBLRDH and

TBLWTH instructions are the only method whereby the

upper 8 bit s o f a pro gram s pa ce word can be acc esse d

as data.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit

word wide add res s s p ac es , res id ing sid e by si de, each

with the same address range. TBLRDL and TBLWTL

access the space that contains the least significant

word, and TBLRDH and TBLWTH access the space that

cont ains the MSB.

Figure 3-2 shows how th e EA is cre ate d fo r t able oper-

ations and data space accesses (PSV = 1). Here,

P<23:0> refers to a program space word, whereas

D<15:0> refers to a data space word.

A set of t able inst ruc tions are prov ide d to move by te or

word-sized data to and from program space.

1. TBLRDL: Table Read Low

Word: Read the least significant word of the

program address;

P<15:0> maps to D<15:0>.

Byte: Read one of the LSBs of the program

address;

P<7:0> maps to the destination byte when byte

select = 0;

P<15:8> m aps to the d estination byte when byte

select = 1.

2. TBLWTL: Ta ble Write Low (ref er to Section 6.0

“Flash Program Memory” for details on Flash

Programming).

3. TBLRDH: Table Read High

Word: Read the most significant word of the

program address;

P<23:16> maps to D<7:0>; D<15:8> always

is = 0.

Byte: Read one of the MSBs of the program

address;

P<23:16> maps to the destination byte when

byte select = 0;

The destination byte will always be = 0 when

byte select = 1.

4. TBLWTH: Table W ri te High (refer to Section 6.0

“Flash Program Memory” for details on Flash

Programming).

FIGURE 3-3: PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(Read as ‘0’).

TBLRDL.W

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

dsPIC30F5015/5016

FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MSB)

3.1.2 DATA ACCESS FROM PROGRAM

MEMORY USING PROGRAM

SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word program space page. This

provides transparent access of stored constant data

from X data space, without the need to use special

instructions (i.e., TBLRDL/H, TBLWTL/H instructions).

Program space access through the data space occurs

if the MSb of the data space EA is set and program

space visibility is enabled, by setting the PSV bit in the

Core Control register (CORCON). The functions of

CORCON are discussed in Section 2.4 “DSP

Engine”.

Data accesses to this area add an additional cycle to

the instruction being executed, since two program

memory fetch es are requ ire d.

Note that the upper half of addressable data space is

always part of the X data space. Therefore, when a

DSP ope ration uses p rogram sp ace mapp ing to acces s

this m em ory reg ion , Y d ata sp ac e s ho uld ty pic al ly co n-

tain state (variable) data for DSP operations, whereas

X data space should typically contain coefficient

(constant) da ta.

Although each dat a sp ace address, 0x8000 and higher ,

maps directly into a corresponding program memory

address (see Figure 3-5), only the lower 16 bits of the

24-bit program word are used to contain the data. The

upper 8 bits shoul d be progra mmed to forc e an illeg al

instruction to maintain machine robustness. Refer

to the “dsPIC30F/33F Programmer’s Reference Man-

ual” (DS70157) for details on instruction encoding.

Note that by incrementing the PC by 2 for each

program memory word, the Least Significant 15 bits of

data space addresses directly map to the Least Signif-

icant 15 bits in the corresponding program space

addresses. The remaining bits are provided by the

Program Space Visibility Page register,

PSVPAG<7:0>, as shown in Figure 3-5.

For instructions which use PSV that are executed

outside a REPEAT loop:

• The following instructions will require one instruc-

tion cycle in addition to the specified execution

time:

-MAC class of instructions with data operand

prefetch

-MOV instr ucti ons

-MOV.D instructions

• All other instructions will require two instruction

cycl es in addition to th e specified execution time

of the instruction.

For instructions that use PSV which are executed

inside a REPEAT loop :

• The follo wing inst ances will re quire two ins truction

cycl es in addition to th e specified execution time

of the instruction:

- Execution in the first iteration

- Execution in the last iteration

- Execution prior to exiting the loop due to an

interrupt

- Execution upon re-entering the loop after an

interr upt is servi ced

• Any other iteration of the REPEAT loop will allow

the instruction, accessing data using PSV, to

execute in a single cycle.

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(Read as ‘0’)

TBLRDH.W

TBLRDH.B (Wn<0> = 1)

TBLRDH.B (Wn<0> = 0)

Note: PSV acc ess is tempo raril y disabl ed durin g

table reads/wr ites.

dsPIC30F5015/5016

FIGURE 3-5: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION

3.2 Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP instruc-

tions), o r as o ne u nified linear a ddre ss ran ge (fo r MC U

instruc tions). The dat a spaces are acces s ed usi ng two

Address Generation Units (AGUs) and separate data

paths.

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key ele me nt of th is archi tec tur e is th at

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent linear

addressing space, X and Y spaces have contiguous

addresses.

When ex ecuting an y instr uctio n other th an one of the

MAC class of instructions, the X block consists of the

64 Kbyte data address space (including all Y

address es). When e xecuting on e of the MAC clas s of

instructions, the X block consists of the 64 Kbyte data

address space excluding the Y address block (for data

reads only). In other words, all other instructions

regard the entire data memory as one composite

address space. The MAC class instructions extract the

Y address space from data space and address it using

EAs sourced from W10 and W11. The remaining X

data space is addressed using W8 and W9. Both

address spaces are concurrently accessed only with

the MAC class instructions.

A data space memory map is shown in Figure 3-6.

Figur e 3-7 s hows a graphi cal s ummar y of h ow X and Y

data spaces are accessed for MCU and DSP

instructions.

23 15 0

PSVPAG(1)

EA<15> =

EA<15> = 1

Data

Space

Data Space Program Space

15 23

0x0000

0x8000

0xFFFF

0x00

0x017FFE

Data Read

Upper Half of Dat a

Space is Mapped

into Program Space

Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address

(i.e., it defines the page in program space to which the upper half of data space is being mapped).

0x001200

Address

Con cat enat i on

BSET CORCON,#2 ; PSV bit set

MOV #0x00, W0 ; Set PSVPAG register

MOV W0, PSVPAG

MOV 0x9200, W0 ; Access program memory location

; using a data space access

0x000100

dsPIC30F5015/5016

FIGURE 3-6: dsPIC30F5015/5016 DATA SPACE MEMORY MAP

0x0000

0x07FE

0x0BFE

0xFFFE

LSB

Address

16 bit s

LSBMSB

MSB

Address

0x0001

0x07FF

0x0BFF

0xFFFF

0x8001 0x8000

Optionally

Mapped

into Program

Memory

0x0FFF 0x0FFE

0x10000x1001

0x0801 0x0800

0x0C01

0x0C00

Near

Data

2 Kbyt e

SFR Space

2 Kbyte

SRAM Space

8 Kbyt e

Space

Unimplemented (X)

X Data

SFR Space

X Data RAM (X)

Y Data RAM (Y)

≈

0x1FFF 0x1FFE

Unimplemented

≈

dsPIC30F5015/5016

FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE

SFR SPACE

(Y SPACE)

X SPACE

SFR SPACE

UNUSED

X SPACE

Y SPACE

UNUSED

Non-MAC Class Ops (Read/Write) MAC Class Ops Read-Only

Indirect EA using any W Indirect EA using W10, W11 Indirect EA using W8, W9

MAC Class Ops (Write)

dsPIC30F5015/5016

3.2.2 DATA SPACES

The X data space is used by all instructions and sup-

ports all addressing modes. There are separate read

and write data buses. The X read data bus is the return

data path for all instructions that view data space as

combined X and Y address space. It is also the X

address space data path for the dual operand read

instructions (MAC class). The X write data bus is the

only write path to data space for all instructions.

The X dat a sp ace also su pports Modulo Address ing for

all instructions, subject to addressing mode restric-

tions. Bit-Reversed Addressing is only supported for

writes to X data space.

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to pro-

vide two concurrent data read paths. No writes occur

across the Y bus. This class of instructions dedicates

two W register pointers, W10 and W11, to always

address Y data space, independent of X data space,

whereas W8 and W9 always address X data space.

Note that during accumulator write back, the data

address space is consi dere d a c om bin ati on of X and Y

data spaces, so the write occurs across the X bus.

Consequently, the write can be to any address in the

entire data space.

The Y data space can only be used for the data

prefetch operation associated with the MAC class of

instructions. It also supports Modulo Addressing for

automat ed c irc ul ar bu f fe r s. Of c ours e, all othe r ins tru c-

tions ca n access the Y dat a address sp ace thro ugh the

X data path, as part of the composite linear space.

The boundary between the X and Y data spaces is

defined as shown in Figure 3-6 and is not user

prog rammabl e. Should an EA poi nt to data outs ide its

own assigned address space, or to a location outside

physical memory, an all-zero word/byte will be

returned. For example, although Y address space is

visible by all non-MAC instructions using any address-

ing mode , an attem pt by a MAC in structi on to fetc h dat a

from that space, using W8 or W9 (X space pointers),

will return 0x0000.

All effective addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space

address range is 64 Kbytes or 32K words.

3.2.3 DATA SPACE WIDTH

The core data width is 16 bits. All internal registers are

organ ized as 16-bit wide words. Data space mem ory is

organized in byte addressable, 16-bit wide blocks.

3.2.4 DATA AL IGNMENT

To help maintain backward compatibility with

PICmicro® devices and improve data space memory

usage ef ficiency, the dsPIC30F instructi on set support s

both word and byte operations. Data is aligned in data

memory and regi sters as words, b ut all da ta sp ace EA s

resolve to bytes. Data byte re ads will rea d the comp lete

word, whi ch contain s the byte, using the LSb of any EA

to determine which byte to select. The selected byte is

placed onto the LSB of the X data path (no byte

acces ses are possible fro m the Y data pa th as the MAC

class of instruction can only fetch words). That is, data

memory and registers are organized as two parallel

byte wide entities with shared (word) address decode,

but separate write lines. Data byte writes only write to

the corresponding side of the array or register which

matches the byte address.

As a conse quence of this byte access ibility, all ef fective

address c alc ul atio ns (in cl udi ng tho se ge nera ted by th e

DSP operations, which are restricted to word-sized

data) a re internally scale d to step through word-aligned

memory. For example, the core would recognize that

Post-Modified Register Indirect Addressing mode,

[Ws++], will result in a value of Ws + 1 for byte

operations and Ws + 2 for word operations.

All word accesses must be al igned to an even a ddress.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. Should a

misaligned read or write be attempted, an address

error trap will be generated. If the error occurred on a

read, the instruction u nderway is completed, wh ereas if

it occurred on a write, the instruction will be executed

but the write will not occur. In either case, a trap will

then be executed, allowing the system and/or user to

examine the machine state prior to execution of the

address fault.

FIGURE 3-8: DATA ALIGNMENT

TABLE 3-2: EFFECT OF INVALID

MEMORY ACCESSES

Attempted Operation Data Returned

EA = an unimplemented address 0 x0000

W8 or W9 used to access Y data

spa ce in a MAC instru ction 0x0000

W10 or W11 used to access X

data space in a MAC instruction 0x0000

15 8 7 0

0001

0003

0005

0000

0002

0004

Byte 1 Byte 0

Byte 3 Byte 2

Byte 5 Byte 4

LSBMSB

dsPIC30F5015/5016

All byte loads into any W register are loaded into the

LSB. The MSB is not modified.

A sign-extend (SE) instruction is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

zero-extend (ZE) instruction on the appropriate

address.

Although m os t i ns truc tio ns are cap able of op era t ing o n

word or byte data sizes, it should be noted that some

instructions, including the DSP instructions, operate

only on words .

3.2.5 NEAR DATA SPACE

An 8 Kbyte ‘near’ data space is reserved in X address

memory space between 0x0000 and 0x1FFF, which is

directly add res sab le via a 13-bit absolut e address field

within all memory direct instructions. The remaining X

address space and all of the Y address space is

address able indirec tly. Additional ly, the whole of X da ta

space is addressable using MOV instructions, which

support memory direct addressing with a 16-bit

address field.

3.2.6 SOFTWARE STACK

The dsPI C DSC de vice c ontain s a softwa re st ack. W15

is used as the Stack Pointer.

The Stack Pointer always points to the first available

free word and grows from lower addresses towards

higher ad dresses. It pre-dec rements for stack pop s and

post-increments for stack pushes, as shown in

Figure 3-9. Note that for a PC push during any CALL

instruc tio n, the M SB o f t he PC i s ze ro-ex te nde d b efo re

the push, ensuring that the MSB is always clear.

There is a Stack Pointer Limit register (SPLIM) associ-

ated with the Stack Pointer. SPLIM is uninitialized at

Reset. As is t he case f or t h e Stack Point er, SPLIM< 0>

is forced to ‘0’, because all stack operations must be

word-aligned. Whenever an Effective Address (EA) is

generated using W15 as a source or destination

pointer, the address thus generated is compared with

the valu e i n SPL IM. If the cont ents of the Stack Po int er

(W15) and the SPLIM register are equal and a push

operatio n is perform ed, a st ack error trap will no t occur.

The stack error trap will occur on a subsequent push

operation. Thus, for example, if it is desirable to cause

a stack error trap when the stack grows beyond

address 0x2000 in RAM, initialize the SPLIM with the

value, 0x1FFE.

Similarl y, a S tack Po inter un derflow ( sta ck erro r) trap i s

generated when the Stack Pointer address is found to

be less than 0x0800, thus preventing the stack from

interfering with the Special Function Register (SFR)

space.

A write to the SPLIM register should not be immediately

follow ed by an ind irec t read ope rati on usi ng W15.

FIGURE 3-9: CALL STACK FRAME

Note: A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Towards

Higher Address

PUSH: [ W 15++]

POP: [--W15]

0x0000

PC<22:16>

dsPIC30F5015/5016

TABLE 3-3: CORE REGISTER MAP

SFR Name Address

(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

W0 0000 W0/WREG 0000 0000 0000 0000

W1 0002 W1 0000 0000 0000 0000

W2 0004 W2 0000 0000 0000 0000

W3 0006 W3 0000 0000 0000 0000

W4 0008 W4 0000 0000 0000 0000

W5 000A W5 0000 0000 0000 0000

W6 000C W6 0000 0000 0000 0000

W7 000E W7 0000 0000 0000 0000

W8 0010 W8 0000 0000 0000 0000

W9 0012 W9 0000 0000 0000 0000

W10 0014 W10 0000 0000 0000 0000

W11 0016 W11 0000 0000 0000 0000

W12 0018 W12 0000 0000 0000 0000

W13 001A W13 0000 0000 0000 0000

W14 001C W14 0000 0000 0000 0000

W15 001E W15 0000 1000 0000 0000

SPLIM 0020 SPLIM 0000 0000 0000 0000

ACCAL 0022 ACCAL 0000 0000 0000 0000

ACCAH 0024 ACCAH 0000 0000 0000 0000

ACCAU 0026 Sign-Extension (ACCA<39>) ACCAU 0000 0000 0000 0000

ACCBL 0028 ACCBL 0000 0000 0000 0000

ACCBH 002A ACCBH 0000 0000 0000 0000

ACCBU 002C Sign-Extension (ACCB<39>) ACCBU 0000 0000 0000 0000

PCL 002E PCL 0000 0000 0000 0000

PCH 0030 — — — — — — — — —PCH

0000 0000 0000 0000

TBLPAG 0032 — — — — — — — —TBLPAG

0000 0000 0000 0000

PSVPAG 0034 — — — — — — — —PSVPAG

0000 0000 0000 0000

RCOUNT 0036 RCOUNT uuuu uuuu uuuu uuuu

DCOUNT 0038 DCOUNT uuuu uuuu uuuu uuuu

DOSTARTL 003A DOSTARTL 0uuuu uuuu uuuu uuu0

DOSTARTH 003C — — — — — — — — —DOSTARTH

0000 0000 0uuu uuuu

DOENDL 003E DOENDL 0uuuu uuuu uuuu uuu0

DOENDH 0040 — — — — — — — — — DOENDH 0000 0000 0uuu uuuu

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 0000 0000 0000

CORCON 0044 — — — US EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0000 0000 0010 0000

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F5015/5016

MODCON 0046 XMODEN YMODEN —— BWM<3:0> YWM<3:0> XWM<3:0> 0000 0000 0000 0000

XMODSRT 0048 XS<15:1> 0 uuuu uuuu uuuu uuu0

XMODEND 004A XE<15:1> 1 uuuu uuuu uuuu uuu1

YMODSRT 004C YS<15:1> 0 uuuu uuuu uuuu uuu0

YMODEND 004E YE<15:1> 1 uuuu uuuu uuuu uuu1

XBREV 0050 BREN XB<14:0> uuuu uuuu uuuu uuuu

DISICNT 0052 —— DISICNT<13:0> 0000 0000 0000 0000

TABLE 3-3: CORE REGISTER MAP (CONTINUED)

SFR Name Address

(Home) Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.

dsPIC30F5015/5016

NOTES:

dsPIC30F5015/5016

4.0 ADDRESS GENERATOR UNITS

The dsPIC DSC core contains two independent

Address Generator Units (AGU): the X AGU and Y

AGU. The Y AGU supports word-sized data reads for

the DSP MAC class of instr uctions o nly . Th e dsPIC DSC

AGUs support three types of data addressing:

• Linear Addressing

• Modulo (Circular) Addressing

• Bit-Revers ed Addre ss in g

Linear and Modulo Data Addressing modes can be

applied to data space or program space. Bit-Reversed

Addressi ng is on ly appli cable to data s pace a ddresses .

4.1 Instruction Addressing Modes

The addressing modes in Table 4-1 form the basis of

the addressing modes optimized to support the specific

features of individual instructions. The addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

4.1.1 FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field

(f) to directly address dat a present in the firs t 8192 bytes

of data memory (near data space). Most file register

instructions employ a working register W0, which is

denoted as WREG in these instructions. The des tination

is typically either the same file register, or WREG (with

the exception of the MUL instruction), which writes the

result to a register or register pair. The MOV instruction

allows additional flexibility and can access the entire

data sp ace during file register operation.

4.1.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where O pe rand 1 is alw a ys a work in g reg ister (i.e., the

address ing mode can only be Reg ister Direct), whi ch is

referred to as Wb. Operand 2 can be a W register,

fetched from data memory, or a 5-bit literal. The result

location can be either a W register or an address

location. The following addressing modes are

supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-bit or 10-bit Literal

TABLE 4-1: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Note: This data sheet summarizes features of this

group of ds PIC30 F devi ces and is not intende d to be

a complete reference source. For more information

on the CPU, peripherals, register descriptions and

general device functionality, refer to the “dsPIC30F

Family Reference Manual” (DS70046). For more

information on the device instruction set and pro-

gramming, refer to the “dsPIC30F/33F Program-

mer’s Reference Manual” (DS70157).

Note: Not all instructions sup port all the address-

ing modes given above. Individual

instructions may support different subsets

of these addressing modes.

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.

decremented) by a constant value.

to form the EA.

dsPIC30F5015/5016

4.1.3 MOVE AND ACCUMULATOR

INSTRUCTIONS

Move instructions and the DSP Accumulator class of

instructions provide a greater degree of addressing

flexibility than other instructions. In addition to the

addressing modes supported by most MCU instruc-

tions, Move and Accumulator instructions also support

mode, also referred to as Register Indexed mode.

In summary, the following addressing modes are

supported by Move and Accumulator instructions:

• Register Direc t

• Register Indi rec t

• Register Indi rec t Post-Mod ifi ed

• Register Indi rec t Pre- Mo dif ied

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

4.1.4 MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also

referred to a s MAC instruction s, utilize a si mplified se t of

addressing modes to allow the user to effectively

manipulate the data pointers through Register Indirect

tables.

The two source operand prefetch registers must be a

member of the set {W8, W9, W10, W11}. For data

reads, W8 and W9 will always be directed to the X

RAGU and W10 and W11 will a lways be dire cted to the

Y AGU. The ef fective addresses generated (before and

after modification) must, therefore, be valid addresses

within X data space for W8 and W9 and Y data space

for W10 and W11.

In summary, the following addressing modes are

supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-Modified by 2

• Register Indirect Post-Modified by 4

• Register Indirect Post-Modified by 6

• Register Indirect with Register Offset (Indexed)

4.1.5 OTHER INSTRUCTIONS

Besides the various addressing mo des outlin ed above,

some i nstructio ns use li teral con sta nts of various sizes.

For example, BRA (branch) instructions use 16-bit

signed l iterals to spe cify the branch de stination dire ctly ,

whereas the DISI instruction uses a 14-bit unsigned

literal fiel d. In som e in stru cti ons , suc h as ADD Acc, the

source of an operand or result is implied by the opc ode

it self. Cert ain opera tions, such as NOP, do not have any

operands.

4.2 Modulo Addressing

Modulo Addressing is a method of providing an auto-

mated means to support circular data buffers using

hardware. The objective is to remove the need for

software to perform data address boundary checks

when executing tightly looped code, as is typical in

many DSP algorithms.

Modulo Addressing can operate in either data or pro-

gram space (since the data pointer mechanism is essen-

tially the same for both). One circular buffer can be

supported in each of the X (which also provides the

pointers into program space) and Y data spaces. Mod-

ulo Addressing can operate on any W register pointer.

However , it is not advisable to use W14 or W15 for Mod-

ulo Addressing, since these two registers are used as

the St ack Frame Pointer a nd Stack Pointer,

respectively.

In general, any particular circular buffer can only be

configu red to o perate in one direc tion, as t here are cer-

tain restrictions on the buffer start address (for incre-

menting buffers) or end address (for decrementing

buffers) based upon the direction of the buffer.

The only exception to the usage restrictions is for buff-

ers which have a power-of-2 length. As these buffers

satisfy the start and end address criteria, they may

operate in a Bidirectional mode, (i.e., address bound-

ary checks will be performed on both the lower and

upper address boundaries).

Note: For the MOV instructions, the addressing

mode specified in the instruction can differ

for the source and destination EA. How-

ever, the 4-bit Wb (Regi ste r Offset) field is

shared between both source and

destination (but typically only used by

one).

Note: Not all instructions su pport all the address-

ing modes given above. Individual

instructions may support different subsets

of these addressing modes.

Note: Register Indirect with Register Offset

Addressing is only available for W9 (in X

spa ce) and W11 (in Y space).

dsPIC30F5015/5016

4.2.1 START AND END ADDRESS

The Modulo Addressing scheme requires that a

starting and an ending address be specified and

loaded in to the 16-bi t M od ulo Bu f fe r Address re gisters :

XMODSRT, XMODEND, YMODSRT and YMODEND

(see Table 3-3).

The length of a circular buffer is not directly specified.

It is determined by the difference between the

corresp onding st art and end ad dress es. Th e ma ximu m

possible length of the circular buffer is 32K words

(64 Kbytes).

4.2.2 W ADDRESS REGISTER

SELECTION

The Mod ulo an d Bi t-Rev ers ed Add ress in g Co ntro l re g-

ister, MODCON<15:0>, contains enable flags, as well

as a W re gister field t o specify the W Address registers .

The XWM and YWM fields select which registers will

operate with Modulo Addressing. If XWM = 15,

X RAGU and X WAGU Modulo Addressing are

disabled. Similarly, if YWM = 15, Y AGU Modulo

Addressi ng is disab led .

The X Address Space Pointer W register (XWM) to

which Modulo Addressing is to be applied, is stored in

MODCON<3 :0> (see Table 3-3). Modulo Add ressin g is

enabled for X data sp ace when XWM is set to any v alue

other than 15 and the XMODEN bit is set at

MODCON<15>.

The Y Address Space Pointer W register (YWM) to

which Modulo Addressing is to be applied, is stored in

MODCON<7:4>. Modulo Addressing is enabled for Y

data space when YWM is set to any value other than

15 and the YMODEN bit is set at MODCON<14>.

FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE

Note: Y-space Modulo Addressing EA calcula-

tions assume word-sized data (LSb of

ever y EA is always clear ).

0x1100

0x1163

Start Addr = 0x1100

End Addr = 0x1163

Length = 0x003 2 w ords

Byte

Address MOV #0x1100,W0

MOV W0, XMODSRT ;set modulo start address

MOV #0x1163,W0

MOV W0,MODEND ;set modulo end address

MOV #0x8001,W0

MOV W0,MODCON ;enable W1, X AGU for modulo

MOV #0x0000,W0 ;W0 holds buffer fill value

MOV #0x1110,W1 ;point W1 to buffer

DO AGAIN,#0x31 ;fill the 50 buffer locations

MOV W0, [W1++] ;fill the next location

AGAIN: INC W0,W0 ;increment the fill value

dsPIC30F5015/5016

4.2.3 MODULO ADDRESSING

APPLICABILITY

Modulo Addressing can be applied to the Effective

Address (EA) calculation associated with any W regis-

ter. It is important to realize that the addres s bou ndaries

check for addresses less than or greater than the upper

(for incrementing buffers) and lower (for decrementing

buffers) boundary addresses (not just equal to). Address

changes may, therefore, jump beyond boundaries and

still be adjusted correctly.

4.3 Bit-Reversed Addressing

Bit-Reversed Addressing is intended to simplify data

reordering for radix-2 FFT al gorithms. It is supported by

the X AGU for data wr ites only.

The modifier , which may be a constant value or register

contents, is regarded as having its bit order reversed.

The addres s sourc e and dest inat ion are ke pt in norma l

order. Thus, the only operand requiring reversal is the

modifier.

4.3. 1 BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-Reversed Addressing is enabled when:

1. BWM (W register selection) in the MODCON

not be accessed using Bit-Reversed Addressing)

and

2. the BREN bit is set in the XBREV register and

3. the addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

If the le ng th of a Bi t- R ev ers ed bu ffer is M = 2N bytes,

then the last ‘N’ bits of the data buffer start address

must be zero s.

XB<14:0> is the Bit-Reversed Address modifier or

‘pivot po int’ which is typ ic all y a consta nt. In t he case of

an FFT computation, its value is equal to half of the FFT

dat a buffer size.

When enabled, Bit-Reversed Addressing will only be

executed for Register Indirect with Pre-Increment or

Post-Increment Addressing and word-sized data writes.

It will not function for any other addressing mode or for

byte-sized data, and normal addresses will be gener-

ated instead. When Bit-Reversed Addressing is active,

the W address pointer will always be added to the

address modifier (XB) and the offset associated with the

addition, as word-si zed data is a requirement, th e LSb of

the EA is ignored (and always cle ar).

If Bit-Reversed Addressing has already been enabled

by setting the BREN (XBREV<15>) bit, then a write to

the XBREV register should not be immediately followed

by an indirect read operation using the W register that

has been designated as the Bit-Reversed Pointer.

FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE

Note: The m odulo correcte d Effective Address is

written back to the re giste r only when Pre-

Modify or Post-Modify Addressing mode is

used to compute the Effective Address.

When an address offset (e.g., [W7 + W2])

is used , m odu lo a dd res s c orrec ti on i s p er-

formed, but the contents of the register

remains unchanged.

Note: All bit-reversed EA calculations assume

word-sized data (LSb of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

Note: Modulo Addressing and Bit-Reversed

Addressing should not be enabled

together. In the event that the user

attempt s to do this , Bit-Reversed Addr ess-

ing wil l assume priori ty when activ e for the

X WAGU, and X WAGU Modulo Address-

ing will be disabled. However, Modulo

Addressing will continue to function in the

X RAGU.

b3 b2 b1 0

b2 b3 b4 0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16-word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4

b11 b10 b9 b8

b15 b14 b13 b12

Sequenti al Addre ss

Pivot Point

dsPIC30F5015/5016

TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Normal Address Bit-Reversed Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0000 00000 0

0001 11000 8

0010 20100 4

0011 31100 12

0100 40010 2

0101 51010 10

0110 60110 6

0111 71110 14

1000 80001 1

1001 91001 9

1010 10 0101 5

1011 11 1101 13

1100 12 0011 3

1101 13 1011 11

1110 14 0111 7

1111 15 1111 15

Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value

4096 0x0800

2048 0x0400

1024 0x0200

512 0x0100

256 0x0080

128 0x0040

64 0x0020

32 0x0010

16 0x0008

80x0004

40x0002

20x0001

dsPIC30F5015/5016

NOTES:

dsPIC30F5015/5016

5.0 INTERRUPTS

The dsPIC30F5015/5016 has 36 interrupt sources and

4 processor exceptions (traps), which must be

arbitrated based on a priority scheme.

The CPU is responsible for reading the Interrupt

Vector Table (IVT) and transferring the address con-

tained in the interrupt vector to the program counter.

The interrupt vector is transferred from the program

data bus into the program counter, via a 24-bit wide

multiplexer on the input of the program counter.

The Interrupt Vector Table (IVT) and Alternate Inter-

rupt Vector Table (AIVT) are placed near the begin-

ning of program memory (0x000004). The IVT and

AIVT are shown in Figure 5-1.

The interrupt controller is responsible for pre-

processing the interrupts and processor exceptions,

prior to their being presented to the processor core.

The peripheral interrupts and traps are enabled, priori-

tized and co ntrolle d using cen tral ized Specia l Functio n

Registers:

• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>

All Interrupt Request Flags are maintained in

these three registers. The flags are set by their

respective peripherals or external signals, and

they are cleared via software.

• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>

All Interrupt Enable Control bits are maintained in

these three registers. These control bits are used

to individually enable interrupts from the

peripherals or external signals.

• IPC0<15:0>... IPC11<7:0>

The user assignable priority level associated with

each of these 44 interrupts is held centrally in

these twelve registers.

• IPL<3:0>

The current CPU priority level is explicitly stored

in the IPL bi ts. IPL<3> i s p res en t in the C ORCO N

STATUS register (SR) in the processor core.

• INTCON1< 15: 0>, IN TCO N2<15:0>

Global interru pt co ntrol fu nctio ns are deriv ed from

these two registers. INTCON1 contains the con-

trol and status flags for the processor exceptions.

The INTCON2 r egister controls the external inter-

rupt request signal behavior and the use of the

alternate vector table.

All interrupt sources can be user assigned to one of

seven priority levels, 1 through 7, via the IPCx

registers. Each interrupt source is associated with an

interrupt vector, as shown in Table 5-1. Levels 7 and 1

represent the highest and lowest maskable priorities,

respectively.

If the NSTDIS bit (INTCON1<15>) is set, nesting of

interrupts is prev en ted . Thus, if a n i nte rrupt is c urrentl y

being serviced, processing of a new interrupt is pre-

vented, even if the new interrupt is of higher priority

than the one currently being serviced.

Certain interrupts have specialized control bits for

features like edge or level triggered interrupts, inter-

rupt-on-change, etc. Control of these features remains

within the peripheral module which generates the

interrupt.

The DISI instruction can be used to disable the

processing of interrupts of priorities 6 and lower for a

certain number of instructions, during which the DISI bit

(INTCON2<14>) remains set.

When an interrupt is serviced, the PC is loaded with the

address stored in the vector location in program

memory that corresponds to the interrupt. There are 63

different vectors within the IVT (refer to Figure 5-2).

These vectors are contained in locations 0x000004

through 0x0000FE of program memory (refer to

Figure 5-2). These locations contain 24-bit addresses,

and in order to preserve robustness, an address error

trap will take place should the PC attempt to fetch any

of these words during normal execution. This prevents

execution of random data as a result of accidentally

decrementing a PC into vector space, accidentally

mappin g a da t a sp ac e add ress into v ector sp ac e or th e

PC rolling over to 0x000000 after reaching the end of

implemented program memory space. Execution of a

GOTO instruc t io n to this ve ctor spac e w il l al so gen erate

an address error trap.

Note: This data sheet summarizes features of this

group of ds PIC30 F devi ces and is not intende d to be

a complete reference source. For more information

on the CPU, peripherals, register descriptions and

general device functionality, refer to the “dsPIC30F

Family Reference Manual” (DS70046). For more

information on the device instruction set and pro-

gramming, refer to the “dsPIC30F/33F Program-

mer’s Reference Manual” (DS70157).

Note: Interru pt flag bit s get set when an interru pt

conditi on occ urs, regar dless o f the s tate of

its corresponding enable bit. User

software should ensure the appropriate

interrupt flag bits are clear prior to

enabling an interrupt.

Note: Assigning a priority level of 0 to an inter-

rupt source is equivalent to disabling that

interrupt.

Note: The IPL bits become read-only whenever

the NSTDIS bit has been set to ‘1’.

dsPIC30F5015/5016

5.1 Interrupt Priority

The user a ssig nab le Interrupt Pr iori ty (I P<2:0 >) bi t s for

each ind ividual interrupt source are located in the Least

Significant 3 bits of each nibble within the IPCx regis-

ter(s). Bit 3 of each nibble is not used and is read as a

‘0’. These bits define the priority level assigned to a

particular interrupt by the user.

Since more than one interrupt request source may be

assigned to a specific user specified priority level, a

means is provided to assign prio rity within a given level.

This method is called “Natural Order Priority”.

Natural Order Priority is determined by the position of

an interrupt in the vector table, and only affects

interrupt operation when multiple interrupts with the

same user-assigned priority become pending at the

same time.

Table 5-1 lists the interrupt numbers and interrupt

sources for the dsPIC DSC devices and their

associated vector numbers.

The ability for the user to assign every interrupt to one

of seven pri ority levels means that the user can as sig n

a very high overall priority level to an interrupt with a

low natural order priority.

TABLE 5-1: INTERRUPT VECTOR TABLE

Note: The user-selectable priority levels start at

0, as th e l ow es t p riori ty and level 7 , as th e

highest priority.

Note 1: The Natural Order Priority scheme has 0

as the highest priority and 53 as the

lowest priority.

2: The Natural Order Priority number is the

same as the INT number.

INT

Number Vector

Number Interrupt Source

Highest Natural Order Priority

0 8 IN T 0 – Extern a l Interr u pt 0

1 9 IC1 – Input Capture 1

2 10 OC1 – Output Compare 1

3 11 T1 – Timer1

4 12 IC2 – Input Captur e 2

5 13 OC2 – Output Compare 2

6 14 T2 – Tim er2

7 15 T3 – Tim er3

8 16 SPI1

9 17 U1RX – UART1 Receiver

10 18 U1TX – UART1 Transmit ter

11 19 ADC – ADC Convert Done

12 20 NVM – NVM Write Complete

13 21 SI2C – I2C™ Slave In terr up t

14 22 MI2C – I 2C Master Interrupt

15 23 Inpu t Change Int er ru pt

16 24 INT1 – Ex te rn al In te rrupt 1

17 25 Reserved

18 26 Reserved

19 27 OC3 – Output Compare 3

20 28 OC4 – Output Compare 4

21 29 T4 – Tim er4

22 30 T5 – Tim er5

23 31 INT2 – Ex te rn al In te rrupt 2

24 32 Reserved

25 33 Reserved

26 34 SPI2

27 35 C1 – Combined IRQ for CAN1

28 36 IC3 – I nput Captur e 3

29 37 IC4 – I nput Captur e 4

30 38 Reserved

31 39 Reserved

32 40 OC5 – Output Compare 5

33 41 OC6 – Output Compare 6

34 42 OC7 – Output Compare 7

35 43 OC8 – Output Compare 8

36 44 INT3 – Ex te rn al In te rrupt 3

37 45 INT4 – Ex te rn al In te rrupt 4

38 46 Reserved

39 4 7 PWM – PWM Period Match

40 48 QEI – QEI Interrupt

41 49 Reserved

42 50 Reserved

43 51 FLTA – PW M Fault A

44 52 FLTB – PWM Fault B

45-53 53-61 Reserved

Lowest Natural Order Priority

dsPIC30F5015/5016

5.2 Reset Sequence

A Reset is not a true exception because the interrupt

controller is not involved in the Reset process. The

process or initi alizes its registers i n respon se to a Reset

which forces the PC to zero. The processor then begins

program execution at location 0x000000. A GOTO

instruction is stored in the first program memory loca-

tion, im media tel y follo wed by th e addres s t arget for th e

GOTO instruction. The processor executes the GOTO to

the speci f ie d add res s and then begi ns op erat ion at the

specified target (start) address.

5.2.1 RESET SOURCES

There are 6 sources of error which will cause a device

Reset.

• Watchdog Time-out:

The Watchdog has timed out, indicating that the

process or is no longer ex ecu tin g the corre ct flo w

of code.

• Uninitialized W Register Trap:

An attempt to use an uninitialized W register as

an Address Pointer will cause a Reset.

• Illegal Instruction Trap:

Attempted execution of any unused opcodes will

result in an illegal instruction trap. Note that a

fetch of an illegal instruction does not result in an

illegal instruction trap if that instruction is flushed

prior to execution due to a flow change.

• Brown-out Reset (BOR):

A momentary dip in the power supply to the

device has been detected which may result in

malfunction.

• Trap Lockout:

Occurrence of multiple trap condit ions

simultaneously will cause a Reset.

5.3 Traps

Traps can be considered as non-maskable interrupts

indicating a software or hardware error, which adhere

to a predefined priority, as shown in Figure 5-1. They

are intended to provide the user a means to correct

errone ous o pera tio n d urin g debug and w he n o pera tin g

within the application.

Note that many of these trap conditions can only be

detected when th ey occur. Conseque ntly, the ques tion-

able instruction is allowed to complete prior to trap

exception processing. If the user chooses to recover

from the error, the result of the erroneous action that

caused the trap may have to be corrected.

There are 8 fixed priority levels for traps: Level 8

through Level 15, which means that IPL3 is always set

during pr ocessing of a trap.

If the use r is not curren tly executing a trap, and set s the

IPL<3:0> bits to a value of ‘0111’ (Level 7), then all

interr upts are disabled, b ut traps c an still b e processed.

5.3.1 TRAP SOURCES

The following traps are provided with increasing

priority. However, since all traps can be nested, priority

has lit tle ef f e ct .

Math Error Trap:

The math error trap executes under the following four

circumstances:

1. Should an attempt be made to divide by zero,

the divide operation will be aborted on a cycle

boundary and the trap taken.

2. If enabled, a math error trap will be taken when

an ar ithmetic operat ion on either Accum ul ato r A

or B causes an overflow from bit 31 and the

Accumulator Guard bits are not utilized.

3. If enabled, a math error trap will be taken when

an ar ithmetic operat ion on either Accum ul ato r A

or B causes a catastrophic overflow from bit 39

and all saturation is disabled.

4. If the shift amount specified in a shift instruction

is greater than the maximum allowed shift

amount, a trap will occur.

Note: If the user does not intend to take correc-

tive action in the event of a trap error

condition, these vectors must be loaded

with the address of a default handler that

simply contains the RESET instruction. If,

on the other hand, one of the vectors

containing an invalid address is called, an

address error trap is generated.

dsPIC30F5015/5016

Address Error Trap:

This trap is initiated when any of the following

circumstances occurs:

1. A misaligned data word access is attempted.

2. A data fetch from unimplemented data memory

location is attempted.

3. A data access of an unimplemented program

memory location is attempted.

4. An instruction fetch from vector space is

attempted.

5. Execution o f a “BRA #literal” instruct ion or a

“GOTO #literal” ins truc ti on, w he re literal

is an u nimplem ented pr ogram me mory addr ess.

6. Executing instructions after modifying the PC to

point to unimplemented program memory

addresses. The PC may be modified by loading

a value into the stack and executing a RETURN

instruction.

Stack Error Trap:

This trap is initiated under the following conditions:

1. The Stack Pointer is loaded with a value which

is greater than the (user-programmable) limit

value written into the SPLIM register (stack

overflow).

2. The Stack Pointer is loaded with a value which

is less than 0x0800 (simple stack underflow).

Oscillator Fail Trap:

This trap is initiated if the external oscillator fails and

operation becomes reliant on an internal RC backup.

5.3.2 HARD AND SOFT TRAPS

It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack

write to an overflowed address). In such a case, the

fixed priority shown in Figure 5-2 is implemented,

whic h may requir e the user t o check if oth er traps are

pending in order to completely correct the Fault.

‘Soft’ traps incl ude exceptions of priority lev el 8 through

level 11, inclusive. The arithmetic error trap (level 11)

falls into this category of traps.

‘Hard’ traps include exceptions of priority level 12

through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14)

traps fall into this category.

Each hard trap that occurs must be Acknowledged

before code execution of any type may continue. If a

lower priority hard trap occurs while a higher priority

trap is pending, acknowledged, or is being processed,

a hard trap conflict will occur.

The device is automatically reset in a hard trap conflict

condition. The TRAPR Status bit (RCON<15>) is set

when the Reset occurs, so that the condition may be

detected in software.

FIGURE 5-1: TRAP VECTORS

Note: In the MAC class of instructions, wherein

the data space is split into X and Y data

space, unimplemented X space includes

all of Y space, and unimplemented Y

space includes all of X space.

Address Error Trap Vector

Oscillator Fail Trap Vector

Stack Error T rap Vector

Reserv ed Vector

Math Error Trap Vector

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Reserv ed Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

Math Error Trap Vector

Decreasing

Priority

0x000000

0x000014

Reserved

Stack Error T rap Vector

Reserv ed Vector

Interrupt 0 Vector

Interrupt 1 Vector

—

Interrupt 52 Vector

Interrupt 53 Vector

IVT

AIVT

0x000080

0x00007E

0x0000FE

Reserved

0x000094

Reset - GOTO Instruction

Reset - GOTO Address 0x000002

Reserved 0x000082

0x000084

0x000004

Reserv ed Vector

dsPIC30F5015/5016

5.4 Interrupt Sequence

All inte rrupt event flags are sampled in the be ginning of

each instruction cycle by the IFSx registers. A pending

Interrupt Request (IRQ) is indicated by the flag bit

being equal to a ‘1’ in an IFSx register. The IRQ will

cause an interrupt to occur if the corresponding bit in

the Interrupt Enable (IECx) register is set. For the

remainder of the instruction cycle, the priorities of all

pending interrupt requests are evaluated.

If there is a pending IRQ with a priority level greater

than the current processor priority level in the IPL bits,

the processor will be interrupted.

The pr ocessor then st acks the curren t program counter

and the low byte of the processor STATUS register

(SRL), as shown in Figure 5-2. The low byte of the

ST ATUS register cont ains the processor pri ority level at

the time prior to the beginning of the interrupt cycle.

The pr ocessor the n loads t he priority level fo r this int er-

rupt into the STATUS register. This action will disable

all lower priority interrupts until the completion of the

Interr u pt Service R outine.

FIGURE 5-2: INTERRUPT STACK

FRAME

The RETFIE (Return from Interrupt) instruction will

unstack the program counter and STATUS registers to

return the processor to its state prior to the interrupt

sequence.

5.5 Alternate Vector Table

In program memory, the Interrupt Vector Table (IVT) is

follow ed by the Altern ate Interr upt Vector Table (AIVT),

as show n in Fig ure 5-1. Access to the Alternate Vector

Table is provided by the ALTIVT bit in the INTCON2

tion processes will use the alternate vectors instead of

the defa ult vectors. The alternate vectors are org anized

in the same manner as the default vectors. The AIVT

supports emulation and debugging efforts by providing

a means to switch between an application and a

support environment, without requiring the interrupt

vectors to be reprogra mmed. Thi s feature al so enable s

switching between applications for evaluation of

different software algorithms at run time.

If the AIVT is not required, the program memory allo-

cated to the AIVT may be used for other purposes.

AIVT is not a protected section and may be freely

programmed by the user.

5.6 Fast Context Saving

A context saving option is available using shadow reg-

isters. Shadow registers are provided for the DC, N,

OV, Z an d C bits in SR, and the re gisters W 0 through

W3. The shadows are only one level deep. The s hadow

registers are accessible using the PUSH.S and POP.S

inst ruc tion s onl y.

When the processor vectors to an interrupt, the

PUSH.S instruction can be used to store the current

value of the aforementioned registers into their

respective shadow registers.

If an ISR of a certain priority uses the PUSH.S and

POP.S instructions for fast context saving, then a

higher priority IS R shou ld no t inc lude the s ame ins truc-

tions. Users must save the key registers in software

during a lo wer priorit y interru pt if the hi gher pri ority ISR

uses fast context saving.

5.7 External Interrupt Requests

The interrupt controller supports five external interrupt

request signals, INT0-INT4. These inputs are edge

sensitive; they require a low-to-high or a high-to-low

transition to generate an interrupt request. The

INTCON2 register has five bits, INT0EP-INT4EP, that

select the polarity of the edge detection circuitry.

5.8 Wake-up from Sleep and Idle

The interrupt controller may be used to wake-up the

processor from either Sleep or Idle modes, if Sleep or

Idle mode is active when the interrupt is generated.

If an enabled interrupt request of sufficient priority is

received by the interrupt controller, then the standard

interrupt request is presented to the processor. At the

same time, the processor will wake-up from Sleep or

Idle and begin execution of the Interrupt Service

Routine (ISR) needed to process the interrupt request.

Note 1: The user can always lower the priority level

by writing a new value into SR. The Interrupt

Service Routine must clear the interrupt flag

bits in the IFSx reg ister before low ering the

processor interrupt priority in order to avoid

recursive interrup ts.

2: The IPL3 bit ( C O R CO N <3>) is always cl ear

when interrupts are being processed. It is

set only dur i ng executio n of traps.

015

W15 (bef ore CALL

)

W15 (after CALL)

St ac k Gr o w s Towa r ds

Higher Address

PUSH : [W15++]

POP : [--W15]

0x0000

PC<15:0>

SRL IPL3 PC<22:16>

dsPIC30F5015/5016

TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F5015

SFR

Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

INTCON1 0080 NSTDIS ———— OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —0000 0000 0000 0000

INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 0000 0000 0000

IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT0IF 0000 0000 0000 0000

IFS1 0086 —— IC4IF IC3IF C1IF SPI2IF —— INT2IF T5IF T4IF OC4IF OC3IF ——INT1IF

0000 0000 0000 0000

IFS2 0088 — — — FLTBIF FLTAIF —— QEIIF PWMIF — INT4IF INT3IF — — — — 0000 0000 0000 0000

IEC0 008C CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE T3IE T2IE OC2IE IC2IE T1IE OC1IE IC1IE INT0IE 0000 0000 0000 0000

IEC1 008E —— IC4IE IC3IE C1IE SPI2IE —— INT2IE T5IE T4IE OC4IE OC3IE ——INT1IE

0000 0000 0000 0000

IEC2 0090 — — — FLTBIE FLTAIE —— QEIIE PWMIE — INT4IE INT3IE — — — — 0000 0000 0000 0000

IPC0 0094 — T1IP<2:0> —OC1IP<2:0>— IC1IP<2:0> — INT0IP<2:0> 0100 0100 0100 0100

IPC1 0096 — T31P<2:0> — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> 0100 0100 0100 0100

IPC2 0098 —ADIP<2:0>— U1TXIP<2:0> — U1RXIP<2:0> — SPI1IP<2:0> 0100 0100 0100 0100

IPC3 009A — CNIP<2:0> —MI2CIP<2:0>— SI2CIP<2:0> — NVMIP<2:0> 0100 0100 0100 0100

IPC4 009C —OC3IP<2:0>— — — — — — — — — INT1IP<2:0> 0100 0000 0000 0100

IPC5 009E — INT2IP<2:0> — T5IP<2:0> — T4IP<2:0> — OC4IP<2:0> 0100 0100 0100 0100

IPC6 00A0 — C1IP<2:0> — SPI2IP<2:0> — — — — — — — — 0100 0100 0000 0000

IPC7 00A2 — — — — — — — — — IC4IP<2:0> — IC3IP<2:0> 0000 0000 0100 0100

IPC8 00A4 — — — — — — — — — — — — — — — — 0000 0000 0000 0000

IPC9 00A6 —PWMIP<2:0>— — — — — INT41IP<2:0> — INT3IP<2:0> 0100 0000 0100 0100

IPC10 00A8 — FLTAIP<2:0> — — — — — — — — — QEIIP<2:0> 0100 0000 0000 0100

IPC11 00AA — — — — — — — — — — — — — FLTBIP<2:0> 0000 0000 0000 0100

Legend: u = uninitialized bit

Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bi t fields.

dsPIC30F5015/5016

TABLE 5-3: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F5016

SFR

Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State

INTCON1 0080 NSTDIS ———— OVATE OVBTE COVTE — — — MATHERR ADDRERR STKERR OSCFAIL —0000 0000 0000 0000

INTCON2 0082 ALTIVT — — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 0000 0000 0000