General Description
The MAX5541 serial-input, voltage-output, 16-bit monoto-
nic digital-to-analog converter (DAC) operates from a
single +5V supply. The DAC output is unbuffered, result-
ing in a low 0.3mA supply current and low 1LSB offset
error. The DAC output range is 0V to VREF. The DAC
latch accepts a 16-bit serial word. A power-on reset
(POR) circuit clears the DAC output to 0V (unipolar
mode) when power is initially applied.
The 10MHz 3-wire serial interface is SPI™/QSPI™/
MICROWIRE™-compatible and interfaces directly with
optocouplers for applications requiring isolation. The
MAX5541 is available in an 8-pin SO package. For the
1LSB (max) INL version, refer to the MAX541 data sheet.
Applications
High-Resolution Offset and Gain Adjustment
Industrial Process Control
Automated Test Equipment
Data Acquisition Systems
Features
♦Full 16-Bit Performance Without Adjustments
♦+5V Single-Supply Operation
♦Low Power: 1.5mW
♦1µs Settling Time
♦Unbuffered Voltage Output Directly Drives 60kΩ
Loads
♦SPI/QSPI/MICROWIRE-Compatible Serial Interface
♦Power-On Reset Circuit Clears DAC Output to 0V
(unipolar mode)
♦Schmitt Trigger Inputs for Direct Optocoupler
Interface
♦Choose MAX541 as a 1LSB (max) INL Upgrade to
the MAX5541
MAX5541
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
________________________________________________________________ Maxim Integrated Products 1
TOP VIEW
SO
DIN
REF
SCLK
CS
1
2
8
7
VDD
DGND
AGND
OUT
MAX5541
3
4
6
5
Pin Configuration
16-BIT DAC
16-BIT DATA LATCH
SERIAL INPUT REGISTER
CONTROL
LOGIC
MAX5541
REF
CS
DIN
SCLK
AGND
OUT
VDD
DGND
Functional Diagram
19-1572; Rev 2; 6/02
PART
MAX5541CSA
MAX5541ESA -40°C to +85°C
0°C to +70°C
TEMP RANGE PIN-PACKAGE
8 SO
8 SO
Ordering Information
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX5541
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%, VREF = +2.5V, VAGND = VDGND = 0, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to DGND............................................................-0.3V to +6V
CS, SCLK, DIN to DGND..........................................-0.3V to +6V
REF to AGND, DGND..................................-0.3V to (VDD +0.3V)
AGND to DGND.....................................................-0.3V to +0.3V
OUT to AGND, DGND.................................. ............-0.3V to VDD
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SO (derate 5.88mW/°C above +70°C)................471mW
Operating Temperature Ranges
MAX5541CSA .....................................................0°C to +70°C
MAX5541ESA ..................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
(Note 5)
(Note 4)
4.75V ≤VDD ≤5.25V
TA= TMIN to TMAX
TA= +25°C
TA= TMIN to TMAX
TA= +25°C
TA= TMIN to TMAX
(Note 3)
CONDITIONS
kΩ11.5RREF
Reference Input Resistance
V2.0 3.0VREF
Reference Input Range
PSRPower-Supply Rejection LSB±1.0
ROUT
DAC Output Resistance kΩ6.25
Bits16NResolution
ppm/°C±0.1Gain-Error Tempco
LSB
±10
Gain Error (Note 2) ±5
ppm/°C±0.05ZSTC
Zero-Code Tempco
LSBINLIntegral Nonlinearity ±4 ±16
±1
±2
Zero-Code Offset Error
UNITSMIN TYP MAXSYMBOLPARAMETER
ZSE LSB
To ±1
/2LSB of FS, CL= 10pF 1µsOutput Settling Time
VDD = 5V (Note 1)
Guaranteed monotonic Bits±0.5 ±1.0DNLDifferential Nonlinearity
CL= 10pF (Note 6) 25 V/µsSRVoltage Output Slew-Rate
Major-carry transition 10 nVsDAC Glitch Impulse
Code = 0000 hex, CS = VDD,
SCLK = VDIN = 0 to VDD levels 10 nVsDigital Feedthrough
Code = FFFF hex 1MHzBWReference -3dB Bandwidth
DYNAMIC PERFORMANCE—REFERENCE SECTION
Code = 0000 hex, VREF = 1VP-P at 100kHz 1mVP-P
Reference Feedthrough
92 dBSNRSignal-to-Noise Ratio
Code = 0000 hex 75 pFCIN
Reference Input Capacitance
STATIC PERFORMANCE—ANALOG SECTION (RL= ∞)
REFERENCE INPUT
DYNAMIC PERFORMANCE—ANALOG SECTION (RL= ∞)
Code = FFFF hex 120
MAX5541
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%, VREF = +2.5V, VAGND = VDGND = 0, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VREF = +2.5V, VAGND = VDGND = 0, CMOS inputs, TA= TMIN to TMAX, unless otherwise noted.)
Note 1: Refer to the MAX541 for the 1LSB (max) INL version.
Note 2: Gain error tested at VREF = +2.0V, +2.5V, and +3.0V.
Note 3: ROUT tolerance is typically ±20%.
Note 4: Min/max ranges guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 5: Reference input resistance is code dependent, minimum at 8555 hex.
Note 6: Slew-rate value is measured from 0% to 63%.
Note 7: Guaranteed by design. Not production tested.
VIN = 0
(Note 7)
CONDITIONS
mW1.5PDPower Dissipation
mA0.3 1.1IDD
Positive Supply Current
V4.75 5.25VDD
Positive Supply Range
V0.40VH
Hysteresis Voltage
pF10CIN
Input Capacitance
µA±1IIN
Input Current
V0.8VIL
Input Low Voltage
V2.4VIH
Input High Voltage
UNITSMIN TYP MAXSYMBOLPARAMETER
(Note 7)
CONDITIONS
µs20
VDD High to CS Low
(power-up delay)
ns45tCL
SCLK Pulse Width Low
ns45tCH
MHz10fCLK
SCLK Frequency
SCLK Pulse Width High
ns0tDH
DIN to SCLK High Hold
ns40tDS
DIN to SCLK High Setup
ns45tCSS0
CS Low to SCLK High Setup
ns45tCSS1
CS High to SCLK High Setup
ns30tCSH0
SCLK High to CS Low Hold
ns45tCSH1
SCLK High to CS High Hold
UNITSMIN TYP MAXSYMBOLPARAMETER
STATIC PERFORMANCE—REFERENCE SECTIONSTATIC PERFORMANCE—DIGITAL INPUTS
POWER SUPPLY
MAX5541
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD = +5V, VREF = +2.5V, TA = +25°C, unless otherwise noted.)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
-40 -20 0 20 40 60 80 100
MAX5541-01
SUPPLY CURRENT (mA)
SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
0.35
0.34
0.33
0.32
0.31
0.30
0.29
0.28
0123456
MAX5541-02
SUPPLY CURRENT (mA)
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
REFERENCE VOLTAGE (V)
1.0
0.6
0.2
0
-0.2
-0.6
0.8
0.4
-0.4
-0.8
-1.0
-60 -20 20 60 100 140
MAX5541-03
ZERO-CODE OFFSET ERROR (LSB)
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE
TEMPERATURE (°C)
1.0
0.6
0.2
0
-0.2
-0.6
0.8
0.4
-0.4
-0.8
-1.0
-60 -20 20 60 100 140
MAX5541-04
INL (LSB)
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE (°C)
+INL
-INL
1.00
0.50
0.25
0.75
0
-0.25
-0.50
-0.75
-1.00
010k 20k 30k 40k 50k 60k 70k
MAX5541-07
INL (LSB)
INTEGRAL NONLINEARITY
vs. CODE
DAC CODE
1.0
0.6
0.2
0
-0.2
-0.6
0.8
0.4
-0.4
-0.8
-1.0
-60 -20 20 60 100 140
MAX5541-05
DNL (LSB)
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE (°C)
+DNL
-DNL
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-60 -20 20 60 100 140
MAX5541-06
GAIN ERROR (LSB)
GAIN ERROR
vs. TEMPERATURE
TEMPERATURE (°C)
0.25
0.75
0.50
1.00
0
-0.25
-0.50
-0.75
-1.00
010k 20k 30k 40k 50k 60k 70k
MAX5541-08
DNL (LSB)
DIFFERENTIAL NONLINEARITY
vs. CODE
DAC CODE
200
160
120
80
40
0
010k 20k 30k 40k 50k 60k 70k
MAX5541-09
REFERENCE CURRENT (µA)
REFERENCE CURRENT
vs. CODE
DAC CODE
MAX5541
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
_______________________________________________________________________________________ 5
2µs/div
MAJOR-CARRY OUTPUT GLITCH
OUT
AC-COUPLED
100mV/div
CS
5V/div
MAX5541-12
2µs/div
DIGITAL FEEDTHROUGH
CODE = 0000 hex
OUT
AC-COUPLED
50mV/div
SCLK
5V/div
MAX5541-13
Typical Operating Characteristics (continued)
(VDD = +5V, VREF = +2.5V, TA = +25°C, unless otherwise noted.)
Pin Description
+5V Supply VoltageVDD
8
Digital GroundDGND7
Serial-Data InputDIN6
Serial-Clock Input. Duty cycle must be between 40% and 60%.SCLK5
Chip-Select Input
CS
4
Voltage Reference Input. Connect to external +2.5V reference.REF3
Analog GroundAGND2
DAC Output VoltageOUT1
FUNCTIONNAMEPIN
1µs/div
FULL-SCALE STEP RESPONSE
(fSCLK = 10MHz)
MAX5541-10
OUT
500mV/div
CL = 13pF, RL = ∞
400ns/div
FULL-SCALE STEP RESPONSE
(fSCLK = 20MHz)
MAX5541-11
OUT
500mV/div
CL = 13pF, RL = ∞
MAX5541
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
6 _______________________________________________________________________________________
;;
;;
;;;
;;
;;;;
;;
;;
tCSHO tCH
tCSSO tCL
tDH
tDS
tCSH1
tCSS1
CS
SCLK
DIN D15 D14 D0
Figure 1. Timing Diagram
;
;
;;
CS
SCLK
DIN
MSB LSB
D15 D8 D7 D6 D5 D4 D3 D2 D1 D0
DAC
UPDATED
D14 D13 D12 D11 D10 D9
Figure 2. 3-Wire Interface Timing Diagram
Detailed Description
The MAX5541 voltage-output, 16-bit digital-to-analog
converter (DAC) offers 16-bit monotonicity with less
than 1LSB differential linearity error. Serial-data transfer
minimizes the number of package pins required.
The MAX5541 is composed of two matched DAC sec-
tions, with a 12-bit inverted R-2R DAC forming the
twelve LSBs and the four MSBs derived from fifteen
identically matched resistors. This architecture allows
the lowest glitch energy to be transferred to the DAC
output on major-carry transitions. It also decreases the
DAC output impedance by a factor of eight compared
to a standard R-2R ladder, allowing unbuffered opera-
tion in medium-load applications. Figure 1 is the Timing
Diagram.
Digital Interface
The MAX5541 digital interface is a standard 3-wire con-
nection compatible with SPI/QSPI/MICROWIRE inter-
faces. The chip-select input (CS) frames the serial data
loading at the data input pin (DIN). Immediately follow-
ing CSs high-to-low transition, the data is shifted
synchronously and latched into the input register on the
rising edge of the serial-clock input (SCLK). After 16
data bits have been loaded into the serial input regis-
ter, it transfers its contents to the DAC latch on CSs
low-to-high transition (Figure 2). Note that if CS does
not remain low during the entire sixteen SCLK cycles,
data will be corrupted. In this case, reload the DAC
latch with a new 16-bit word.
External Reference
The MAX5541 operates with external voltage refer-
ences from 2V to 3V. The reference voltage determines
the DACs full-scale output voltage.
Power-On Reset
The MAX5541 has a power-on reset (POR) circuit to set
the DACs output to 0V in unipolar mode when VDD is
first applied. This ensures that unwanted DAC output
voltages will not occur immediately following a system
power-up, such as after power loss. In bipolar mode,
the DAC output is set to -VREF.
MAX5541
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
_______________________________________________________________________________________ 7
Applications Information
Reference and Analog Ground Inputs
The MAX5541 operates with external voltage references
from 2V to 3V, and maintains 16-bit performance with
proper reference selection and application. Ideally, the
reference’s temperature coefficient should be less than
0.4ppm/°C to maintain 16-bit accuracy to within 1LSB
over the commercial (0°C to +70°C) temperature range.
Since this converter is designed as an inverted R-2R
voltage-mode DAC, the input resistance seen by the
voltage reference is code dependent. The worst-case
input-resistance variation is from 11.5kΩ(at code 8555
hex) to 200kΩ(at code 0000 hex). The maximum
change in load current for a 2.5V reference is 2.5V/
11.5kΩ= 217µA; therefore, the required load regulation
is 7ppm/mA for a maximum error of 0.1LSB. This implies
a reference output impedance of <18mΩ. In addition,
the impedance of the signal path from the voltage refer-
ence to the reference input must be kept low because it
contributes directly to the load-regulation error.
The requirement for a low-impedance voltage reference
is met with capacitor bypassing at the reference inputs
and ground. A 0.1µF ceramic capacitor with short leads
between REF and AGND provides high-frequency
bypassing. A surface-mount ceramic chip capacitor is
preferred because it has the lowest inductance. An
additional 10µF between REF and AGND provides low-
frequency bypassing. A low-ESR tantalum, film, or
organic semiconductor capacitor works well. Leaded
capacitors are acceptable because impedance is not
as critical at lower frequencies. The circuit can benefit
from even larger bypassing capacitors, depending on
the stability of the external reference with capacitive
loading. If separate force and sense lines are not used,
connect the appropriate force and sense pins together
close to the package.
AGND must also be low impedance, as load-regulation
errors will be introduced by excessive AGND resis-
tance. As in all high-resolution, high-accuracy applica-
tions, separate analog and digital ground planes yield
the best results. Connect DGND to AGND at the AGND
pin to form the “star” ground for the DAC system. For
the best possible performance, always refer remote
DAC loads to this system ground.
Unbuffered Operation
Unbuffered operation reduces power consumption as
well as offset error contributed by the external output
buffer. The R-2R DAC output is available directly at
OUT, allowing 16-bit performance from +VREF to AGND
without degradation at zero-scale. The DAC’s output
impedance is also low enough to drive medium loads
(RL> 60kΩ) without degradation of INL or DNL, only
the gain error is increased by externally loading the
DAC output.
External Output Buffer Amplifier
In unipolar mode, the output amplifier is used in a volt-
age-follower connection. The DAC’s output resistance
is constant and is independent of input code; however,
the output amplifier’s input impedance should still be as
high as possible to minimize gain errors. The DAC’s
output capacitance is also independent of input code,
thus simplifying stability requirements on the external
amplifier.
In single-supply applications, precision amplifiers with
input common-mode ranges including AGND are avail-
able; however, their output swings do not normally
include the negative rail (AGND) without significant per-
formance degradation. A single-supply op amp, such
as the MAX495, is suitable if the application does not
use codes near zero.
Since the LSBs for a 16-bit DAC are extremely small
(38.15µV for VREF = 2.5V), pay close attention to the
external amplifier’s input specification. The input offset
voltage can degrade the zero-scale error and might
require an output offset trim to maintain full accuracy if
the offset voltage is greater than 1/2LSB. Similarly, the
input bias current multiplied by the DAC output resis-
tance (typically 6.25kΩ) contributes to the zero-scale
error. Temperature effects also must be taken into con-
sideration. Over the commercial temperature range, the
offset voltage temperature coefficient (referenced to
+25°C) must be less than 0.42µV/°C to add less than
1/2LSB of zero-scale error. The external amplifier’s
input resistance forms a resistive divider with the DAC
output resistance, which results in a gain error. To con-
tribute less than 1/2LSB of gain error, the input resis-
tance typically must be greater than:
The settling time is affected by the buffer input capaci-
tance, the DAC’s output capacitance, and PC board
capacitance. The typical DAC output voltage settling
time is 1µs for a full-scale step. Settling time can be sig-
nificantly less for smaller step changes. Assuming a
single time-constant exponential settling response, a
full-scale step takes twelve time constants to settle to
within 1/2LSB of the final output voltage. The time con-
stant is equal to the DAC output resistance multiplied
by the total output capacitance. The DAC output
capacitance is typically 10pF. Any additional output
capacitance will increase the settling time.
6.25k 1
2
1
2
205M
14
ΩΩ /
=
MAX5541
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
8 _______________________________________________________________________________________
The external buffer amplifier’s gain-bandwidth product
is important because it increases the settling time by
adding another time constant to the output response.
The effective time constant of two cascaded systems,
each with a single time-constant response, is approxi-
mately the root square sum of the two time constants.
The DAC output’s time constant is 1µs/12 = 83ns,
ignoring the effect of additional capacitance. If the time
constant of an external amplifier with 1MHz bandwidth
is 1/2π(1MHz) = 159ns, then the effective time con-
stant of the combined system is:
This suggests that the settling time to within 1/2LSB of
the final output voltage, including the external buffer
amplifier, will be approximately 12 ✕180ns = 2.15µs.
Digital Inputs and Interface Logic
The digital interface for the 16-bit DAC is based on a 3-
wire standard that is SPI/QSPI/MICROWIRE–compati-
ble. The three digital inputs (CS, DIN, and SCLK) load
the digital input data serially into the DAC.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. This means that opto-
couplers can interface directly to the MAX5541 without
additional external logic. The digital inputs are TTL/
CMOS-logic compatible.
Unipolar Configuration
Figure 3 shows the MAX5541 configured for unipolar
operation with an external op amp. The op amp is set for
unity gain, and Table 1 shows the codes for this circuit.
Power-Supply Bypassing and
Ground Management
For optimum system performance, use PC boards with
separate analog and digital ground planes. Wire-wrap
boards are not recommended. Connect the two ground
planes together at the low-impedance power-supply
source. Connect DGND and AGND together at the IC.
The best ground connection can be achieved by con-
necting the DACs DGND and AGND pins together and
connecting that point to the system analog ground
plane. If the DACs DGND is connected to the system
digital ground, digital noise may get through to the
DACs analog portion.
Bypass VDD with a 0.1µF ceramic capacitor connected
between VDD and AGND. Mount it with short leads
close to the device. Ferrite beads can also be used to
further isolate the analog and digital power supplies.
83ns 159ns 180ns
22
()
+
()
=
Figure 3. Typical Operating Circuit
0V0000 0000 0000 0000
VREF ✕(1 / 65,536)0000 0000 0000 0001
VREF ✕(32,768 / 65,536) = 1/2VREF
1000 0000 0000 0000
VREF ✕(65,535 / 65,536)1111 1111 1111 1111
ANALOG OUTPUT, VOUT
MSB LSB
DAC LATCH CONTENTS
Table 1. Unipolar Code Table
TRANSISTOR COUNT: 2209
SUBSTRATE CONNECTED TO DGND
Chip Information
MAX5541
MAX495
DGND
VDD (REFS)REF
OUT
SCLK
DIN
CS
AGND_
0.1µF
0.1µF
+5V
+2.5V
EXTERNAL OP AMP
MC68XXXX
PCS0
MOSI
SCLK
UNIPOLAR
OUT
10µF
MAX5541
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
9_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SOICN .EPS
PACKAGE OUTLINE, .150" SOIC
1
1
21-0041 B
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
MAX
0.010
0.069
0.019
0.157
0.010
INCHES
0.150
0.007
E
C
DIM
0.014
0.004
B
A1
MIN
0.053A
0.19
3.80 4.00
0.25
MILLIMETERS
0.10
0.35
1.35
MIN
0.49
0.25
MAX
1.75
0.050
0.016L0.40 1.27
0.3940.386D
D
MINDIM
D
INCHES
MAX
9.80 10.00
MILLIMETERS
MIN MAX
16 AC
0.337 0.344 AB8.758.55 14
0.189 0.197 AA5.004.80 8
N MS012
N
SIDE VIEW
H 0.2440.228 5.80 6.20
e 0.050 BSC 1.27 BSC
C
HE
eBA1
A
D
0-8
L
1
VARIATIONS:
