A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 1
1 Features
♦ AS-i Complete Specification V2.1 compliant
♦ Integrated EEPROM
♦ Additional addressing channel using an opto-
electronic interface
♦ Extended address mode operation as
programmable option (up to 62 slaves)
♦ High impedance AS-i line input, additional pins for
further impedance optimizations
♦ DC voltage output, approximately 24 volts, not
stabilized
♦ 5-volt DC output, stabilized, CMOS logic can be
supplied directly (e.g. µC)
♦ LED status indicator output (compliant to the
standard indication recommendation)
♦ Periphery fault indication
♦ Integrated watchdog
2 Description
The A²SI is a monolithic CMOS integrated circuit
designed for AS-i (Actuator Sensor-interface)
networks. AS-i networks are intended for industrial
automation.
The main advantage of AS-i solutions is that
actuators and sensors are connected using a two-
wire unshielded cable that is easy to install. This
cable transports both power and information/data.
AS-i network c omm unication is based on the m aster-
slave principle. The network can be extended (to
cable lengths greater than 100m ) by using the A²SI in
the repeater mode configuration.
AS-i is a standard for the automation industry based
on the European standard EN 50295.
The device is available in a 28-pin SSOP package.
3 Block Diagram
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 2
RECEIVE
TRANSMIT
ELECTRONIC
INDUCTOR POWER
SUPPLY OSCILLATOR
4
4
4
DIGITAL
LOGIC
THERMAL
PROTECTION
A2SI™
GND2 GND1
ASI+
ASI–
8 MHz
DO.
DI.
DSR
PST
P.
FIDLEDIRDGND0V
UIN UOUT U5R U5RD OSC1/2
CAP
ASIP
ASIN
10 µF
1 µF5V
24V
POWERFAIL
DETECTION
IRD
AMP
Figure 1: Block Diagram
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 3
4 Pin Description
Table 1: Pin Description
PIN # PIN NAME TYPE DESCRIPTION
1 ASIP INOUT To be connected to the AS-i-line ASI+ via reverse polarity protection diode
2 ASIN INOUT To be connected to the AS-i-line ASI-
3 0V SUPPLY Common 0V for all ports except ASIP/ASIN (to be connected to ASI- line)
4 IRD IN Addressing channel input
5 FID IN Input peripheral fault indication
6 OSC2 IN Crystal oscillator (8 MHz x-tal)
7 OSC1 IN Crystal oscillator / external clock input
8 DO3 OUT Output of data D3
9 DO2 OUT Output of data D2
10 DO1 OUT Output of data D1
11 DO0 OUT Output of data D0
12 GND SUPPLY Digital IO ground, must be connected to pin 0V
13 P3 I/O Input/output of parameter P3
14 P2 I/O Input/output of parameter P2 / receive strobe in ”Master Mode”
15 P1 I/O Input/output of parameter P1 / power fail in ”Master Mode”
16 P0 I/O Input/output of parameter P0 / data clock in ”Master Mode”
17 DI0 IN Input of data D0
18 DI1 IN Input of data D1
19 DI2 IN Input of data D2
20 DI3 IN Input of data D3
21 PST OUT Parameter strobe output
22 DSR I/O Data strobe output/reset input
23 U5RD SUPPLY Digital 5V supply input, should be connected to U5R
24 LED OUT Output LED "AS-i-Diagnosis" / addressing channel output
25 CAP IN/OUT For connection of external RC components
26 U5R OUT Internal 5V supply that might be used to supply external circuits as well
27 UOUT OUT Supply of external circuitry (e.g. sensor, actuator, etc.), approx. VUIN minus 7 volt
28 UIN SUPPLY Input of the power supply block (usually to be connected to the AS-i-line ASI+
via reverse polarity protection diode)
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 4
5 Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ASIP
ASIN
0V
IRD
FID
OSC2
OSC1
DO1
DO3
DO2
GND
P3
P2 P1
UIN
UOUT
U5R
CAP
LED
U5RD
DSR
PST
DI3
DO0 DI2
DI1
DI0
A2SI
P0
Figure 2: Pin Configuration, 28 Pin SSOP
6 Functional Block Description
6.1 Power Supply
The electronic inductor provides the de-coupled
voltage at the UOUT pin and the power supply
regulates the internal 5V operating voltage. The de-
coupling circ uit (electronic co il) is connected between
the UIN and UOUT pin and guarantees a high
impedance seen at UIN. An external capacitor and
resistor are required to allow a low-pass filter with a
very high time c ons tant. T his high time c ons tant value
is necessary to maximize the input impedance. The
de-coupling circuit limits the current that can be
drawn from UOUT. The power supply will shut down
the de-coupling circuit in case of an overload
condition to prevent a total malfunction of the
complete AS-i line. The regulated 5-volt supply
voltage is connected to the pin U5R. Two external
capacitors are necessary to cope with fast internal
and external load changes (spikes). The current
drawn from the U5R pin (up to 4 mA) has to be
subtracted from the total load current. The power
supply circuit dissipates the major amount of power:
The total power dissipation shall not exceed the
specified values of Figure 6. The ground reference
voltage for both UOUT and U5R is defined by the 0V
pin. This pin must be connected to ASI-.
6.2 Receiver
The receiver detects the signals on the AS-i line and
delivers the appropriate pulses to the digital logic.
The DC value of the input signal is removed and the
AC signal is band-pass filtered. The digital output
signals are extracted from the sin2-shaped input
pulses by a set of comparators. The maximum
voltage of the first negative pulse determines the
threshold level for all following pulses. The m aximum
value is digitally filtered to guarantee stable conditions
(burst spikes have no effect). This approach
combines a fast adaptation to changing signal
amplitudes with a high detection safety. The receiver
delivers the positive (P-PULSE) and negative (N-
PULSE) pulses to the IC's logic. The logic resets the
comparators after receiving the REC-RESET signal.
When the receiver is turned on, the transmitter is
turned off to reduce power consumption.
6.3 Transmitter
The transmitter draws a modulated current between
the ASI+ and ASI- pins to generate the
communication signals. The shape of the current
corresponds to the integral of a sin2-function. The
transmitter uses a current DAC and a high current
driver. This driver must be activated before the
transm ission to achieve operating conditions. A s mall
current is required which will be ramped up slowly to
avoid any false voltage pulses on the AS-i line. The
amount of cir cuitry between the ASI+ and ASI- pins is
minim ized to allow high impedance values . W hen the
transmitter is turned on, the receiver is turned off to
reduce power consumption.
6.4 Power-Fail Detection
The power-f ail detector consists of a comparator that
generates a logic signal in case the power drops
below 22VDC (Power-Fail) f or mor e than tLoff (0.8 ± 0.1
ms ). The power-fail signal will be presented at pin P1
in master/repeater mode. The power-fail detection
monitor s the value of the ASIP voltage. It will activate
a logic signal if the power fails for more than 1ms.
The device is then buffered by the external capacitor
at UOUT. The IC’s internal circuitry will be reset when
the U5R supply voltage fails.
6.5 Digital Logic
The digital logic block performs the analysis of the
received signal, controls the reaction of the IC,
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 5
transmits the slave response, switches the I/O-ports,
and controls the internal EEPROM. Its principal
function is described in detail in section 7.
6.6 Protection Circuitry
The device has several protection cells that prevent
the disruption or malfunction of the complete AS-i
line. The thermal detection shuts down the power
supply in case of over-heating c ondition (tem perature
> 140°C typical for more than 2 seconds) and when
UOUT is shorted to GND for more than 2 seconds.
The device can only be reactivated by a power-on
reset. The over-heating condition can occur by
overloading any of the output pins. Therefore, the
circuit m onitors the operating conditions of the power
supply (effectively controls UOUT and U5R) and
measures the temperature of the silicon.
RECEIVE
TRANSMIT
POWERFAIL
DETECTION
POWER
SUPPLY OSCILLATOR
DIGITAL
LOGIC
THERMAL
PROTECTION
A2SI™
GND2 GND1
DO(3:0)
DI(3:0)
DSR
PST
P(3:0)
FIDLEDIRDGND
0V
UIN UOUT U5R U5RD OSC1/2
CAP
ASIP
ASIN
Over-Heating
Imp-Pos
Imp-Neg
Rec-Reset
Send-Out
Standby
Power-Fail
Power-On
Reset
UOUT
Shut Down
Clock
OUTPUT
STAGE
INPUT
STAGE
I/O
STAGE
OUTPUT
STAGE
INPUT
STAGE
OUTPUT
STAGE
OUTPUT
STAGE INPUT
STAGE
INPUT
STAGE AC
Current
INPUT
Data Out
Data In
Data Strobe
Reset
Param
Strobe
Param
In
Param
Out
LED
Out
Fault
In
IRD In
Logic
AC
ELECTRONIC
INDUCTOR
Figure 3: Functional Block Diagram
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 6
6.7 Infrared Diode Input
The IRD input can be used as an alternative
communication pin. The IRD circuitry will be turned
off when the communication has been switched to the
AS-i line. The logic sets this input either to photo-
detector or CMOS mode. In photo-detector m ode, the
signals of an external photodiode are amplified. In
CMOS mode (master/repeater mode only), the input
signals have to be CMOS levels between 0V and
VU5R.
Data-Out-0
Data-Out-1
Data-Out-2
Data-Out-3
Data-Strobe
Reset
Data-In-0
Data-In-1
Data-In-2
Data-In-3
Param-Out-0
Param-Out-1
Param-Out-2
Param-Out-3
Param-Strobe
Param-In-0
Param-In-1
Param-In-2
Param-In-3
IRD-In
Fault-In
LED-Out
Overheating
UOUT Shoutdown
PORTS
DO-Reg-0
DO-Reg-1
DO-Reg-2
DO-Reg-3
DI-Reg-0
DI-Reg-1
DI-Reg-2
DI-Reg-3
PO-Reg-0
PO-Reg-1
PO-Reg-2
PO-Reg-3
PI-0
PI-1
PI-2
PI-3
E2PROM
STATE MACHINE
Rec-Reg-0
Rec-Reg-1
Rec-Reg-2
Rec-Reg-3
Rec-Reg-4
Rec-Reg-5
Rec-Reg-6
Rec-Reg-7
Rec-Reg-8
Rec-Reg-9
Rec-Reg-10
Rec-Strb
Send-Reg-0
Send-Reg-1
Send-Reg-2
Send-Reg-3
Send-Strb
UART
Add-Clk
Add-Out
Add-In
Imp-Pos
Imp-Neg
Send-Out
Standby
Rec-Reset
Digital Logic
Power-Fail
Power-On-Reset
Figure 4: Digital Logic
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 7
7 Description of Digital Logic
The digital logic is structured in four (4) parts (see
Figure 4):
1. the UART, which analyzes the incoming signal
from the AS-i line and ensures correct timing of
output signals;
2. the STATE MACHINE, which controls the
reaction of the IC;
3. the PORTS, which contain registers and
asynchronous logic blocks;
4. and finally the EEPROM, which contains the non-
volatile data of the A2SI circuit.
Rec-Reg-0
Rec-Reg-1
Rec-Reg-2
Rec-Reg-3
Rec-Reg-4
Rec-Reg-5
Rec-Reg-6
Rec-Reg-7
Rec-Reg-8
Rec-Reg-9
Rec-Reg-10
UART
Send-Reg-0
Send-Reg-1
Send-Reg-2
Send-Reg-3
RECEIVE
REGISTER
SEND
MUXER
Send-D
Add-Out
RECEIVE
MUXER
MAN CODE
CHECKER
CONTROL
UNIT
PULSE
ENCODER
ACTIVITY
CHECKER
SEND
REGISTER
STROBE
UNIT
N-Pulse
P-Pulse
Add-In
Send-Strb
Rec-Strb
Add-Clk
Send-Standby
Rec-Reset
Figure 5: UART Block Diagram
7.1 UART Operational Modes
7.1.1 Master/Repeater Mode
7.1.1.1 IRD Input
The IC sends the signal retrieved from the IRD pin to
the AS-i line as an AS-i telegram. The input signal is
Manchester-coded and active low. A falling edge of
the IRD signal, which is conducted to ADD-IN, starts
the receiving process and triggers the Activity-
Checker. The Receive-Muxer selects the IRD pin as
input for the receive data. The IRD signal is
connected with the Send-Muxer to SEND-D via ADD-
IN. The IRD s ignal is latched every 500 ns as long as
there is activity on the input pin. If ther e is a high level
on the IRD input longer then 7.0 µs the Activity-
Checker will recognize this as no activity and the
Receive-Muxer is returned to an idle state. The
information on the IRD pin is transported to the
SEND-D pin with a delay of 2.0 µs up to 2.5 µs. The
sender is always in non-standby mode. The SEND-
SBY signal is steady low and there is no generation of
ADD-CLK.
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 8
7.1.1.2 AS-i Input
A signal on the AS-i-line generates signals at the
receiver output that are pulse-coded with a minimal
pulse width of 750 ns up to 875 ns. A pulse on the
AS-i line starts the receiver and triggers the Activity-
Checker through N-PULSE or P-PULSE. The
Receive-Muxer selects the AS-i-line pins as input for
the receive data. The N-PULSE and P-PULSE
signals are latched every 500 ns as long as there is
activity on the input pins. If there is a pulse distance
on the AS-i-line inputs longer then 7.0 µs, the receiver
will recognize this as no activity and the Receive-
Muxer will go to the idle state.
The Pulse-Encoder is used to convert the active high
pulse-coded signal to a active low Manchester-II-
coded (MAN) signal. It will also check the pulse
stream for timing and pulse errors (e.g. alternation
error). In Master/Repeater mode the Pulse-Encoder
additionally resynchronizes an error-free MAN
telegram into a proper 3 µs time base. This is to
eliminate the pulse jitter of the transformed AS-i
telegram. The synchronized MAN signal is sent to
ADD-OUT through the Send-Muxer. ADD-OUT is
connected to LED-OUT on a higher hierarchy level.
All in all, the information on the AS-i-line pins is
transported to the LED-OUT pin with a delay of 2.5 µ s
up to 3.0 µs. In Master/Repeater mode the sender is
never in standby mode, hence the SEND-SBY signal
is always low.
A generation of ADD-CLK is provided to simplify the
external processing of the Manchester-coded data.
The rising edge of the ADD-CLK signal is in the
middle of the second half of the Manchester data
assuring that the correct binary data can be clocked
into a shift r egister. The ADD-CLK s tarts with a rising
edge 2.0 µs after the falling edge of the start bit at
ADD-OUT with a period of 6.0 µs and a ratio of 1:1.
The last rising edge of the ADD-CLK signal occurs
2.0 µs after the falling edge of the end bit at ADD-
OUT.
If the received signal in the Master Mode is a slave,
answer with start bit, four (4) data bits, parity, and end
bit, and if a pause greater than 6.0 µs follows, the
UART generates the active high REC-STRB signal
with a pulse width of 500 ns. The REC-STRB signal is
connected to the P2 Parameter Output in this mode.
It appears 10.0 to 10.5 µs after the rising edge of the
end bit on the AS-i-line.
7.1.1.3 Ports
The f unctional assignm ents of som e IC ports depend
on the operational mode of the IC. Thus, these ports
perform multiple functions that are related to a
particular mode of the IC.
In the Master or the Repeater Mode the following
signals and ports are connected:
Add-Clk P0 Parameter output port bit 0
Power-Fail P1 Parameter output port bit 1
Rec-Strobe P2 Parameter output port bit 2
Add-Out LED LED output/addressing channel
output
Add-In IRD Fault indicator input/addressing
channel input
7.1.2 Slave Mode
In the Slave Mode the Receive-Muxer is watching the
two input channels (AS-i-line and IRD pin) depending
on a multiplex select signal MPX. MPX has a
frequency of about 1.0 kHz. If MPX is low the
Receive-Muxer selects the AS-i-line and vice versa if
it is high it selects the IRD pin as data input. The
channel, from which a valid master call is received
first, will be locked until the next IC-reset occurs.
7.1.2.1 IRD Input Mode
The signal on the IRD input is Manchester -coded and
low active. A low level of the IRD signal starts the
receiver and triggers the Activity-Checker. The
Control-Unit enables the Receive-Register and the
received information is clocked every 6 µs into the
Receive-Register. If there is a high level on the IRD
input longer then 7.0 µs, the Control-Unit will
recognize this as no ac tivity and the Receive-Register
will be disabled. If the received information is a
correct master call with Start-Bit, eleven Data-Bits,
Parity-Bit, End-Bit, and following pause of either
greater than 6.0 µs (Synchronous Mode) or 18.0 µs
(Asynchronous Mode), the UART generates the
internal active high REC-STRB signal with a pulse
width of 500 ns. If the received telegr am c ontained an
error, the Control-Unit will not generate the REC-
STRB signal but go to its asynchronous state waiting
for a pause at the IRD input. After a pause is
detected, the UART will be ready to receive the next
telegram from the IRD input.
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 9
If a REC-STRB signal is generated, it occurs 9.5 µs
up to 10.0 µs (Synchronous Mode) or 21.0 µs up to
21.5 µs (Asynchronous Mode), respectively, after the
rising edge of the End-Bit on the IRD pin signal. If the
slave was in asynchr onous state, it now trans forms to
synchronous state. The Rec-Muxer is locked to the
IRD input until the next IC-reset. After the generation
of a REC-STRB signal the Control-Unit waits for
about 6.0 µs for the SEND-STRB to be generated by
the Main-State-Machine.
If the Control-Unit receives the active high SEND-
STRB signal (pulse width 500 ns), it starts the
transmission of the Send-Register data. Therefore,
the Send-Register data will be converted to an active
low Manchester II-coded (MAN) signal, which is sent
to the LED-OUT pin via ADD-OUT. The first falling
edge of the MAN signal occurs 11.75 µs
(Synchronous Mode) or 12.25 µs (Asynchronous
Mode) after the rising edge of the REC-STRB signal.
Therefore the delay from the rising edge of the End-
Bit of the master call (IRD input) to the first falling
edge of the slave response (LED output) is 21.25 to
21.75 µs (Synchronous Mode) or 33.25 to 33.75 µs
(Asynchronous Mode). If all data is sent, the Control-
Unit sets the sender in standby mode (SEND-SBY is
high) and check s for a slave pause on the IRD input.
After the pause was detected, the UART is ready to
receive the next telegram from the IRD input.
In case the Control-Unit will not receive a SEND-
STRB signal within the given time frame (for instance,
if this slave was not addressed), it will check for
activity on the IRD input. If any activity is detec ted in a
time frame of about 60 µs (another slave is
transmitting data), the Control-Unit will wait for the
next pause (slave pause). Otherwise, it will just wait
for the end of the response time (60 µs). In both
cases the Control-Unit stays synchronous. Once a
slave pause is detected, the UART will be ready to
receive the next telegram from the IRD input.
7.1.2.2 AS-i Input Mode
A signal on the AS-i-line generates two pulse-coded
signals (N-PULSE, P-PULSE) at the receiver output
with a m inimum pulse width of 750 to 875 ns. A pulse
on the AS-i line starts the receiver and triggers the
Activity-Checker through N-PULSE or P-PULSE.
The Pulse-Encoder is used to convert the active high
pulse coded signal to an active low Manchester-II-
coded (MAN) signal. It will also check the pulse
stream for timing and pulse errors (e.g. alternation
error). The Control-Unit enables the Receive-Register
so that the received information can be clocked in
every 6 µs. If there is a pulse distance on the AS-i-
line input longer than 7.0 µs, the Control-Unit
recognizes this as no activity and disables the
Receive-Register.
If the received information is a correct master call
with Start-Bit, eleven (11) Data-Bits, Parity-Bit, End-
Bit, and following a pause greater than either 6.0 µs
(Synchronous Mode) or 18.0 µs (Asynchronous
Mode), the UART generates the internal active high
REC-STRB signal with a pulse width of 500 ns. If the
received telegram contained an error, the Control-
Unit will not generate the REC-STRB signal but go to
its asynchronous state waiting f or a pause at the AS-i
line input. After a pause is detected, the UART is
ready to receive the next telegram from the AS-i line
input.
If a REC-STRB signal is generated, it occurs 10.0 to
10.5 µs (Synchronous Mode) or 21.5 to 22 µs
(Asynchronous Mode), respectively, after the rising
edge (receiver comparator switching point) of the
End-Bit on the AS-i line input. If the slave was in
asynchronous state, it now transforms to
synchronous state. The Rec-Muxer is locked to the
AS-i line input until the next IC-reset. After the
generation of a REC-STRB signal, the Control-Unit
waits for about 6.0 µs for the SEND-STRB to be
generated by the Main-State-Machine.
If the Control-Unit receives the active high SEND-
STRB signal (pulse width 500 ns), it starts the
transmission of the Send-Register data. Therefore,
the Send-Register data will be converted to an active
low Manchester II-coded (MAN) signal, which is sent
to the AS-i line transmitter via SEND-D. The first
falling edge of the MAN signal occurs 11.75 µs
(Synchronous Mode) or 12.25 µs (Asynchronous
Mode) after the rising edge of the REC-STRB signal.
Consequently, the delay from the rising edge of the
End-Bit of the master call (AS-i input) to the first
falling edge of the slave response (AS-i output) is
21.75 to 22.25 µs (Synchronous Mode) or 33.75 to
34.25 µs (Asynchronous Mode).
The SEND-SBY will always be set low 0.5 µs after the
rising edge of REC-STRB. This is to turn on the
transmitter and let it settle at its operation point. The
small offset current, which is required to operate the
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 10
transmitter, will be ramped up slowly to avoid any
false voltage pulses on the AS-i line.
If all data is sent, the Control-Unit sets the sender in
standby mode (SEND-SBY is high) and checks for a
slave pause on the AS-i line input. After a pause is
detected, the UART will be ready to receive the next
telegram from the AS-i line input.
In case the Control-Unit will not receive a SEND-
STRB signal within the given time frame (for instance,
if this slave was not addressed), it will check for
activity on the AS-i line. If any ac tivity is detected in a
time frame of about 60 µs (another slave is
transmitting data), the Control-Unit will wait for the
next pause (slave pause). Otherwise, it will just wait
for the end of the response time (60 µs). In both
cases the Control-Unit stays synchronous. Once a
slave pause is detected, the UART is r eady to receive
the next telegram from the AS-i line input.
7.1.2.3 Ports
In the Slave Mode it is not necessary to decode the
IO-Configuration; all Data-Out and Data-In signals are
directly connected to the respective port.
If the Multiplex-Flag-nvmem is TRUE, the output ports
will switch to high impedance state for a certain
period of time following the rising edge of the Data-
Strobe.
If Watchdog-Flag is TRUE and Watchdog-active-
Flag-nvmem is TRUE, a reset (INIT) will be
performed.
An active FID (logic high) signal shall cause a
flashing status LED (frequency approx. 2Hz) and Bit 1
of the Status-Register (S1) shall be set as well. If FID
is not active (logic low), S1 is cleared. In that case,
the status LED operation depends on the Data-
Exchange-Disable flag.
If the Data-Exchange-Disable flag is set (no data
exchange allowed) a steady-on LED shall indicate
that the communication is off. Note: An active FID
has priority and will cause a flashing LED even if the
Data-Exchange-Disable flag is set.
If the UART has selected the IRD input channel, the
LED output should not toggle. In this mode, the LED
pin does not operate as indicator LED output.
Theref ore, periphery f ailures or status inf ormation will
not be signaled.
If OVER-HEAT is TRUE, the IC will be put into shut-
down and stay there until the next power-on reset
occurs.
If INVERT-DATA-IN is TRUE, all input data is
inverted. This feature will simplify the circuitry for
NPN-inputs.
7.1.2.4 State Machine
The so-called Main-State-Machine performs the
central control of the A2SI IC concerning the mode
control, the access to the EEPROM; the processing
of master requests; and the control of the IC ports.
There is a register interface (receive and send
register) between Main-State-Machine and UART
(controls the serial data communication channels).
This register interface is used to exchange
communication data between UART and Main-State-
Machine.
To avoid the situation in which a single slave IC is
accidentally locked in a disallowed state that could
jeopardize the entire system, all prohibited states of
the state machine will lead to a RESET. This means
that the IC will execute its reset procedure by
performing the instruction ”Reset Slave (RES)”.
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7.2 Summary of Master Calls
In the following diagram, all Master Calls that will be
decoded by the A2SI are listed. The "Enter Program
Mode" call is intended f or factory program ming of the
IC only. In order to achieve EEPROM firmware
protection and to comply to the complete AS-i
specification, the call "Enter Program Mode" will be
deactivated before shipment of the slave. Please
refer to the A2SI Applic ation Note [4] for details of the
programming process.
Table 2: A²SI Master Calls and Related Slave Responses
Master Re
q
uest Slave Res
p
onse
Instruction MNE ST CB A4 A3 A2 A1 A0 I4 I3 I2 I1 I0 PB EB SB I3 I2 I1 I0 PB EB
Data Exchange DEXG 0 0 A4 A3 A2 A1 A0 0 D3
~Sel D2 D1 D0 PB 1 0 D3
E3 D2
E2 D1
E1 D0
E0 PB 1
Write Parameter WPAR 0 0 A4 A3 A2 A1 A0 1 P3
~Sel P2 P1 P0 PB 1 0 P3
I3 P2
I2 P1
I1 P0
I0 PB 1
Address Assignment ADRA 0 0 0 0 0 0 0 A4 A3 A2 A1 A0 PB 1 0 0 1 1 0 PB 1
Write Extented ID
Code-1 WID1 01000000ID3ID2ID1ID0PB1 00000PB1
Delete Address DELA 0 1 A4 A3 A2 A1 A0 0 0 Sel 0 0 0 PB 1 0 0 0 0 0 PB 1
Reset Slave RES 0 1 A4A3A2A1A0 1 1
~Sel 100PB1 00110PB1
Read IO
Confi
g
uration RDIO 0 1 A4A3A2A1A0 1 0
Sel 0 0 0 PB 1 0 IO3 IO2 IO1 IO0 PB 1
Read ID Code RDID 0 1 A4A3A2A1A0 1 0
Sel 0 0 1 PB 1 0 ID3 ID2 ID1 ID0 PB 1
Read ID Code-1 RID1 0 1 A4 A3 A2 A1 A0 1 0
Sel 0 1 0 PB 1 0 ID3 ID2 ID1 ID0 PB 1
Read ID Code-2 RID2 0 1 A4 A3 A2 A1 A0 1 0
Sel 0 1 1 PB 1 0 ID3 ID2 ID1 ID0 PB 1
Read Status RDST 0 1 A4A3A2A1A0 1 1
~Sel 1 1 0 PB 1 0 S3 S2 S1 S0 PB 1
Broadcast (Reset) BR01 011111110101PB1 --- no slave response ---
Enter Program Mode PRGM010000011101PB1 --- no slave response ---
Note: In extended address mode the "Select Bit" defines whether the A-Slave or B-Slave is being addressed. Dependent on
the type of master call the I3 bit carries the select bit information (Sel) or the inverted select bit information (~Sel).
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8 Electrical Specification
8.1 Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a
stres s rating only, and functional operation of the device at t hese or any other c onditions above the operational l imi ts noted in this specification
is not i mplied. Exposure to maximum rating c ondi tions f or extended condi tions may eff ect devic e performance, functionali t y, and reliability.
Table 3: Absolute Maximum Ratings
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
V0V ,VGND Voltage reference 0 0 V
VASIP Positive AS-i supply voltage -0.3 40 V
VASIN Negative AS-i supply voltage -0.3 20 V 1
VASIP-ASIN Voltage difference from ASIP to ASIN (VASIP - VASIN)-0.340V
2
VASIPP AS-i supply pulse voltage, voltage difference between pins
ASIP and ASIN (from ASIP to ASIN) 50 V 3
VUIN Aux. power supply input voltage -0.3 40 V
VUINPV Aux. power supply input voltage pulse 50 V 3
Vinputs1 Voltage at pins DI3 - DI0, DO3 - DO0, P3 - P0, DSR, PST,
LED, FID, UOUT
-0.3 VUIN +
0.3 VV
inputs1
≤ 40V
Vinputs2 Voltage at pins OSC1, OSC2, IRD, CAP, U5R, U5RD -0.3 7 V
Iin Input current into any pin except supply pins -25 25 mA
H Humidity non-condensing 4
VHBM1 Electrostatic discharge – human body model (HBM1) 4000 V 5
VHBM2 Electrostatic discharge – human body model (HBM2) 2000 V 6
VEDM Electrostatic discharge – equipment discharge model (EDM) 400 V 7
θSTG Storage temperature -55 125 °C
Ptot Total power temperature 0.85 W 8
1ASIN-pi n shall be shorted to 0V-pin and GND-pi n on PCB.
2Reverse polarit y protecti on has to be performed externally.
3Pulse with ≤ 50µs, repetition rate ≤ 0. 5 Hz.
4Defined in DIN 40040 cond. F.
5HBM1: C = 100pF charged to VHBM1 with resis tor R = 1.5kΩ in series, valid for ASIP-ASIN only.
6HBM2: C = 100pF charged to VHBM2 with resis tor R = 1.5kΩ i n series, valid for all pi ns except ASIP-AS IN.
7EDM: C = 200pF charged to V EDM with no resistor in series, valid for ASIP-ASIN only.
8At maximum operating temperature, the allowed total power dissipation depends on the addit i onal thermal resist ance from case to ambient
and on the operation ambient temperat ure (see Figure 6).
CAUTION: ELECTROSTATIC SENSITIVE DEV ICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to high-energy
electrostatic discharge.
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Ptot = f (Ta); 1L / 2L = 1 layer / 2 layer PCB
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
-25 0 25 50 75 100
Ta
Ptot (2L)
Ptot (1L)
Figure 6: Maximum Power Dissipation, PTOT = f(Ambient Temperature)
Table 4: Operating Conditions
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
VUIN Positive supply voltage 16 33.1 V 1
VASIN Negative AS-i supply voltage 0 0 V 2
V0V, VGND Negative supply voltage 0 0 V
IASI Supply current at VASI = 30V 9 mA 3
ICL1 Max. output sink current at pins DO3 - DO0, DSR 10 mA
ICL2 Max. output sink current at pins P0 - P3, PST 10 mA
θamb Ambient temperature range, operating range -25 85 °C
1DC paramet er (no power fail det ected); V UIN = VUOUT + VDROP
2 ASIN shall be shorted with 0V and GND to ensure proper funct ionality of transmitt er circui t .
3 fc = 8.000 MHz, no load at any pi n without reaction of the circ ui t, AS IP is short-cut to UIN and A SIN to 0V respecti vel y.
8.2 DC and AC Characteristics
All param eters are valid for the recomm ended range of VASIP - VASIP (VUIN - V0V) and θamb. The devices are tested
within the recom mended range of VASIP - VASIP (VIN - V0V), θam b = +25°C (+ 85°C and - 25°C on sam ple base only)
unless otherwise stated. Unused input pins shall be connected to a suitable potential within the application circuit
because there are no internal pull-up/down resistors. It is recom mended that these pins be connected either to 0V
or via resistor to UOUT.
W ith an external LOW signal at the data strobe pin DSR (pull-down open drain driver) for more than 44µs, the IC
will execute its reset procedure. During a power on procedure, all data and parameter ports will stay in a high-
impedance state.
If the IC has been put in its initialization procedure by an exter nal reset via DSR, the LED pin should not be toggled
externally to avoid having the IC control logic transfer to test mode.
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8.2.1 Digital Input and Output Pins
Table 5: Input/Output Voltage and Current
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
Pins DI0 - DI3, P0 - P3, DSR, FID, PST1
VIL Voltage range for input ”low” level, not P0 – P3 0 2.5 V
VIL Voltage range for input ”low” level, only P0 – P3 0 2.4 V
VIH Voltage range for input ”high” level 3.5 VUOUT V
VHYST Hysteresis for switching level 0.25 V 2
IIL Current range for input ”low” level -20 -5 µA
IIH Current range for input ”high” level -10 10 µA VO = 5V
IIHV Current range for high voltage input 2 mA VO = 30V
Pins DO0 - DO3, P0 - P3, DSR, PST
VOL1 Voltage range for output ”low” level 0 1 V IOL1 = 10mA
VOL2 Voltage range for output ”low” level 0 0.4 V IOL2 = 2mA
IOH Output leakage current -10 10 µA VOH = 4.5V
CDL Capacitance at pin DSR 10 pF 3
Pin LED
VOL Voltage range for output ”low” level 0 1 V IOL1 = 10mA 4
IOH Output leakage current -10 30 µA VOH = 40V 5
1 PST is used as i nput for test purpose only.
2 Switching l evel approximately 3V , i .e. 3V ± VHYST.
3 For higher capaci tive load an external pull-up res i stor connec ted to UOUT is nec essary to reach VICH ≥ 3.5V at DSR in less than 35 µs after
beginning of DSR = Low pulse, otherwise a res et will be executed.
4 The output driver sends a “low” (LED on).
5 The output driver s ends a “high” (equivalent to tri-state, LE D off).
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Table 6: Timing Parameter Port
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
tsetupL Valid output data LOW of P0 - P3 to PST-H/L 0.1 0.5 µs
tsetupH Valid output data HIGH of P0 - P3 to PST-H/L 0.1 0.5 µs
tPST PST pulse width 5 6 µs
tPI-latch PST-H/L to parameter input latch 11 13.5 µs 1
tCYCLE Next cycle 150 µs
1 The parameter i nput data must be stable within t he peri od that is def i ned by minimum and maximum t PI-latch.
PST
tsetup tPST
tCYCLE
tPI-latch
Parameter port output data
parameter input value (PIx) = parameter output value (POx) wired AND
with external signal source value
keep stable
min max
PO0-PO3
Figure 7: Timing Diagram Parameter Port P0 - P3
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Table 7: Timing Data Port Outputs
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
tsetupL Valid output data LOW of DO0 - DO3 to DSR-H/L 0.1 0.5 µs
tsetupH Valid output data HIGH of DO0 - DO3 to DSR-H/L 0.1 0.5 µs
tholdL Valid output data LOW of DO0 - DO3 to DSR-L/H 0.1 0.5 µs
tholdH Valid output data HIGH of DO0 - DO3 to DSR-L/H 0.1 0.5 µs
tDSTR DSR pulse width 5 6 µs
tDI-latch DSR-H/L to data input latch 11 13.5 µs 1
tCYCLE Next cycle 150 µs
1 The data input must be stable withi n the period that i s defined by minimum and maximum of t DI-latch.
DSR
tsetup tDSR
tCYCLE
tDI-latch
Data port output data
keep stable
min max
DO0-DO3
DI0-DI3 Data port inp ut data
thold
data remains, if multiplex
flag is not set hi-z, if multiplex flag is set
Figure 8: Timing Diagram Data Port DO0 - DO3
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Table 8: Timing Reset Signal
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
tALM1 Ext. DSR (no reset) 35 µs
tALM2 Ext. DSR to DO0 - DO3 Hi-Z 44 µs
tRESET1 Reset time after DSR = external L ->H transition 2 ms
DSR
DO0-DO3
tALM1
tALM2
>0
tRESET1
hi-z
PO0-PO3 hi-z
D a ta p or t o utput d a ta
Pa ramete r p ort o u tpu t d ata
Figure 9: Timing Diagram External Reset via DSR
8.2.2 A ddressing Channel Input IRD
The addressing channel input IRD is a dedicated photodiode input. The photodiode can be connected to the pins
IRD and 0V directly. The IRD input is an AC current input. A valid signal at the current input has to have a certain
amplitude (r ange) and should not exceed a certain off set value ( s ee Figur e 10 and T able 9) . A logic "low" at the IRD
input will be detected if the present signal value drops below IIRDO, and a "high” will be detected if its pr es ent value is
greater than IIRDO + IIRDA.
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MIN
IIRDA
MAX
IIRDA
MAX
IIRDO
time
IRD
input
current
Figure 10: Photo Current Waveforms
Table 9: AC Current Amplitude of IR Diode Input in Slave Mode
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
IIRDO Input current offset 10 µAPP
IIRDA Input current amplitude 10 100 µAPP
Table 10: Digital Input IRD in Master/Repeater Mode
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
VIL Voltage range for input ”low” level 0 2.5 V
VIH Voltage range for input ”high” level 3.5 VU5R V
Tr /TfRise/fall time 100 ns 1
1 In order to avoid j i t tery on the AS -i l i ne, the ris e/fall tim e of the IRD input signal should be as l ow as pos sible.
8.2.3 Fault Indication Input, FID
The fault indication input FID is a digital input dedicated for a periphery fault messaging signal (for properties, see
Table 5). T he S1 s tatus bit is equivalent to the F ID input s ignal. A FID tr ansition will occ ur at S1 with a certain delay,
because a synchronizer circuit is put in between.
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8.2.4 Voltage Outputs
Table 11: Properties of Voltage Output Pins UOUT and U5R
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
VUOUT UOUT output supply voltage VUIN-
VDROPma
x
VUIN-
VDROPmi
n
VI
UOUT = 30mA
VUOUTp UOUT output voltage pulse deviation 1.5 V 1
tUOUTp UOUT output voltage pulse deviation width 2 ms 1
VDROP Voltage drop from pin UIN to pin UOUT 6.5 7.7 V VUIN > 22V
VU5R 5V supply voltage 4.5 5.5 V
IUOUT UOUT output supply current 0 30 mA IU5R = 0 2
I5V U5R output supply current 0 4 mA IUOUT < 26 mA
IoTotal voltage output current IUOUT + I5V 30 mA
IUOUTS Short circuit output current 50 mA
CLUOUT Load capacitance at UOUT 10 470 µF
CL5V Load capacitance at U5R 1 µF
1 COUT = 10 µF, out put current s witc hes from 0 to 30 mA and vic e versa.
2 11.0V < VOUT < 27.6V.
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8.2.5 A S-i Bus Load
The f ollowing parameters ar e deter mined with shortcuts between the pins ASIP and UIN and the pins ASIN and 0V,
respectively.
Table 12: AS-i Bus Interface Properties (Pins ASIP/ASIN and UIN)
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
VUIN Input AS-i voltage at UIN VUOUTmin+
VDROPmax
VUOUTmax +
VDROPmin
V1
ILIN Input current limit at UIN 56 mA
VSIG Input signal voltage difference between ASIP
and ASIN 38V
PP
ISIG Modulated output peak current from ASIP to
ASIN 55 68 mAP
CZener Parasitic capacitance of the external over-
voltage protection diode (zener diode) 20 pF 2
RIN1 Equivalent resistor of the device 16 kΩ2, 3
LIN1 Equivalent inductor of the device 18 mH 2, 3
CIN1 Equivalent capacitor of the device 30 pF 2, 3
RIN2 Equivalent resistor of the device 16 kΩ2, 3
LIN2 Equivalent inductor of the device 12 18 mH 2, 3
CIN2 Equivalent capacitor of the device 15 +
(L-12mH)*2.5pF/mH pF 2, 3
1 DC Param eter
2 The equivalent c i rcuit of a slave (which is calcul at ed from the im pedance of the device and the parallel ed external over-vol tage protecti on
diode (zener diode)) has t o satis fy the Complete AS-i-Specific at i on v.2.1 concerning the requirements for the extended address range.
3 Subtrac t i ng the maximum parasitic capaci tance of t he external over vol t age protecti on di ode (20pF) ei ther the tripl e RIN1, LIN1 and CIN1 or the
triple RIN2, LIN2 and CIN2 has to be commi tted by the devi ce to ful f il the Complete A S-i-Spec i f icati on v2. 1.
8.2.6 Input Impedance Control
Table 13: CAP Pin
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
RCAP External filter resistor 0 2.2 kΩ
CCAP External filter capacitor 4.7 100 nF 1
1 A de-coupli ng capacit or def i nes internal l ow-pass f i l ter time cons tant; l ower values decrease the i mpedance but im prove t he turn-on time.
Higher values do not i mprove the i mpedance but do i ncrease the turn-on time. The turn-on tim e al so depends on the l oad capacit or at UOUT.
After connecti ng the slave t o t he power, t he capacit or i s charged with the maximum current IUOUT. The impedance will increase when the
voltage allows t he anal og circui t ry to fully operat e.
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8.2.7 Oscillator
Table 14: Oscillator Pins (OSC1 and OSC2)
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
COSC External parasitic capacitor at oscillator pins OSC1,
OSC2 05pF
VIL Input ”low” voltage 0 1.5 V 1
VIH Input ”high” voltage 3.5 VU5R V
1 For external clock applied to OS C1 onl y.
8.2.8 Development Infor mation Data
Table 15: Information Data
Conditions: Asynchronous mode, reset to default comparator level at “line pause“.
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
VLSIGon Receiver comparator threshold level (see Figure 11) 45 50 % Related to
amplitude of 1st
pulse
treset1 Reset time after Master Call „Reset AS-i-Slave“ or
DSR = external L ->H transition 2ms 1
treset2 Reset time after power on 30 ms 2
treset3 Reset time after power on with high capacitive load 1000 ms 3
VASIP-PF VASIP voltage to detect power fail (master mode only) 21.5 23.5 V
tLoff Power supply break down time (master mode only) 0.7 0.9 ms 4
VPOR1F VU5R voltage to trigger internal reset procedure,
falling voltage 3.0 4.0 V 1
VPOR1R VU5R voltage to trigger INIT procedure, rising voltage 2.5 3.5 V 1
tLow Power-on reset pulse width 4 6 µs
TShut Chip temperature for thermal shut down
(overheating) 125 160 °C
1 Guaranteed by design onl y.
2 ‘Power_on’ start s lates t at VUIN = 18V, external capacitor at pin UOUT less t han or equal 10µF.
3 CUOUT = 470µF, treset3 is guaranteed by desi gn onl y.
4 CUOUT > 10µF, no power fail generated at VASI P < VASI P-PF f or t < t Loff (in m as t er mode only).
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First negative
pulse of the
ASI telegram
VLSIGon
VLSIGon =
(
0.45 - 0.50
)
* VSIG / 2
The IC determines the
amplitude of the first
negative pulse of the
ASI telegram. This
amplitude is asserted
to be VSIG / 2.
"DC level"
VSIG / 2
Figure 11: Receiver Comparator Set Up
VASIP
VPOR1R
VPOR1F
VUIN
VU5R
POR (active low)
No reset, but if the break down
time exceeds tLoff, a power-fail
signal will be generated Reset will
be initalized
< ca. 15V
0V
≤ tLoff
VASIP-PF
tLow
Power-on Reset will
be active, if the VU5R
drops below VPOR1F
MASTER MODE only All Modes
VASIN
Figure 12: Power-Fail Generation (in Master Mode) and Reset Behavior (All Modes)
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9 Application Circuits
The f ollowing f igures show typical applic ation cases of the A2SI IC. Figure 14 shows an application circuit in which
the A2SI is replacing an ASI3+ circuit. Finally, Figure 15 shows how the A2SI circuit can be used to perform the
analog/digital interfac e between the AS-i- line and the master elec tronics. T his figure also s hows that the IC can be
used in repeater applications as well.
9.1 EMC Precautions
Precautions must be taken to avoid radio frequency interference. Keeping input lines as short as possible and
connecting unused inputs to UOUT through a pull-up resistor are both recommended. Furthermore, the supply pins
should be de-coupled with ceramic capacitors (10 to 100 nF) in addition to the normal de-coupling capacitors.
9.2 T y pical Slave Application
ASI
ASI
8
10 nF
DSR
PST
FID
LED
IRD
GND
0V
U
IN
U
OUT
U5R
U5RD
OSC1
CAP
ASIP
ASIN
10
µ
F
1
µ
F
A
2
SI
OSC2
0V
+24V
+5V
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
P0
P1
P2
P3
DI_0
DI_1
DI_2
DI_3
DO_0
DO_1
DO_2
DO_3
P0
P1
P2
P3
DS&Reset
PST
Fault Input
39V/0.5W
1.2 kΩ RED GREEN
100n 10n
Figure 13: Typical Application, Slave Mode
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9.3 T y pical ASI3+ Compatible Application
ASI
ASI
10 nF
DSR
PST
FID
LED
IRD
GND
0V
U
IN
U
OUT
U5R
U5RD
CAP
ASIP
ASIN
10
µ
F
1
µ
F
A
2
SI
8
OSC1
OSC2
0V
+24V
+5V
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
P0
P1
P2
P3
DI_0
DI_1
DI_2
DI_3
DO_0
DO_1
DO_2
DO_3
P0
P1
P2
P3
DS&Reset
PS
39V/0.5W
1.2 kΩ
10n
100n
Figure 14: Typical ASI3+ Compatible Application
Note: Depending on I/O-configuration, DO- and DI-ports are connected and Multiplex-Flag is set.
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9.4 T y pical Master/Repeater Application
ASI+
ASI–
8 MHz
10 nF
DSR
PST
FID
LED
IRD
GND
0V
U
IN
U
OUT
U5R
U5RD
OSC1
CAP
ASIP
ASIN
10
µ
F
1
µ
F
A
2
SI
OSC2
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
P0
P1
P2
P3
39V
+U
B
Vo
GND
+U
B
Vo
GND
+U
B
Vo
GND
+U
B
Vo
GND
+5V
REC_CLK
(optional)
REC_STRB
(optional)
RECEIVE
SEND
0V
ISOLATION
/
POWER_FAI
L
1.2 kΩ
Figure 15: Master/Repeater Application
The inform ati on furnis hed here by AMI i s bel ieved to be c orrect and acc urat e. However, AMI s hall not be liabl e to lic ens ee or any thi rd party for
any damages, including but no limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect,
special, incidental, or consequential damages of any kind in connection with or arising out of the furnishing, performance, or use of the
technical dat a. No obligation or liability to licens ee or any third part y s hall arise or flow out of AMI´s rendering technical or other services .
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 26
10 Package Outline
Figure 17: SSOP Package
Figure 18: Package Dimensions
Table 16: Package Dimensions (mm)
Symbol A A1 A2 B C D E E H L α
Nominal 1.86 0.13 1.73 0.30 0.15 10.20 5.30 7.80 0.75 4°
Maximum 1.99 0.21 1.78 0.38 0.20 10.33 5.38 7.90 0.95 8°
Minimum 1.73 0.05 1.68 0.25 0.13 10.07 5.20
0.65
BSC 7.65 0.55 0°
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 27
11 Ordering Information
11.1 Device Ordering Codes
Ordering Code Description Operating Temperature
Range Package Type Device
Marking Shipping Form
A2SI-ST Standard version of
A²SI -25°C to 85°C 28-pin SSOP
(5.3 x 10.2) A²SI Tubes
A2SI-SR Standard version of
A²SI -25°C to 85°C 28-pin SSOP
(5.3 x 10.2) A²SI Tape-and-Reel
A2SI-MT Pre-programmed
master function -25°C to 85°C 28-pin SSOP
(5.3 x 10.2) A²SI
+ yellow dot Tubes
A2SI-MR Pre-programmed
master function -25°C to 85°C 28-pin SSOP
(5.3 x 10.2) A²SI
+ yellow dot Tape-and-Reel
11.2 Demo Kit Ordering Code
Ordering Code Kit for Device Description
A2SI-KIT A²SI Kit includes:
• Evaluation board with A²SI
• 3 A²SI samples
• 1 A²SI-M sample
• Collateral (Brochure, Data Sheet, Application Note)
Evaluation board dimensions (L x W x H): 34 x 31 x 8 mm
A²SI™
June 2000 Advanced AS-Interface IC
A²SI™ is a trademark of Am erican Mic rosystems , Inc . AMI reserves the right t o change the detail spec ifications as may be required to perm it
improvements in the des i gn of i ts products.
OA030100 28
12 Package Marking
Figure 19: Package Marking
Top Marking: A²SI Product name
AMI Manufacturer
XXXX Date code (year and week)
Y Assembly location
ZZ Traceability code
Bottom Marking: AAAA Country of assembly
Further Information is available at http://www.amis.com/a2si.
Sales Offices on http://www.amis.com/sales/.
Products s old by AMI are covered exclus ively by t he warranty, patent i ndem nif ic ation and other provis ions appeari ng in AMI´s s t andard "Term s
of Sale" (as the s ame may be am ended by AMI, at its sole dis cretion, from time to t ime). AMI m akes no warranty (express, statutory, implied
and/or by description), including without limitation any warranties of merchantability and/or fitness for a particular purpose, regarding the
information set forth in the Materials pertaining to AMI´s products, or regarding the freedom of any products described in the Materials from
patent and/or ot her infringement. AMI reserves the right t o discontinue product ion and change specific ations and prices of its products at any
time and without notice. AMI´s products are intended for use in commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are
specificall y not recommended without addi t i onal mutual l y agreed upon processi ng by A MI f or such appli cations .
©Copyright 2000 American Microsystems, Inc. 2300 Buckskin Road Pocatello, Idaho 83201, U.S.A. All rights reserved.
