©2001 Fairchild Semiconductor Corporation 2N6784 Rev. A
2N6784
2.25A, 200V, 1.500 Ohm, N-Channel Power
MOSFET
The 2N6784 is an N-Channel enhancement mode silicon
gate power MOS field effect transistor designed for
applications such as switching regulators, switching
converters, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. This type can be operated directly from
integrated circuits.
Features
• 2.25A, 200V
•r
DS(ON)
= 1.500
Ω
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Majority Carrier Device
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-205AF
Ordering Information
PART NUMBER PACKAGE BRAND
2N6784 TO-205AF 2N6784
NOTE: When ordering, use the entire part number.
G
D
S
SOURCE
DRAIN
(CASE)
GATE
Data Sheet April 1998 File Number
1906.2
©2001 Fairchild Semiconductor Corporation 2N6784 Rev. A
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
2N6784 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
200 V
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DGR
200 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.25
1.5
A
A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
9A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
±
20 V
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
2.25 A
Pulse Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
9A
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
15 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.12 W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J,
T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 0.25mA, V
GS
= 0V 200 - - V
Gate to Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 0.5mA 2 - 4 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= 200V, V
GS
= 0V - - 250
µ
A
V
DS
= 160V, V
GS
= 0V, T
C
= 125
o
C - - 1000
µ
A
On-State Drain Current (Note 2) V
DS(ON)
I
D
= 2.25A, V
GS
= 10V - - 3.37 V
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V - -
±
100 nA
Drain to Source On Resistance (Note 2) r
DS(ON)
I
D
= 1.5A, V
GS
= 10V, T
A
= 25
o
C - 1.0 1.500
Ω
I
D
= 1.5A, V
GS
= 10V, T
A
= 125
o
C - - 2.81
Ω
Diode Forward Voltage V
SD
I
S
= 2.25A, V
GS
= 0V 0.7 - 1.5 V
Forward Transconductance (Note 2) gfs V
DS
= 5V, I
D
= 1.5A 0.9 1.3 2.7 S
Turn-On Delay Time t
d(ON)
V
DD
≅
75V, I
D
= 1.5A, R
G
= 50
Ω
(Figure 17) MOSFET Switching Times are
Essentially Independent of Operating
Temperature
- - 15 ns
Rise Time t
r
- - 20 ns
Turn-Off Delay Time t
d(OFF)
- - 30 ns
Fall Time t
f
- - 20 ns
Input Capacitance C
ISS
V
DS
= 25V, V
GS
= 0V, f = 1MHz
(Figure 14)
60 135 200 pF
Output Capacitance C
OSS
20 60 80 pF
Reverse Transfer Capacitance C
RSS
51625pF
Thermal Resistance Junction to Case R
θ
JC
- - 8.33
o
C/W
Thermal Resistance Junction to Ambient R
θ
JA
Free Air Operation - - 175
o
C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Reverse Recovery Time t
rr
T
J
= 150
o
C, I
SD
= 2.25A, dI
SD
/dt = 100A/
µ
s - 290 - ns
Reverse Recovered Charge Q
RR
T
J
= 150
o
C, I
SD
= 2.25A, dI
SD
/dt = 100A/
µ
s - 2.0 -
µ
C
NOTES:
2. Pulse test: pulse width
≤
300
µ
s, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal impedance curve (Figure 3).
2N6784
©2001 Fairchild Semiconductor Corporation 2N6784 Rev. A
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
0
50 100
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
150
25 75 125
2.5
2.0
1.5
1.0
0.5
10-5 10-4 10-3 10-2 10-1 110
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
1
0.1
0.01
SINGLE PULSE
0.5
0.2
0.1
0.05
0.02
0.01
PDM
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
t1
t2
THERMAL IMPEDANCE
110
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
50
20
10
1
0.1
0.05
ID, DRAIN CURRENT (A)
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
BY rDS(ON)
AREA IS LIMITED
OPERATION IN THIS
10µs
100µs
1ms
10ms
DC
100ms
1000
ID, DRAIN CURRENT (A)
010203040
2
4
6
8
10
50
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE TEST = 80µs
0
10V
5V 4V
VGS = 8V
9V
6V
7V
2N6784
©2001 Fairchild Semiconductor Corporation 2N6784 Rev. A
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Typical Performance Curves Unless Otherwise Specified (Continued)
0
2
0246 10
4
6
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
8
8
10
PULSE TEST = 80µs
4.0V
VGS = 6V
5V
9V
7V
10V
8V
06 8 12 142
VSD, GATE TO SOURCE VOLTAGE (V)
410
0.1
1.0
10
ID, DRAIN CURRENT (A)
TJ = 25oC
TJ = 125oC
TJ = -55oC
80µs PULSE TEST
0.5
0.2
5
2
ID, DRAIN CURRENT (A)
rDS(ON), ON-STATE RESISTANCE (Ω)
4
3
2
1
00246810
VGS = 20V
VGS = 10V
80µs PULSE TEST
NORMALIZED ON RESISTANCE
2.2
1.4
1.0
0.6
0.2 -40 0 40
TJ, JUNCTION TEMPERATURE (oC)
120
1.8
80
VGS = 10V, ID = 1.25A
160
NORMALIZED DRAIN TO SOURCE
1.25
1.05
0.95
0.85
0.75 -40 0 40
TJ, JUNCTION TEMPERATURE (oC)
120
1.15
80 160
BREAKDOWN VOLTAGE
500
100
0020 50
C, CAPACITANCE (pF)
300
VDS, DRAIN TO SOURCE VOLTAGE (V)
400
200
10 30 40
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
VGS = 0V, f = 1MHz
CRSS
COSS
CISS
2N6784
©2001 Fairchild Semiconductor Corporation 2N6784 Rev. A
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves Unless Otherwise Specified (Continued)
2.5
2.0
1.5
1.0
0.5
00246810
ID, DRAIN CURRENT (A)
gfs, TRANSCONDUCTANCE (S)
80µs PULSE TEST
TJ = 125oC
TJ = -55oC
TJ = 25oC
0 1.0 2.0 3.0 4.0
VSD, SOURCE TO DRAIN VOLTAGE (V)
10
1.0
0.1
IDR, REVERSE DRAIN CURRENT (A)
80µs PULSE TEST
TJ = 150oCTJ = 25oC
15
10
5
0024
Qg, TOTAL GATE CHARGE (nC)
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 4A
VDS = 40V
VDS = 160V
6810
VDS = 100V
2N6784
©2001 Fairchild Semiconductor Corporation 2N6784 Rev. A
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-
VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50kΩ
VDS
S
DUT
D
G
IG(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
IG(REF)
0
2N6784
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
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systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
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Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
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that has been discontinued by Fairchild semiconductor.
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Formative or
In Design
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OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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