LM25118MH/NOPB - NATIONAL SEMICONDUCTOR

(8) FB

VIN (1) (16) VCC

RT (3)

(18) HB

VOUT

AGND (6)

PGND (14)

DAP (EP)

(13) CSG

RAMP (5)

SS (7)

(12) CS

(15) LO

(10) VOUT

(19) HO

(20) HS

(9) COMP

LM25118MH

VIN

EN (4)

SYNC (11)

VCCX (17)

UVLO (2)

OFF

VEN(ON)

VEN(OFF)

010 20 30 40 50

VIN (V)

100

EFFICIENCY (%)

1 AMP

2 AMP

3 AMP

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Folder

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM25118

SNVS726F –JULY 2011–REVISED MARCH 2018

LM25118 Wide Voltage Range Buck-Boost Controller

1 Features

1• Input Voltage Operating Range From 3 V to 42 V

• Emulated Peak Current Mode Control

• Smooth Transition Between Step-Down and Step-

Up Modes

• Switching Frequency Programmable to 500 KHz

• Oscillator Synchronization Capability

• Internal High Voltage Bias Regulator

• Integrated High and Low-Side Gate Drivers

• Programmable Soft-Start Time

• Ultra-Low Shutdown Current

• Enable Input

• Wide Bandwidth Error Amplifier

• 1.5% Feedback Reference Accuracy

• Thermal Shutdown

• Package: 20-Pin HTSSOP (Exposed Pad)

• Create a Custom Design Using the LM25118 With

the WEBENCH®Power Designer

2 Applications

Industrial Buck-Boost Supplies

3 Description

The LM25118 wide voltage range Buck-Boost

switching regulator controller features all of the

functions necessary to implement a high-

performance, cost-efficient Buck-Boost regulator

using a minimum of external components. The Buck-

Boost topology maintains output voltage regulation

when the input voltage is either less than or greater

than the output voltage making it especially suitable

for automotive applications. The LM25118 operates

as a buck regulator while the input voltage is

sufficiently greater than the regulated output voltage

and gradually transitions to the buck-boost mode as

the input voltage approaches the output. This dual-

mode approach maintains regulation over a wide

range of input voltages with optimal conversion

efficiency in the buck mode and a glitch-free output

during mode transitions. This easy-to-use controller

includes drivers for the high-side buck MOSFET and

the low-side boost MOSFET. The control method of

the regulator is based upon current mode control

using an emulated current ramp. Emulated current

mode control reduces noise sensitivity of the pulse-

width modulation circuit, allowing reliable control of

the very small duty cycles necessary in high input

voltage applications. Additional protection features

include current limit, thermal shutdown, and an

enable input. The device is available in a power-

enhanced, 20-pin HTSSOP package featuring an

exposed die attach pad to aid thermal dissipation.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM25118 HTSSOP (20) 6.50 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic Efficiency vs VIN and IOUT, VOUT = 12 V

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 4

6 Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 7

6.6 Typical Characteristics............................................ 10

7 Detailed Description............................................ 12

7.1 Overview................................................................. 12

7.2 Functional Block Diagram....................................... 12

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 21

8 Application and Implementation ........................ 23

8.1 Application Information............................................ 23

8.2 Typical Application.................................................. 23

9 Power Supply Recommendations...................... 34

9.1 Bias Power Dissipation Reduction.......................... 34

9.2 Thermal Considerations.......................................... 35

10 Layout................................................................... 35

10.1 Layout Guidelines ................................................. 35

10.2 Layout Example .................................................... 35

11 Device and Documentation Support................. 36

11.1 Device Support...................................................... 36

11.2 Receiving Notification of Documentation Updates 36

11.3 Community Resources.......................................... 36

11.4 Trademarks........................................................... 36

11.5 Electrostatic Discharge Caution............................ 36

11.6 Glossary................................................................ 36

12 Mechanical, Packaging, and Orderable

Information........................................................... 37

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (July 2017) to Revision F Page

• Deleted roque text from ESD Ratings table. ......................................................................................................................... 6

Changes from Revision D (August 2014) to Revision E Page

• Moved the automotive device to a standalone data sheet (SNVSAX7)................................................................................. 1

• Changed language of WEBENCH list item; added additional content and links for WEBENCH further in data sheet ......... 1

• Moved the storage temp parameters to the Absolute Maximum Ratings .............................................................................. 6

• Changed junction temperature range from: ±150°C max to: –40°C to 150°C ...................................................................... 6

• Changed Handling Ratings table to ESD Ratings.................................................................................................................. 6

• Moved the junction temperature ranges in the Electrical Characteristics table to the test conditions statement .................. 7

• Removed the VOLL minimum value......................................................................................................................................... 8

• Removed the VOLH minimum value......................................................................................................................................... 8

• Added Community Resources section ................................................................................................................................ 36

Changes from Revision C (Novemeber 2013) to Revision D Page

• Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Device

Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and

Documentation Support; Mechanical, Packaging, and Ordering Information ........................................................................ 1

• Changed Removed footnote to "VCC, LO, VCCX, UVLO to GND" ....................................................................................... 6

Changes from Revision B (April, 2013) to Revision C Page

• Deleted VIN Range on Functional Block Diagram................................................................................................................. 12

• Changed Figure 19............................................................................................................................................................... 24

• Changed VIN Specification................................................................................................................................................... 24

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• Changed L1 Buck Mode Value............................................................................................................................................. 26

• Changed IRIPPLE(BUCK) Value.................................................................................................................................................. 26

• Changed Inductor Selection – L1 Text................................................................................................................................. 26

• Changed Equation 16........................................................................................................................................................... 26

• Changed Equation 17........................................................................................................................................................... 26

• Added Efficiency Parameter................................................................................................................................................. 26

• Changed I1(PEAK)Value........................................................................................................................................................... 27

• Changed I2(PEAK) Value.......................................................................................................................................................... 27

• Changed R13 = RSENSE Text ................................................................................................................................................ 27

• Added Equation 20 .............................................................................................................................................................. 27

• Added Equation 21 .............................................................................................................................................................. 27

• Changed Equation 24 .......................................................................................................................................................... 27

• Changed Equation 25 .......................................................................................................................................................... 27

• Changed R13(BUCK) Value..................................................................................................................................................... 27

• Changed R13(BUCK-BOOST) Value............................................................................................................................................ 27

• Added Inductor Current Limit Calculation Section................................................................................................................ 28

• Added Equation 29 .............................................................................................................................................................. 28

• Added Equation 31 .............................................................................................................................................................. 28

• Changed Equation 34........................................................................................................................................................... 28

• Changed ESRMAX Value....................................................................................................................................................... 28

• Deleted Previous Equation 17.............................................................................................................................................. 28

• Deleted Previous Equation 18.............................................................................................................................................. 28

• Changed C1 – C5 = Input Capacitors Text.......................................................................................................................... 29

• Changed R8, R9 Text........................................................................................................................................................... 30

• Changed R1, R3, C21 Text.................................................................................................................................................. 30

• Changed Equation 45 .......................................................................................................................................................... 30

• Changed R4, C18, C17 Text................................................................................................................................................ 31

• Changed DMIN to DMAX in Equation 47.................................................................................................................................... 31

• Changed DMAX Value............................................................................................................................................................ 31

• Changed DC Gain(MOD) Value............................................................................................................................................... 31

• Changed ESRZERO Value...................................................................................................................................................... 31

• Changed R4, C18, C17 Text................................................................................................................................................ 32

• Changed Figure 21............................................................................................................................................................... 33

• Changed Figure 22............................................................................................................................................................... 33

• Changed Figure 23............................................................................................................................................................... 33

• Added Figure 24................................................................................................................................................................... 33

• Added Figure 25................................................................................................................................................................... 33

• Added Figure 26................................................................................................................................................................... 33

Changes from Revision A (March 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 24

RAMP

AGND

VCC

PGND

COMP

VOUT

VIN

UVLO HO

VCCX

CSG

SYNC

10 11

Exposed Pad

on Bottom

(DAP)

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5 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP With Exposed Pad

Top View

Pin Functions

PIN TYPE DESCRIPTION

NO. NAME

1 VIN P/I Input supply voltage.

2 UVLO I

If the UVLO pin is below 1.23 V, the regulator will be in standby mode (VCC regulator running,

switching regulator disabled). When the UVLO pin exceeds 1.23 V, the regulator enters the

normal operating mode. An external voltage divider can be used to set an undervoltage

shutdown threshold. A fixed 5-µA current is sourced out of the UVLO pin. If a current limit

condition exists for 256 consecutive switching cycles, an internal switch pulls the UVLO pin to

ground and then releases.

3 RT I The internal oscillator frequency is set with a single resistor between this pin and the AGND pin.

The recommended frequency range is 50 kHz to 500 kHz.

4 EN I If the EN pin is below 0.5 V, the regulator will be in a low power state drawing less than 10 µA

from VIN. EN must be raised above 3 V for normal operation.

5 RAMP I Ramp control signal. An external capacitor connected between this pin and the AGND pin sets

the ramp slope used for emulated current mode control.

6 AGND G Analog ground.

7 SS I Soft-Start. An external capacitor and an internal 10-µA current source set the rise time of the

error amp reference. The SS pin is held low when VCC is less than the VCC undervoltage

threshold (< 3.7 V), when the UVLO pin is low (< 1.23 V), when EN is low (< 0.5 V) or when

thermal shutdown is active.

8 FB I Feedback signal from the regulated output. Connect to the inverting input of the internal error

amplifier.

9 COMP O Output of the internal error amplifier. The loop compensation network should be connected

between COMP and the FB pin.

10 VOUT I Output voltage monitor for emulated current mode control. Connect this pin directly to the

regulated output.

11 SYNC I Sync input for switching regulator synchronization to an external clock.

12 CS I Current sense input. Connect to the diode side of the current sense resistor.

13 CSG I Current sense ground input. Connect to the ground side of the current sense resistor.

14 PGND G Power Ground.

15 LO O Boost MOSFET gate drive output. Connect to the gate of the external boost MOSFET.

16 VCC P/I/O Output of the bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located

as close to the controller as possible.

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Pin Functions (continued)

PIN TYPE DESCRIPTION

NO. NAME

17 VCCX P/I Optional input for an externally supplied bias supply. If the voltage at the VCCX pin is greater

than 3.9 V, the internal VCC regulator is disabled and the VCC pin is internally connected to

VCCX pin supply. If VCCX is not used, connect to AGND.

18 HB I High-side gate driver supply used in bootstrap operation. The bootstrap capacitor supplies

current to charge the high-side MOSFET gate. This capacitor should be placed as close to the

controller as possible and connected between HB and HS.

19 HO O Buck MOSFET gate drive output. Connect to the gate of the high side buck MOSFET through a

short, low inductance path.

20 HS I Buck MOSFET source pin. Connect to the source terminal of the high-side buck MOSFET and

the bootstrap capacitor.

— EP — Exposed thermal pad. Solder to the ground plane under the IC to aid in heat dissipation.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VIN, EN, VOUT to GND –0.3 45 V

VCC, LO, VCCX, UVLO to GND –0.3 16 V

HB to HS –0.3 16 V

HO to HS –0.3 HB + 0.3 V

HS to GND –4 45 V

CSG, CS to GND –0.3 0.3 V

RAMP, SS, COMP, FB, SYNC, RT to GND –0.3 7 V

Junction temperature –40 150 °C

Storage temperature, Tstg –55 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2) ±1000

(1) Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated

in the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is

functional and the device should not be operated beyond such conditions. For ensured specifications and conditions, see Electrical

Characteristics.

(2) VIN ≥5.0 V is required to initially start the controller.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VIN(2) 3 42 V

VCC, VCCX 4.75 14 V

Junction temperature –40 +125 °C

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.

(2) JEDEC 2-Layer test board (JESD 51-3)

(3) JEDEC 4-Layer test board (JESD 51-7) with 4 thermal vias under the Exposed Pad

(4) JEDEC 4-Layer test board (JESD 51-7) with 12 thermal vias under the Exposed Pad

6.4 Thermal Information

THERMAL METRIC(1) LM25118

UNITPWP (HTSSOP)

20 PINS

RθJA Junction-to-ambient thermal resistance 110(2)

°C/W40(3)

35(4)

RθJC(bot) Junction-to-case (bottom) thermal resistance 4 °C/W

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(1) Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely

parametric norm at TJ= 25°C, and are provided for reference purposes only.

6.5 Electrical Characteristics

Unless otherwise specified, the following conditions apply: VIN = 24 V, VCCX = 0 V, EN = 5 V, RT = 29.11 kΩ, no load on LO

and HO. Typical values apply for TJ= 25°C; minimum and maximum values apply over the full junction temperature range for

operation: −40°C to +125°C.(1)(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN SUPPLY

IBIAS VIN operating current VCCX = 0 V 4.5 5.5 mA

IBIASX VIN operating current VCCX = 5 V 1 1.85 mA

ISTDBY VIN shutdown current EN = 0 V 1 10 µA

VCC REGULATOR

VCC(REG) VCC regulation VCCX = 0 V 6.8 7 7.2 V

VCC(REG) VCC regulation VCCX = 0 V, VIN = 6 V 5 5.25 5.5 V

VCC sourcing current limit VCC = 0 21 35 mA

VCCX switch threshold VCCX rising 3.68 3.85 4.02 V

VCCX switch hysterisis 0.2 V

VCCX switch RDS(ON) ICCX = 10 mA 5 12 Ω

VCCX switch leakage VCCX = 0 V 0.5 1 µA

VCCCX pulldown

resistance VCCX = 3 V 70 kΩ

VCC undervoltage lockout

voltage VCC rising 3.52 3.7 3.86 V

VCC undervoltage

hysterisis 0.21 V

HB DC bias current HB-HS = 15 V 205 260 µA

VC LDO mode turnoff 10 V

EN INPUT

VEN(OFF) EN input low threshold VEN falling 0.5 V

VEN(ON) EN input high threshold VEN rising 3 V

EN input bias current VEN = 3 V –1 1 µA

EN input bias current VEN = 0.5 V –1 1 µA

EN input bias current VEN = 42 V 50 µA

UVLO THRESHOLDS

UVLO UVLO standby threshold UVLO Rising 1.191 1.231 1.271 V

ΔUVLO UVLO threshold hysteresis 0.105 V

UVLO pullup current

source UVLO = 0 V 5 µA

UVLO pulldown RDS(ON) 100 200 Ω

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Electrical Characteristics (continued)

Unless otherwise specified, the following conditions apply: VIN = 24 V, VCCX = 0 V, EN = 5 V, RT = 29.11 kΩ, no load on LO

and HO. Typical values apply for TJ= 25°C; minimum and maximum values apply over the full junction temperature range for

operation: −40°C to +125°C.(1)(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SOFT START

SS current source SS = 0 V 7.5 10.5 13.5 µA

SS to FB offset FB = 1.23 V 150 mV

SS output low voltage Sinking 100 µA, UVLO = 0 V 7 mV

ERROR AMPLIFIER

VREF FB reference voltage Measured at FB pin,

FB = COMP 1.212 1.23 1.248 V

FB input bias current FB = 2 V 20 200 nA

COMP sink/source current 3 mA

AOL DC gain 80 dB

fBW Unity bain bandwidth 3 MHz

PWM COMPARATORS

tHO(OFF) Forced HO off-time 305 400 495 ns

TON(MIN) Minimum HO on-time 70 ns

COMP to comparator offset 200 mV

OSCILLATOR (RT PIN)

fSW1 Frequency 1 RT = 29.11 kΩ178 200 224 kHz

fSW2 Frequency 2 RT = 9.525 kΩ450 515 575 kHz

SYNC

Sync threshold falling 1.3 V

CURRENT LIMIT

VCS(TH) Cycle-by-cycle sense

voltage threshold (CS-

CSG) RAMP = 0 buck mode –103 –125 –147 mV

VCS(THX) Cycle-by-cycle sense

voltage threshold (CS-

CSG) RAMP = 0 buck-boost mode –218 –255 –300 mV

CS bias current CS = 0 V 45 60 µA

CSG bias current CSG = 0 V 45 60 µA

Current limit fault timer 256 cycles

RAMP GENERATOR

IR2 RAMP current 2 VIN = 12 V, VOUT = 12 V 95 115 135 µA

IR3 RAMP current 3 VIN = 5 V, VOUT = 12 V 65 80 95 µA

VOUT bias current VOUT = 42 V 245 µA

LOW-SIDE (LO) GATE DRIVER

VOLL LO low-state output voltage ILO = 100 mA 0.14 0.23 V

VOHL LO high-state output

voltage ILO = –100 mA

VOHL = VCC-VLO 0.25 V

LO rise time C-load = 1 nF, VCC = 8 V 16 ns

LO fall time C-load = 1 nF, VCC = 8 V 14 ns

IOHL Peak LO source current VLO = 0 V, VCC = 8 V 2.2 A

IOLL Peak LO sink current VLO = VCC = 8 V 2.7 A

HIGH-SIDE (HO) GATE DRIVER

VOLH HO low-state output

voltage IHO = 100 mA 0.135 0.21 V

VOHH HO high-state output

voltage IHO = –100 mA,

VOHH = VHB-VOH 0.25 V

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Electrical Characteristics (continued)

Unless otherwise specified, the following conditions apply: VIN = 24 V, VCCX = 0 V, EN = 5 V, RT = 29.11 kΩ, no load on LO

and HO. Typical values apply for TJ= 25°C; minimum and maximum values apply over the full junction temperature range for

operation: −40°C to +125°C.(1)(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) When the duty cycle exceeds 75%, the LM25118 controller gradually phases into the Buck-Boost mode.

HO rise time C-load = 1 nF, VCC = 8 V 14 ns

HO fall time C-load = 1 nF, VCC = 8 V 12 ns

IOHH Peak HO source current VHO = 0 V, VCC = 8 V 2.2 A

IOLH Peak HO sink current VHO = VCC = 8 V 3.5 A

HB-HS undervoltage

lockout 3 V

BUCK-BOOST CHARACTERISTICS(2)

Buck-boost mode Buck duty cycle 69% 75% 80%

THERMAL

TSD Thermal shutdown junction

temperature 165 °C

ΔTSD Thermal shutdown

hysterisis 25 °C

0 1 2 3 4 5 6 7 8

OUTPUT VOLTAGE (V)

0.5

1.5

2.5

3.5

CURRENT (A)

LO Source

LO Sink

HO Sink

HO Source

10k 100k 1M 10M

FREQUENCY (Hz)

-10

GAIN (dB)

-30

150

120

PHASE (°)

0 10 20 30 40 50

VCC (V)

IVCC (mA)

02 4 6 8 10 12

VIN (V)

VCC (V)

65 110

-275

-100

CURRENT LIMIT THRESHOLD (mV)

VOUT/VIN DC (%)

70 75 80 85 90 95 100 105

-250

-225

-200

-175

-150

-125

010 20 30 40 50

VIN (V)

100

EFFICIENCY (%)

1 AMP

2 AMP

3 AMP

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6.6 Typical Characteristics

Figure 1. Efficiency vs VIN and IOUT VOUT = 12 V Figure 2. Current Limit Threshold vs VOUT/VIN VOUT = 12 V

Figure 3. VCC vs VIN Figure 4. VCC vs IVCC

Figure 5. Error Amplifier Gain/Phase Figure 6. LO and HO Peak Gate Current vs Output Voltage

VCC = 8 V

020 40 60 80 100 120 140 160

RT (k:)

100

200

300

400

500

600

FOSC (kHz)

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Typical Characteristics (continued)

Figure 7. Oscillator Frequency vs RT

VOUT

VIN VCC

REGULATOR

Vin

LEVEL

SHIFT

THERMAL

SHUTDOWN

LM25118

VCC UVLO

HB UVLO

ERROR

AMP

COMP

TRACK

and

HOLD

CLK

OSCILLATOR

AGND

CLK

CSG

CLK

RAMP GENERATOR

= 5 PA x Vin +

SHUTDOWN

AND STANDBY

MODE

CONTROL

PWM

I-LIMIT

RAMP

Vin

10 PA

Vin

IRAMP BUCK-BOOST

MODE CONTROL

PGND

VOUT

3.9V

HICCUP MODE

FAULT TIMER

UVLO

VIN

VCCX

SYNC

A=10

C12

C11

1.23V

C13

DISABLE

1.23V

IRAMP (buck-boost)

C10

50 PA

5 PA

IRAMP (buck) = (5PA x (Vin -Vout)) + 50 PA

Vth(buck) = 1.25V

(buck-boost) = 2.50V

Vth

10 Rs V/A

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7 Detailed Description

7.1 Overview

The LM25118 high voltage switching regulator features all of the functions necessary to implement an efficient

high voltage buck or buck-boost regulator using a minimum of external components. The regulator switches

smoothly from buck to buck-boost operation as the input voltage approaches the output voltage, allowing

operation with the input greater than or less than the output voltage. This easy-to-use regulator integrates high-

side and low-side MOSFET drivers capable of supplying peak currents of 2 A. The regulator control method is

based on current mode control using an emulated current ramp. Peak current mode control provides inherent line

feedforward, cycle-by-cycle current limiting and ease-of-loop compensation. The use of an emulated control ramp

reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing of very small duty

cycles necessary in high input voltage applications. The operating frequency is user programmable from 50 kHz

to 500 kHz. An oscillator synchronization pin allows multiple LM25118 regulators to self synchronize or be

synchronized to an external clock. Fault protection features include current limiting, thermal shutdown, and

remote shutdown capability. An undervoltage lockout input allows regulator shutdown when the input voltage is

below a user selected threshold, and a low state at the enable pin will put the regulator into an extremely low

current shutdown state. The device is available in the 20-pin HTSSOP package featuring an exposed pad to aid

in thermal dissipation.

7.2 Functional Block Diagram

VOUT

CSG

LM25118

VIN

Q2 (OFF)

Buck Switch

Current

Diode

Current

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7.3 Feature Description

A buck-boost regulator can maintain regulation for input voltages either higher or lower than the output voltage.

The challenge is that buck-boost power converters are not as efficient as buck regulators. The LM25118 has

been designed as a dual-mode controller whereby the power converter acts as a buck regulator while the input

voltage is above the output. As the input voltage approaches the output voltage, a gradual transition to the buck-

boost mode occurs. The dual mode approach maintains regulation over a wide range of input voltages, while

maintaining the optimal conversion efficiency in the normal buck mode. The gradual transition between modes

eliminates disturbances at the output during transitions. Figure 8 shows the basic operation of the LM25118

regulator in the buck mode. In buck mode, transistor Q1 is active and Q2 is disabled. The inductor current ramps

in proportion to the Vin – Vout voltage difference when Q1 is active and ramps down through the recirculating

diode D1 when Q1 is off. The first order buck mode transfer function is VOUT/VIN = D, where D is the duty cycle

of the buck switch, Q1.

Figure 8. Buck Mode Operation

18 17 16 15 14 13 120

100

DUTY CYCLE (%)

VIN (V)

VOUT

CSG

LM25118 D1

Buck Switch

Current

Diode

Current

VIN

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Feature Description (continued)

Figure 9 shows the basic operation of buck-boost mode. In buck-boost mode, both Q1 and Q2 are active for the

same time interval each cycle. The inductor current ramps up (proportional to VIN) when Q1 and Q2 are active

and ramps down through the recirculating diode during the off-time. The first order buck-boost transfer function is

VOUT/VIN = D/(1 – D), where D is the duty cycle of Q1 and Q2.

Figure 9. Buck-Boost Mode Operation

Figure 10. Mode Dependence on Duty Cycle (VOUT =12 V)

SYNC

LM25118

SYNC

LM25118

UP TO FIVE

LM25118 DEVICES

RT = 6.4 x 109

f- 3.02 x 103

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Feature Description (continued)

7.3.1 UVLO

An undervoltage lockout pin is provided to disable the regulator when the input is below the desired operating

range. If the UVLO pin is below 1.13 V, the regulator enters a standby mode with the outputs disabled, but with

VCC regulator operating. If the UVLO input exceeds 1.23 V, the regulator will resume normal operation. A

voltage divider from the input to ground can be used to set a VIN threshold to disable the regulator in brownout

conditions or for low input faults.

If a current limit fault exists for more than 256 clock cycles, the regulator will enter a hiccup mode of current

limiting and the UVLO pin will be pulled low by an internal switch. This switch turns off when the UVLO pin

approaches ground potential allowing the UVLO pin to rise. A capacitor connected to the UVLO pin will delay the

return to a normal operating level and thereby set the off-time of the hiccup mode fault protection. An internal 5-

µA pullup current pulls the UVLO pin to a high state to ensure normal operation when the VIN UVLO function is

not required and the pin is left floating.

7.3.2 Oscillator and Sync Capability

The LM25118 oscillator frequency is set by a single external resistor connected between the RT pin and the

AGND pin. The RTresistor should be located very close to the device and connected directly to the pins of the

IC. To set a desired oscillator frequency (f), the necessary value for the RTresistor can be calculated from

Equation 1:

(1)

The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must be

of higher frequency than the free-running frequency set by the RTresistor. A clock circuit with an open-drain

output is the recommended interface from the external clock to the SYNC pin. The clock pulse duration should

be greater than 15 ns.

Figure 11. Sync From Multiple Devices

Multiple LM25118 devices can be synchronized together simply by connecting the SYNC pins together. In this

configuration, all of the devices will be synchronized to the highest frequency device. The diagram in Figure 11

shows the SYNC input and output features of the LM25118. The internal oscillator circuit drives the SYNC pin

with a strong pulldown and weak pullup inverter. When the SYNC pin is pulled low, either by the internal

oscillator or an external clock, the ramp cycle of the oscillator is terminated and forced 400 ns off-time is initiated

before a new oscillator cycle begins. If the SYNC pins of several LM25118 ICs are connected together, the IC

with the highest internal clock frequency will pull all the connected SYNC pins low and terminate the oscillator

ramp cycles of the other ICs. The LM25118 with the highest programmed clock frequency will serve as the

master and control the switching frequency of all the devices with lower oscillator frequencies.

Emulated

Ramp

Ton

Buck:

Buck - Boost:

Pedestal Level = (volts/amp)

Rsx10

CRAMP

tON

50+)- VOUTVIN(x

CRAMP

tON

50+VINx

SYNC

100 PA

DEADTIME

ONE - SHOT

1.23V

I 1/RT

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Feature Description (continued)

Figure 12. Simplified Oscillator and Block Diagram With Sync I/O Circuit

7.3.3 Error Amplifier and PWM Comparator

The internal high gain error amplifier generates an error signal proportional to the difference between the

regulated output voltage and an internal precision reference (1.23 V). The output of the error amplifier is

connected to the COMP pin. Loop compensation components, typically a type II network shown in Figure 18 are

connected between the COMP and FB pins. This network creates a low-frequency pole, a zero, and a noise

reducing high-frequency pole. The PWM comparator compares the emulated current sense signal from the

RAMP generator to the error amplifier output voltage at the COMP pin. The same error amplifier is used for

operation in buck and buck-boost mode.

Figure 13. Composition of Emulated Current Signal

gm x L

CRAMP

RS x A =

gm x L

CRAMP =A x RS

5 PA

Vx VIN + 50 PA

IRAMP (buck - boost) =

5 PA

Vx (VIN - VOUT) + 50 PA

IRAMP (buck) =

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Feature Description (continued)

7.3.4 Ramp Generator

The ramp signal of a pulse-width modulator with current mode control is typically derived directly from the buck

switch drain current. This switch current corresponds to the positive slope portion of the inductor current signal.

Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and

provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current

signal for PWM control is the large leading edge spike due to circuit parasitics. The leading edge spike must be

filtered or blanked to avoid early termination of the PWM pulse. Also, the current measurement may introduce

significant propagation delays. The filtering, blanking time, and propagation delay limit the minimal achievable

pulse width. In applications where the input voltage may be relatively large in comparison to the output voltage,

controlling a small pulse width is necessary for regulation. The LM25118 uses a unique ramp generator which

does not actually measure the buck switch current but instead creates a signal representing or emulating the

inductor current. The emulated ramp provides signal to the PWM comparator that is free of leading edge spikes

and measurement or filtering delays. The current reconstruction is comprised of two elements: a sample-and-

hold pedestal level and a ramp capacitor that is charged by a controlled current source. See Figure 13 for details.

The sample-and-hold pedestal level is derived from a measurement of the recirculating current through a current

sense resistor in series with the recirculating diode of the buck regulator stage. A small value current-sensing

resistor is required between the recirculating diode anode and ground. The CS and CSG pins should be Kelvin

connected directly to the sense resistor. The voltage level across the sense resistor is sampled and held just

prior to the onset of the next conduction interval of the buck switch. The current sensing and sample-and-hold

provide the DC level of the reconstructed current signal. The sample and hold of the recirculating diode current is

valid for both buck and buck-boost modes. The positive slope inductor current ramp is emulated by an external

capacitor connected from the RAMP pin to the AGND and an internal voltage controlled current source. In buck

mode, the ramp current source that emulates the inductor current is a function of the VIN and VOUT voltages per

Equation 2.

(2)

In buck-boost mode, the ramp current source is a function of the input voltage VIN, per Equation 3.

(3)

Proper selection of the RAMP capacitor (CRAMP) depends upon the value of the output inductor (L) and the

current sense resistor (RS). For proper current emulation, the sample and hold pedestal value and the ramp

amplitude must have the same relative relationship to the actual inductor current. That is:

where

• gmis the ramp generator transconductance (5 µA/V)

• A is the current sense amplifier gain (10 V/V) (4)

The ramp capacitor should be located very close to the device and connected directly to the RAMP and AGND

pins.

1 +VOUT

Iout x VIN

A = 10k

1k + RG

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Feature Description (continued)

The relationship between the average inductor current and the pedestal value of the sampled inductor current

can cause instability in certain operating conditions. This instability is known as sub-harmonic oscillation, which

occurs when the inductor ripple current does not return to its initial value by the start of the next switching cycle.

Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch

node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this

oscillation. The 50 µA of offset current provided from the emulated current source adds enough slope

compensation to the ramp signal for output voltages less than or equal to 12 V. For higher output voltages,

additional slope compensation may be required. In such applications, the ramp capacitor can be decreased from

the nominal calculated value to increase the ramp slope compensation.

The pedestal current sample is obtained from the current sense resistor (Rs) connected to the CS and CSG pins.

It is sometimes helpful to adjust the internal current sense amplifier gain (A) to a lower value to obtain the higher

current limit threshold. Adding a pair of external resistors RG in a series with CS and CSG as shown in Figure 14

reduces the current sense amplifier gain A according to Equation 5.

(5)

7.3.5 Current Limit

In the buck mode the average inductor current is equal to the output current (Iout). In buck-boost mode the

average inductor current is approximately equal to:

(6)

Consequently, the inductor current in buck-boost mode is much larger especially when VOUT is large relative to

VIN. The LM25118 provides a current monitoring scheme to protect the circuit from possible overcurrent

conditions. When set correctly, the emulated current sense signal is proportional to the buck switch current with a

scale factor determined by the current sense resistor. The emulated ramp signal is applied to the current limit

comparator. If the peak of the emulated ramp signal exceeds 1.25 V when operating in the buck mode, the PWM

cycle is immediately terminated (cycle-by-cycle current limiting). In buck-boost mode the current limit threshold is

increased to 2.50 V to allow higher peak inductor current. To further protect the external switches during

prolonged overload conditions, an internal counter detects consecutive cycles of current limiting. If the counter

detects 256 consecutive current limited PWM cycles, the LM25118 enters a low power dissipation hiccup mode.

In the hiccup mode, the output drivers are disabled, the UVLO pin is momentarily pulled low, and the soft-start

capacitor is discharged. The regulator is restarted with a normal soft-start sequence once the UVLO pin charges

back to 1.23 V. The hiccup mode off-time can be programmed by an external capacitor connected from UVLO

pin to ground. This hiccup cycle will repeat until the output overload condition is removed.

0100 200 300 400 500 600

FREQUENCY (kHz)

0.75

0.8

0.85

0.9

0.95

MAX DUTY CYCLE

CSG

TRACK

and HOLD

RAMP

1k RG

10k

0.2V

RAMP

RESET

Vth

CRAMP

CURRENT LIMIT

COMPARATOR

IRAMP

CURRENT SENSE

AMPLIFIER

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Feature Description (continued)

In applications with low output inductance and high input voltage, the switch current may overshoot due to the

propagation delay of the current limit comparator and control circuitry. If an overshoot should occur, the sample-

and-hold circuit will detect the excess recirculating diode current. If the sample-and-hold pedestal level exceeds

the internal current limit threshold, the buck switch will be disabled and will skip PWM cycles until the inductor

current has decayed below the current limit threshold. This approach prevents current runaway conditions due to

propagation delays or inductor saturation since the inductor current is forced to decay before the buck switch is

turned on again.

Figure 14. Current Limit and Ramp Circuit

7.3.6 Maximum Duty Cycle

Each conduction cycle of the buck switch is followed by a forced minimum off-time of 400 ns to allow sufficient

time for the recirculating diode current to be sampled. This forced off-time limits the maximum duty cycle of the

controller. The actual maximum duty cycle will vary with the operating frequency of Equation 7.

DMAX = 1 - f × 400 × 10–9

where

• f is the oscillator frequency in Hz (7)

Figure 15. Maximum Duty Cycle vs Frequency

Vout

D = Vin + Vout

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Feature Description (continued)

Limiting the maximum duty cycle will limit the maximum boost ratio (VOUT/VIN) while operating in buck-boost

mode. For example, from Figure 15, at an operating frequency of 500 kHz, DMAX is 80%. Using the buck-boost

transfer function.

(8)

with

• D = 80%, solving for VOUT results in

• VOUT = 4 × VIN

With a minimum input voltage of 5 V, the maximum possible output voltage is 20 V at f = 500 kHz. The buck-

boost step-up ratio can be increased by reducing the operating frequency which increases the maximum duty

cycle.

7.3.7 Soft Start

The soft-start feature allows the regulator to gradually reach the initial steady-state operating point, thus reducing

start-up stresses and surges. The internal 10-µA soft-start current source gradually charges an external soft-start

capacitor connected to the SS pin. The SS pin is connected to the positive input of the internal error amplifier.

The error amplifier controls the pulse-width modulator such that the FB pin approximately equals the SS pin as

the SS capacitor is charged. Once the SS pin voltage exceeds the internal 1.23-V reference voltage, the error

amp is controlled by the reference instead of the SS pin. The SS pin voltage is clamped by an internal amplifier

at a level of 150 mV above the FB pin voltage. This feature provides a soft-start controlled recovery in the event

a severe overload pulls the output voltage (and FB pin) well below normal regulation but doesn’t persist for 256

clock cycles.

Various sequencing and tracking schemes can be implemented using external circuits that limit or clamp the

voltage level of the SS pin. The SS pin acts as a noninverting input to the error amplifier anytime SS voltage is

less than the 1.23-V reference. In the event a fault is detected (overtemperature, VCC undervoltage, hiccup

current limit), the soft-start capacitor will be discharged. When the fault condition is no longer present, a new soft-

start sequence will begin.

7.3.8 HO Output

The LM25118 contains a high-side, high-current gate driver and associated high voltage level shift. This gate

driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.1-µF ceramic

capacitor, connected with short traces between the HB pin and HS pin is recommended for most circuit

configurations. The size of the bootstrap capacitor depends on the gate charge of the external FET. During the

off-time of the buck switch, the HS pin voltage is approximately –0.5 V and the bootstrap capacitor is charged

from VCC through the internal bootstrap diode. When operating with a high PWM duty cycle, the buck switch will

be forced off each cycle for 400 ns to ensure that the bootstrap capacitor is recharged.

7.3.9 Thermal Protection

Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction

temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power reset state,

disabling the output driver and the bias regulator. This protection is provided to prevent catastrophic failures from

accidental device overheating.

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7.4 Device Functional Modes

Figure 10 shows how duty cycle effects the operational mode and is useful for reference in the following

discussions. Initially, only the buck switch is active and the buck duty cycle increases to maintain output

regulation as VIN decreases. When VIN is approximately equal to 15.5 V, the boost switch begins to operate with

a low duty cycle. If VIN continues to fall, the boost switch duty cycle increases and the buck switch duty cycle

decreases until they become equal at VIN = 13.2 V.

7.4.1 Buck Mode Operation: VIN > VOUT

The LM25118 buck-boost regulator operates as a conventional buck regulator with emulated current mode

control while VIN is greater than VOUT and the buck mode duty cycle is less than 75%. In buck mode, the LO

gate drive output to the boost switch remains low.

7.4.2 Buck-Boost Mode Operation: VIN ≊≊ VOUT

When VIN decreases relative to VOUT, the duty cycle of the buck switch will increase to maintain regulation.

Once the duty cycle reaches 75%, the boost switch starts to operate with a very small duty cycle. As VIN is

further decreased, the boost switch duty cycle increases until it is the same as the buck switch. As VIN is further

decreased below VOUT, the buck and boost switch operate together with the same duty cycle and the regulator

is in full buck-boost mode. This feature allows the regulator to transition smoothly from buck to buck-boost mode.

Note that the regulator can be designed to operate with VIN less than 4 V, but VIN must be at least 5 V during

start-up. Figure 16 shows a timing illustration of the gradual transition from buck to buck-boost mode when the

input voltage ramps downward over a few switching cycles.

Figure 16. Buck (HO) and Boost (LO) Switch Duty Cycle vs. Time,

Illustrating Gradual Mode Change With Decreasing Input Voltage

Vcc

Vin

Internal Enable Signal

3.5V

VIN and VCC

10V

3.7V

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Device Functional Modes (continued)

7.4.3 High Voltage Start-Up Regulator

The LM25118 contains a dual-mode, high voltage linear regulator that provides the VCC bias supply for the

PWM controller and the MOSFET gate driver. The VIN input pin can be connected directly to input voltages as

high as 42 V. For input voltages below 10 V, an internal low dropout switch connects VCC directly to VIN. In this

supply range, VCC is approximately equal to VIN. For VIN voltages greater than 10 V, the low dropout switch is

disabled and the VCC regulator is enabled to maintain VCC at approximately 7 V. A wide operating range of 4 V

to 42 V (with a startup requirement of at least 5 V) is achieved through the use of this dual-mode regulator.

The output of the VCC regulator is current limited to 35 mA, typical. Upon power up, the regulator sources

current into the capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the VCC under-

voltage threshold of 3.7 V and the UVLO input pin voltage is greater than 1.23 V, the gate driver outputs are

enabled and a soft-start sequence begins. The gate driver outputs remain enabled until VCC falls below 3.5 V or

the voltage at the UVLO pin falls below 1.13 V.

In many applications, the regulated output voltage or an auxiliary supply voltage can be applied to the VCCX pin

to reduce the IC power dissipation. For output voltages between 4 V and 15 V, VOUT can be connected directly

to VCCX. When the voltage at the VCCX pin is greater than 3.85 V, the internal VCC regulator is disabled and

an internal switch connects VCCX to VCC, reducing the internal power dissipation.

In high voltage applications, take extra care to ensure the VIN pin voltage does not exceed the absolute

maximum voltage rating of 45 V. During line or load transients, voltage ringing on the VIN line that exceeds the

absolute maximum rating can damage the IC. Both careful PCB layout and the use of quality bypass capacitors

located close to the VIN and GND pins are essential.

Figure 17. VIN and VCC Sequencing

7.4.4 Enable

The LM25118 contains an enable function which provides a very low input current shutdown mode. If the EN pin

is pulled below 0.5 V, the regulator enters shutdown mode, drawing less than 10 µA from the VIN pin. Raising

the EN input above 3 V returns the regulator to normal operation. The EN pin can be tied directly to the VIN pin if

this function is not needed. It must not be left floating. A 1-MΩpullup resistor to VIN can be used to interface with

an open-collector or open-drain control signal.

(8) FB

VIN (1) (16) VCC

RT (3)

(18) HB

VOUT

AGND (6)

PGND (14)

DAP (EP)

(13) CSG

RAMP (5)

SS (7)

(12) CS

(15) LO

(10) VOUT

(19) HO

(20) HS

(9) COMP

LM25118MH

VIN

EN (4)

SYNC (11)

VCCX (17)

UVLO (2)

OFF

VEN(ON)

VEN(OFF)

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM25118 high voltage switching regulator features all of the functions necessary to implement an efficient

high voltage buck or buck-boost regulator using a minimum of external components. A buckboost regulator can

maintain regulation for input voltages either higher or lower than the output voltage.

8.2 Typical Application

Figure 18. Typical Application Circuit

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Typical Application (continued)

Figure 19. 12-V, 3-A Typical Application Schematic

8.2.1 Design Requirements

The procedure for calculating the external components is illustrated with the following design example. The

designations used in the design example correlate to the Figure 19. The design specifications are:

• VOUT = 12 V

• VIN = 5 V to 42 V

• f = 300 kHz

• Minimum load current (CCM operation) = 600 mA

• Maximum load current = 3 A

Iripple

Ipk+

Io Buck

Ipk-

Iripple

1/Fs

L1 Current

Io/(1-D) B-B

RT = 6.4 x 109

f- 3.02 x 103

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Typical Application (continued)

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM25118 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 R7 = RT

RT sets the oscillator switching frequency. Generally speaking, higher operating frequency applications will use

smaller components, but have higher switching losses. An operating frequency of 300 kHz was selected for this

example as a reasonable compromise for both component size and efficiency. The value of RTcan be calculated

as:

(9)

therefore, R7 = 18.3 kΩ

Figure 20. Inductor Current Waveform

OUT OUT IN(MIN) RIPPLE(BUCK-BOOST)

2(PEAK) IN(MIN) TOL

I (V V ) I

IV 2(1 L )



Ku 

RIPPLE(BUCK)

OUT

1(PEAK) TOL

I2(1 L )



K 

IN(MIN) OUT

OUT IN(MIN) RIPPLE

V (V )

L1 Buck-Boost Mode

(V V ) f I

 u u

OUT IN(MAX) OUT

IN(MAX) RIPPLE

V (V V )

L1 Buck Mode

V f I



u u

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Typical Application (continued)

8.2.2.3 Inductor Selection – L1

The inductor value is determined based upon the operating frequency, load current, ripple current, and the input

and output voltages. See Figure 20 for details.

To keep the circuit in continuous conduction mode (CCM), the maximum ripple current IRIPPLE should be less

than twice the minimum load current. For the specified minimum load of 0.6 A, the maximum ripple current is 1.2

Ap-p. Also, the minimum value of L must be calculated both for a buck and buck-boost configurations. The final

value of inductance will generally be a compromise between the two modes. It is desirable to have a larger value

inductor for buck mode, but the saturation current rating for the inductor must be large for buck-boost mode,

resulting in a physically large inductor. Additionally, large value inductors present buck-boost mode loop

compensation challenges which will be discussed in Error Amplifier Configuration . For the design example, the

inductor values in both modes are calculated as:

(10)

where

• VOUT is the output voltage

• VIN(MAX) is the maximum input voltage

• f is the switching frequency

• IRIPPLE is the selected inductor peak to peak ripple current (1.2 A selected for this example)

• VIN(MIN) is the minimum input voltage

• (11)

The resulting inductor values are:

L1 = 23.8 µH, Buck Mode (12)

L1 = 9.8 µH, Buck-Boost mode (13)

A 10-µH inductor was selected which is a compromise between these values, while favoring the buck-boost

mode. As illustrated in the compensation section, the inductor value should be as low as possible to move the

buck-boost right-half-plane zero to a higher frequency. The ripple current is then rechecked with the selected

inductor value using Equation 10 and Equation 11.

IRIPPLE(BUCK) = 2.86 A (14)

IRIPPLE(BUCK-BOOST) = 1.17 A (15)

Because the inductor selected is lower than calculated for the Buck mode, the minimum load current for CCM in

buck mode is 1.42 A at maximum VIN.

With a 10-µH inductor, the worst case peak inductor currents can be estimated for each case, assuming a 20%

inductor value tolerance and 80% efficiency of the converter.

(16)

where

•ηis efficiency

• LTOL is the inductor tolerance (17)

C15 = CRAMP = L x 10-6

2 x RSENSE

(BUCK-BOOST) IN(MIN) OUT RIPPLE(BUCK-BOOST)

OUT BUCK-BOOST

IN(MIN)

2.5 (1 M)

R13 V V I

10 K

V 2

˜ 

§ ·



˜ ˜  ˜

¨ ¸

(BUCK) RIPPLE(BUCK)

OUT BUCK

1.25(1 M)

R13 I

10 K



§ ·

˜  ˜

¨ ¸

BUCK BOOST IN(MIN)

K 1 V

t 

BUCK IN(MAX) OUT

K 1 V V

t 



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Typical Application (continued)

For this example, Equation 16 and Equation 17 yield:

I1(PEAK) = 5.33 A (18)

I2(PEAK) = 13.4 A (19)

An acceptable current limit setting would be 6.7 A for buck mode because the LM25118 automatically doubles

the current limit threshold in buck-boost mode. The selected inductor must have a saturation current rating at

least as high as the buck-boost mode cycle-by-cycle current limit threshold, in this case at least 13.5 A. A 10-µH,

15-A inductor was chosen for this application.

8.2.2.4 R13 = RSENSE

To select the current sense resistor, begin by calculating the minimum K values for each mode using

Equation 20 and Equation 21. K represents the slope compensation of the controller and is different for each

mode, KBUCK and KBUCK-BOOST. KBUCK and KBUCK-BOOST were selected to be 1.33 and 3, respectively.

(20)

(21)

KBUCK = 1.33 (22)

KBUCK-BOOST = 3 (23)

Use Equation 24 and Equation 25 to calculate RSENSE for each mode of operation. A design margin, M, should be

selected between 10%-30% to allow for component tolerances. For this design M was selected to be 10%.

(24)

(25)

R13(BUCK) = 19.89 mΩ(26)

R13(BUCK-BOOST) = 15.5 mΩ(27)

An RSENSE value of no more than 15.5 mΩmust be used to ensure the required maximum output current in the

buck-boost mode. A standard value of 15 mΩwas selected for this design.

8.2.2.5 C15 = CRAMP

With the inductor value selected, the value of C3 necessary for the emulation ramp circuit is:

(28)

With the inductance value (L1) selected as 10 µH, the calculated value for CRAMP is 333 pF. A standard value of

330 pF was selected.

OUT

MAX OUT IN(MIN) RIPPLE(BUCK-BOOST)

OUT

IN(MIN)

ESR V V I

V 2



˜ 

OUT MAX OUT

MIN MAX

OUT IN(MIN) OUT

I D V

C With D

f V V V

u ' 

6OUT

IN(MIN) OUT

LIMIT(BUCK-BOOST)

50 10 V

2.5 C15 f (V V )

I10 R13



u u



u u 

6OUT

IN(MAX)

LIMIT(BUCK)

50 10 V

1.25 C15 f V

I10 R13



u u



u u

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Typical Application (continued)

8.2.2.6 Inductor Current Limit Calculation

The current limit for each mode can be calculated using Equation 29 and Equation 31. If the peak current limit is

less than the calculated inductor peak current, the R13 and C15 need to be recalculated. This can be done by

increasing the previous K values or M and reiterating the calculations.

(29)

ILIMIT (BUCK) = 7.37 A (30)

(31)

ILIMIT (BUCK-BOOST) = 14.29 A (32)

8.2.2.7 C9 - C12 = Output Capacitors

In buck-boost mode, the output capacitors C9 – C12 must supply the entire output current during the switch on-

time. For this reason, the output capacitors are chosen for operation in buck-boost mode, the demands being

much less in buck operation. Both bulk capacitance and ESR must be considered to ensure a given output ripple

voltage. Buck-boost mode capacitance can be estimated from:

(33)

ESR requirements can be estimated from:

(34)

For this example, with a ΔVOUT (output ripple) of 50 mV:

CMIN = 141 µF (35)

ESRMAX = 4.6 mΩ(36)

If hold-up times are a consideration, the values of input and output capacitors must be increased appropriately.

Note that it is usually advantageous to use multiple capacitors in parallel to achieve the ESR value required.

Also, it is good practice to put a 0.1-µF to 0.47-µF ceramic capacitor directly on the output pins of the supply to

reduce high-frequency noise. Ceramic capacitors have good ESR characteristics, and are a good choice for input

and output capacitors. Note that the effective capacitance of ceramic capacitors decreases with DC bias. For

larger bulk values of capacitance, a low-ESR electrolytic is usually used. However, electrolytic capacitors have

poor tolerance, especially over temperature, and the selected value should be selected larger than the calculated

value to allow for temperature variation. Allowing for component tolerances, the following values of Cout were

chosen for this design example:

Two 180-µF Oscon electrolytic capacitors for bulk capacitance

Two 47-µF ceramic capacitors to reduce ESR

Two 0.47-µF ceramic capacitors to reduce spikes at the output

8.2.2.8 D1

Reverse recovery currents degrade performance and decrease efficiency. For these reasons, a Schottky diode of

appropriate ratings should be used for D1. The voltage rating of the boost diode should be equal to VOUT plus

some margin.

IRMS(BUCK-BOOST) = 1 - D

IOUT D(1 -D)

IRMS(BUCK) = IOUT D(1 -D)

LM25118

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Typical Application (continued)

8.2.2.9 D4

A Schottky type recirculating diode is required for all LM25118 applications. The near ideal reverse recovery

characteristics and low forward voltage drop are particularly important diode characteristics for high input voltage

and low output voltage applications. The reverse recovery characteristic determines how long the current surge

lasts each cycle when the buck switch is turned on. The reverse recovery characteristics of Schottky diodes

minimize the peak instantaneous power in the buck switch during the turn-on transition. The reverse breakdown

rating of the diode should be selected for the maximum VIN plus some safety margin.

The forward voltage drop has a significant impact on the conversion efficiency, especially for applications with a

low output voltage. Rated current for diodes vary widely from various manufacturers. For the LM25118 this

current is user selectable through the current sense resistor value. Assuming a worst-case, 0.6-V drop across the

diode, the maximum diode power dissipation can be high. The diode should have a voltage rating of VIN and a

current rating of IOUT. A conservative design would at least double the advertised diode rating because

specifications between manufacturers vary. For the reference design, a 100-V, 10-A Schottky in a D2PAK

package was selected.

8.2.2.10 C1 – C5 = Input Capacitors

A typical regulator supply voltage has a large source impedance at the switching frequency. Good-quality input

capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current

during the buck switch on-time. When the buck switch turns on, the current into the buck switch steps from zero

to the lower peak of the inductor current waveform, then ramps up to the peak value, and then drops to the zero

at turnoff. The RMS current rating of the input capacitors depends on which mode of operation is most critical.

(37)

The RMS current demand on the input capacitor(s) is at the maximum value when the duty cycle is at 50%.

(38)

Checking both modes of operation we find:

IRMS(BUCK) = 1.5 A (39)

IRMS(BUCK-BOOST) = 4.7 A (40)

Therefore C1 — C5 should be sized to handle 4.7 A of ripple current. Quality ceramic capacitors with a low ESR

should be selected. To allow for capacitor tolerances, five 2.2-µF, 100-V ceramic capacitors will be used. If step

input voltage transients are expected near the maximum rating of the LM25118, a careful evaluation of the

ringing and possible spikes at the device VIN pin should be completed. An additional damping network or input

voltage clamp may be required in these cases.

8.2.2.11 C20

The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value

of C20 should be no smaller than 0.1 µF, and should be a good-quality, low-ESR, ceramic capacitor. A value of 1

µF was selected for this design. C20 should be 10 x C8.

If operating without VCCX, then

fOSC x (QCBuck + Boost) + ILOAD(INTERNAL) (41)

must be less than the VCC current limit.

8.2.2.12 C8

The bootstrap capacitor between the HB and HS pins supplies the gate current to charge the buck switch gate at

turnon. The recommended value of C8 is 0.1 µF to 0.47 µF, and should be a good-quality, low-ESR, ceramic

capacitor. A value of 0.1 µF was chosen for this design.

OFF IN

C21 R1 R3 R1 R3

t Ln 1 .98

R1 R3 V R3

ª º

 ˜ ˜ 

˜  ˜

« »

 ˜

¬ ¼

R3 = 1.23 x VIN(MIN) + 5 PA x R1 - 1.23

- 1

R8 1.23V

VOUT

tSS = 10 PA

C16 x 1.23V

LM25118

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Product Folder Links: LM25118

Typical Application (continued)

8.2.2.13 C16 = CSS

The capacitor at the SS pin determines the soft-start time, that is, the time for the reference voltage and the

output voltage, to reach the final regulated value. The time is determined from:

(42)

and assumes a current limit>Iload + ICout

For this application, a C16 value of 0.1 µF was chosen which corresponds to a soft-start time of about 12 ms.

8.2.2.14 R8, R9

R8 and R9 set the output voltage level, the ratio of these resistors is calculated from:

(43)

For a 12-V output, the R8/R9 ratio calculates to 8.76. The resistors should be chosen from standard value

resistors and a good starting point is to select resistors within power ratings appropriate for the output voltage.

Values of 309 Ωfor R9 and 2.67 kΩfor R8 were selected.

8.2.2.15 R1, R3, C21

A voltage divider can be connected to the UVLO pin to set a minimum operating voltage VIN(UVLO) for the

regulator. If this feature is required, the easiest approach to select the divider resistor values is to choose a value

for R1 between 10 kΩand 100 kΩ, while observing the minimum value of R1 necessary to allow the UVLO

switch to pull the UVLO pin low. This value is:

R1 ≥1000 × VIN(MAX)

R1 ≥75 k

R3 is then calculated from:

(44)

Because VIN(MIN) for our example is 5 V, set VIN(UVLO) to 4 V for some margin in component tolerances and input

ripple.

R1 = 75 k is chosen because it is a standard value

R3 = 29.332 k is calculated from Equation 44. 29.4 k was used because it is a standard value

Capacitor C21 provides filtering for the divider and the off time of the hiccup duty cycle during current limit. The

voltage at the UVLO pin should never exceed 15 V when using an external set-point divider. It may be necessary

to clamp the UVLO pin at high input voltages.

Knowing the desired off time during hiccup current limit, the value of C21 is given by:

(45)

Notice that tOFF varies with VIN

In this example, C21 was chosen to be 0.1 µF. This will set the tOFF time to 723 µs with VIN = 12 V.

8.2.2.16 R2

A 1-M pullup resistor connected from the EN pin to the VIN pin is sufficient to keep enable in a high state if on-off

control is not used.

fz = 2 x S x R4 x C18

ESRzero = 2S x ESR x COUT

fRHPzero = RLOAD (1 - D)2

2S x L x D

MAX

P(MOD) LOAD OUT

1 D

f2 R C



S u u

DCGain(MOD) = RLOAD x VIN

10RS(VIN + 2VOUT)

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Product Folder Links: LM25118

Typical Application (continued)

8.2.2.17 Snubber

A snubber network across the buck recirculating diode reduces ringing and spikes at the switching node.

Excessive ringing and spikes can cause erratic operation and increase noise at the regulator output. In the limit,

spikes beyond the maximum voltage rating of the LM25118 or the recirculating diode can damage these devices.

Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead

lengths for the snubber connections are very short. Start with a resistor value between 5 and 20 Ω. Increasing

the value of the snubber capacitor results in more damping, however the snubber losses increase. Select a

minimum value of the capacitor that provides adequate clamping of the diode waveform at maximum load. A

snubber may be required for the boost diode as well. The same empirical procedure applies. Snubbers were not

necessary in this example.

8.2.2.18 Error Amplifier Configuration

8.2.2.18.1 R4, C18, C17

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One

advantage of current mode control is the ability to close the loop with only three feedback components, R4, C18,

and C17. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC

modulator gain of the LM25118 is as follows:

(46)

The dominant, low frequency pole of the modulator is determined by the load resistance (RLOAD) and output

capacitance (COUT). The corner frequency of this pole is:

(47)

For this example, RLOAD = 4 Ω, DMAX = 0.705, and COUT = 454 µF, therefore:

fP(MOD) = 149 Hz (48)

DC Gain(MOD) = 4.59 = 13.25 dB (49)

Additionally, there is a right-half plane (RHP) zero associated with the modulator. The frequency of the RHP zero

is:

(50)

fRHPzero = 7.8 kHz (51)

The output capacitor ESR produces a zero given by:

(52)

ESRZERO = 76 kHz (53)

The RHP zero complicates compensation. The best design approach is to reduce the loop gain to cross zero at

about 25% of the calculated RHP zero frequency. The Type ll error amplifier compensation provided by R4, C18,

and C17 places one pole at the origin for high DC gain. The second pole should be placed close to the RHP

zero. The error amplifier zero (Equation 54) should be placed near the dominate modulator pole. This is a good

starting point for compensation.

Components R4 and C18 configure the error amplifier as a Type II configuration which has a DC pole and a zero

(54)

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Product Folder Links: LM25118

Typical Application (continued)

C17 introduces an additional pole used to cancel high frequency switching noise. The error amplifier zero

cancels the modulator pole leaving a single pose response at the crossover frequency of the loop gain if the

crossover frequency is much lower than the right half plane zero frequency. A single pole response at the

crossover frequency yields a very stable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 2.0 kHz was selected (about 25% of

the right-half-plane zero frequency). The error amplifier zero (fz) should be selected at a frequency near that of

the modulator pole and much less than the target crossover frequency. This constrains the product of R4 and

C18 for a desired compensation network zero to be less than 2 kHz. Increasing R4, while proportionally

decreasing C18 increases the error amp gain. Conversely, decreasing R4 while proportionally increasing C18

decreases the error amp gain. For the design example C18 was selected for 100 nF and R4 was selected to be

10 kΩ. These values set the compensation network zero at 159 Hz. The overall loop gain can be predicted as

the sum (in dB) of the modulator gain and the error amp gain.

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be

configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier

compensation components can be designed with the guidelines given. Step load transient tests can be

performed to verify acceptable performance. The step load goal is minimal overshoot with a damped response.

Please see the plots shown in Figure 21 through Figure 26 which illustrate the gain and phase diagrams of the

design example.

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Typical Application (continued)

8.2.3 Application Curves

The plots shown in Figure 21 through Figure 26 show the gain and phase diagrams of the design example. The

overall bandwidth is lower in a buck-boost application due the compensation challenges associated with the

right-half-plane zero. For a pure buck application, the bandwidth could be much higher. The LM5116 data sheet

is a good reference for compensation design of a pure buck mode regulator.

Figure 21. Modulator Gain and Phase - Buck Mode Figure 22. Modulator Gain and Phase - Buck-Boost Mode

Figure 23. Error Amplifier Gain and Phase - Buck Mode Figure 24. Error Amplifier Gain and Phase - Buck-Boost

Mode

Figure 25. Overall Loop Gain and Phase - Buck Mode Figure 26. Overall Loop Gain and Phase - Buck-Boost

Mode

VCC

CSG

LM25118

VOUT

VIN

Cout

VBIAS

VCCX

VCC

GND

LM25118

VOUT

CSG

VIN

Cout

VCCX

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Product Folder Links: LM25118

9 Power Supply Recommendations

9.1 Bias Power Dissipation Reduction

Buck or Buck-boost regulators operating with high-input voltage can dissipate an appreciable amount of power

while supplying the required bias current of the IC. The VCC regulator must step-down the input voltage VIN to a

nominal VCC level of 7 V. The large voltage drop across the VCC regulator translates into high power dissipation

in the VCC regulator. There are several techniques that can significantly reduce this bias regulator power

dissipation. Figure 27 and Figure 28 depict two methods to bias the IC, one from the output voltage and one from

a separate bias supply. In the first case, the internal VCC regulator is used to initially bias the VCC pin. After the

output voltage is established, the VCC pin bias current is supplied through the VCCX pin, which effectively

disables the internal VCC regulator. Any voltage greater than 4 V can supply VCC bias through the VCCX pin.

However, the voltage applied to the VCCX pin should never exceed 15 V. The voltage supplied through VCCX

must be large enough to drive the switching MOSFETs into full saturation.

Figure 27. VCC Bias From VOUT 4 V < VOUT < 15 V

Figure 28. VCC Bias With Additional Bias Supply

Controller

VIN GND GND VOUT

Inductor

CIN

COUT

RSENSE

QBUCK

DBUCK

DBOOST

QBOOST

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9.2 Thermal Considerations

The highest power dissipating components are the two power MOSFETs, the recirculating diode, and the output

diode. The easiest way to determine the power dissipated in the MOSFETs is to measure the total conversion

losses (PIN - POUT), then subtract the power losses in the Schottky diodes, output inductor and any snubber

resistors. An approximation for the recirculating Schottky diode loss is:

P = (1-D) × IOUT × VFWD (55)

The boost diode loss is:

P = IOUT × VFWD (56)

If a snubber is used, the power loss can be estimated with an oscilloscope by observation of the resistor voltage

drop at both turnon and turnoff transitions. The LM25118 package has an exposed thermal pad to aid power

dissipation. Selecting diodes with exposed pads will aid the power dissipation of the diodes as well. When

selecting the MOSFETs, pay careful attention to RDS(ON) at high temperature. Also, selecting MOSFETs with low

gate charge will result in lower switching losses.

See Application Notes AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages

(SNVA183) and AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419) for thermal management

techniques for use with surface mount components.

10 Layout

10.1 Layout Guidelines

In a buck-boost regulator, there are two loops where currents are switched very fast. The first loop starts from the

input capacitors, and then to the buck switch, the inductor, the boost switch then back to the input capacitor. The

second loop starts from the inductor, and then to the output diode, the output capacitor, the recirculating diode,

and back to the inductor. Minimizing the PCB area of these two loops reduces the stray inductance and

minimizes noise and the possibility of erratic operation. A ground plane in the PCB is recommended as a means

to connect the input filter capacitors to the output filter capacitors and the PGND pins of the LM25118. Connect

all of the low current ground connections (CSS, RT, CRAMP) directly to the regulator AGND pin. Connect the AGND

and PGND pins together through topside copper area covering the entire underside of the device. Place several

vias in this underside copper area to the ground plane of the input capacitors.

10.2 Layout Example

Figure 29. LM25118 Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM25118 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM25118MH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM25118

LM25118MHE/NOPB ACTIVE HTSSOP PWP 20 250 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM25118

LM25118MHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM25118

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM25118 :

•Automotive: LM25118-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM25118MHE/NOPB HTSSOP PWP 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

LM25118MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Mar-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM25118MHE/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0

LM25118MHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Mar-2018

Pack Materials-Page 2

MECHANICAL DATA

PWP0020A

www.ti.com

MXA20A (Rev C)

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