LTC4100
1
4100fc
For more information www.linear.com/LTC4100
Typical applicaTion
DescripTion
Smart Battery
Charger Controller
The LT C
®
4100 Smart Battery Charger is a single chip
charging solution that dramatically simplifies construction
of an SBS compliant system. The LTC4100 implements
a Level 2 charger function whereby the charger can be
programmed by the battery or by the host. A SafetySignal
on the battery being charged is monitored for temperature,
connectivity and battery type information. The SMBus
interface remains alive when the AC power adapter is
removed and responds to all SMBus activity directed to
it, including SafetySignal status (via the ChargerStatus
command). The charger also provides an interrupt to the
host whenever a status change is detected (e.g., battery
removal, AC adapter connection).
Charging current and voltage are restricted to chemistry-
specific limits for improved system safety and reliability.
Limits are programmable by two external resistors. Ad-
ditionally, the maximum average current from the AC
adapter is programmable to avoid overloading the adapter
when simultaneously supplying load current and charging
current. When supplying system load current, charg-
ing current is automatically reduced to prevent adapter
overload.
Figure 1. 4A Smart Battery Charger
FeaTures
applicaTions
n Single Chip Smart Battery Charger Controller
n 100% Compliant (Rev. 1.1) SMBus Support Allows
for Operation with or without Host
n SMBus Accelerator Improves SMBus Timing
n Wide Output Voltage Range: 3.5V to 26V
n Hardware Interrupt and SMBAlert Response
Eliminate Interrupt Polling
n High Efficiency Synchronous Buck Charger
n 0.5V Dropout Voltage; Maximum Duty Cycle > 98%
n AC Adapter Current Limit Maximizes Charge Rate
n ±0.8% Voltage Accuracy; ±4% Current Accuracy
n Up to 4A Charging Current Capability
n 10-Bit DAC for Charge Current Programming
n 11-Bit DAC for Charger Voltage Programming
n User-Selectable Overvoltage and Overcurrent Limits
n High Noise Immunity SafetySignal Sensor
n Available in a 24-Pin SSOP Package
n Portable Instruments and Computers
n Data Storage Systems and Battery Backup Servers
L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and
PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 6650174 and 5723970.
17
11
6
10
7
9
8
15
16
13
14
20
5
4
24
23
1
3
2
21
22
18
19
12
3V
TO 5.5V
0.12µF
0.1µF
0.068µF 0.1µF
0.01µF
0.0015µF
6.04k
10k
54.9k
100Ω
0.033Ω
20µF
20µF
0.1µF
10µH
0.025Ω
SMBCLK
5k
SMBDAT
SMBCLK
SMBDAT
DCIN
4100 TA01
CHGEN
SMBALERT#
ACP SMART BATTERY
SYSTEM LOAD
1.13k
1.21k
13.7k
SafetySignal
VDD
DCDIV
CHGEN
ACP
SMBALERT
SCL
SDA
THB
THA
ILIM
VLIM
IDC
DCIN
INFET
CLP
CLN
TGATE
BGATE
PGND
CSP
BAT
VSET
ITH
GND
LTC4100
VBAT
< 5.5V
> 5.5V
LTC4101
LTC4100
PART
LTC4100
2
4100fc
For more information www.linear.com/LTC4100
pin conFiguraTionabsoluTe MaxiMuM raTings
Voltage from VDD to GND ................................. 7V/–0.3V
Voltage from CHGEN, DCDIV, SDA,
SCL and SMBALERT to GND ............................ 7V/–0.3V
Voltage from DCIN, CLP, CLN to GND ............ 32V/–0.3V
Voltage from CLP to CLN .......................................±0.3V
PGND wrt. GND .................................................... ±0.3V
CSP, BAT to GND ............................................... 28V/–5V
Operating Ambient Temperature Range (Note 4)
–40°C to 85°C
Junction Temperature Range ................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................... 300°C
(Note 1)
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
G PACKAGE
24-LEAD PLASTIC SSOP
24
23
22
21
20
19
18
17
16
15
14
13
TGATE
PGND
BGATE
INFET
DCIN
CHGEN
SMBALERT
SDA
SCL
ACP
DCDIV
GND
CLP
CLN
BAT
CSP
IDC
ITH
VSET
VDD
THA
THB
VLIM
ILIM
TJMAX = 125°C, θJA = 90°C/W
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4100EG#PBF LTC4100EG#TRPBF LTC4100EG 24-Lead Plastic SSOP –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4100EG LTC4100EG#TR LTC4100EG 24-Lead Plastic SSOP –40°C to 85°C
Consult LT C Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DCIN Operating Range ●6 28 V
IDCIN DCIN Operating Current Charging, Sum of Currents on DCIN,
CLP and CLN
3 5 mA
VTOL Charge Voltage Accuracy (Note 2)
●
–0.8
–1
0.8
1
%
%
ITOL Charge Current Accuracy (Note 3) VCSP – VBAT Target = 102.3mV
IDAC = 0xFFFF
●
–4
–5
4
5
%
%
VDD VDD Operating Voltage 0V ≤ VDCIN ≤ 28V ●3 5.5 V
Shutdown
Battery Leakage Current DCIN = 0V, VCLP = VCLN = VCSP = VBAT ●15 35 µA
UVLO Undervoltage Lockout Threshold DCIN Rising, VBAT = 0V ●4.2 4.7 5.5 V
VDD Power-Fail Part Held in Reset Until this VDD Present ●3 V
DCIN Current in Shutdown VCHGEN = 0V 2 3 mA
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
LTC4100
3
4100fc
For more information www.linear.com/LTC4100
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Sense Amplifier, CA1
Input Bias Current into BAT Pin 11.66 µA
CMSL CA1/I1 Input Common Mode Low ●0 V
CMSH CA1/I1 Input Common Mode High VDCIN ≤ 28V ●VCLN–0.2 V
Current Comparators ICMP and IREV
ITMAX Maximum Current Sense Threshold (VCSP–VBAT) VITH = 2.5V ●140 165 200 mV
ITREV Reverse Current Threshold (VCSP–VBAT) – 30 mV
Current Sense Amplifier, CA2
Transconductance 1 mmho
Source Current Measured at ITH, VITH = 1.4V –40 µA
Sink Current Measured at ITH, VITH = 1.4V 40 µA
Current Limit Amplifier
Transconductance 1.5 mmho
VCLP Current Limit Threshold ●93 100 107 mV
ICLN CLN Input Bias Current 100 nA
Voltage Error Amplifier, EA
Transconductance 1 mmho
Sink Current Measured at ITH, VITH = 1.4V 36 µA
OVSD Overvoltage Shutdown Threshold as a Percent of
Programmed Charger Voltage
●102 107 110 %
Input P-Channel FET Driver (INFET)
DCIN Detection Threshold (VDCIN–VCLP) DCIN Voltage Ramping Up from VCLP–0.05V ●0 0.17 0.25 V
Forward Regulation Voltage (VDCIN–VCLP)●25 50 mV
Reverse Voltage Turn-Off Voltage (VDCIN–VCLP)●–60 –25 mV
INFET ON Clamping Voltage (VDCIN–VINFET) IINFET = 1µA ●5 5.8 6.5 V
INFET OFF Clamping Voltage (VDCIN–VINFET) IINFET = –25µA 0.25 V
Oscillator
fOSC Regulator Switching Frequency 255 300 345 kHz
fMIN Regulator Switching Frequency in Drop Out Duty Cycle ≥ 98% 20 25 kHz
DCMAX Regulator Maximum Duty Cycle VCSP = VBAT 98 99 %
Gate Drivers (TGATE, BGATE)
VTGATE High (VCLP-VTGATE) ITGATE = –1mA 50 mV
VBGATE High CLOAD = 3000pF 4.5 5.6 10 V
VTGATE Low (VCLP-VTGATE) CLOAD = 3000pF 4.5 5.6 10 V
VBGATE Low IBGATE = 1mA 50 mV
TGTR
TGTF
TGATE T
ransition Time
TGATE Rise Time
TGATE Fall Time
CLOAD = 3000pF, 10% to 90%
CLOAD = 3000pF, 10% to 90%
50
50
110
100
ns
ns
BGTR
BGTF
BGATE T
ransition Time
BGATE Rise Time
BGATE Fall Time
CLOAD = 3000pF, 10% to 90%
CLOAD = 3000pF, 10% to 90%
40
40
90
80
ns
ns
VTGATE at Shutdown (VCLN-VTGATE) ITGATE = –1µA 100 mV
VBGATE at Shutdown ITGATE = 1µA 100 mV
LTC4100
4
4100fc
For more information www.linear.com/LTC4100
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AC Present Comparator
VACP DCDIV Threshold VDCDIV Rising from 1V to 1.4V ●1.14 1.20 1.26 V
DCDIV Hysteresis 25 mV
DCDIV Input Bias Current VDCDIV = 1.2V –1 1 µA
ACP VOH IACP = –2mA 2 V
ACP VOL IACP = 1mA 0.5 V
DCDIV to ACP Delay VDCDIV = 1.3V 10 µs
SafetySignal Decoder
SafetySignal Trip (RES_COLD/RES_OR) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9kΩ ±1%
●95 100 105 kΩ
SafetySignal Trip (RES_IDEAL/RES_COLD) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9kΩ ±1%
●28.5 30 31.5 kΩ
SafetySignal Trip (RES_HOT/RES_IDEAL) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9kΩ ±1%
●2.85 3 3.15 kΩ
SafetySignal Trip (RES_UR/RES_HOT) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9kΩ ±1%
●425 500 575 Ω
Time Between SafetySignal Measurements DCDIV = 1.3V
DCDIV = 1V
32
250
ms
ms
DACs
Charging Current Resolution Guaranteed Monotonic Above IMAX/16 10 Bits
Charging Current Granularity RILIM = 0
RILIM = 10k ±1%
RILIM = 33k ±1%
RILIM = Open (or Short to VDD)
1
2
4
4
mA
mA
mA
mA
Wake-Up Charging Current (IWAKE-UP) All Values of RILIM
All Values of RVLIM
80 (Note 5) mA
Charging Current Limit
CSP – BAT
RILIM = 0 (0-1A)
Charging Current = 0x03FF (0x0400 Note 7)
97.3 107.3 mV
RILIM = 10k ±1% (0-2A)
Charging Current = 0x07FE (0x0800 Note 7)
97.3 107.3 mV
RILIM = 33k ±1% (0-3A)
Charging Current = 0x0BFC (0x0C00 Note 7)
72.3 82.3 mV
RILIM = 0pen (or Short to VDD) (0-4A)
Charging Current = 0x0FFC (0x1000 Note 7)
97.3 107.3 mV
Charging Voltage Resolution Guaranteed Monotonic (2.9V ≤ VBAT ≤ 28V) 11 Bits
Charging Voltage Granularity 16 mV
Charging Voltage Limit RVLIM = 0
Charging Voltage = 0x2260 (Note 7)
8.730 8.800 8.870 V
RVLIM = 10k ±1%
Charging Voltage = 0x3330 (Note 7)
12.999 13.104 13.209 V
RVLIM = 33k ±1%
Charging Voltage = 0x4400 (Note 7)
17.269 17.408 17.547 V
RVLIM = 100k ±1%
Charging Voltage = 0x5400 DCIN ≥ 22V
(Note 7)
21.538 21.712 21.886 V
RVLIM = 0pen (or Short to VDD)
Charging Voltage = 0x6D60 DCIN ≥ 29V
(Note 7)
27.781 28.006 28.231 V
LTC4100
5
4100fc
For more information www.linear.com/LTC4100
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Logic Levels
VIL SCL/SDA Input Low Voltage VDD = 3V and VDD = 5.5V ●0.8 V
VIH SCL/SDA Input High Voltage VDD = 3V and VDD = 5.5V ●2.1 V
VOL SDA Output Low Voltage IPULL-UP = 350µA ●0.4 V
IIL SCL/SDA Input Current VSDA, VSCL = VIL –1 1 µA
IIH SCL/SDA Input Current VSDA, VSCL = VIH –1 1 µA
VOL SMBALERT Output Low Voltage IPULL-UP = 500µA ●0.4 V
SMBALERT Output Pull-Up Current VSMBALERT = VOL –17.5 –10 –3.5 µA
ILEAK SDA/SCL/SMBALERT Power Down Leakage VSDA, VSCL, VSMBALERT = 5.5V, VDD = OV ●–2 2 µA
VOL CHGEN Output Low Voltage IOL = 100µA ●0.5 V
CHGEN Output Pull-Up Current VCHGEN = VOL –17.5 –10 –3.5 µA
VIL CHGEN Input Low Voltage ●0.9 V
VIH CHGEN Input High Voltage VDD = 3V
VDD = 5.5V
●2.5
3.9
V
V
Power-On Reset Duration VDD Ramp from 0V to >3V in <5µs 100 µs
SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)
tHIGH SCL Serial Clock High Period IPULL-UP = 350µA, CLOAD = 250pF,
RPU = 9.31k, VDD = 3V and VDD = 5.5V
●4 µs
tLOW SCL Serial Clock Low Period IPULL-UP = 350µA, CLOAD = 250pF,
RPU = 9.31k, VDD = 3V and VDD = 5.5V
●4.7 15000 µs
tRSDA/SCL Rise Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V and
VDD = 5.5V
●1000 ns
tFSDA/SCL Fall Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V and
VDD = 5.5V
●300 ns
tSU:STA Start Condition Setup Time VDD = 3V and VDD = 5.5V ●4.7 µs
tHD:STA Start Condition Hold Time VDD = 3V and VDD = 5.5V ●4 µs
tHD:DAT SDA to SCL Falling-Edge Hold Time, Slave
Clocking in Data
VDD = 3V and VDD = 5.5V ●300 ns
tTIMEOUT Time Between Receiving Valid ChargingCurrent()
and ChargingVoltage() Commands
VDD = 3V and VDD = 5.5V ●140 175 210 sec
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: See Test Circuit.
Note 3: Does not include tolerance of current sense resistor.
Note 4: The LTC4100E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Current accuracy dependent upon circuit compensation and sense
resistor.
Note 6: CTH is defined as the sum of capacitance on THA, THB and
SafetySignal.
Note 7: The corresponding overrange bit will be set when a HEX value
greater than or equal to this value is used.
LTC4100
6
4100fc
For more information www.linear.com/LTC4100
Typical perForMance characTerisTics
Disconnect/Reconnect Battery
(Load Dump)
Battery Leakage Current
vs Battery Voltage Efficiency at 19V VDCIN
Efficiency at 12.6V with 15V VDCIN SMBus Accelerator Operation Low Current Operation
INFET Response Time to
Reverse Current VOUT vs IOUT PWM Frequency vs Duty Cycle
TEST PERFORMED ON DEMOBOARD
VIN = 15VDC
CHARGER = ON
ICHARGE = <10mA
Vs OF PFET (5V/DIV)
Id (REVERSE) OF
PFET (5A/DIV)
Vgs OF PFET (2V/DIV)
4100 G01
VCHARGE = 12.6V
INFET = 1/2 Si4925DY
Vgs = 0
Vs = 0V
Id = 0A
1.25µs/DIV
OUTPUT CURRENT (A)
0 0.5 1.0 2.0 3.0 4.01.5 2.5 3.5 4.5
OUTPUT VOLTAGE ERROR (%)
4100 G02
DCIN = 20V
VBAT = 12.6V
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
DUTY CYCLE (VOUT/VIN)
0 0.1 0.2 0.4 0.6 0.90.80.3 0.5 0.7 1.0
PWM FREQUENCY (kHz)
4100 G03
PROGRAMMED CURRENT = 10%
DCIN = 15V
DCIN = 20V
DCIN = 24V
350
300
250
200
150
100
50
0
4100 G04
LOAD CURRENT = 1A, 2A, 3A
DCIN = 20V
VFLOAT = 12.6V
VFLOAT
1V/(DIV)
LOAD
STATE DISCONNECT RECONNECT
1A STEP
3A STEP
3A STEP
1A STEP
BATTERY VOLTAGE (V)
0 5 10 15 20 25 30
BATTERY LEAKAGE CURRENT (µA)
4100 G05
40
35
30
25
20
15
10
5
0
VDCIN = 0V
CHARGING CURRENT (A)
1.000.50 1.50 2.00 2.50 3.00
EFFICIENCY (%)
4100 G06
16.8V
12.6V
100
95
90
85
80
75
CHARGING CURRENT (A)
1.000.50 1.50 2.00 2.50 3.00
EFFICIENCY (%)
4100 G07
100
95
90
85
80
75
1µs/DIV
4100 G08
5V
0V
RPULLUP = 15k
LTC4100
VDD = 5V
CBUS = 200pF
TA = 25°C
PROGRAMMED CURRENT (A)
0
MEASURED CURRENT (A)
0.5
0.3
0.4
0.2
0.1
0
–0.1 0.1
4100 G09
0.2 0.40.3
VDD = 5V
TEMP = 27°C
DCIN = 15V
LOW
CURRENT
MODE
PROGRAMMED
CURRENT
NO LOW
CURRENT
MODE
LTC4100
7
4100fc
For more information www.linear.com/LTC4100
Typical perForMance characTerisTics
Charging Current Error Charging Voltage Error
CHARGING CURRENT (A)
0
OUTPUT CURRENT ERROR (A)
0.4
0.2
0.3
0.1
0
–0.1
–0.2
–0.3
–0.4 1
4100 G10
243
DCIN = 15V, NoLowI
DCIN = 20V, NoLowI
DCIN = 15V, LowI
DCIN = 20V, LowI
VDD = 5V
TEMP = 27°C
VLOAD = 12V
CHARGING VOLTAGE (V)
0
OUTPUT VOLTAGE ERROR (V)
0.150
0.100
0.125
0.075
0.050
0
0.025
–0.025
–0.050
–0.075
–0.100
–0.125
–0.150 16
4100 G11
42 6 10 14 18
812 2220
DCIN = 15V
VDD = 5V
TEMP = 27°C
ILOAD = 0.120A
DCIN = 20V
pin FuncTions
TGATE (Pin 1): Drives the Top External P-MOSFET of the
Battery Charger Buck Converter.
PGND (Pin 2): High Current Ground Return for BGATE
Driver.
BGATE (Pin 3): Drives the Bottom External N-MOSFET of
the Battery Charger Buck Converter.
INFET (Pin 4): Drives the Gate of the External Input
P-MOSFET.
DCIN (Pin 5): External DC Power Source Input. Bypass to
ground with a 0.1µF capacitor.
CHGEN (Pin 6): Digital Bidirectional Pin to Enable Charger
Function. This pin is connected as a wired AND bus.
The following events will cause the POWER_FAIL bit in
the ChargerStatus register to become set:
1. An external device pulling the CHGEN signal to within
0.9V to GND;
2. The AC adapter voltage is not above the battery voltage.
SMBALERT (Pin 7): Active Low Interrupt Output to Host
(referred to as the SMBALERT# signal in the SMBus Revi-
sion 1.1 specification). Signals host that there has been a
change of status in the charger registers and that the host
should read the LTC4100 status registers to determine if
any action on its part is required. This signal can be con-
nected to the optional SMBALERT# line of the SMBus.
Open drain with weak current source pull-up to VDD (with
Schottky to allow it to be pulled to 5V externally).
SDA (Pin 8): SMBus Data Signal from Main (host-
controlled) SMBus. External pull-up resistor is required.
SCL (Pin 9): SMBus Clock Signal from Main (host-
controlled) SMBus. External pull-up resistor is required.
ACP (Pin 10): This Output Indicates the Value of the
DCDIV Comparator. It can be used to indicate whether
AC is present or not.
DCDIV (Pin 11): Supply Divider Input. This is a high im-
pedance comparator input with a 1.2V threshold (rising
edge) and hysteresis.
GND (Pin 12): Ground for Digital and Analog Circuitry.
ILIM (Pin 13): An external resistor is connected between this
pin and GND. The value of the external resistor programs
the range and resolution of the programmed charger cur-
rent. This is a digital, not an analog, function.
LTC4100
8
4100fc
For more information www.linear.com/LTC4100
pin FuncTions
VLIM (Pin 14): An external resistor is connected between
this pin and GND. The value of the external resistor pro-
grams the range and resolution of the charging voltage.
This is a digital, not an analog, function.
THB (Pin 15): SafetySignal Force/Sense Pin to Smart
Battery. See description of operation for more detail. The
maximum allowed combined capacitance on THA, THB and
SafetySignal is 1nF (see Figure 4). A series resistor 54.9k
needs to be connected between this pin and the battery’s
SafetySignal for this circuit to work correctly.
THA (Pin 16): SafetySignal Force/Sense Pin to Smart
Battery. See description of operation for more detail. The
maximum allowed combined capacitance on THA, THB
and SafetySignal is 1nF (see Figure 4). A series resistor
1130Ω needs to be connected between this pin and the
battery’s SafetySignal for this circuit to work correctly.
VDD (Pin 17): Power Supply Input for the LTC4100 Digital
Circuitry. Bypass this pin with 0.1µF. Typically between
3.3V and 5VDC.
VSET (Pin 18): Tap Point of the Programmable Resistor
Divider, which Provides Battery Voltage Feedback to the
Charger.
ITH (Pin 19): Control Signal of the Inner Loop of the Current
Mode PWM. Higher ITH corresponds to higher charging
current in normal operation. A 0.0015µF capacitor to GND
filters out PWM ripple. Typical full-scale output current
is 40µA. Nominal voltage range for this pin is 0V to 3V.
IDC (Pin 20): Bypass to GND with a 0.068µF Capacitor.
CSP (Pin 21): Current Amplifier CA1 Input. This pin and
the BAT pin measure the voltage across the sense resis-
tor, RSENSE, to provide the instantaneous current signals
required for both peak and average current mode operation.
BAT (Pin 22): Battery Sense Input and the Negative Refer-
ence for the Current Sense Resistor. A bypass capacitor
of at least 10µF is required.
CLN (Pin 23): Negative Input to the Input Current Limiting
Circuit Block. If no current limit function is desired, connect
this pin to CLP. The threshold is set at 100mV below the
voltage at the CLP pin. When used to limit supply current,
a filter is needed to filter out the switching noise.
CLP (Pin 24): Positive Input to the Input Current Limiting
Circuit Block. This pin also serves as a power supply for
the IC.
LTC4100
9
4100fc
For more information www.linear.com/LTC4100
block DiagraM
Figure 2
C7
0.0015µF
R5, 6.04k
+
–
+
–
+
+
1.28V
1.19V
WATCHDOG
DETECT tON
OSCILLATOR
DCIN
PWM
LOGIC
S
R
Q
CA1
BUFFERED
ITH
+
–
+
–
÷5
+
–
17mV
100mV 1.19V
1.2V
CLP
SMBus
INTERFACE
AND CONTROL
THERMISTER
INTERFACE
LIMIT
DECODER
ICMP
IREV
0V
VSET BAT
CSP
IDC
ILIM
VLIM
ITH
ACP
DCDIV
TO SMBUS
POWER SUPPLY
PGND
CLN
CLP
DCIN
INFET
CHGEN
SMBALERT
SDA
SCL
THA
THB
GND
CLP
TGATE
BGATE
SYSTEM
LOAD EA
CL1
5.8V
11-BIT
VDAC
10-BIT
IDAC
3k
11.67µA
3k
9k
–
–
12
18
1
3
2
23
24
5
4
6
8
9
16
15
13
14
11
10
19
20
21
22
R4
100Ω
C4
0.01µF
C5, 0.1µF
VBAT
VBAT
CSP
CSP
Q2
Q3
Q1
RCL
20µF
D1
L1
VIN
VIN
7
10µA
VDD
RSENSE
20µF
C8
0.068µF
RVLIM RILIM
17 VDD
R1
C9
C1, 0.1µF
1.13k
TO HOST AND BATTERY
54.9k
10k
CA2
R10
R11
C6, 0.12µF
gm = 1m
Ω
gm = 1m
Ω
gm = 1.5m
Ω
LTC4100
10
4100fc
For more information www.linear.com/LTC4100
Overview (Refer to Block Diagram)
The LTC4100 is composed of a battery charger section, a
charger controller, a 10-bit DAC to control charger current,
an 11-bit DAC to control charger voltage, a SafetySignal
decoder, limit decoder and an SMBus controller block. If
no battery is present, the SafetySignal decoder indicates a
RES_OR condition and charging is disabled by the charger
controller (CHGEN = Low). Charging will also be disabled if
DCDIV is low, or the SafetySignal is decoded as RES_HOT.
If a battery is inserted and AC power is connected, the
battery will be charged with an 80mA “wake-up” current.
The wake-up current is discontinued after tTIMEOUT if the
SafetySignal is decoded as RES_UR or RES_C0LD, and
the battery or host doesn’t transmit charging commands.
The SMBus interface and control block receives Charg-
ingCurrent() and ChargingVoltage() commands via the
SMBus. If ChargingCurrent() and ChargingVoltage()
command pairs are received within a tTIMEOUT interval, the
values are stored in the current and voltage DACs and the
charger controller asserts the CHGEN line if the decoded
SafetySignal value will allow charging to commence. Charg-
ingCurrent() and ChargingVoltage() values are compared
against limits programmed by the limit decoder block; if
the commands exceed the programmed limits these limits
are substituted and overrange flags are set.
The charger controller will assert SMBALERT whenever
a status change is detected, namely: AC_PRESENT,
TesT circuiT
+
–+
–
+
–
EA
VDAC
0.6V
LT1055
CSP BAT VSET ITH
LTC4100
1.19V
4100 TC01
21 22 18 19
operaTion
BATTERY_PRESENT, ALARM_INHIBITED, or VDD power-
fail. The host may query the charger, via the SMBus, to
obtain ChargerStatus() information. SMBALERT will be
de-asserted upon a successful read of ChargerStatus()
or a successful Alert Response Address (ARA) request.
Battery Charger Controller
The LTC4100 charger controller uses a constant off-time,
current mode step-down architecture. During normal
operation, the top MOSFET is turned on each cycle when
the oscillator sets the SR latch and turned off when
the main current comparator ICMP resets the SR latch.
While the top MOSFET is off, the bottom MOSFET is
turned on until either the inductor current trips the current
comparator IREV, or the beginning of the next cycle. The
oscillator uses the equation,
tOFF =V
DCIN −V
BAT
( )
V
DCIN •fOSC
( )
to set the bottom MOSFET on-time. The result is quasi-
constant frequency operation: the converter frequency
remains nearly constant over a wide range of output volt-
ages. This activity is diagrammed in Figure 3.
The peak inductor current, at which ICMP resets the SR
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
VTOL =V
BAT
−
VVDAC
VVDAC
•100
FOR VVDAC =17.57V(0x44A0)
DCIN =21V
CLN =CLP =20V
LTC4100
11
4100fc
For more information www.linear.com/LTC4100
operaTion
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by the IDAC at the IDC pin and adjusts
ITH for the desired voltage across RSENSE.
The voltage at BAT is divided down by an internal resis-
tor divider set by the VDAC and is used by error amp EA
to decrease ITH if the divider voltage is above the 1.19V
reference.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (100mV/
RCL). At input current limit, CL1 will decrease the ITH volt-
age to reduce charging current.
An overvoltage comparator, OV, guards against transient
overshoots (>7%). In this case, the top MOSFET is turned
off until the overvoltage condition is cleared. This feature
is useful for batteries that “load dump” themselves by
opening their protection switch to perform functions such
as calibration or pulse mode charging.
PWM Watchdog Timer
There is a watchdog timer that observes the activity on
the TGATE pin. If TGATE stops switching for more than
40µs, the watchdog activates and turns off the top MOSFET
for about 400ns. The watchdog engages to prevent very
low frequency operation in dropout—a potential source
of audible noise when using ceramic input and output
capacitors.
Charger Start-Up
When the charger is enabled, it will not begin switching
until the ITH voltage exceeds a threshold that assures initial
current will be positive. This threshold is 5% to 15% of the
maximum programmed current. After the charger begins
switching, the various loops will control the current at a
level that is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation, but is typically less than 1ms.
SMBus Interface
All communications over the SMBus are interpreted by the
SMBus interface block. The SMBus interface is a SMBus
slave device at address 0x12. All internal LTC4100 registers
may be updated and accessed through the SMBus interface,
and charger controller as required. The SMBus protocol is
a derivative of the I2C bus (Reference
I2C-Bus and How to
Use It, V1.0
by Philips, and
System Management Bus Speci-
fication
, Version 1.1, from the SBS Implementers Forum, for
a complete description of the bus protocol requirements).
All data is clocked into the shift register on the rising
edge of SCL. All data is clocked out of the shift register
on the falling edge of SCL. Detection of an SMBus Stop
condition, or power-on reset via the VDD power-fail, will
reset the SMBus interface to an initial state at any time.
The LTC4100 command set is interpreted by the SMBus
interface and passed onto the charger controller block as
control signals or updates to internal registers.
Figure 3
tOFF
OFF
OFF
ON
ON
TGATE
BGATE
INDUCTOR
CURRENT
TRIP POINT SET
BY ITH VOLTAGE
4100 F03
*http://www.SBS-FORUM.org
LTC4100
12
4100fc
For more information www.linear.com/LTC4100
operaTion
Description of Supported Battery Charger Functions
The functions are described as follows (see Table 1 also):
FunctionName() ‘hnn (command code)
Description: A brief description of the function.
Purpose: The purpose of the function, and an example
where appropriate.
•SMBus Protocol: Refer to Section 5 of the Smart
Battery Charger specification for more details.
Input, Output or Input/Output: A description of the data
supplied to or returned by the function.
ChargerSpecInfo() (‘h11)
Description: The SMBus Host uses this command to read
the LTC4100’s extended status bits.
Purpose: Allows the System Host to determine the
specification revision the charger supports as well as
other extended status information.
•SMBus Protocol: Read Word.
Output: The CHARGER_SPEC indicates that the LTC4100
supports Version 1.1 of the Smart Battery Charger
Specification. The SELECTOR_SUPPORT indicates that
the LTC4100 does not support the optional Smart Battery
Selector Commands.
ChargerMode() (‘h12)
Description: The SMBus Host uses this command to set
the various charger modes. The default values are set to
allow a Smart Battery and the LTC4100 to work in concert
without requiring an SMBus Host.
Purpose: Allows the SMBus Host to configure the charger
and change the default
modes. This is a write only function,
but the value of the “mode” bit, INHIBIT_CHARGE may be
determined using the ChargerStatus() function.
•SMBus Protocol: Write Word.
Input: The INHIBIT_CHARGE bit allows charging to be
inhibited without changing the ChargingCurrent() and
ChargingVoltage() values. The charging may be resumed
by clearing this bit. This bit is automatically cleared when
power is reapplied or when a battery is reinserted.
The ENABLE_POLLING bit is not supported by the LTC4100.
Values written to this bit are ignored.
The POR_RESET bit sets the LTC4100 to its power-on
default condition.
The RESET_TO_ZERO bit sets the ChargingCurrent()and
ChargingVoltage() values to zero. This function ALWAYS
clears the ChargingVoltage() and ChargingCurrent() values
to zero even if the INHIBIT_CHARGE bit is set.
ChargerStatus() (‘h13)
Description: The SMBus Host uses this command to read
the LTC4100’s status bits.
Purpose: Allows the SMBus Host to determine the status
and level of the LTC4100.
•SMBus Protocol: Read Word.
Output: The CHARGE_INHIBITED bit reflects the status
of the LTC4100 set by the INHIBIT_CHARGE bit in the
ChargerMode() function.
The POLLING_ENABLED, VOLTAGE_NOTREG, and
CURRENT_NOTREG are not supported by the LTC4100.
The LTC4100 always reports itself as a Level 2 Smart
Battery Charger.
CURRENT_OR bit is set only when ChargingCurrent()
is set to a value outside the current regulation range of
the LTC4100. This bit may be used in conjunction with
the INHIBIT_CHARGE bit of the ChargerMode() and
ChargingCurrent() to determine the current capability of
the LTC4100. When ChargingCurrent() is set to the ILIM
+ 1, the CURRENT_OR bit will be set.
VOLTAGE_OR bit is set only when ChargingVoltage()
is set to a value outside the voltage regulation range of
the LTC4100. This bit may be used in conjunction with
the INHIBIT_CHARGE bit of the ChargerMode() and
ChargingVoltage() to determine the voltage capability of
the LTC4100. When ChargingVoltage() is set to the VLIM,
the VOLTAGE_OR bit will be set.
The RES_OR bit is set only when the SafetySignal resis-
tance value is greater than 95kΩ. This indicates that the
SafetySignal is to be considered as an open circuit.
LTC4100
13
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For more information www.linear.com/LTC4100
operaTion
ChargerSpecInfo() 7'b0001_001 8'h11 Info
(0x12)
Return
Read Values
ChargerMode() 7'b0001_001 8'h12 Control
Permitted
Write Values
ChargerStatus() 7'b0001_001 8'h13 Status
Return
Read Values
ChargingCurrent() 7'b0001_001 8'h14 Value CHARGING_CURRENT[15:0]
Permitted
Write Values
ChargingVoltage() 7'b0001_001 8'h15 Value CHARGING_VOLTAGE[15:0]
Permitted
Write Values
AlarmWarning() 7'b0001_001 8'h16 Control
Permitted
Write Values
LTCO() 7'b0001_001 8'h3C Register
Permitted
Write Values
Return
Read Values
Alert Response 7'b0001_100 N/A Status LTC4100's Address
Address (0x18)
Read
Byte
Access
SMBus
Address
Command
Code
Data
Type
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
1/0 1/0 Ign 1/0
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 1 0 0 0 1/0
1/0 1/0 1/0 1/0
0 0 0 1/0 0 0 1 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 1 X
Function
SELECTOR_SUPPORT
CHARGER_SPEC
RESET_TO_ZERO
POR_RESET
ENABLE_POLLING
INHIBIT_CHARGE
AC_PRESENT
BATTERY_PRESENT
POWER_FAIL
ALARM_INHIBITED
RES_UR
RES_HOT
RES_COLD
RES_OR
VOLTAGE_OR
CURRENT_OR
CURRENT_NOTREG
VOLTAGE_NOTREG
POLLING_ENABLED
CHARGE_INHIBITED
Reserved
Reserved
Ignored
Ignored
OVER_CHARGED_ALARM
TERMINATE_CHARGE_ALARM
RESERVED_ALARM
OVER_TEMP_ALARM
TERMINATE_DISCHARGE_ALARM
Reserved
REMAINING_CAPACITY_ALARM
REMAINING_TIME_ALARM
INITIALIZED
DISCHARGING
FULLY_CHARGED
FULLY DISCHARGED
ERROR
NO_LOWI
Undefined
Reserved LTC4100's Version Identification
Ignored Ignored
Unsigned integer representing current in mA
LEVEL:3/LEVEL:2
Not Supported
Unsigned integer representing voltage in mV
1/0
Return
Values
Table 1. Summary of Supported Charger Functions
LTC4100
14
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For more information www.linear.com/LTC4100
operaTion
The RES_COLD bit is set only when the SafetySignal
resistance value is greater than 28.5kΩ. The SafetySignal
indicates a cold battery. The RES_COLD bit will be set
whenever the RES_OR bit is set.
The RES_HOT bit is set only when the SafetySignal
resistance is less than 3150Ω, which indicates a hot battery.
The RES_HOT bit will be set whenever the RES_UR bit is set.
The RES_UR bit is set only when the SafetySignal resis-
tance value is less than 575Ω.
ALARM_INHIBITED bit is set if a valid AlarmWarning()
message has been received and charging is inhibited as
a result. This bit is cleared if both ChargingVoltage() and
ChargingCurrent() are rewritten to the LTC4100, power
is removed (DCDIV < VACP), or if a battery is removed.
The setting of the ALARM_INHIBITED will activate the
LTC4100 SMBALERT pull-down.
POWER_FAIL bit is set if the LTC4100 does not have suf-
ficient DCIN voltage to charge the battery or if an external
device is pulling the CHGEN input signal low. Charging
is disabled whenever this bit is set. The setting of this bit
does not clear the values in the ChargingVoltage() and
ChargingCurrent() function values, nor does it necessarily
affect the charging modes of the LTC4100.
BATTERY_PRESENT is set if a battery is present other-
wise it is cleared. The LTC4100 uses the SafetySignal
in order to determine battery presence. If the LTC4100
detects a RES_OR condition, the BATTERY_PRESENT
bit is cleared immediately. The LTC4100 will not set the
BATTERY_PRESENT bit until it successfully samples
the SafetySignal twice and does not detect a RES_OR
condition on either sampling. If AC is not present (e.g.
DCDIV < VACP), this bit may not be set for up to one-half
second after the battery is connected to the SafetySignal.
The ChargingCurrent() and ChargingVoltage() function
values are immediately cleared whenever this bit is cleared.
Charging will never be allowed if this bit is cleared. A
change in BATTERY_PRESENT will activate the LTC4100
SMBALERT pull-down.
AC_PRESENT is set if the voltage on DCDIV is greater than
VACP. This does not necessarily indicate that the voltage
on DCIN is sufficient to charge the battery. A change
in AC_PRESENT will activate the LTC4100 SMBALERT
pull-down.
ChargingCurrent() (‘h14)
Description: The Battery, System Host or other master
device sends the desired charging current (mA) to the
LTC4100 .
Purpose: The LTC4100 uses RILIM, the granularity of the
IDAC, and the value of the ChargingCurrent() function to
determine its charging current supplied to the battery. The
charging current will never exceed the maximum current
permitted by RILIM. The ChargingCurrent() value will be
truncated to the granularity of the IDAC. The charging cur-
rent will also be reduced if the battery voltage exceeds the
programmed charging voltage.
•SMBus Protocol: Write Word.
Input: The CHARGING_CURRENT is an unsigned 16 bit
integer specifying the requested charging current in mA.
The following table defines the maximum permissible
value of CHARGING_CURRENT that will not set the
CURRENT_OR in the ChargerStatus() function for a given
value of the RILIM:
RILIM ChargingCurrent() Current
Short to GND 0x0000 through 0x03FF 0mA through 1023mA
10kΩ ±1% 0x0000 through 0x07FF 0mA through 2047mA
33kΩ ±1% 0x0000 through 0x0BFF 0mA through 3071mA
Open (or Short to VDD) 0x0000 through 0x0FFF 0mA through 4095mA
ChargingVoltage() (‘h15)
Description: The Battery, SMBus Host or other master
device sends the desired charging voltage (mV) to the
LTC4100.
Purpose: The LTC4100 uses RVLIM, the granularity of the
VDAC, and the value of the ChargingVoltage() function to
determine its charging voltage supplied to the battery. The
charging voltage will never be forced beyond the voltage
permitted by RVLIM. The ChargingVoltage() value will be
truncated to the granularity of the VDAC. The charging
voltage will also be reduced if the battery current exceeds
the programmed charging current.
•SMBus Protocol: Write Word.
Input: The CHARGING_VOLTAGE is an unsigned 16-bit
integer specifying the requested charging voltage in mV.
LTC4100
15
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For more information www.linear.com/LTC4100
operaTion
The LTC4100 considers any value from 0x0001 through
0x049F the same as writing 0x0000. The following
table defines the maximum permissible value of
CHARGING_VOLTAGE that will not set the VOLTAGE_OR
in the ChargerStatus() function for a given value of RVLIM:
RVLIM Maximum ChargingVoltage()
Short to GND 0x225F (8796mV)
10kΩ ±1% 0x332F (13100mV)
33kΩ ±1% 0x43FF (17404mV)
100kΩ ±1% 0x54CF (21708mV)
Open (or Short to VDD) 0x6D5F (27996mV)
AlarmWarning() (‘h16)
Description: The Smart Battery, acting as a bus master
device, sends the AlarmWarning() message to the LTC4100
to notify it that one or more alarm conditions exist. Alarm
indications are encoded as bit fields in the Battery’s Sta-
tus register, which is then sent to the LTC4100 by this
function.
Purpose: The LTC4100 will use the information sent by
this function to properly charge the battery. The LTC4100
will only respond to certain alarm bits. Writing to this
function does not necessarily cause an alarm condition
that inhibits battery charging.
•SMBus Protocol: Write Word.
Input: Only the OVER_CHARGED_ALARM, TERMINATE
_CHARGE_ALARM, reserved (0x2000), and OVER
_TEMP_ALARM bits are supported by the LTC4100.
Writing a one to any of these specified bits will inhibit
the charging by the LTC4100 and will set the ALARM_
INHIBITED bit in the ChargerStatus() function. The
TERMINATE_DISCHARGE_ALARM, REMAINING_
CAPACITY_ALARM, REMAINING_TIME_ALARM, and the
ERROR bits are ignored by the LTC4100.
LTC0() (‘h3C)
Description: The SMBus Host uses this command to
determine the version number of the LTC4100 and set
extended operation modes not defined by the Smart Bat-
tery Charger Specification.
Purpose: This function allows the SMBus Host to deter-
mine if the battery charger is an LTC4100. Identifying the
manufacturer and version of the Smart Battery Charger
permits software to perform tasks specific to a given
charger. The LTC4100 also provides a means of disabling
the LOWI current mode of the IDAC.
•SMBus Protocol: Write Word.
Input: The NO_LOWI is the only bit recognized by this
function. The default value of NO_LOWI is zero. The
LTC4100 LOWI current mode provides a more accurate
average charge current when the charge current is less
than 1/16 of the full scale IDAC value. When the NO_LOWI
is set, a less accurate IDAC algorithm is used to generate
the charging current, but because the charger is not pulsed
on and off, it may be preferred.
•SMBus Protocol: Read Word.
Output: The NO_LOWI indicates the IDAC mode of opera-
tion. If clear, then the LOWI current mode will be used
when the charging current is less than 1/16 of the full-
scale IDAC value.
The LT C Version Identification will always be 0x202 for
the LTC4100.
Alert Response Address (ARA)
Description: The SMBus system host uses the Alert
Response Address to quickly identify the generator of an
SMBALERT# event.
Purpose: The LTC4100 will respond to an ARA address
0x18 if the SMBALERT signal is actively pulling down the
SMBALERT# bus. The LTC4100 will follow the prioritiza-
tion reporting as defined in the System Management Bus
Specification, Version 1.1, from the SBS Implementers
Forum.
•SMBus Protocol: A 7-bit Addressable Device Responds
to an ARA.
Output: The Device Address will be sent to the SMBus
system host. The LTC4100 Device address is 0x12.
The following events will cause the LTC4100 to pull-down
the SMBALERT# bus through the SMBALERT pin:
•Change of AC_PRESENT in the ChargerStatus()
function.
LTC4100
16
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For more information www.linear.com/LTC4100
operaTion
•Change of BATTERY_PRESENT in the ChargerStatus()
function.
•Setting ALARM_INHIBITED in the ChargerStatus()
function.
•Internal power-on reset condition.
SMBus Accelerator Pull-Ups
Both SCL and SDA have SMBus accelerator circuits
which reduce the rise time on systems with significant
capacitance on the two SMBus signals. The dynamic pull-up
circuitry detects a rising edge on SDA or SCL and applies
1mA to 10mA pull-up to VDD when VIN > 0.8V until VIN
< VDD – 0.8V (external pull-up resistors are still required
to supply DC current). This action allows the bus to meet
SMBus rise time requirements with as much as 250pF on
each SMBus signal. The improved rise time will benefit
all of the devices which use the SMBus, especially those
devices that use the I2C logic levels. Note that the dynamic
pull-up circuits only pull to VDD, so some SMBus devices
that are not compliant to the SMBus specifications may still
have rise time compliance problems if the SMBus pull-up
resistors are terminated with voltages higher than VDD.
The Control Block
The LTC4100 charger operations are handled by the con-
trol block. This block is capable of charging the selected
battery autonomously or under SMBus Host control.
The control block can request communications with the
system management host (SMBus Host) by asserting
SMBALERT = 0; this will cause the SMBus Host, if present,
to poll the LTC4100.
The control block receives SMBus slave commands from
the SMBus interface block.
The control block allows the LTC4100 to meet the following
Smart Battery-controlled (Level 2) charger requirements:
1. Implements the Smart Battery’s critical warning mes-
sages over the SMBus.
2. Operates as an SMBus slave device that responds to
ChargingVoltage() and ChargingCurrent() commands
and adjusts the charger output parameters accordingly.
3. The host may control charging by disabling the Smart
Battery’s ability to transmit ChargingCurrent() and
ChargingVoltage() request functions and broadcast-
ing the charging commands to the LTC4100 over the
SMBus.
4. The LTC4100 will still respond to Smart Battery critical
warning messages without host intervention.
Wake-Up Charging Mode
The following conditions must be met in order to allow
wake-up charging of the battery:
1. The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.
2. AC must be present. This is qualified by DCDIV > VACP.
Wake-up charging initiates when a newly inserted battery
does not send ChargingCurrent() and ChargingVoltage()
functions to the LTC4100.
The following conditions will terminate the wake-up
charging mode.
1. A TTIMEOUT period is reached when the SafetySignal is
RES_COLD or RES_UR.
2. The SafetySignal is registering RES_OR.
3. The successful writing of the ChargingCurrent() AND
ChargingVoltage() function. The LTC4100 will proceed
to the controlled charging mode after these two func-
tions are written.
4. The SafetySignal is registering RES_HOT.
5. The AC power is no longer present. (DCDIV < VACP)
6. The ALARM_INHIBITED becomes set in the Charger-
Status() function.
7. The INHIBIT_CHARGE is set in the ChargerMode()
function.
8. The CHGEN pin is pulled low by an external device. The
LTC4100 will resume wake-up charging, if the CHGEN
pin is released by the external device. Toggling the
CHGEN pin will not reset the TTIMEOUT timer.
9. There is insufficient DCIN voltage to charge the battery.
The LTC4100 will resume wake-up charging when there
is sufficient DCIN voltage to charge the battery. This
condition will not reset the TTIMEOUT timer.
LTC4100
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Controlled Charging Algorithm Overview
The following conditions must be met in order to allow
controlled charging to start on the LTC4100:
1. The ChargingVoltage() AND ChargingCurrent() function
must be written to non-zero values.
2. The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.
3. AC must be present. This is qualified by DCDIV > VACP.
The following conditions will stop the controlled charging
algorithm and will cause the battery charger controller to
stop charging:
1. The ChargingCurrent() AND ChargingVoltage() functions
have not been written for TTIMEOUT.
2. The SafetySignal is registering RES_OR.
3. The SafetySignal is registering RES_HOT.
4. The AC power is no longer present. (DCDIV < VACP)
5. ALARM_INHIBITED is set in the ChargerStatus()
function.
6. INHIBIT_CHARGE is set in the ChargerMode()
function. Clearing INHIBIT_CHARGE will cause the
LTC4100 to resume charging using the previous
ChargingVoltage() AND ChargingCurrent() function
values.
7. RESET_TO_ZERO is set in the ChargerMode() function.
8. CHGEN pin is pulled low by an external device. The
LTC4100 will resume charging using the previous
ChargingVoltage() AND ChargingCurrent() function
values, if the CHGEN pin is released by the external
device.
9. Insufficient DCIN voltage to charge the battery. The
LTC4100 will resume charging using the previous
ChargingVoltage() AND ChargingCurrent() function
values, when there is sufficient DCIN voltage to charge
the battery.
10. Writing a zero value to ChargingVoltage() function.
11. Writing a zero value to ChargingCurrent() function.
The SafetySignal Decoder Block
This block measures the resistance of the SafetySignal and
features high noise immunity at critical trip points. The low
power standby mode supports only battery presence SMB
charger reporting requirements when AC is not present.
The SafetySignal decoder is shown in Figure 4. The value
of RTHA is 1.13k and RTHB is 54.9k.
Figure 4. SafetySignal Decoder Block
RTHA
1.13k
RSafetySignal
RTHB
54.9k
VDD
VDD
4100 F04
THA_SELB
THB_SELB
+
–
+
–
RES_OR
RES_COLD
RES_H0T
RES_UR
LATCH
SafetySignal
CONTROL
MUX
REF
HI_REF
LO_REF
TH_HI
TH_LO
THA
THB
CSS
16
15
Figure 5. Simplified VLIM Circuit Concept (ILIM is Similar)
VLIM
12.5k
25k
33k
25k
25k
12.5k
RVLIM
VDD
VLIM [3:0]
4100 F05
AC_PRESENT
4
+
–
+
–
+
–
+
–
ENCODER
14
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SafetySignal sensing is accomplished by a state machine
that reconfigures the switches of Figure 4 using THA_SELB
and THB_SELB, a selectable reference generator, and two
comparators. This circuit has two modes of operation
based upon whether AC is present.
When AC is present, the LTC4100 samples the value of
the SafetySignal and updates the ChargerStatus register
approximately every 32ms. The state machine successively
samples the SafetySignal value starting with the RES_OR
≥ RES_COLD threshold, then RES_C0LD ≥ RES_IDEAL
threshold, RES_IDEAL ≥ RES_HOT threshold, and finally
the RES_HOT ≥ RES_UR threshold. Once the SafetySignal
range is determined, the lower value thresholds are
not sampled. The SafetySignal decoder block uses the
previously determined SafetySignal value to provide the
appropriate adjustment in threshold to add hysteresis.
The RTHB resistor value is used to measure the RES_OR
≥ RES_COLD and RES_COLD ≥ RES_IDEAL thresholds by
connecting the THB pin to VDD and measuring the voltage
resultant on the THA pin. The RTHA resistor value is used
to measure the RES_IDEAL ≥ RES_HOT and RES_HOT ≥
RES_UR thresholds by connecting the THA pin to VDD and
measuring the voltage resultant on the THB pin.
The SafetySignal decoder block uses a voltage divider
network between VDD and GND to determine SafetySig-
nal range thresholds. Since the THA and THB inputs are
sequentially connected to VDD, this provides VDD noise
immunity during SafetySignal measurement.
When AC power is not available the SafetySignal block
supports the following low power operating features:
1. The SafetySignal is sampled every 250ms or less,
instead of 32ms.
2. A full SafetySignal status is sampled every 30s or less,
instead of every 32ms.
The SafetySignal impedance is interpreted according to
Table 4.
Table 4. SafetySignal State Ranges
SafetySignal
RESISTANCE
CHARGE STATUS BITS DESCRIPTION
0Ω to 500Ω RES_UR
RES_HOT
BATTERY_PRESENT
Underrange
500Ω to 3kΩ RES_HOT
BATTERY_PRESENT
Hot
3kΩ to 30kΩ BATTERY_PRESENT Ideal
30kΩ to 100kΩ RES_COLD
BATTERY_PRESENT
Cold
Above 100kΩ RES_OR RES_COLD Overrange
Note: The underrange detection scheme is a very important feature of the
LTC4100. The RTHA/RSafetySignal divider trip point of0.333•VDD (1V) is
well above the0.047•VDD (140mV) threshold of a system using a 10k
pull-up. A system using a 10k pull-up would not be able to resolve the
important underrange to hot transition point with a modest 100mV of
ground offset between battery and SafetySignal detection circuitry. Such
offsets are anticipated when charging at normal current levels.
The required values for RTHA and RTHB are shown in
Table 5.
Table 5. SafetySignal External Resistor Values
EXTERNAL RESISTOR VALUE (Ω)
RTHA 1130 ±1%
RTHB 54.9k ±1%
CSS represents the capacitance between the SafetySignal
and GND. CSS may be added to provide additional noise
immunity from transients in the application. CSS cannot
exceed 1nF if the LTC4100 is to properly sense the value
of RSafetySignal.
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The ILIM Decoder Block
The value of an external resistor connected from this pin
to GND determines one of four current limits that are
used for maximum charging current value. These limits
provide a measure of safety with a hardware restriction on
charging current which cannot be overridden by software.
Table 6. ILIM Trip Points and Ranges
EXTERNAL
RESISTOR
(RILIM) ILIM VOLTAGE
CONTROLLED
CHARGING
CURRENT RANGE GRANULARITY
Short to GND VILIM < 0.09VDD 0 < I < 1023mA 1mA
10k ±1% 0.17VVDD <
VILIM < 0.34VVDD
0 < I < 2046mA 2mA
33k ±1% 0.42VVDD <
VILIM < 0.59V
0 < I < 3068mA 4mA
Open (>250k,
or Short to VDD)
0.66VVDD <
VILIM
0 < I < 4092mA 4mA
The VLIM Decoder Block
The value of an external resistor connected from this pin
to GND determines one of five voltage limits that are ap-
plied to the charger output value. These limits provide a
measure of safety with a hardware restriction on charging
voltage which cannot be overridden by software.
Table 7. VLIM Trip Points and Ranges (See Figure 5)
EXTERNAL
RESISTOR
(RVLIM) VLIM VOLTAGE
CONTROLLED
CHARGING VOLTAGE
(VOUT) RANGE GRANULARITY
Short to
GND
VVLIM < 0.09VVCCP 2900mV < VOUT
< 8800mV
16mV
10k ±1% 0.17VVDD < VVLIM
< 0.34VVDD
2900mV < VOUT
< 13104mV
16mV
33k ±1% 0.42VVCCP < VVLIM
< 0.59VVDD
2900mV < VOUT
< 17408mV
16mV
100k ±1% 0.66VVDD < VVLIM
< 0.84VVDD
2900mV < VOUT
< 21712mV
16mV
Open or
Tied to VDD
0.91VVDD < VVLIM 2900mV < VOUT
< 28000mV
16mV
The Voltage DAC Block
Note that the charger output voltage is offset by VREF.
Therefore, the value of VREF is subtracted from the
SMBus ChargingVoltage() value in order for the output
voltage to be programmed properly (without offset). If the
ChargingVoltage() value is below the nominal reference
voltage of the charger, nominally 1.184V, the charger
output voltage is programmed to zero. In addition, if the
ChargingVoltage() value is above the limit set by the VLIM
pin, then the charger output voltage is set to the value
determined by the VLIM resistor and the VOLTAGE_OR bit
is set. These limits are demonstrated in Figure 6.
PROGRAMMED VALUE (V)
0
CHARGER V
OUT
(V)
25
20
15
10
5
0
10 20 25
4100 F06
515 30 35
RVLIM = 33k
Figure 6. Transfer Function of Charger
NOTE: THE LTC4100 CAN BE PROGRAMMED WITH ChargingVoltage() FUNCTION VALUES
BETWEEN 1.184V AND 2.9V, HOWEVER, THE BATTERY CHARGER CONTROLLER OUTPUT
VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2.9V.
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The Current DAC Block
The current DAC is a delta-sigma modulator which controls
the effective value of an external resistor, RSET, used to
set the current limit of the charger. Figure 7 is a simplified
diagram of the DAC operation. The delta-sigma modulator
and switch convert the ChargingCurrent() value, received
via the SMBus, to a variable resistance equal to:
1.25RSET/[ChargingCurrent()/ILIM[x]] = RIDC
Therefore, programmed current is equal to:
ICHARGE = (102.3mV/R
SENSE) (ChargingCurrent()/
ILIM[x]), for ChargingCurrent() < ILIM[x].
When a value less than 1/16th of the maximum current
allowed by ILIM is applied to the current DAC input, the
current DAC enters a different mode of operation called
LOWI. The current DAC output is pulse width modulated
with a high frequency clock having a duty cycle value of
1/8. Therefore, the maximum output current provided by
the charger is IMAX/8. The delta-sigma output gates this
low duty cycle signal on and off. The delta-sigma shift
registers are then clocked at a slower rate, about 45ms/
bit, so that the charger has time to settle to the IMAX/8
value. The resulting average charging current is equal to
that requested by the ChargingCurrent() value.
Note: The LOWI mode can be disabled by setting the
NO_LOWI bit in the LTC0() function.
When wake-up is asserted to the current DAC block, the
delta-sigma is then fixed at a value equal to 80mA, inde-
pendent of the ILIM setting.
Input FET
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLP pin,
and provides an indication of this condition at both the
CHGEN pin and the PWR_FAIL bit in the ChargerStatus()
register. It also controls the gate of the input FET to keep
a low forward voltage drop when charging and prevents
reverse current flow through the input FET.
If the input voltage is less than VCLP, it must go at least
130mV higher than VCLP to activate the charger. The CHGEN
pin is forced low unless this condition is met. The gate
of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLP drops to less than 25mV,
the input FET is turned off slowly. If the voltage between
DCIN and CLP is ever less than –25mV, then the input FET
is turned off quickly to prevent significant reverse current
from flowing in the input FET. In this condition the CHGEN
pin is driven low and the charger is disabled.
The AC Present Block (AC_PRESENT)
The DCDIV pin is used to determine AC presence. If the
DCDIV voltage is above the DCDIV comparator threshold
(VACP), then the ACP output pin will be switched to VDD and
the AC_PRESENT bit in the ChargerStatus() function will be
set. If the DCDIV voltage is below the DCDIV comparator
threshold minus the DCDIV comparator hysteresis, then
the ACP output pin is switched to GND and the AC_PRES-
ENT bit in the ChargerStatus() function is cleared. The
ACP output pin is designed to drive 2mA continuously.
Figure 7. Current DAC Operation
IPROG
(FROM CA1 AMP)
4100 F07
+
–
RSET VREF
IDC
CHARGING_CURRENT
VALUE
ITH
∆-∑
MODULATOR
19
20
ILIMIT/8
AVERAGE CHARGER CURRENT
4100 F08
~40ms
0
Figure 8. Charging Current Waveform in Low Current Mode
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Adapter Limiting
An important feature of the LTC4100 is the ability to auto-
matically adjust charging current to a level which avoids
overloading the wall adapter. This allows the product to
operate at the same time that batteries are being charged
without complex load management algorithms. Addition-
ally, batteries will automatically be charged at the maximum
possible rate of which the adapter is capable.
This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1 in
Figure 9 senses the voltage across RCL, connected be-
tween the CLP and CLN pins. When this voltage exceeds
100mV, the amplifier will override programmed charging
current to limit adapter current to 100mV/RCL. A lowpass
filter formed by 4.99k and 0.1µF is required to eliminate
switching noise. If the current limit is not used, CLP should
be connected to CLN.
Setting Input Current Limit
To set the input current limit, you need to know the mini-
mum wall adapter current rating. Subtract 7% for the input
current limit tolerance and use that current to determine
the resistor value.
RCL = 100mV/ILIM
ILIM = Adapter Min Current
– (Adapter Min Current•7%)
As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one
can simply set the adapter current limit value to the actual
adapter rating (Figure 9).
Charge Termination Issues
Batteries with constant current charging and voltage-
based charger termination might experience problems
with reductions of charger current caused by adapter
limiting. It is recommended that input limiting feature be
defeated in such cases. Consult the battery manufacturer
for information on how your battery terminates charging.
Setting Output Current Limit (Refer to Figure 1)
The LTC4100 current DAC and the PWM analog circuitry
must coordinate the setting of the charger current. Failure
to do so will result in incorrect charge currents.
Table 8. Common RCL Resistor Values
ADAPTER RATING (A) –7% ADAPTER RATING (A) RCL VALUE* (Ω) 1% RCL LIMIT (A) RCL POWER DISSIPATION (W) RCL POWER RATING (W)
1.5 1.40 0.068 1.47 0.15 0.25
1.8 1.67 0.062 1.61 0.16 0.25
2.0 1.86 0.051 1.96 0.20 0.25
2.3 2.14 0.047 2.13 0.21 0.25
2.5 2.33 0.043 2.33 0.23 0.50
2.7 2.51 0.039 2.56 0.26 0.50
3.0 2.79 0.036 2.79 0.28 0.50
3.3 3.07 0.033 3.07 0.31 0.50
3.6 3.35 0.030 3.35 0.33 0.50
4.0 3.72 0.027 3.72 0.37 0.50
* Rounded to nearest 5% standard step value. Many nonstandard values are popular.
100mV
–
+
R1
4.99k
CLP
CLN
INFET
4100 F09
LTC4100
C9
0.1µF
+
RCL*
VIN
CL1
*RCL = 100mV
ADAPTER CURRENT LIMIT
TO LOAD
24
23
4
Figure 9. Adaptor Current Limiting
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IMAX is the full-scale charge current. Chose the lowest IMAX
value that is still above your expected battery charge cur-
rent as requested over the SMBus. If you deviate from the
resistance values shown in Table 9, it will lead to charge
current gain errors. The requested current and the actual
charge current applied to the battery will not be the same.
Table 9. Recommended Resistor Values
IMAX (A) RSENSE (Ω) 1% RSENSE (W) RILIM (Ω) 1%
1.023 0.100 0.25 0
2.046 0.05 0.25 10k
3.068 0.025 0.5 33k
4.092 0.025 0.5 Open
Warning
DO NOT CHANGE THE VALUE OF RILIM DURING OPERA-
TION. The value must remain fixed and track the RSENSE
value at all times. Changing the current setting can result
in currents that greatly exceed the requested value and
potentially damage the battery or overload the wall adapter
if no input current limiting is provided.
Inductor Selection
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency gener-
ally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value
on ripple current and low current operation must also be
considered. The inductor ripple current ∆IL decreases with
higher frequency and increases with higher VIN.
∆IL=1
(f)(L) VOUT 1−VOUT
V
IN
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(IMAX). Remember the
maximum ∆IL occurs at the maximum input voltage. The
inductor value also has an effect on low current operation.
The transition to low current operation begins when the
inductor current reaches zero while the bottom MOSFET
is on. Lower inductor values (higher ∆IL) will cause this
to occur at higher load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
practice 10µH is the lowest value recommended for use.
Table 10. Recommended Inductor Values
Maximum Average
Current (A) Input Voltage (V)
Minimum Inductor Value
(µH)
1 ≤20 40 ± 20%
1 >20 56 ± 20%
2 ≤20 20 ± 20%
2 >20 30 ± 20%
3 ≤20 15 ± 20%
3 >20 20 ± 20%
4 ≤20 10 ± 20%
4 >20 15 ± 20%
Charger Switching Power MOSFET
and Diode Selection
Tw o external power MOSFETs must be selected for use
with the charger: a P-channel MOSFET for the top (main)
switch and an N-channel MOSFET for the bottom (syn-
chronous) switch.
The peak-to-peak gate drive levels are set internally. This
voltage is typically 6V. Consequently, logic-level threshold
MOSFETs must be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; many of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the on-
resistance RDS(ON), total gate capacitance QG, reverse
transfer capacitance CRSS, input voltage and maximum
output current. The charger is operating in continuous
mode so the duty cycles for the top and bottom MOSFETs
are given by:
Main Switch Duty Cycle = VOUT/VIN
Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN
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The MOSFET power dissipations at maximum output
current are given by:
PMAIN = VOUT/VIN(IMAX)2(1 + δ∆T)RDS(ON)
+ k(VIN)2(IMAX)(CRSS)(fOSC)
PSYNC = (VIN – VOUT)/VIN(IMAX)2(1 + δ∆T)RDS(ON)
where δ∆T is the temperature dependency of RDS(ON) and
k is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the PMAIN equation
includes an additional term for transition losses, which
are highest at high input voltages. For VIN < 20V the high
current efficiency generally improves with larger MOSFETs,
while for VIN > 20V the transition losses rapidly increase to
the point that the use of a higher RDS(ON) device with lower
CRSS actually provides higher efficiency. The synchronous
MOSFET losses are greatest at high input voltage or during
a short circuit when the duty cycle in this switch in nearly
100%. The term (1 + δ∆T) is generally given for a MOSFET
in the form of a normalized RDS(ON) vs temperature curve,
but δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. CRSS = QGD/∆VDS is usually specified
in the MOSFET characteristics. The constant k = 2 can be
used to estimate the contributions of the two terms in the
main switch dissipation equation.
If the charger is to operate in low dropout mode or with
a high duty cycle greater than 85%, then the topside
P-channel efficiency generally improves with a larger
MOSFET. Using asymmetrical MOSFETs may achieve cost
savings or efficiency gains.
The Schottky diode D1, shown in the typical application
on the back page, conducts during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on
and storing charge during the dead-time, which could cost
as much as 1% in efficiency. A 1A Schottky is generally
a good size for 4A regulators due to the relatively small
average current. Larger diodes can result in additional
transition losses due to their larger junction capacitance.
The diode may be omitted if the efficiency loss can be
tolerated.
Calculating IC Power Dissipation
The power dissipation of the LTC4100 is dependent upon
the gate charge of the top and bottom MOSFETs (Q2 &
Q3 respectively) The gate charge (QG) is determined from
the manufacturer’s
data sheet and is dependent upon both
the gate voltage swing and the drain voltage swing of the
MOSFET. Use 6V for the gate voltage swing and VDCIN for
the drain voltage swing.
PD = VDCIN•(fOSC (QGQ2 + QGQ3) + IDCIN) + VDD•IDD
Example: VDCIN = 19V, fOSC = 345kHz, QGQ2 = 25nC,
QGQ3 = 15nC, IDCIN = 5mA, VDD = 5.5V,
IDD = 1mA.
PD = 428mW
Calculating VDD Current
The LTC4100 VDD current, or IDD, consist of three parts:
a. IRUN = Current due to active clocking and bias inside
the IC.
b. ITHRM = Current due to thermistor circuit activity.
c. IACCEL = Current due to SMBus acceleration activity.
IDD = IRUN + ITHRM + IACCEL
a) IRUN current is basically independent of SCL clock rate.
Once the LTC4100 determines that there is activity on
the SMBus, it turns on its internal HF oscillator. This
HF oscillator remains on until a stop event occurs or
SDA and SCL are at logic level 1 for the SMBus timeout
period. Then it shuts off the HF oscillator. Thus, the
length of the transmission and the rate of transmission
bursts are more important in determining how much
current the LTC4100 burns, rather than the SCL rate.
In the equation below, IQ is the static current the IC
consumes as a function of the VDD voltage when not
active. Since it is hard to quantify the actual messages
going down the SMBus, one must estimate the SMBus
activity level in term of bus utilization per second.
IRUN = Message Duty Cycle•950µA
+ (1 – Message Duty Cycle)•IQ
where IQ (typical) = VDD/47.2k
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b) ITHRM current is due to SafetySignal (thermistor pin)
sampling that will vary with the presence of DC power
being on or off. DCDIV is detected every 32ms. RTHX
is the value of the safety signal resistance, which will
vary with temperature or battery configuration.
b1) ITHRM(ON) when DC is on:
ITHRM(ON)_OVERRANGE=1/16•VDD/(54.9k + RTHX)
where RTHX > 100k
ITHRM(ON)_COLD=1/8•VDD/(54.9k + RTHX) where
RTHX > 30k
ITHRM(ON)_NORMAL=1/8•VDD/(54.9k + RTHX)
+1/16•VDD/(1.13k + RTHX)
ITHRM(ON)_HOT*=1/8•VDD/(54.9k + RTHX)
+1/8•VDD/(1.13k + RTHX)
where RTHX < 3k
*= includes underrange
b2) ITHRM(OFF) when DC is off, the thermistor monitoring
rate is reduced to every 250ms or less.
ITHRM(OFF)_OVERRANGE=1/50•VDD/(54.9k + RTHX)
where RTHX > 100K
ITHRM(OFF)_COLD=1/50•VDD/(54.9k + RTHX)
+1/1000•VDD/(54.9k + RTHX)
where RTHX > 30K
ITHRM(OFF)_NORMAL=1/50•VDD/(54.9k + RTHX) +
1/500•VDD/(54.9k + RTHX)+1/1000•VDD/(1.13k
+ RTHX)
ITHRM(OFF)_HOT*=1/50•VDD/(54.9k + RTHX) +
1/500•VDD/(54.9k + RTHX)+1/500•VDD/(1.13k +
RTHX)
where RTHX < 3k
* includes underrange
c) IACCEL is the current used by the SMBus accelerators.
This directly depends on the SMBus frequency, duty
cycle of messages sent on the SMBus and how long
it takes to drive the SMBus to VDD.
IACCEL = IPULL-UP•2•SMBus Frequency•
Message Duty Cycle•VDD/2.25V•Rise Time
applicaTions inForMaTion
Complete Examples
1) Battery thermistor = 400Ω, VDD = 5.0V
Battery mode (DC is off), SMBus activity is 10kHz
and a 2% SMBus duty cycle, which represents a
suspended or sleep condition of a notebook.
ITOTAL = IRUN + ITHRM(OFF) + IACCEL = 121.9µA
+ 5.26µA + 2.44µA = 130µA
Battery mode and a 10% SMBus duty cycle, which
represents an active notebook at idle.
ITOTAL = IRUN + ITHRM(OFF) + IACCEL = 189.5µA
+ 5.26µA + 12.2µA = 207µA
DCIN = ON and a 20% SMBus duty cycle which
represents an active notebook charging.
ITOTAL = IRUN + ITHRM(ON) + IACCEL = 274µA
+ 215.6µA + 24.4µA = 514µA
2) Battery thermistor = 10kΩ, VDD = 5.0V
Battery mode (DC is off), SMBus activity is 10kHz
and a 2% SMBus duty cycle:
ITOTAL = IRUN + ITHRM(OFF) + IACCEL = 121.9µA
+ 2.14µA + 2.44µA = 126µA
Battery mode and a 10% SMBus duty cycle:
ITOTAL = IRUN + ITHRM(OFF) + IACCEL = 189.5µA
+ 2.14µA + 12.2µA = 204µA
DCIN = ON and a 20% SMBus duty cycle:
ITOTAL = IRUN + ITHRM(OFF) + IACCEL = 274µA
+ 37.7µA + 24.4µA = 336µA
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Soft-Start and Undervoltage Lockout
The LTC4100 is soft-started by the 0.12µF capacitor on
the ITH pin. On start-up, ITH pin voltage will rise quickly
to 0.5V, then ramp up at a rate set by the internal 30µA
pull-up current and the external capacitor. Battery charging
current starts ramping up when ITH voltage reaches 0.8V
and full current is achieved with ITH at 2V. With a 0.12µF
capacitor, time to reach full charge current is about 2ms
and it is assumed that input voltage to the charger will reach
full value in less than 2ms. The capacitor can be increased
up to 1µF if longer input start-up times are needed.
In any switching regulator, conventional timer-based
soft-starting can be defeated if the input voltage rises much
slower than the time out period. This happens because
the switching regulators in the battery charger and the
computer power supply are typically supplying a fixed
amount of power to the load. If input voltage comes up
slowly compared to the soft-start time, the regulators will
try to deliver full power to the load when the input voltage
is still well below its final value. If the adapter is current
limited, it cannot deliver full power at reduced output
voltages and the possibility exists for a quasi “latch” state
where the adapter output stays in a current limited state at
reduced output voltage. For instance, if maximum charger
plus computer load power is 30W, a 15V adapter might
be current limited at 2.5A. If adapter voltage is less than
(30W/2.5A = 12V) when full power is drawn, the adapter
voltage will be pulled down by the constant 30W load
until it reaches a lower stable state where the switching
regulators can no longer supply full load. This situation
can be prevented by utilizing the DCDIV resistor divider,
set higher than the minimum adapter voltage where full
power can be achieved.
Input and Output Capacitors
We recommend the use of high capacity low ESR/ESL
X5R type ceramic capacitors. Alternative capacitors
include OSCON or POSCAP type capacitors. Aluminum
electrolytic capacitors are not recommended for poor
ESR and ESL reasons. Solid tantalum low ESR capacitors
are acceptable, but caution must be used when tantalum
capacitors are used for input or output bypass. High input
surge currents can be created when the power adapter is
hot-plugged into the charger or when a battery is con-
nected to the charger. Use only “surge robust” low ESR
tantalums. Regardless of which type of capacitor you
use, after voltage selection, the most important thing
to meet is the ripple current requirements followed by
the capacitance value. By the time you solve the ripple
current requirements, the minimum capacitance value is
often met by default. The following equation shows the
minimum COUT (±20% tolerance) capacitance values for
stability when used with the compensation shown in the
typical application on the back page.
COUT(MIN) = 200/L1
The use of aluminum electrolytic for C1, located at the
AC adapter input terminal, is helpful in reducing ringing
during the hot-plug event. Refer to Application Note 88
for more information.
In the 4A lithium battery charger (typical application on
back page), the input capacitor (C2) is assumed to absorb
all input switching ripple current in the converter, so it
must have adequate ripple current rating. Worst-case RMS
ripple current will be equal to one half of output charging
current. C2 is recommended to be equal to or greater than
C4 (output capacitor) in capacitance value.
The output capacitor (C4) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
I
RMS =
0.29(V
BAT )•1−V
BAT
V
DCIN
L1•f
For example, VDCIN = 19V, VBAT = 12.6V, L1 = 10µH, and
f = 300kHz, IRMS = 0.41A.
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or induc-
tors may be added to increase battery impedance at the
300kHz switching frequency. Switching ripple current splits
between the battery and the output capacitor depending
on the ESR of the output capacitor and the battery imped-
ance. If the ESR of C3 is 0.2Ω and the battery impedance
is raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.
LTC4100
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applicaTions inForMaTion
CONNECTOR
TO BATTERY TO SYSTEM
4100 F10
VDD
Figure 10. Recommended SMBus Transient Protection
4100 F11
VBAT
L1
VIN
HIGH
FREQUENCY
CIRCULATING
PATH
BAT
SWITCH NODE
C2 C4
D1
TO CSP AND BAT
VIAS TO CSP AND BAT
4100 F12
4100 F12
DIRECTION OF CHARGING CURRENT
RSENSE
DIRECTION OF CHARGING CURRENT
RSENSE
Figure 11. High Speed Switching Path
Figure 12. Kelvin Sensing of Charging Current
Protecting SMBus Inputs
The SMBus inputs, SCL and SDA, are exposed to uncon-
trolled transient signals whenever a battery is connected
to the system. If the battery contains a static charge, the
SMBus inputs are subjected to transients which can cause
damage after repeated exposure. Also, if the battery’s posi-
tive terminal makes contact to the connector before the
negative terminal, the SMBus inputs can be forced below
ground with the full battery potential, causing a potential
for latch-up in any of the devices connected to the SMBus
inputs. Therefore it is good design practice to protect the
SMBus inputs as shown in Figure 10.
SafetySignal (Thermistor) Value
The SafetySignal (typical application on back page), is a
multifunction signal the communicates three pieces of
information in order of importance:
1) Presence of the Smart Battery
2) The maximum time duration of the wake-up charge
allowed.
3) An optional and redundant temperature measurement
system.
The value of the resistance to ground communicates all
this information. The resistance ranges and what it does
is covered by the SBS Smart Battery Charger standard in
Section 6. Basically if you have a battery chemistry, such
as Li-ion, that cannot safely withstand an infinite duration
wake-up charge, the SafetySignal resistance value needs
to be less than 425Ω. The popular value to use is a fixed
300Ω resistor. Otherwise the resistance value is 10k which
is normally expected to be done using a 10k NTC resistor.
LTC4100
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applicaTions inForMaTion
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall times
should be minimized. To prevent magnetic and electrical
field radiation and high frequency resonant problems,
proper layout of the components connected to the IC is
essential. (See Figure 11.) Here is a PCB layout priority list
for proper layout. Layout the PCB using this specific order.
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for
a clean FET drive. This includes IC supply pins that
connect to the switching FET source pins. The IC can
be placed on the opposite side of the PCB relative to
above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time
with smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at
the sense resistor location.
5. Place output capacitors next to the sense resistor
output and ground.
6. Output capacitor ground connections need to feed
into same copper that connects to the input capacitor
ground before tying back into system ground.
Interfacing with a Selector
The LTC4100 is designed to be used with a true analog
multiplexer for the SafetySignal sensing path. Some
selector ICs from various manufacturers may not imple-
ment this. Consult LT C applications department for more
information.
Electronic Loads
The LTC4100 is designed to work with a real battery.
Electronic loads will create instability within the LTC4100
preventing accurate programming currents and volt-
ages. Consult LT C applications department for more
information.
LTC4100
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G24 SSOP 0204
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
1 2 3 4 5678 9 10 11 12
7.90 – 8.50*
(.311 – .335)
2122 18 17 16 15 14 13
19202324
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC4100
29
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For more information www.linear.com/LTC4100
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
(Revision history begins at Rev B)
REV DATE DESCRIPTION PAGE NUMBER
B 10/09 Add Table to Typical Application
Text Added to Pin Functions
Text Changes to Operation Section
Changes to Table 1
Added ‘Calculating VDD Current’ Section
Updated ‘Input and Output Capacitors’ Section
Added ‘SafetySignal (Thermistor) Value’ Section
Changes to Typical Application
1
8
11, 12, 15
13
23
25
26
29
C 02/14 SafetySignal Trip conditions: changed the value of RTHB from 54.9Ω to 54.9kΩ 4
LTC4100
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For more information www.linear.com/LTC4100
© LINEAR TECHNOLOGY CORPORATION 2006
LT 0214 REV C • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4100
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC1760 Smart Battery System Manager Autonomous Power Management and Battery Charging for Tw o Smart Batteries,
SMBus Rev 1.1 Compliant
LTC1960 Dual Battery Charger/Selector with SPI Interface Simultaneous Charge or Discharge of 2 Batteries, DAC Programmable Current
and Voltage, Input Current Limiting Maximizes Charge Current
LTC1980 Combination Battery Charger and DC/DC Converter Input Supply May be Above or Below Battery Voltage, up to 8.4V Float Voltage,
24-Pin SSOP Package
LTC4006 Small, High Efficiency, Fixed Voltage, Lithium-Ion
Battery Charger
Constant Current/Constant Voltage Switching Regulator with Termination Timer,
AC Adapter Current Limit and SafetySignal Sensor in a Small 16-Pin Package
LTC4007 High Efficiency, Programmable Voltage Battery
Charger with Termination
Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit,
SafetySignal Sensor and Indicator Outputs
LTC4008 High Efficiency, Programmable Voltage/Current
Battery Charger
Constant Current/Constant Voltage Switching Regulator; Resistor Voltage/
Current Programming, AC Adapter Current Limit and SafetySignal Sensor
LTC4101 Smart Battery Charger Controller For Smart Batteries with Voltages Below 5.5V
LTC4412 Low Loss PowerPath™ Controller Very Low Loss Replacement for Power Supply ORing Diodes Using Minimal
External Components
LTC4100 Li-Ion Battery Charger ILIM = 4A/VLIM = 17.4V, Adapter Rating = 2.7A
5
11
20
12
17
14
13
10
6
7
8
9
1
3
21
18
16
15
C4
0.01µF
25V
C5
0.1µF
10V
0.1µF
10V
C9
0.1µF
10V
R4
100Ω
300Ω
SDA
SCL
RTHB
54.9k
1%
RTHA
1.13k
1%
RSNS
0.025Ω
0.5W, 1%
R
CL
0.033Ω
0.5W
1%
OPTIONAL
DISCHARGE
PATH TO
SYSTEM
LOAD
C4,C5
10µF × 2
25V
X5R
C2, C3
10µF × 2
25V
X5R
SYSTEM
LOAD
Q3
Q1
DCIN
DCIN
100k
Q2
Q4
D6
R11
1.21k
1%
R5
6.04k
1%
C6, 0.12µF
10V, X7R
C8, 0.068µF
10V, X7R
C7, 0.0015µF
10V, X7R
R10
13.7k
1%
C1
0.1µF
15V TO 20V
DCIN
FROM WALL
ADAPTER
R1
4.9k
L1
10µH
4A
4 24 23
D1
D1: MBRM140T3G
D2-D5: SMALL SIGNAL SCHOTTKY
D6: 18V ZENER DIODE
Q1: 1/2 Si4925BDY
Q2: FDS6685
Q3: FDC645N
Q4: 1/2 Si4925
4100 TA02
R6, RVLIM 33k
SDA
SCL
10k10k
3V TO 5.5V
SafetySignal
D2
D3
D4
D5
4-CELL Li-Ion
SMART BATTERY
22
19
DCIN
DCDIV
IDC
GND
VDD
VLIM
ILIM
ACP
CHGEN
SMBALERT
SDA
SCL
INFET
TGATE
BGATE
CSP
VSET
THA
THB
CLNCLP
LTC4100
BAT
PGND
ITH 2
