2010-2011 Microchip Technology Inc. DS41418B
PIC16(L)F707
Data Sheet
40/44-Pin, Flash Microcontrollers
with nanoWatt XLP and
mTouch™ Technology
DS41418B-page 2 2010-2011 Microchip Technology Inc.
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by up dates. I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC , PI Cmi cro, PIC START,
PIC32 logo, rfPIC and UNI/O are registered trademark s of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In- Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PIC DEM .net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance ,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-157-5
Note the following details of the code protection feature on Microch ip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2010-2011 Microchip Technology Inc. DS41418B-page 3
PIC16(L)F707
Devices included in thi s data sheet:
High-Performance RISC CPU:
• Only 35 Single-Word Instructions to Learn:
- All single-cycle instructions except branches
• Operati ng Speed:
- DC – 20 MHz clock input
- DC – 200 ns instruction cycle
• 8K x 14 Words of Flash Program Memory
• 363 Bytes of Data Memory (SRAM)
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• Processor Read Access to Program Memory
• Pinout Compatible to other 40-pin PIC16CXXX
and PIC16FXXX Microcontrollers
S pecial Microcontroller Features:
• Precision Internal Oscillator:
- 16 MHz or 500 kHz operation
- Factory calibrated to ±1%, typical
- Software selectable ÷1, ÷2, ÷4 or ÷8 divider
• 31 kHz Low-Power Internal Oscillator
• Ext erna l Oscillator Block with:
- 3 crystal/resonator modes up to 20 MHz
- 3 external clock modes up to 20 MHz
• Pow er- on Reset (POR)
• Power-up Timer (PWRT)
• Oscillator Start-Up Timer (OST)
• Brown-out Reset (BOR):
- Selectable between two trip points
- Disabled in Sleep option
• Watchdog Timer (WDT)
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™) via two
pins
• In-Circuit Debug (ICD) via Two Pins
• Multiplexed Master Clear with Pull-up/Input Pin
• Industri al and Extended Tem pe r atu re Ra nge
• High-Endurance Flash Cell:
- 1,000 Write Flash Endurance (typical)
- Flash Retention: >40 years
- Power-Saving Sleep mode
• Operati ng Voltage Ran ge:
- 1.8V to 3.6V (PIC16LF707)
• 1.8V to 5.5V (PIC16F707)
Extreme Low-Power Management
PIC16LF707 with nanoWatt XLP:
• Sleep mode: 20 nA @ 1.8V, typical
• Watchdog Timer: 500 nA @ 1.8V, typical
• Timer1 Oscillator: 600 nA @ 1.8V, typical
@ 32 kHz
mTouch™ Technology Features:
• Up to 32 Channels
• Two Capacitive Sensing modules:
- Acquire 2 samples simultaneously
• Multiple Power modes:
- Operation during Sleep
- Proximity sensing with ul tra low µA current
• Adjustable Waveform Min. and Max. for Optimal
Noise Performance
• 1.8V to 5.5V Operation (3.6V max. for
PIC16LF707)
Analog Features:
• A/D Converter:
- 8-bit resolution and up to 14 channels
- Conversion available during Sleep
- Selectab le 1.0 24V/2 .04 8V/4 .09 6V voltage
reference
• On-chip 3.2V Regulator (PIC16F707 device only)
Peripheral Highl ight s:
• Up to 35 I/O Pins and 1 Input-only Pin:
- High current source/sink for direct LED drive
- Interrupt-on-pin change
- Individually programmable weak pull-ups
• Timer0/A/B: 8-Bit Timer/Counter with 8-Bit
Prescaler
• Enhanced Timer1/3:
- Dedicated low-power 32 kHz oscillator driver
- 16-bit timer/counter with prescaler
- External Gate Input mode with toggle and
single sh ot mod es
- Interrupt-on-gate completion
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Captu re, Compare, PWM modules (CCP):
- 16-bit Capture, max. resolution 12.5 ns
- 16-bit Compare, max. resolution 200 ns
- 10-bit PWM, max. frequency 20 kHz
• Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)
•PIC16F707
• PIC16LF707
40/44-Pin, Flash Microc ontrollers with
nanoWatt XLP and mTouch™ Technology
PIC16(L)F707
DS41418B-page 4 2010-2011 Microchip Technology Inc.
• Synchronous Serial Port (SSP):
- SPI (Master/Slave)
-I
2C™ (Slave) with Address Mask
• Voltage Refere nce mod ule :
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
reference selection
Pin Diagrams
Device Program
Memory Flash
(words)
SRAM
(bytes) I/Os Ca pacitive Touch
Channels 8-bit A/D
(ch) AUSART CCP Timers
8/16-bit
PIC16(L)F707 8192 363 36 32 14 Yes 2 4/2
40-PIN PDIP
PIC16F707/PIC16LF707
1
2
3
4
5
6
7
8
9
10
VPP/MCLR/RE3
VCAP(3)/SS(2)/AN0/RA0
CPSA0/AN1/RA1
DACOUT/CPSA1/AN2/RA2
CPSA2/VREF/AN3/RA3
TACKI/T0CKI/CPSA3/RA4
VCAP(3)/SS(2)/CPSA4/AN4/RA5
CPSA5/AN5/RE0
CPSA6/AN6/RE1
CPSA7/AN7/RE2
RB6/CPSB14/ICSPCLK
RB5/AN13/CPSB13/T1G/T3CKI
RB4/AN11/CPSB12
RB3/AN9/CPSB11/CCP2(1)
RB2/AN8/CPSB10
RB1/AN10/CPSB9
RB0/AN12/CPSB8/INT
VDD
VSS
RD2/CPSB7
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
VSS
CLKIN/OSC1/CPSB0/RA7
VCAP(3)/CLKOUT/OSC2/CPSB1/RA6
T1CKI/T1OSO/CPSB2/RC0
CCP2(1)/T1OSI/CPSB3/RC1
TBCKI/CCP1/CPSB4/RC2
SCL/SCK/RC3
T3G/CPSB5/RD0
CPSB6/RD1
RC5/CPSA9/SDO
RC4/SDI/SDA
RD3/CPSA8
RD4/CPSA12
RC7/CPSA11/RX/DT
RC6/CPSA10/TX/CK
RD7/CPSA15
RD6/CPSA14
RD5/CPSA13
RB7/CPSB15/ICSPDAT
Note 1: CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F707 only.
2010-2011 Microchip Technology Inc. DS41418B-page 5
PIC16(L)F707
Pin Diagrams
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
CPSA2/VREF/AN3/RA3
DACOUT/CPSA1/AN2/RA2
CPSA0/AN1/RA1
VCAP(3)/SS(2)/AN0/RA0
VPP/MCLR/RE3
CCP2(1)/CPSB11/AN9/RB3
ICSPDAT/CPSB15/RB7
ICSPCLK/CPSB14/RB6
T3CKI/T1G/CPSB13/AN13/RB5
CPSB12/AN11/RB4
NC RC6/CPSA10/TX/CK
RC5/CPSA9/SDO
RC4/SDI/SDA
RD3/CPSA8
RD2/CPSB7
RD1/CPSB6
RD0/CPSB5/T3G
RC3/SCK/SCL
RC2/CPSB4/CCP1/TBCKI
RC1/CPSB3/T1OSI/CCP2(1)
RC0/CPSB2/T1OSO/T1CKI
RA6/OSC2/CLKOUT/CPSB1/VCAP(3)
RA7/OSC1/CLKIN/CPSB0
VSS
VSS
NC
VDD
RE2/AN7/CPSA7
RE1/AN6/CPSA6
RE0/AN5/CPSA5
RA5/AN4/CPSA4/SS(2)/VCAP(3)
RA4/CPSA3/T0CKI/TACKI
DT/RX/CPSA11/RC7
CPSA12/RD4
CPSA13/RD5
CPSA14/RD6
CPSA15/RD7
VSS
VDD
VDD
INT/CPSB8/AN12/RB0
CPSB9/AN10/RB1
CPSB10/AN8/RB2
44-PIN QFN (8x8x0.9)
PIC16F707
PIC16LF707
Note 1: CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F707 only.
PIC16(L)F707
DS41418B-page 6 2010-2011 Microchip Technology Inc.
Pin Diagrams
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
VREF/CPSA2/AN3/RA3
DACOUT/CPSA1/AN2/RA2
CPSA0/AN1/RA1
VCAP(3)/SS(2)/AN0/RA0
VPP/MCLR/RE3
NC
ICSPDAT/CPSB15/RB7
ICSPCLK/CPSB14/RB6
T1G/CPSB13/AN13/RB5
CPSB12/AN11/RB4
NC RC6/CPSA10/TX/CK
RC5/CPSA9/SDO
RC4/SDI/SDA
RD3/CPSA8
RD2/CPSB7
RD1/CPSB6
RD0CPSB5/T3G
RC3//SCK/SCL
RC2CPSB4/CCP1/TBCKI
RC1/CPSB3/T1OSI/CCP2(1)
NC
NC
RC0/T1OSO/T1CKI/CPSB2
RA6/OSC2/CLKOUT/CPSB1/VCAP(3)
RA7/OSC1/CLKIN/CPSB0
VSS
VDD
RE2/AN7/CPSA7
RE1/AN6/CPSA6
RE0/AN5/CPSA5
RA5/AN4/CPSA4/SS(2)/VCAP(3)
RA4/CPSA3/T0CKI/TACKI
DT/RX/CPSA11/RC7
CPSA12/RD4
CPSA13/RD5
CPSA14/RD6
VSS
VDD
INT/CPSB8/AN12/RB0
CPSB9/AN10/RB1
CPSB10/AN8/RB2
CCP2(1)/CPSB11/AN9/RB3
CPSA15/RD7 5
4PIC16F707
PIC16LF707
44-PIN TQFP
Note 1: CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F707 only.
2010-2011 Microchip Technology Inc. DS41418B-page 7
PIC16(L)F707
Pin Diagrams
10
2
3
4
5
6
1
18
19
20
21
22
12
13
11
15
38
8
7
33
32
40
39
16
17
29
30
31
23
24
25
26
27
28
36
34
35
9
37
CPSA2/VREF/AN3/RA3
DACOUT/CPSA1/AN2/RA2
CPSA0/AN1/RA1
VCAP/SS(2)/AN0/RA0
VPP/MCLR/RE3
CCP2(1)/CPSB11/AN9/RB3
ICSPDAT/CPSB15/RB7
ICSPCLK/CPSB14/RB6
T3CKI/T1G/CPSB13/AN13/RB5
CPSB12/AN11/RB4 RC6/CPSA10/TX/CK
RC5/CPSA9/SDO
RC4/SDI/SDA
RD3/CPSA8
RD2/CPSB7
RD1/CPSB6
RD0/CPSB5/T3G
RC3/SCK/SCL
RC2/CPSB4/CCP1/TBCKI
RC1/CPSB3/T1OSI/CCP2(1)
RC0/CPSB2/T1OSO/T1CKI
RA6/OSC2/CLKOUT/CPSB1/VCAP(3)
RA7/OSC1/CLKIN/CPSB0
VSS
VDD
RE2/AN7/CPSA7
RE1/AN6/CPSA6
RE0/AN5/CPSA5
RA5/AN4/CPSA4/SS(2)/VCAP(3)
RA4/CPSA3/T0CKI/TACKI
DT/RX/CPSA11/RC7
CPSA12/RD4
CPSA13/RD5
CPSA14/RD6
CPSA15/RD7
VSS
VDD
INT/CPSB8/AN12/RB0
CPSB9/AN10/RB1
CPSB10/AN8/RB2
40-PIN UQFN (5x5x0.5)
PIC16F707
PIC16LF707
Note 1: CCP2 pi n locat io n may be selec ted as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F707 only.
14
PIC16(L)F707
DS41418B-page 8 2010-2011 Microchip Technology Inc.
TABLE 1: 40/44-PIN ALLOCATION TABLE FOR PIC16F70 7/P IC16LF7 07
I/O
40-Pin PDIP
44-Pin TQFP
44-Pin QF N
40-Pin U QF N
ANSEL
A/D
DAC
Cap Sensor
Timers
CCP
AUSART
SSP
Interrupt
Pull-up
Basic
RA0 219 19 17 YAN0 — — — — SS(3) — — VCAP(4)
RA1 3 20 20 18 Y AN1 — CPSA0 — — — — — — —
RA2 421 21 19 YAN2 DACOUT CPSA1 — — — — — — —
RA3 5 22 22 20 Y AN3/
VREF VREF CPSA2 — — — — — — —
RA4 623 23 21 Y — — CPSA3 T0CKI/
TACKI — — — — — —
RA5 7 24 24 22 Y AN4 — CPSA4 — — — SS(3) ——VCAP(4)
RA6 14 31 33 29 Y — — CPSB1 — — — — — — OSC2/
CLKOUT/
VCAP(4)
RA7 13 30 32 28 Y — — CPSB0 — — — — — — OSC1/
CLKIN
RB0 33 8 9 8 Y AN12 —CPSB8 — — — — IOC/INT Y —
RB1 34 9 10 9 Y AN10 — CPSB9 — — — — IOC Y —
RB2 35 10 11 10 YAN8 —CPSB10 — — — — IOC Y —
RB3 36 11 12 11 Y AN9 — CPSB11 — CCP2(2) ——IOCY —
RB4 37 14 14 12 YAN11 —CPSB12 — — — — IOC Y —
RB5 38 15 15 13 Y AN13 — CPSB13 T1G/
T3CKI ———IOCY—
RB6 39 16 16 14 Y — — CPSB14 — — — — IOC YICSPCLK/
ICDCLK
RB7 40 17 17 15 Y — — CPSB15 — — — — IOC Y ICSPDAT/
ICDDAT
RC0 15 32 34 30 Y — — CPSB2 T1OSO/
T1CKI — — — — — —
RC1 16 35 35 31 Y — — CPSB3 T1OSI CCP2(2) —— ———
RC2 17 36 36 32 Y — — CPSB4 TBCKI CCP1 — — — — —
RC3 18 37 37 33 — — — — — — — SCK/
SCL —— —
RC4 23 42 42 38 — — — — — — — SDI/
SDA — — —
RC5 24 43 43 39 Y — — CPSA9 — — — SDO — — —
RC6 25 44 44 40 Y — — CPSA10 — — TX/CK — — — —
RC7 26 1 1 1 Y — — CPSA11 — — RX/DT — — — —
RD0 19 38 38 34 Y — — CPSB5 T3G — — — — — —
RD1 20 39 39 35 Y — — CPSB6 — — — — — — —
RD2 21 40 40 36 Y — — CPSB7 — — — — — — —
RD3 22 41 41 37 Y — — CPSA8 — — — — — — —
RD4 27 2 2 2 Y — — CPSA12 — — — — — — —
RD5 28 3 3 3 Y — — CPSA13 — — — — — — —
RD6 29 4 4 4 Y — — CPSA14 — — — — — — —
RD7 30 5 5 5 Y — — CPSA15 — — — — — — —
RE0 825 25 23 YAN5 —CPSA5 — — — — — — —
RE1 9 26 26 24 Y AN6 — CPSA6 — — — — — — —
RE2 10 27 27 25 YAN7 —CPSA7 — — — — — — —
RE3 1 18 18 16 — — — — — — — — — Y(1) MCLR/
VPP
Note 1: Pul l-up activated only wi th external MCLR configuration.
2: RC1 is the default pin locati on for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
3: RA5 is the default pi n locat io n for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.
4: PIC16F707 only. VCAP functionality is selectable by the VCAPEN bits in Configuration Word 2.
2010-2011 Microchip Technology Inc. DS41418B-page 9
PIC16(L)F707
VDD 11, 32 7, 28 7, 8, 28 7,
26 — — — — — — — — — VDD
Vss 12, 31 6, 29 6, 30,
31 6,
27 —— — — —————VSS
TABLE 1: 40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707
I/O
40-Pin PDIP
44-Pin TQFP
44-Pin QF N
40-Pin UQFN
ANSEL
A/D
DAC
Cap Sensor
Timers
CCP
AUSART
SSP
Interrupt
Pull-up
Basic
Note 1: Pul l-up activated only wi th external MCLR configuration.
2: RC1 is the default pin locati on for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
3: RA5 is the default pi n locat io n for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.
4: PIC16F707 only. VCAP functionality is selectable by the VCAPEN bits in Configuration Word 2.
PIC16(L)F707
DS41418B-page 10 2010-2011 Microchip Technology Inc.
Table of Contents
1.0 Device Overview ....................................................................................................................................................................... 13
2.0 Memory Organization....................................................................................................................................... ...... ...... ..... ...... .. 19
3.0 Resets ....................................................................................................................................................................................... 31
4.0 Interrupts ....................................................................................................................................... ...... ..... ...... ...... ...... ..... ...... .... 4 1
5.0 Low Dropout (LDO) Voltage Regulator...................................................................................................................................... 51
6.0 I/O Po rts.................................................................................................................................................................................... 53
7.0 Oscillator Module..................................................................................................................................... . ...... ...... ...... ..... ...... .... 71
8.0 Device Configuration........................................................................................................................................ .. ...... ..... ...... ...... 77
9.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 81
10.0 Fixed Voltage Reference........................................................................................................................................................... 91
11.0 Digital-to-Analog Conver ter (DAC) Module ............................................................................................................................... 93
12.0 Timer0 Module......................................................................................................................................... ..... ...... ...... ..... ...... ...... 97
13.0 Timer1/3 Modules with Gate Control........................................................................................................................................ 101
14.0 TimerA/B Modules................................................................................................................................................................... 113
15.0 Timer2 Module......................................................................................................................................................................... 117
16.0 Capacitive Sensing Module..................................................................................................................................................... 119
17.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................. 129
18.0 Addressable Universal Synchronous Asynch ronous Receiver Transmitter (AUSART)........................................................... 139
19.0 SSP Module Overview ..................................................................................................................................... ...... ...... ..... ...... 159
20.0 Program Memory Read........................................................................................................................................................... 181
21.0 Power-Down Mode (Sleep) ..................................................................................................................................................... 185
22.0 In-Circuit Serial Programming™ (IC SP™ ) .............................................................................................................................. 187
23.0 Instruction Set Summary......................................................................................................................................................... 189
24.0 Development Support ....................................................................................................................................... .. ...... ..... ...... .... 199
25.0 Electrical Specifications........................................................................................................................................................... 203
26.0 DC and AC Characteristics Graphs and Charts...................................................................................................................... 233
27.0 Packaging Information............................................................................................................................................................. 269
Appendix A: Data Sheet Revision History....................................................................................................................................... .. 279
Appendix B: Migrating From Other PIC® Devices............................................................................................................................ 279
The Microchip Web Site..................................................................................................................................... ...... .......... ..... ...... .... 2 8 7
Customer Change Notification Service ..................................................................................................................................... .. ...... 287
Customer Support ............................................................................................................................................................................. 287
Reader Response................................................................................................................................... .. ...... ..... ...... ...... ...... ..... ...... 288
Product Ide n ti fi catio n System............................................................................................................................................................. 289
2010-2011 Microchip Technology Inc. DS41418B-page 11
PIC16(L)F707
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PIC16(L)F707
DS41418B-page 12 2010-2011 Microchip Technology Inc.
NOTES:
PIC16(L)F707
DS41418B-page 14 2010-2011 Microchip Technology Inc.
FIGURE 1-1: PIC16(L)F707 BLOCK DIAGRAM
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
PORTA
PORTB
PORTC
PORTD
PORTE
RA4
RA5
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RE0
RE1
RE2
8
8
Timer0
RA3
RA1
RA0
8
3
RA6
RA7
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RB0
RB1
RB2
RB3
RB4
RB5
RB7
AN6
AN0 AN1 AN2 AN3 AN4 AN5 AN7
Synchronous
SDA SCL SSSDO
Serial Port
SDI/ SCK/
TX/CK RX/DT
Internal
Oscillator
Block
Configuration 13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
Direct Addr 7
RAM Addr
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
PORTB
PORTC
PORTD
PORTE
RC1
8
8
8
3
Synchronous
SDA SCL SSSDO
Serial Port
SDI/ SCK/
Internal
Oscillator
Block
Configuration 13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
8 Level Stack
(13-bit)
7
Addr MUX
FSR Reg
STATUS Reg
MUX
ALU
Instruction
Decode and
Control
Timing
Generation
PORTB
PORTC
PORTD
PORTE
RC1
8
8
8
3
Analog-To-Digital Converter
RB6
Synchronous
SDA SCL SSSDO
Serial Port
SDI/ SCK/
Internal
Oscillator
Block
Configuration
RE3
CCP2
CCP2
CCP1
CCP1
VREF
RA2
AN9AN8 AN10 AN11 AN12 AN13
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VDD
Brown-out
Reset
VSS
T0CKI T1G T1CKI
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VDD
Brown-out
Reset
VSS
T0CKI
MCLR VDD VSS
T0CKI
Timer1
32 kHz
Oscillator
T1OSI
T1OSO
LDO
Regulator
Capacitive Sensing Module A
CPSA6CPSA0 CPSA1 CPSA2 CPSA3 CPSA4 CPSA7 CPSA8 CPSA9 CPSA10 CPSA11 CPSA12 CPSA13 CPSA14 CPSA15
CPSA5
Flash
Program
Memory RAM
T3G T3CKI
Timer1 Timer2 Timer3 TimerA TimerB AUSART
TACKI TBCKI
CPSB6CPSB0 CPSB1 CPSB2 CPSB3 CPSB4 CPSB7 CPSB8 CPSB9 CPSB10 CPSB11 CPSB12 CPSB13 CPSB14 CPSB15
CPSB5
Capacitive Sensing Module B
Digital-To-Analog
DACOUT
Converter
2010-2011 Microchip Technology Inc. DS41418B-page 15
PIC16(L)F707
TABLE 1-1: PIC16(L)F707 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
RA0/AN0/SS/VCAP RA0 T TL CMOS General purpose I/O.
AN0 AN — A/D Channel 0 input.
SS ST — Slave Select input.
VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F only).
RA1/AN1/CPSA0 RA1 TTL CMOS General purpose I/O.
AN1 AN — A/D Channel 1 input.
CPSA0 AN — Capacitive sensing A input 0.
RA2/AN2/CPSA1/DACOUT RA2 TTL CMOS General purpose I/O.
AN2 AN — A/D Channel 2 input.
CPSA1 AN — Capacitive sensing A input 1.
DACOUT — AN Voltage Reference Output.
RA3/AN3/VREF/CPSA2 RA3 TTL CMOS General purpose I/O.
AN3 AN — A/D Channel 3 input.
VREF AN — A/D Voltage Reference input.
CPSA2 AN — Capacitive sensing A input 2.
RA4/CPSA3/T0 CKI/TACKI RA4 TTL CMOS General purpose I/O.
CPSA3 AN — Capacitive sensing A input 3.
T0CKI ST — Timer0 clock input.
TACKI ST — TimerA clock input.
RA5/AN4/CPSA4/SS/VCAP RA5 TTL CMOS General purpose I/O.
AN4 AN — A/D Channel 4 input.
CPSA4 AN — Capacitive sensing A input 4.
SS ST — Slave Select input.
VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F only).
RA6/OSC2/CLKOUT/VCAP/
CPSB1 RA6 TTL CMOS General purpose I/O.
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS FOSC/4 output.
VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F only).
CPSB1 AN — Capacitive sensing B input 1.
RA7/OSC1/CLKIN/ CPSB0 RA7 TTL CMOS General purpose I/O.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
CLKIN CMOS — External clock input (EC mode).
CLKIN ST — RC oscillator connection (RC mode).
CPSB0 AN — Capacitive sensing B input 0.
RB0/AN12/CPSB 8/INT RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN12 AN — A/D Channel 12 input.
CPSB8 AN — Capacitive sensing B input 8.
INT ST — Exter n a l in te rrupt.
RB1/AN10/CPSB 9 RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN10 AN — A/D Channel 10 input.
CPSB9 AN — Capacitive sensing B input 9.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt T rigger input with I2C
HV = High Voltage XTAL = Crystal levels
PIC16(L)F707
DS41418B-page 16 2010-2011 Microchip Technology Inc.
RB2/AN8/CPSB10 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN8 AN — A/D Channel 8 input.
CPSB10 AN — Capacitive sensing B input 10.
RB3/AN9/CPSB11/CCP2 RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-ch ange.
Individually enabled pull-up.
AN9 AN — A/D Channel 9 input.
CPSB11 AN — Capacitive sensing B input 11.
CCP2 ST CMOS Capture/Compare/PWM2.
RB4/AN11/CPSB12 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-ch ange.
Individually enabled pull-up.
AN11 AN — A /D Channel 11 input.
CPSB12 AN — Capacitive sensing B input 12.
RB5/AN13/CPSB 13/T1G/T3CK I RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN13 AN — A/D Channel 13 input.
CPSB13 AN — Capacitive sensing B input 13.
T1G ST — Timer1 gate input.
T3CKI ST — Timer3 clock input.
RB6/ICSPCLK/ICDCLK/CPSB14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
ICSPCLK ST — Serial Programming Clock.
ICDCLK ST — In-Circuit Debug Clock.
CPSB14 AN — Capacitive sensing B input 14.
RB7/ICSPDAT/ICDDAT/CPSB15 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
ICSPDAT ST CM OS ICSP™ Data I/O.
ICDDAT ST — In-Circuit Data I/O.
CPSB15 AN — Capacitive sensing B input 15.
RC0/T1OSO/T1CKI/CP SB2 RC0 ST CMOS G eneral purpose I/O.
T1OSO XTAL X TAL Timer1 oscillator connection.
T1CKI ST — Timer1 clock input.
CPSB2 AN — Capacitive sensing B input 2.
RC1/T1OSI/CCP2/ CPS B3 RC1 ST CMOS G eneral purpose I/O.
T1OSI X TAL XTAL Timer1 oscillator connection.
CCP2 ST CMOS Capture/Compare/PWM2.
CPSB3 AN — Capacitive sensing B input 3.
RC2/CCP1/CPSB4/T BCKI RC2 ST CMOS General purpose I/O.
CCP1 ST CMOS Capture/Compare/PWM1.
CPSB4 AN — Capacitive sensing B input 4.
TBCKI ST — TimerB clock input.
RC3/SCK/SCL RC3 ST CMOS General purpose I/O.
SCK ST CMOS SPI clock.
SCL I2C™ OD I2C™ clock.
TABLE 1-1: PIC16(L)F707 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt T rigger input with I2C
HV = High Voltage XTAL = Crystal le vels
2010-2011 Microchip Technology Inc. DS41418B-page 17
PIC16(L)F707
RC4/SDI/SDA RC4 ST CMOS General purpose I/O.
SDI ST — SPI data input.
SDA I2C™ OD I2C™ data input/output.
RC5/SDO/CPSA9 RC5 ST CMOS G eneral purpose I/O.
SDO — CMOS SPI data output.
CPSA9 AN — Capacitive sensing A input 9.
RC6/TX/CK/CPSA10 RC6 ST CMOS General purpose I/O.
TX — CMOS USART asynchronous transmit.
CK ST CMOS USART synchronous clock.
CPSA10 AN — Capacitive sensing A input 10.
RC7/RX/DT/C P SA11 RC7 ST CMOS General purpose I/O.
RX ST — USART asynchronous input.
DT ST CMOS USART synchronous data.
CPSA11 AN — Capacitive sensing A input 11.
RD0/CPSB5/T3G RD0 ST CMOS G eneral purpose I/O.
CPSB5 AN — Capacitive sensing B input 5.
T3G ST — Timer3 Gate input.
RD1/CPSB6 RD1 ST CMOS General purpose I/O.
CPSB6 AN — Capacitive sensing B input 6.
RD2/CPSB7 RD2 ST CMOS General purpose I/O.
CPSB7 AN — Capacitive sensing B input 7.
RD3/CPSA8 RD3 ST CMOS General purpose I/O.
CPSA8 AN — Capacitive sensing A input 8.
RD4/CPSA12 RD4 ST CMOS General purpose I/O.
CPSA12 AN — Capacitive sensing A input 12.
RD5/CPSA13 RD5 ST CMOS General purpose I/O.
CPSA13 AN — Capacitive sensing A input 13.
RD6/CPSA14 RD6 ST CMOS General purpose I/O.
CPSA14 AN — Capacitive sensing A input 14.
RD7/CPSA15 RD7 ST CMOS General purpose I/O.
CPSA15 AN — Capacitive sensing A input 15.
RE0/AN5/CPSA5 RE0 ST CMO S G eneral purpose I/O.
AN5 AN — A/D Channel 5 input.
CPSA5 AN — Capacitive sensing A input 5.
RE1/AN6/CPSA6 RE1 ST CMO S G eneral purpose I/O.
AN6 AN — A/D Channel 6 input.
CPSA6 AN — Capacitive sensing A input 6.
RE2/AN7/CPSA7 RE2 ST CMO S G eneral purpose I/O.
AN7 AN — A/D Channel 7 input.
CPSA7 AN — Capacitive sensing A input 7.
RE3/MCLR/VPP RE3 TTL — General purpose input.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Program ming voltage.
VDD VDD Power — Positive supply.
TABLE 1-1: PIC16(L)F707 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt T rigger input with I2C
HV = High Voltage XTAL = Crystal levels
PIC16(L)F707
DS41418B-page 18 2010-2011 Microchip Technology Inc.
VSS VSS Power — Ground reference.
Note: The PIC16F707 devices have an internal low dropout voltage regulator. An external capacitor must be
connected to one of the available VCAP pins to stabilize the regulator. For more information, see
Section 5.0 “Low Dropout (LDO) Voltag e Regulator”. The PIC16LF 707 devic es do n ot ha ve the volta ge
regulator and therefore no external capacitor is required.
TABLE 1-1: PIC16(L)F707 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt T rigger input with I2C
HV = High Voltage XTAL = Crystal le vels
2010-2011 Microchip Technology Inc. DS41418B-page 19
PIC16(L)F707
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC16(L)F707 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The Reset vector is at 0000h and the interrupt
vector is at 0004 h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16(L)F707
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.
RP1 RP0
00Bank 0 is selected
01Bank 1 is selected
10Bank 2 is selected
11Bank 3 is selected
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.
2.2.1 GENERAL PURPOSE REGI STER
FILE
The register file is organized as 363 x 8 bits. Each
register is accessed either directly or indirectly through
the File Select Register (FSR), (Refer to Section 2.5
“Indirect Addressing, INDF a nd FSR Reg isters ” ).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (refer to Table 2-2).
These reg ister s ar e static R AM.
The Special Function Registers can be classified into
two sets: core and peripheral. The Special Function
Registers associated with the “core” are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
PC<12:0>
13
0000h
0004h
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
0005h
On-chip
1FFFh
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
Page 2
Page 3
17FFh
1800h
PIC16(L)F707
DS41418B-page 20 2010-2011 Microchip Technology Inc.
TABLE 2-1: DATA MEMORY MAP FOR PIC16(L)F707
Legend: = Unimplemented data memory locations, read as ‘0’,
* = Not a phys ical re gist e r
File Address
Indir e ct ad d r.(*) 00h Indirec t addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h
TMR0 01h OPTION 81h TMR0 101h OPTION 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h TACON 105h ANSELA 185h
PORTB 06h TRISB 86h CPSBCON0 106h ANSELB 186h
PORTC 07h TRISC 87h CPSBCON1 107h ANSELC 187h
PORTD 08h TRISD 88h CPSACON0 108h ANSELD 188h
PORTE 09h TRISE 89h CPSACON1 109h ANSELE 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch
PIR2 0Dh PIE2 8Dh PMADRL 10Dh Reserved 18Dh
TMR1L 0Eh PCON 8Eh PMDATH 10Eh Reserved 18Eh
TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh Reserved 18Fh
T1CON 10h OSCCON 90h TMRA 110h
General
Purpose
Register
16 Bytes
190h
TMR2 11h OSCTUNE 91h TBCON 111h 191h
T2CON 12h PR2 92h TMRB 112h 192h
SSPBUF 13h SSPADD/SSPMSK 93h DACCON0 113h 193h
SSPCON 14h SSPSTAT 94h DACCON1 114h 194h
CCPR1L 15h WPUB 95h
General
Purpose
Register
11 Bytes
115h 195h
CCPR1H 16h IOCB 96h 116h 196h
CCP1CON 17h T3CON 97h 117h 197h
RCSTA 18h TXSTA 98h 118h 198h
TXREG 19h SPBRG 99h 119h 199h
RCREG 1Ah TMR3L 9Ah 11Ah 19Ah
CCPR2L 1Bh TMR3H 9Bh 11Bh 19Bh
CCPR2H 1Ch APFCON 9Ch 11Ch 19Ch
CCP2CON 1Dh FVRCON 9Dh 11Dh 19Dh
ADRES 1Eh T3GCON 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
General
Purpose
Register
96 Bytes
20h
7Fh
General
Purpose
Register
80 Bytes
A0h
EFh
General
Purpose
Register
80 Bytes
120h
16Fh
General
Purpose
Register
80 Bytes
1A0h
1EFh
Accesses
70h – 7Fh F0h
FFh
Accesses
70h – 7Fh 170h
17Fh
Accesses
70h – 7Fh 1F0h
1FFh
BANK 0 BANK 1 BANK 2 BANK 3
2010-2011 Microchip Technology Inc. DS41418B-page 21
PIC16(L)F707
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on all
other
resets
Bank 0
00h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 T imer0 Module Register 0000 0000 0000 0000
02h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
03h(2) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
04h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
05h PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
09h PORTE — — — — RE3 RE2 RE1 RE0 ---- xxxx ---- uuuu
0Ah(1),(2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(2) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF 0000 ---0 0000 ---0
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON0000 00-0 uuuu uu-u
11h TMR2 Timer2 Module Register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h C CP R1 H Captur e/Co mpar e/P WM R egis t er 1 (MSB ) xxxx xxxx uuuu uuuu
17h CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CC PR 2 H Capture/Compare/P WM Regi s ter 2 (MS B) xxxx xxxx uuuu uuuu
1Dh CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.
PIC16(L)F707
DS41418B-page 22 2010-2011 Microchip Technology Inc.
Bank 1
80h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
81h OPTION_REG RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
83h(2) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
84h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE ———— ‘1’ TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111
8Ah(1),(2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh(2) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE 0000 ---0 0000 ---0
8Eh PCON — — — — — —PORBOR ---- --qq ---- --uu
8Fh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
90h OSCCON —— IRCF1 IRCF0 ICSL ICSS — — --10 00-- --10 uu--
91h OSCTUNE —— TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000
92h P R2 Timer2 Period Regi ster 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address R egist er 0000 0000 0000 0000
93h(3) SSPMSK Synchrono us Serial Port (I2C mode) Address Mask Register 1111 1111 1111 1111
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000
97h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 — T3SYNC —TMR3ON0000 -0-0 uuuu -u-u
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
9Ah TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
9Bh TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
9Ch APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00
9Dh FVRCON FVRRDY FVREN —— CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 x000 0000 x000 0000
9Eh T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/
DONE T3GVAL T3GSS1 T3GSS0 0000 0x00 uuuu uxuu
9Fh ADCON1 — ADCS2 ADCS1 ADCS0 —— ADREF1 ADREF0 -000 --00 -000 --00
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on all
other
resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.
2010-2011 Microchip Technology Inc. DS41418B-page 23
PIC16(L)F707
Bank 2
100h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
101h TMR0 Timer0 Module Register 0000 0000 0000 0000
102h(2) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
103h(2) STATUS IRP RP1 RP0 TOPD ZDCC0001 1xxx 000q quuu
104h() FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
105h TACON TMRAON — TACS TASE TAPSA TAPS2 TAPS1 TAPS0 0-00 0000 0-00 0000
106h CPSBCON0 CPSBON CPSBRM —— CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000
107h CPSBCON1 — — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000
108h CPSACON0 CPSAON CPSARM —— CPSARNG1 CPSARNG0 CPSAOUT TAXCS 0--- 0000 0--- 0000
109h CPSACON1 — — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000
10Ah(1),(2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh(2) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
10Ch PMDATL Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
10Dh PMADRL Program Memory Read Address Register Low Byte xxxx xxxx uuuu uuuu
10Eh PMDATH —— Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
10Fh PMADRH — — — Program Memory Re ad Address Register High By te ---x xxxx ---u uuuu
110h TMRA TimerA Module Register 0000 0000 0000 0000
111h TBCON TMRBON — TBCS TBSE TBPSA TBPS2 TBPS1 TBPS0 0-00 0000 0-00 0000
112h TMRB TimerB Module Register 0000 0000 0000 0000
113h DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — — 000- 00-- 000- 00--
114h DACCON1 — — — DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on all
other
resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.
PIC16(L)F707
DS41418B-page 24 2010-2011 Microchip Technology Inc.
Bank 3
180h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
181h OPTION_REG RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
183h(2) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
184h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
185h ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111
186h ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111
187h ANSELC ANSC7 ANSC6 ANSC5 —— ANSC2 ANSC1 ANSC0 111- -111 111- -111
188h ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111
189h ANSELE — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111
18Ah(1),(2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh(2) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
18Ch PMCON1 — — — — — — —RD1--- ---0 1--- ---0
18Dh —Reserved — —
18Eh —Reserved — —
18Fh —Reserved — —
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on all
other
resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.
2010-2011 Microchip Technology Inc. DS41418B-page 25
PIC16(L)F707
2.2.2.1 STATUS Register
The S TATUS registe r, shown in Register 2-1, co nt ains:
• the arithmetic status of t he ALU
• the Reset status
• the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 23.0
“Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
REGISTER 2-1: STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDC
(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Select bi t (use d for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rot ate (RRF, RLF) in structions , this b it is loaded with ei ther the hi gh-order or low-orde r
bit of the source register.
PIC16(L)F707
DS41418B-page 26 2010-2011 Microchip Technology Inc.
2.2.2.2 OPTION Register
The OPTION register, shown in Register 2-2, is a
readable and writable register, which contains various
control bits to configure:
• Timer0/WDT prescaler
• External R B0/INT interrup t
•Timer0
• Weak pull-ups on PORTB
Note: To achie ve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting PSA bit of t he OP T IO N r eg i ste r
to ‘1’. Refer to Section 13.3 “Timer1/3
Prescaler”.
REGISTER 2-2: OPTION_REG: OPTI ON REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual bits in the WPUB register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 TMR0CS: Timer0 Clock Source Select bit
1 = Transit ion on RA4/T0CKI pin
0 = Internal instruction cycle clo ck (FOSC/4)
bit 4 TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA 4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assig nment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate
2010-2011 Microchip Technology Inc. DS41418B-page 27
PIC16(L)F707
2.2.2.3 PCON Regist er
The Power Control (PCON) register contains flag bits
(refer to Table 3-4) to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
The PCON register bits are shown in Register 2-3.
REGISTER 2-3: PCON: POWER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-q R/W-q
— — — — — —PORBOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
q = Value depends on condition
bit 7-2 Unimplemented: Read as ‘0’
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Re set occurred (m us t be se t in s of tware af ter a Power-on Reset or Brow n -out Reset
occurs)
PIC16(L)F707
DS41418B-page 28 2010-2011 Microchip Technology Inc.
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register , which is a readable
and writable r egister. The high byte (PC<12:8>) is not
directly readable or writable and comes from
PCLA TH. On any Reset, the PC is cleared. Figure 2-2
shows the two situations for the loading of the PC. The
upper example in Figure 2-2 shows how the PC is
loaded on a write to PCL (PCLATH<4:0> PCH).
The lower example in Figure 2-2 shows how the PC is
loaded during a CALL or GOTO instruction
(PCLATH<4: 3> PCH).
FIGURE 2-2: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COMPUTED GOTO
A comput ed GOTO is a ccom pli shed by addi ng a n offset
to the program counter (ADDWF PCL). When
performing a table read using a computed GOTO
method, care should be exercised if the table location
crosses a PCL memory boundary (each 256-byte
block). Refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
2.3.2 STACK
All devices have an 8-level x 13-bit wide hardware
stack (refer to Figure 2-1). The stack space is not part
of either program or data space and the Stack Pointer
is not readable o r writ able. The PC is PUSHed onto the
stack when a CALL instruction is executed or an
interrupt causes a branch. The stack is POPed in the
event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
The st ack operates as a circular buffer . This means that
after the st ack h as be en PU SHed ei gh t time s, th e nint h
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).
2.4 Program Memory Paging
All devices are capable of addressing a continuous 8K
word block of program memory. The CALL and GOTO
instructions provide only 11 bits of address to allow
branchi ng with in any 2K prog ram memory pag e. When
doing a CALL or GOTO instruction, the upper 2 bits of
the address are provided by PCLATH<4:3>. When
doing a CALL or GOTO instruction, the user must ensure
that the page select bits are programmed so that the
desired program memo ry page is addressed. If a retu rn
from a CALL instruction (or interrupt) is executed, the
entire 13-bit PC is POPed off the stack. Therefore,
manipulation of the PCLATH<4 :3> bits is not required
for the RETURN ins tructio ns (whi ch POPs the addr ess
from the stack).
Example 2-1 shows the calling of a subroutine in
page 1 of t he program m emory . This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routi ne (if interrupts are used).
EXAMPLE 2-1: CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU Result
GOTO, CALL
OPCODE<10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interr upt add res s.
Note: The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite th e co nten ts of the PCLATH regis-
ter for any subsequent subroutine calls or
GOTO instructions.
ORG 500h
PAGESEL SUB_P1 ;Select page 1
;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 900h ;page 1 (800h-FFFh)
SUB1_P1 : ;called subroutine
;page 1 (800h-FFFh)
:
RETURN ;return to
;Call subroutine
;in page 0
;(000h-7FFh)
2010-2011 Microchip Technology Inc. DS41418B-page 29
PIC16(L)F707
2.5 Indirect Addressing, INDF and
FSR Registers
The INDF register is no t a physica l register. Addressin g
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit of
the STATUS register, as shown in Figure 2-3.
A simple program to clear RAM location 020h-02Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: INDIRECT ADDRESSING
FIGURE 2-3: DIRECT/INDIRECT ADDRESSING
MOVLW 020h ;initialize pointer
MOVWF FSR ;to RAM
BANKISEL 020h
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE ;yes continue
Note: For memory map detail, refer to Table 2-2.
Data
Memory
Indirect AddressingDirect Addressing
Bank Select Location Select
RP1 RP0 6 0
From Opcode IRP File Select Register
70
Bank Select Location Select
00 01 10 11 180h
1FFh
00h
7Fh
Bank 0 Bank 1 B ank 2 Bank 3
PIC16(L)F707
DS41418B-page 30 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 31
PIC16(L)F707
3.0 RESETS
The PIC16(L)F707 differentiates between various
kinds of Re set :
a) Power-on Reset (PO R)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
d) MCLR Reset during normal operation
e) MCLR Reset during Sleep
f) Brown-out Reset (BOR)
Some regi sters a re not af fected in any Rese t condi tion;
their st at us is un kn ow n o n POR a nd un ch ang ed in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Pow er- on Reset (POR)
•MCLR
Reset
•MCLR
Reset du ring Sleep
•WDT Reset
• Brown-out Reset (BOR)
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal
operation. TO a nd PD bi t s are s et or cle are d d ifferentl y
in different Reset situations, as indicated in Table 3-3.
These bi ts are used in software to determine the n ature
of the Reset.
A simplif ied block diagra m of the On-Chip Rese t Circu it
is shown i n Figure 3-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 25.0 “Electrical
Specifications” for pulse width specifications.
FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
MCLR/VPP
VDD
OSC1/
WDT
Module
POR
OST/PWRT
WDTOSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Reset
Enable OST
Enable PWRT
Sleep
Brown-out(1)
Reset BOREN
CLKIN
Note 1: Refer to the Configuration Word Register 1 (Register 8-1).
MCLRE
PIC16(L)F707
DS41418B-page 32 2010-2011 Microchip Technology Inc.
TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE
POR BOR TO PD Condition
0x11Power-on Reset or LDO Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out Reset
1101WD T Reset
1100WD T Wake-up
11uuMCLR Reset during normal operation
1110MCLR Reset during Sleep or interrupt wake-up from Sleep
TABLE 3-2: RESET CONDITION FOR SPECIAL REGISTERS(2)
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 0000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 0000h 000u uuuu ---- --uu
MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu
WDT Reset 0000h 0000 1uuu ---- --uu
WDT Wake- up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 0000h 0001 1uuu ---- --u0
Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note1: When the wake-up is due to an interrupt and global enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
2010-2011 Microchip Technology Inc. DS41418B-page 33
PIC16(L)F707
3.1 MCLR
The PIC16(L)F707 has a noise filter in the MCLR Reset
path. The filter will detect and ignore small pulses.
It should be noted that a Reset does not drive the
MCLR pin low.
Vo lta ges app lied to the pin th at exce ed it s s pecif icatio n
can resu lt in both MCL R Rese t s a nd e xc es sive c urre nt
bey ond t h e de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt .
For this rea son, Microc hip recomme nds that the MC LR
pin no long er be tied direc tl y to VDD. The use of an RC
netw ork, as show n in Figure 3-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RE3/MCLR pin
becomes an external Reset input. In this mode, the
RE3/MCLR pin has a weak pull-up to VDD. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
FIGURE 3-2: RECOMMENDED MCLR
CIRCUIT
3.2 Power-on Reset (POR)
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level fo r proper operation. A
maximum rise time for VDD is required. See
Section 25.0 “Electrical S pecific ations” for det ails. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will ke ep the device in
Reset until VDD reaches VBOR (see Section 3.5
“Brown-Out Reset (BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
3.3 Power-up Timer (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the WDT
oscillator. For more information, see Section 7.3
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
PWRTE, can d isable (if set ) or enabl e (if cleare d or pro-
grammed) the Power-up Timer. The Power-up Timer
should be enabled when Brown-out Reset is enabled,
although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
•V
DD variation
• Temperature variation
• Process variation
See DC parameters for details (Section 25.0
“Electrical Specifications”).
3.4 Watchdog Timer (WDT)
The WDT has the following features:
• Shares an 8-bit prescaler with Timer0
• Time-out period is from 17 ms to 2.2 seconds,
nominal
• Enabl ed by a Conf ig urat ion bit
WDT is cleared under certain conditions described in
Table 3-3.
3.4.1 WDT OSCILLATOR
The WDT derives its time base from 31 kHz internal
oscillator.
VDD PIC® MCU
MCLR
R1
10 k
C1
0.1 F
Note: The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word 1.
Note: When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
PIC16(L)F707
DS41418B-page 34 2010-2011 Microchip Technology Inc.
3.4.2 WDT CONTROL
The WDTE bit is located in the Configuration Word
Register 1. When set, the WDT runs continuously.
The PSA and PS<2:0> bits of the OPTION register
control the WDT period. See Section 12.0 “Timer0
Module” for more information.
FIGURE 3-3: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0
Postscaler
8
PS<2:0>
PSA
TO TMR0
1
10
0
Clock Source
To TxG
Divide by
512
WDTE
TMRxGE
TxGSS = 11
WDTE
WDT Re set
Low-Power
WDT O S C
TABLE 3-3: WDT STATUS
Conditions WDT
WDTE = 0Cleared
CLRWDT Command
Exit Sleep + System Clock = EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
2010-2011 Microchip Technology Inc. DS41418B-page 35
PIC16(L)F707
3.5 Brown-Out Reset ( BOR)
Brown-out Reset is enabled by programming the
BOREN<1:0> bits in the Configuration register. The
brown-out trip point is selectable from two trip points
via the BORV bit in the Confi gura tion r egister.
Between the POR and BOR, complete voltage range
coverage for execution protection can be imple-
mented.
Two bits are used to enable the BOR. When
BOREN = 11, the BOR is always enabled. When
BOREN = 10, the BOR is en abl ed , bu t di sabled durin g
Sleep. When BOREN = 0X, the BOR is disabled.
If VDD falls below VBOR for greater than parameter
(TBOR) (see Section 25.0 “Electrical Specifica-
tions”), the brown-out situation will reset the device.
This will occur regardless of VDD slew rate. A Reset is
not en sure d to occu r if VDD falls below VBOR for more
than para me ter ( TBOR).
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Pow er-up T imer will be re-initial ized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
FIGURE 3-4: BROWN-OUT SITUATIONS
Note: When erasing Flash program memory , the
BOR is forced to enabled at the minimum
BOR setting to ensure that any code
protection circuitry is operating properly.
64 ms(1)
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset 64 ms(1)
< 64 ms
64 ms(1)
VBOR
VDD
Internal
Reset
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
PIC16(L)F707
DS41418B-page 36 2010-2011 Microchip Technology Inc.
3.6 Time-out Sequence
On power- up, the t ime-out sequ ence is a s follows: first,
PWR T time-out is invoked after PO R has ex pired, the n
OST is act iv ated af te r the PWRT time-ou t has exp ire d.
The tot a l time -ou t wil l vary bas ed on os ci llator configu-
ration and PWRTE bit stat us. For exampl e, in EC mode
with PWRTE bit = 1 (PWRT disabled), there will be no
time-out at all. Figure 3-5, Figure 3-6 and Figure 3-7
depict tim e-o ut sequ en ces .
Since the time-outs oc cur from the PO R pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 3-6). This i s usefu l for te sting purpos es or
to synchronize more than one PIC16(L)F707 device
operating in parallel.
Table 3-2 shows the Reset conditions for some special
registers.
3.7 Power Control (PCON) Register
The Power Contro l (PCON) register has two S t atus bits
to indicate what type of Reset that last occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaf fec ted oth erwise. T he user m ust write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more information, see Section 3.5 “Brown-Out
Reset (BOR)”.
FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
TABLE 3-4: TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration Power-up Brown-out Reset Wake-up from
Sleep
PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1
XT, HS, LP TPWRT + 1024 •
TOSC 1024 • TOSC TPWRT + 1 024 •
TOSC 1024 • TOSC 1024 • TOSC
RC, EC, INTOSC TPWRT —TPWRT ——
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT T ime-out
OST Time-out
Internal Reset
2010-2011 Microchip Technology Inc. DS41418B-page 37
PIC16(L)F707
FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
FIGURE 3-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
PIC16(L)F707
DS41418B-page 38 2010-2011 Microchip Technology Inc.
TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS
Register Address Power-on Reset/
Brown-out Reset(1) MCLR Reset/
WDT Reset W ake-up from Slee p through
Interrupt/Time-out
W—xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h/
100h/180h xxxx xxxx xxxx xxxx uuuu uuuu
TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h/
102h/182h 0000 0000 0000 0000 PC + 1(3)
STATUS 03h/83h/
103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4)
FSR 04h/84h/
104h/184h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h xxxx xxxx xxxx xxxx uuuu uuuu
PORTB 06h xxxx xxxx xxxx xxxx uuuu uuuu
PORTC 07h xxxx xxxx xxxx xxxx uuuu uuuu
PORTD 08h xxxx xxxx xxxx xxxx uuuu uuuu
PORTE 09h ---- xxxx ---- xxxx ---- uuuu
PCLATH 0Ah/8Ah/
10Ah/18Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh/
10Bh/18Bh 0000 000x 0000 000x uuuu uuuu(2)
PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2)
PIR2 0Dh 0000 ---0 0000 ---0 uuuu ---u(2)
TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 10h 0000 00-0 uuuu uu-u uuuu uu-u
TMR2 11h 0000 0000 0000 0000 uuuu uuuu
T2CON 12h -000 0000 -000 0000 -uuu uuuu
SSPBUF 13h xxxx xxxx xxxx xxxx uuuu uuuu
SSPCON 14h 0000 0000 0000 0000 uuuu uuuu
CCPR1L 15h xxxx xxxx xxxx xxxx uuuu uuuu
CCPR1H 16h xxxx xxxx xxxx xxxx uuuu uuuu
CCP1CON 17h --00 0000 --00 0000 --uu uuuu
RCSTA 18h 0000 000x 0000 000x uuuu uuuu
TXREG 19h 0000 0000 0000 0000 uuuu uuuu
RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu
CCPR2L 1Bh xxxx xxxx xxxx xxxx uuuu uuuu
CCPR2H 1Ch xxxx xxxx xxxx xxxx uuuu uuuu
CCP2CON 1Dh --00 0000 --00 0000 --uu uuuu
ADRES 1Eh xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes to o low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 3-2 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Rese ts will caus e bit 0 = u.
2010-2011 Microchip Technology Inc. DS41418B-page 39
PIC16(L)F707
ADCON0 1Fh --00 0000 --00 0000 --uu uuuu
OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h 1111 1111 1111 1111 uuuu uuuu
TRISB 86h 1111 1111 1111 1111 uuuu uuuu
TRISC 87h 1111 1111 1111 1111 uuuu uuuu
TRISD 88h 1111 1111 1111 1111 uuuu uuuu
TRISE 89h ---- 1111 ---- 1111 ---- uuuu
PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu
PIE2 8Dh 0000 ---0 0000 ---0 uuuu ---u
PCON 8Eh ---- --qq ---- --uu(1,5) ---- --uu
T1GCON 8Fh 0000 0x00 uuuu uxuu uuuu uxuu
OSCCON 90h --10 qq-- --10 qq-- --uu qq--
OSCTUNE 91h --00 0000 --uu uuuu --uu uuuu
PR2 92h 1111 1111 1111 1111 uuuu uuuu
SSPADD 93h 0000 0000 0000 0000 uuuu uuuu
SSPMSK 93h 1111 1111 1111 1111 uuuu uuuu
SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu
WPUB 95h 1111 1111 1111 1111 uuuu uuuu
IOCB 96h 0000 0000 0000 0000 uuuu uuuu
T3CON 97h 0000 -0-0 0000 -0-0 uuuu -u-u
TXSTA 98h 0000 -010 0000 -010 uuuu -uuu
SPBRG 99h 0000 0000 0000 0000 uuuu uuuu
TMR3L 9Ah xxxx xxxx uuuu uuuu uuuu uuuu
TMR3H 9Bh xxxx xxxx uuuu uuuu uuuu uuuu
APFCON 9Ch ---- --00 ---- --00 ---- --uu
FVRCON 9Dh q000 0000 q000 0000 q000 0000
ADCON1 9Fh -000 --00 -000 --00 -uuu --uu
TACON 105h 0-00 0000 0-00 0000 u-uu uuuu
CPSBCON0 106h 00-- 0000 00-- 0000 uu-- uuuu
CPSBCON1 107h ---- 0000 ---- 0000 ---- uuuu
CPSACON0 108h 00-- 0000 00-- 0000 uu-- uuuu
CPSACON1 109h ---- 0000 ---- 0000 ---- uuuu
PMDATL 10Ch xxxx xxxx xxxx xxxx uuuu uuuu
PMADRL 10Dh xxxx xxxx xxxx xxxx uuuu uuuu
PMDATH 10Eh --xx xxxx --xx xxxx --uu uuuu
PMADRH 10Fh ---x xxxx ---x xxxx ---u uuuu
TMRA 110h 0000 0000 0000 0000 uuuu uuuu
TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register Address Power-on Reset/
Brown-out Reset(1) MCLR Reset/
WDT Reset W ake-up from Slee p through
Interrupt/Time-out
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and regist ers will be affec ted differently.
2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 3-2 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Rese ts will caus e bit 0 = u.
PIC16(L)F707
DS41418B-page 40 2010-2011 Microchip Technology Inc.
TBCON 111h 0-00 0000 0-00 0000 u-uu uuuu
TMRB 112h 0000 0000 0000 0000 uuuu uuuu
DACCON0 113h 000- 00-- 000- 00-- uuu- uu--
DACCON1 114h ---0 0000 ---0 0000 ---u uuuu
ANSELA 185h 1111 1111 1111 1111 uuuu uuuu
ANSELB 186h 1111 1111 1111 1111 uuuu uuuu
ANSELC 187h 1111 1111 1111 1111 uuuu uuuu
ANSELD 188h 1111 1111 1111 1111 uuuu uuuu
ANSELE 189h ---- -111 ---- -111 ---- -uuu
PMCON1 18Ch 1--- ---0 1--- ---0 u--- ---u
TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS (C ONTINUED)
Register Address Power-on Reset/
Brown-out Reset(1) MCLR Reset/
WDT Reset W ake-up from Slee p through
Interrupt/Time-out
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes to o low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 3-2 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Rese ts will caus e bit 0 = u.
TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets(1)
STATUS IRP RP1 RP0 TO PD ZDC C0001 1xxx 000q quuu
PCON — — — — — —PORBOR ---- --qq ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are
not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2010-2011 Microchip Technology Inc. DS41418B-page 41
PIC16(L)F707
4.0 INTERRUPTS
The PIC16(L)F707 device family features an
interruptible core, allowing certain events to preempt
normal program flow. An Interrupt Service Routine
(ISR) is used to determine the source of the interrupt
and act ac cordingly. Some int errupts can be co nfigured
to wake the MCU from Sleep mode.
The PIC16F707 family has 16 interrupt sources,
differentiated by corresponding interrupt enable and
flag bits:
• Timer0 Overflow Interrupt
• External Edge Detect on INT Pin Interrupt
• PORTB Change Interrupt
• Timer1 Gate Interrupt
• A/D Conversion Complete Inte rrup t
• AUSART Receive Interrupt
• AUSART Transmit Interrupt
• SSP Event Interrupt
• CCP1 Event Interrupt
• Timer2 Match with PR2 Interrupt
• Timer1 Overflow Interrupt
• CCP2 Event Interrupt
• TimerA Overflow Interrupt
• TimerB Overflow Interrupt
• Timer3 Overflow Interrupt
• Timer3 Gate Interrupt
A block diagram of the interrupt logic is shown in
Figure 4-1.
FIGURE 4-1: INTERRUPT LOGIC
TMR0IF
TMR0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in Sleep mode)(1)
Inter rupt to CPU
TMR1GIE
TMR1GIF
ADIF
ADIE
IOC-RB0
IOCB0
IOC-RB1
IOCB1
IOC-RB2
IOCB2
IOC-RB3
IOCB3
CCP1IF
CCP1IE
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
RCIF
RCIE
TMR2IE
TMR2IF
SSPIE
SSPIF
TXIE
TXIF
TMR1IE
TMR1IF
Note 1: Some peripherals depend upon the
system clock for operation. Since the
system clock is suspended during
Sleep, these peripherals will not wake
the part from Sleep. See Section 21.1
“Wake-up from Sleep”.
CCP2IF
CCP2IE
TMRAIF
TMRAIE
TMR3IF
TMR3IE
TMR3GIF
TMR3GIE
TMRBIF
TMRBIE
PIC16(L)F707
DS41418B-page 42 2010-2011 Microchip Technology Inc.
4.1 Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the interrupt
enable b it of the i nterrupt eve nt is cont ained in the
PIE1 and PIE2 registers)
The INTCON, PIR1 and PIR2 registers record individ-
ual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual Interrupt Enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Coun ter (PC) is pushed onto the
stack
• PC is loaded with the interrupt vector 0004h
The ISR determines the source of the interrupt by
polling the interrupt flag bits. The interrupt flag bits must
be cleared before exiting the ISR to avoid repeated
interrupt s. Becaus e the GIE b it is cleared, an y in terrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack and setti ng the GIE bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
4.2 Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code e xecut ion at the
interrupt vector begins. The latency for synchronous
interrupts is 3 instruction cycles. For asynchronous
interrupts, the latency is 3 to 4 instruction cycles,
depending on when the interrupt occurs. See Figure 4-2
for timing details.
FIGURE 4-2: INT PIN INTERRUPT TIMING
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All inte rrupts wi ll be ignore d while the G IE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h) Inst (0005h)
Dummy Cycl e
Inst (PC) Inst (PC + 1)
Inst (PC – 1) Inst (0004h)
Dummy Cycl e
Inst ( PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 25.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1) (2)
(3) (4)
(5)
(1)
2010-2011 Microchip Technology Inc. DS41418B-page 43
PIC16(L)F707
4.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate with out t he system clock. The inter rupt source
must have the appropriate interrupt enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
process or will bran ch to the inte rrupt vector . O therwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 21.0 “Power-
Down Mode (Sleep)” for more details.
4.4 INT Pin
The external interrupt, INT pin, causes an
asynchronous, edge-triggered interrupt. The INTEDG bit
of the OPTION register determines on which edge the
interrupt will occur. When the INTEDG bit is set, the
rising edge will cause the interrupt. When the INTEDG
bit is clear, the falling edge will cause the interrupt. The
INTF bit of the INTCON register will be set when a valid
edge appears on the INT pin. If the GI E and INTE bits
are also set, the processor will redirect program
execution to the interrupt vector. This interrupt is
disabled by clearing the INTE bit of the INTCON register .
4.5 Context Saving
When an interrupt occurs, only the return PC value is
saved to the stack. If the ISR modifies or uses an
instruction that modifies key registers, their values
must be s aved at the begi nning of the ISR and res tored
when the ISR completes. This prevents instructions
following the ISR from using invalid data. Examples of
key registers include the W, STATUS, FSR and
PCLATH registers.
The code shown in Example 4-1 can be used to do the
following.
• Save the W register
• Save the STATUS register
• Save the PCLATH regist er
• Execute the ISR program
• Restore the PCLATH register
• Restore the STAT US register
• Restore the W register
Since most instructions modify the W register, it must
be saved immediately upon entering the ISR. The
SWAPF instruction is used when saving and restoring
the W and STATUS registers because it will not affect
any bits in the STATUS register. It is useful to place
W_TEMP in shared memory because the ISR cannot
predict which bank will be selected when the interrupt
occurs.
The processor will branch to the interrupt vector by
loading the PC with 0004h. The PCLATH register will
remain unchanged. This requires the ISR to ensure
that the PCLATH register is set properly before using
an instruction that causes PCLATH to be loaded into
the PC. See Section 2.3 “PCL and PCLATH” for
details on PC operation.
EXAMPLE 4-1: SAVING W, STATUS AND PCLATH REGISTERS IN RAM
Note: The microcontroller does not normally
require saving the PCLATH register.
However, if computed GOTO’s are used,
the PCLATH registe r must be saved at the
beginning of the ISR and restored when
the ISR is complete to ensure correct
program flow.
MOVWF W_TEMP ;Copy W to W_TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
BANKSEL STATUS_TEMP ;Select regardless of current bank
MOVWF STATUS_TEMP ;Copy status to bank zero STATUS_TEMP register
MOVF PCLATH,W ;Copy PCLATH to W register
MOVWF PCLATH_TEMP ;Copy W register to PCLATH_TEMP
:
:(ISR) ;Insert user code here
:
BANKSEL STATUS_TEMP ;Select regardless of current bank
MOVF PCLATH_TEMP,W ;
MOVWF PCLATH ;Restore PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
PIC16(L)F707
DS41418B-page 44 2010-2011 Microchip Technology Inc.
4.5.1 INTCON REGISTER
The INTCON register is a readable and writable
register, which c ontains the various enable and flag bit s
for TMR0 register overflow, PORTB change and
external RB0/INT/SEG0 pin interrupts.
Note: Interru pt flag bit s are set when an interr upt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User sof tware sh ould ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 4-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE TMR0IE INTE RBIE(1) TMR0IF(2) INTF RBIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: PORTB Change Interrupt Enable bit(1)
1 = Enables the PORTB change interrupt
0 = Disables the PORTB change interrupt
bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = TM R0 register has overflowed (must be cleare d in so ftwa re)
0 = TM R0 register did no t overfl ow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: PORTB Change Interrupt Flag bit
1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in
software)
0 = None of the PORTB general purpose I/O pins have changed state
Note 1: The appropriate bits in the IOCB register must also be set.
2: TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing TMR0IF bit.
2010-2011 Microchip Technology Inc. DS41418B-page 45
PIC16(L)F707
4.5.2 PIE1 REGIST ER
The PIE1 regis te r con t ai ns th e in terrupt enable bi t s, a s
shown in Register 4-2.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 4-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enable the Timer1 gate acquisition complete interrupt
0 = Disable the Timer1 gate acquisition complete interrupt
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
PIC16(L)F707
DS41418B-page 46 2010-2011 Microchip Technology Inc.
4.5.3 PIE2 REGISTER
The PIE2 regis te r con t ai ns th e in terrupt enable bi t s, a s
shown in Register 4-3.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 4-3: PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other
Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 TMR3GIE: Tim er3 Ga te Inter rupt Fla g bit
1 = Enable the Timer3 gate acquisition complete interrupt
0 = Disable the Timer3 gate acquisition complete interrupt
bit 6 TMR3IE: Timer3 Overflow Interrupt Enable bit
1 = Enables the Timer3 overflow interrupt
0 = Disables the Timer3 overfl ow interrupt
bit 5 TMRBIE: TimerB Overfl ow Interrupt Enable bit
1 = Enables the TimerB interrupt
0 = Disables the TimerB interrupt
bit 4 TMRAIE: TimerA Overfl ow Interrupt Enable bit
1 = Enables the TimerA interrupt
0 = Disables the TimerA interrupt
bit 3-1 Unimplemented: Read as '0'
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
2010-2011 Microchip Technology Inc. DS41418B-page 47
PIC16(L)F707
4.5.4 PIR1 REGISTER
The PIR1 register contains the interrupt flag bits, as
shown in Register 4-4.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 4-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Timer1 gate is inactive
0 = Timer1 gate is active
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is not full
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A Timer1 register capture occurred (must be cleared in software)
0 = No Timer1 register capture occurred
Compare mode:
1 = A Timer1 register compare match occurred (must be cleared in software)
0 = No Timer1 register compare matc h occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The Timer1 register overflowed (must be cleared in software)
0 = The Timer1 register did not overflow
PIC16(L)F707
DS41418B-page 48 2010-2011 Microchip Technology Inc.
4.5.5 PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 4-5.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 4-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR3GIF: Timer3 Gate Interrupt Flag bit
1 = Timer3 gate is inactive
0 = Timer3 gate is active
bit 6 TMR3IF: Timer3 Overflow Interrupt Flag bit
1 = Timer3 register overflowed (must be cleared in software)
0 = Timer3 register did not overflow
bit 5 TMRBIF: TimerB Overflow Interrupt Flag bit
1 = TimerB register has overflowed (must be cleared in software)
0 = TimerB register did not overflow
bit 4 TMRAIF: TimerA Overflow Interrupt Flag bit
1 = TimerA register has overflowed (must be cleared in software)
0 = TimerA register did not overflow
bit 3-1 Unimplemented: Read as ‘0’
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A Timer1 register capture occurred (must be cleared in software)
0 = No Timer1 register capture occurred
Compare Mode
1 = A Timer1 register compare match occurred (must be cleared in software)
0 = No Time r1 register compare match occurred
PWM Mode
Unused in this mode
2010-2011 Microchip Technology Inc. DS41418B-page 49
PIC16(L)F707
TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
OPTION_REG RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE 0000 ---0 0000 ---0
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF 0000 ---0 0000 ---0
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by interrupts.
PIC16(L)F707
DS41418B-page 50 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 51
PIC16(L)F707
5.0 LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC16F707 device has an internal Low Dropout
Regul ator (LDO ) which provi des op eration abov e 3.6V.
The LDO regulates a voltage for the internal device
logic while permitting the VDD and I/O pins to operate
at a higher voltage. There is no user enable/disable
control available for the LDO, it is always active. The
PIC16LF707 operates at a maximum VDD of 3.6V and
does not incorporate an LDO.
A device I/O pin may be configu red as the LD O volt age
output, identified as the VCAP pin. Although not
required, an external low-ESR capacitor may be
connected to the VCAP pin for additional regulator
stability.
The VCAPEN<1:0> bits of Configuration Word 2
determines which pin is assigned as the VCAP pin.
Refer to Table 5-1.
On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
device is h eld in R es et whi le a con st a nt c urre nt source
charges the external capacitor. After the cap is fully
char ged, the device i s releas ed from Re set. For mor e
informat ion on rec om me nde d c ap a ci tor v al ues an d th e
constant current rate, refer to the LDO Regulator
Characteristics Table in Section 25.0 “Electrical
Specifications”.
TABLE 5-2: SUMMARY OF CONFIGURATION WORD WITH LDO
TABLE 5-1: VCAPEN<1:0> SELECT BITS
VCAPEN<1:0> Pin
00 RA0
01 RA5
10 RA6
11 No VCAP
Name Bits Bit -/7 Bit -/6 B it 13/5 Bit 12/4 Bit 11/3 Bit 10/2 B it 9/1 B it 8/0 Register
on Page
CONFIG2 13:8 — — — — — — — — 78
7:0 — — VCAPEN1(1) VCAPEN0(1) ————
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.
Note 1: PIC16F707 only.
PIC16(L)F707
DS41418B-page 52 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 53
PIC16(L)F707
6.0 I/O PORTS
There are thirty-five ge neral purpose I/O pins ava ilable.
Depending on which peripherals are enabled, some or
all of the pins m ay n ot b e a va ilable as g ene ral purpose
I/O. In general, when a peripheral is enabled, the
associated pin may not be used as a general purpose
I/O pin.
Each port has two registers for its operation. These
registers are:
• TRISx registers (data direction register)
• PORTx registers (port read/write register)
Ports with analog functions also have an ANSELx
register which can disable the digital input and save
power. A simplifi ed mo del of a gen eri c I /O po rt, w i tho ut
the interfaces to other peripherals, is shown in
Figure 6-1.
FIGURE 6-1: GENERIC I/O PORT
OPERATION
6.1 Alternate Pin Funct ion
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between dif ferent pins. The APFCON reg ister
is shown in Register 6-1. For this device family, the
following functions can be moved between different
pins.
•SS
(Slave Select)
• CCP2
QD
CK
Data Register
I/O pin
Read PORTx
Write PORTx
TRISx
Data Bus
To peripherals
ANSELx
VDD
VSS
REGISTER 6-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SSSEL CCP2SEL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0’.
bit 1 SSSEL: SS Input Pin Selection bit
0 =SS
function is on RA5/AN4/CPS7/SS/VCAP
1 =SS function is on RA0/AN0/SS/VCAP
bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit
0 = CCP2 function is on RC1/T1OSI/CCP2
1 = CCP2 function is on RB3/CCP2
PIC16(L)F707
DS41418B-page 54 2010-2011 Microchip Technology Inc.
6.2 PORTA and TRISA Registers
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 6-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a T RISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 6-1 shows how to
initialize PORTA.
Reading the PORTA register (Register 6-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the POR T dat a latc h.
The TRISA register (Register 6-3) controls the PORTA
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISA register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
EXAMPLE 6-1: INITIALIZING PORTA
Note: The ANSELA register must be initialized
to config ure an analog channel as a digit al
input. Pins configured as analog inputs
will read ‘0’.
BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW 0Ch ;Set RA<3:2> as inputs
MOVWF TRISA ;and set RA<7:4,1:0>
;as outputs
REGISTER 6-2: PORTA: PORTA REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RA<7:0>: PORTA I/O Pin bits
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 6-3: TRISA: PORTA TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISA<7:0>: PORTA Tri-St ate Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
2010-2011 Microchip Technology Inc. DS41418B-page 55
PIC16(L)F707
6.2.1 ANSELA REGISTER
The ANSELA register (Register 6-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affec ted port.
6.2.2 PIN DESCRIPTIONS
Each PORT A pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the A/D Converter (ADC), refer to the
appropriate section in this dat a s heet.
6.2.2.1 RA0/AN0/VCAP
The RA0 pin is configurable to function as one of the
following:
• General purpose I/O
• Analog input for the A/D
• Slave Select input for the SSP(1)
• Voltage Regulator Capacitor pin (PIC16F707
only)
6.2.2.2 RA1/AN1/CPSA0
The RA1 pin is configurable to function as one of the
following:
• General purpose I/O
• Analog input for the A/D
• Capacitive sensing input
6.2.2.3 RA2/AN2/CPSA1/DACOUT
The RA2 pin is configurable to function as one of the
following:
• General purpose I/O
• Analog input for the A/D
• Capacitive sensing input
• DAC Output
REGISTER 6-4: ANSELA: PORTA ANALOG SELECT REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit ‘0’ = Bit is cleared
-n = Value at POR ‘1’ = Bit is set x = Bit is unknown
bit 7-0 ANSA<7:0>: Analog Select between Analog or Digital Function on pins RA<7:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Note 1: SS pin location may be selected as RA5
or RA0.
PIC16(L)F707
DS41418B-page 56 2010-2011 Microchip Technology Inc.
6.2.2.4 RA3/AN3/VREF+/CPSA2
The RA3 pin is configurable to function as one of the
following:
• General purpose I/O
• Analog input for the A/D
• Voltage Reference input for the A/D
• Capacitive sensing input
6.2.2.5 RA4/CPSA3/T0CKI/TACKI
The RA4 pin is configurable to function as one of the
following:
• General purpose I/O
• Capacitive sensing input
• Clock input for Timer0
• Clock input for TimerA
The Timer0 clock input function works independently
of any TRIS register setting. Effectively, if TRISA4 = 0,
the PORTA4 register bit will output to the pad and
clock Timer 0 at the same time.
6.2.2.6 RA5/AN4/CPSA4/SS/VCAP
The RA5 pin is configurable to function as one of the
following:
• General purpose I/O
• Capacitive sensing input
• Analog input for the A/D
• Slave Select input for the SSP(1)
•Voltage Regulator Capacitor pin (PIC16F707
only)
6.2.2.7 RA6/CPSB1/OSC2/CLKOUT/VCAP
The RA6 pin is configurable to function as one of the
following:
• General purpose I/O
• Crystal/resonator connection
• Clock Output
• Voltage Regulator Capacitor pin (PIC16F707
only)
• Capacitive sensing input
6.2.2.8 RA7/CPSB0/OSC1/CLKIN
The RA7 pin is configurable to function as one of the
following:
• General purpose I/O
• Crystal/resonator connection
• Clock Input
• Capacitive sensing input.
Note 1: SS pin location may be selected as RA5
or RA0.
TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all ot her
Resets
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000
ADCON1 —ADCS2 ADCS1 ADCS0 —— ADREF1 ADREF0 -000 --00 -000 --00
ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111
APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00
CPSACON0 CPSAON CPSARM —— CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000
CPSACON1 — — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000
CPSBCON0 CPSBON CPSBRM —— CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000
CPSBCON1 — — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000
CONFIG2(1) — — VCAPEN1 VCAPEN0 — — — — ——
OPTION_REG RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx xxxx xxxx
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
TACON TMRAON — TACS TASE TAPSA TAPS2 TAPS1 TAPS0 0-00 0000 0-00 0000
DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — — 000- 00-- 000- 00--
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: PIC16 F7 07 only.
2010-2011 Microchip Technology Inc. DS41418B-page 57
PIC16(L)F707
6.3 PORTB and TRISB Registers
PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 6-6). Setting a TRISB bit (=1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Imped ance mode).
Clea ring a TRI SB bi t (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-2 shows how to ini tia liz e PO R TB.
Reading the PORTB register (Register 6-5) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, th is value is modifi ed and the n written
to the PORT dat a lat ch.
The TRISB register (Register 6-6) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’. Example 6-2 shows how to initialize PORTB.
EXAMPLE 6-2: INITIALIZING PORTB
6.3. 1 ANSELB REGISTER
The ANSELB register (Register 6-9) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no affect on digital
output functions. A pin with TRIS clear and ANSELB
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior when executing read-modify-write
inst ruct ion s on the af f ected port.
6.3.2 WEAK PULL-UPS
Each of the PORTB pi ns has an ind ividually co nfigurable
internal weak pull-up. Control bit s WPUB<7:0> enable or
disable ea ch pu ll-up (see Register 6-7). Each weak pull-
up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the RBPU bit of the OPTION register .
6.3.3 INTERRUPT-ON-CHANGE
All of the PORTB pins are individually configurable as an
interrupt-on-change pin. Control bits IOCB<7:0> enable
or disable the interrupt function for each pin. Refer to
Register 6-8. The interrupt-on-change feature is
disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the present value
is compared with the old va lue l atch ed on the last rea d
of PORTB to determine which bits have changed or
mismatched the old value. The ‘mismatch’ outputs of
the last read are OR’d together to set the PORTB
Change Interrupt Flag bit (RBIF) in the INTCON
register.
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the inte rrupt by:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear the flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading or writing PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After these Resets, the RBIF flag will
continue to be set if a mismatch is present.
Note: The ANSELB register must be initialized
to conf igure an analo g channel as a di gital
input. Pins configured as analog inputs
will read ‘0’.
BANKSEL PORTB ;
CLRF PORTB ;Init PORTB
BANKSEL ANSELB
CLRF ANSELB ;Make RB<7:0> digital
BANKSEL TRISB ;
MOVLW B’11110000’;Set RB<7:4> as inputs
;and RB<3:0> as outputs
MOVWF TRISB ;
Note: When a pin change occurs at the same
time as a read operation on PORTB, the
RBIF flag will always be set. If multiple
PORTB pins are configured for the
interrupt-on-change, the user may not be
able to identify which pin changed state.
PIC16(L)F707
DS41418B-page 58 2010-2011 Microchip Technology Inc.
REGISTER 6-5: PORTB: PORTB REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RB<7:0>: PORTB I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 6-6: TRISB: PORTB TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
REGISTER 6-7: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 WPUB<7:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
2010-2011 Microchip Technology Inc. DS41418B-page 59
PIC16(L)F707
6.3.4 PIN DESCRIPTIONS
Each PORTB pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I2C or interrupts, refer to the appropriate
section in this data sheet.
6.3.4.1 RB0/AN12/CPSB8/INT
These pins are configurable to function as one of the
following:
• General purpose I/O
• Analog input for the ADC
• Capacitive sensing input
• External edge triggered interrupt
6.3.4.2 RB1/AN10/CPSB9
These pins are configurable to function as one of the
following:
• General purpose I/O
• Analog input for the ADC
• Capacitive sensing input
6.3.4.3 RB2/AN8/CPSB10
These pins are configurable to function as one of the
following:
• General purpose I/O
• Analog input for the ADC
• Capacitive sensing input
REGISTER 6-8: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
REGISTER 6-9: ANSELB: PORTB ANALOG SELECT REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ANSB<7:0>: Analog Select between Analog or Digital Function on Pins RB<7:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
PIC16(L)F707
DS41418B-page 60 2010-2011 Microchip Technology Inc.
6.3.4.4 RB3/AN9/CPSB11/CCP2
These pins are configurable to function as one of the
following:
• General purpose I/O
• Analog input for the ADC
• Capac iti ve se ns ing in put
• Capture 2 input, Compare 2 output, and PWM2
output
6.3.4.5 RB4/AN11/CPSB12
These pins are configurable to function as one of the
following:
• General purpose I/O
• Analog input for the ADC
• Capac iti ve se ns ing in put
6.3.4.6 RB5/AN13/CPSB13/T1G/T3CKI
These pins are configurable to function as one of the
following:
• General purpose I/O
• Analog input for the ADC
• Capacitive sensing input
• Timer1 gate input
• Timer3 clock input
6.3.4.7 RB6/ICSPCLK/CPSB14
These pins are configurable to function as one of the
following:
• General purpose I/O
• In-Circuit Serial Programming clock
• Capacitive sensing input
6.3.4.8 RB7/ICSPDAT/CPSB15
These pins are configurable to function as one of the
following:
• General purpose I/O
• In-Circuit Serial Progr amming data
• Capacitive sensing input
Note: CCP2 pin location may be selected as
RB3 or RC1.
TABLE 6-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
V alue on all
other
Resets
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000
ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111
APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
CPSBCON0 CPSBON CPSBRM —— CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000
CPSBCON1 ———— CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000X
IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000
OPTION_REG RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx
T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 — T3SYNC —TMR3ON0000 -0-0 0000 -0-0
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
2010-2011 Microchip Technology Inc. DS41418B-page 61
PIC16(L)F707
6.4 PORTC and TRISC Registers
PORTC is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISC
(Register 6-11). Setting a TRISC bit (= 1) will ma ke the
corresponding PORTC pin an input (i.e., put the
corr esponding o utput dr iver in a Hi gh-Impeda nce mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pi n an outp ut ( i.e. , enab le th e out put dri ver and
put th e co nte nts of t he ou tp ut l atc h on t h e se le cted pi n) .
Example 6-3 shows how to initialize PORTC.
Reading the PORTC register (Register 6-10) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pin s are read, thi s value is modi fied and the n written
to the PORT data latch.
The TRISC register (Register 6-11) cont r ol s th e PO RTC
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISC register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘ 0’.
EXAMPLE 6-3: INITIALIZING PORTC
The location of the CCP2 function is controlled by the
CCP2SEL bit in the APFCON register (see Register 6-1).
BANKSEL PORTC ;
CLRF PORTC ;Init PORTC
BANKSEL TRISC ;
MOVLW B‘00001100’ ;Set RC<3:2> as inputs
MOVWF TRISC ;and set RC<7:4,1:0>
;as outputs
REGISTER 6-10: PORTC: PORTC REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 6-11: TRISC: PORTC TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
PIC16(L)F707
DS41418B-page 62 2010-2011 Microchip Technology Inc.
6.4.1 ANSELC REGISTER
The ANSELC register (Register 6-12) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELC bits has no affect on digital
output functions. A pin with TRIS clear and ANSELC
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior when executing read-modify-write instruc-
tions on the affected port.
6.4.2 PIN DESCRIPTIONS
Each PORTC pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I2C or interrupts, refer to the appropriate
section in this data sheet.
6.4.2.1 RC0/T1OSO/T1CKI/CPSB2
These pins are configurable to function as one of the
following:
• General purpose I/O
• Timer1 oscillator output
• Timer1 cl ock input
• Capacitive sensing input
6.4.2.2 RC1/T1OSI/CCP2/CPSB3
These pins are configurable to function as one of the
following:
• General purpose I/O
• Timer1 oscillator input
• Capture 2 input, Compare 2 output, and PWM2
output
• Capacitive sensing input
Note: The ANSELC register must be initialized
to conf igure an analo g channel as a di gital
input. Pins configured as analog inputs
will read ‘0’.
REGISTER 6-12: ANSELC: PORTC ANALOG SELECT REGISTER
R/W-1 R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1
ANSC7 ANSC6 ANSC5 —— ANSC2 ANSC1 ANSC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 ANSC<7:5>: Analog Select between Analog or Digital Function on Pins RC<7:5>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 ANSC<2:0>: Analog Select between Analog or Digital Function on Pins RC<2:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Note: CCP2 pin location may be selected as
RB3 or RC1.
2010-2011 Microchip Technology Inc. DS41418B-page 63
PIC16(L)F707
6.4.2.3 RC2/CCP1/CPSB4/TBCKI
These pins are configurable to function as one of the
following:
• General purpose I/O
• Capture 1 input, Compare 1 output, and PWM1
output
• Capacitive sensing input
• TimerB Clock input
6.4.2.4 RC3/SCK/SCL
These pins are configurable to function as one of the
following:
• General purpose I/O
• SPI clock
•I
2C™ clock
6.4.2.5 RC4/SDI/SDA
These pins are configurable to function as one of the
following:
• General purpose I/O
• SPI data inpu t
•I
2C data I/O
6.4.2.6 RC5/SDO/CPSA9
These pins are configurable to function as one of the
following:
• General purpose I/O
• SPI data outpu t
• Capacitive sensing input
6.4.2.7 RC6/TX/CK/CPSA10
These pins are configurable to function as one of the
following:
• General purpose I/O
• Asynchronous serial output
• Synchronous cl ock I/O
• Capacitive sensing input
6.4.2.8 RC7/RX/DT/CPSA11
These pins are configurable to function as one of the
following:
• General purpose I/O
• Asynchronous serial input
• Synchronous serial data I/O
• Capacitive sensing input
TABLE 6-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
V alu e on a ll
other
Resets
ANSELC ANSC7 ANSC6 ANSC5 —— ANSC2 ANSC1 ANSC0 111- -111 111- -111
APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00
CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
CPSACON0 CPSAON CPSARM —— CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000
CPSACON1 — — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000
CPSBCON0 CPSBON CPSBRM —— CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000
CPSBCON1 — — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON 0000 00-0 uuuu uu-u
TBCON TMRBON — TBCS TBSE TBPSA TBPS2 TBPS1 TBPS0 0-00 0000 0-00 0000
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
PIC16(L)F707
DS41418B-page 64 2010-2011 Microchip Technology Inc.
6.5 PORTD and TRISD Registers
PORTD is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISD
(Register 6-14). Setting a TRISD bit (= 1) will make the
corresponding PORTD pin an input (i.e., put the
corr esponding o utput dr iver in a Hi gh-Impeda nce mode).
Clearing a TRISD bit (= 0) will make the corresponding
PORTD pi n an outp ut ( i.e. , enab le th e out put dri ver and
put th e co nte nts of t he ou tp ut l atc h on t h e se le cted pi n) .
Example 6-4 shows how to initialize PORTD.
Reading the PORTD register (Register 6-13) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
The TRISD register (Register 6-14) controls the
PORTD pin output drivers, even when they are being
used as analo g inpu ts. The us er shou ld ens ure the bit s
in the TRISD register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
EXAMPLE 6-4: INITIALIZING PORTD
6.5.1 ANSELD REGISTER
The ANSELD register (Register 6-15) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELD bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELD bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note: The ANSELD register must be initialized
to config ure an analog channel as a digit al
input. Pins configured as analog inputs
will read ‘0’.
BANKSEL PORTD ;
CLRF PORTD ;Init PORTD
BANKSEL ANSELD
CLRF ANSELD ;Make PORTD digital
BANKSEL TRISD ;
MOVLW B‘00001100’ ;Set RD<3:2> as inputs
MOVWF TRISD ;and set RD<7:4,1:0>
;as outputs
REGISTER 6-13: PORTD: PORTD REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bits
1 = Port pin is > VIH
0 = Port pin is < VIL
2010-2011 Microchip Technology Inc. DS41418B-page 65
PIC16(L)F707
6.5.2 PIN DESCRIPTIONS
Each PORTD pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I2C or interrupts, refer to the appropriate
section in this data sheet.
6.5.2.1 RD0/CPSB5/T3G
These pins are configurable to function as one of the
following:
• General purpose I/O
• Capacitive sensing input
• Timer3 Gate input
6.5.2.2 RD1/CPSB6
These pins are configurable to function as one of the
following:
• General purpose I/O
• Capacitive sensing input
6.5.2.3 RD2/CPSB7
These pins are configurable to function as one of the
following:
• General purpose I/O
• Capacitive sensing input
6.5.2.4 RD3/CPSA8
These pins are configurable to function as one of the
following:
• General purpose I/O
• Capacitive sensing input
6.5.2.5 RD4/CPSA12
These pins are configurable to function as one of the
following:
• General purpose I/O
• Capacitive sensing input
REGISTER 6-14: TRISD: PORTD TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits
1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output
REGISTER 6-15: ANSELD: PORTD ANALOG SELECT REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
PIC16(L)F707
DS41418B-page 66 2010-2011 Microchip Technology Inc.
6.5.2.6 RD5/CPSA13
These pins are configurable to function as one of the
following:
• General purpose I/O
• Capac iti ve se ns ing in put
6.5.2.7 RD6/CPSA14
These pins are configurable to function as one of the
following:
• General purpose I/O
• Capac iti ve se ns ing in put
6.5.2.8 RD7/CPSA15
These pins are configurable to function as one of the
following:
• General purpose I/O
• Capacitive sensing input
TABLE 6-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111
CPSACON0 CPSAON CPSARM —— CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000
CPSACON1 — — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000
CPSBCON0 CPSBON CPSBRM —— CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000
CPSBCON1 — — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000
T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/
DONE T3GVAL T3GSS1 T3GSS0 0000 0x00 uuuu uxuu
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx xxxx xxxx
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.
2010-2011 Microchip Technology Inc. DS41418B-page 67
PIC16(L)F707
6.6 PORTE and TRISE Registers
PORTE is a 4-bit wide, bidirectional port. The
corres pond ing d ata direc tion regis ter is TRISE. Se tting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e.,
enable the output driver and put the contents of the
output latch on th e s el ected pin). The exception is RE3,
which is input only and its TRIS bit will always read as
‘1’. Example 6-5 shows h ow to initialize PO R TE.
Readi ng t he PO R T E regi ste r (Register 6-16) reads th e
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch. RE3 reads ‘0’ when
MCLRE = 1.
The TR I SE r eg is t er ( Register 6-17) controls the PORTE
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISE register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘ 0’.
EXAMPLE 6-5: INITIALIZING PORTE
6.6. 1 ANSELE REGISTER
The ANSELE register (Register 6-18) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELE bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELE bits has no affect on digital
output functions. A pin with TRIS clear and ANSELE
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior when executing read-modify-write
inst ruct ion s on the af f ected port.
Note: The ANSELE register must be initialized
to conf igure an analo g channel as a di gital
input. Pins configured as analog inputs
will read ‘0’.
BANKSEL PORTE ;
CLRF PORTE ;Init PORTE
BANKSEL ANSELE ;
CLRF ANSELE ;digital I/O
BANKSEL TRISE ;
MOVLW B‘00001100’ ;Set RE<2> as an input
MOVWF TRISE ;and set RE<1:0>
;as outputs
REGISTER 6-16: PORTE: PORTE REGISTER
U-0 U-0 U-0 U-0 R-x R/W-x R/W-x R/W-x
— — — — RE3 RE2 RE1 RE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 RE<3:0>: PORTE I/O Pin bits
1 = Port pin is > VIH
0 = Port pin is < VIL
PIC16(L)F707
DS41418B-page 68 2010-2011 Microchip Technology Inc.
6.6.2 PIN DESCRIPTIONS
Each PORTE pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I2C or interrupts, refer to the appropriate
section in this data sheet.
6.6.2.1 RE0/AN5/CPSA5
These pins are configurable to function as one of the
following:
• General purpose I/O
• Analog input for the ADC
• Capacitive sensing input
6.6.2.2 RE1/AN6/CPSA6
These pins are configurable to function as one of the
following:
• General purpose I/O
• Analog input for the ADC
• Capacitive sensing input
6.6.2.3 RE2/AN7/CPSA7
These pins are configurable to function as one of the
following:
• General purpose I/O
• Analog input for the ADC
• Capacitive sensing input
REGISTER 6-17: TRISE: PORTE TRI-STATE REGISTER
U-0 U-0 U-0 U-0 R-1 R/W-1 R/W-1 R/W-1
— — — — TRISE3 TRISE2 TRISE1 TRISE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3 TRISE3: RE3 Port Tri-state Control bit
This bit is always ‘1’ as RE3 is an input only
bit 2-0 TRISE<2:0>: RE<2:0> Tri-State Control bits(1)
1 = PORTE pin configured as an input (tri-stated)
0 = PORTE pin configured as an output
REGISTER 6-18: ANSELE: PORTE ANALOG SELECT REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1
— — — — — ANSE2 ANSE1 ANSE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on Pins RE<2:0>, respectively
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2010-2011 Microchip Technology Inc. DS41418B-page 69
PIC16(L)F707
6.6.2.4 RE3/MCLR/VPP
These pins are configurable to function as one of the
following:
• General purpose input
• Master Clear Reset with weak pull-up
• Programming voltage reference input
TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR, BOR
Va lue on
all other
Resets
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000
ANSELE ———— — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111
CPSACON0 CPSAON CPSARM —— CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000
CPSACON1 ———— CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000
PORTE ———— RE3 RE2 RE1 RE0 ---- xxxx ---- xxxx
TRISE ————TRISE3
(1) TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Note 1: This bit is always ‘1’ as RE3 is input only.
PIC16(L)F707
DS41418B-page 70 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 71
PIC16(L)F707
7.0 OSCILLATOR MODU LE
7.1 Overview
The oscillator module has a wide variety o f clock s ources
and selection features that allow it to be used in a wide
range o f a pplic atio ns wh ile m axim izi ng pe rform ance and
minimizing power consumption. Figure 7-1 illustrates a
block d ia gram of th e os ci ll ator modu le.
Clock sources can be configured from external
oscilla tors, quartz crystal resonators , ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system can be configured to use an internal calibrated
high-frequency oscillator as clock source, with a choice
of se lec t abl e s peed s v ia software.
Clock source modes are configured by the FOSC bits
in Configuration Word 1 (CONFIG1). The oscillator
module can be configured for one of eight modes of
operation.
1. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on OSC2/CLKOUT.
2. RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.
3. INTOSC – Internal oscillator with FOSC/4 output
on OSC2 and I/O on OSC1/CLKIN.
4. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
5. EC – Ex ternal clock with I/O on OSC 2/CLKOUT.
6. HS – High Gain Crystal or Ceramic Resonator
mode.
7. XT – Medium Gain Crystal or Ceramic
Resonator Oscillator mode.
8. LP – Low-Power Crystal mode.
FIGURE 7-1: SI MPLI FI ED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
(CPU and Peripherals)
OSC1
OSC2
Sleep
External Oscillator
LP, XT, HS, RC, EC
System Clock
Postscaler
MUX
MUX
16 MHz/500 kHz
8 MHz/250 kHz
4 MHz/125 kHz
2 MHz/62.5 kHz
IRCF<1:0>
11
10
01
00
FOSC<2:0>
(Configu ra ti on Word 1)
Internal Oscillator (OSCCON Register)
500 kHz INTOSC
32x
MUX
0
1
PLL
PLLEN
(Configuration Word 1)
PIC16(L)F707
DS41418B-page 72 2010-2011 Microchip Technology Inc.
7.2 Clock Source Modes
Clock source modes can be classified as external or
internal.
• Internal clock source (INTOSC) is contained
within the oscillator module and derived from a
500 kHz high precision oscillator. The oscillator
module has eight selectable output frequencies,
with a maximum internal frequency of 16 MHz.
• Extern al c loc k mo de s rely on ext erna l circuitry for
the clock source. Examples are: oscillator mod-
ules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.
The syste m cl oc k can be selected betw ee n ex tern al or
internal clock sources via the FOSC bits of the
Configuration Word 1.
7.3 Internal Clock Modes
The oscillator module has eight output frequencies
derived from a 500 kHz high precision oscillator. The
IRCF bits of the OSCCON register select the
postscaler applied to the clock source dividing the
frequency by 1, 2, 4 or 8. Setting the PLLEN bit of the
Config ura tion Word 1 loc ks the interna l c lo ck s ourc e to
16 MHz befo re the p ostscal er is sel ecte d by the I RCF
bits. T he P LLEN bit m us t be se t or c lea red at th e ti me
of programming; therefore, only the upper or low four
clock source frequencies are selectable in software.
7.3.1 INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the devi ce is pr ogrammed using the o scillator selectio n
or the FOSC<2:0> bits in the CONFIG1 register. See
Section 8.0 “Device Configuration” for more
information.
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT outputs the selected
inter nal oscillator fr equency div ided by 4. Th e CLKOUT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
In INTOSCIO mode, OSC1/CLKIN and OSC2/
CLKOUT are available for general purpose I/O.
7.3.2 FREQUENCY SELECT BITS (IRCF)
The output of the 500 kHz INTOSC and 16 MHz
INT OSC, w ith Pha se Locke d Loop enabl ed, conne ct to
a postscaler and multiplexer (see Figure 7-1). The
Internal Oscillator Frequency Select bits (IRCF) of the
OSCCON register select the frequency output of the
internal oscillator. Depending upon the PLLEN bit, one
of four frequencies of two frequency sets can be
selected via software:
If PLLEN = 1, frequency selection is as follows:
•16 MHz
• 8 M Hz (Default after Reset)
•4 MHz
•2 MHz
If PLLEN = 0, frequency selection is as follows:
•500 kHz
• 250 kHz (Defau lt af te r Reset)
•125 kHz
•62.5 kHz
There is no start-up delay before a new frequency
selected in the IRCF bits takes effect. This is because
the old and new fre que nc ies are deri ved from INT O SC
via the post s ca ler and multiplexer.
Start-up delay specifications are located in the
Table 25-4 in Section 25.0 “Electrical
Specifications”.
Note: Following any Reset, the IRCF<1:0> bits
of the OSCCON register are set to ‘10’ and
the freq uency selec tion is se t to 8 MHz or
250 kHz. The user can modify the IRCF
bits to select a different frequency.
2010-2011 Microchip Technology Inc. DS41418B-page 73
PIC16(L)F707
7.4 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 7-1)
display s the st atus and a llows fre que ncy sele ction of t he
internal oscillator (INTOSC) system clock. The
OSCCON reg is ter c ont a ins the foll ow ing bits:
• Frequency selection bits (IRCF)
• Status Locked bits (I CSL)
• Status Stab l e bits (ICS S)
REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 U-0 R/W-1 R/W-0 R-q R-q U-0 U-0
—— IRCF1 IRCF0 ICSL ICSS — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
q = Value depends on condition
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 IRCF<1:0>: Internal Oscillator Frequency Select bits
When PLLEN = 1 (16 MHz INTOSC)
11 =16MHz
10 = 8 MHz (PO R val ue)
01 =4MHz
00 =2MHz
When PLLEN = 0 (500 kHz INTOSC)
11 = 500 kHz
10 = 250 kHz (PO R value)
01 = 125 kHz
00 = 62. 5 kHz
bit 3 ICSL: Internal Clock Oscillator Status Locked bit (2% Stable)
1 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) is in lock.
0 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has not yet locked.
bit 2 ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable)
1 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has stabilized to its maximum accuracy
0 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has not yet reached its maximum accuracy
bit 1-0 Unimplemented: Read as ‘0’
PIC16(L)F707
DS41418B-page 74 2010-2011 Microchip Technology Inc.
7.5 Oscillator Tuning
The INTOSC is factory calibrated but can be adjusted
in software by writing to the OSCTUNE register
(Register 7-2).
The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the INTOSC
frequency will begin shif tin g to th e new frequen cy. Code
execution continues during this shift. There is no
indication that the shif t has occ urred.
REGISTER 7-2: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits
01 1111 = Maximu m frequency
01 1110 =
•
•
•
00 0001 =
00 0000 = Oscillator module is running at the factory-calibrated frequency.
11 1111 =
•
•
•
10 0000 = Minimum frequency
2010-2011 Microchip Technology Inc. DS41418B-page 75
PIC16(L)F707
7.6 External Clock Modes
7.6.1 OSCILLATOR START-UP TIMER (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations on the OSC1 pin before the device is
release d from Reset. This occ urs follo wing a Power-on
Reset (POR) and when the Power-up Timer (PWRT)
has expired (if configured), or a wake-up from Sleep.
During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
cryst al res onator or ce ramic res onator, has st arted an d
is providing a stable system clock to the oscillator
module.
7.6.2 EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 7-2 shows the pin
connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 7-2: EXT ER NAL CLOCK (EC)
MODE OPERATION
7.6.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 7-3). The mod e select s a low ,
medium or high gain setting of the internal inverter-
amplifi er to support vari ous resonator typ es and spee d.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier . LP mode current consumption
is the least of the three modes. This mode is bes t suited
to drive resonators with a low drive level specification, for
example, tuning fork type cry st als.
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current c onsumption is the medium of the three mo des.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifie r. HS mode current consumption
is the highest of the three modes. This mode is best
suited for reso nators that require a high driv e se tting.
Figure 7-3 and Figure 7-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
FIGURE 7-3: QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
OSC1/CLKIN
OSC2/CLKOUT(1)
I/O
Clock from
Ext. System PIC® MCU
Note 1: Alternate pin functions are described in
Secti on 6.1 “Alternate Pin Function”.
Note 1: Quartz crystal characteristics vary
according to type, package and
manufacturer. The user should consult the
manuf actu rer da ta shee ts for spec ifi catio ns
and recom mended applicati on.
2: Always veri fy oscill ator performan ce over
the VDD and temperature range that is
expected for the application.
3: For oscillator desig n assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
selected.
C1
C2
Quartz
RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
Crystal
OSC2/CLKOUT
PIC16(L)F707
DS41418B-page 76 2010-2011 Microchip Technology Inc.
FIGURE 7-4: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
7.6.4 EXTERNAL RC MODES
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by 4. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 7-5 shows the
external RC mode connections.
FIGURE 7-5: EXTERNAL RC MODES
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resis t or (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
• threshold voltage variation
• component tolerances
• p ack ag ing varia tio ns in capacit ance
The user also needs to take into account variation due
to tolerance of external RC components used.
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
C1
C2 Ceramic RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
RP(3)
Resonator
OSC2/CLKOUT
OSC2/CLKOUT(1)
CEXT
REXT
PIC® MCU
OSC1/CLKIN
FOSC/4 o r
Internal
Clock
VDD
VSS
Recommended values: 10 k REXT 100 k, <3V
3 k REXT 100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1: Alternate pin functions are described in
Section 6.1 “Alternate Pin Function”.
2: Output depend s upon RC or RCIO clock mod e.
I/O(2)
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Value on
POR, BOR
Value on
all other
Resets(1)
CONFIG1(1) —CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —
OSCCON —— IRCF1 IRCF0 ICSL ICSS — — --10 qq-- --10 qq--
OSCTUNE —— TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: See Configuration Word 1 (Register 8-1) for operation of all bits.
2010-2011 Microchip Technology Inc. DS41418B-page 77
PIC16(L)F707
8.0 DEVICE CONFIGURATION
Device Configuration consists of Configuration Word 1
and Configuration Word 2 registers, Code Protection
and Device ID.
8.1 Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1
register at 2007h and Configuration Word 2 register at
2008h. These registers are only accessible during
programming.
REGISTER 8-1: CONFIG1: CONFIGURATION WORD REGISTER 1
R/P-1 R/P-1 U-1(4) R/P-1 R/P-1 R/P-1
DEBUG PLLEN — BORV BOREN1 BOREN0
bit 13 bit 8
U-1(4) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
—CPMCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
bit 7 bit 0
Legend: P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13 DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger
bit 12 PLLEN: INTOSC PLL Enable bit
0 = INTOSC frequency is 500 kHz
1 = INTOSC frequency is 16 MHz (32x)
bit 11 Unimplemented: Read as ‘1’
bit 10 BORV: Brown-out Reset Voltage Selection bit
0 = Brown-out Reset Voltage (VBOR) set to 2.5 V nominal
1 = Brown-out Reset Voltage (VBOR) set to 1.9 V nominal
bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1)
0x = BOR disabled (Preconditioned State)
10 = BOR enabled during operation and disabled in Sleep
11 = BOR enabled
bit 7 Unimplemented: Read as ‘1’
bit 6 CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5 MCLRE: RE3/MCLR Pin Function Select bit(3)
1 = RE3/MCLR pin function is MCLR
0 = RE3/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire program memory will be erased when the code protection is turned off.
3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
4: MPLAB® IDE masks unimplemented Configuration bits to ‘0’.
PIC16(L)F707
DS41418B-page 78 2010-2011 Microchip Technology Inc.
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
101 = INT OSC oscil la tor: CLKOUT functi on on RA6/OSC2/CLKOUT pin, I/O funct ion on RA7/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKO UT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
REGISTER 8-1: CONFIG1: CONFIGURATION WORD REGISTER 1 (CONTINUED)
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire program memory will be erased when the code protection is turned off.
3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
4: MPLAB® IDE masks unimplemented Configuration bits to ‘0’.
REGISTER 8-2: CONFIG2: CONFIGURATION WORD REGISTER 2
U-1(1) U-1(1) U-1(1) U-1(1) U-1(1) U-1(1) U-1(1) U-1(1)
— — — — — — — —
bit 15 bit 8
U-1(1) U-1(1) R/P-1 R/P-1 U-1(1) U-1(1) U-1(1) U-1(1)
— — VCAPEN1 VCAPEN0 — — — —
bit 7 bit 0
Legend: P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: R ead as ‘1’
bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits
For the PIC16LF707:
These bits are ignored. All VCAP pin functions are disabled.
For the PIC16F707:
00 =V
CAP functionality is enabled on RA0
01 =V
CAP functionality is enabled on RA5
10 =V
CAP functionality is enabled on RA6
11 = All VCAP functions are disabled (not recommended)
bit 3-0 Unimplemented: Read as ‘1’
Note 1: MPLAB® IDE masks unimplemented Configuration bits to ‘0’.
2010-2011 Microchip Technology Inc. DS41418B-page 79
PIC16(L)F707
8.2 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out usin g ICSP™ for verification purposes.
8.3 User ID
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during Program/Verify mode. Only
the Least Significant 7 bits of the ID locations are
reported when using MPLAB IDE. See the
“PIC16F707/PIC16LF707 Memory Programming
Specification” (DS41332) for more information.
Note: The entire Flash program memory will be
erased w hen the code prote ction is turned
off. See the “PIC16F707/PIC16LF707
Memory Programming Specification”
(DS41332) for more information.
PIC16(L)F707
DS41418B-page 80 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 81
PIC16(L)F707
9.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 8-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 8-bit binary result via successive
approximation and stores the conversion result into the
ADC result register (ADRES). Figure 9-1 shows the
bloc k diagram of the ADC.
The ADC vol tage referen ce is software selectab le to be
either internally generated or externally supplied.
The AD C can gener ate an i nterrupt upon comple tio n of
a conve rsion. This inte rrupt can be used to wake-up the
device from Sleep.
FIGURE 9-1: ADC BLOCK DIAGRAM
AN0
AN1
AN2
AN4
AVDD
VREF+
ADON
GO/DONE
ADREF = 10
ADREF = 0x
CHS<3:0>
VSS
AN5
AN6
AN7
AN3
AN8
AN9
AN10
AN11
AN12
AN13
Reserved
FVREF
0000
0001
0010
0011
0100
0101
0111
0110
1000
1001
1010
1011
1100
1101
1110
1111
8
ADC
ADRES
ADREF = 11
PIC16(L)F707
DS41418B-page 82 2010-2011 Microchip Technology Inc.
9.1 ADC Configuration
When configuring and using the ADC the following
functio ns must be considere d:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC convers ion cl ock source
• Interrupt control
• Results formatting
9.1.1 P ORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associat ed TRIS and ANSEL bits. Refer to Section 6.0
“I/O Ports” for more information.
9.1.2 CHANNEL SELECTION
The CHS bits of the ADCON0 r egister det ermine whic h
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 9.2
“ADC Operation” for more information.
9.1.3 ADC VOLTAGE REFERENCE
The ADREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be either VDD, an external
volt age source or the internal Fixed V oltage Refere nce.
The negative volt a ge reference is al way s c onn ec ted to
the ground reference. See Section 10.0 “Fixed
Voltage Reference” for more details on the Fixed
Voltage Refere nc e.
9.1.4 CONVERSION CLOCK
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
•F
OSC/2
•F
OSC/4
•FOSC/8
•FOSC/16
•F
OSC/32
•FOSC/64
•FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 8-bit conversion requires 10 TAD periods
as shown in Figure 9-2.
For correct conversion, the appropriate TAD
specif ica tio n m us t be m et . R efe r to th e A/D conv ers io n
requirements in Section 25.0 “Electrical
Specifications” for more information. Table 9-1 gives
examples of appropriate ADC clock selections.
Note: Analo g v ol tages on a ny pin that is d efined
as a digital inpu t may ca use the i nput buf-
fer to conduct excess current.
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD) Device Fr eque ncy (FOSC)
ADC
Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
Fosc/4 100 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s4.0 s
Fosc/8 001 400 ns(2) 0.5 s(2) 1.0 s2.0 s8.0 s(3)
Fosc/16 101 800 ns 1.0 s2.0 s4.0 s16.0 s(3)
Fosc/32 010 1.6 s2.0 s4.0 s8.0 s(3) 32.0 s(3)
Fosc/64 110 3.2 s4.0 s8.0 s(3) 16.0 s(3) 64.0 s(3)
FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be perf ormed during S leep.
2010-2011 Microchip Technology Inc. DS41418B-page 83
PIC16(L)F707
FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
9.1.5 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is th e ADIF bit in the
PIR1 register . The ADC Interrupt Enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
This interrupt can be generated while the device is
operatin g or while in Sle ep. If the device is in Sle ep, the
interrupt will wake-up the device. Upon waking from
Sleep, the n ext ins tructio n follow ing th e SLEEP instruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
Please refer to Section 9.1.5 “Interrupts” for more
information.
TAD1 TAD2 TAD3TAD4TAD5 TAD6TAD7 TAD8 TAD9
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
b7 b6 b5 b4 b3 b2 b1 b0
Tcy to TAD
Conversion Starts
ADRES register is loaded,
GO/DONE bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
TAD0
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
PIC16(L)F707
DS41418B-page 84 2010-2011 Microchip Technology Inc.
9.2 ADC Operation
9.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
9.2.2 COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF interrupt flag bit
• Update the ADRES regi ster with new co nversion
result
9.2.3 TERMINATING A CONVERSION
If a co nver sion must b e term ina ted be fore comp leti on,
the GO/DONE bit can be cleared in software. The
ADRES register will be updated with the partially com-
plete Analog-to-Digital conversion sample. Incomplete
bits will match the last bit converted.
9.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC wa its on e additio nal instru ction bef ore sta rting th e
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
9.2.5 SPECIAL EVENT TRIG GER
The Special Event Trigger of the CCP module allows
periodic ADC measurements without software inter-
vention. When this trigger occurs, the GO/DONE bit is
set by hardw are and the T imer1 co unter reset s to zero.
Using the S pecial Event T rigger does not assure proper
ADC timi ng. I t is the user’s resp onsib ility t o ensu re that
the ADC timing requirements are met.
Refer to Section 17.0 “Capture/Compare/PWM
(CCP) Module” for more information.
9.2.6 A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1. Con fig ure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Config ure pin as analo g (Refe r to the ANSEL
register)
2. Configure the ADC module:
• Select ADC conversion clock
• Config ure vo lt ag e refere nc e
• Select ADC input channel
• Turn on ADC module
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2).
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
• Polli ng the GO /DO N E bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Cle ar the ADC interrupt fla g (required i f interrupt
is enabled).
Note: The GO/DONE bit shou ld not be se t in the
same instruction that turns on the ADC.
Refe r to Section 9.2.6 “A/D Conversion
Procedure”.
Note: A devi ce Rese t forces all reg is ters to th eir
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
Note 1: The g lobal in terrupt can be disa bled if the
user is att empting to w ake-u p from Sleep
and resume in-line code execution.
2: Refer to Section 9.3 “A/D Acquisition
Requirements”.
2010-2011 Microchip Technology Inc. DS41418B-page 85
PIC16(L)F707
EXAMPLE 9-1: A/D CONVERSION
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL ADCON1 ;
MOVLW B’01110000’;ADC Frc clock,
;VDD reference
MOVWF ADCON1 ;
BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
BANKSEL ANSELA ;
BSF ANSELA,0 ;Set RA0 to analog
BANKSEL ADCON0 ;
MOVLW B’00000001’;AN0, On
MOVWF ADCON0 ;
CALL SampleTime ;Acquisiton delay
BSF ADCON0,GO ;Start conversion
BTFSC ADCON0,GO ;Is conversion done?
GOTO $-1 ;No, test again
BANKSEL ADRES ;
MOVF ADRES,W ;Read result
MOVWF RESULT ;store in GPR space
PIC16(L)F707
DS41418B-page 86 2010-2011 Microchip Technology Inc.
9.2.7 ADC REGISTER DEFINITIONS
The following registers are used to control the
operation of the A DC.
REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHS<3:0>: Analog Channel Select bits
0000 =AN0
0001 =AN1
0010 =AN2
0011 =AN3
0100 =AN4
0101 =AN5
0110 =AN6
0111 =AN7
1000 =AN8
1001 =AN9
1010 =AN10
1011 =AN11
1100 =AN12
1101 =AN13
1110 =Reserved
1111 = Fixed Voltage Reference (FVREF)
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
2010-2011 Microchip Technology Inc. DS41418B-page 87
PIC16(L)F707
REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
—ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
000 =F
OSC/2
001 =F
OSC/8
010 =F
OSC/32
011 =F
RC (clock supplied from a dedicated RC oscillator)
100 =F
OSC/4
101 =F
OSC/16
110 =F
OSC/64
111 =F
RC (clock supplied from a dedicated RC oscillator)
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 ADREF<1:0>: Voltage Reference Configuration bits
0x =VREF is connected to VDD
10 =VREF is connected to external VREF (RA3/AN3)
11 =V
REF is connected to internal Fixed Voltage Reference
REGISTER 9-3: ADRES: ADC RESULT REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<7:0>: ADC Result Register bits
8-bit conversion result.
PIC16(L)F707
DS41418B-page 88 2010-2011 Microchip Technology Inc.
9.3 A/D Acquisition Requirements
For the AD C to meet it s s pe ci fie d ac cu rac y, the c harg e
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The analog
input model is shown in Figure 9-3. The source
impeda nce (RS) and the inte rnal sam pling swi tch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 9-3. The maximum recommended
impedance for analog sources is 10 k. As the
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done bef ore the conversion can be s tarted. To calculate
the minimum acquisition time, Equation 9-1 may be
used. Th is equation assumes that 1 /2 LSb error is u sed
(256 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
EQUATION 9-1: ACQUISITION TIME EXAMPLE
TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Co efficient++=
TAMP TCTCOFF++=
2µs TCTemperature - 25°C0.05µs/°C++=
TCCHOLD RIC RSS RS++ ln(1/511)–=
10pF 1k
7k
10k
++– ln(0.001957)=
1.12
=µs
TACQ 2µs 1.12µs 50°C- 25°C0.05µs/°C++=
4.42µs=
VAPPLIED 1e
Tc–
RC
---------
–
VAPPLIED 11
2n1+
1–
--------------------------–
=
VAPPLIED 11
2n1+
1–
--------------------------
–
VCHOLD=
VAPPLIED 1e
TC–
RC
----------
–
VCHOLD=
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD char ge res pon se to VAPPLIED
;combining [1] and [2]
The value for TC can be approximated with the following equations:
Solving for TC:
Therefore:
Temperature 50°C and external impedance of 10k
5.0V V DD=
Assumptions:
Note: Whe re n = number of bits of the ADC.
Note 1: The reference voltage (VREF) has no effect on the equation, s ince it cancels itself ou t.
2: The charge holding capacitor (CHOLD) is not disc harged after ea c h conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
2010-2011 Microchip Technology Inc. DS41418B-page 89
PIC16(L)F707
FIGURE 9-3: ANALOG INPUT MODEL
FIGURE 9-4: ADC TRANSFER FUNCTION
CPIN
VA
Rs ANx
5 pF
VDD
VT 0.6V
VT 0.6V I LEAKAGE(1)
RIC 1k
Sampling
Switch
SS Rss
CHOLD = 10 pF
VSS/VREF-
6V
Sampling Switch
5V
4V
3V
2V
567891011
(k)
VDD
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD = Input Capacitance
= Threshold Voltage
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
various junctions
RSS
Note 1: Refer to Section 25.0 “Electrical Specifications”.
RSS = Resistance of Sampling Switch
FFh
FEh
ADC Output Code
FDh
FCh
04h
03h
02h
01h
00h
Full-Scale
FBh
1 LSB ideal
VSS Zero-Scale
Transition VREF
Transition
1 LSB ideal
Full-Scale Range
Analog Input Voltage
PIC16(L)F707
DS41418B-page 90 2010-2011 Microchip Technology Inc.
TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR, BOR
Va lue on
all other
Resets
ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000
ADCON1 — ADCS2 ADCS1 ADCS0 —— ADREF1 ADREF0 -000 --00 -000 --00
ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111
ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111
ANSELE — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111
ADRES A/D Result Register Byte xxxx xxxx uuuu uuuu
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
FVRCON FVRRDY FVREN — — CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 q000 0000 q000 0000
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
TRISE — — — — TRISE3 TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for ADC
module.
2010-2011 Microchip Technology Inc. DS41418B-page 91
PIC16(L)F707
10.0 FIXED VOLTAGE REFERENCE
The Fixed Voltage Reference, or FVR, is a stable
voltage reference independent of VDD with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
• ADC input channel
• ADC positive reference
• Digital -to- Analog Converte r (DAC)
• Capacitive Sensing Modules (CSM)
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
10.1 Independent Gain Amplifiers
The output of the FVR supplied to the ADC and
CSM/DAC modules is routed through the two
independent programmable gain amplifiers. Each
amplifier can be configured to amplify the reference
voltage by 1x, 2x or 4x.
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Refer-
ence Section 9.0 “Analog-to-Digital Converter
(ADC) Module” for addi t i on al i nfo r ma tio n o n sel e cti ng
the appropriate input channel.
The CDAFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the capacitive sensing an d
digital-to-analog converter modules. Reference
Section 16.0 “Capacitive Sensing Module” and
Section 11.0 “Digital-to-Analog Converter (DAC)
Module” for additional informa tion.
10.2 FVR Stabilizat ion Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for
use, the FVRRDY bit of the FVRCON register will be set.
See Section 25.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 10-1: VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
CDAFVR<1:0>
X1
X2
X4
X1
X2
X4
2
2
FVR BUFFER1
(To ADC Module)
FVR BUFFER2
(To Cap Sense, DAC)
+
_
FVREN
FVRRDY 1.024V Fixed
Reference
PIC16(L)F707
DS41418B-page 92 2010-2011 Microchip Technology Inc.
REGISTER 10-1: FVRCON: FIXED VOLTAGE REFERENCE REGISTER
R-q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FVRRDY(1) FVREN —— CDAFVR1(2) CDAFVR0(2) ADFVR1(2) ADFVR0(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
q = Value depends on condition
bit 7 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
0 = Fixed Voltage Reference output is not active or stable
1 = Fixed Voltage Referen ce out put is ready for use
bit 6 FVREN: Fixed Voltage Reference Enable bit
0 = Fixed Voltage Reference is disabled
1 = Fixed Voltage Reference is enabled
bit 5-4 Reserved: Read as ‘0’. Maintain these bits clear
bit 3-2 CDAFVR<1:0>: Cap Sense an d D/A Converter Fixed Voltage Reference Selecti on bit(2)
00 = CSM and D/A Converter Fixed Voltage Reference Peripheral output is off.
01 = CSM and D/A Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)
10 = CSM and D/A Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)
11 = CSM and D/A Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)
bit 1-0 ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bit(2)
00 = A/D Converter Fixed Voltage Reference Peripheral output is off.
01 = A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)
10 = A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)
11 = A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)
Note 1: FVRRDY is always ‘1’ on PIC16F707 devices.
2: Fixed Voltage Reference output cannot exceed VDD.
TABLE 10-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bi t 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
FVRCON FVRRDY FVREN Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 q000 0000 q000 0000
Legend: Shaded cells are not used by the voltage reference module.
2010-2011 Microchip Technology Inc. DS41418B-page 93
PIC16(L)F707
11.0 DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with VDD, with 32
selectable o utp ut l ev els . The output of the D AC ca n b e
configured to supply a reference voltage to the
following:
• DACOUT device pin
• Capacitive sensing modules
The Digit al-to-An alog Converte r (DAC) can be enabled
by setting the DACEN bit of the DACCON0 register.
11.1 Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels
are set with the DACR<4:0> bits of the DACCON1
register.
The DAC out put vol t age is determ ine d by the foll ow in g
equation:
EQUATION 11-1:
11.2 Output Clamped to VSS
The DAC output voltage can be set to VSS with no
power consumption by setting the DACEN bit of the
DACCON0 register to ‘0’.
11.3 Output Ratiometric to VDD
The DAC is VDD derived and therefore, the DAC output
changes with fluctuations in VDD. The tested absolute
accuracy of the DAC can be found in Section 25.0
“Electrical Specifications”.
11.4 Voltage Reference Output
The DAC can be output to the device DACOUT pin by
setting the DACOE bit of the DACCON0 register to ‘1’.
Selecting the reference voltage for output on the
DACOUT pin automatically overrides the digital output
buffer and digital input threshold detector functions of
that pin. Reading the DACOUT pin when it has been
configured for reference voltage output will always
return a ‘0’.
Due to the limited curren t drive cap abilit y, a buffer must
be used on the voltage reference output for external
connections to DACOUT. Example 11-1 shows an
example buffering technique.
11.5 Operation During Sleep
When the device wakes up from Sleep through an
interrupt o r a W a tchdo g T imer tim e-out, th e conte nts of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
11.6 Effects of a Reset
A device Reset af fec t s the follow ing:
• Voltage reference is disabled
• Fixed voltag e reference is disabled
• DAC is removed from the DACOUT pin
• The DACR<4:0> range select bits are cleared
VOUT VSOURCE VSOURCE – x DACR[4:0]
25
-----------------------------
VSOURCE+= -
IF DACEN = 1
IF DACEN = 0 & DACLPS = 1 & DACR[4:0] = 11111
VOUT VSOURCE = +
IF DACEN = 0 & DACLPS = 0 & DACR[4:0] = 00000
VOUT VSOURCE = -
VSOURCE+ = VDD, VREF, or FVR BUFFER 2
VSOURCE- = VSS
+-
PIC16(L)F707
DS41418B-page 94 2010-2011 Microchip Technology Inc.
FIGURE 11 -1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
EXAMPLE 11-1: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
16-to-1 MUX
DACR<4:0>
R
DACEN
VDD
VREF
DACPSS[1:0] = 00
R
R
R
R
R
R
32 S teps DAC
FVR
DACPSS[1:0] = 01
DACPSS[1:0] = 10
DACOUT pin
DACOE
DACLPS
DACEN
DACLPS
BUFFER 2
(To Capacitive
Sensing Module)
R
Buffered DAC Output
+
–
DAC
Module
Voltage
Reference
Output
Impedance
R
DACOUT
PIC16F707/
PIC16LF707
2010-2011 Microchip Technology Inc. DS41418B-page 95
PIC16(L)F707
REGISTER 11-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0
DACEN DACLPS DACOE —DACPSS1 DACPSS0 — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 DACEN: Digital-to-Analog Con ver ter Enable bit
0 = Digital-to-Analog Converter is disabled
1 = Digital-to-Analog Converter is enabled
bit 6 DACLPS: DAC Low-Power Voltage State Select bit
0 =V
DAC = DAC negative referenc e sou rce sele cted
1 =V
DAC = DAC positive ref erence source selected
bit 5 DACOE: DAC Voltage Outp ut En able bit
0 = DAC voltage level is output on th e DA COU T pin
1 = DAC voltage level is disconnected from the DACOUT pin
bit 4 Unimplemented: Read as ‘0’
bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits
00 =V
DD
01 =VREF
10 = FVR Buffer 2 output
11 = Reserved, do not use
bit 1-0 Unimplemented: Read as ‘0’
REGISTER 11-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — DACR4 DACR3 DACR2 DACR1 DACR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 DACR<4:0>: DAC Voltage Output Select bits
PIC16(L)F707
DS41418B-page 96 2010-2011 Microchip Technology Inc.
TABLE 11-1: REGISTERS ASSOCIATED WITH THE DIGITAL-TO-ANALOG CONVERTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
FVRCON FVRRDY FVREN Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 q000 0000 q000 0000
DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — — 000- 00-- 000- 00--
DACCON1 — — — DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the DAC module.
2010-2011 Microchip Technology Inc. DS41418B-page 97
PIC16(L)F707
12.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (shared with Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Inter rupt on overflow
Figure 12-1 is a block diagram of the Timer0 module.
FIGURE 12-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
T0CKI
TMR0SE
TMR0
WDT
Time-out
PS<2:0>
WDTE
Data Bus
Set Flag bit TMR0IF
on Overflow
TMR0CS
0
1
0
1
0
1
8
8
8-bit
Prescaler
0
1
FOSC/4
PSA
PSA
PSA
Sync
2 TCY
Divide by
512
TMR1GE
T1GSS = 11
pin
Note 1: TMR0SE , TMR0CS, PS A, PS<2:0> are bits in the OPTION register.
2: WDTE bit is in Configuration Word 1.
3: T1GSS and TMR1GE are in the T1GCON register.
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DS41418B-page 98 2010-2011 Microchip Technology Inc.
12.1 Timer0 Operation
The T ime r0 module can be used as either an 8-b it timer
or an 8-bit counter.
12.1.1 8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the OPTION
register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
12.1.2 8-BIT COUNTER MODE
In 8-bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin. 8-bit
Counter mode using the T0CKI pin is selected by setting
the TMR0CS bit of the OPTION register to ‘1’.
The rising or fall ing transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION register.
12.1.3 SOFTWARE PROGRAMMA BLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignme nt is contro lled by the PSA bit o f the OPTION
register. To as si gn t he p res ca ler t o Timer0, the PSA bit
must be cleared to a ‘0’.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
select able via th e PS<2:0> bits of the OPTION registe r .
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When the
prescaler is enabled or assigned to the Timer0 module,
all instructions w riting to the TMR 0 reg ister will c lear the
prescaler.
12.1.4 TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The T imer0
interrupt enable is the TMR0IE bit of the INTCON
register.
12.1.5 USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks.
Therefore, the high and low periods of the external
clock source must meet the timing requirements as
shown in Section 25.0 “Electrical Specifications”.
12.1.6 TIMER ENABLE
Operati on of Time r0 is alw ays en abled and the mo dule
will operate according to the settings of the OPTION
register.
12.1.7 OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
Note: When the presc aler is a ssigned to W DT, a
CLRWDT inst ruction wi ll clear the p rescaler
along with the WDT.
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
2010-2011 Microchip Technology Inc. DS41418B-page 99
PIC16(L)F707
REGISTER 12-1: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 TMR0CS: TMR0 Clock Source Select bit
1 = Transit ion on T0CKI pin
0 = Internal instruction cycle clo ck (FOSC/4)
bit 4 TMR0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assig nme nt bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
BIT VALUE TMR0 RA TE WD T RAT E
TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
OPTION_REG RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend: – = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.
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DS41418B-page 100 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 101
PIC16(L)F707
13.0 TIMER1/3 MODULES WITH
GATE CONTROL
The Timer1 and Timer3 modules are 16-bit timers/
counters with the following features:
• 16-bit timer/counter register pair (TMRxH:TMRxL)
• Programmable internal or external clock source
• 3-bit prescaler
• Dedicated LP oscillator circuit (Timer1 only)
• Synchronous or asynchronous operation
• Multiple Timer1/3 gate (count enable) sources
• Inter rupt on overflow
• Wake-up on overflow (external c lock,
Asynchronous mode only)
• Time base for the Capture/Compare function
(Timer1 only)
• Special Event Trigger with CCP (Timer1 only)
• Selectable Gate Sour ce Polarity
• Gate Toggle mode
• Ga te Single-pulse mode
• Gate Value Status
• Gate Event Interrupt
Figure 13-1 is a block diagram of the Timer1/3
modules.
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DS41418B-page 102 2010-2011 Microchip Technology Inc.
FIGURE 13-1: TIMER1/TIMER3 BLOCK DIAGRAM
TMRxH TMRxL
TxSYNC
TxCKPS<1:0>
Prescaler
1, 2, 4, 8
0
1
Synchronized
clock input
2
Set flag bit
TMRxIF on
Overflow TMRx(2)
TMRxON
Note 1: ST Buffer is high speed type when using TxCKI.
2: Timer1/3 register increme nts on rising edge.
3: Synchronize does not operate while in Sleep.
4: Timer1 gat e source is TimerA. Timer3 g at e source is TimerB. Refer to Table 13-1.
5: Timer1 clock source is CPSAOSC. Timer3 clock source is CPSBOSC. Refer to Table 13-1.
6: Timer3 does not have a T3OSC circuit. There is no T3OS CEN bit. Timer3 can operate from T1 OSC.
TxG
T1OSC
FOSC
Internal
Clock
T1OSO/T1CKI
T1OSI
T1OSCEN
1
0
TxCKI
TMRxCS<1:0>
(1)
Synchronize(3)
det
Sleep input
TMRxGE
0
1
00
01
10
11
From TimerA /B
From Timer2
TxGPOL
D
Q
CK
Q
0
1
TxGVAL
TxGTM
Single Pulse
Acq. Control
TxGSPM
TxGGO/DONE
TxGSS<1:0>
EN
OUT 11
10
00
00
FOSC/4
Internal
Clock
From WDT
Overflow
Match PR2
Overflow(4)
R
D
EN
Q
Q1 RD
TXGCON
Data Bus
det
Interrupt TMRxGIF
Set
TxCLK
FOSC/2
Internal
Clock
D
EN
Q
TxG_IN
(6)
Cap. Sense(5)
Oscillator A/B
TABLE 13-1: CPSOSC/TIMER
ASSOCIATION
Period
Measurement Cap Sense
Oscillator Divider Timer
(Gate Source)
Timer1 CPS A TimerA
Timer3 CPS B TimerB
2010-2011 Microchip Technology Inc. DS41418B-page 103
PIC16(L)F707
13.1 Timer1/3 Operation
The Timer1 and Timer3 modules are 16-bit increment-
ing counters which are accessed through the
TMRxH:TMRxL register pair. Writes to TMRxH or
TMRxL directly update the counter.
When us ed with an interna l clock source, t he modul e is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and incre-
ments on every selected edge of the external source.
Timer1/3 is enabled by configuring the TMRxON and
TMRxGE bits in the TxCON and TxGCON registers,
respectively. Table 13-2 displays the Timer1/3 enable
selections.
13.2 Clock Source Selection
The TMRxCS<1:0> bits of the TxCON register and the
T1OSCEN bit of the T1CON register are used to select
the clock source for Timer1/3. Table 13-3 displays the
clock so urce selec tions.
13.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMRxH:TMRxL register pair will increment on multiples
of FOSC as determined by the Timer1/3 presc aler.
13.2.2 EXTERNAL CLOCK SOURCE
When the external clock source is selected, the
Timer1/3 modules may work as a timer or a counter.
When enabled to count, Timer1/3 is in cremented on the
rising edge of the external clock input TxCKI or a
capacitive sensing oscillator signal. Either of these
external clock sources can be synchronized to the
microcontroller system clock or they can be run
asynchronously. If set for the capacitive sensing
oscillator signal, Timer1 will use the CPS A signal and
Timer3 will use the CPS B signal (see Table 13-1).
When used as a timer with a clock oscillator, an
external 32.768 kHz crys tal can be used in co njunction
with the dedicated internal oscillator circuit. Only one
dedicated internal oscillator circuit is available. See
Section 13.4 “Timer1/3 Oscillator” for more
information.
TABLE 13-2: TIMER1/3 ENABLE
SELECTIONS
TMRxON TMRxGE Timer1/3
Operation
00Off
01Off
10Always On
11Cou nt Enabled
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
inc rement ing ri sing ed ge after any one o r
more of the following conditions:
• Timer1/3 enabled after POR reset
• Write to TMRxH or TMRxL
• Timer1/3 is disabled
• Timer1/3 is disabled (TMRxON = 0)
when TxCKI is high, then Timer1/3 is
enabled (TMRxON=1) when TxCKI i s
low.
TABLE 13-3: CLOCK SOURCE SELECTIONS
TMRxCS1 TMR xCS0 T1OSCEN Timer1 Clock Source Timer3 Clo ck Source
01xSystem Clock (FOSC) System Clock (FOSC)
00xInstruction Clock (FOSC/4) Instruction Clock (FOSC/4)
11xCapacitive Sensing A Oscillator Capacitive Sensing B Oscillator
100External Clocking on T1CKI Pin Externa l Clocki ng on T3 CKI Pin
101Oscillator Circuit on T1OSI/
T1OSO Pins Oscillator Circuit on T1OSI/
T1OSO Pins
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DS41418B-page 104 2010-2011 Microchip Technology Inc.
13.3 Timer1/3 Prescaler
T ime r1 and Time r3 have four prescaler options allowing
1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits
of the TxCON register control the presc ale counter. The
prescale counter is not directly readable or writable;
however , the prescaler counter is cleared upon a write to
TMRxH or T MR xL .
13.4 Timer1/3 Oscillator
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins T1OSI (input) and T1OSO
(amplifier output). This internal circuit is to be used in
conjun cti on wi th an ext erna l 32.76 8 kHz crystal.
The oscillator circuit is enabled by setting the
T1OSC EN bit of the T1C ON register . Th e oscillato r can
provide a clock source to Timer1 and/or Timer3. The
oscillator will continue to run during Sleep.
13.5 Timer1/3 Operation in
Asynchronous Counter Mode
If control bit TxSYNC of the TxCON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If external clock source is selected, then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will w ake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 13.5.1 “Reading and Writing Timer1/3 in
Asynchronous Counter Mode”).
13.5.1 READING AND WRITING TIMER1/3
IN ASYNCHRONOUS COUNTER
MODE
Reading TMRxH or TMRxL while the timer is running
from an e xternal asyn chronous cl ock will ens ure a valid
read (taken care of in hardware). However, the user
should keep i n mind that rea ding t he 16-bi t ti mer in two
8-bit values itself poses certain problems, since the
timer may overflow between the reads.
For writes , it is re commend ed that th e user s imply sto p
the timer and write the desired values. A write
conte ntion may occ ur by writin g to th e time r regi sters,
while the register is incrementing. This may pro duce an
unpredic table val ue in the TMRxH:T MRxL register p air .
13.6 Timer1/3 Gate
T i mer1/3 c an be con fig ured to cou nt freely or the c ount
can be enabled and disabled using Timer1/3 gate
circuit ry. This is also referre d to as Timer1/3 gate c ount
enable.
T imer 1/3 gate ca n also be driven by multipl e select abl e
sources.
13.6.1 TIMER1/3 GATE COUNT ENABLE
The T imer1/3 gate is enabled by setting the TMRxGE bit
of the TxGCON register. The polarity of the Timer1/3
gate is configured using the TxGPOL bit of the TxGCON
register.
When T ime r1/3 gate (Tx G) input is act ive, T imer1/3 wil l
increment on the rising edge of the Timer1/3 clock
source. Whe n Timer1/3 gate input is in ac tiv e, n o i nc re-
menting will occur and Timer1/3 will hold the current
count. See Figure 13-3 for timing details.
13.6.2 TIMER1/3 GATE SOURCE
SELECTION
The Timer1/3 gate source can be selected from one of
four dif ferent sources. Sou rce selec tion is cont rolled b y
the TxGSS bits of the TxGCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the TxGPOL bit of the
TxGCON register.
Note: The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay ob served prior to enab ling Timer1/3.
TABLE 13-4: TIMER1/3 GATE ENABLE
SELECTIONS
TxCLK TxGPOL TxG Timer1/3 Operation
00 Counts
01 Holds Count
10 Holds Count
11 Counts
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13.6.3 TxG PIN GATE OPERATION
The TxG pin is one so urce for Timer 1/3 gate contr ol.
It can be used to supply an external source to the
T ime r1/3 gate circu itry. T im er1 ga te ca n be c onfig ured
for the T 1G pi n an d Timer3 gat e ca n be con fig ured for
the T3G pin.
13.6.4 TIMERA/B OVERFLOW GATE
OPERATION
When TimerA/B increments from FFh to 00h a low-to-
high pulse will automatically be generated and
internally supplied to the T imer1/3 gat e circuitry . T imer1
gate can be confi gured for T imerA overflo w and T imer3
gate can be configured for TimerB overflow.
13.6.5 TIMER2 MAT CH GA TE OP ER AT IO N
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs , a low-to-high pul se will automa tically be gen er-
ated and internally supplied to the Timer1/3 gate cir-
cuitry. Both Timer1 gate and Timer3 gate can be
configured for the Timer2 match.
13.6.6 WATCHDOG OVERFLOW GATE
OPERATION
The Watchdog Timer oscillator, prescaler and counter
will b e au tom ati ca lly tu rned on w h en T MRx G E = 1 and
TxGSS se lects the WDT as a ga te s ourc e fo r Timer1 /3
(TxGSS = 11). TMRxON does not factor into the oscil-
lator, prescaler and counter enable. See Table 13-6.
Both Timer1 gate and Timer3 gate can be configured
for Watchdog overflow.
The PSA and PS bits of the OPTION register still
control w hat time -out interva l is select ed. Changi ng the
prescaler during operation may result in a spurious
capture.
Enabling the Watchdog Timer oscillator does not
automatically enable a Watchdog Reset or wake-up
from Sleep upon counter overflow.
As the gate signal coming from the WDT counter will
generate different pulse widths, depending on if the
WDT is enabled, when the CLRWDT instruction is exe-
cuted, and so on, Toggle mode must be used. A spe-
cific sequence is required to put the device into the
correct state to capture the next WDT counter interval.
TABLE 13-5: TIMER1/3 GATE SOURCES
TxGSS Timer1 Gate Source Timer3 Gate Source
00 Timer1 Gate Pin Timer3 Gate Pin
01 Overflow of Time rA
(TMRA increments from FFh to 00h) Overflow of TimerB
(TMRB increments from FFh to 00h)
10 Timer2 match PR2
(TMR2 increments to match PR2) Timer2 match PR2
(TMR2 increments to match PR2)
11 Count Enabled by WDT Overflow
(Watchdog Time-out interval expired) Count Enabled by WDT Overflow
(Watchdog Ti me-out interval expired)
Note: When us ing the WDT as a gate source for
Timer1/3, operations that clear the
Watchdog Timer (CLRWDT, SLEEP
instructions) will affect the time interval
being measured for capacitive sensing.
This incl udes waking from Sleep. All other
interr upts that might wake th e dev ice from
Sleep should be disabled to prevent them
from disturbing the measurement period.
TABLE 13-6: WDT/TIMER1/3 GATE INTERRACTION
WDTE TMRxGE = 1 an d
TxGSS = 11 WDT Oscill ator
Enable WDT Reset Wake-up WDT Available for
TxG Source
1NYYYN
1YYYYY
0YYNNY
0NNNNN
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DS41418B-page 106 2010-2011 Microchip Technology Inc.
13.6.7 TIMER1/3 GATE TOGGLE MODE
When Timer1/3 Gate Toggle mode is enabled, it is
pos sibl e t o me as ur e t he f u ll -c y cle l e ng t h of a Timer1/ 3
gate sig nal, as opp osed to the duratio n of a singl e level
pulse.
The Timer1/3 gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 13-4 for timing details.
Timer1/3 Gate Toggle mode is enabled by setting the
TxGTM bit of the TxGCON register. When the TxGTM
bit is c leared, the fl ip-flop is c leared and held c lear . Thi s
is necessary in order to control which edge is
measured.
13.6.8 TIMER1/3 GATE SINGLE-PULSE
MODE
When Timer1/3 Gate Single-Pulse mode is enabled, it
is possible to capture a single puls e gate event. T imer1/
3 Gate Single-Pulse mode is first enabled by se tting the
TxGSPM bit in the TxGCON register. Next, the
TxGGO/DONE bit in the TxGCON r egister must be se t.
The Timer1/3 will be fully enabled on the next incre-
menting edge. On the next trailing edge of the pulse,
the TxGGO/DONE bit will automatically be cleared. No
other gate events will be allowed to increment Timer1/
3 until the TxGGO/DONE bit is once again set in soft-
ware.
Clearing the TxGSPM bit of the TxGCON register will
also clear the TxGGO/DONE bit. See Figure 13-5 for
timing details.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1/3
gate sou rce to be measured. See Figure 13-6 for timing
details.
13.6.9 TIMER1/3 GATE VALUE STATUS
When Timer1/3 gate value status is utilized, it is
possible to read the most current level of the gate
control value. The value is stored in the TxGVAL bit in
the TxGCON register. The TxGVAL bit is valid even
when the Timer1/3 gate is not enabled (TMRxGE bit is
cleared).
13.6.10 TIMER1/3 GATE EVENT
INTERRUPT
When Timer1/3 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIRx reg ister will be
set. If the TMRxGIE bit in the PIEx register is set, then
an interrupt will be recognized. See Table 13-7 for
interr upt bit locati on s.
The TMRxGIF flag bit operates even when the
T imer1/3 gate is not enabled (TMRxGE bit is cleared).
13.7 Timer1/3 Interrupt
The Timer1/3 register pair (TMRxH:TMRxL)
increments to FFFFh and rolls over to 0000h. When
T i mer1/3 rolls over, the T ime r1/3 int errup t flag bit of th e
PIRx register is set. See Table 13-7 for interrupt bit
locations.
To enable the interrupt on rollover, you must set these
bits:
• TMRxON bit of the TxCON register
• TMRxIE bit of the PIEx register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMRxIF bit in
the Interrupt Service Routine.
Note: Enabling Toggle mode at the same time
as chan ging the gate po larity may res ult in
indeterm in ate ope rati on.
TABLE 13-7: TIMER1/3 INTERRUPT BIT LOCATIONS
Timer1 Timer3
Interrupt Flag TMR1IF bit in PIR1 register TMR3IF bit in PIR2 register
Interrupt Enable TMR1IE bit in PIE1 register TMR3IE bit in PIE2 register
Gate Interrupt Flag TMR1GIF bit in PIR1 register TMR3GIF bit in PIR2 register
Gate Interrupt Enable TMR1GIE bit in PIE1 register TMR3GIE bit in PIE2 register
Note: The TMRxH:TMRxL register pair and the
TMRxIF bit should be cleared before
enabling interrupts.
2010-2011 Microchip Technology Inc. DS41418B-page 107
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13.8 Timer1/3 Operation During Sleep
Timer1/3 can only operate during Sleep when setup in
Asynch ronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMRxON bit of the TxCON register must be set
• TMRxIE bit of the PIEx register must be set
• PEIE bit of the INTCON register must be set
• TxSYNC bit of the TxCON register must be set
• TMRxCS bits of the TxCON register must be
configured
• T1OSCEN bit of the T1CON register must be
configured
• TMRxGIE bit of the TxGCON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
13.9 CCP Capture/Compare Time Base
(Timer1 Only)
The CCP module uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered wh en the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
For more information, see Section 17.0 “Capture/
Compare/PWM (CCP) Module”.
13.10 CCP Special Event T rigger (Timer1
only)
When the CCP is confi gu r ed to trig ger a sp ec ial even t,
the trigger will clear the TMR1H:TMR1L register pair.
This s pecial event does not cause a Timer1 interrupt.
The CCP modu le may still be conf igu r ed to ge nera te a
CCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer 1 shou ld be sync hronized to the FOSC/4 to utilize
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
In the eve nt that a wri te to TMR1H or TMR1L coi ncides
with a Special Event T rigger from the CCP, the write will
take precedence.
For more information, see Section 17.2.4 “Special
Event Trigger”.
FIGURE 13-2: TIMER1/TIMER3 INCREMENTING EDGE
TxCKI = 1
when TMR1/3
Enabled
TxCKI = 0
when TMR1/3
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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DS41418B-page 108 2010-2011 Microchip Technology Inc.
FIGURE 13-3: TIMER1/TIMER3 GATE COUNT ENABLE MODE
FIGURE 13-4: TIMER1/TIMER3 GATE TOGGLE MODE
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer1/3 N N + 1 N + 2 N + 3 N + 4
TMRxGE
TxGPOL
TxGTM
TxG_IN
TxCKI
TxGVAL
TIMER1/3 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8
2010-2011 Microchip Technology Inc. DS41418B-page 109
PIC16(L)F707
FIGURE 13-5: TIMER1/TIM ER3 GATE SINGLE-PULSE MODE
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
TIMER1/3 N N + 1 N + 2
TxGSPM
TxGGO/
DONE Set by software Cleared by hardware on
falling edge of TxGVAL
Set by hardware on
falling edge of TxGVAL
Cleared by software Cleared by
software
TMRxGIF
Counting enabled on
rising edge of TxG
PIC16(L)F707
DS41418B-page 110 2010-2011 Microchip Technology Inc.
FIGURE 13-6: TIMER1/TIMER3 GATE SINGLE-PULSE AND TOGG LE COMBINED MODE
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
TIMER1/3 NN + 1
N + 2
TxGSPM
TxGGO/
DONE Set by software Cleared by hardware on
falling edge of TxGVAL
Set by hardware on
falling edge of TxGVAL
Cleared by sof tware Cleared b y
software
TMRxGIF
TxGTM
Counting enabled on
rising edge of TxG
N + 4
N + 3
2010-2011 Microchip Technology Inc. DS41418B-page 111
PIC16(L)F707
13.11 Timer1/3 Control Regis ter
The Timer1/3 Control register (TxCON), shown in
Register 13-1, is used to control Timer1/3 and select
the various features of the Timer1/3 module.
REGISTER 13-1: TxCON: TIMER1/TIMER3 CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0
TMRxCS1 TMRxCS0 TxCKPS1 TxCKPS0 T1OSCEN(1) TxSYNC —TMRxON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 TMRxCS<1:0>: Timerx Clock Source Select bits
11 =Timerx clock source is Capacitive Sensing Oscillator (CPSxOSC)
10 =Timerx clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from TxCKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on T1OSI/T1OSO pins
01 =Timerx clock source is system clock (FOSC)
00 =Timerx clock source is instruction clock (FOSC/4)
bit 5-4 TxCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: LP Oscillator Enable Control bit(1)
1 = Dedicated Timer1/3 oscillator circuit enabled
0 = Dedicated Timer1/3 oscillator circuit disabled
bit 2 TxSYNC: Timerx External Clock Input Synchronization Control bit
If TMRxCS<1:0> = 1X
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock (FOSC)
If TMRxCS<1:0> = 0X
This bit is ignored. Timerx uses the internal clock when TMR1CS<1:0> = 0X.
bit 1 Unimplemented: Read as ‘0’
bit 0 TMRxON: Timerx on bit
1 = Enables Timerx
0 = S tops T imerx
Clears Timerx gate flip-flop
PIC16(L)F707
DS41418B-page 112 2010-2011 Microchip Technology Inc.
REGISTER 13-2: TxGCON: TIMER1/TIMER3 GATE CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0
TMRxGE TxGPOL TxGTM TxGSPM TxGGO/
DONE TxGVAL TxGSS1 TxGSS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
bit 7 TMRxGE: Timerx Gate Enable bit
If TMRx ON = 0:
This bit is ignored.
If TMRx ON = 1:
1 = Timerx counting is controlled by the Timerx gate function
0 = Timerx counts regardless of Timerx gate function
bit 6 TxGPOL: Timerx Gate Polarity bit
1 = Timerx gate is active-hi gh (Timerx coun ts when gate is high)
0 = Timerx gate is active-low (Timerx counts when gate is low)
bit 5 TxGTM: Timerx Gate Toggle Mode bit
1 = Timerx Gate Toggle mode is enabled
0 = Timerx Gate Toggle mode is disabled and toggle flip-flop is cleared
Timerx gate flip-flop toggles on every rising edge.
bit 4 TxGSPM: Timerx Gate Single-Pulse Mode bit
1 = Timerx gate Single-Pulse mode is enabled and is controlling Timerx gate
0 = Timerx gate Single-Pulse mode is disab led
bit 3 TxGGO/DONE: Timerx Gate Single-Pulse Acquisition Status bit
1 = Tim erx gate single-pulse acquisition is ready, waiting for an edge
0 = Timerx gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2 TxGVAL: Timerx Gate Current State bit
Indicates the current state of the Timerx gate that could be provided to TMRxH:TMRxL.
Unaffected by Ti merx Gate Enable (TMRxGE).
bit 1-0 TxGSS<1:0>: Timerx Gate Source Select bits
00 = Timerx gate pin
01 = TimerA/B overflow out put
10 = TMR2 Match PR2 output
11 = Watchdog Timer scaler overflow
Watchdog Timer oscillator is turned on if TMRxGE = 1, regardless of the state of TMR1ON.
2010-2011 Microchip Technology Inc. DS41418B-page 113
PIC16(L)F707
14.0 TIMERA/B MODULES
TimerA and TimerB are two more Timer0-type
modules. Timers A and B are available as general-
purpose timers/counters, and are closely integrated
with the capacitive sensing modules.
The TimerA/B modules incorporate the following
features:
• 8-bit timer/counter register (TMRx)
• 8-bit prescaler
• Programmable internal or external clock source
• Programmable external clock edge selection
• Inter rupt on overflow
• TMRA can be used to gate Timer1
• TMRB can be used to gate Timer3
Figure 14-1 is a block diagram of the TimerA/TimerB
modules.
FIGURE 14-1: BLOCK DIAGRAM OF THE TIMERA/TIMERB PRESCALER
TxCKI
TMRxSE
pin
TMRx
TMRxPS<2:0>
Data Bus
Set Fl a g b i t TMR x IF
on Overflow
TMRxCS
Note 1: TxXCS is in the CPSxCON0 register.
0
1
0
18
8
8-bit
Prescaler
FOSC/4
TMRxPSA
Sync
2 Tcy
Ov e rfl o w to Time r 1/3
1
0
TxXCS
From
CPSxOSC
PIC16(L)F707
DS41418B-page 114 2010-2011 Microchip Technology Inc.
14.1 TimerA/B Operation
The TimerA/B modules c an be u se d a s ei the r 8-bit tim-
ers or 8-bit counters. Additio nally , the module s can also
be used to set Timer1’s/Timer3’s period of measure-
ment for the capacitive sensing modules via Timer1’s
or Timer3’s gate feature.
14.1.1 8-BIT TIMER MODE
The TimerA/B modules will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMRxCS bit of the TxCON
registers.
When TMRx is written, the increment is inhibited for
two instruction cycles immediately following the write.
14.1.2 8-BIT COUNTER MODE
In 8-bit Counter mode, the TimerA/B modules will
increment on every rising or falling edge of the TxCKI
pin or the Capacitive Sensing Oscillator (CPSxOSC)
signal. 8-bit Counter mode using the TxCKI pin is
selected by setting the TMRxCS bit of the TxCON
register to ‘1’ and resetting the TxXCS bit in the
CPSxCON0 register to ‘0’. 8-bit Counter mode using the
Capacitive Sensing Oscillator (CPSxOSC) signal is
selected by setting the TMRxCS bit in the TxCON
register to ‘1’ and setting the TxXCS bit in the
CPSxCON0 register to ‘1’.
The rising or fall ing transition of the incrementing edge
for either input source is determined by the TMRxSE bit
in the TxCON register.
14.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
For TimerA/B modules, the software programmable
prescaler is exclusive to the Timer. The prescaler is
enabled by clearing the TMRxPSA bit of the TxCON
register.
There are 8 prescaler options for TimerA/B modules
ranging from 1:2 to 1:256. The prescale values are
selectable via the TMRxPS<2:0> bits of the TxCON
register for TimerA/B. In order to have a 1:1 prescaler
value fo r th e TimerA /B m odu les , th e p res ca ler m us t b e
disabled.
The prescaler is not readable or writable. When the
prescaler is enabled or assigned to the Timer module, all
instructions writing to the TMRx register will clear the
prescaler. Enabling the TimerA/B modules also clears
the prescaler.
14.1.4 TIMERA/B INTERRUPT
TimerA/B will generate an interrupt when the
corresponding TMR register overflows from FFh to
00h. The TMRxIF interrupt flag bit of the PIR2 register
is set every time the TMRx register overflows. These
interrupt flag bits are set regardless of whether or not
the rela tive Timer interrupt is enabled. The interrupt flag
bits can only be cleared in software. The TimerA/B
interrupt enable bits are the TMRxIE in the PIE2
register.
14.1.5 USING TIMERA/B WITH AN
EXTERNAL CLOCK
When TimerA/B is in Counter mode, the
synchronization of the TxCKI input and the TMRx
register is accomplished by sampling the prescaler
output on the Q2 and Q4 cycles of the internal phase
clocks. Therefore, the high and low periods of the
external clock source must meet the timing
requirements as shown in Section 25.0 “Electrical
Specifications”.
14.1.6 TIMER ENABLE
Operation of TimerA/B is enabled by setting the
TMRxON bit of the TxCON register. When the module
is disabled, the value in the TMRx register is
maintained. Enabling the TMRx module will reset the
prescaler used by the counter.
14.1.7 OPERATION DURING SLEEP
T imerA and T imerB cannot operate while the processor
is in Sleep mode. The contents of the TMRx registers
will remain unchanged while the processor is in Sleep
mode.
TABLE 14-1: CPSOSC/TIMER
ASSOCIATION
Cap Sense
Oscillator Divider Timer Period
Measurement
CPS A TimerA Timer1
CPS B TimerB Timer3
Note: The value written to the TMRx register can
be adjusted, in order to account for the
two instruction cycle delay when TMRx is
written.
Note: TimerA/B interrupts cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
2010-2011 Microchip Technology Inc. DS41418B-page 115
PIC16(L)F707
REGISTER 14-1: TxCON: TIMERA/TIMERB CONTROL REGISTER
R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMRxON — TMRxCS TMRxSE TMRxPSATMRxPS2 TMRxPS1 TMRxPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMRxON: TimerA/Time rB On/Of f Contr ol bit
1 = Tim erx is enabled
0 = Timerx is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 TMRxCS: TMRx Clock Source Select bit
1 = Transition on TxCKI pin or CPSxOS C sig nal
0 = Internal instruction cycle clo ck (FOSC/4)
bit 4 TMRxSE: TMRx Source Edge Select bit
1 = Increment on high-to-low transition on TxCKI pin
0 = Increment on low-to-high transition on TxCKI pin
bit 3 TMRxPSA: Prescaler Assignment bit
1 = Prescaler is disabled. Timer cl ock input bypasses prescaler.
0 = Prescaler is enabled. Timer clock input comes from the prescaler output.
bit 2-0 TMRxPS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
BIT VALUE TMRx RATE
TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH TIMERA/B
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
CPSACON0 CPSAON CPSARM — — CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000
CPSBCON0 CPSBON CPSBRM — — CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000
PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE 0000 ---0 0000 ---0
PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF 0000 ---0 0000 ---0
TACON TMRAON — TACS TASE TAPSA TAPS2 TAPS1 TAPS0 0-00 0000 0-00 0000
TBCON TMRBON — TBCS TBSE TBPSA TBPS2 TBPS1 TBPS0 0-00 0000 0-00 0000
TMRA TimerA Module Register 0000 0000 0000 0000
TMRB TimerB Module Register 0000 0000 0000 0000
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: – = Unimplemented locations, read as ‘0’. Shaded cells are not used by the TimerA/B modules.
PIC16(L)F707
DS41418B-page 116 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 117
PIC16(L)F707
15.0 TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following
features:
• 8-bit timer register (TMR2)
• 8-bit period register (PR2)
• Interrupt on TMR2 match with PR2
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
See Figure 15-1 for a block diagram of Timer2.
15.1 Timer2 Operation
The clock input to the Timer2 module is the system
instruction clock (FOSC/4). The clock is fed into the
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:16. The output of the prescal er is the n use d to
increm ent the TM R2 regis ter.
The val ues of T MR2 and PR2 are co nstan tly com pared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented.
The match output of the Timer2/PR2 comparator is
then fed into th e T i mer2 post sca ler. The post s caler has
post scal e options of 1:1 to 1: 16 inclus ive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
The TMR2 and PR2 registers are both fully readable
and w rita ble. O n any Rese t, the TMR2 regis ter is set to
00h and the PR2 register is set to FFh.
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Tim er2 is turned off by clearin g
the TMR2ON bit to a ‘0’.
The Timer2 presc ale r is contro lle d by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
• A write to TMR2 occurs.
• A write to T2CON occurs.
• Any device Reset occurs (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset).
FIGURE 15-1: TIMER2 BLOCK DIAGRAM
Note: TMR2 is not cleared when T2CON is
written.
Comparator
TMR2 Sets Flag
TMR2
Output
Reset
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
TOUTPS<3:0>
T2CKPS<1:0>
PIC16(L)F707
DS41418B-page 118 2010-2011 Microchip Technology Inc.
REGISTER 15-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
0001 = 1:2 Postscaler
0010 = 1:3 Postscaler
0011 = 1:4 Postscaler
0100 = 1:5 Postscaler
0101 = 1:6 Postscaler
0110 = 1:7 Postscaler
0111 = 1:8 Postscaler
1000 = 1:9 Postscaler
1001 = 1:10 Postscaler
1010 = 1:11 Postscaler
1011 = 1:12 Postscaler
1100 = 1:13 Postscaler
1101 = 1:14 Postscaler
1110 = 1:15 Postscaler
1111 = 1:16 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Tim er2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 =Prescaler is 1
01 =Prescaler is 4
1x = Prescaler is 16
TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR, BOR
Va lue on
all other
Resets
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PR2 Timer2 Module Period Register 1111 1111 1111 1111
TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
2010-2011 Microchip Technology Inc. DS41418B-page 119
PIC16(L)F707
16.0 CAPACITIVE SENSING
MODULE
The capacitive sensing modules (CSM) allow for an
interaction with an end user without a mechanical
interface. In a typical application, the capacitive
sensing module is attached to a pad on a Printed
Circuit Board (PCB), which is electrically isolated from
the end user. When the end user places their finger
over the PCB pad, a capacitive load is added, causing
a frequ ency shif t in the c apaci tive sensin g module. Th e
capacitive sensing module requires software and at
least one timer resource to determine the change in
frequency. Key features of this module include:
• Analog MUX for monitoring multiple inputs
• Capacitive sensing oscillator
• Multiple Power modes
• High power range with variable voltage
references
• Multiple timer resources
• Software control
• Operation during sleep
• Acquire two samples simultaneously (when using
both CSM modules)
Two identical capacitive sensing modules are
implemented on the PIC16F707/PIC16LF707. The
modules are named CPSA and CPSB. The timer
module integration fo r both capa citive sensing modules
is shown in Table 16-1. A block diagram of the
capa citive se nsing module is shown in Figure 16-1 and
Figure 16-2.
TABLE 16-1: CPSOSC TIMER USAGE
Cap Sense Oscillator Mode Frequency Measurement Duration Control
Cap S ense Oscillator A TimerA/Software TimerA Software
Timer1/Software Timer1 Software
Timer1/TimerA Timer1 TimerA
Cap S ense Oscillator B TimerB/Software TimerB Software
Timer3/Software Timer3 Software
Timer3/TimerB Timer3 TimerB
PIC16(L)F707
DS41418B-page 120 2010-2011 Microchip Technology Inc.
FIGURE 16-1: CAPA CITIVE SENSING BLOCK DIAGRAM
TMRxCS
CPSx0
CPSx1
CPSx2
CPSx3
CPSx4
CPSx5
CPSx6
CPSx7
CPSx8
CPSx9
CPSx10
CPSxCH<3:0>
Capacitive
Sensing
Oscillator
CPSxRNG<1:0>
CPSxRM
TMRx
0
1
Set
TMRxIF
Overflow
TxXCS
0
1
TxCKI
TMRxCS<1:0>
T1OSC/
TxCKI
TMRxH:TMRxL
EN
TxGSS<1:0>
Timer1/3 Gate
Control Logic
TxG
CPSxOUT
CPSx11
CPSx12
CPSx13
CPSx14
CPSx15
CPSxCLK
Note 1: If CPSxON = 0, disabling capacitive sensing, no channel is selected.
FOSC/4
FOSC
FOSC/4
TimerA/B Module
Timer1/3 Module
CPSxON(1)
CPSxON
0
10
1
Ref-
Ref+
DAC
FVR
Int.
Ref.
CPSxOSC
Watchdog Timer Module
LP WDT
OSC WDT
Scaler Overflow
WDT
Event
PS<2:0>
Timer2 Module
TMR2 Overflow Postscaler Set
TMR2IF
2010-2011 Microchip Technology Inc. DS41418B-page 121
PIC16(L)F707
FIGURE 16-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM
0
1
VDD
CPSxCLK
Oscillator Module
CPSx SQ
R
+
-
+
-
Note 1: Module Enable and Power mode selections are not shown.
2: Comparators remain active in Noise Detection mode.
(2)
(1)
(1) (2)
0
1
Internal
References
FVR(3)
DAC(3)
CPSxRM
Analog Pin
Ref- Ref+
PIC16(L)F707
DS41418B-page 122 2010-2011 Microchip Technology Inc.
16.1 Analog MUX
Each capacitive sensing module can monitor up to 16
inputs, providing 32 capacitive sensing inputs in total.
The capacitive sensing inputs are defined as
CPSA<15:0> for capacitive sensing module A, and
CPSB<15:0> for capacitive sensing module B. To
determine if a frequency change has occurred the use
must:
• Select the appropriate CPS pin by setting the
CPSxCH<3:0> bits of the CPSxCON1 register.
• Set the corresponding ANSEL bit.
• Set the corresponding TRIS bit.
• Run the software algorithm.
Selection of the CPSx pin while the module is enabled
will c ause the capac itive sensin g osci llator to be on the
CPSx pin. Fail ure to set the c orrespondi ng ANSEL and
TRIS bits can cause the capacitive sensing oscillator to
stop, leading to false frequency readings.
16.2 Capacitive Sensing Oscill ator
The ca p acitive sens ing o scil lator c onsi sts of a cons ta nt
current source and a constant current sink, to produce
a triangle waveform. The CPSxOUT bit of the
CPSxCON0 re gis ter sh ow s the s t at us of the cap a ci tiv e
sensing oscillator, whether it is sinking or sourcing
current. The oscillator is designed to drive a capacitive
load (sin gle PCB pa d) and at the same time, be a cloc k
source to either TimerA/B or Timer1/3. The oscillator
has three different current settings as defined by
CPSxRNG<1:0> of the CPSxCON0 register. The
different current settings for the oscillator serve two
purposes:
• Maximize the number of counts in a timer for a
fixed time base.
• Maximize the count differential in the timer during
a change in frequency.
16.3 Voltage References
The capacitive sensing oscillator uses voltage
references to provide two voltage thresholds for
oscillation. The upper voltage threshold is referred to
as Ref+ and the lower voltage threshold is referred to
as Ref-.
The user can elect to use fixed voltage references,
which are internal to the capacitive sensing oscillator,
or variable voltage references, which are supplied by
the Fixed Voltage Reference (FVR) module and the
Digital-to-Analog Converter (DAC) module.
When the fixed voltage references are used, the VSS
volt age determi nes the lower th reshold le vel (Ref-) and
the VDD voltage determines the upper threshold level
(Ref+).
When the variable voltage references are used, the
DAC voltage determines the lower threshold level
(Ref-) and the FVR voltage determines the upper
threshold level (Ref+) . An advantage of usin g these ref-
erence sources is that oscillation frequency remains
constant with changes in VDD.
Different oscillation frequencies can be obtained
through the use of these variable voltage references.
The more the upper voltage reference level is lowered
and the more the lower voltage reference level is
raised, the higher the capacitive sensing oscillator
frequency becomes.
Selection between the voltage references is controlled
by the CPSxRM bit of the CPSxCON0 register. Setting
this bit selects the variable voltage references and
clearing this bit selects the fixed voltage references.
Please see Section 10.0 “Fixed Voltage Reference”
and Section 11.0 “Digital-to-Analog Converter
(DAC) Module” for more information on configuring
the variable voltage levels.
2010-2011 Microchip Technology Inc. DS41418B-page 123
PIC16(L)F707
16.4 Power Modes
The capacitive sensing oscillator can operate in one of
seven different power modes. The power modes are
separated into two ranges; the low range and the high
range.
When the oscillator's low range is selected, the fixed
internal voltage references of the capacitive sensing
oscillator are being used. When the oscillator's high
range is selected, the variable voltage references
supplied by the FVR and DAC modules are being used.
Selection between the voltage references is controlled
by the CPSxRM bit of the CPSxCON0 register. See
Section 16.3 “Voltage References” for more
information.
Within each range there are three distinct power
modes; Low, Medium and High. Current consumption
is dependent upon the range and mode selected.
Selecting power modes within each range is accom-
plished by configuring the CPSxRNG <1:0> bits in the
CPSxCON0 register. See Table 16-2 for proper power
mode selection.
The remaining mode is a Noise Detection mode that
resides within the high range. The Noise Detection
mode is unique in th at it disabl es the sink ing and sourc-
ing of current on the analog pin but leaves the rest of
the oscillator circuitry active. This reduces the oscilla-
tion frequency on the analog pin to zero and also
greatly reduces the current consumed by the oscillator
module.
When noise is introduced onto the pin, the oscillator is
driven at the frequency determined by the noise. This
produ ce s a d etectable signal at the com p a r ato r ou tput,
indicating the presence of activity on the pin.
Figure 16-2 shows a more detailed drawing of the
current sources and comparators associated with the
oscillator.
16.5 Timer Resources
To measure the change in frequency of the capacitive
sensin g oscillato r , a fixed ti me base is require d. For the
period of the fixed time base, the capacitive sensing
oscillator is used to clock either TimerA/B or Timer1/3
(for CPSA/B, respectively). The frequency of the
capacitive sensing oscillator is equal to the number of
counts in the timer divided by the period of the fixed
time base.
16.6 Fixed Ti me Base
To measure the frequency of the capacitive sensing
oscillator, a fixed time base is required. Any timer
resource or software loop can be used to establish the
fixed ti me base. It i s up to the e nd user to de termine the
method in which the fixed time base is generated.
TABLE 16-2: POWER MODE SELECTION
CPSxRM Range CPSxRNG<1:0> Mode Nominal Current (1)
0Low 00 Off 0.0 µA
01 Low 0.1 µA
10 Medium 1.2 µA
11 High 18 µA
1High 00 Nois e De tectio n 0.0 µA
01 Low 9 µA
10 Med ium 30 µA
11 High 100 µA
Note: See Section 25.0 “Electrical Specifications” for more information.
Note: The fi xed tim e b as e ca n not be genera ted
by the timer resource that the capacitive
sensing oscillator is clocking.
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DS41418B-page 124 2010-2011 Microchip Technology Inc.
16.6.1 TIMERA/B
To select TimerA/B as the timer resource for the
capacitive sensing module:
• Set the TAXCS/TBXCS bit of the CPSACON0/
CPSBCON0 register.
• Clear the TMRACS/TMRBCS bit of the TACON/
TBCON register.
When TimerA/B is chosen as the timer resource, the
cap acitive sens ing oscillato r will be the clock so urce for
TimerA/B. Refer to Section 14.0 “TimerA/B Mod-
ules” for additional information.
16.6.2 TIMER1/3
To select Timer1/3 as the timer resource for the
capacitive se nsing modu le, set the TMR xCS<1:0> of
the Tx CON r eg ister to ‘ 11’. When Timer1/3 is cho sen
as the t imer resource , the capacitive s ensing osc illa-
tor wil l be the cloc k sou rc e fo r Timer1/3. B eca use the
Timer1/3 module has a gate control, developing a
time base for the frequency measurement can be
simplifie d by usi ng the TimerA/B ov erfl ow flag.
It is recommend that the TimerA/B overflow flag, in
conjun ction with the Toggle mod e o f the Ti mer1/3 gate,
be used to develop the fixed time base required by the
software portion of the capacitive sensing module.
Refer to Section 13.11 “Timer1/3 Control Register ”
for additional information.
16.7 Software Control
The software portion of the capacitive sensing module
is require d to dete rmine th e chan ge in freq uency of the
capacitive sensing oscillator. This is accomplished by
the following:
• Setting a fixed time base to acquire counts on
Ti merA/B or Timer1/3.
• Est ab lis hi ng the nom in al freq uen cy for the
capacitive sensing oscillator.
• Est ab lis hi ng the redu ce d frequ enc y for the
capacitive sensing oscillator due to an additional
capacitive load.
• Set the frequency threshold.
16.7.1 NOMINAL FREQ UENCY (NO
CAPACITIVE LOAD)
To determine the nominal frequency of the capacitive
sensing oscillator:
• Remov e any ext ra capa citive lo ad on the s elected
CPSx pin.
• At the start of the fixed time base, clear the timer
resource.
• At the end of the fixed time bas e, save the val ue
in the timer resource.
The value of the timer resource is the number of
oscillations of the capacitive sensing oscillator for the
given time base. The frequency of the capacitive
sensing oscillator is equal to the number of counts on
the timer divided by the period of the fixed time base.
16.7.2 REDUCED FREQUENCY
(ADDITION AL CAPACITIVE LOAD)
The extra capacitive load will cause the frequency of
the capacitive sensing oscillator to decrease. To
determine the reduced frequency of the capacitive
sensing oscillator:
• Add a typical capacitive load on the selected
CPSx pin.
• Use the same fixed time base as the nominal
frequency measurement.
• At the start of the fixed time base, clear the timer
resource.
• At the end of the fixed time bas e, save the val ue
in the timer resource.
The value of the timer resource is the number of
oscillations of the capacitive sensing oscillator with an
additional capacitive load. The frequency of the
capacitive sensing oscillator is equal to the number of
counts on the timer divided by the period of the fixed
time base. This frequency should be less than the
value obtained during the nominal frequency
measurement.
TABLE 16-3: TIMER1/3 ENABLE FUNCTION
TMRxON TMRxGE Timerx Operat ion
00 Off
01 Off
10 On
11Count Enabl ed by Inp ut
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PIC16(L)F707
16.7.3 FREQUENCY THRESHOLD
The frequency threshold should be placed midway
between the value of nominal frequency and the
reduced frequency of the capacitive sensing oscillator.
Refer to Application Note AN1103, “Software Handling
for Capacitive Sensing” (DS01103) for more detailed
information on the software required for capacitive
sensing module.
16.8 Operation during Sleep
The capaciti ve s ensin g osc illato r wi ll co ntinue to run as
long as th e mo dule is enabl ed, independent of the par t
being in Sl eep . In ord er for th e software to det ermine if
a frequency change has occurred, the part must be
awak e. Howe ver, the part does n ot have to be aw ake
when the timer resource is acquiring counts.
Note: For more information on general
capacitive sensing refer to Application
Notes:
• AN1101, “Introduction to Capacitive
Sensing” (DS01101)
• AN1102, “Layout and Physical
Design Guidelines for Capacitive
Sensing” (DS011 02).
Note: TimerA/B does not o perate when in Sleep,
and therefore cannot be used for
capaci tive se nse mea sur ements in Sle ep.
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DS41418B-page 126 2010-2011 Microchip Technology Inc.
REGISTER 16-1: CPSxCON0: CAPACITIVE SENSING CONTROL REGISTER 0
R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0
CPSxON CPSxRM —— CPSxRNG1 CPSxRNG0 CPSxOUT TxXCS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 CPSxON: Capacitive Sensing Module Enable bit
1 = Capacitive sensing module is e nabled
0 = Capacitiv e sensing module is disabled
bit 6 CPSxRM: Capacitive Sensing Reference Mode bit
1 = Capaciti v e sensing module is in hig h range. D AC and FVR provide oscillator volta ge references.
0 = Capaciti v e sensing modu le is in low range. Internal oscillat or voltage refe rences are used.
bit 5-4 Unimplemented: Read as ‘0’
bit 3-2 CPSxRNG<1:0>: Capaciti ve Sens in g Cur rent Range bits
If CPSxRM = 0 (low range):
11 = Oscillator is in high range: Charge/discharge current is nominally 18 µA.
10 = Oscillator is in medium range. Charge/discharge current is nominally 1.2 µA.
01 = Oscillator is in low range. Charge/discharge current is nominally 0.1 µA.
00 = Oscillator is off.
If CPSxRM = 1 (high range):
11 = Oscillator is in high range: Charge/discharge current is nominally 100 µA.
10 = Oscillator is in medium range. Charge/discharge current is nominally 30 µA.
01 = Oscill ator is in low range. Charge/discharg e current is nomi nally 9 µA .
00 =Oscillator is on; Noise Detection mode; No charge/discharge current is supplied.
bit 1 CPSxOUT: Capacitive Sensing Oscillator Status bit
1 = Oscillator is sourcing current (Current flowing out of the pin)
0 = Oscillator is sinking current (Current flowing into the pin)
bit 0 TxXCS: TimerA/B Extern al Cloc k Sourc e Sele ct bit
If TMRxCS = 1:
The TxXCS bit controls which clock external to the core/TimerA/B module supplies TimerA/B:
1 = TimerA/B clock source is the capacitive sensing oscillator
0 = TimerA/B clock source is the TxCKI pin
If TMRxCS = 0:
TimerA/B clock source is controlled by the core/TimerA/B module and is FOSC/4.
2010-2011 Microchip Technology Inc. DS41418B-page 127
PIC16(L)F707
REGISTER 16-2: CPSxCON1: CAPACITIVE SENSING CONTROL REGISTER 1
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — CPSxCH3 CPSxCH2 CPSxCH1 CPSxCH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, rea d as ‘0’
u = bit is unchanged x = Bit is unkno wn -n /n = Value at POR an d BO R / Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 CPSxCH<3:0>: Ca paci tive S ensing Ch ann el S elect bits
If CPSxON = 0:
The se bits are i gnored. No channel is sel ected.
If CPSxON = 1:
0000 = channe l 0 , (CPSx0)
0001 = channe l 1 , (CPSx1)
0010 = channe l 2 , (CPSx2)
0011 = channe l 3 , (CPSx3)
0100 = channe l 4 , (CPSx4)
0101 = channe l 5 , (CPSx5)
0110 = channe l 6 , (CPSx6)
0111 = channe l 7 , (CPSx7)
1000 = channe l 8 , (CPSx8)
1001 = channe l 9 , (CPSx9)
1010 = channe l 1 0, (CPSx10)
1011 = channe l 11, (CPSx11)
1100 = channe l 1 2, (CPSx12)
1101 = channe l 1 3, (CPSx13)
1110 = channe l 1 4, (CPSx14)
1111 = channe l 1 5, (CPSx15)
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DS41418B-page 128 2010-2011 Microchip Technology Inc.
TABLE 16-4: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all ot her
Resets
ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111
ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111
ANSELC ANSC7 ANSC6 ANSC5 —— ANSC2 ANSC1 ANSC0 111- -111 111- -111
ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111
ANSELE — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111
CPSACON0 CPSAON CPSARM —— CPSARNG1 CPSARNG0 CPSAOUT TAXCS 00-- 0000 00-- 0000
CPSACON1 — — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000
CPSBCON0 CPSBON CPSBRM —— CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000
CPSBCON1 — — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000
TACON TMRAON — TACS TASE TAPSA TAPS2 TAPS1 TAPS0 0-00 0000 0-00 0000
TBCON TMRBON — TBCS TBSE TBPSA TBPS2 TBPS1 TBPS0 0-00 0000 0-00 0000
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON0000 00-0 0000 00-0
T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 — T3SYNC —TMR3ON0000 -0-0 0000 -0-0
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
TRISE — — — — TRISE3 TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the capacitive sensing modules.
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PIC16(L)F707
17.0 CAPTURE/COMPARE/PWM
(CCP) MODULE
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events. In Capture mode, the peripheral allows the
timing of the duration of an event. The Compare mode
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate a pulse-width modulated signal of
varying frequency and duty cycle.
The timer resources used by the module are shown in
Table 17-2.
Additional information on CCP modules is available in
Application Note AN594, “Using the CCP Modules”
(DS00594).
TABLE 17-1: CCP MODE – TIMER
RESOURCES REQUIR ED
CCP Mode Timer Resource
Capture Timer1
Compare Timer1
PWM Timer2
Note: Timer3 has no connection to either CCP.
TABLE 17-2: INTERACTION OF TWO CCP MODULES
CCP1 Mode CCP2 Mode Interaction
Capture Capture Same TMR1 time base
Capture Compare Same TMR1 time base(1 , 2)
Compare Compare Same TMR1 time base(1, 2)
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt).
The rising edges will be aligned.
PWM Capture None
PWM Compare None
Note 1: If CCP2 is configured as a Special Event Trigger, CCP1 will clear Timer1, affecting the value captured on
the CCP2 pin.
2: If CCP1 is in Capture mode and CCP2 is configured as a Special Event Trigger, CCP2 will clear Timer1,
affecting the value captured on the CCP1 pin.
Note: CCPRx and CCPx throughout this
document refer to CCPR1 or CCPR2 and
CCP1 or CCP2, respectively.
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DS41418B-page 130 2010-2011 Microchip Technology Inc.
REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mo de:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM<3:0>: CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (CCPxIF bit of the PIRx register is set)
0011 = Unused (reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit of the PIRx register is set)
1001 = Compare mode, clear output on match (CCPxIF bit of the PIRx register is set)
1010 = Comp are mo de, generate s oftware interrupt on m atc h (CC Px IF b it is se t of the PIRx reg is ter,
CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit of the PIRx register is set, TMR1 is reset
and A/D conversion(1) is started if the ADC module is enabled. CCPx pin is unaffected.)
11xx = PWM mode.
Note 1: A/D conversion start feature is available only on CCP2.
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PIC16(L)F707
17.1 Capture Mode
In Capture mode, CCPRxH:CCPRxL captures the
16-bit value of the TMR1 r egister wh en an eve nt occurs
on pin CCPx. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the interrupt request flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value (refer to Figure 17-1).
17.1.1 CCPx PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Either RC1 or RB3 can be selected as the CCP2 pin.
Refer to Section 6.1 “Alternate Pin Function” for
more information.
FIGURE 17-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
17.1.2 TIMER1 MODE SELECTION
T imer1 must be running in Timer mode or Synchronized
Counter mod e for the CCP mod ule to use t he capture
feature. In Asynchronous Counter mode or when
Timer1 is clocked at FOSC, the capture operation may
not work.
17.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in operating mode.
17.1.4 CCP PRESCALER
There are four prescaler settings specified by the
CCPxM<3 :0> bits o f the CC PxCON regis ter . Whenev er
the CCP module is turned off, or the CCP module is not
in Captu re mode, the presca ler count er is clea red. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler (refer to Example 17-1).
EXAMPLE 17-1: CHANGING BETWEEN
CAPTURE PRESCALERS
17.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
T imer1 module in Capture mode. It can be drive n by the
instruction clock (FOSC/4), or by an external clock
source.
If Timer1 is clocked by FOSC/4, then Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
If Timer1 is clocked by an external clock source, then
Capt ure m ode wil l ope rate as defi ned in Section 17.1
“Capture Mode”.
Note: If th e CCPx p in is c onfigured as an output,
a write to the port can cause a capture
condition.
CCPRxH CCPRxL
TMR1H TMR1L
Set Flag bit CCPxIF
(PIRx register)
Capture
Enable
CCPxCON<3:0>
Prescaler
1, 4, 16
and
Edge Detect
CCPx
System Clock (FOSC)
Note: Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
BANKSEL CCP1CON ;Set Bank bits to point
;to CCP1CON
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS;Load the W reg with
; the new prescaler
; move value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
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DS41418B-page 132 2010-2011 Microchip Technology Inc.
TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111
ANSELC ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0 111- -111 111- -111
APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00
CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
CCPRxL Capture/Compare/PWM Register X Low Byte xxxx xxxx uuuu uuuu
CCPRxH Capture/Compare/PWM Register X High Byte xxxx xxxx uuuu uuuu
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE 0000 ---0 0000 ---0
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF 0000 ---0 0000 ---0
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON
0000 00-0 uuuu uu-u
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 0000 0x00
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: - = Unimplemented locations, re ad as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the capture.
2010-2011 Microchip Technology Inc. DS41418B-page 133
PIC16(L)F707
17.2 Compare Mode
In Compare mode, the 16-bit CCPRx register value is
constantly compared against the TMR1 register pair
value. When a mat ch occurs, the CCPx modul e may:
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register.
All Compare modes can generate an interrupt.
FIGUR E 1 7-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
17.2.1 CCPx PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
Either RC1 or RB3 can be selected as the CCP2 pin.
Refer to Section 6.1 “Alternate Pin Function” for
more information.
17.2.2 TIMER1 MODE SELECTION
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
17.2.3 SOFTWARE INTERRUPT MODE
When Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPxIF bit in the PIRx
register is set and the CCPx module does not assert
control of the CCPx pin (refer to the CCPxCON
register).
17.2.4 SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is en abled
(CCP2 onl y)
The CCPx m odule does no t assert control of the CCPx
pin in this mode (refer to the CCPxCON register).
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL
register pair. The TMR1H, TMR1L register pair is not
reset until th e next r ising ed ge of the T imer1 clock. This
allows the CCPRxH, CCPRxL register pair to
effectively provide a 16-bit programmable period
register for Timer1.
17.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
Note: Clearing the CCPxCON register will force
the CCPx compare output latch to the
default lo w level. This is n ot the POR T I /O
data l atch.
CCPRxH CCPRxL
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set CCPxIF Interrupt Flag
(PIRx)
Match
TRIS
CCPxCON<3:0>
Mode Select
Output Enable
Special Event Trigger will:
• Clear TMR1H and TMR1L registers.
• NOT set interrupt flag bit TMR1IF of the PIR1 register.
• Set the GO/DONE bit to start the ADC conversion
(CCP2 only).
CCPx 4
Note: Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. For the Compare operation of the
TMR1 register to the CCPRx register to
occur, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 registe r.
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will
preclude the Reset from occurring.
PIC16(L)F707
DS41418B-page 134 2010-2011 Microchip Technology Inc.
TABLE 17-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000
ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111
ANSELC ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0 111- -111 111- -111
APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00
CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
CCPRxL Capture/Compare/PWM Register X Low Byte xxxx xxxx uuuu uuuu
CCPRxH Capture/Compare/PWM Register X High Byte xxxx xxxx uuuu uuuu
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE 0000 ---0 0000 ---0
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF — — — CCP2IF 0000 ---0 0000 ---0
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON
0000 00-0 uuuu uu-u
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 0000 0x00
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: - = Unimplemented locations, re ad as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the compare.
2010-2011 Microchip Technology Inc. DS41418B-page 135
PIC16(L)F707
17.3 PWM Mode
The PWM mode generates a pulse-width modulated
signal on the CCPx pin. The duty cycle, period and
resolution are determined by the following registers:
•PR2
•T2CON
• CCPRxL
• CCPxCON
In Pulse-Width Modulation (PWM) mode, the CCP
module produce s up to a 10 -bit resol ution PWM outp ut
on the CCPx pin.
Figure 17-3 show s a s impl ifie d bl ock d iag ram of PWM
operation.
Figure 17-4 shows a typical waveform of the PWM
signal.
For a ste p-by-step proc edure on how t o set up the CC P
module for PWM operation, refer to Section 17.3.8
“Setup for PWM Operation”.
FIGURE 17-3: SIMPLIFIED PWM BLOCK
DIAGRAM
The PWM output (Figure 17-4) has a time base
(period) and a time that the output stays high (duty
cycle).
FIGURE 17-4: CCP PWM OUTPUT
17.3.1 CCPX PIN CONFIGURATION
In PWM mode, the CCPx pin is multiplexed with the
PORT data latch. The user must configure the CCPx
pin as an outpu t by clearing the associated TRIS bit.
Either RC1 or RB3 can be selected as the CCP2 pin.
Refer to Section 6.1 “Alternate Pin Function” for
more information.
CCPRxL
CCPRxH(2) (Slave)
Comparator
TMR2
PR2
(1)
RQ
S
Duty Cycle Registers CCPxCON<5:4>
Clear Timer2 ,
toggle CCPx pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler , to create the 10-bit time
base.
2: In PWM mode, CCPRxH is a read-only register.
TRIS
CCPx
Comparator
Note: Clearing the CCPxCON register will
relinquish CCPx control of the CCPx pin.
Period
Pulse Width
TMR2 = 0
TMR2 = CCPRxL:CCPxCON<5:4>
TMR2 = PR2
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DS41418B-page 136 2010-2011 Microchip Technology Inc.
17.3.2 PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 17-1.
EQUATION 17-1: PWM PERIOD
When TM R2 is equa l to PR2, t he followi ng three ev ents
occur on t he next incremen t cycle:
• TMR2 is cl eare d
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The P WM dut y cy cle is latc hed fro m CCPRx L int o
CCPRxH.
17.3.3 PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit value
to multiple registers: CCPRxL register and D CxB<1:0>
bits of the CCPxCON register. The CCPRxL contains
the eight MSbs and the DCxB<1:0> bits of the
CCPxCON register contain the two LSbs. CCPRxL and
DCxB<1:0> bits of the CCPxCON register can be written
to at any time. The duty cycle value is not latched into
CCPRxH until after the period completes (i.e., a match
between PR2 and TMR2 registers occurs). While using
the PWM, the CCPRxH register is read-only.
Equation 17-2 is used to calculate the PWM pulse
width.
Equation 17-3 is used t o c alc ul ate the PWM duty cy cl e
ratio.
EQUATION 17-2: PULSE WI DTH
EQUATION 17-3: DUTY CYCLE RATIO
The CCPRxH register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycle. Thi s doubl e
buffering is essential for gl itchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler , to create the 10-bit time ba se. The system
clock is used if the Timer2 pres caler is s et to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (refer to
Figure 17-3).
Note: The Timer2 postscaler (refer to
Section 15.1 “Timer2 Operation”) is not
used in the determination of the PWM
frequency.
PWM Period PR21+4TOSC =
(TM R2 Prescale Value)
Note: TOSC = 1/FOSC
Pulse Width CCPRxL:CCPxCON<5:4>
=
TOSC
(TM R2 Prescale Value)
Note: TOSC = 1/FOSC
Duty Cycle Ratio CCPRxL:CCPxCON<5:4>
4PR2 1+
-----------------------------------------------------------------------=
2010-2011 Microchip Technology Inc. DS41418B-page 137
PIC16(L)F707
17.3.4 PWM RESOLUTI ON
The res olution de termine s th e number of avai lable dut y
cycles for a given period. For example, a 10-bit resolution
will r e sult in 10 24 di sc ret e d ut y c ycl es , wh er eas an 8- b it
resol uti on wi ll re su lt in 2 56 di s cre te du ty c ycl es .
The ma ximum P WM re solut ion i s 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 17-4.
EQUATION 17-4: PWM RESOLUTION
17.3.5 OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state o f the mo dule will no t change. I f the CC Px
pin is dri ving a value , it wil l cont inue to d rive th at valu e.
When the device wakes up, TMR2 wil l continue from it s
previous state.
17.3.6 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any c hanges in the sys tem clock fre-
quency will result in changes to the PWM frequency.
Refer to Section 7.0 “Oscillator Module” for
additional details.
17.3.7 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
17.3.8 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Disable the PWM pi n (CCPx ) outp ut driv er(s) b y
setting the associated TRIS bit(s).
2. Load the PR2 register with the PWM period value.
3. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
4. Load the CCPRxL register and the DCxBx bits of
the CCPxCON register, with the PWM duty cy cle
value.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register. See Note below.
• Configure the T2CKPS bits of the T2CON
register with the Timer2 prescale value.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
Note: If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
Resolution 4PR2 1+log 2log
------------------------------------------ bits=
TABLE 17-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6
TABLE 17-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5
PIC16(L)F707
DS41418B-page 138 2010-2011 Microchip Technology Inc.
6. Enable PWM output pin:
• Wai t until T imer2 o verflows, TM R2IF bit of the
PIR1 registe r is set. See the Note bel ow.
• Enable the PWM pin (CCPx) output driver(s)
by clearing the associated TRIS bit(s).
Note: In order to s end a complete duty cycle and
period on the firs t PWM out put, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
TABLE 17-7: SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111
ANSELC ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0 111- -111 111- -111
APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00
CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
CCPRxL Capture/Compare/PWM Register X Low Byte xxxx xxxx uuuu uuuu
CCPRxH Capture/Compare/PWM Register X High Byte xxxx xxxx uuuu uuuu
PR2 Timer2 Perio d Register 1111 1111 1111 1111
T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TMR2 Timer2 Module Register 0000 0000 0000 0000
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: - = Unimplemented locations, re ad as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
2010-2011 Microchip Technology Inc. DS41418B-page 139
PIC16(L)F707
18.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)
module is a serial I/O communications peripheral. It
contains all the clock generators, shift registers and
data buffers necessary to perform an input or output
serial data transfer independent of device program
execution. The AUSART, also known as a Serial
Communicati ons Interface (SCI), can b e configured as
a full-duplex asynchronous system or half-duplex
synchronous system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These device s typ icall y do n ot have inter nal cl ocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The AUSART m odule includes the follow ing capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-ch arac ter out put buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-du ple x sy nc hron ous master
• Half-du ple x sy nc hron ous slave
• Sleep operation
Block diagrams of the AUSART transmitter and
receiver are shown in Figure 18-1 and Figure 18-2.
FIGURE 18-1: AUSART TRANSMIT BLOCK DIAGRAM
TXIF
TXIE
Interrupt
TXEN
TX9D
MSb LSb
Data Bus
TXREG Register
Transmit Shift Register (TSR)
(8) 0
TX9
TRMT SPEN
TX/CK
Pin Buffer
and Control
8
SPBRG
FOSC ÷ n
n
+ 1 Multiplier x4 x16 x64
SYNC 100
BRGH x10
Baud Rate Generator
•••
PIC16(L)F707
DS41418B-page 140 2010-2011 Microchip Technology Inc.
FIGURE 18-2: AUSART RECEIVE BLOCK DIAGRAM
The operation of the AUSART module is controlled
through two registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
These registers are detailed in Register 18-1 and
Register 18-2, respecti vely.
RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR
FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt
RCIF
RCIE
Data Bus
8
Stop START
(8) 7 1 0
RX9
• • •
SPBRG
FOSC ÷ n
n
+ 1 Multiplier x4 x16 x64
SYNC 100
BRGH x10
Baud Rate Generato r
2010-2011 Microchip Technology Inc. DS41418B-page 141
PIC16(L)F707
18.1 AUSART Asynchronous Mode
The AUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output l evel of that bit wi thout returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eig ht
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit Baud Rate
Generator is used to derive standard baud rate
frequencies from the system oscillator. Refer to
Table 18-5 for examples of baud rate configurations.
The AUSART transmits and receives the LSb first. The
AUSART’s transmitter and receiver are functionally
indepen dent, but share th e sa me dat a format and bau d
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data b it.
18.1.1 AUSART ASYNCHRONOUS
TRANSMITTER
The AUSART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
18.1.1.1 Enabling the Transmitter
The AUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
•TXEN = 1
• SYNC = 0
• SPEN = 1
All other AUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the AUSART. Clearing the SYNC
bit of the TXSTA register configures the AUSART for
asynchronous operation. Setting the SPEN bit of the
RCST A register enables the AUSART and automatically
configures the TX/CK I/O pin as an output.
18.1.1.2 Transmitting Data
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR re gister. If the T SR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then tran sferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bit s
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
18.1.1.3 Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the AUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new char acter ha s been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execut ion. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF fla g bit will be set wheneve r the TXR EG is emp ty,
regardless of the state of TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE i nterrupt en able bi t upon w riting the last charact er
of the transmission to the TXREG.
Note 1: When the SPEN bit is set, the RX/DT I/O
pin is automatically configured as an input,
regardless of the state of the correspond-
ing TRIS bit and whether or not the AUS-
ART receiver is enabled. The RX/DT pin
data can be read via a normal PO RT read
but PORT latch data output is precluded.
2: The corresponding ANSEL bit must be
clear ed for the R X/DT por t pin to en sure
proper AUSART functionality.
3: The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
PIC16(L)F707
DS41418B-page 142 2010-2011 Microchip Technology Inc.
18.1.1.4 TSR Status
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
18.1.1.5 Transmitting 9-Bit Characters
The AUSART supports 9-bit character transmissions.
When the TX9 bit o f the TXSTA regist er is set the AUS-
ART will shift 9 bits out for each character transmitted.
The TX9D bit of the TXSTA register is the ninth, and
Most Sig nific ant, data bit. Wh en tr ansmitti ng 9-bit dat a,
the TX9D data bit must be written before writing the 8
Least Significant bits into the TXREG. All nine bits of
data will be transferred to the TSR shift register imme-
diately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. Refer to Section 18.1.2.7 “Address
Detection” for more information on the Address mode.
18.1.1.6 Asynchronous Transmission Set-up:
1. Initialize the SPBRG register and the BRGH bit to
achieve the desired baud rate (Refer to
Section 18.2 “AUSART Baud Rate Generator
(BRG)”).
2. Enable the asy nch ron ous seri al port by clearin g
the SYNC bit and setting the SPEN bit.
3. If 9-bit tran smis si on is desire d, s et th e TX9 co n-
trol bit. A set nin th data bi t will indicat e that the 8
Least Significant data bits are an address when
the receiver is set for address detection.
4. Enable the transmission by setting the TXEN
contr ol bit . Thi s wi ll c aus e th e TXI F i nte rrup t bi t
to be set.
5. If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
6. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
7. Load 8-bit data into the TXREG register. This
will start the transmission.
FIGURE 18-3: ASYNCHRONOUS TRANSMISSION
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
Word 1 Stop bit
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG Word 1
BRG Output
(Shift Clock)
TX/CK pin
TXIF bit
(Transmit Buffer
Empty Flag)
TRMT bit
(Tran s mit Sh ift
Reg. Empty Flag)
1 TCY
2010-2011 Microchip Technology Inc. DS41418B-page 143
PIC16(L)F707
FIGURE 18-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
18.1.2 AUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 18-2. The dat a is rec eived on th e RX/DT pin and
drives the data recovery block. The dat a recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) op erat es at the bit rat e. When all 8 or 9
bits of the character have been shifted in, they are
immediately transferred to a two character First-In
First-Out (FIFO) memory. The FIFO buffering allows
receptio n of two complete characters and the s t art of a
third cha rac ter be fore software must start servi ci ng th e
AUSART receiver. The FIFO and RSR registers are not
direc tly ac cessible b y s oftwar e. Ac cess to the r e ce ived
data is via the RCREG register.
18.1.2.1 Enabling the Receiver
The AUSART receiver is enabled for asynchronous
operatio n by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other AUSART control bits are assumed to be in
their defaul t st ate .
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the AUSART. Clearing the SYNC bit
of the TXSTA register configures the AUSART for
asynchronous operation. Setting the SPEN bit of the
RCST A register enables the AUSART and automatically
configures the RX/DT I/O pin as an input.
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX/CK pin
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Start bit Stop bit Start bit
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
TXIF bit
(Transmit Buffer
Empty Flag)
TABLE 18-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Valu e on
POR, BOR
Valu e on
all other
Resets
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXREG AUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for asynchronous transmission.
PIC16(L)F707
DS41418B-page 144 2010-2011 Microchip Technology Inc.
18.1.2.2 Receivi ng Data
The receiver data recovery circuit initiates character
receptio n on t he fallin g edge of the first bit. Th e firs t bit,
also known as the Start bit, is always a zero. The data
recover y circ uit co unt s o ne-hal f bit ti me to the cen ter of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recover y circuit c ounts a full bit time to the cente r of the
next bit. The bit is then sampled by a majority detect
circuit and the resulti ng ‘0’ or ‘1’ is shif ted into the RSR.
This repeats until all data bits have been sampled and
shif ted into the RSR. One final bit time is measu red and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
charact er , otherwis e the framing error i s cleared for thi s
character. Refer to Section 18.1.2.4 “Receive
Framing Error” for more information on framing
errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the AUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
18.1.2.3 Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whenever the AUSAR T receiver i s enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt fla g bit is read-o nly, it ca nnot b e set or cl eared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Receive Interrupt Enable bit of the PIE1
register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit of the PIR1 register will be
set when there is an unread character in the FIFO,
regardless of the state of interrupt enable bits.
18.1.2.4 Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indic ates t hat a Stop bit was not seen at the exp ected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represen ts the s ta tus o f the top un read charac ter in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the AUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
18.1.2.5 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun e rror will be genera ted if a th ird charac ter , in it s
entirety, is received before the FIFO is accessed. Whe n
this happens the OERR bit of the RCSTA register is set.
The ch a racter s al re ad y i n the F I FO bu ffer ca n be r e ad
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
setting the AUSART by clearing the SPEN bit of the
RCSTA register.
Note 1: When the SPEN bit is set, the TX/CK I/O
pin is a utomaticall y c on figured as an out-
put, regardless of the state of the corre-
spondi ng TR IS bit an d whethe r or not the
AUSART transmitter is enabled. The
PORT l atch is di sconnected from the out-
put driver so it is not possible to use the
TX/CK pin as a general purpose output.
2: The corresponding ANSEL bit must be
clear ed fo r the RX/DT port pin t o ensu re
proper AUSART functionality.
Note: If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. Refer to
Section 18.1.2.5 “Receive Overrun
Error” for more information on overrun
errors.
Note: If all receive characters in the receive
FIFO hav e framing errors, re peated reads
of the RCREG will not clear the FERR bit.
2010-2011 Microchip Technology Inc. DS41418B-page 145
PIC16(L)F707
18.1.2.6 Receivi ng 9- bit Characte rs
The AUS ART support s 9-bit c haracter rece ption. When
the RX9 bit of the RCSTA register is set the AUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
charact er in the recei ve FIFO. When read ing 9- bit dat a
from the receive FIFO buffer, the RX9D data bit must
be read befo re reading the 8 L east Signifi cant bits fro m
the RCREG.
18.1.2.7 Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit of the PIR1 register. All other characters will be
ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop b it oc cu rs. When use r s oftware de tec t s th e end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
18.1.2.8 Asynchronous Reception Set-up:
1. Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (refer to
Section 18.2 “AUSART Baud Rate Generator
(BRG)”).
2. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
3. If in terrup ts are de sired, set the RCI E bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
5. Enable reception by setting the CREN bit.
6. The RCIF interrupt flag bit of the PIR1 register
will be set when a character is transferred from
the RSR to the receive buffer . An interrupt will be
generated if the RCIE bit of the PIE1 register
was also set.
7. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data b it.
8. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
9. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
18.1.2.9 9-bit Address Detection Mode Set-
up
This mode would typically be used in RS-485 systems.
To set up an asynchronous reception with address
detect enable:
1. Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (refer to
Section 18.2 “AUSART Baud Rate Generator
(BRG)”).
2. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
3. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4. Enable 9-bit reception by setting the RX9 bit.
5. Enable a ddress d etection by setting the ADDEN
bit.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit of the PIR1 register
will be set whe n a chara cter with t he nin th bit s et
is transferred from the RSR to the receive buffer .
An interrupt will be generated if the RCIE inter-
rupt enabl e bit of th e PIE1 regi ster w as also se t.
8. Read th e RC STA regist er to ge t t he erro r fla gs.
The ninth data bit will always be set.
9. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
PIC16(L)F707
DS41418B-page 146 2010-2011 Microchip Technology Inc.
FIGURE 18-5: ASYNCHRONOUS RECEPTION
Start
bit bit 7/8
bit 1bit 0 bi t 7/8 bit 0Stop
bit
Start
bit Start
bit
bit 7/8 Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
Stop
bit
Note: This timin g diagram sho ws three words appearing on the RX input. The RCREG (receive buffer) is r ead after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Valu e on
all other
Resets
ANSELC ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0 111- -111 111- -111
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCREG AUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for asynchronous re ception.
2010-2011 Microchip Technology Inc. DS41418B-page 147
PIC16(L)F707
REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: AUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Read as ‘0’
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Synchronous mode.
PIC16(L)F707
DS41418B-page 148 2010-2011 Microchip Technology Inc.
REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit(1)
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables si ngle receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronou s mod e – Slave:
Don’t care
bit 4 CREN: Conti nuous Receive Enab le bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disable s continuou s receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
Synchronous mode:
Must be set to ‘0’
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received D ata
This can be address/data bit or a parity bit and must be calculated by user firmware.
Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure
TRISx = 1.
2010-2011 Microchip Technology Inc. DS41418B-page 149
PIC16(L)F707
18.2 AUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit timer that
is dedicated to the support of both the asynchronous
and synchronous AUSART operation.
The SPBRG register determines the period of the free
running baud rate timer. In Asynchronous mode the
multiplier of the baud rate period is determined by the
BRGH bit of the TXSTA register. In Synchronous mode,
the BRGH bit is ignored.
Table 18-3 contains the formulas for determining the
baud rate . Example 18-1 provides a sam ple calcul ation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
Asynchronous modes have been computed for your
convenience and are shown in Table 18-5. It may be
advant ageous to use the high baud rate (BRG H = 1), to
reduce the baud rate error.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures that
the BRG does not wait for a timer overflow before
outputting the new baud rate.
EXAMPLE 18-1: CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of
9600, and Asynchronous m ode with SY NC = 0 and BRGH
= 0 (as seen in Table 18-5):
Solving for SPBRG:
SPBRG FOSC
64 De sire d Baud Rate
---------------------------------------------------------
1–=
Desired Ba ud R ate FOSC
64 SPBRG 1+
---------------------------------------=
16000000
64 9600
------------------------
1–=
25.04225==
Actual B aud Rate 16000000
64 25 1+
---------------------------=
9615=
Error Actual Baud R ate Desired Baud R ate –
Desired Baud Rat e
--------------------------------------------------------------------------------------------------
100=
9615 9600–
9600
------------------------------
100 0.16%==
%
TABLE 18-3: BAUD RATE FORMULAS
Configuration Bits AUSART Mode Baud Rate Formula
SYNC BRGH
00 Asynchronous FOSC/[64 (n+1)]
01 Asynchronous FOSC/[16 (n+1)]
1x Synchronous FOSC/[4 (n+1)]
Legend: x = Don’t care, n = value of SPBRG register
TABLE 18-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Value on
all other
Resets
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
PIC16(L)F707
DS41418B-page 150 2010-2011 Microchip Technology Inc.
TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
SYNC = 0, BRGH = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.0000 MHz FOSC = 11.0592 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 — — — — — — —— — —— —
1200 1221 1.73 255 1200 0.00 239 1201 0.08 207 1200 0.00 143
2400 2404 0.16 129 2400 0.00 119 2403 0.16 103 2400 0.00 71
9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17
10417 10417 0.00 29 10286 -1.26 27 10416 -0.01 23 10165 -2.42 16
19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8
57.6k — — — 57.60k 0.00 7—— —
57.60k 0.00 2
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.0000 MHz FOSC = 11.0592 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 —— — —— — —— — —— —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — —— —
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.82k -1.36 21 57.60k 0.00 19 58.8k 2.12 16 57.60k 0.00 11
115.2k 113.64k -1.36 10 115.2k 0.00 9 — — — 115.2k 0.00 5
2010-2011 Microchip Technology Inc. DS41418B-page 151
PIC16(L)F707
BAUD
RATE
SYNC = 0, BRGH = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 —— — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES
PIC16(L)F707
DS41418B-page 152 2010-2011 Microchip Technology Inc.
18.3 AUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary cir-
cuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and trans-
mit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The AUSART can operate as either a master or slave
device.
Start and Stop bits are not used in synchronous
transmissions.
18.3.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the AUSART
for Synchronous Master operation:
• SYNC = 1
• CSRC = 1
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the de vi c e f or sy n ch ronous op era t i on . Se tt ing the C SR C
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCST A
regis ter ensures th at the dev ic e i s in th e Tra ns m it mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
AUSART.
18.3.1.1 Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config-
ured as a master transmit s the c lock on the TX/CK lin e.
The TX/CK pin output driver is automatically enabled
when the AUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the le ading edg e to ensure they are v alid at the trail-
ing edge of each clock. One clock cycle is generated
for each data bit. Only as many clock cycles are
generated as there are data bits.
18.3.1.2 Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are
automat ically e nabled w hen the AUSAR T is configure d
for synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG reg is ter. If the TSR st ill co nt a ins al l or part of a
previous character, the new character data is held in
the TXREG until the last bit of the previous character
has been tran smitted. If this is the first ch aracter, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately trans-
ferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TXREG.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
18.3.1.3 Synchronous Master Transmission
Set-up:
1. Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (refer to
Section 18.2 “AUSART Baud Rate Generator
(BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Disable Receive mode by clearing bits SREN
and CREN.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. S tart transm ission by loading data to the TXREG
register.
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
2010-2011 Microchip Technology Inc. DS41418B-page 153
PIC16(L)F707
FIGURE 18-6: SYNCHRONOUS TRANSMISSION
FIGURE 18-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 7
Word 1 bit 2 bit 0 bit 1 bit 7
RX/DT
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit ‘1’ ‘1’
Word 2
TRMT b it
Write Word 1 Write Word 2
Note: Synchronous M ast er mode, SPBRG = 0, continuous transmission of two 8-bit words.
pin
TX/CK pin
RX/DT pin
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bi t
TABLE 18-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Valu e on
all other
Resets
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXREG AUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous master transmission.
PIC16(L)F707
DS41418B-page 154 2010-2011 Microchip Technology Inc.
18.3.1.4 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
AUSAR T is config ured fo r synch ronous master receiv e
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the com pletio n of one c har acter. When CREN i s set,
clocks are continuously generated until CREN is
cleared . If CREN is cleared in the middle of a c haracter
the CK clo ck sto p s imm ed iat ely and t he p a rtia l charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cl eared at the co mpletion of the first cha racter
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
receive d into the RSR, t he RCIF bit of the PIR1 reg ister
is set and the character is automatically transferred to
the two character receive FIFO. The Least Significant
eight bits of the top character in the receive FIFO are
available in RCREG. The RCIF bit remains set as long
as there are un-read characters in the receive FIFO.
18.3.1.5 Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device
confi g ure d a s a sl av e re ce iv es the cl o ck o n the TX/ CK
line. The TX/CK pin output driver is automatically
disabled when the device is configured for
synch ronous slave transmit or recei ve operation. Serial
data bits change on the leading edge to e nsure they are
valid at the trailing edge of each clock. One data bit is
transferred for each clock cycle. Only as many clock
cycles should be received as there are data bits.
18.3.1.6 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be genera ted if a th ird charac ter , in it s
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be recei ved until the erro r is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register.
18.3.1.7 Receiving 9-bit Characters
The AUSAR T support s 9-bit chara cter receptio n. When
the RX9 bit of the RCSTA register is set, the AUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
charact er i n t he rec eiv e FIFO . Whe n r ead ing 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read befo re reading the 8 Le ast Signifi cant bit s from
the RCREG.
Address detection in Synchronous modes is not
supported, therefore the ADDEN bit of the RCSTA
register must be cleare d.
18.3.1.8 Synchronous Master Reception
Set-up:
1. Initialize the SPBRG register for the ap prop ria te
baud rate. Set or clear the BRGH bit, as
required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set bit RX9.
6. Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
8. Interrupt f lag bit RCIF of th e PIR1 register w ill be
set when reception of a character is complete.
An interrupt will be generated if the RCIE inter-
rupt enable bit of the PIE1 register was set.
9. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit, which
resets the AUSART.
2010-2011 Microchip Technology Inc. DS41418B-page 155
PIC16(L)F707
FIGURE 18-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
pin
TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Valu e on
all other
Resets
ANSELC ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0 111- -111 111- -111
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCREG AUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception.
PIC16(L)F707
DS41418B-page 156 2010-2011 Microchip Technology Inc.
18.3.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the AUSART
for synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TX STA reg ister configur es the device as a slave.
Clearing the SREN and CREN bits of the RCST A register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
AUSART.
18.3.2.1 AUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes are identical (refer to Section 18.3.1.2
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The second word will rem ain in TXRE G registe r .
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
5. If the PEIE and TXIE bits are set, the interrupt
will wa ke the dev ice from Sleep and e xecute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
18.3.2.2 Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the CREN and SREN bits.
3. If using interrup ts, ensu re that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
4. If 9-bit transmission is desired, set the TX9 bit.
5. Enable transmission by setting the TXEN bit.
6. Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Valu e on
all other
Resets
ANSELC ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0 111- -111 111- -111
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXREG AUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave transmission.
2010-2011 Microchip Technology Inc. DS41418B-page 157
PIC16(L)F707
18.3.2.3 AUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 18.3.1.4 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
nev er Idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is rec eived, th e RSR regist er will tran sfer the da ta
to the RCREG register. If the RCIE interrupt enable bit
of the PIE1 register is set, the interrupt generated will
wake the device from Sleep and execute the next
instruction. If the GIE bit is also set, the program will
branch to the interrupt vector.
18.3.2.4 Synchronous Slave Reception Set-
up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
3. If 9-bit reception is desired, set the RX9 bit.
4. Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
5. Set the CREN bit to enable reception.
6. The RCIF bit of the PIR1 register will be set
when re ce pt io n i s co mp le te . An i n t err u pt wil l be
generated if the RCIE bit of the PIE1 register
was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
8. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Valu e on
all other
Resets
ANSELC ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0 111- -111 111- -111
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCREG AUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.
PIC16(L)F707
DS41418B-page 158 2010-2011 Microchip Technology Inc.
18.4 AUSART Operation During Sleep
The AUSAR T will remain active during Sleep only in th e
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the
necessary signals to run the transmit or receive shift
registers during Sleep.
Synchronous Slave mode uses an exte rnally generated
clock to r un the transmit and receive shift registers.
18.4.1 SYNCHRONOUS RECEIVE DURING
SLEEP
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA control registers must be
configured for synchronous slave reception (refer
to Section 18.3.2.4 “Synchronous Slave
Reception Set-up:”).
• If interrupts are desired, set the RCIE bit of the
PIE 1 regi ster and the PEI E bit of the INTCON
register.
• The RCIF interrupt flag must be cleared by read-
ing RCREG to unload any pending characters in
the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the da ta word has b een c om ple tel y
clocked in by the external device, the RCIF interrupt
flag bi t of th e PIR1 regis ter will be s et. The reb y, waking
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address
0004h will be called.
18.4.2 SYNCHRONOUS TRANSMIT
DURING SLEEP
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA control registers must be
configured for synchronous slave transmission
(refer to Section 18.3.2.2 “Synchronous Slave
Transmission Set-up:”).
• The T XIF inte rrupt flag mu st be clea red by w rit ing
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
• If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON
register.
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set then the Interrupt
Service Routine at address 0004h will be called.
2010-2011 Microchip Technology Inc. DS41418B-page 159
PIC16(L)F707
19.0 SSP MODULE OVERVIEW
The Synchronous Serial Port (SSP) module is a serial
inter fac e u sef ul for com m uni ca tin g with other pe ripher-
als or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play d riv ers, A/D converters, et c. The SSP m odu le ca n
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
19.1 SPI Mode
The SPI m ode allow s 8 bits o f data to be sync hronously
transmitted and received, simultaneously. The SSP
module can be operated in one of two SPI modes:
•Master mode
• Slave mode
SPI is a full-duplex protocol, with all communication
being bidirectional and initiated by a master device. All
clocking is provided by the master device and all bits
are transmitted, MSb first. Care must be taken to
ensure that all devices on the SPI bus are setup to
allow all controllers to send and receive data at the
same time.
A typical SPI connection between microcontroller
devices is shown in Figure 19-1. Addressing of more
than one slave device is accomplished via multiple
hardware slave select lines. External hardware and
additional I/O pins must be used to support multiple
slave select addressing. This prevents extra overhead
in software for communication.
For SPI communication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Ser ial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
FIGURE 19-1: TYPICAL SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
Processor 1
SCK
SPI Master SSPM<3:0> = 00xx
Serial Input Buf fe r
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
Processor 2
SCK
SPI Slave SSPM<3:0> = 010x
Serial Clock
SS
Slave Select
General I/O (optional)
PIC16(L)F707
DS41418B-page 160 2010-2011 Microchip Technology Inc.
FIGURE 19-2: SPI MODE BLOCK
DIAGRAM 19.1.1 MASTER MODE
In Master mode, data transfer can be initiated at any
time beca use the m aster co ntrols the SCK line. M aster
mode determines when the slave (Figure 19-1,
Processor 2) transm its dat a via control of the SCK l ine.
19.1.1. 1 Master Mode Operat ion
The SSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
register shifts the data in and out of the device, MSb
first. The SSPBUF regist er hold s the dat a tha t is writ ten
out of the master until the received data is ready . Once
the eight bits of data have been received, the byte is
moved to the SSPBUF register. The Buffer Full Status
bit, BF of the SSPSTAT register, and the SSP Interrupt
Flag bi t, SSPI F of the PIR1 reg is te r, are then set .
Any write to the SSPBUF register during transmission/
recep tion of dat a wil l be i gno red and t he W rit e Co lli sio n
Detect bit, WCOL of the SSPCON register, will be set.
User software must clear the WCOL bit so that it can be
determined if the following write(s) to the SSPBUF
register compl eted successfully.
When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte of d ata is writte n to the S SPBUF. The BF bit of th e
SSPSTAT register is set when SSPBUF has been
loaded with the received data (transmission is
complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. The SSP interrupt may be used to
determine when the transmission/reception is
complete and the SSPBUF must be read and/or
written. If interrupts are not used, then software polling
can be done to ensure that a write collision does not
occur. Example 19-1 shows the loading of the SSPBUF
(SSPSR) for data transmission.
19.1.1.2 Enabling Master I/O
To enable the serial port, the SSPEN bit of the
SSPCON register, must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON register and then set the SSPEN bit. If a
Master mo de of ope r atio n is se lec te d in the S SPM bits
of the SSPCON register, the SDI, SDO and SCK pins
will be assigned as serial port pins.
For thes e pins to f unc tio n as s eri al p ort pi ns, they m us t
have their corresponding data direction bits set or
cleared in the associated TRIS register as follows:
• SDI configured as input
• SDO configured as output
• SCK configured as output
Read Write
Internal
Data Bus
SDI
SDO
RA5/SS
SCK
SSPSR Reg
SSPBUF Reg
SSPM<3:0>
bit 0 Shift
Clock
SS
Control
Enable
Edge
Select
Clock Select
TMR2
FOSC
Prescaler
4, 16, 64
TRISx
2
4
RA0/SS SSSEL
Output
2
Edge
Select
bit 7
Note: The SSPSR is not directly readable or
writable and can only be accessed by
addressing the SSPBUF register.
2010-2011 Microchip Technology Inc. DS41418B-page 161
PIC16(L)F707
19.1.1.3 Master Mode Setup
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is loaded with a byte
value. If the master is only going to receive, SDO output
coul d b e disabl ed (p rog r a m me d an d u se d as an input ) .
The SSPSR register will continue to shift in the signal
present on the SDI pin at the programmed clo ck rate.
When initializing SPI Master mode operation, several
options need to be specified. This is accomplished by
programming the appropriate control bits in the
SSPCON and SSPSTAT registers. These control bits
allow the following to be specified:
• SCK as clock output
• Idle sta te of SCK (CKP bit)
• Data input sample phase (SMP bit)
• Output data on rising/falling edge of SCK (CKE bit)
• Clock bit rate
In Master mode, the SPI clock rate (bit rate) is user
selectable to be one of the following:
•F
OSC/4 (or TCY)
•F
OSC/16 (or 4 TCY)
•FOSC/64 (or 16 TCY)
• (Timer2 out put)/2
This allows a maximum data rate of 5 Mbps
(at FOSC =20MHz).
Figure 19-3 shows the waveforms for Master mode.
The clock polarity is selected by appropri ately program-
ming the CKP bit of the SSPCON register. When the
CKE bit is set, the SDO data is valid before there is a
clock edge on SCK. The sample time of the input data
is shown based on the state of the SMP bit and can
occur at the middle or end of the data output time. The
time when the SSPBUF is loaded with the received
data is shown.
19.1.1.4 Sleep in Master Mode
In Master mode, all module clocks are halted and the
transmission/receptio n will remain in their current st ate,
paused, until the device wakes from Sleep. After the
devic e wake s up from Sleep, t he modul e will co ntin ue
to transmit/receive data.
PIC16(L)F707
DS41418B-page 162 2010-2011 Microchip Technology Inc.
FIGURE 19-3: SPI MASTER MODE WAVEFORM
EXAMPLE 19-1: LOADING THE SSPBUF (SSPSR) REGISTER
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7 bit 0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
BANKSEL SSPSTAT ;
LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)?
GOTO LOOP ;No
BANKSEL SSPBUF ;
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
2010-2011 Microchip Technology Inc. DS41418B-page 163
PIC16(L)F707
19.1.2 SLAVE MODE
For any SPI device acting as a slave, the data is
transmitted and received as external clock pulses
appear on the SCK pin. This external clock must meet
the minimum high and low times as specified in the
electrical specifications.
19.1.2.1 Slave Mode Operation
The SSP consists of a transmit/receive shift register
(SSPSR) and a buf fer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was writ ten to the SSPSR
until the received data is ready.
The slave has no control as to when data will be
clocked in or out of the device. All data that is to be
transmitted, to a master or another slave, must be
loaded into the SSPBUF register before the first clock
pulse is received.
Once eight bits of data have been received:
• Received byte is moved to the SSPBUF register
• BF bit of the SSPSTAT register is set
• SSPIF bit of the PIR1 register is set
Any write to the SSPBUF register during transmission/
receptio n of dat a will be ignored and the W rite Colli sion
Detect bit, WCOL of the SSPCON register, will be set.
User software m ust clear t he WCOL bit so that it can be
determined if the following write(s) to the SSPBUF
regi ster completed successfully.
The user’s firmware must read SSPBUF, clearing the
BF flag, or the SSPOV bit of the SSPCON register will
be set with the reception of the next byte and
communication will be disabled.
A SPI module tran smit s and rece ives at the sa me time,
occasionally causing dummy data to be transmitted/
received. It is up to the user to determine which data is
to be used and what can be discarded.
19.1.2.2 Enabling Slave I/O
To enable the serial port, the SSPEN bit of the
SSPCON register must be set. If a Slave mode of
operatio n is selec ted i n the SSPM bits of the SSPCON
register, the SDI, SDO and SCK pins will be assigned
as serial port pins.
For thes e pins to f unc tio n as s eri al p ort pin s, th ey m us t
have their corresponding data direction bits set or
cleared in the associated TRIS register as follows:
• SDI configured as input
• SDO configured as output
• SCK configured as input
Optionally, a fourth pin, Slave Select (SS) may be used
in Slave mode. Slave Select may be configured to
operate on one of the following pins via the SSSEL bit in
the APFCON register.
•RA5/AN4/SS
•RA0/AN0/SS
Upon selection of a Slave Select pin, the appropriate
bits must be set in the ANSELA and TRISA registers.
Slave Select must be set as an input by setting the
corresponding bit in TRISA, and digital I/O must be
enabled on the SS pin by clearing the corresponding bit
of the ANSELA register.
19.1.2.3 Slave Mode Setup
When initializing the SSP module to SPI Slave mode,
compati bility must be ensure d with the ma ster de vice.
This is done by programming the appropriate control
bits of the SSPCON and SSPSTAT registers. These
control bits allow the fo llow ing to be specified:
• SCK as cl ock input
• Idle state of SCK (CKP bit)
• Data input sample phase (SMP bit)
• Output data on rising/falling edge of SCK (CKE bit)
Figure 19-4 and Figure 19-5 show ex ample wav eforms
of Slave mode operation.
PIC16(L)F707
DS41418B-page 164 2010-2011 Microchip Technology Inc.
FIGURE 19-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
2010-2011 Microchip Technology Inc. DS41418B-page 165
PIC16(L)F707
19.1.2.4 Slave Select Operation
The SS pin allows Synchronous Slave mode operation.
The SPI must be in Slave mode with SS pin control
enabled (SSPM<3:0> = 0100). The associated TRIS bit
for the SS pin must be set, making SS an input.
In Slave Select mode, when:
•SS
= 0, The device operates as s pecified in
Section 19.1.2 “Slave Mode”.
•SS
= 1, The SPI module is held in Reset and the
SDO pin will be tri-stated.
When the SPI m od ul e re sets, the bi t c oun ter i s cl eare d
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit. Figure 19-6
shows the timing waveform for such a synchronization
event.
19.1.2.5 Sleep in Slave Mode
While in Sleep mode, the slave can transmit/receive
data. The SPI Transmit/Recei ve Sh if t registe r o pe r ate s
asynchronously to the device on the externally supplied
clock source. This allows the device to be placed in
Sleep mode and data to be shifted into the SPI Trans-
mit/Receive Shift register. When all 8 bits have been
received, the SSP interrupt flag bit will be set and if
enabled, will wake the device from Sleep.
FIGURE 19-6: SLAVE SELECT SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPM<3:0> = 0100),
the SPI module will reset if the SS pin is
driven high.
2: If the SPI is us ed in Slave mode w ith CKE
set, the SS pin control must be enabled.
Note: SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7 bit 0
SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.
PIC16(L)F707
DS41418B-page 166 2010-2011 Microchip Technology Inc.
REGISTER 19-1: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of
overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read
the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the over-
flow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register.
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins(1)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity S elect bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
Note 1: When enabled, these pins must be properly configured as input or output.
2010-2011 Microchip Technology Inc. DS41418B-page 167
PIC16(L)F707
REGISTER 19-2: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
bit 6 CKE: SPI Clock Edge Select bit
SPI mode, CKP = 0:
1 = Data stable on rising edge of SCK
0 = Data stable on falling edge of SCK
SPI mode, CKP = 1:
1 = Data stable on falling edge of SCK
0 = Data stable on rising edge of SCK
bit 5 D/A: Data/Addr ess bit
Used in I2C mode only.
bit 4 P: Stop bit
Used in I2C mode only.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read /W ri te Information bit
Used in I2C mode only.
bit 1 UA: Update Address bit
Used in I2C mode only.
bit 0 BF: Buffer Full Status bit
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
PIC16(L)F707
DS41418B-page 168 2010-2011 Microchip Technology Inc.
TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Value on all
othe r Resets
ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111
APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PR2 Timer2 Period Register 1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Tr ansmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
2010-2011 Microchip Technology Inc. DS41418B-page 169
PIC16(L)F707
19.2 I2C Mode
The SSP module, in I2C mode, implements all slave
functions, except general call support. It provides
inter rupts on S ta rt and S top bit s in hardware to fac ilitate
firmwa re im ple me nt ations of the mast er f unctions. The
SSP module implements the I2C Standard mode
specifications:
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
• Start and Stop bit interrupts enabled to support
firmware Master mode
•Address masking
Two pins are used for dat a tra nsfer; th e SC L pi n (cl oc k
line) and the SDA pin (data line). The user must
configure the two pin’s data direction bits as inputs in
the appropriate TRIS register. Upon enabling I2C
mode, the I2C slew rate limiters in the I/O pads are
controll ed by th e SMP bit of the SSPSTAT register. The
SSP module functions are enabled by setting the
SSPEN bit of the SSPCON register.
Data is sampled on the rising edge and shifted out on
the fallin g edge of the cloc k. This ensu res that the SDA
signal is va lid dur ing the SCL hi gh tim e. The SC L cl ock
input must have minimu m high and low times for proper
operation. Refer to Section 25.0 “Electrical
Specifications”.
FIGURE 19-7: I2C™ MODE BLOCK
DIAGRAM
FIGURE 19-8: TYPICAL I2C™
CONNECTIONS
The SSP module has six registers for I2C operation.
They are:
• SSP Control (SSPCON) register
• SSP Status (SSPSTAT) register
• Serial Receive/Transmit Buffer (SSPBUF) register
• SSP Shift Register (SSPSR), not directly
accessible
• SSP Address (SSPADD) register
• SSP Address Mask (SSPMSK) register
19.2.1 HARDWARE SETUP
Selection of I2C mode, with the SSPEN bit of the
SSPCON register set, fo rces th e SCL an d SDA pi ns to
be open d rain, p rovided th ese pins are programme d as
inputs by setting the appropriate TRISC bits. The SSP
module will override the input state with the o utput data,
when required, such as for Acknowledge and slave-
transmitter sequences.
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
Start and
Stop bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
SCL
SDA
Shift
Clock
MSb LSb
SSPMSK Reg
Note: Pull-up resistors must be provided
externally to the SCL and SDA pins for
proper operation of the I2C module.
Slave 1
Master
SDA
SCL
VDD VDD
SDA
SCL
Slave 2
SDA
SCL
(optional)
PIC16(L)F707
DS41418B-page 170 2010-2011 Microchip Technology Inc.
19.2.2 START AND STOP CONDITIONS
During times of no data transfer (Idle time), both the
clock l ine (SCL ) and th e dat a line (SDA) are pulled high
through external pull-up resistors. The Start and Stop
conditions determine the start and stop of data trans-
missi on. Th e Start condition is d efi ned as a h igh -to-low
transition of the SDA line while SCL is high. The Stop
condition is defined as a low-to-high transition of the
SDA line while SCL is high.
Figure 19-9 shows the Start and Stop conditions. A
master device generates these conditions for starting
and terminating data transfer. Due to the definition of
the S t art and S top condit ions, when dat a is being trans-
mitted, the SDA line can only change state when the
SCL line is low.
FIGURE 19-9: S TART AND STOP CONDITIONS
19.2.3 ACKNOWLEDGE
After the valid reception of an addr ess or data byte, the
hardware automatically will generate the Acknowledge
(ACK) pulse and load the SSPBUF register with the
received value currently in the SSPSR register. There
are certain conditions that will cause the SSP module
not to generate this ACK pulse. They includ e any or all
of the following:
• The Buffer Full bit, BF of the SSPSTAT register,
was set before the transfer was received.
• The SSP Overflow bit, SSPOV of the SSPCON
register, was set be fore the tran sfer was recei ved.
• The SSP Module is being operated in Firmware
Master mode.
In such a case, th e SSPSR regi ster value is no t loade d
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. Table 19-2 shows the results of when a data
transfer byte is receiv ed, given the statu s of bits BF and
SSPOV. Flag bit BF is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
SDA
SCL P
Stop
Condition
S
Start
Condition
Change of
Data Allowed
Change of
Data Allowed
TABLE 19-2: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received SSPSR SSPBUF Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
00 Yes Yes Yes
10 No No Yes
11 No No Yes
0 1 No No Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
2010-2011 Microchip Technology Inc. DS41418B-page 171
PIC16(L)F707
19.2.4 ADDRESSING
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register . All incom-
ing bits are sampled with the rising edge of the clock
line (SCL).
19.2.4.1 7-bit Addressing
In 7-bit Addressing mode (Figure 19-10), the value of
register SSPSR<7:1> is compared to the value of
register SSPADD<7:1>. The address is compared on
the falling edge of the eighth clock (SCL) pulse. If the
addresses match, and the BF and SSPOV bits are
clear, the following events occur:
• The SSPSR register value is loaded into the
SSPBUF register.
• The BF bit is set.
•An ACK
pulse is generated.
• SSP interrupt flag bit, SSPIF of the PIR1 register,
is set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
19.2.4.2 10-bit Addressing
In 10-bit Address mode, two address bytes need to be
receive d by the slave (Figure 19-11). The fi ve Most Sig-
nifican t bits (MSbs ) of the fi rst a ddre ss byt e sp ec ify if it
is a 10-bi t addres s. The R/W bi t of the SSPSTAT regis-
ter mus t s pec ify a w rite so the s lav e dev ic e w i ll rec eiv e
the seco nd addre ss byte. Fo r a 10 -bit add ress, th e first
byt e would equ al ‘1111 0 A9 A8 0’, where A9 and
A8 are the two MSbs of the address.
The sequ ence of e vents for 10-bit a ddress is as follows
for reception:
1. Load SSP ADD register with high byte of address.
2. Receive first (high) byte of address (bits SSPIF,
BF and UA of the SSPSTAT register are set).
3. Read the SSPBUF register (clears bit BF).
4. Clear the SSPIF flag bit.
5. Update the SSPADD register with second (low)
byte of address (clears UA bit and releases the
SCL line).
6. Receive low b yte of addr ess (bits SSPIF, BF an d
UA are set).
7. Update the SSPADD register with the high byte
of address. If match releases SCL line, this will
clear bit UA.
8. Read the SSPBUF register (clears bit BF).
9. Clear flag bit SSPIF.
If data is requested by the master, once the slave has
been addressed:
1. Receive repeated Start condition.
2. Receive repeat of high byte address with R/W = 1,
indicating a read.
3. BF bit is set an d the CKP bit is cleared, st opping
SCL and indicating a read request.
4. SSPBUF is written, setting BF, with the data to
send to the master device.
5. CKP is set in software, releasing the SCL line.
19.2.4. 3 Address Mask ing
The Address Masking register (SSPMSK) is only
accessible while the SSPM bits of the SSPCON
register are set to ‘1001’. In th is r egi ste r, the user can
select which bits of a received address the hardware
will compare when determining an address match. Any
bit that is set to a zero in the SSPMSK register, the
corresponding bit in the received address byte and
SSPADD register are ignored when determining an
address match. By default, the register is set to all
ones, requiring a complete match of a 7-bit address or
the lower eight bits of a 10-bit address.
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DS41418B-page 172 2010-2011 Microchip Technology Inc.
19.2.5 RECEPTION
When th e R/W bit of the rece ived addres s byte is clear,
the master will write data to the slave. If an address
match occurs, the received address is loaded into the
SSPBUF register. An address byte overflow will occur
if that loaded address is not read from the SSPBUF
before the next complete byte is received.
An SSP interrupt is generated for each data transfer byte.
The BF, R/ W and D/A bits of the SSPSTAT register are
used to determine the st atus of th e last received b yt e.
FIGURE 19-10 : I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
765
D0
D1
D2
D3
D4
D5D6
D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678912
34
Bus Master
sends Stop
condition
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4D5D6
D7
ACK
R/W = 0
Receiving Address
SSPIF
BF
SSPOV
ACK
ACK is not sent.
2010-2011 Microchip Technology Inc. DS41418B-page 173
PIC16(L)F707
FIGURE 19-11: I2C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
SSPIF
BF
Receive Data Byte
R/W
Receive Fi rst Byte of Address
Cleared in softwa re
Cleared in software
Receive Second Byte of Address
Cleared by har dwar e
when SSPADD is updated
with low byte of address
UA
Clock is held low until
update of S SPADD has
taken place
UA is set indicating
that the SSPADD needs to
be updated
UA is set indicating
that SSPA DD needs to
be updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written
with contents of SSPSR Dummy read of SSPBUF
to clear BF flag
CKP
Receive Data Byte
Bus master
sends Stop
condition
ACK
Cleared in software Cleared in software
SSPOV
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Clock is held low until
update of SSPADD has
taken place
SDA
SCL S123456789 123456789 12345 789P
11110A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
ACK
ACK D2
6
ACK
12345789
D7 D6 D5 D4 D3 D1 D0D2
6
ACK
0
PIC16(L)F707
DS41418B-page 174 2010-2011 Microchip Technology Inc.
19.2.6 TRANSMISSION
When the R/W bit of the received address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set and the slave will respond to
the master by reading out data. After the address match,
an ACK pulse is generated by the slave ha rdware and
the SCL pin is held low (clock is automatically stretched)
until the slave is ready to respond. See Section 19.2.7
“Clock Stretching”. The data the slave will transmit
must be loaded into the SSPBUF register, which sets
the BF bit. The SCL li ne is released by setting the CKP
bit of the SSPCON register .
An SSP interru pt is generated for e ach transferred da ta
byte. The SSPIF flag bit of the PIR1 regi ster initiates an
SSP interrupt, and must be cleared by software before
the nex t byte is transmi tted. The BF bi t of the SSPSTA T
register is cleared on the falling edge of the 8th
received clock pulse. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
Following the 8th falling clo ck edge, control of the SDA
line is released back to the master so that the master
can acknowl edge or not acknow ledge the response. If
the master sends a not acknowledge, the slave’s
transmission is complete and the slave must monitor for
the next Start condition. If the master acknowledges,
control of the bus is returned to the slave to transmit
another byte of data. Just as with the previous byte, the
clock is stretched by the slave, data must be loaded into
the SSPBUF and CKP must be set to release the clock
line (S CL ).
FIGURE 19-12 : I2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF
BF
CKP
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting DataR/WReceiving Address
123456789 123456789 P
Cleared in software
Set bit after writing to SSPBUF
SData in
sampled SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written to
before the CKP bit can be set)
Dummy read of SSPBUF
to clear BF flag SSPBUF is written in software From SSP Interrupt
Servi ce Routine
2010-2011 Microchip Technology Inc. DS41418B-page 175
PIC16(L)F707
FIGURE 19-13 : I2C™ SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF
S123456789 1 23456789 12345 789 P
11110A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 11110 A8
R/W = 1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus Master
sends S top
condition
A9
6
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updat ed with low
byte of address.
UA
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
Cleared in software
Completion of
clears BF flag
CKP
CKP is set in software, initiates transmission
CKP is automatically cleared in hardware holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
Bus Master
sends Restarts
condition
Dummy read of SSPBUF
to clear BF flag
PIC16(L)F707
DS41418B-page 176 2010-2011 Microchip Technology Inc.
19.2.7 CLOCK STRETCHING
During any SCL low phase, any device on the I2C bus
may hold the SCL line low and delay, or pause, the
transmission of dat a. This “stretching” of a transmission
allows devices to slow down communication on the
bus. The SCL line must be constantly sampled by the
master to ensure that all devices on the bus have
released SCL for more data.
Stretching usually occurs after an ACK bit of a
transmi ssio n, d el ayi ng the fi rst bit of th e n ex t b yte . Th e
SSP module hardware automatically stretches for two
conditions:
• After a 10-bit address byte is received (update
SSPADD register)
• Anytime the CKP bit of the SSPCON register is
cleared by hardware
The module will hold SCL low until the CKP bit is set.
This all ows the use r slave so ftware to updat e SSPBUF
with data that may not be readily available. In 10-bit
addressing modes, the SSPADD register must be
updated after receiving the first and second address
bytes. The SSP module will hold the SCL line low until
the SSPADD has a byte written to it. The UA bit of the
SSPSTAT register will be set, along with SSPIF,
indicating an address update is needed.
19.2.8 FIRMWARE MASTER MODE
Master mode of operation is supported in firmware
using interrupt generation on the detection of the Start
and Stop conditions. The Stop (P) and Start (S) bits of
the SSPSTAT register are cleared from a Reset or
when the SSP module is disabled (SSPEN cleared).
The Stop (P) and Start (S) bits will toggle based on the
Start and Stop conditions. Control of the I2C bus may
be t aken when the P bit i s set or the bus is Idl e and both
the S and P bits are clear.
In Firmware Master mode, the SCL and SDA lines are
manipulated by s etting/clearing the correspo nding TRIS
bit(s). The output level is always low, irrespective of the
value(s) in the corresponding PORT register bit(s).
When transmitting a ‘1’ , the TRIS bit must be set (input)
and a ‘0’, the TRIS bit must be clear (output).
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt will occur if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Firmware Master mode of operation can be done with
either the Slave mode Idle (SSPM<3:0> = 1011), or
with either of the Slave modes in which interrupts are
enabled. When both master and slave functionality is
enabled, the software needs to differentiate the
source(s) of the interrupt.
Refer to Application Note AN554, “Software
Implementation of I2C™ Bus Master” (DS00554) for more
information.
19.2.9 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allow the
determin ation of when the bu s is free. The S top (P) an d
S tart (S) bits are cl eared from a Reset or when the SSP
module is disabled. The Stop (P) and Start (S) bits will
toggle based on the Start and Stop conditions. Control
of the I2C bus may be taken when the P bit of the
SSPSTAT register is set or when the bus is Idle, and
both the S and P bits are clear. When the bus is busy,
enabling the SSP interrupt will generate the interrupt
when the Stop condition occurs.
In Multi-Master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRIS bits). There are two stages where
this arbitration of the bus can be lost. They are the
Address Transfer and Data Transfer stages.
When the slav e log ic is enab led, th e sla ve co ntinue s to
receive. If arbitration was lost during the address
transfer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data
transfer stage, the device will need to re-transfer the
data at a later time.
Refer to Application Note AN578, “Use of the SSP
Module in the I2C™ Multi-Master Environment”
(DS00578) for more information.
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PIC16(L)F707
19.2.10 CLOCK SYNCHRONIZATION
When the CKP bit is cleared, the SCL output is held
low on c e i t is samp l ed lo w. Therefor e, the C KP bit wi l l
not stretch the SCL line until an external I2C master
device has already asserted the SCL line low. The
SCL output will remain low until the CKP bit is set and
all other devices on the I2C bus have released SCL.
This ensures that a write to the CKP bit will not violate
the minimum high time requirement for SCL
(Figure 19-14).
19.2.11 SL EE P OPERATIO N
While in Sleep mode, the I2C module can receive
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
FIGURE 19-14: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX-1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock
PIC16(L)F707
DS41418B-page 178 2010-2011 Microchip Technology Inc.
REGISTER 19-3: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
1 = A byte is re ce iv ed whi le the SSPBUF reg is ter is s til l hol din g the pre vi ous b yte . S SPOV is a “d on’ t
care” in Transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity S elect bit
1 = Release control of SCL
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = Reserved
1001 = Load SSPMSK register at SSPADD SFR Address(1)
1010 = Reserved
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1: When this mode is selected, any reads or writes to the SSP ADD SFR address accesses the SSPMSK register.
2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit.
2010-2011 Microchip Technology Inc. DS41418B-page 179
PIC16(L)F707
REGISTER 19-4: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I2C MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: SPI Data Input Sample Phase bit
1 = Slew Rate Control (limiting) disabled. Operating in I2C Standard mode (100 kHz and 1 MHz).
0 = Slew Rate Control (limiting) enabled. Operating in I2C Fast mode (400 kHz).
bit 6 CKE: SPI Clock Edge Select bit
This bit must be maintained clear. Used in SPI mode only.
bit 5 D/A: DATA/ADDRESS bit (I2C mode onl y)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Rese t)
0 = Stop bit was not detected last
bit 3 S: Start bit
This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: READ/WRITE bit Informa tion
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or ACK bit.
1 = Read
0 = Write
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit:
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
PIC16(L)F707
DS41418B-page 180 2010-2011 Microchip Technology Inc.
REGISTER 19-5: SSPMSK: SSP MASK REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave Mode, 10-bit Address
I2C Slave Mode, 10-bit Address (SSPM<3:0> = 0111):
1 = The received addres s bit ‘ 0’ is compared to SSPADD<0> to detect I2C address match
0 = The received addres s bit ‘ 0’ is not used to detect I2C address match
All other SSP modes: this bit has no effect.
REGIST ER 19-6: SSPADD: SSP I2C™ ADDRESS REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADD<7:0>: Address bits
Receiv ed add res s
TABLE 19-3: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Name B it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n
POR, BOR
Value on
all other
Resets
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPBUF Synchronous Serial Port Receive Buffer/T ransmit Register xxxx xxxx uuuu uuuu
SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SSPMSK(2) Synchr onous Serial Port (I2C mode) Address Mask Register 1111 1111 1111 1111
SSPSTAT SMP(1) CKE(1) D/A PSR/WUA BF 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in
I2C mode.
Note 1: Maintain these bits clear in I2C mode.
2: Accessible only when SSPM<3:0> = 1001.
2010-2011 Microchip Technology Inc. DS41418B-page 181
PIC16(L)F707
20.0 PROGRAM MEMORY READ
The Flash program memory is readable during normal
operatio n over the ful l VDD range of the dev ice. To read
data from Program Memory, five Special Function
Registers (SFRs) are used:
•PMCON1
•PMDATL
•PMDATH
• PMADRL
• PMADRH
The value written to the PMADRH:PMADRL register
pair determines which program memory location is
read. The read operation will be initiated by setting the
RD bit of the PMCON1 register. The program memory
flash controller takes two instructions to complete the
read. As a conse quence, af ter the RD bit has been set,
the next two instructions will be ignored. To avoid
conflic t with progra m execution, it is recommen ded that
the two instructions following the setting of the RD bit
are NOP. When the read co mp letes, the resul t is pla ced
in the PMDATLH:PMDATL register pair. Refer to
Example 20-1 for sample code.
EXAMPLE 20-1: PROGRAM MEMORY READ
Note: Code-protect does not effect the CPU
from performing a read operation on the
program memory. For more information,
refer to Section 8 .2 “Code Protection”.
BANKSEL PMADRL ;
MOVF MS_PROG_ADDR, W;
MOVWF PMADRH ;MS Byte of Program Address to read
MOVF LS_PROG_ADDR, W;
MOVWF PMADRL ;LS Byte of Program Address to read
BANKSEL PMCON1 ;
BSF PMCON1, RD ;Initiate Read
NOP
NOP ;Any instructions here are ignored as program
;memory is read in second cycle after BSF
BANKSEL PMDATL ;
MOVF PMDATL, W ;W = LS Byte of Program Memory Read
MOVWF LOWPMBYTE ;
MOVF PMDATH, W ;W = MS Byte of Program Memory Read
MOVWF HIGHPMBYTE ;
Required
Sequence
PIC16(L)F707
DS41418B-page 182 2010-2011 Microchip Technology Inc.
REGISTER 20-1: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1 U-0 U-0 U-0 U-0 U-0 U-0 R/S-0
— — — — — — —RD
bit 7 bit 0
Legend: S = Setable bit, cleared in hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘1’
bit 6-1 Unimplemented: Read as ‘0’
bit 0 RD: Read Control bit
1 = Initiat es a progra m mem ory read (The R D is c lea red in har dw are ; the R D bit can only be s et (no t
cleared) in software).
0 = Does not initiate a program memory read
REGISTER 20-2: PMDATH: PROGRAM MEMORY DATA HIGH REGISTER
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
—— PMD13 PMD12 PMD11 PMD10 PMD9 PMD8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a
program memory read command.
REGISTER 20-3: PMDATL: PROGRAM MEMORY DATA LOW REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a
program memory read command.
2010-2011 Microchip Technology Inc. DS41418B-page 183
PIC16(L)F707
REGISTER 20-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH REGISTER
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — PMA12 PMA11 PMA10 PMA9 PMA8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 PMA<12:8>: Program Memory Read Address bits
REGISTER 20-5: PMADRL: PROGRAM MEMORY ADDRESS LOW REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PMA<7:0>: Program Memory Re ad Addre ss bit s
TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY READ
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Value on all
other Re s e ts
PMCON1 ———————RD1--- ---0 1--- ---0
PMADRH — — — Program Memory Read Address Register High Byte ---x xxxx ---x xxxx
PMADRL Program Memory Read Address Regist er Low Byte xxxx xxxx xxxx xxxx
PMDATH —— Program Mem ory Read D ata Register High Byte --xx xxxx --xx xxxx
PMDATL Program Memory Read Data Register Low Byte xxxx xxxx xxxx xxxx
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the program memory read.
PIC16(L)F707
DS41418B-page 184 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 185
PIC16(L)F707
21.0 POWER-DOWN MODE (SLEEP)
The Power-down mode is entered by executing a
SLEEP instruction.
Upon entering Sleep mode, the following conditions
exist:
1. WDT will be cleared but keeps running, if
enabled.
2. PD bit of the STATUS register is cleared.
3. TO bit of the STATUS register is set.
4. CPU clock is disabled.
5. 31 kHz LFINTOSC is unaffected and peri pherals
that operate from it may continue operation in
Sleep.
6. T imer1/3 oscilla tor is unaf fecte d and peri pherals
that operate from it may continue operation in
Sleep.
7. ADC is unaf fec ted, if th e dedi cated FRC c lock i s
selected.
8. Capacitive Sensing oscillators are unaffected.
9. I/O ports maintain the status they had before
SLEEP was executed (driving high, low or high-
impedance).
10. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
• I/O pins should not be floating
• Ext ernal circuit ry sinkin g current from I/O pins
• Internal circuitry sourci ng cur rent from I/O pins
• Current dra w fr om pi ns w i th int erna l w eak p ull -ups
• Modules using 31 kHz LFINTOSC
• Modules using Timer1/3 oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching cur-
rents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 11.0 “Digital-to-Analog Con-
verter (DAC) Module” and Section 10.0 “Fixed Volt-
age Reference” for more information on these
modules.
21.1 Wake-up from Sleep
The devi ce can wa ke-up from Sleep th rough one of th e
following events:
1. External Reset input on MCLR pin, if enabled
2. BOR Rese t, if enabl ed
3. POR Reset
4. Watchdog Timer, if enabled
5. Any external interrupt
6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of
program executi on.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up thro ugh an interrupt eve nt, the co rres pon din g
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
ins tructi on afte r the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should hav e a NOP after the SLEEP instruct ion.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
PIC16(L)F707
DS41418B-page 186 2010-2011 Microchip Technology Inc.
21.1.1 WAKE-UP USIN G INTERR UPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llowin g wil l occur:
• If the interrupt occurs before the execution of a
SLEEP instruction
-SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
-TO
bit of the STATUS register will not be set
-PD
bit of the STATUS register will not be
cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction
-SLEEP instruction will be completely exe-
cuted
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
-TO
bit of the STATUS register will be set
-PD bit of the STATUS regi ste r will be cle are d.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruct ion completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 21-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
CLKOUT(2)
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency(4)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy Cycle
PC + 2 0004h 0005h
Dummy Cycle
TOST(3)
PC + 2
Note 1: XT, HS or LP Osc illa tor mode assume d.
2: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
3: TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on all
other
Resets
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000x
IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4IOCBF3IOCBF2IOCBF1 IOCBF0 0000 0000 0000 0000
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE ——— CCP2IE 0000 ---0 0000 ---0
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIR2 TMR3GIF TMR3IF TMRBIF TMRAIF ——— CCP2IF 0000 ---0 0000 ---0
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.
2010-2011 Microchip Technology Inc. DS41418B-page 187
PIC16(L)F707
22.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process allowing the
device to be p ro gramme d w ith t he most recen t f irm war e
or a custom firmware. Fiv e pins are need ed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
•MCLR
/VPP
•VDD
•VSS
The device is placed into Program/Verify mode by
holding the ICSPCLK and ICSPDAT pins low then
raising the voltage on MCLR/VPP from 0v to VPP. In
Program/V erify mode the program memory , user IDs and
the Confi guration Wo rds are prog rammed through s erial
commun ica tion s. T he IC SPDAT pin is a bidirect iona l I/O
used for transferring the serial data and th e ISCPCLK pin
is the clock input. For more information on ICSP™ refer
to the “PIC16F707/PIC16LF707 Programming
Specification” (DS41405A).
FIGURE 22-1: TYPICAL CONNECT ION FOR ICSP™ PROGRAMMING
Note: The IC D 2 produce s a VPP voltage greater
than the maximum VPP specification of the
PIC16(L)F707. When using this program-
mer, an external circuit, such as the
AC164112 MPLAB® ICD 2 VPP voltage
limiter, is req uired to keep the V PP volt a ge
within the device specifications.
VDD
VPP
GND
External D e vi ce to be
Data
Clock
VDD
MCLR/VPP
VSS
ICSPDAT
ICSPCLK
**
*
To Normal Connections
*Isolation devices (as required).
10k
Programming
Signals Programmed
VDD
PIC16(L)F707
DS41418B-page 188 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 189
PIC16(L)F707
23.0 INSTRUCTION SET SUMMARY
The PIC16(L)F707 instruction set is highly orthogonal
and is comprised of three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 23-1, while the various opcode
fields are sum m ariz ed in Table 23-1.
Table 23-2 lists the instructions recognized by the
MPASMTM assembler.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W regis ter . If ‘d’ is one, the res ult is place d
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
For literal and control operatio ns, ‘k’ represents an 8-
bit or 11-bit constant, or literal value.
One instr uction cycle co nsists of four os cillator periods ;
for an oscillator frequency of 4 MHz, this gives a
nominal instruction execution time of 1 s. All
instructions are executed within a single instruction
cycle, unless a conditional test is true, or the program
counter is changed as a result of an instruction. When
this occurs, the execution takes two instruction cycles,
with the second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
23.1 Read-Modif y-Write Op erations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
For example, a CLRF PORTB instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the unin-
tended consequence of clearing the condition that set
the RBIF flag.
TABLE 23-1: OPCODE FIELD
DESCRIPTIONS
FIGURE 23-1: GENERAL FORMAT FOR
INSTRUCTIONS
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral fie ld, constant data or label
xDon’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
dDestination select; d = 0: store result i n W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
CCarry bit
DC Digit carry bit
ZZero bit
PD Power-down bit
Byte-oriented file registe r operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriente d file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (li te r a l )
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16(L)F707
DS41418B-page 190 2010-2011 Microchip Technology Inc.
TABLE 23-2: PIC16(L)F707 INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcod e Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
–
k
k
k
–
k
–
–
k
k
Add literal and W
AND literal with W
Call Subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move litera l to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2010-2011 Microchip Technology Inc. DS41418B-page 191
PIC16(L)F707
23.2 Instruction Descriptions
ADDLW Add literal and W
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the
W register.
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 127
d 0,1
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Desc ription: Add the con tents of the W re gister
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W registe r . I f
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal
‘k’. The r esult is placed in the W
register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 127
d 0,1
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is sto r ed bac k in regi ste r ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
St at us Af fe cte d: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
St at us Af fe cte d: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
St at us Af fe cte d: None
Descr iption: If bit ‘b’ in regis ter ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the
next instru ction is discarde d, and
a NOP is executed instead, making
this a 2-cycle instruction.
PIC16(L)F707
DS41418B-page 192 2010-2011 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Desc ription: If bit ‘b’ in register ‘f’ is ‘0’, the next
instructi on is exec uted .
If bit ‘b’ is ‘1’, then the next
instructi on is dis ca rded an d a NOP
is exec ute d i nst ead, making thi s a
2-cycle instruction.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loa ded from PCLATH.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Desc ript ion : The con tents of registe r ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
St at us Af fe cte d: TO, PD
Description: CLRWDT instruction resets the
W atchdog T imer . It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
St at us Af fe cte d: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
St at us Af fe cte d: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2010-2011 Microchip Technology Inc. DS41418B-page 193
PIC16(L)F707
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decrem ented. If ‘d’ is ‘0’, th e result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
resu lt is ‘0’, then a NOP is
executed instead, making it a
2-cycle instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The e le ven -bi t im me dia t e v al ue i s
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
incremen ted. If ‘ d’ is ‘0’, th e result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
St at us Af fe cte d: None
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOP is executed
instead, making it a 2-cycle
instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
St at us Af fe cte d: Z
Descr iption: The conten ts of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W registe r.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .OR. (f) (destination)
St at us Af fe cte d: Z
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is pla ce d back in
register ‘f’.
PIC16(L)F707
DS41418B-page 194 2010-2011 Microchip Technology Inc.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Description: The contents of register f is
moved to a destination dependent
upon the status of d. If d = 0,
destination is W register. If d = 1,
the destination is file register f
itself. d = 1 is useful to test a file
register since status flag Z is
affected.
Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
W= value in FSR
register
Z= 1
MOVLW Move literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Desc ription: The eight-b it literal ‘k’ i s loaded i nto
W register. The “don’t cares” will
assemble as ‘0’s.
Words: 1
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W= 0x5A
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 127
Operation: (W) (f)
St at us Af fe cte d: None
Description: Move data from W register to
register ‘f’.
Words: 1
Cycles: 1
Example: MOVW
FOPTION
Before Instruction
OPTION= 0xFF
W = 0x4F
After Instruction
OPTION= 0x4F
W = 0x4F
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
St at us Af fe cte d: None
Description: No operation.
Words: 1
Cycles: 1
Example: NOP
2010-2011 Microchip Technology Inc. DS41418B-page 195
PIC16(L)F707
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
Status Affected: None
Description: Return from Interrupt. Stack is
POPed an d Top-of-S t ack (TOS) is
loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
St at us Af fe cte d: None
Description: The W register is loaded with the
eight bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Words: 1
Cycles: 2
Example:
TABLE
CALL TABLE;W contains
table
;offset value
• ;W now has table value
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
St at us Af fe cte d: None
Description: Return from subroutine. The stack
is POPed an d t he top of th e s tack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
PIC16(L)F707
DS41418B-page 196 2010-2011 Microchip Technology Inc.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110 0110
C=0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C=1
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Desc ript ion : The conten t s of regis te r ‘f’ are
rotat ed one bit to the r ight throug h
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is place d
back in register ‘f’.
Register fC
Register fC
SLEEP Enter Sleep mode
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
St at us Af fe cte d: T O , PD
Descripti on: The power-down S tatus bit, PD is
cleared. Time-out Status bit, TO
is set. Watchdog Timer an d its
prescaler are cleared.
The processor is put into Sleep
mode with th e oscillat or stopped.
SUBLW Subtract W from literal
Syntax: [ label ] SUBLW k
Operands: 0 k 255
Operation: k - (W) W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
C = 0W k
C = 1W k
DC = 0W<3:0> k<3:0>
DC = 1W<3:0> k<3:0>
2010-2011 Microchip Technology Inc. DS41418B-page 197
PIC16(L)F707
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
C = 0W f
C = 1W f
DC = 0W<3:0> f<3:0>
DC = 1W<3:0> f<3:0>
XORLW Exclusive OR literal with W
Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
St at us Af fe cte d: Z
Description: The contents of the W register
are XOR’ed with the eig ht-b it
literal ‘k’. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) destination)
St at us Af fe cte d: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
PIC16(L)F707
DS41418B-page 198 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 199
PIC16(L)F707
24.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Progra mm ers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-C ost D emonstration/Development Boards,
Evaluation Kits, and Starter Kits
24.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Deb ugger (so ld separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Exten si ve on-l in e he lp
• Integration of select third party tools, such a s
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source f iles ( eithe r C or assembly)
• One-tou ch compile o r assemble , and downl oad to
emulator and simulator tools (automatically
updates all project information)
• Debug us ing :
- Sour ce files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
PIC16(L)F707
DS41418B-page 200 2010-2011 Microchip Technology Inc.
24.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compil ers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
24.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcont rollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compil ers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
process or , and one-s tep driver , and can run on multipl e
platforms.
24.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly co de
• Conditional assembly for multi-purpose
sour ce fil es
• Directives that allow complete control over the
assembly process
24.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLA B C18 C Compiler. It can link re locatable ob jects
from precompiled libraries, using directives from a
linker script.
The MPLIB O bject Li brarian manage s the cre ation an d
modification of library files of precompiled code. When
a rout in e from a l ibra ry is cal led fro m a so urc e f ile, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, re placement, delet ion and extraction
24.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the asse mbler to pro duce i ts o bje ct file . The ass embl er
generates relocatable object files that can then be
archived or linke d with other relocatable ob ject files and
arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB IDE compatibility
2010-2011 Microchip Technology Inc. DS41418B-page 201
PIC16(L)F707
24.7 MPLAB SIM Software Simulat or
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most periph erals and i nternal regi sters.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
developm ent tool .
24.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated D evelopment Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgrad able through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
24.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
device s. It debugs and programs PIC® Flash mi crocon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nect ed to t he des ign e nginee r's PC using a hig h-spee d
USB 2.0 i nte rfac e a nd is co nnected to the t arget with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports al l
MPLAB ICD 2 headers.
24.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most af fordable price point using the powerful graphica l
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller , hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
PIC16(L)F707
DS41418B-page 202 2010-2011 Microchip Technology Inc.
24.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The P ICkit™ 2 Develo pment Program mer/Debu gger i s
a low-cost development tool with an easy to use inter-
face fo r programmin g and debu gging Micr ochip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 famil ies o f 8 -bi t, 1 6-b it, and 32-b it
microcontrollers, and many Microchip Serial EEPROM
produ cts . With Mic rochip ’s power ful MPL AB Integrate d
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file reg ist ers can be ex amin ed and m odifie d.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller , hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
24.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64 ) for me nus an d err or messag es an d a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is in cluded
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer can rea d, verify an d program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPL AB PM3 has high-spe ed comm unications and
optimized algorithms for quick programming of large
memory devices and inc orporates an MMC card for file
storage and data applications.
24.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards includ e prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The board s suppo rt a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory .
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience t he specified d evice. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2010-2011 Microchip Technology Inc. DS41418B-page 203
PIC16(L)F707
25.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias.......................................................................................................-40°C to +125°C
Storage temperature........................................................................................................................ -65°C to +150°C
Vo lt a ge on VDD with respect to VSS, PIC16F707 ............................................................................... -0.3V to +6.5V
Vo lt a ge on VCAP pin with respect to VSS, PIC16F707 ....................................................................... -0.3V to +4.0V
Vo lt a ge on VDD with respect to VSS, PIC16LF707 ............................................................................. -0.3V to +4.0V
Vo lt a ge on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum curr ent out of VSS pin ...................................................................................................................... 95 mA
Maximum curr ent into VDD pin......................................................................................................................... 70 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin..............................................................................................25 mA
Maximum current sunk by all ports(2), -40°C TA +85°C for industrial ........................................................200 mA
Maximum current sunk by all ports(2), -40°C TA +125°C for extended........................................................90 mA
Maximum current sourced by all ports(2), 40°C TA +85°C for industrial................................................... 140 mA
Maximum current sourced by all ports(2), -40°C TA +125°C for extended...................................................65 mA
Note 1: Power diss ipation is ca lcu la t ed as follow s : PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x
IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This is a stre ss rating onl y and functi onal operati on of the devi ce at those or an y other condi tions abov e those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
PIC16(L)F707
DS41418B-page 204 2010-2011 Microchip Technology Inc.
25.1 DC Characteristics: PIC16(L)F707-I/E (Industrial, Extended)
PIC16LF707 Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC16F707 Standard Operating Conditions (unless otherwis e stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
D001 VDD Supply Volt a g e
PIC16LF707 1.8
1.8
2.3
2.5
—
—
—
—
3.6
3.6
3.6
3.6
V
V
V
V
FOSC 16 MHz: HFINTOSC, EC
FOSC 4MHz
FOSC 20 MHz , EC
FOSC 20 MHz, HS
D001 PIC16F707 1.8
1.8
2.3
2.5
—
—
—
—
5.5
5.5
5.5
5.5
V
V
V
V
FOSC 16 MHz: HFINTOSC, EC
FOSC 4 MHz
FOSC 20 MHz, EC
FOSC 20 MHz, HS
D002* VDR RAM Data Retention Voltage(1)
PIC16LF707 1.5 — — V Device in Sleep mode
D002* PIC16F707 1.7 — — V Device in Sleep mode
VPOR*Po wer-on Reset Release Voltage —1.6— V
VPORR*Power-on Reset Rearm Voltage
PIC16LF707 — 0.8 — V Dev ice in Sleep mode
PIC16F707 —1.7 — V Device in Sleep mode
D003 VFVR Fixed Voltage Reference V oltage,
Initial Accuracy -5.5
-5.5
-5.5
—
—
—
5.5
5.5
5.5
%
%
%
VFVR = 1.024V, VDD 2.5V
VFVR = 2.048V, VDD 2.5V
VFVR = 4.096V, VDD 4.75V;
-40 TA85°C
-6
-6
-6
—
—
—
6
6
6
%
%
%
VFVR = 1.024V, VDD 2.5V
VFVR = 2.048V, VDD 2.5V
VFVR = 4.096V, VDD 4.75V;
-40 TA125°C
D004* SVDD VDD Rise Rate to ensure internal
Power-on Reset signal 0.05 — — V/ms See S ection 3.2 “Pow er-o n Reset
(POR)” for details.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2010-2011 Microchip Technology Inc. DS41418B-page 205
PIC16(L)F707
FIGURE 25-1: POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
VSS
NPOR
TPOR(3)
POR REARM
Note 1: When NPOR is low, the device is held in Reset.
2: TPOR 1 s typ ical.
3: TVLOW 2.7 s typical.
TVLOW(2)
PIC16(L)F707
DS41418B-page 206 2010-2011 Microchip Technology Inc.
25.2 DC Characteristics: PIC16(L)F707-I/E (Industrial, Extended)
PIC16LF707 Standard Ope r ating Condi tions (unles s otherwise stated)
Operating temperature -40°C TA +85°C for indu strial
-40°C TA +125°C for extended
PIC16F707 Standard Oper a ting Condit ions (unless ot herwise stated)
Operating temperature -40°C TA +85°C for indu strial
-40°C TA +125°C for extended
Param
No. Device
Characteristics Min. Typ† Max. Units Conditions
VDD Note
Supply Current (IDD)(1, 2)
D009 LDO Regulator —350 —A — HS, EC OR INTOSC/INTOSCIO (8-16 MHZ)
Clock modes with all VCAP pins disabled
—50 —A — All VCAP pins disabled
—30 —A — VCAP enabled on RA0, RA5 or RA6
— 5 — A — LP Clock mode and Sleep (requires FVR and
BOR to be disabled)
D010 — 7.0 12 A1.8F
OSC = 32 kHz
LP Oscillator mode (Note 4),
-40°C TA +85°C
—9.014 A3.0
D010 —11 20 A1.8 FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40°C TA +85°C
—14 22 A3.0
—15 24 A5.0
D011 — 7.0 12 A1.8
FOSC = 32 kHz
LP Oscillator mode
-40°C TA +125°C
—9.018 A3.0
D011 —11 21 A1.8 FOSC = 32 kHz
LP Oscillator mode (Note 4)
-40°C TA +125°C
—14 25 A3.0
—15 27 A5.0
D011 — 110 150 A1.8F
OSC = 1 MHz
XT Oscillator mode
— 150 215 A3.0
D011 —120 175 A1.8 FOSC = 1 MHz
XT Oscillator mode (Note 5)
—180 250 A3.0
—240 300 A5.0
D012 — 230 300 A1.8F
OSC = 4 MHz
XT Oscillator mode
— 400 600 A3.0
D012 —250 350 A1.8 FOSC = 4 MHz
XT Oscillator mode (Note 5)
—420 650 A3.0
—500 750 A5.0
D013 — 125 180 A1.8F
OSC = 1 MHz
EC Oscillator mode
— 230 270 A3.0
D013 —150 205 A1.8 FOSC = 1 MHz
EC Oscillator mode (Note 5)
—225 320 A3.0
—250 410 A5.0
Note 1: The test conditions for all IDD measurem ents in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCL R = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA ) with REXT in k
4: FVR and BOR are disabled.
5: 0.1 F capacitor on VCAP (RA0).
2010-2011 Microchip Technology Inc. DS41418B-page 207
PIC16(L)F707
Supply Current (IDD)(1, 2)
D014 — 290 330 A1.8FOSC = 4 MHz
EC Oscillator mode
— 460 500 A3.0
D014 —300 430 A1.8 FOSC = 4 MHz
EC Oscillator mode (Note 5)
—450 655 A3.0
—500 730 A5.0
D015 — 100 130 A1.8F
OSC = 500 kHz
MFINTOSC mode
— 120 150 A3.0
D015 —115 195 A1.8 FOSC = 500 kHz
MFINTOSC mode (Note 5)
—135 200 A3.0
—150 220 A5.0
D016 — 650 800 A1.8F
OSC = 8 MHz
HFINTOSC mode
— 1000 1200 A3.0
D016 —625 850 A1.8 FOSC = 8 MHz
HFINTOSC mode (Note 5)
—1000 1200 A3.0
—1100 1500 A5.0
D017 — 1.0 1.2 mA 1.8 FOSC = 16 MHz
HFINTOSC mode
— 1.5 1.85 mA 3.0
D017 — 1 1.2 mA 1.8 FOSC = 16 MHz
HFINTOSC mode (Note 5)
—1.5 1.7 mA 3.0
—1.7 2.1 mA 5.0
D018 — 210 240 A1.8F
OSC = 4 MHz
EXTRC mode (Note 3, Note 5)
— 340 380 A3.0
D018 —225 320 A1.8 FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
—360 445 A3.0
—410 650 A5.0
D019 — 1.6 1.9 mA 3.0 FOSC = 20 MHz
HS Oscillator mode
—2.02.8mA3.6
D019 —1.6 2mA 3.0 FOSC = 20 MHz
HS Oscillator mode (Note 5)
—1.9 3.2 mA 5.0
25.2 DC Characteristics: PIC16(L)F707-I/ E (Industrial, Extended) (Continued)
PIC16LF707 Standard Operating Conditions (unless otherwise stat ed)
Operating temperature -40°C TA +85°C for indu strial
-40°C TA +125°C for extended
PIC16F707 Standard Operating Condit ions (unless otherwise stated)
Operating temperature -40°C TA +85°C for indu strial
-40°C TA +125°C for extended
Param
No. Device
Characteristics Min. Typ† Max. Units Conditions
VDD Note
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCL R = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA ) with REXT in k
4: FVR and BOR are disabled.
5: 0.1 F capacitor on VCAP (RA0).
PIC16(L)F707
DS41418B-page 208 2010-2011 Microchip Technology Inc.
25.3 DC Characteristics: PIC16(L)F707-I/E (Power-Down)
PIC16LF707 Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC16F707 Standard Operating Co nditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Characteristics Min. Typ† Max.
+85°C Max.
+125°C Units Conditions
VDD Note
Power-down Base Current (IPD)(2)
D020 — 0.02 0.7 3.9 A 1.8 WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
— 0.08 1.0 4.3 A3.0
D020 —4.3 10.2 17 A1.8 WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
— 5 10.5 18 A3.0
—5.5 11.8 21 A5.0
D021 — 0.5 1.7 4.1 A 1.8 LP WD T Current (Note 1)
— 0.8 2.5 4.8 A3.0
D021 — 6 13.5 16.4 A1.8 LPWDT Current (Note 1)
—6.5 14.5 16.8 A3.0
—7.5 16 18.7 A5.0
D021A — 8.5 18 22 A 1.8 F VR curr ent (Note 1, Note 3)
— 8.5 18 22 A3.0
D021A —23 44 48 A1.8 FVR current (Note 1, Note 3,
Note 5)
—25 45 55 A3.0
—26 60 70 A5.0
D022 — — — — A 1.8 BOR Current (Note 1, Note 3)
— 7.5 12 22 A3.0
D022 — — — — A1.8 BOR Current (Note 1, Note 3,
Note 5)
—23 42 49 A3.0
—25 46 50 A5.0
D026 — 0.6 3 7 A 1.8 T1OSC Current (Note 1)
—1.8 6 8.75A3.0
D026 —4.5 11.1 —A1.8 T1OSC Current (Note 1)
— 6 12.5 —A3.0
— 7 13.5 —A5.0
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD curren t from th i s l imit. Ma x
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down curre nt is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.
4: A/D oscillator source is FRC.
5: 0.1 F capacitor on VCAP (RA0).
6: Includes FVR IPD and DAC IPD.
2010-2011 Microchip Technology Inc. DS41418B-page 209
PIC16(L)F707
Power-down Base Current (IPD)(2)
D027 — 0.06 0.7 5.0 A 1.8 A/ D Current (Note 1, Note 4), no
conversion in progress
— 0.08 1.0 5.5 A3.0
D027 — 6 10.7 18 A1.8 A/D Current (Note 1, Note 4), no
conversion in progress
— 7 10.6 20 A3.0
—7.2 11.9 22 A5.0
D027A — 250 400 — A 1.8 A/D Current (Note 1, Note 4),
conversion in progress
— 250 400 — A3.0
D027A —280 430 —A1.8 A/D Current (Note 1, Note 4,
Note 5), conversion in progress
—280 430 —A3.0
—280 430 —A5.0
D028 — 2.2 3.2 14.4 A 1.8 Cap Sense Low Range
Low Power
—3.34.415.6A3.0
D028 —6.5 13 21 A1.8 Cap Sense Low Range
Low Power
— 8 14 23 A3.0
— 8 14 25 A5.0
D028A — 4.2 6 17 A 1.8 Cap Sense Low Range
Medium Power
—6 7 18A3.0
D028A —8.5 15.5 23 A1.8 Cap Sense Low Range
Medium Power
—11 17 24 A3.0
—11 18 27 A5.0
D028B — 12 14 25 A 1.8 Cap Sense Low Range
High Power
—3235 44A3.0
D028B —16 20 31 A1.8 Cap Sense Low Range
High Power
—36 41 50 A3.0
—42 49 58 A5.0
D028C — 115 — — A 1.8 Cap Sense HighRange
Low Power (Note 6)
—120— — A3.0
D028C —135 — — A1.8 Cap Sense High Range
Low Power (Note 6)
—140 — — A3.0
—150 — — A5.0
25.3 DC Characteristics: PIC16(L)F707-I/E (Power-Down) (Continued)
PIC16LF707 Standard Operating Co nditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC16F707 Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Characteristics Min. Typ† Max.
+85°C Max.
+125°C Units Conditions
VDD Note
† Data in “Typ” column is at 3.0V, 25°C unless otherwise st ated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current fr om thi s l im i t. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down curre nt is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.
4: A/D oscillator source is FRC.
5: 0.1 F capacitor on VCAP (RA0).
6: Includes FVR IPD and DAC IPD.
PIC16(L)F707
DS41418B-page 210 2010-2011 Microchip Technology Inc.
D028D — 125 — — A 1.8 Cap Sense HighRange
Medium Power (Note 6)
—130— — A3.0
D028D —145 — — A1.8 Cap Sense High Range
Medium Power (Note 6)
—150 — — A3.0
—160 — — A5.0
D028E — 150 — — A 1.8 Cap Sense HighRange
High Power (Note 6)
—170— — A3.0
D028E —180 — — A1.8 Cap Sense High Range
High Power (Note 6)
—190 — — A3.0
—200 — — A5.0
25.3 DC Characteristics: PIC16(L)F707-I/E (Power-Down) (Continued)
PIC16LF707 Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC16F707 Standard Operating Co nditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Characteristics Min. Typ† Max.
+85°C Max.
+125°C Units Conditions
VDD Note
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD curren t from th i s l imit. Ma x
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down curre nt is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.
4: A/D oscillator source is FRC.
5: 0.1 F capacitor on VCAP (RA0).
6: Includes FVR IPD and DAC IPD.
2010-2011 Microchip Technology Inc. DS41418B-page 211
PIC16(L)F707
25.4 DC Characteristics: PIC16(L)F707-I/ E
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
VIL Input L ow Voltage
I/O PORT:
D030 with TTL buffer — — 0.8 V 4.5V VDD 5.5V
D030A — — 0.15 VDD V1.8V VDD 4.5V
D031 with Schmitt Trigger buffer — — 0.2 VDD V2.0V VDD 5.5V
with I2C™ levels — — 0.3 VDD V
D032 MCLR, OSC1 (RC mode)(1) ——0.2VDD V
D033A OSC1 (HS mode) — — 0.3 VDD V
VIH Input High Voltage
I/O po rts : — —
D040 with TTL buffer 2.0 — — V 4.5V VDD 5.5V
D040A 0.25 VDD +
0.8 ——V1.8V VDD 4.5V
D041 with Schmitt Trigger buffer 0.8 VDD ——V2.0V VDD 5.5V
with I2C™ levels 0.7 VDD ——V
D042 MCLR 0.8 VDD ——V
D043A OSC1 (HS mode) 0.7 VDD ——V
D043B OSC1 (RC mode) 0.9 VDD ——V(Note 1)
IIL Input Leakage Current(2)
D060 I/O ports — ± 5
± 5
± 125
± 1000
nA
nA
VSS VPIN VDD, Pin at high-
impedance, 85°C
125°C
D061 MCLR(3) —± 50± 200nAVSS VPIN VDD, 85°C
IPUR PORTB Weak Pull-up Current
D070* 25
25 100
140 200
300 AVDD = 3.3V, VPIN = VSS
VDD = 5.0V, VPIN = VSS
VOL Output Low Volta ge(4)
D080 I/O ports ——0.6V
IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
VOH Output High Volta ge (4)
D090 I/O ports VDD - 0.7 — — V IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
Capacitive Loading Specs on Output Pins
D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
Program Flash Memory
Legend: T BD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
PIC16(L)F707
DS41418B-page 212 2010-2011 Microchip Technology Inc.
D130 EPCell Endurance 100 1k — E/W Temperature during programm ing:
10°C TA 40°C
D131 VDD for Read VMIN ——V
Voltage on MCLR/VPP during
Erase/Program 8.0 — 9.0 V Temperature during programming:
10°C TA 40°C
VDD for Bulk Erase 2. 7 3 — V Tem perature during pro gramm ing:
10°C TA 40°C
D132 VPEW VDD for Write or Row Erase 2.7 — — V VMIN = Minimum operating voltage
VMAX = Maximum operating
voltage
IPPPGM Current on MCLR/VPP during
Erase/Write ——5.0mA
Temperature during programming:
10°C TA 40°C
IDDPGM Current on VDD during Erase/
Write —5.0 mA Temperature during programming:
10°C TA 40°C
D133 TPEW Erase/Write cycle time — 2.8 ms Temperat ure during programming:
10°C TA 40°C
D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications
are violated
VCAP Capacitor Charging
D135 Charging current — 200 — A
D135A Source/sink capability when
charging complete —0.0—mA
25.4 DC Characteristics: PIC16(L)F707-I/E (Continued)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
2010-2011 Microchip Technology Inc. DS41418B-page 213
PIC16(L)F707
25.5 Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No. Sym Characteristic Typ Units Conditions
TH01 JA Thermal Resistance Junction to Ambient 47.2 C/W 40-pin PDIP package
46 C/W 44-pin TQFP package
24.4 C/W 44-pin QFN 8x8mm package
TBD C/W 40-pin UQFN 5x5mm package
TH02 JC Thermal Resistance Junction to Case 24.7 C/W 40-pin PDIP package
14.5 C/W 44-pin TQFP package
20 C/W 44-pin QFN 8x8mm package
TBD C/W 40-pin UQFN 5x5mm package
TH03 TJMAX Maximum Junction Temperature 15 0 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/OI/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2, 3)
Note 1: IDD is current to run the chip alone without driving any load on the outpu t pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
PIC16(L)F707
DS41418B-page 214 2010-2011 Microchip Technology Inc.
25.6 Timing Paramet er Symbology
The timing parameter symbols have been created with
one of the following formats:
FIGURE 25-2: LOAD CONDITIONS
1. TppS2ppS
2. TppS
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppe rcase lett ers and their meanings:
SFFall PPeriod
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
V
SS
C
L
Legend: CL = 50 pF for all pins, 15 pF for
OSC2 output
Load Con dition
Pin
2010-2011 Microchip Technology Inc. DS41418B-page 215
PIC16(L)F707
25.7 AC Characteristi cs: PIC16F707-I/E
FIGURE 25-3: CLOCK TIMING
FIGURE 25-4: PIC16F70 7 VOLTAGE FREQUE NCY GRAPH, -40°C
TA
+125°C
OSC1/CLKIN
OSC2/CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
OS02
OS03OS04 OS04
OSC2/CLKOUT
(LP,XT,HS M odes)
(CLKOUT Mode)
1.8
2.5
2.0
0
2.3
Frequency (MHz)
VDD (V)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.
420
10 16
5.5
3.6
PIC16(L)F707
DS41418B-page 216 2010-2011 Microchip Technology Inc.
FIGURE 25-5: PIC16LF707 VOLTAGE FREQUENCY GRAPH, -40°C
TA
+125°C
FIGURE 25-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
1.8
2.5
2.0
0
2.3
Frequency (MHz )
VDD (V)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.
420
10 16
3.6
125
25
2.0
0
60
85
VDD (V)
4.0 5.04.5
Temperature (°C)
2.5 3.0 3.5 5.5
1.8
Note 1: This chart covers both regulator enabled and regulator disabled states.
2: Regulator Nominal voltage.
3.3(2)
-40
-20
+ 5%
± 2%
+ 5%
± 3%
2010-2011 Microchip Technology Inc. DS41418B-page 217
PIC16(L)F707
TABLE 25-1: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode
DC — 4 MHz XT Oscillator mode
DC — 20 MH z HS Oscillator mode
DC — 20 MH z EC Oscillator mode
Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode
0.1 — 4 MHz XT Os cillator mode
1 — 4 MHz HS Oscillator mode, VDD 2.7V
1 — 20 MHz HS Oscillator mode, VDD 2.7V
DC — 4 MHz RC Oscillator mode
OS02 TOSC External CLKIN Period(1) 27 — s LP Oscillator mode
250 — ns XT Oscillator mode
50 — ns HS Oscillator mode
50 — ns EC Oscillator mode
Oscillator Period(1) — 30.5 — s LP Oscillator mode
250 — 10,000 ns XT Oscillator mode
250 — 1,000 ns HS O scillator mode, VDD 2.7V
50 — 1,000 ns HS Oscillator mode, VDD 2.7V
250 — — ns RC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
OS04* TosH,
TosL Ex ternal CLKIN H igh,
External CLKI N Lo w 2——s LP oscillator
100 — — ns XT oscillator
20 — — ns HS oscillator
OS05* TosR,
TosF External CLKIN R ise,
External CLKIN Fall 0—ns LP osc illator
0—ns XT oscillator
0—ns HS oscillator
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cyc le period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
PIC16(L)F707
DS41418B-page 218 2010-2011 Microchip Technology Inc.
FIGURE 25-7: CLKOUT AND I/O TIMING
TABLE 25-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Freq.
Tolerance Min. Typ† Max. Units Conditions
OS08 HFOSC Internal Calibrated HFINTOSC
Frequency(2) 2% — 16.0 — MHz 0°C TA +85°C,
VDD V
5% — 16.0 — MHz -40°C TA +125°C
OS08A MFOSC Internal Calibrated MFINTOSC
Frequency(2) 2% — 500 — kHz 0°C TA +85°C
VDD V
5% — 500 10 kHz -40°C TA +125°C
OS10* TIOSC ST HFINTOSC Wake-up from Sleep
Start-up Time ——58s
MFINTOSC Wake-up from Sleep
Start-up Time — — 20 30 s
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cyc le period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
3: By design.
FOSC
CLKOUT
I/O pi n
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
OS11
OS19
OS13
OS15
OS18, OS19
OS20
OS21
OS17 OS16
OS14
OS12
OS18
Old Value New Value
Write Fetch Read ExecuteCycle
2010-2011 Microchip Technology Inc. DS41418B-page 219
PIC16(L)F707
TABLE 25-3: CLKOUT AND I/O TIMING PARAMETERS
S tandard Operating Conditi ons (unle ss othe rwis e stated)
Operati ng Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
OS11 TosH2ckL Fosc to CLKOUT (1) ——70nsVDD = 3.3-5.0V
OS12 TosH2ckH Fosc to CLKOUT (1) ——72nsVDD = 3.3-5.0V
OS13 TckL2ioV CLKOUT to Port out valid(1) ——20ns
OS14 Tio V2c kH Port input valid befo re CL KOUT(1) TOSC + 200 ns — — ns
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3 -5.0V
OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid
(I/O in hold time) 50 — — ns VDD = 3.3-5.0V
OS17 Tio V2os H Port input val id to Fosc (Q2 cycl e)
(I/O in setup time) 20 — — ns
OS18 TioR Port output rise time(2) —
—40
15 72
32 ns VDD = 2.0V
VDD = 3.3-5. 0V
OS19 Tio F Port output fall time(2) —
—28
15 55
30 ns VDD = 2.0V
VDD = 3.3-5. 0V
OS20* Tinp INT pin input high or low time 25 — — ns
OS21* Trbp PORTB interrupt-on-change new input
level time TCY ——ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2: Includes OSC2 in CLKOUT mode.
PIC16(L)F707
DS41418B-page 220 2010-2011 Microchip Technology Inc.
FIGURE 25-8: RESE T, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMI NG
FIGURE 25-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-Up Time
Internal Reset(1)
Wat c hdog Timer
33
32
30
31
34
I/O pins
34
Note 1: Asserted low .
Reset(1)
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33(1)
Note 1: 64 ms delay only if PW RTE bit in the Configuration Word register is programmed to ‘0’. 2 ms
delay if PWRTE = 0 and VREG EN = 1.
Reset
(due to BOR)
VBOR and VHYST
37
2010-2011 Microchip Technology Inc. DS41418B-page 221
PIC16(L)F707
TABLE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET PARAMETERS
S tandard Operating Conditi ons (unle ss othe rwis e stated)
Operati ng Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
30 TMCLMCLR Pulse Width (low) 2
5—
——
—s
sVDD = 3.3-5V, -40°C to +85°C
VDD = 3.3-5V
31 TWDTLP Low Power Watchdog Timer Time-
out Period (No Prescaler) 10 18 27 ms VDD = 3.3V-5V
32 TOST Oscillator Start-up Timer Period(1),
(2) —1024—Tosc(Note 3)
33* TPWRT Power-up Timer Period,
PWRTE =040 65 140 ms
34* TIOZ I/O high-impedance from MCLR
Low or Watchdog Timer Reset ——2.0s
35 VBOR Brown-out Reset Voltage 2.38
1.80 2.5
1.9 2.73
2.11 V BORV=2.5V
BORV=1.9V
36* VHYST Brown-out Reset Hysteresis 0 25 50 mV -40°C to +85°C
37* TBORDC Brown-out Reset DC Response
Time 135
10 sVDD VBOR, -40°C to +85°C
VDD VBOR
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note1: Instruction cycle period (TCY) equals four time s the inpu t oscil lator tim e base pe riod. All s pecifi ed values are
based o n charac terization data for that partic ular oscill ator type under st anda rd operatin g conditions with t he
device executi ng code. Exceedi ng these speci fied lim its may result in an u nstab le oscil lator ope ration and /or
higher t han expecte d curre nt co nsu mption. All devices are te st ed to o perate at “mi n” val ues wi th an externa l
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all dev ices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decouple d as clos e to the devi ce as
possible. 0.1 F and 0.01 F values in parallel are recommended.
PIC16(L)F707
DS41418B-page 222 2010-2011 Microchip Technology Inc.
FIGURE 25-10: TIMER0/A/B AND TIME R1/3 EXTERNA L CLOCK TIMINGS
T0CKI/TACKI/TBCKI
T1CKI/T3CKI
40 41
42
45 46
47 49
TMRx
TABLE 25-5: TIMER0/A/B AND TIMER1/3 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
40* TT0H T0CKI/TACK I/TBCKI High
Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Pre s-
caler 10 — — ns
41* TT0L T0CKI/TACKI/TBCKI Low
Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Pre s-
caler 10 — — ns
42* TT0P T0CKI/TACKI/TBCKI Period Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 256)
45* TT1H T1CKI/
T3CKI High
Time
Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI/
T3CKI Low
Time
Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
47* TT1P T1CKI/
T3CKI Input
Period
Synchronous Greater of:
30 or TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
Asynchronous 60 — — ns
48 FT1 Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit
T1OSCEN)
32.4 32.76
8 33.1 kHz
49* TCKEZTMR
1Delay from External Clock Edge to T imer
Increment 2 TOSC —7 TOSC — Timers in Sync
mode
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2010-2011 Microchip Technology Inc. DS41418B-page 223
PIC16(L)F707
FIGURE 25-11: CAPTURE/COM PARE/PWM TIMINGS (CCP)
Note: Refer to Figure 25-2 for load conditions.
(Capture mode)
CC01 CC02
CC03
CCPx
TABLE 25-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
CC01* Tc cL CCPx Input Low Time No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 20 — — n s
CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — n s
CC03* TccP CCPx Input Period 3TCY + 40
N— — ns N = prescale value (1, 4 or 16)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
TABLE 25-7: PIC16F707 A/D CONVERTER (ADC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
AD01 NRResolution — — 8 bit
AD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0V
AD03 EDL Differential Error — — ±1 LS b No missing codes
VREF = 3.0V
AD04 EOFF Offset Error — — ±2.2 LS b VREF = 3.0V
AD05 EGN Gain Error — — ±1.5 LSb VREF = 3.0V
AD06 VREF Reference Voltage(3) 1.8 — VDD V
AD07 VAIN Full-Scale Range VSS —VREF V
AD08 ZAIN Recommended Impedance of
Analog Voltage Source —— 50
kCan go higher if external 0.01F capacitor is
present on input pin.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decr eases with an increase in the input voltage and has no missing codes.
3: When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
PIC16(L)F707
DS41418B-page 224 2010-2011 Microchip Technology Inc.
FIGURE 25-12: PIC16F707 A/D CONVERSION TIMING (NOR MAL MODE)
TABLE 25-8: PIC16F707 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
AD130* TAD A/D Clock Period 1. 0 — 9.0 sTOSC-based
A/D Internal RC Oscillator
Period 1.0 2.0 6.0 s ADCS<1:0> = 11 (ADRC mode)
AD131 TCNV Conversion Time (not including
Acquisition Time) (1) — 10.5 — TAD Set GO/DONE bit to conversion
complete
AD132* TACQ Acquisition Time — 1.0 — s
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The ADRES register may be read on the following TCY cycle.
AD131
AD130
BSF ADCON0, GO
Q4
A/D CLK
A/D Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
765 3210
Note 1: If the A/D clock sour ce is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
4
AD134 (TOSC/2(1))
1 TCY
AD132
2010-2011 Microchip Technology Inc. DS41418B-page 225
PIC16(L)F707
FIGURE 25-13: PIC16F707 A/D CONVERSION TIMING (SLEEP MODE)
FIGURE 25-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
AD132
AD131
AD130
BSF ADCON0, GO
Q4
A/D CLK
A/D Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
7 5 3210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be execut ed.
AD134
4
6
1 TCY
(TOSC/2 + TCY(1))
1 TCY
Note: Refer to Figure 25-2 for load conditions.
US121 US121
US120 US122
CK
DT
TABLE 25-9: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
S tandard Operating Conditi ons (unle ss othe rwis e stated)
Operati ng Temperature -40°C TA +125°C
Param.
No. Symbol Characteristic Min. Max. Units Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid 3.0-5.5V — 80 ns
1.8-5.5V — 100 ns
US121 TCKRF Clock out rise time and fall time
(Master mo de) 3.0-5.5V — 45 ns
1.8-5.5V — 50 ns
US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns
1.8-5.5V — 50 ns
PIC16(L)F707
DS41418B-page 226 2010-2011 Microchip Technology Inc.
FIGURE 25-15: USART SYNCHRONO US RECEIVE (MASTER/SLAVE) TIMING
FIGURE 25-16 : SPI MAST E R MODE TIMING (CKE = 0, SMP = 0)
Note: Refer to Figure 25-2 for load conditions.
US125
US126
CK
DT
TABLE 25-10: USART SYNCHRONOUS RECEIVE REQUIREMENTS
S tandard Operating Conditi ons (unle ss othe rwis e stated)
Operati ng Temperatu re -40°C TA +125°C
Param.
No. Symbol Characteristic Min. Max. Units Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK (DT hold time) 10 — ns
US126 TCKL2DTL Data-hold after CK (DT hold time) 15 — ns
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP70
SP71 SP72
SP73 SP74
SP75, SP76
SP78
SP79
SP80
SP79
SP78
MSb LSb
bit 6 - - - - - -1
MSb In LSb In
bit 6 - - - -1
Note: Refer to Figure 25-2 for load conditions.
2010-2011 Microchip Technology Inc. DS41418B-page 227
PIC16(L)F707
FIGURE 25-17 : SPI MAST E R MODE TIMING (CKE = 1, SMP = 1)
FIGURE 25-18 : SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP81
SP71 SP72
SP74
SP75, SP76
SP78
SP80
MSb
SP79
SP73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 25-2 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
SP70
SP71 SP72
SP73
SP74
SP75, SP76 SP77
SP78
SP79
SP80
SP79
SP78
MSb LSb
bit 6 - - - - - -1
MSb In bit 6 - - - -1 LSb In
SP83
Note: Refer to Figure 25-2 for load conditions.
2010-2011 Microchip Technology Inc. DS41418B-page 229
PIC16(L)F707
FIGURE 25-20 : I2C™ BUS START/STOP BITS TIMING
TABLE 25-11: SPI MODE REQUIREMENTS
Param
No. Symbol Characteristic Min. Typ† Max. Units Conditions
SP70* TSSL2SCH,
TSSL2SCLSS to SCK or SCK input TCY ——ns
SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns
SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns
SP73* TDIV2SCH,
TDIV2SCLSetup time of SDI data input to SCK edge 100 — — ns
SP74* TSCH2DIL,
TSCL2DILHold time of SDI data input to SCK edge 100 — — ns
SP75* TDOR SDO data output rise time 3.0- 5.5V — 10 25 ns
1.8-5.5V — 25 50 ns
SP76* TDOF SDO data output fall time — 10 25 ns
SP77* TSSH2DOZSS to SDO output high-impedance 10 — 50 ns
SP78* TSCR SCK output rise time
(Master mode) 3.0-5.5V — 10 25 ns
1.8-5.5V — 25 50 ns
SP79* TSCF SCK output fall time (Master mode) — 10 25 ns
SP80* TSCH2DOV,
TSCL2DOVSDO data output valid after
SCK edge 3.0-5.5V — — 50 ns
1.8-5.5V — — 145 ns
SP81* TDOV2SCH
,
TDOV2SCL
SDO data output setup to SCK edge Tcy — — ns
SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns
SP83* TSCH2SSH,
TSCL2SSHSS after SCK edge 1.5TCY +
40 ——ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3 .0V, 25°C unless oth erwis e s t ated. These parameters are for design g uid anc e
only and are not tested.
Note: Refer to Figure 25-2 for load conditions.
SP91
SP92
SP93
SCL
SDA
Start
Condition Stop
Condition
SP90
PIC16(L)F707
DS41418B-page 230 2010-2011 Microchip Technology Inc.
FIGURE 25-21 : I2C™ BUS DATA TIMING
TABLE 25-12: I2C™ BUS START/STOP BITS REQUIREMENTS
Param
No. Symbol Characteristic Min. Typ Max. Units Conditions
SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Start condition
Setup time 400 kHz mode 600 — —
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
clock pulse is generated
Hold time 400 kHz mode 600 — —
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.
Note: Refer to Figure 25-2 for load conditions.
SP90
SP91 SP92
SP100 SP101
SP103
SP106 SP107
SP109 SP109 SP110
SP102
SCL
SDA
In
SDA
Out
2010-2011 Microchip Technology Inc. DS41418B-page 231
PIC16(L)F707
TABLE 25-13: I2C™ BUS DATA REQUIREMENTS
Param.
No. Symbol Characteristic Min. Max. Units Conditions
SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP Module 1.5TCY —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP Module 1.5TCY —
SP102* TRSDA and SCL rise
time 100 kHz mode — 1000 ns
400 kHz mode 20 +
0.1CB300 ns CB is specifie d to be fr om
10-400 pF
SP103* TFSDA and SCL fall
time 100 kHz mode — 250 ns
400 kHz mode 20 +
0.1CB250 ns CB is specifie d to be fr om
10-400 pF
SP106* THD:DAT Data input hold
time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup
time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
SP109* TAA Output valid from
clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s T ime the bus must be free
before a new transmis-
si on can start
400 kHz mode 1.3 — s
SP111 CBBus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but
the require ment TSU:DAT 250 ns must the n be met. Thi s will auto mat ically be the ca se if the de vice do es
not stretc h the low pe riod of the SCL sig nal. If such a device does s tretch the lo w period of th e SCL signal,
it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to
the Standard mode I2C bus specification), before the SCL line is released.
PIC16(L)F707
DS41418B-page 232 2010-2011 Microchip Technology Inc.
FIGURE 25-22: CAP SENSE OSCILLATOR
TABLE 25-14: CAP SENSE OSCILLATOR SPECIFICATIONS
Param.
No. Symbol Characteristic Min. Typ† Max. Units Conditions
CS01 ISRC Current Source High — -5.8 -6 A-40, -85°C
Medium — -1.1 -3.2 A
Low — -0.2 -0.9 A
CS02 ISNK Current Sink High — 6.6 6 A-40, -85°C
Medium — 1.3 3.2 A
Low — 0.24 0.9 A
CS03 VCHYST Cap Hysteresis High — 525 — mV VCTH-VCTL
Medium — 375 — mV
Low — 280 — mV
* These parameters are characterized but not tested.
† Data in “Typ” column is a t 3.0V, 25°C unle ss otherwise stated. These parameters are for de si gn g uidance
only and are not tested.
ISRC
VCTH
VCTL
ISNK
EnabledEnabled
2010-2011 Microchip Technology Inc. DS41418B-page 233
PIC16(L)F707
26.0 DC AND AC CHARACTERIS TICS GRAPHS AND CHARTS
“Typical” represents the mean of the distribution at 25
C. “Maximum” or “minimum” represents (mean + 3
) or
(mean - 3
) respectively, where
is a standard deviation, over the whole temperature range.
FIGURE 26-1: PIC16F70 7 MA XIM UM IDD vs. FOSC OVER VDD, EC MOD E , VCAP = 0.1µF
Note: The gra phs an d tables pro vi ded f oll owin g this note are a s tatistica l s um mar y ba sed on a limite d nu mb er of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
1.8V
2.5V
3V
3.6V
5V
0.00
200.00
400.00
600.00
800.00
1,000.00
1,200.00
1,400.00
1,600.00
1,800.00
2,000.00
2,200.00
1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz
VDD (V)
Typic al: Sta tisti ca l Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
PIC16(L)F707
DS41418B-page 234 2010-2011 Microchip Technology Inc.
FIGURE 26-2: PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, EC MODE
FIGURE 26-3: PIC16F70 7 TYPICAL IDD vs. FOSC OVER VDD, EC MODE, VCAP = 0.1µF
1.8V
2V
2.5V
3V
3.3V
3.6V
0
200
400
600
800
1,000
1,200
1,400
1,600
1,800
2,000
2,200
2,400
1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(- 40°C to 125°C)
FOSC
IDD (µA)
1.8V
2.5V
3V
3.6V
5V
0
200
400
600
800
1,000
1,200
1,400
1,600
1,800
2,000
1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz
Typica l: Statisti ca l Mean @25° C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
FOSC
IDD (µA)
2010-2011 Microchip Technology Inc. DS41418B-page 235
PIC16(L)F707
FIGURE 26-4: PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, EC MODE
FIGURE 26-5: PIC16F70 7 MA XIM UM IDD vs. VDD OVER FOSC, EXTRC MODE, VCAP = 0.1µF
1.8V
2V
2.5V
3V
3.3V
3.6V
0
200
400
600
800
1,000
1,200
1,400
1,600
1,800
2,000
2,200
1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
FOSC
1 MHz
4 MHz
0
100
200
300
400
500
600
1.8 2 2.5 3 3.3 3.6 4.2 4.5 5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40 °C to 125°C)
IDD (µA)
VDD (V)
PIC16(L)F707
DS41418B-page 236 2010-2011 Microchip Technology Inc.
FIGURE 26-6: PIC16LF707 MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE
FIGURE 26-7: PIC16F70 7 TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE, VCAP = 0.1µF
1 MHz
4 MHz
0
50
100
150
200
250
300
350
400
450
500
1.8 2 2.5 3 3.3 3.6
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
VDD (V)
1 MHz
4 MHz
0
50
100
150
200
250
300
350
400
450
1.8 2 2.5 3 3.3 3.6 4.2 4.5 5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
VDD (V)
IDD (µA)
2010-2011 Microchip Technology Inc. DS41418B-page 237
PIC16(L)F707
FIGURE 26-8: PIC16LF707 TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE
FIGURE 26-9: PIC16F70 7 MA XIM UM IDD vs. FOSC OVER VDD, HS MOD E , VCAP = 0.1µF
1 MHz
4 MHz
0
50
100
150
200
250
300
350
400
450
1.8 2 2.5 3 3.3 3.6
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
VDD (V)
IDD (µA)
3V
3.6V
4.5V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Fosc
IDD (mA)
5V
PIC16(L)F707
DS41418B-page 238 2010-2011 Microchip Technology Inc.
FIGURE 26-10: PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, HS MODE
FIGURE 26-11: PIC16F707 TYPICAL IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1µF
2.5V
3V
3.6V
0.00
0.50
1.00
1.50
2.00
2.50
4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Fosc
IDD (mA)
3.3V
3V
3.6V
4.5V
0.00
0.50
1.00
1.50
2.00
4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Fosc
IDD (mA)
5V
2010-2011 Microchip Technology Inc. DS41418B-page 239
PIC16(L)F707
FIGURE 26-12: PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, HS MODE
FIGURE 26-13 : PIC16F 70 7 MAXIM U M IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1µF
2.5V
3V
3.3V
0.00
0.50
1.00
1.50
2.00
2.50
4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (mA)
Fosc
3.6V
1 MHz
4 MHz
0
100
200
300
400
500
600
1.8 2 2.5 3 3.3 3.6 4.2 4.5 5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
VDD (V)
PIC16(L)F707
DS41418B-page 240 2010-2011 Microchip Technology Inc.
FIGURE 26-14: PIC16LF707 MAXIMUM IDD vs. VDD OVER FOSC, XT MODE
FIGURE 26-15 : PIC16F 70 7 TY PICA L IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1µF
1 MHz
4 MHz
0
100
200
300
400
500
600
1.8 2 2.5 3 3.3 3.6
IDD (µA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
VDD (V)
1 MHz
4 MHz
0
100
200
300
400
500
600
1.8 2 2.5 3 3.3 3.6 4.2 4.5 5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
VDD (V)
2010-2011 Microchip Technology Inc. DS41418B-page 241
PIC16(L)F707
FIGURE 26-16: PIC16LF707 TYPICAL IDD vs. VDD OVER FOSC, XT MOD E
FIGURE 26-17 : PIC16F 70 7 IDD vs. VDD, LP MODE, VCAP = 0.1µF
1 MHz
4 MHz
0
100
200
300
400
500
600
1.8 2 2.5 3 3.3 3.6
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
VDD (V)
32 kHz Typical
32 kHz Maximum
10.0
12.5
15.0
17.5
20.0
1.8 3 5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
VDD (V)
VDD (V)
PIC16(L)F707
DS41418B-page 242 2010-2011 Microchip Technology Inc.
FIGURE 26-18 : PIC16L F70 7 IDD vs. VDD, LP MODE
FIGURE 26-19 : PIC16F 70 7 MAXIM U M IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF
32 kHz Typical
32 kHz Maximum
5
10
15
20
25
30
1.8 3 3.3 3.6
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
VDD (V)
110
120
130
140
150
160
170
180
190
200
210
62.5 kHz 125 kHz 250 kHz 500 kHz
5V
3.6V
1.8V
2.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
FOSC
IDD (µA)
2010-2011 Microchip Technology Inc. DS41418B-page 243
PIC16(L)F707
FIGURE 26-20: PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE
FIGURE 26-21 : PIC16F 70 7 MAXIM U M IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF
1.8V
2.5V
3V
3.6V
100
110
120
130
140
150
160
170
62.5 kHz 125 kHz 250 kHz 500 kHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
FOSC
IDD (µA)
0
200
400
600
800
1,000
1,200
1,400
1,600
1,800
2,000
2 MHz 4 MHz 8 MHz 16 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
FOSC
1.8V
2.5V
5V
3.6V
PIC16(L)F707
DS41418B-page 244 2010-2011 Microchip Technology Inc.
FIGURE 26-22: PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE
FIGURE 26-23 : PIC16F 70 7 TY PICA L IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0. 1µF
1.8V
2.5V
3V
3.6V
0
250
500
750
1,000
1,250
1,500
1,750
2,000
2,250
2 MHz 4 MHz 8 MHz 16 MHz
s
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
FOSC
1.8V
2.5V
3.6V
5V
80
90
100
110
120
130
140
150
160
62.5 kHz 125 kHz 250 kHz 500 kHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
FOSC
2010-2011 Microchip Technology Inc. DS41418B-page 245
PIC16(L)F707
FIGURE 26-24: PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE
FIGURE 26-25 : PIC16F 70 7 TY PICA L IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0. 1µF
3.6V
1.8V
2.5V
3V
70
80
90
100
110
120
130
140
62.5 kHz 125 kHz 250 kHz 500 kHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
FOSC
1.8V
2.5V
3.6V
5V
0
200
400
600
800
1,000
1,200
1,400
1,600
1,800
2,000
2 MHz 4 MHz 8 MHz 16 MHz
Typical: S tatistical Mean @25°C
Maximu m: Mean (Worst-Case Tem p) + 3
(-40°C to 125°C)
IDD (µA)
FOSC
PIC16(L)F707
DS41418B-page 246 2010-2011 Microchip Technology Inc.
FIGURE 26-26: PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE
FIGURE 26-27 : PIC16F 70 7 MAXIM UM BASE IPD vs. VDD, VCAP = 0.1µF
3.6V
1.8V
2.5V
3V
0
200
400
600
800
1,000
1,200
1,400
1,600
1,800
2,000
2 MHz 4 MHz 8 MHz 16 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IDD (µA)
VDD (V)
85°C
125°C
0
5
10
15
20
25
1.8V 2V 3V 3.6V 4V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
2010-2011 Microchip Technology Inc. DS41418B-page 247
PIC16(L)F707
FIGURE 26-28: PIC16LF707 MAXIMUM BASE IPD vs. VDD
FIGURE 26-29: PIC16F707 TYPICAL BASE IPD vs. VDD, VCAP = 0.1µF
125°C
85°C
0
1
2
3
4
5
6
7
1.8V 2V 2.5V 3V 3.6V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
25°C
2
3
4
5
6
7
8
1.8V 2V 3V 3.6V 4V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
PIC16(L)F707
DS41418B-page 248 2010-2011 Microchip Technology Inc.
FIGURE 26-30: PIC16LF707 TYPICAL BASE IPD vs. VDD
FIGURE 26-31: PIC16F707 FIXED VOLTAGE REFERENCE IPD vs. VDD, VCAP = 0.1µF
25°C
0
50
100
150
200
250
1.8V 2V 2.5V 3V 3.6V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (nA)
VDD (V)
Typ. 25°C
Max. 125°C
Max. 85°C
0
10
20
30
40
50
60
70
1.8V 2V 3V 3.6V 5V 5.5V
Typical: Statistical Mean @25°C
Maxi mum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
2010-2011 Microchip Technology Inc. DS41418B-page 249
PIC16(L)F707
FIGURE 26-32: PIC16LF707 FIXED VOLTAGE REFERENCE IPD vs. VDD
FIGURE 26-33: PIC16F707 BOR IPD vs. VDD, VCAP = 0.1µF
Typ. 25°C
Max. 125°C
Max. 85°C
0
5
10
15
20
25
1.8V 2V 2.5V 3V 3.6V
Typica l: Statisti ca l Mean @25° C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
Typ. 25°C
Max. 125°C
Max. 85°C
0
10
20
30
40
50
60
70
2V 3V 3.6V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
PIC16(L)F707
DS41418B-page 250 2010-2011 Microchip Technology Inc.
FIGURE 26-34: PIC16LF707 BOR IPD vs. VDD
FIGURE 26-35: PIC16F707 CAP SENSE HIGH POWER IPD vs. VDD, VCAP = 0.1µF
Typ. 25°C
Max. 125°C
Max. 85°C
0
5
10
15
20
25
30
2V 2.5V 3V 3.6V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
Typ. 25°C
Max. 125°C
Max. 85°C
0
10
20
30
40
50
60
70
1.8V 2V 3V 3.6V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
2010-2011 Microchip Technology Inc. DS41418B-page 251
PIC16(L)F707
FIGURE 26-36: PIC16LF707 CAP SENSE HIGH POWER IPD vs. VDD
FIGURE 26-37: PIC16F707 CAP SENSE MEDIUM POWER IPD vs. VDD, VCAP = 0.1µF
Typ. 25°C
Max. 125°C
Max. 85°C
0
10
20
30
40
50
60
1.8V 2V 2.5V 3V 3.6V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
Typ. 25°C
Max. 125°C
Max. 85°C
0
5
10
15
20
25
30
1.8V 2V 3V 3.6V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(- 40°C to 125°C)
IPD (µA)
VDD (V)
PIC16(L)F707
DS41418B-page 252 2010-2011 Microchip Technology Inc.
FIGURE 26-38: PIC16LF707 CAP SENSE MEDIUM POW ER IPD vs. VDD
FIGURE 26-39: PIC16F707 CAP SENSE LOW POWER IPD vs. VDD, VCAP = 0.1µF
Typ. 25°C
Max. 125°C
Max. 85°C
0
2
4
6
8
10
12
14
16
18
20
1.8V 2V 2.5V 3V 3.6V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
Typ. 25°C
Max. 125°C
Max. 85°C
0
5
10
15
20
25
30
1.8V 2V 3V 3.6V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
2010-2011 Microchip Technology Inc. DS41418B-page 253
PIC16(L)F707
FIGURE 26-40: PIC16LF707 CAP SENSE LOW POWER IPD vs. VDD
FIGURE 26-41: PIC16F707 T1OSC 32 kHz IPD vs. VDD, VCAP = 0.1µF
Typ. 25°C
Max. 125°C
Max. 85°C
0
2
4
6
8
10
12
14
16
18
1.8V 2V 2.5V 3V 3.6V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40 °C to 125°C)
IPD (µA)
VDD (V)
Typ. 25° C
Max. 85°C
0
2
4
6
8
10
12
14
16
1.8V 2V 3V 3.6V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
PIC16(L)F707
DS41418B-page 254 2010-2011 Microchip Technology Inc.
FIGURE 26-42: PIC16LF707 T1OSC 32 kHz IPD vs. VDD
FIGURE 26-43: PIC16F707 TYPICAL ADC IPD vs. VDD, VCAP = 0.1µF
Typ.
Max. 85°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1.8V 2V 2.5V 3V 3.6V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
Typ. 25°C
5.0
5.5
6.0
6.5
7.0
7.5
1.8V 2V 3V 3.6V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
2010-2011 Microchip Technology Inc. DS41418B-page 255
PIC16(L)F707
FIGURE 26-44: PIC16LF707 TYPICAL ADC IPD vs. VDD
FIGURE 26-45: PIC16F707 ADC IPD vs. VDD, VCAP = 0.1µF
Typ. 25°C
0
50
100
150
200
250
1.8V 2V 2.5V 3V 3.6V
Typical: Statistical Mean @25°C
Maxim um: Mean (Wor st -C ase Temp) + 3
(-40°C to 125°C)
IPD (nA)
VDD (V)
Max. 85°C
Max. 125°C
5
10
15
20
25
1.8V 2V 3V 3.6V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
PIC16(L)F707
DS41418B-page 256 2010-2011 Microchip Technology Inc.
FIGURE 26-46: PIC16LF707 ADC IPD vs. VDD
FIGURE 26-47: PIC16F707 WDT IPD vs. VDD, VCAP = 0.1µF
Max. 85°C
Max. 125°C
0
1
2
3
4
5
6
7
8
1.8V 2V 2.5V 3V 3.6V
Typical: Statistical Mean @25°C
Maximu m: Me an (Wor st-C a se Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
Typ. 25°C
Max. 85°C
0
2
4
6
8
10
12
14
16
18
1.8V 2V 3V 3.6V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40 °C to 125°C)
IPD (µA)
VDD (V)
2010-2011 Microchip Technology Inc. DS41418B-page 257
PIC16(L)F707
FIGURE 26-48: PIC16LF707 WDT IPD vs. VDD
FIGURE 26-49: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
Typ. 25°C
Max. 85°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.8V 2V 2.5V 3V 3.6V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (µA)
VDD (V)
Max. -40°
Typ. 25°
Min. 125 °
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.8 3.6 5.5
Maximu m: Me an + 3 (-40°C to 125°C)
Minimum: Mean - 3 (-40°C to 125°C)
VIN (V)
VDD (V)
Typical: Mean @25°C
PIC16(L)F707
DS41418B-page 258 2010-2011 Microchip Technology Inc.
FIGURE 26-50: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
FIGURE 26-51: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
VIHMin. 125°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.8 3.6 5.5
VIN (V)
VDD (V)
VIHMax. -40°C
Maximum: Mean + 3 (-40°C to 125°C)
Minimum: Mean - 3 (-40°C to 125°C)
Typical: Mean @25° C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
1.8 3.6 5.5
VIN (V)
VDD (V)
VIL Min. 125°C
VIL Max. -40°C
Maximu m: Mea n + 3 (-40°C to 125°C)
Minimum: Mean - 3 (-40°C to 125°C)
Typical: Mean @25°C
2010-2011 Microchip Technology Inc. DS41418B-page 259
PIC16(L)F707
FIGURE 26-52 : VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V
FIGURE 26-53 : VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V
Max. -40°
Min. 125°
Typ. 25°
5
5.1
5.2
5.3
5.4
5.5
5.6
-5.0-4.2-3.4-2.6-1.8-1.0-0.2
Maximum: Mean + 3 (-40°C to 125°C)
Minimu m: Me an - 3 (-40°C to 125°C)
Typical: Mean @25°C
VOH (V)
IOH (mA)
2.6
2.8
3
3.2
3.4
3.6
3.8
-5.0-4.2-3.4-2.6-1.8-1.0-0.2
Maxi mum: Mean + 3 (-40°C to 125°C)
Minimum: Mean - 3 (-40°C to 125°C)
Typical: Mean @25°C
VOH (V)
IOH (mA)
Max. -40°
Typ. 25°
Min. 125°
PIC16(L)F707
DS41418B-page 260 2010-2011 Microchip Technology Inc.
FIGURE 26-54 : VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V
FIGURE 26-55 : VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-2.0-1.8-1.6-1.4-1.2-1.0-0.8-0.6-0.4-0.20.0
VOH (V)
IOH (mA)
Max. -40°
Typ. 25°
Min. 125°
Maxi mum: Mean + 3 (-40°C to 125°C)
Minimum: Mean - 3 (-40°C to 125°C)
Typical: Me an @25° C
Min. -40°
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
5.0 6.0 7.0 8.0 9.0 10.0
VOL (V)
IOL (mA )
Max. 125°
Typ. 25°
Maxi mum: Mean + 3 (-40°C to 125°C)
Minimum: Mean - 3 (-40°C to 125°C)
Typical: Mean @25°C
2010-2011 Microchip Technology Inc. DS41418B-page 261
PIC16(L)F707
FIGURE 26-56 : VOL vs. IOL OVER TEMPERATURE, VDD = 3.6
FIGURE 26-57 : VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V
Min. -40°
Typ. 25°
Max. 125°
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
4.0 5.0 6.0 7.0 8.0 9.0 10.0
Maximu m: Me an + 3 (-40°C to 125° C)
Minimum: Mean - 3 (-40°C to 125°C)
Typical: Mean @25°C
VOL (V)
IOL (mA)
0
0.2
0.4
0.6
0.8
1
1.2
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
Maxi mum: Mean + 3 (-40°C to 125°C)
Minimum: Mean - 3 (-40°C to 125°C)
T ypical: Mean @25°C
VOL (V)
IOL (mA)
Max. 125°
Min. -40°
PIC16(L)F707
DS41418B-page 262 2010-2011 Microchip Technology Inc.
FIGURE 26-58 : PIC16F 70 7 PWR T PERIO D
FIGURE 26-59: PIC16F707 WDT TIME-OUT PERIOD
Max. -40°C
Min. 125°C
45
55
65
75
85
95
105
1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V 5.5V
TIME (ms)
VDD
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Typ. 25°C
Typ. 25°C
Max. -40°C
Min. 125°C
10.00
12.00
14.00
16.00
18.00
20.00
22.00
24.00
1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
TIME (ms)
VDD
2010-2011 Microchip Technology Inc. DS41418B-page 263
PIC16(L)F707
FIGURE 26-60 : PIC16F 70 7 HFIN TOSC WAKE-UP FR OM SLEEP START-U P TIME
FIGURE 26-61: PIC16F707 A/D INTERNAL RC OSCILLATOR PERIOD
Max.
Typ.
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.8V 2V 3V 3.6V 4V 4.5V 5V 5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
TIME (us)
VDD
Max.
Min.
0.0
1.0
2.0
3.0
4.0
5.0
6.0
1.8V 3.6V 5.5V
Typical: S tatistical Mean @25°C
Maximu m: Me an (Wor st-C a se Temp) + 3
(-40°C to 125°C)
Period (µs)
VDD(V)
PIC16(L)F707
DS41418B-page 264 2010-2011 Microchip Technology Inc.
FIGURE 26-62: PIC16F707 CAP SENSE OUTPUT CURRENT, POWER MODE = HIGH
FIGURE 26-63: PIC16F707 CAP SENSE OUTPUT CURRENT, POWER MODE = MEDIUM
-15000
-10000
-5000
0
5000
10000
15000
20000
1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5
Current (nA)
VDD(V)
Min. Sink -40°C
Typ. Sink 25°C
Max. Sink 85°C
Min. Source 85°C
Typ. Source 25°C
Max. Source -40°C
-3000
-2000
-1000
0
1000
2000
3000
1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5
Current (nA)
VDD(V)
Max. Sink -40°C
Typ. Sink 25°C
Min. Sink 85°C
Min. Source 85°C
Typ. Source 25°C
Max. Source -40°C
2010-2011 Microchip Technology Inc. DS41418B-page 265
PIC16(L)F707
FIGURE 26-64: PIC16F707 CAP SENSE OUTPUT CURRENT, POWER MODE = LOW
FIGURE 26-65: PIC16F707 CAP SENSOR HYSTERESIS, POWER MODE = HIGH
-800
-600
-400
-200
0
200
400
600
1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5
Current (nA)
VDD(V)
Max. Sink 85°C
Typ. Sink 25°C
Min. Sink -40°C
Min. Source 85°C
Typ. Sour ce 25° C
Max. Source -40°C
300
400
500
600
700
1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5
Max. 125°C
Max. 85°C
Typ. 25°C
Min. 0°C
Min. -40°C
mV
VDD(V)
PIC16(L)F707
DS41418B-page 266 2010-2011 Microchip Technology Inc.
FIGURE 26-66: PIC16F707 CAP SENSOR HYSTERESIS, POWER MODE = MEDIUM
FIGURE 26-67: PIC16F707 CAP SENSOR HYSTERESI S, POWER MODE = LOW
250
300
350
400
450
500
550
1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5
Max. 125°C
Typ. 25°C
Min. 0°C
Min. -40°C
mV
VDD(V)
Max. 85°C
150
200
250
300
350
400
450
1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5
Max. 125°C
Max. 85°C
Typ. 25°C
Min. 0°C
mV
VDD(V)
Min -40°C
2010-2011 Microchip Technology Inc. DS41418B-page 267
PIC16(L)F707
FIGURE 26-68: TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V
FIGURE 26-69: TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25°C
-1.5
-1
-0.5
0
0.5
1
1.5
1.8 2.5 3 3.6 4.2 5.5
Voltage
Percent Change (%)
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
-40 0 45 85 125
Temperature (°C)
Percent Change (%)
PIC16(L)F707
DS41418B-page 268 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 269
PIC16(L)F707
27.0 PACKAGING INFORMATION
27.1 Package Marking Information
*Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event th e full Mi crochip p a rt numbe r canno t be marke d on one line , it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
40-Lead PDIP (600 mil) Example
XXXXXXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
44-Lead QFN (8x8x0.9 mm) Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
PIN 1 PIN 1
44-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
XXXXXXXXXX
PIC16F707
3
e
10033K1
-I/P
PIC16F707
3
e
-I/ML
10033K1
3
e
PIC16F707
10033K1
-I/PT
PIC16(L)F707
DS41418B-page 270 2010-2011 Microchip Technology Inc.
*Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event th e full Mi crochip p a rt numbe r canno t be marke d on one line , it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
40-Lead UQFN (5x5x0.5 mm) Example
PIN 1 PIN 1
PIC16F707
10033K1
-I/MV
3
e
2010-2011 Microchip Technology Inc. DS41418B-page 271
PIC16(L)F707
27.2 Package Details
The following sections give the technical details of the packages.
N
NOTE 1
E1
D
123
A
A1 b1
be
c
eB
E
L
A2
PIC16(L)F707
DS41418B-page 272 2010-2011 Microchip Technology Inc.
!"#$%&'& !
DEXPOSED
PAD
D2
e
b
K
L
E2
2
1
N
NOTE 1
2
1
E
N
BOTTOM VIEW
TOP VIEW
A3 A1
A
2010-2011 Microchip Technology Inc. DS41418B-page 273
PIC16(L)F707
!"#$%&'& !
PIC16(L)F707
DS41418B-page 274 2010-2011 Microchip Technology Inc.
() !*#(+'+'+",-( !
A
E
E1
D
D1
e
b
NOTE 1 NOTE 2
N
123
c
A1
L
A2
L1
α
φ
β
2010-2011 Microchip Technology Inc. DS41418B-page 275
PIC16(L)F707
() !*#(+'+'+",-( !
PIC16(L)F707
DS41418B-page 276 2010-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2011 Microchip Technology Inc. DS41418B-page 277
PIC16(L)F707
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16(L)F707
DS41418B-page 278 2010-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2011 Microchip Technology Inc. DS41418B-page 279
PIC16(L)F707
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (4/2010)
Original release of this data sheet.
Revision B (4/2011)
Updated the data sheet to new format; Added 40-Pin
UQFN diagram; Updated Table 1 and Table 25-5;
Added 40-Lead UQFN Package Marking Information
and Package Details; Other minor corrections.
APPENDIX B: MIGRATING FROM
OTHER PIC®
DEVICES
This discusses some of the issues in migrating from
other PIC® de vices to t he PIC16F707 family of devices.
B.1 PIC16F77 to PIC16F707
Note: This device has been designed to perform
to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performan ce c haracte ristic s tha n it s eal ier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.
Note: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capacitor
values and/or the oscillator mode may be
required.
TABLE B-1: FEATURE COMPARISON
Feature PIC16F77 PIC16F707
Max. Operating Speed 20 M Hz 20 MHz
Max. Program
Memory (Words) 8K 8K
Max. SRAM (Bytes) 368 363
A/D Resolution 8-bit 8-bit
Timers (8/16-bit) 2/1 4/2
Oscillator Modes 4 8
Brown-out Reset Y Y
Internal Pull -up s RB<7:0> RB<7:0>
Interrupt-on-change RB<7:4> RB<7:0>
Comparator 0 0
USART Y Y
Extended WDT N N
Software Control
Option of WDT/BOR NN
INTOSC Frequencies None 500 kHz -
16 MHz
Clock Switch in g N N
PIC16(L)F707
DS41418B-page 280 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 281
PIC16(L)F707
INDEX
A
A/D Specifications....................................................223, 224
Absolute Maximum Ratings..............................................203
AC Characteristics
Industrial and Extended............................................215
Load Conditions...................... ....... .. .. .... .. .. .. ....... .. .. ..214
ADC ....................................................................................81
Acquisition Requirements ................ .... .... .... ........... ....88
Associ a te d registers................................... .................90
Block Diag ram................... ............... ..................... ......81
Calculating Acquisition Time.......................................88
Channel Selection........................................ ....... .... ....82
Configuration...............................................................82
Configuring Interrupt...................................................84
Conversi o n Clo ck............ ............... ..................... ........82
Conversion Procedure ......................... .... .... ......... .. ....84
Internal Sampling Switch (RSS) IMPEDANCE ................88
Interrupts.....................................................................83
Operation....................................................................84
Operation During Sleep ..............................................84
Port Configuration.......................................................82
Reference Voltage (VREF)...........................................82
Source Impedance.............. .... ............. .... ............. .... ..88
Special Event Trigger..................................................84
ADCON0 Register .........................................................21, 86
ADCON1 Register .........................................................22, 87
Addressable Universal Synchronous Asynchronous
Receive r Tr a n smitter (AUSAR T).......... ............... ......139
ADRES Register.................................................................87
ADRESH Register...............................................................21
Alternate Pin Function.........................................................53
Analog-to-Digital Converter. See AD C
ANSELA Re g i ster .............................. ........................... ......55
ANSELB Re g i ster .............................. ...........................59, 62
ANSELD Register...............................................................65
ANSELE Re g i ster .............................. ........................... ......68
APFCON Register...............................................................53
Assembler
MPASM Assembler...................................................200
AUSART ...........................................................................139
Associated Registers
Baud Rate Generator........................................149
Asynchronous Mode.................................................141
Associated Registers
Receive.....................................................146
Transmit....................................................143
Baud Rate Generator (BRG) ............................149
Receiver............................................................143
Setting up 9-bit Mode with Address Detect .......145
Transmitter........................................................141
Baud Rate Generator (BRG)
Baud Rate Error, Calculating............. ........... ....149
Formulas...........................................................149
High Baud Rate Select (BRGH Bit) ..................149
Synchronous Master Mode... ................. ...... .....152, 156
Associated Registers
Receive.....................................................155
Transmit....................................................153
Reception..........................................................154
Transmission ....................................................152
Synchronous Slave Mode
Associated Registers
Receive .................................................... 157
Transmit ................................................... 156
Reception ......................................................... 157
Transmission.................................................... 156
B
BF bit ........................................................................ 167, 179
Block Diagrams
(CCP) Capture Mode Operation....................... ...... .. 131
ADC............................................................................ 81
ADC Transfer Function............................................... 89
Analog Input Model..................................................... 89
AUSART Receive..................................................... 140
AUSA R T Tran sm i t..... .. ..... ...... ...... ...... .. ..... ...... ...... ... 13 9
CCP PWM...... ..................... ..................... ................ 135
Clock Source.............................................................. 71
Compare................................................................... 133
Crys ta l Oper a ti o n..... ...... ..... ...... ...... ......... ...... ...... ...... . 75
Digital-to-Analog Converter (DAC). ............................ 94
External RC Mode...................................................... 76
Interrupt Logic ............................................................. 41
MCLR Circuit............ ............... ............... .................... 33
On-Chip Reset Circuit................................................. 31
Resonator Operation.................................................. 76
SPI Mode.................................................................. 160
SSP (I2C Mode)........................................................ 169
Timer1 ...................................................................... 102
Timer2 ...................................................................... 117
TMR0/WDT Prescaler ........................................ 97, 113
Voltage Reference....................... .. .... .. ......... .... .. .... .... 94
Voltage Reference Output Buffer Example ................ 94
Brown-out Reset (BOR)...................................................... 35
Specifications ........................................................... 221
Timing and Characteristics..................................... .. 220
C
C Compilers
MPLAB C18.............................................................. 200
Capacitive Sensing................................ .... .. ......... .... .... .... 119
Capture Module. See Capture/Compare /PWM (CCP)
Capture/Compare/PWM ( CCP)....... ............... ........ ........ .. 129
Associated registers w/ Capture............................... 132
Associ a te d registers w/ Comp a re........ ..................... 134
Associated registers w/ PWM................................... 138
Capture Mode........................................................... 131
CCPx Pin Configu ration............... ..................... ........ 131
Compare Mode......................................................... 133
CCPx Pin Configuration.................................... 133
Software Interrupt Mode........................... 131, 133
Special Event Trigger....................................... 133
Timer1 Mode Selection............................. 131, 133
Interaction of Two CCP Modules (table)................... 129
Prescaler .................................................................. 131
PWM Mode................... ............................ ................ 135
Duty Cycle........................................................ 136
Effects of Reset................................................ 137
Example PWM Frequencies and
Reso l u t i o n s , 2 0 MH Z.... ...... ..... ...... ...... ..... 1 3 7
Example PWM Frequencies and
Reso l u t i o n s , 8 MH z .... ...... ......... ...... ...... ... 13 7
Operation in Sleep Mode................................ .. 137
Setup for Operation.......................................... 137
System Clock Frequency Changes. ................. 137
PWM Period ............................................................. 136
PIC16(L)F707
DS41418B-page 282 2010-2011 Microchip Technology Inc.
Setup for PWM Operation.................... .....................137
Timer Resources.......................................................129
CCP. See Capture/Compare/PWM (CCP )
CCP1CON Regis te r. ............... ..................... .............. .........21
CCP2CON Regis te r. ............... ..................... .............. .........21
CCPR1H Registe r........ ............... ............... .............. ...........21
CCPR1L Regis te r... ............... .............. ..................... ...........21
CCPR2H Registe r........ ............... ............... .............. ...........21
CCPR2L Regis te r... ............... .............. ..................... ...........21
CCPxCON Regist e r ......... ............... ..................... .............130
CKE bit............................... ....... .. .... .. .. .... ....... .. .... .. ...167, 179
CKP bit............................... ....... .. .... .. .. .... ....... .. .... .. ...166, 178
Clock Sources
External Modes...........................................................75
EC.......................................................................75
HS.......................................................................75
LP........................................................................75
OST.....................................................................75
RC.......................................................................76
XT .......................................................................75
Code Examples
A/D Conversion............................. ............... ...............85
Call of a Subroutine in Page 1 from Page 0................28
Changing Between Capture Prescalers....................131
Indirect Addressing.....................................................29
Initializing PORTA.......................................................54
Initializing PORTB.......................................................57
Initializing PORTC.......................................................61
Initializing PORTD.......................................................64
Initializing PORTE.......................................................67
Loading the SSPBUF (SSPSR ) Register..................162
Saving W, STATUS and PCLATH R egisters in RAM .43
Compare Module. See Capture/Compare/ PW M (CCP)
CONFIG1 Register.................. .............. ..................... ...77, 78
Customer Change Notification Service .............................287
Custome r Notification Ser vice..... ............... .............. .........287
Customer Support........ .... ............. .... ...... ........... ...... .... .....287
D
D/A bit ................ ........................... ..................... ...............179
DACCON0 (Digital-to-Analog Converter Control 0)
Register.......................................................................95
DACCON1 (Digital-to-Analog Converter Control 1)
Register.......................................................................95
Data Memory.......................................................................19
Data/Ad d r e ss b i t (D /A)......................................................179
DC and AC Characteristics..................... ......... .. .... .... .......233
DC Characteristics
Extended and Industrial. ...........................................211
Industrial and Extended............................................204
Development Support .......................................................199
Device Configuration...........................................................77
Code Protection ..........................................................79
Configuration Word.....................................................77
User ID........................................................................79
Device Overview.................................................................13
Digital-to-Analog Converter (DAC)......................................93
Associ a te d Re g i sters........ .............. ..................... .......96
Effects of a Reset........................................................93
Operation During Sleep ..............................................93
E
EECON1 Regist e r........ ............... ..................... ............... ....24
Effects of Reset
PWM mode........................... ........................... .........137
Electrical Specifications ....................................................203
Enhanced Capture/Compare/PWM (ECCP)
Specifications ........................................................... 223
Errata.................................................................................. 11
F
Firmware Instructions ....................................................... 189
Fixed Voltage Reference. See FV R
FSR R e g i s ter ............ ..... ...... ...... ...... ..... ...... ...... ..... ...... . 21, 2 2
Fuses. See Configuration Bits
FVR..................................................................................... 91
FVRCON Register.............................................................. 92
G
General Purpose Register File ........................ ............. ...... 19
I
I2C Mode
Associated Registers................................................ 180
INDF Register............................................................... 21, 22
Indirect Addressing, INDF and FSR Registers ...................29
Instruction Format............................................................. 189
Instr uctio n Se t..... .. ...... ..... ...... .. ...... ..... ...... ...... ...... ..... .. ..... 189
ADDLW..................................................................... 191
ADDWF..................................................................... 191
ANDLW..................................................................... 191
ANDWF..................................................................... 191
MOVF ....................................................................... 194
BCF .......................................................................... 191
BSF........................................................................... 191
BTFSC...................................................................... 191
BTFSS...................................................................... 192
CALL......................................................................... 192
CLRF ........................................................................ 192
CLRW....................................................................... 192
CLRWDT .................................................................. 192
COMF....................................................................... 192
DECF........................................................................ 192
DECFSZ ................................................................... 193
GOTO ....................................................................... 193
INCF ......................................................................... 193
INCFSZ..................................................................... 193
IORLW...................................................................... 193
IORWF...................................................................... 193
MOVLW.................................................................... 194
MOVWF.................................................................... 194
NOP.......................................................................... 194
RETFIE..................................................................... 195
RETLW..................................................................... 195
RETURN................................................................... 195
RLF........................................................................... 196
RRF .......................................................................... 196
SLEEP...................................................................... 196
SUBLW..................................................................... 196
SUBWF..................................................................... 197
SWAPF..................................................................... 197
XORLW .................................................................... 197
XORWF .................................................................... 197
Summary Ta b l e...... ........................... ..................... ..190
INTCON Register................................................................ 44
Internal Oscillator Block
INTOSC
Specifications ................................................... 218
Internal Sampling Switch (RSS) IMPEDANCE........................ 88
Internet Address ........................... .................................... 287
Interrupts............................................................................. 41
ADC............................................................................ 84
2010-2011 Microchip Technology Inc. DS41418B-page 283
PIC16(L)F707
Associated registers w/ Interrupts...............................49
Config u ration Word w/ LDO....... ..................... ............51
Interrupt-on-Change....................................................57
Synchronous Serial Port Interrupt...............................48
INTOSC Specifications............. ............... ............... ..........218
IOCB Register........ ............... ..................... .........................59
L
Load Conditions....... .. ....... .. .. .. .... .. .. ....... .. .. .. .... .. .. ....... .. .. ..214
M
MCLR..................................................................................33
Internal........................................................................33
Memory Organization..........................................................19
Data ............................................................................19
Program......................................................................19
Microc h i p In ternet Web Sit e............................... ...............287
Migrating from other PIC Microcontroller Devices.............279
MPLAB ASM30 Assembler, Linker, Librarian ...................200
MPLAB Integrated Development Environment Software..199
MPLAB PM3 Device Programmer ....................................202
MPLAB REA L IC E In -Circuit Em u l a tor System............. ....201
MPLINK Object Linker/MPL IB Objec t Librarian........ ........200
O
OPCODE Fiel d Descr ip tions. ............... .............. ...............189
OPTION Register................................................................26
OPTION_R EG Re g i ster........ ..................... ..................... ....99
OSCCON Register..............................................................73
Oscillator
Associ a te d registers................................... .........76, 117
Oscillator Module
EC...............................................................................71
HS...............................................................................71
INTOSC ......................................................................71
INTOSCIO...................................................................71
LP................................................................................71
Oscillator Tuning.........................................................74
RC...............................................................................71
RCIO...........................................................................71
XT ...............................................................................71
Oscillator Parameters .......................................................218
Oscillator Specifications....................................................217
Oscillator Start-up Timer (OST)
Specifications............................................................221
OSCTUNE Regis te r.................. ..................... .....................74
P
P (Stop) bit........................................................................179
Packaging .........................................................................269
Marking.....................................................................269
PDIP Details..............................................................271
Pagin g , Program Memory........................ ...........................28
PCL and PCLATH...............................................................28
Computed GOTO........................................................28
Stack...........................................................................28
PCL Register .................................................................21, 22
PCLATH Register .............................. .............. .............21 , 22
PCON Register.......................................................2 2, 27, 36
PIE1 Register................................................................22, 45
PIE2 Register......................................................................22
Pinout Descriptions
PIC16F707/PIC16LF707.............................................15
PIR1 Regi ster............. ..................... ..................... .........21, 47
PIR2 Regi ster............. ..................... ..................... .........21, 48
PMADRH Register............................................................183
PMADRL Registe r...... ..................... ........ ............... .......... 183
PMCON1 Register.......... ............... .............. ............. 182, 183
PMDATH Register............................................................ 182
PMDA T L R e g i s ter.... .. ...... ...... ..... ...... ...... ...... ..... ...... ...... ... 182
PORTA ............................................................................... 54
ANSELA Register....................................................... 55
Associated Registers.................................................. 56
Pin Descriptions and Diagrams .................................. 55
PORT A R e g i s t e r...... ...... ..... .. ...... ...... .. ..... ...... .. ...... ..... 2 1
RA0............................................................................. 55
RA3............................................................................. 56
RA4............................................................................. 56
RA5............................................................................. 56
RA6............................................................................. 56
RA7............................................................................. 56
Specifications ........................................................... 219
PORTA Register................................................................. 54
PORTB ............................................................................... 57
Additional Pin Functions
ANSELB Re gister. ..................... ............. 57, 62, 67
Weak Pull-up...................................................... 57
Associated Registers.................................................. 60
Interrupt-on-Change ................................................... 57
P1B/P1C/P1D.See Enhanced Capture/Compare/
PWM+ (ECCP+)................................................. 57
Pin Descriptions and Diagrams .................................. 59
PORT B R e g i s t e r...... ...... ..... .. ...... ...... .. ..... ...... .. ...... ..... 2 1
RB0............................................................................. 59
RB1............................................................................. 59
RB2............................................................................. 59
RB3............................................................................. 60
RB4............................................................................. 60
RB5............................................................................. 60
RB6............................................................................. 60
RB7............................................................................. 60
PORTB Register................................................................. 58
PORTC............................................................................... 61
Associated Registers.................................................. 63
P1A.See Enhanced Capture/Compare/PWM+
(ECCP+)............................................................. 61
PORT C R e g i s te r.......... ..... ...... ...... .. ...... ..... ...... ...... ..... 2 1
RC0 ............................................................................ 62
RC2 ............................................................................ 63
RC3 ............................................................................ 63
RC4 ............................................................................ 63
RC5 ............................................................................ 63
RC6 ............................................................................ 63
RC7 ............................................................................ 63
Specifications ........................................................... 219
PORTC Register................................................................. 61
PORTD............................................................................... 64
Additional Pin Functions
ANSE L D R e gi s t e r.. ..... .. ...... ...... .. ..... ...... ...... ...... . 64
Associated Registers.................................................. 66
P1B/P1C/P1D.See Enhanced Capture/Compare/
PWM+ (ECCP+)................................................. 64
PORT D R e g i s te r.......... ..... ...... ...... .. ...... ..... ...... ...... ..... 2 1
RD6 ...................................................................... 65, 66
PORTD Register................................................................. 64
PORTE ............................................................................... 67
Associated Registers.................................................. 69
PORT E R e g i s t e r...... ...... ..... .. ...... ...... .. ..... ...... .. ...... ..... 2 1
RE0............................................................................. 68
RE1............................................................................. 68
RE2............................................................................. 68
PIC16(L)F707
DS41418B-page 284 2010-2011 Microchip Technology Inc.
RE3.............................................................................69
PORTE Register .................................................................67
Power-Down Mode (Sleep). . .............................................185
Associ a te d Re g i sters........ .............. ..................... .....186
Power-on Res e t............................ ..................... .................33
Power-up Timer (PWRT)......... .............. ..................... .........33
Specifications............................................................221
PR2 Register...............................................................22, 168
Precisio n In ternal Oscilla tor Paramete rs.............. .............218
Prescaler
Shared WDT/Timer0......... .............. ....................98, 114
Product Identification System............................................289
Program ..............................................................................19
Program Memory ................................................................19
Map and Stack (PIC16F707/PIC 16LF707) .................19
Paging.........................................................................28
Program Memory Read (PM R ) .........................................181
Associ a te d Re g i sters........ .............. ..................... .....183
Programming, Device Instructions....................................189
R
R/W bit..............................................................................179
RCREG.............................................................................145
RCREG Register.................................................................21
RCSTA Regis te r......... ............... .............. ....................21, 148
Reader Response.............................................................288
Read-Modify-Write Operations ..........................................189
Receive Overflow Indicator bit (SSPOV)...................166, 178
Registers
ADCON0 (ADC Control 0) ..........................................86
ADCON1 (ADC Control 1) ..........................................87
ADRES (ADC Result) .................................................87
ANSEL A ( PORTA An a l o g Se le ct)...............................55
ANSEL B ( PORTB An a l o g Select).........................59, 62
ANSELD (PORTD Analog Select) ..............................65
ANSEL E ( PORTE An a l o g Se le ct)...............................68
APFCON (Alternate Pin Function Control)..................53
CCPxCON (CCP Operatio n ).............. ........ ...............130
CONFIG1 (Configuration Word Register 1) ..........77, 78
DACCON0 ..................................................................95
DACCON1 ..................................................................95
FVRCON (Fixed Voltage Reference Register) ...........92
INTCON (Interrupt Control).........................................44
IOCB (Interrupt-on-Change PORTB)..........................59
OPTION_R EG (OPTION)....... ..................... ...............26
OPTION_R EG (Option) .............. ............................ ....99
OSCCON (Oscillator Control) .....................................73
OSCTUNE (Oscillator Tuning )................... ............... ..74
PCON (Power Control Register).................................27
PCON (Power Control) ...............................................36
PIE1 (Peripheral Interrupt Enable 1)...........................45
PIR1 (Peripheral Interrupt Register 1) ........................47
PIR2 (Peripheral Interrupt Request 2) ........................48
PMADRH (Program Memory Address High).............183
PMADRL (Program Memory Address Low)..............183
PMCON1 ( Pr o g ram Me mor y C o n trol 1)........ .. ......... .182
PMDATH (Program Memory Data High) ...................182
PMDATL (Program Memory Data Low)....................182
PORTA........................................................................54
PORTB........................................................................58
PORTC .......................................................................61
PORTD .......................................................................64
PORTE........................................................................67
RCSTA (Receive Status and Control). ......................148
Reset Values...... ............... ........................... ...............38
Reset Values (Special Registers)...............................40
SSPCON (Sy n c Serial Port Control) Registe r .. 166, 178
SSPSTAT (Sync Serial Port Status) Register... 167, 179
STATUS ..................................................................... 25
T2CON ..................................................................... 118
TRISA (Tri - State PO R TA).. ...... ..... .. .. ...... .. .. ..... .. ...... ... 5 4
TRISB (Tri - State PO R TB).. ...... ..... .. .. ...... .. .. ..... .. ...... ... 5 8
TRISC (Tri-State PORTC).......................................... 61
TRISD (Tri-State PORTD).......................................... 65
TRISE (Tri - State PO R TE).. ...... ..... .. .. ...... .. .. ..... .. ...... ... 6 8
TXSTA (Transmit Status and Control)...................... 147
WPUB (Wea k Pull-up PORTB)................................... 58
Reset .................................................................................. 31
Resets
Associated Registers.................................................. 40
Revision History................................................................ 279
S
S (Start) bit........................................................................ 179
SMP bit..................................................................... 167, 179
Software Simulator (MPLAB SIM) .................................... 201
SPBRG............................................................................. 149
SPBRG Register................................................................. 22
Special Event Trigger ......................................................... 84
Special Function Registers................................................. 19
SPI Mo d e.... .. ...... ...... ..... .. ...... ...... ..... ...... ...... ...... ..... ...... .. . 165
Associated Registers................................................ 168
Typical Master/Slave Connection............................. 159
SSP................................................................................... 159
I2C Mode .... .. ...... ..... .......... ...... ..... ...... ...... ..... ...... ..... 169
Acknowledge.................................................... 170
Addressing........................................................ 171
Cloc k Stret ch i n g ........ ...... ..... .. ...... ...... .. ..... ...... . 176
Cloc k Synch ro n i zati o n........ ...... ...... ...... . ...... ..... 1 7 7
Firmware Master Mode ..................................... 176
Hardware Setup................................................ 169
Multi-Master Mode............................................ 176
Reception ......................................................... 172
Sleep Operation. ............................................... 177
Start/Stop Conditions........................................ 170
Transmission.................................................... 174
Master Mode............................................................. 160
SPI Mo d e...... ...... . ...... ...... ...... .. ..... ...... ...... ..... ...... ..... 159
Slave Mode..... .............. ............................ ........163
Typical SPI Master/Slave Connection ...................... 159
SSPADD Regist e r.... ............... ............... .............. ............... 22
SSPBUF Register............................................................... 21
SSPCON Re g i ster ........... .. ...... .. ...... . ...... ...... ...... 21, 166, 17 8
SSPEN bit................................................................. 166, 178
SSPIF ................................................................................. 48
SSPM bits.. ........................... ..................... ............... 166 , 178
SSPO V b i t. .. .. ...... ...... ..... .. ...... .. ...... .. ..... ...... ...... .. ..... . 166, 1 7 8
SSPSTAT Regi ster..................... ..................... ... 22, 167, 179
STATUS Regi ster...... ..................... ..................... ............... 25
Synchronous Serial Port Enable bit (SSPEN) .......... 166, 178
Synchronous Serial Port Interrupt....................................... 48
Synchronous Serial Port Mode Select bits (SSPM).. 166, 178
T
T1CON Registe r........ ............... ............... ............... ...... 21, 22
T2CON Registe r.. ..................... ............... ........ ... 21, 118 , 168
Thermal Considerations .................................................... 213
Time-out Sequence ............................... .... .... .... ........... .... .. 36
Timer0................................................................................. 97
Associ a te d Re g i sters.. ............... ..................... .... 99, 115
Interrupt ...................................................................... 99
Operation...................... ........................... ... 98, 103, 114
2010-2011 Microchip Technology Inc. DS41418B-page 285
PIC16(L)F707
Specifications............................................................222
Timer1...............................................................................101
Asynchronous Counter Mode ...................................104
Reading and Writing .............. .. .. .... .. .. .. ..... .. .... ..104
Modes of Operation ........................... .... .... .. ......... ....103
Oscillator...................................................................104
Prescaler...................................................................104
Specifications............................................................222
TMR1H Register.......................................................101
TMR1L Register........................................................101
Timer2
Associ a te d registers................................... ...............118
Timers
Timer2
T2CON..............................................................118
Timing Diagrams
A/D Conversion............................ ..................... ........224
A/D Conversion (Sleep Mode) ..................................225
Asynchronous Reception..........................................146
Asynchronous Transmission.....................................142
Asynchronous Transmission (Back-to-Back)............143
Brown-out Reset (BOR)............................................220
Brown-out Reset Situations ........................................35
CLKOUT and I/O. . .....................................................218
Clock Synchronization ..............................................177
Clock Timing.............................................................215
Enhanced Capture/Compare/PWM (ECCP).............223
I2C Bus Data.............................................................230
I2C Bus Start/Stop Bits ..............................................229
I2C Recepti o n (7 -bit Addres s). ..................... .............172
I2C Slave Mode with SEN = 0 (Recept ion,
10-bit Address) .................................................173
I2C Tra n sm i s sion (7-bit Ad d r e ss)................ ..... ...... ...174
INT Pin Interrupt..........................................................42
Reset, WDT, OST and Power-up Timer ...................220
Slave Select Synchronization ...................................165
SPI Master Mode......................................................162
SPI Mast e r Mode (CKE = 1, SMP = 1) .....................22 7
SPI Mode (Slave Mode with CKE = 0)......................164
SPI Mode (Slave Mode with CKE = 1)......................164
SPI Slave Mode (CKE = 0) .......................................227
SPI Slave Mode (CKE = 1) .......................................228
Synchronous Reception (Master Mode, SREN) .......155
Synchronous Transmission.......................................153
Synchronous Transmission (T hrough TXEN) ...........153
Time-out Sequence
Case 1 ................................................................36
Case 2 ................................................................37
Case 3 ................................................................37
Timer0 and Timer1 External Clock ...........................222
USART Synchronous Receive (Master/Slave) .........226
USART Synchronous Transmission (Master/Slave).225
Wake-up from Interrupt.............................................186
Timing Pa rameter Symb o l o g y................................. ..........214
Timing Requirements
I2C Bus Data.............................................................231
I2C Bus Start /Stop Bits.............. ...............................230
SPI Mode..................................................................229
TMR0 Register....................................................................21
TMR1H Register...........................................................21, 22
TMR1L Register............................................................21, 22
TMR2 Register....................................................................21
TMRO Register.. ..................... ..................... ..................... ..23
TRISA .................................................................................54
TRISA Register.............................................................22, 54
TRISB................................................................................. 57
TRISB Register............................................................. 22, 58
TRISC................................................................................. 61
TRISC Regist e r......... .............. ............... ............... ........ 22, 61
TRISD................................................................................. 64
TRISD Regist e r......... .............. ............... ............... ........ 22, 65
TRISE................................................................................. 67
TRISE Register............................................................. 22, 68
TXREG ............................................................................. 141
TXREG Register................................................................. 21
TXSTA Reg ister........................... ............................... 22, 147
BRGH Bit.................................................................. 149
U
UA..................................................................................... 179
Update Address bit, UA.......... ......... .. .... .. .... ....... .... .. .... .... 179
USART
Synchronous Master Mode
Requirements, Synchronous Receive.............. 226
Requirements, Synchronous Transmi ssion...... 225
Timing Diagram, Synchronous Receive........... 226
Timing Diagram, Synchronous Transmission... 225
V
VREF. SEE ADC Reference Voltage
W
Wake-up Using Interrupts................................................. 186
Watchdog Timer (WDT)...................................................... 33
Clock Source.............................................................. 33
Modes......................................................................... 34
Period......................................................................... 33
Specifications ........................................................... 221
WCOL bit....... ..................... ..................... ................. 166, 178
WPUB Regist e r............... ..................... ........................... .... 58
Write Collision Detect bit (WCOL) ............................ 166, 178
WWW Address ............. .................................. .................. 287
WWW, On-Line Support..................................................... 11
PIC16(L)F707
DS41418B-page 286 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS41418B-page 287
PIC16(L)F707
THE MICROCHIP WEB SITE
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Customers should contact their distributor,
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PIC16(L)F707
DS41418B-page 288 2010-2011 Microchip Technology Inc.
READER RESP ONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
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DS41418BPIC16(L)F707
1. What are the best features of this document ?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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2010-2011 Microchip Technology Inc. DS41418B-page 289
PIC16(L)F707
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: PIC16F707, PIC16LF707, PIC16F707T, PIC16LF707T(1)
Temperature
Range: I= -40C to +85C
E= -40C to +125C
Package: MV = Micro Lead Fr ame (UQ FN)
ML = Micro Lead Frame (QFN)
P = Plastic DIP
PT = TQFP (Thin Quad Flatpack)
Pattern: 3-Digit Pattern Code for QTP (blank otherwise)
Examples:
a) PIC16F707-E/P 301 = Extend ed Temp., PDIP
package, QTP pattern #301
b) PIC16F707-I/ML = Industrial T emp., QFN pack-
age
Note 1: T = In tape and reel.
DS41418B-page 290 2010-2011 Microchip Technology Inc.
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Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-2819-3180
Fax: 86-571-2819-3189
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11 - 4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spai n - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921- 5869
Fax: 44-118-921-5820
Worldwide Sales and Service
05/02/11
