8 Megabit High Speed CMOS SRAM DPS1MX8MKN3-A DESCRIPTION: The DPS1MX8MKN3-A High Speed SRAM `'STACK'' devices are a revolutionary new memory subsystem using Dense-Pac Microsystems' ceramic Stackable Leadless Chip Carriers (SLCC) mounted on a co-fired ceramic substrate having side-brazed leads. The device packs 8-Megabits of low-power CMOS static RAM in a 600-mil-wide, 32-pin dual-in-line package. The DPS1MX8MKN3-A STACK devices contain two 512K x 8 SRAM die, each packaged in a hermetically sealed SLCC, making the devices suitable for commercial, industrial and military applications. By using SLCCs, the `'Stack'' family of devices offer a higher board density of memory than available with conventional through-hole, surface mount or hybrid techniques. FUNCTIONAL BLOCK DIAGRAM FEATURES: * Organizations Available: 1Meg x 8 * Access Times: 20*, 25, 30, 35, 45ns * Fully Static Operation - No clock or refresh required * Single +5V Power Supply, 10% Tolerance * TTL Compatible * Common Data Inputs and Outputs * Low Data Retention Voltage: 2.0V min. * Package Available: 32 Pin DIP PIN-OUT DIAGRAM * Commercial and Industrial Grade only. PIN NAMES A0 - A18 I/O0 - I/O7 CE0, CE1 WE VDD VSS 30A129-92 REV. A Address Data Input / Output Low Chip Enables Write Enable Power (+5.0V) Ground This document contains information on a product that is currently released to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change products or specifications herein without prior notice. 1 DPS1MX8MKN3-A Dense-Pac Microsystems, Inc. RECOMMENDED OPERATING RANGE 3 TRUTH TABLE Mode Not Selected Read Write H = HIGH CE WE I/O Pin H L L X H L HIGH-Z DOUT DIN L = LOW Supply Current Standby Active Active X = Don't Care ABSOLUTE MAXIMUM RATING3 Symbol TSTC TBIAS VDD VI/O Parameter Max. Unit Storage Temperature -65 to +150 C Temperature Under Bias -55 to +125 C Supply Voltage1 -0.5 to +7.0 V Input/Output Voltage1 -0.5 to VDD +0.5 V CAPACITANCE4: TA = +25C, F = 1.0MHz Symbol CADR CCE CWE CI/O Parameter Address Input Chip Enable Write Enable Data Input/Output Max. 18 12 18 22 Unit Condition pF VIN2 = 0V Symbol Characteristic VDD Supply Voltage VIH Input HIGH Voltage VIL Input LOW Voltage M/B Operating TA I Temperature C Min. 4.5 2.2 -0.52 -55 -40 -0 Typ. 5.0 Max. Unit 5.5 V VDD+0.3 V 0.8 V +25 +125 C +25 +85 +25 +70 AC TEST CONDITIONS Input Pulse Levels Input Pulse Rise and Fall Times Input and Output Timing Reference Levels 0V to 3.0V 5ns* 1.5V OUTPUT LOAD Load 1 2 CL 100pF 5pF Parametric Measured except tLZ, tHZ and tWHZ tLZ, tHZ and tWHZ +5V Figure 1. Output Load * Including Probe and Jig Capacitance. 480 DC OUTPUT CHARACTERISTICS Symbol Parameter VOH HIGH Voltage VOL LOW Voltage DOUT Conditions Min. Max. Unit IOH= -4mA 2.4 V IOL=8mA 0.4 V CL* 255 DC OPERATING CHARACTERISTICS: Symbol Characteristics IIN Input Leakage Current Output Leakage Current Operating Supply Current Full Standby Supply Current Standby Current (TTL) Data Retention Supply Current (3.0V) Data Retention Supply Current (2.0V) Output LOW Voltage Output HIGH Voltage IOUT ICC ISB1 ISB2 IDR3 IDR2 VOL VOH Test Condition Over Operating Ranges C I M/B Typ. Unit () Min. Max. Min. Max. Min. Max. VIN = 0V to VDD - -10 +10 -10 +10 -10 +10 A VI/O = 0V to VDD , CE = VIH or WE = VIL Cycle = min., Duty = 100%, IOUT = 0mA VIN VDD -0.2V or VIN VSS +0.2V CE = VIH - -20 +20 -20 +20 -20 +20 A 145 230 240 240 mA 2 20 20 30 mA 40 120 120 120 mA VDR = 3V, CE VDR -0.2V 300 1000 2000 4000 A VDR = 2V, CE VDR -0.2V 200 600 1600 360 A 0.4 V V IOL = 8.0mA IOH = -4.0mA - 0.4 2.4 0.4 2.4 2.4 Typical measurement made at +25C, Cycle = min., VDD = 5.0V. 2 30A129-92 REV. A DPS1MX8MKN3-A Dense-Pac Microsystems, Inc. Data Retention AC Characteristics 8 Symbol VDR VCDR tR Parameter VDD for Data Retention Chip Disable to Data Retention Time Operating Recovery Time Test Condition CE VDR -0.2V Min. 2.0 Typ. - Max. - Unit V See Data Retention Waveform 0 - - ns See Data Retention Waveform 5 - - ms AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: No. Symbol 1 2 3 4 5 6 tRC tAA tCO tCLZ tCHZ tOH Parameter Read Cycle Time Address Cycle Time Chip Enable Output Valid Chip Enable to Output in LOW-Z 4, 6 Chip Enable to Output in HIGH-Z 4, 5 Output Hold from Address Change 20ns* 25ns 30ns Over Operating Ranges 35ns 45ns Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 20 25 20 20 3 30 25 25 3 8 4 35 30 30 3 10 5 45 35 35 3 15 5 45 45 3 20 5 25 5 Over Operating Ranges 6, 7 30ns 35ns 45ns Unit ns ns ns ns ns ns AC OPERATING CONDITION AND CHARACTERISTIC READ CYCLE: No. Symbol 7 8 9 10 11 12 13 14 15 16 tWC tAW tCW tAS tWP tWR tWHZ tDW tDH tOW Parameter Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Setup Time ** Write Pulse Width Write Recovery Time Write Enable to Output in HIGH-Z 4, 5 Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 20ns* 25ns Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 20 13 13 0 13 0 0 9 0 3 8 25 15 15 0 15 0 0 10 0 3 10 30 20 20 0 20 0 0 12 0 3 12 35 25 25 0 25 0 0 15 0 3 15 45 35 35 0 35 0 0 20 0 3 20 Unit ns ns ns ns ns ns ns ns ns ns * Available in Commercial and Industrial Grade Only. ** Valid for both Read and Write Cycles. DATA RETENTION WAVEFORM: CE Controlled. VDD 4.5V 2.3V VDR1 CE 0V 30A129-92 REV. A 3 DPS1MX8MKN3-A Dense-Pac Microsystems, Inc. READ CYCLE ADDRESS CE DATA I/O WRITE CYCLE 1: CE Controlled. ADDRESS CE WE DATA IN DATA OUT 4 30A129-92 REV. A DPS1MX8MKN3-A Dense-Pac Microsystems, Inc. WRITE CYCLE 2: WE Controlled. 8 ADDRESS CE WE DATA IN DATA OUT NOTE: 1. 2. 3. All voltages are with respect to VSS. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at DC level). Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 4. 5. 6. 7. 8. This parameter is guaranteed and not 100% tested. Transition is measured at the point of 500mV from steady state voltage. When CE is LOW and WE is HIGH, I/O pins are in the output state, and input signals of opposite phase to the outputs must not be applied. The outputs are in a high impedance state when WE is LOW. CE and WE can initiate and terminate WRITE Cycle. WAVEFORM KEY Data Valid HIGH to LOW 30A129-92 REV. A Transition from LOW to HIGH Transition from or Don't Care Data Undefined 5 DPS1MX8MKN3-A Dense-Pac Microsystems, Inc. ORDERING INFORMATION * Customer to be notified of changes to the die. MECHANICAL DRAWING Dense-Pac Microsystems, Inc. 7321 Lincoln Way, Garden Grove, California 92841-1431 (714) 898-0007 u (800) 642-4477 u FAX: (714) 897-1772 u http://www.dense-pac.com 6 30A129-92 REV. A