74HC132; 74HCT132 Quad 2-input NAND Schmitt trigger Rev. 4 -- 1 December 2015 Product data sheet 1. General description The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals. 2. Features and benefits Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Applications Wave and pulse shapers Astable multivibrators Monostable multivibrators 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 4. Ordering information Table 1. Ordering information Type number 74HC132D Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HCT132D 74HC132DB 74HCT132DB 74HC132PW 74HCT132PW 5. Functional diagram $ < $ < % % $ < % $ < Logic symbol 74HC_HCT132 Product data sheet < % % PQD Fig 1. $ PQD Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 PQD Fig 3. Logic diagram (one Schmitt trigger) (c) NXP Semiconductors N.V. 2015. All rights reserved. 2 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 6. Pinning information 6.1 Pinning $ % 9&& % < $ % % < $ *1' < $ < PQD Fig 4. Pin configuration SO14 and (T)SSOP14 6.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 7. Functional description Table 3. Function table[1] Input Output nA nB L L H L H H H L H H H L [1] nY H = HIGH voltage level; L = LOW voltage level; X = don't care. 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 3 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA 50 mA IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC supply current - IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot [2] SO14, and (T)SSOP14 packages [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage Conditions 74HC132 74HCT132 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 4 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V 74HC132 VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V VI = VT+ or VT - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2.0 - 20 - 40 A CI input capacitance - 3.5 - - - - - pF IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V 74HCT132 VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT; VCC = 4.5 V VI = VT+ or VT; VCC = 4.5 V IO = 20 A; - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 A ICC additional supply current per input pin; VI = VCC 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 30 108 - 135 - 147 A CI input capacitance - 3.5 - - - - - pF 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 5 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 11. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 6. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 36 125 155 190 VCC = 4.5 V - 13 25 31 38 ns VCC = 5.0 V; CL = 15 pF - 11 - - - ns - 10 21 26 32 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns - 6 13 16 19 ns - 24 - - - pF - 20 33 41 50 ns 74HC132 propagation delay nA, nB to nY; see Figure 5 tpd [1] VCC = 2.0 V VCC = 6.0 V transition time tt [2] see Figure 5 VCC = 6.0 V power dissipation capacitance CPD ns per package; VI = GND to VCC [3] 74HCT132 propagation delay nA, nB to nY; see Figure 5 tpd [1] VCC = 4.5 V VCC = 5.0 V; CL = 15 pF transition time tt power dissipation capacitance CPD - 17 - - - ns VCC = 4.5 V; see Figure 5 [2] - 7 15 19 22 ns per package; VI = GND to VCC 1.5 V [3] - 20 - - - pF [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 6 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 12. Waveforms 9, Q$Q%LQSXW 90 *1' W3+/ 92+ W3/+ 9< 90 9; Q<RXWSXW 92/ W7+/ W7/+ DDL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Input to output propagation delays Table 8. Measurement points Type Input Output VM VM VX VY 74HC132 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT132 1.3 V 1.3 V 0.1VCC 0.9VCC 9, QHJDWLYH SXOVH W: 90 *1' 9, WI WU WU WI SRVLWLYH SXOVH *1' 90 90 90 W: 9&& * 9, 92 '87 57 &/ DDK Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 6. Test circuit for measuring switching times 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 7 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger Table 9. Test data Type Input Load Test VI tr, tf CL 74HC132 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HCT132 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL 13. Transfer characteristics Table 10. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 7 and Figure 8. Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 0.7 1.18 1.5 0.7 1.5 0.7 1.5 V VCC = 4.5 V 1.7 2.38 3.15 1.7 3.15 1.7 3.15 V 74HC132 VT+ VT VH positive-going threshold voltage VCC = 6.0 V 2.1 3.14 4.2 2.1 4.2 2.1 4.2 V negative-going VCC = 2.0 V threshold VCC = 4.5 V voltage VCC = 6.0 V 0.3 0.63 1.0 0.3 1.0 0.3 1.0 V 0.9 1.67 2.2 0.9 2.2 0.9 2.2 V 1.2 2.26 3.0 1.2 3.0 1.2 3.0 V hysteresis voltage VCC = 2.0 V 0.2 0.55 1.0 0.2 1.0 0.2 1.0 V VCC = 4.5 V 0.4 0.71 1.4 0.4 1.4 0.4 1.4 V VCC = 6.0 V 0.6 0.88 1.6 0.6 1.6 0.6 1.6 V VCC = 4.5 V 1.2 1.41 1.9 1.2 1.9 1.2 1.9 V VCC = 5.5 V 1.4 1.59 2.1 1.4 2.1 1.4 2.1 V negative-going VCC = 4.5 V threshold VCC = 5.5 V voltage 0.5 0.85 1.2 0.5 1.2 0.5 1.2 V 0.6 0.99 1.4 0.6 1.4 0.6 1.4 V hysteresis voltage VCC = 4.5 V 0.4 0.56 - 0.4 - 0.4 - V VCC = 5.5 V 0.4 0.60 - 0.4 - 0.4 - V 74HCT132 VT+ VT VH positive-going threshold voltage 14. Transfer characteristics waveforms 92 9, 97 9+ 97 9, 9+ 97 Fig 7. 97 Transfer characteristics 74HC_HCT132 Product data sheet 92 PQD PQD Fig 8. Transfer characteristics definitions All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 8 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger DDD DDD ,&& $ ,&& $ 9,1 9 9,1 9 a. VCC = 2.0 V b. VCC = 4.5 V DDD ,&& P$ 9,1 9 c. VCC = 6.0 V Fig 9. Typical 74HC132 transfer characteristics 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 9 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger DDD DDD ,&& P$ ,&& P$ 9,1 9 9,1 9 a. VCC = 4.5 V b. VCC = 5.5 V Fig 10. Typical 74HCT132 transfer characteristics 15. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula: Padd = fi (tr ICC(AV) + tf ICC(AV)) VCC where: Padd = additional power dissipation (W); fi = input frequency (MHz); tr = rise time (ns); 10 % to 90 %; tf = fall time (ns); 90 % to 10 %; ICC(AV) = average additional supply current (A). Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 11 and Figure 12. An example of a relaxation circuit using the 74HC132; 74HCT132 is shown in Figure 13. 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 10 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger DDD DYHUDJH ,&& $ SRVLWLYHJRLQJ HGJH QHJDWLYHJRLQJ HGJH 9&& 9 (1) Positive-going edge. (2) Negative-going edge. Fig 11. Average additional supply current as a function of VCC for 74HC132; linear change of VI between 0.1VCC to 0.9VCC. DDD DYHUDJH ,&& $ SRVLWLYHJRLQJ HGJH QHJDWLYHJRLQJ HGJH 9&& 9 (1) Positive-going edge. (2) Negative-going edge. Fig 12. Average additional supply current as a function of VCC for 74HCT132; linear change of VI between 0.1VCC to 0.9VCC. 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 11 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 9&& 5 9&& $ < % & DDF For 74HC132 and 74HCT132: 1 1 f = --- -----------------T K RC For K-factor, see Figure 14 Fig 13. Relaxation oscillator DDD . DDD . 9&& 9 9&& 9 K-factor for 74HC132 K-factor for 74HCT132 Fig 14. Typical K-factor for relaxation oscillator 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 12 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 16. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ = 4 $ $ $ $ SLQLQGH[ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP LQFKHV R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7( Fig 15. Package outline SOT108-1 (SO14) 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 13 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ = 4 $ $ $ $ SLQLQGH[ /S / GHWDLO; Z 0 ES H PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7( 02 Fig 16. Package outline SOT337-1 (SSOP14) 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 14 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ = 4 $ SLQLQGH[ $ $ $ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7( 02 Fig 17. Package outline SOT402-1 (TSSOP14) 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 15 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 17. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 18. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT132 v.4 20151201 Product data sheet - 74HC_HCT132 v.3 Modifications: 74HC_HCT132 v.3 Modifications: * Type numbers 74HC132N and 74HCT132N (SOT27-1) removed. 20120830 Product data sheet - 74HC_HCT132_CNV v.2 * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. * * Legal texts have been adapted to the new company name where appropriate. Figure 14 added (typical K-factor for relaxation oscillator). 74HC_HCT132_CNV v.2 19970826 74HC_HCT132 Product data sheet Product specification - All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 - (c) NXP Semiconductors N.V. 2015. All rights reserved. 16 of 19 74HC132; 74HCT132 NXP Semiconductors Quad 2-input NAND Schmitt trigger 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT132 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 1 December 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 18 of 19 NXP Semiconductors 74HC132; 74HCT132 Quad 2-input NAND Schmitt trigger 21. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Transfer characteristics . . . . . . . . . . . . . . . . . . 8 Transfer characteristics waveforms. . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 December 2015 Document identifier: 74HC_HCT132