Product Folder Order Now Support & Community Tools & Software Technical Documents LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 LMV84x CMOS Input, RRIO, Low Power, Wide Supply Range, 4.5-MHz Operational Amplifiers 1 Features 3 Description * The LMV84x devices are low-voltage and low-power operational amplifiers that operate with supply voltages ranging from 2.7 V to 12 V and have rail-torail input and output capability. Their low offset voltage, low supply current, and CMOS inputs make them ideal for high impedance sensor interface and battery-powered applications. 1 * * * * * * * * * * * * Unless Otherwise Noted, Typical Values at TA = 25 C, V+ = 5 V. Small 5-Pin SC70 Package (2.00 mm x 1.25 mm x 0.95 mm) Wide Supply Voltage Range: 2.7 V to 12 V Specified Performance at 3.3 V, 5 V and 5 V Low Supply Current: 1 mA Per Channel Unity Gain Bandwidth: 4.5 MHz Open-Loop Gain: 133 dB Input Offset Voltage: 500 V Maximum Input Bias Current: 0.3 pA CMRR at 112 dB and PSSR at 108 dB Input Voltage Noise: 20 nV/Hz Temperature Range: -40C to 125C Rail-to-Rail Input and Output (RRIO) The single LMV841 is offered in the space-saving 5pin SC70 package, the dual LMV842 in the 8-pin VSSOP and 8-pin SOIC packages, and the quad LMV844 in the 14-pin TSSOP and 14-pin SOIC packages. These small packages are ideal solutions for area-constrained PCBs and portable electronics. Device Information(1) PART NUMBER LMV841 LMV842 2 Applications * * * * LMV844 High Impedance Sensor Interface Battery-Powered Instrumentation High Gain and Instrumentation Amplifiers DAC Buffers and Active Filters PACKAGE BODY SIZE (NOM) SC70 (5) 2.00 mm x 1.25 mm VSSOP (8) 3.00 mm x 3.00 mm SOIC (8) 4.90 mm x 3.91 mm SOIC (14) 8.65 mm x 3.91 mm TSSOP (14) 5.00 mm x 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Applications - VIN + + Active Band-Pass Filter SENSOR RS + VS + - RS - + LOAD High Impedance Sensor Interface CMOS Input Feature High-Side, Current-Sensing Rail-to-Rail Input and Output Feature Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics - 3.3 V ............................. 5 Electrical Characteristics - 5 V ................................ 6 Electrical Characteristics - 5-V .............................. 7 Typical Characteristics ............................................ 10 Detailed Description ............................................ 16 7.1 Overview ................................................................. 16 7.2 Functional Block Diagram ....................................... 16 7.3 Feature Description................................................. 16 7.4 Device Functional Modes........................................ 17 7.5 Interfacing to High Impedance Sensor .................. 20 8 Application and Implementation ........................ 21 8.1 Application Information............................................ 21 8.2 Typical Applications ................................................ 21 9 Power Supply Recommendations...................... 25 10 Layout................................................................... 25 10.1 Layout Guidelines ................................................. 25 10.2 Layout Example .................................................... 25 11 Device and Documentation Support ................. 26 11.1 11.2 11.3 11.4 11.5 11.6 Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 26 26 12 Mechanical, Packaging, and Orderable Information ........................................................... 26 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (July 2016) to Revision I Page * Changed ESD Ratings table footnotes to TI standard .......................................................................................................... 4 * Changed Thermal Information table ....................................................................................................................................... 4 * Changed Phase Margin vs CL graphic ................................................................................................................................ 13 * Changed Overshoot vs CL graphic ....................................................................................................................................... 14 Changes from Revision G (February 2013) to Revision H * Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 Changes from Revision F (February 2013) to Revision G * 2 Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 23 Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 5 Pin Configuration and Functions DCK Package 5-Pin SC70 Top View D or DGK Package 8-Pin SOIC and VSSOP Top View D or PW Package 14-Pin SOIC and TSSOP Top View Pin Functions PIN NAME DESCRIPTION I/O. +IN I Noninverting Input -IN I Inverting Input OUT O Output V+ P Positive Supply V- P Negative Supply Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 3 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) See MIN MAX UNIT -300 300 mV 13.2 V V+ + 0.3 V- - 0.3 V 10 mA VIN differential + - Supply voltage (V - V ) Voltage at input and output pins Input current Junction temperature Soldering information (3) 150 C Infrared or convection (20 s) 235 C Wave soldering lead temperature (10 s) 260 C 150 C -65 Storage temperature, Tstg (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office / Distributors for availability and specifications. The maximum power dissipation is a function of TJ(MAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RJA. All numbers apply for packages soldered directly onto a PCB. 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human-body model (HBM) (1) UNIT 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V 250 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Temperature (1) Supply voltage (V+ - V-) (1) MIN MAX UNIT -40 125 C 2.7 12 V The maximum power dissipation is a function of TJ(MAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RJA. All numbers apply for packages soldered directly onto a PCB. 6.4 Thermal Information LMV84x THERMAL METRIC (1) DCK (SC70) DGK (VSSOP) D (SOIC) PW (TSSOP) UNIT 5 PINS 8 PINS 8 PINS 14 PIN 14 PINS RJA Junction-to-ambient thermal resistance (2) 269.9 179.2 121.4 85.4 113.3 C/W RJC(top) Junction-to-case (top) thermal resistance 93.8 69.2 65.7 43.5 38.9 C/W RJB Junction-to-board thermal resistance 48.8 99.7 62.0 39.8 56.3 C/W JT Junction-to-top characterization parameter 2.0 10.0 16.5 9.2 3.1 C/W JB Junction-to-board characterization parameter 47.9 98.3 61.4 39.6 55.6 C/W RJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A C/W (1) (2) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. The maximum power dissipation is a function of TJ(MAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RJA. All numbers apply for packages soldered directly onto a PCB. Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 6.5 Electrical Characteristics - 3.3 V Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 3.3 V, V- = 0 V, VCM = V+ / 2, and RL > 10 M to V+ / 2. (1) PARAMETER VOS TEST CONDITIONS Input offset voltage TCVOS Input offset voltage drift Input bias current IB MIN (2) TYP (3) MAX (2) -500 50 500 at the temperature extremes -800 at the temperature extremes -5 (4) 800 0.5 (4) (5) 5 0.3 at the temperature extremes IOS 300 Input offset current Common-mode rejection ratio LMV841 CMRR Common-mode rejection ratio LMV842 and LMV844 PSRR Power supply rejection ratio CMVR Input common-mode voltage range 40 84 0 V VCM 3.3 V at the temperature extremes 2.7 V V+ 12 V, VO = V+ /2 at the temperature extremes CMRR 50 dB, at the temperature extremes Large signal voltage gain RL = 10 k VO = 0.2 V to 3.1 V at the temperature extremes at the temperature extremes 106 dB 108 dB -0.1 3.4 dB 131 dB 96 52 RL = 2 k to V+/2 at the temperature extremes RL = 10 k to V+/2 at the temperature extremes RL = 2 k to V+/2 at the temperature extremes RL = 10 k to V+/2 at the temperature extremes Output swing high, (measured from V+) (1) (2) (3) (4) (5) mV 100 120 33 mV 50 70 65 Output swing low, (measured from V-) 80 120 28 VO V 123 96 100 pA dB 82 100 V/C fA 75 86 at the temperature extremes V 112 80 77 0 V VCM 3.3 V RL = 2 k VO = 0.3 V to 3 V AVOL 10 UNIT mV 65 75 mV Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. This parameter is ensured by design and/or characterization and is not tested in production. Positive current corresponds to current flowing into the device. Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 5 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com Electrical Characteristics - 3.3 V (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 3.3 V, V- = 0 V, VCM = V+ / 2, and RL > 10 M to V+ / 2.(1) PARAMETER TEST CONDITIONS Sourcing VO = V+/2 VIN = 100 mV at the temperature extremes Output short-circuit current (6) (7) IO MIN (2) TYP (3) 20 32 at the temperature extremes mA 27 mA 15 0.93 IS Supply current SR Slew rate GBW Gain bandwidth product m Phase margin en Input-referred voltage noise f = 1 kHz 20 ROUT Open-loop output impedance f = 3 MHz 70 (8) THD+N Total harmonic distortion + noise CIN (6) (7) (8) Per channel UNIT 15 20 Sinking VO = V+/2 VIN = -100 mV MAX (2) 1.5 at the temperature extremes mA 2 AV = 1, VO = 2.3 VPP 10% to 90% 2.5 V/s 4.5 MHz 67 f = 1 kHz , AV = 1 RL = 10 k Deg nV/ 0.005% Input capacitance 7 pF The maximum power dissipation is a function of TJ(MAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RJA. All numbers apply for packages soldered directly onto a PCB. Short circuit test is a momentary test. Number specified is the slower of positive and negative slew rates. 6.6 Electrical Characteristics - 5 V Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5 V, V- = 0 V, VCM = V+ / 2, and RL > 10 M to V+ / 2. (1) PARAMETER VOS Input offset voltage TCVOS Input offset voltage drift (4) IB Input bias current (4) (5) IOS Input offset current TEST CONDITIONS (1) (2) (3) (4) (5) 6 TYP (3) MAX (2) -500 50 500 at the temperature extremes -800 at the temperature extremes -5 800 0.35 5 0.3 at the temperature extremes 40 Common-mode rejection ratio LMV841 0 V VCM 5 V at the temperature extremes Common-mode rejection ratio LMV842 and LMV844 0 V VCM 5 V at the temperature extremes Power supply rejection ratio 2.7 V V+ 12 V, VO = at the temperature V+/2 extremes 10 300 86 CMRR PSRR MIN (2) 82 V/C pA fA dB 106 dB 79 86 V 112 80 81 UNIT 108 dB Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. This parameter is ensured by design and/or characterization and is not tested in production. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 Electrical Characteristics - 5 V (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5 V, V- = 0 V, VCM = V+ / 2, and RL > 10 M to V+ / 2.(1) PARAMETER CMVR TEST CONDITIONS CMRR 50 dB, at the temperature extremes Input common-mode voltage range RL = 2 k VO = 0.3V to 4.7 V AVOL Large signal voltage gain RL = 10 k VO = 0.2V to 4.8V MIN (2) -0.2 100 at the temperature extremes at the temperature extremes RL = 10 k to V+/2 at the temperature extremes RL = 2 k to V+/2 at the temperature extremes Output swing high, (measured from V+) dB 133 dB 96 Sourcing VO = V+/2 VIN = 100 mV Output short-circuit current (6) IO (7) Sinking VO = V+/2 VIN = -100 mV 20 mA 15 Slew rate GBW Gain bandwidth product m Phase margin en Input-referred voltage noise f = 1 kHz 20 ROUT Open-loop output impedance f = 3 MHz 70 THD+N Total harmonic distortion + noise f = 1 kHz , AV = 1 RL = 10 k CIN Input capacitance (7) (8) mV 28 SR (6) 70 mA Supply current at the temperature extremes AV = 1, VO = 4 VPP 10% to 90% mV 15 IS (8) 120 33 0.96 Per channel mV 80 20 at the temperature extremes 50 140 at the temperature extremes at the temperature extremes mV 70 38 RL = 10 k to V+/2 100 120 78 Output swing low, (measured from V-) V 125 32 VO UNIT 5.2 68 RL = 2 k to V+/2 MAX (2) 96 100 at the temperature extremes TYP (3) 1.5 mA 2 2.5 V/s 4.5 MHz 67 Deg nV/ 0.003% 6 pF The maximum power dissipation is a function of TJ(MAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RJA. All numbers apply for packages soldered directly onto a PCB. Short circuit test is a momentary test. Number specified is the slower of positive and negative slew rates. 6.7 Electrical Characteristics - 5-V Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5 V, V- = -5 V, VCM = 0 V, and RL > 10 M to VCM. (1) (1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device. Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 7 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com Electrical Characteristics - 5-V (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5 V, V- = -5 V, VCM = 0 V, and RL > 10 M to VCM.(1) PARAMETER VOS Input offset voltage TCVOS Input offset voltage drift TEST CONDITIONS at the temperature extremes Input bias current TYP (3) MAX (2) -500 50 500 -800 (4) 800 0.25 at the temperature extremes IB MIN (2) -5 (4) (5) 5 0.3 at the temperature extremes IOS Input offset current 40 86 Common-mode rejection ratio LMV841 -5 V VCM 5 V at the temperature extremes Common-mode rejection ratio LMV842 and LMV844 -5 V VCM 5 V at the temperature extremes PSRR Power supply rejection ratio 2.7 V V+ 12 V, VO = at the temperature 0V extremes CMVR Input common-mode voltage range CMRR 50 dB CMRR Large signal voltage gain RL = 10 k VO = -4.8 V to 4.8 V 106 dB 108 dB -5.2 100 5.2 100 dB 136 dB 96 95 RL = 2 k to 0 V Output swing high, (measured from V+) VO RL = 10 k to 0 V at the temperature extremes Sourcing VO = 0 V VIN = 100 mV Output short-circuit current (6) (7) Sinking VO = 0 V VIN = -100 mV (2) (3) (4) (5) (6) (7) 8 20 20 15 mV 37 mA 15 at the temperature extremes mV 80 100 at the temperature extremes mV 160 200 52 mV 75 95 105 at the temperature extremes 130 155 at the temperature extremes RL = 2 k to 0 V Output swing low, (measured from V-) IO at the temperature extremes 44 RL = 10 k to 0 V V 126 96 at the temperature extremes pA dB 82 at the temperature extremes V/C 112 80 86 V fA 80 86 RL = 2 k VO = -4.7 V to 4.7 V AVOL 10 300 UNIT 29 mA Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. This parameter is ensured by design and/or characterization and is not tested in production. Positive current corresponds to current flowing into the device. The maximum power dissipation is a function of TJ(MAX), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA) / RJA. All numbers apply for packages soldered directly onto a PCB. Short circuit test is a momentary test. Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 Electrical Characteristics - 5-V (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = 5 V, V- = -5 V, VCM = 0 V, and RL > 10 M to VCM.(1) PARAMETER TEST CONDITIONS TYP (3) MAX (2) 1.03 1.7 IS Supply current SR Slew rate GBW m en Input-referred voltage noise f = 1 kHz 20 ROUT Open-loop output impedance f = 3 MHz 70 THD+N Total harmonic distortion + noise f = 1 kHz , AV = 1 RL = 10k CIN Input capacitance (8) (8) Per channel MIN (2) at the temperature extremes AV = 1, VO = 9 VPP 10% to 90% 2 UNIT mA 2.5 V/s Gain bandwidth product 4.5 MHz Phase margin 67 Deg nV/ 0.006% 3 pF Number specified is the slower of positive and negative slew rates. Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 9 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com 6.8 Typical Characteristics At TA = 25C, RL = 10 k, VS = 5 V. Unless otherwise specified. 200 200 VS = 3.3V 150 125C 100 85C 50 VOS (PV) VOS (PV) 100 VS = 5.0V 150 0 -50 -100 50 125C 0 85C -50 25C -100 25C -150 -150 -40C -200 -1 0 1 2 3 -200 -1 4 -40C 0 1 2 VCM (V) 3 4 5 6 VCM (V) Figure 1. VOS vs VCM Over Temperature at 3.3 V Figure 2. VOS vs VCM Over Temperature at 5 V 200 200 VS = 5V 150 150 125C 100 0 VOS (PV) 85C 50 VOS (PV) 100 25C 125C 50 0 85C -50 -50 25C -100 -40C -100 -150 -150 -200 -6 -200 2 -40C -4 -2 0 2 4 6 4 6 8 10 12 14 VCM (V) VSUPPLY (V) Figure 3. VOS vs VCM Over Temperature at 5 V Figure 4. VOS vs Supply Voltage 140 200 RL = 10 k: OPEN LOOP GAIN (dB) 150 VOS (PV) 100 50 0 3.3V -50 5V -100 5V 130 RL = 2 k: 120 110 RL = 600O 100 -150 -200 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) Figure 5. VOS vs Temperature 10 Submit Documentation Feedback 90 0 100 200 300 400 500 OUTPUT SWING FROM RAIL (mV) Figure 6. DC Gain vs VOUT Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 Typical Characteristics (continued) At TA = 25C, RL = 10 k, VS = 5 V. Unless otherwise specified. 20 TA = 25C 0.15 15 0.10 10 0.05 5 IBIAS (pA) IBIAS (pA) 0.20 0 -0.05 TA = 85C 0 5.0V -5 5V -0.10 -10 5V -0.15 -0.20 -5 -4 -3 -2 -1 0 1 5V -15 3.3V 2 3 4 -20 -5 5 3.3V -4 -3 -2 -1 VCM (V) 1 2 3 4 5 VCM (V) Figure 7. Input Bias Current vs VCM Figure 8. Input Bias Current vs VCM 200 1.4 TA = 125C 125C 150 SUPPLY CURRENT (mA) 1.3 100 IBIAS (pA) 0 50 0 5.0V -50 -100 5V 85C 1.1 25C 1.0 0.9 3.3V -150 1.2 -40C -200 -5 -4 -3 -2 -1 0 1 2 3 4 0.8 2 5 4 6 VCM (V) 8 10 12 14 SUPPLY VOLTAGE (V) Figure 9. Input Bias Current vs VCM Figure 10. Supply Current Per Channel vs Supply Voltage 40 45 125C 85C -40C 40 25C ISOURCE (mA) ISINK (mA) 35 30 25 20 2 4 6 85C 125C 8 10 35 25C -40C 30 12 25 2 4 SUPPLY VOLTAGE (V) Figure 11. Sinking Current vs Supply Voltage 6 8 10 12 SUPPLY VOLTAGE (V) Figure 12. Sourcing Current vs Supply Voltage Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 11 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com Typical Characteristics (continued) At TA = 25C, RL = 10 k, VS = 5 V. Unless otherwise specified. 135 65 RL = 2 k: 60 125C VOUT FROM RAIL HIGH (mV) 115 85C 105 95 85 75 25C 65 55 -40C RL = 10 k: 55 125C 50 85C 45 40 35 25C 30 -40C 25 20 45 35 2 4 6 8 10 12 15 2 14 4 Figure 13. Output Swing High vs Supply Voltage RL = 2 k VOUT FROM RAIL LOW (mV) VOUT FROM RAIL LOW (mV) 70 125C 130 85C 120 110 100 90 25C 80 70 -40C 60 4 6 RL = 10 k: 125C 65 60 85C 55 50 45 25C 40 -40C 35 8 10 12 25 2 14 4 SINK 125C 0.4 6 8 10 12 14 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 16. Output Swing Low vs Supply Voltage RL = 10 k 60 85C 130 GAIN PHASE -40C 0.3 0.2 90 40 -40C 25C 0.1 VS = 3.3V, 5.0V, +/-5V 0 -0.1 25C GAIN (dB) VOUT FROM RAIL (V) 14 30 Figure 15. Output Swing Low vs Supply Voltage RL = 2 k 125C -40C 20 10 0 125C 85C -0.4 125C CL = 20 pF -20 10k 100k SOURCE -0.5 0 5 10 15 20 ILOAD (mA) 25 30 Figure 17. Output Voltage Swing vs Load Current Submit Documentation Feedback 50 -40C -0.2 -0.3 12 12 75 140 0.5 10 Figure 14. Output Swing High vs Supply Voltage RL = 10 k RL = 2 k: 50 2 8 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 150 6 PHASE () VOUT FROM RAIL HIGH (mV) 125 1M -30 10M FREQUENCY (Hz) Figure 18. Open-Loop Frequency Response Over Temperature Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 Typical Characteristics (continued) At TA = 25C, RL = 10 k, VS = 5 V. Unless otherwise specified. 60 130 GAIN 80 PHASE VS=10V CL=20 pF 90 20 50 PHASE (q) VS = 3.3V CL = 100 pF 60 PHASE () 40 GAIN (dB) Vs = 3.3 V Vs = 5 V Vs = 10 V 70 50 40 30 20 0 10 10 VS = 3.3V, 5.0V, 10V 0 CL = 20 pF, 50 pF, 100 pF -20 10k 100k 1M -30 10M 1 2 3 4 5 67 10 20 30 50 70100 CLOAD 200 500 1000 D001 Figure 20. Phase Margin vs CL FREQUENCY (Hz) Figure 19. Open-Loop Frequency Response Over Load Conditions 120 3.3V 110 5.0V 100 3.3V 5V PSRR (dB) +PSRR 3.3V 5.0V 5V 60 40 20 3.3V: VCM = 1V CMRR (dB) 5.0V 80 90 5V 70 50 5.0V: VCM = 2.5V -PSRR 5V : VCM = 0V 5V: VCM = 0V 0 100 3.3V : VCM = 1V 5.0V : VCM = 2.5V 30 1k 10k 100k 1M 100 1k FREQUENCY (Hz) 10k 100k 1M FREQUENCY (Hz) Figure 21. PSRR vs Frequency Figure 22. CMRR vs Frequency 160 140 500 mV/DIV CHANNEL SEPARATION (dB) 180 120 100 f = 250 kHz AV = +1 VIN = 2 VPP CL = 20 pF 80 VS = 3.3V, 5.0V, 5V 60 100 1k 10k 100k 400 ns/DIV 1M FREQUENCY (Hz) Figure 23. Channel Separation vs Frequency Figure 24. Large Signal Step Response With Gain = 1 Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 13 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com Typical Characteristics (continued) 50 mV/DIV 200 mV/DIV At TA = 25C, RL = 10 k, VS = 5 V. Unless otherwise specified. f = 250 kHz AV = +1 f = 250 kHz AV = +10 VIN = 100 mVPP CL = 20 pF VIN = 200 mVPP CL = 20 pF 400 ns/DIV 400 ns/DIV Figure 25. Large Signal Step Response With Gain = 10 Figure 26. Small Signal Step Response With Gain = 1 20 mV/DIV SLEW RATE (V/s) 3.0 f = 250 kHz AV = +10 VIN = 10 mVPP CL = 20 pF FALLING EDGE 2.5 2.0 RISING EDGE AV = +1 1.5 VIN = 2 VPP RL = 10 k CL = 20 pF 1.0 400 ns/DIV 2 4 6 8 10 SUPPLY VOLTAGE (V) 12 Figure 28. Slew Rate vs Supply Voltage Figure 27. Small Signal Step Response With Gain = 10 35 100 25 50 NOISE (nV/Hz) OVERSHOOT (%) 30 20 15 10 5.0V 20 V(s) = 3.3 V V(s) = 5 V V(s) = 5 V 5 0 10 3.3V 20 30 40 50 70 100 200 300 CLOAD (pF) 500 700 1000 D002 5V 10 10 100 1k 10k 100k FREQUENCY (Hz) Figure 29. Overshoot vs CL Figure 30. Input Voltage Noise vs Frequency 14 Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 Typical Characteristics (continued) At TA = 25C, RL = 10 k, VS = 5 V. Unless otherwise specified. 1 10 VS = 5V RL = 10 k AV = +10 0.1 1 VOUT = 4.5 VPP AV = +10 THD + N (%) THD + N (%) CL = 50 pF 0.01 0.1 0.01 AV = +1 VS = 5V RL = 10 k CL = 20 pF f = 1 kHz AV = +1 0.001 10 100 1k 10k 0.001 0.001 100k 0.01 FREQUENCY (Hz) 0.1 1 10 VOUT (V) Figure 31. THD+N vs Frequency Figure 32. THD+N vs VOUT 100 10 ROUT (:) 100x 1 10x 0.1 1x 0.01 0.001 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 33. Closed-Loop Output Impedance vs Frequency Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 15 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com 7 Detailed Description 7.1 Overview The LMV84x devices are operational amplifiers with near-precision specifications: low noise, low temperature drift, low offset, and rail-to-rail input and output. Possible application areas include instrumentation, medical, test equipment, audio, and automotive applications. Its low supply current of 1 mA per amplifier, temperature range of -40C to +125C, 12-V supply with CMOS input, and the small SC70 package for the LMV841 make the LMV84x a unique op amp family and a perfect choice for portable electronics. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Protection The LMV84x devices have a set of anti-parallel diodes D1 and D2 between the input pins, as shown in Figure 34. These diodes are present to protect the input stage of the amplifier. At the same time, they limit the amount of differential input voltage that is allowed on the input pins. A differential signal larger than one diode voltage drop can damage the diodes. The differential signal between the inputs needs to be limited to 300 mV or the input current needs to be limited to 10 mA. NOTE When the op amp is slewing, a differential input voltage exists that forward-biases the protection diodes. This may result in current being drawn from the signal source. While this current is already limited by the internal resistors R1 and R2 (both 130 ), a resistor of 1 k can be placed in the feedback path, or a 500- resistor can be placed in series with the input signal for further limitation. 16 Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 Feature Description (continued) V + + V ESD IN IN ESD V + R1 D1 D2 + V ESD + - VOUT R2 ESD - V - V Figure 34. Protection Diodes Between the Input Pins 7.3.2 Input Stage The input stage of this amplifier consists of both a PMOS and an NMOS input pair to achieve a rail-to-rail input range. For input voltages close to the negative rail, only the PMOS pair is active. Close to the positive rail, only the NMOS pair is active. In a transition region that extends from approximately 2 V below V+ to 1 V below V+, both pairs are active, and one pair gradually takes over from the other. In this transition region, the input-referred offset voltage changes from the offset voltage associated with the PMOS pair to that of the NMOS pair. The input pairs are trimmed independently to ensure an input offset voltage of less then 0.5 mV at room temperature over the complete rail-to-rail input range. This also significantly improves the CMRR of the amplifier in the transition region. NOTE The CMRR and PSRR limits in the tables are large-signal numbers that express the maximum variation of the input offset of the amplifier over the full common-mode voltage and supply voltage range, respectively. When the common-mode input voltage of the amplifier is within the transition region, the small signal CMRR and PSRR may be slightly lower than the large signal limits. 7.4 Device Functional Modes 7.4.1 Driving Capacitive Load The LMV84x can be connected as noninverting unity gain amplifiers. This configuration is the most sensitive to capacitive loading. The combination of a capacitive load placed on the output of an amplifier along with the output impedance of the amplifier creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response is under-damped, which causes peaking in the transfer. When there is too much peaking, the op amp might start oscillating. The LMV84x can directly drive capacitive loads up to 100 pF without any stability issues. To drive heavier capacitive loads, an isolation resistor (RISO) must be used, as shown in Figure 35. By using this isolation resistor, the capacitive load is isolated from the output of the amplifier, and hence, the pole caused by CL is no longer in the feedback loop. The larger the value of RISO, the more stable the output voltage is. If values of RISO are sufficiently large, the feedback loop is stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive. Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 17 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com Device Functional Modes (continued) RISO - V OUT V IN + CL Figure 35. Isolating Capacitive Load 7.4.2 Noise Performance The LMV84x devices have good noise specifications and are frequently used in low-noise applications. Therefore it is important to determine the noise of the total circuit. Besides the input-referred noise of the op amp, the feedback resistors may have an important contribution to the total noise. For applications with a voltage input configuration, in general it is beneficial general, beneficial to keep the resistor values low. In these configurations high resistor values mean high noise levels. However, using low resistor values will increase the power consumption of the application. This is not always acceptable for portable applications, so there is a trade-off between noise level and power consumption. Besides the noise contribution of the signal source, three types of noise need to be taken into account for calculating the noise performance of an op amp circuit: * Input-referred voltage noise of the op amp * Input-referred current noise of the op amp * Noise sources of the resistors in the feedback network, configuring the op amp To calculate the noise voltage at the output of the op amp, the first step is to determine a total equivalent noise source. This requires the transformation of all noise sources to the same reference node. A convenient choice for this node is the input of the op amp circuit. The next step is to add all the noise sources. The final step is to multiply the total equivalent input voltage noise with the gain of the op amp configuration. If the input-referred voltage noise of the op amp is already placed at the input, the user can use the inputreferred voltage noise without further transferring. The input-referred current noise needs to be converted to an input-referred voltage noise. The current noise is negligibly small, as long as the equivalent resistance is not unrealistically large, so the user can leave the current noise out for these examples. That leaves the user with the noise sources of the resistors, being the thermal noise voltage. The influence of the resistors on the total noise can be seen in the following examples, one with high resistor values and one with low resistor values. Both examples describe an op amp configuration with a gain of 101 which gives the circuit a bandwidth of 44.5 kHz. The op amp noise is the same for both cases, that is, an input-referred noise voltage of 20 nV/ and a negligibly small input-referred noise current. + en in RF RG Figure 36. Noise Circuit 18 Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 Device Functional Modes (continued) To calculate the noise of the resistors in the feedback network, the equivalent input-referred noise resistance is needed. For the example in Figure 36, this equivalent resistance Req can be calculated using Equation 1: R RG Req = F RF + RG (1) The voltage noise of the equivalent resistance can be calculated using Equation 2: enr = 4kTReq where * * * * * enr = thermal noise voltage of the equivalent resistor Req (V/ ) k = Boltzmann constant (1.38 x 10-23 J/K) T = absolute temperature (K) Req = resistance () (2) The total equivalent input voltage noise is given by Equation 3: en in = env 2 + enr 2 where * * en in = total input equivalent voltage noise of the circuit env = input voltage noise of the op amp (3) The final step is multiplying the total input voltage noise by the noise gain using Equation 4, which is in this case the gain of the op amp configuration: en out = en in Anoise (4) The equivalent resistance for the first example with a resistor RF of 10 M and a resistor RG of 100 k at 25C (298 K) equals Equation 5: R RG 10 M W 100 k W Req = F = = 99 k W RF + RG 10 M W + 100 k W (5) Now the noise of the resistors can be calculated using Equation 6, yielding: enr = 4kTReq = 4 1.38 10-23 J/K 298K 99 k W = 40 nV/ Hz (6) The total noise at the input of the op amp is calculated in Equation 7: en in = env 2 + enr 2 = (20 nV/ Hz )2 + (40 nV/ Hz )2 = 45 nV/ Hz (7) For the first example, this input noise, multiplied with the noise gain, in Equation 8 gives a total output noise of: en out = en in Anoise = 45 nV/ Hz 101 = 4.5 mV/ Hz (8) In the second example, with a resistor RF of 10 k and a resistor RG of 100 at 25C (298 K), the equivalent resistance equals Equation 9: R RG 10 k W 100 W Req = F = = 99 W RF + RG 10 k W + 100 W (9) The resistor noise for the second example is calculated in Equation 10: Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 19 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com Device Functional Modes (continued) enr = 4kTReq = 4 1.38 10-23 J/K 298 K 99 W = 1 nV/ Hz (10) The total noise at the input of the op amp is calculated in Equation 10: en in = env 2 + enr 2 = (20 nV/ Hz )2 + (1 nV/ Hz )2 = 20 nV/ Hz (11) For the second example the input noise, multiplied with the noise gain, in Equation 12 gives an output noise of: en out = en in Anoise = 20 nV/ Hz 101 = 2 mV/ Hz (12) In the first example the noise is dominated by the resistor noise due to the very high resistor values, in the second example the very low resistor values add only a negligible contribution to the noise and now the dominating factor is the op amp itself. When selecting the resistor values, it is important to choose values that do not add extra noise to the application. Choosing values above 100 k may increase the noise too much. Low values keep the noise within acceptable levels; choosing very low values however, does not make the noise even lower, but can increase the current of the circuit. 7.5 Interfacing to High Impedance Sensor With CMOS inputs, the LMV84x are particularly suited to be used as high impedance sensor interfaces. Many sensors have high source impedances that may range up to 10 M. The input bias current of an amplifier loads the output of the sensor, and thus cause a voltage drop across the source resistance, as shown in Figure 37. When an op amp is selected with a relatively high input bias current, this error may be unacceptable. The low input current of the LMV84x significantly reduces such errors. The following examples show the difference between a standard op amp input and the CMOS input of the LMV84x. The voltage at the input of the op amp can be calculated with Equation 13: VIN+ = VS - IB x RS (13) For a standard op amp, the input bias Ib can be 10 nA. When the sensor generates a signal of 1 V (VS) and the sensors impedance is 10 M (RS), the signal at the op amp input is calculated in Equation 14: VIN = 1 V - 10 nA x 10 M = 1 V - 0.1 V = 0.9 V (14) For the CMOS input of the LMV84x, which has an input bias current of only 0.3 pA, this would give Equation 15: VIN = 1 V - 0.3 pA x 10 M = 1 V - 3 V = 0.999997 V (15) The conclusion is that a standard op amp, with its high input bias current input, is not a good choice for use in impedance sensor applications. The LMV84x devices, in contrast, are much more suitable due to the low input bias current. The error is negligibly small; therefore, the LMV84x are a must for use with high-impedance sensors. SENSOR RS VS + - IB V VIN+ + + - V Figure 37. High Impedance Sensor Interface 20 Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The rail-to-rail input and output of the LMV84x and the wide supply voltage range make these amplifiers ideal to use in numerous applications. Three sample applications, namely the active filter circuit, high-side current sensing, and thermocouple sensor interface, are provided in the Typical Applications section. 8.2 Typical Applications 8.2.1 Active Filter Circuit C C R2 R2 R1 C - R1 C - R3 + R3 + Figure 38. Active Band-Pass Filter Implementation 8.2.1.1 Design Requirements In this example it is required to design a bandpass filter with band-pass frequency of 10 kHz, and a center frequence of approximately 10% from the total frequence of the filter. This is achieved by cascading two bandpass filters, A and B, with slightly different center frequencies. 8.2.1.2 Detailed Design Procedure The center frequency of the separate band-pass filters A, and B can be calculated by Equation 16: fmid = R1 + R3 1 2pC R1R2R3 where * * * * C = 33 nF R1 = 2 K R2 = 6.2 K and R3 = 45 (16) This gives Equation 17 for filter A: fmid = 1 p 33 nF 2 k W + 6.2 k W = 9.2 kHz 2 k W 6.2 k W 45 k W (17) and Equation 18 for filter B with C = 27nF: fmid = 1 p 27 nF 2 k W + 6.2 k W = 11.2 kHz 2 k W 6.2 k W 45 k W (18) Bandwidth can be calculated by Equation 19: Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 21 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com Typical Applications (continued) B= 1 pR2C (19) For filter A, this gives Equation 20: 1 = 1.6 kHz B= p 6.2 k W 33 nF (20) and Equation 21 for filter B: 1 = 1.9 kHz B= p 6.2 k W 27 nF (21) 8.2.1.3 Application Curve The responses of filter A and filter B are shown as the thin lines in Figure 39; the response of the combined filter is shown as the thick line. Shifting the center frequencies of the separate filters farther apart, results in a wider band; however, positioning the center frequencies too far apart results in a less flat gain within the band. For wider bands more band-pass filters can be cascaded. 10 FILTER A FILTER B GAIN (dB) 0 -10 -20 -30 COMBINED FILTER -40 1k 10k 100k FREQUENCY (Hz) Figure 39. Active Band-Pass Filter Curve NOTE Use the WEBENCH internet tools at www.ti.com for your filter application. 8.2.2 High-Side, Current-Sensing Circuit V RF + RG RS + RG RF LOAD Z Figure 40. High-Side, Current-Sensing Circuit 22 Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 Typical Applications (continued) 8.2.2.1 Design Requirements In this example, it is desired to measure a current between 0 A and 2 A using a sense resistor of 100 m, and convert it to an output voltage of 0 to 5 V. A current of 2 A flowing through the load and the sense resistor results in a voltage of 200 mV across the sense resistor. The op amp amplifies this 200 mV to fit the current range to the output voltage range. 8.2.2.2 Detailed Design Procedure To measure current at a point in a circuit, a sense resistor is placed in series with the load, as shown in Figure 40. The current flowing through this sense resistor results in a voltage drop, that is amplified by the op amp. The rail-to-rail input and the low VOS features make the LMV84x ideal op amps for high-side, currentsensing applications. The input and the output relation of the circuit is given by Equation 22: VOUT = RF/RG x VSENSE (22) For a load current of 2 A and an output voltage of 5 V the gain would be VOUT / VSENSE = 25. If the feedback resistor, RF, is 100 k, then the value for RG is 4 k. The tolerance of the resistors has to be low to obtain a good common-mode rejection. 8.2.3 Thermocouple Sensor Signal Amplification Figure 41 is a typical example for a thermocouple amplifier application using an LMV841, LMV842, or LMV844. A thermocouple senses a temperature and converts it into a voltage. This signal is then amplified by the LMV841, LMV842, or LMV844. An ADC can then convert the amplified signal to a digital signal. For further processing the digital signal can be processed by a microprocessor, and can be used to display or log the temperature, or the temperature data can be used in a fabrication process. Cold junction Temperature LM35 RF RG T Metal A Copper - RG LMV841 + Metal B Thermocouple Copper Amplified Thermocouple Output RF Cold junction Reference Figure 41. Thermocouple Sensor Interface 8.2.3.1 Design Requirements In this example it is desired to measure temperature in the range of 0C to 500C with a resolution of 0.5C using a K-type thermocouple sensor. The power supply for both the LMV84x and the ADC is 3.3 V. 8.2.3.2 Detailed Design Procedure A thermocouple is a junction of two different metals. These metals produce a small voltage that increases with temperature. A K-type thermocouple is a very common temperature sensor made of a junction between nickelchromium and nickel-aluminum. There are several reasons for using the K-type thermocouple. These include temperature range, the linearity, the sensitivity, and the cost. Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 23 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com Typical Applications (continued) A K-type thermocouple has a wide temperature range. The range of this thermocouple is from approximately -200C to approximately 1200C, as can be seen in Figure 42. This covers the generally used temperature ranges. Over the main part of the range the behavior is linear. This is important for converting the analog signal to a digital signal. The K-type thermocouple has good sensitivity when compared to many other types; the sensitivity is 41 V/C. Lower sensitivity requires more gain and makes the application more sensitive to noise. In addition, a K-type thermocouple is not expensive, many other thermocouples consist of more expensive materials or are more difficult to produce. THERMOCOUPLE VOLTAGE (mV) 50 40 30 20 10 0 -10 -200 0 200 400 600 800 1000 1200 TEMPERATURE (C) Figure 42. K-Type Thermocouple Response The temperature range of 0C to 500C results in a voltage range from 0 mV to 20.6 mV produced by the thermocouple. This is shown in Figure 42. To obtain the best accuracy the full ADC range of 0 to 3.3 V is used and the gain needed for this full range can be calculated Equation 23: AV = 3.3 V / 0.0206 V = 160 (23) If RG is 2 k, then the value for RF can be calculated with this gain of 160. Because AV = RF / RG, RF can be calculated in Equation 24: RF = AV x RG = 160 x 2 k = 320 k (24) To achieve a resolution of 0.5C a step smaller than the minimum resolution is needed. This means that at least 1000 steps are necessary (500C/0.5C). A 10-bit ADC would be sufficient as this gives 1024 steps. A 10-bit ADC such as the two channel 10-bit ADC102S021 would be a good choice. At the point where the thermocouple wires are connected to the circuit on the PCB unwanted parasitic thermocouple is formed, introducing error in the measurements of the actual thermocouple sensor. Using an isothermal block as a reference will compensate for this additional thermocouple effect. An isothermal block is a good heat conductor. This means that the two thermocouple connections both have the same temperature. The temperature of the isothermal block can be measured, and thereby the temperature of the thermocouple connections. This is usually called the cold junction reference temperature. In the example, an LM35 is used to measure this temperature. This semiconductor temperature sensor can accurately measure temperatures from -55C to 150C. The ADC in this example also coverts the signal from the LM35 to a digital signal, hence, the microprocessor can compensate for the amplified thermocouple signal of the unwanted thermocouple junction at the connector. 24 Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 LMV841, LMV842, LMV844 www.ti.com SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 9 Power Supply Recommendations The LMV84x is specified for operation from 2.7 V to 12 V (1.35 V to 6 V) over a -40C to 125C temperature range. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Absolute Maximum Ratings. CAUTION Supply voltages larger than 13.2 V can permanently damage the device. For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI suggests placing 10-nF capacitors as close as possible to the operational amplifier power supply pins. For single supply, place a capacitor between V+ and V- supply leads. For dual supplies, place one capacitor between V+ and ground, and one capacitor between V- and ground. 10 Layout 10.1 Layout Guidelines * * * * * The V+ pin must be bypassed to ground with a low-ESR capacitor. The optimum placement is closest to the V+ and ground pins. Take care to minimize the loop area formed by the bypass capacitor connection between V+ and ground. The ground pin must be connected to the PCB ground plane at the pin of the device. The feedback components must be placed as close to the device as possible to minimize strays. 10.2 Layout Example Place components close to device and to each other to reduce parasitic error VOUTA Place low-ESR ceramic bypass capacitor close to device RF Run the input traces as far away from the supply lines as possible OUTA V+ GND -INA OUTB VIN +INA -INB V- +INB GND RG Place low-ESR ceramic bypass capacitor close to device GND VS- Figure 43. Layout Example (Top View) Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 Submit Documentation Feedback 25 LMV841, LMV842, LMV844 SNOSAT1I - OCTOBER 2006 - REVISED OCTOBER 2017 www.ti.com 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 1. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMV841 Click here Click here Click here Click here Click here LMV842 Click here Click here Click here Click here Click here LMV844 Click here Click here Click here Click here Click here 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright (c) 2006-2017, Texas Instruments Incorporated Product Folder Links: LMV841 LMV842 LMV844 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMV841MG/NOPB ACTIVE SC70 DCK 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 A97 LMV841MGX/NOPB ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 A97 LMV842MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMV84 2MA LMV842MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMV84 2MA LMV842MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green NIPDAUAG | SN Level-1-260C-UNLIM -40 to 125 AC4A LMV842MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green NIPDAUAG | SN Level-1-260C-UNLIM -40 to 125 AC4A LMV844MA/NOPB ACTIVE SOIC D 14 55 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 LMV844MA LMV844MAX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 LMV844MA LMV844MT/NOPB ACTIVE TSSOP PW 14 94 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMV844 MT LMV844MTX/NOPB ACTIVE TSSOP PW 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LMV844 MT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 10-Dec-2020 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMV841, LMV842, LMV844 : * Automotive: LMV841-Q1, LMV842-Q1, LMV844-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LMV841MG/NOPB SC70 DCK 5 1000 178.0 LMV841MGX/NOPB SC70 DCK 5 3000 LMV842MAX/NOPB SOIC D 8 2500 LMV842MM/NOPB VSSOP DGK 8 LMV842MMX/NOPB VSSOP DGK B0 (mm) K0 (mm) P1 (mm) 8.4 2.25 2.45 1.2 4.0 178.0 8.4 2.25 2.45 1.2 330.0 12.4 6.5 5.4 2.0 1000 178.0 12.4 5.3 3.4 8 3500 330.0 12.4 5.3 W Pin1 (mm) Quadrant 8.0 Q3 4.0 8.0 Q3 8.0 12.0 Q1 1.4 8.0 12.0 Q1 3.4 1.4 8.0 12.0 Q1 LMV844MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMV844MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV841MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV841MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LMV842MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMV842MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMV842MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMV844MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMV844MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI's products are provided subject to TI's Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI's provision of these resources does not expand or otherwise alter TI's applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2020, Texas Instruments Incorporated