Core10/100 Ethernet Media Access Controller Product Summary * Intended Use * Ethernet Media Access Controller * Supports 10/100 Mb/s Half/Full-Duplex Operations * Supports CSMA/CD Defined by IEEE 802.3 Standard * * * * * Network Interface Features - Supports 10/100 Mb/s Data Transfer Rate - Media Independent Interface (MII) Meets the IEEE 802.3 CSMA/CD Standard - Full or Half-Duplex Operation - Flexible Address Filtering - External RAM for Storing MAC Addresses - Up to 16 Physical Addresses - 512-Bit Hash Table for Multicast Addresses Operates as Internal Configurable FIFOs - Programmable Threshold Levels - "Store and Forward" Functionality * ProACIS3/E * ProASICPLUS(R) * Axcelerator(R) * RTAX-S Core Deliverables Data Link-Layer Functionality - - Supported Families Key Features * Transmit/Receive RAM Interfaces * Evaluation Version - * Netlist Version - Structural Verilog and VHDL Netlists (with and without I/O Pads) Compatible with Actel's Designer Software Place-and-Route Tool - Compiled RTL Simulation Model Supported in Actel's Libero IDE Control and Status Registers - Configurable 8-, 16-, or 32-Bit Slave Interface - Single Interrupt Line - Interrupt Mitigation Control Mechanism * Host Interface and DMA Controller - Configurable 8-, 16-, 32-Bit Data Bus Length - Configurable Address Bus Length - Big or Little Endian Data Byte Ordering - Scatter/Gather Capabilities - Programmable Burst Length - Intelligent Arbitration between Transmit and Receive Processes * Descriptor "Ring" or "Chain" Structures - Single Descriptor Pointing to up to Two Data Buffers - Automatic Descriptor List Pooling Fully RTL Version - Verilog and VHDL Core Source Code - Core Synthesis Scripts Testbench (Verilog and VHDL) Synthesis and Simulation Support Descriptor/Buffer Architecture for Data Storage - Compiled RTL Simulation Model Fully Supported in Actel's Libero(R) Integrated Design Environment (IDE) * Synthesis: Synplicity(R), Synopsys(R) (Design (R)/ FPGA CompilerTM), ExemplarTM Compiler * Simulation: OVI-Compliant Verilog Simulators and Vital-Compliant VHDL Simulators Low-Power Capabilities - Independent Clocks for Data and Control Paths - Run/Suspend/Stop Modes of Operation May 2005 (c) 2005 Actel Corporation v 3 .1 1 Core10/100 Ethernet Media Access Controller Contents General Description General Description . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Descriptions . . . . . . . . . . . . . . . . Core10/100 Variations and Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Utilization and Performance . . . . . . . . . . . I/O Signal Description . . . . . . . . . . . . . . . . . . . . . . . Control and Status Register (CSR) Interface . . . . . CSR Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Data and Frame Descriptors . . . . . . . . . . . . Transmit Data / Receive Data /Address RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Timer . . . . . . . . . . . . . . . . . . . . . . Data Link Layer Operation . . . . . . . . . . . . . . . . . . . Clock and Reset Control . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . Core10/100 is a high-speed MAC Ethernet controller (Figure 1). It implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for media access control over an Ethernet connection. Communication with an external host is implemented via a set of Control and Status Registers and the DMA controller for external shared RAM memory. For data transfers, Core10/100 operates as a DMA master. It automatically fetches from transmit data buffers and stores receive data buffers into external RAM with minimum CPU intervention. The linked list management enables the use of various memory allocation schemes. External RAMs are used as configurable FIFO memories and there are separate memories for transmit and receive processes. The core has a generic host-side interface that connects with external CPUs. This host interface can be configured to work with 8-, 16-, or 32-bit data bus widths with big or little endian byte ordering. Figure 2 on page 3 shows a typical application using Core10/100. Typical applications include: LAN controllers, AFDX controllers, and embedded systems. Figure 3 on page 3 shows the primary blocks of Core10/100. 2 4 5 5 6 8 10 22 24 34 35 35 37 38 40 40 47 48 48 48 Transmit Data RAM Transmit Control Data Interface DATA Controller Receive MII Receive Control Control Interface Control and Status Registers and Control Logic Receive Data RAM Figure 1 * Core10/100 Block Diagram 2 Transmit MII v3.1 Address RAM Transmit RAM Core10/100 Ethernet Media Access Controller Shared RAM CPU (8-, 16- or 32-Bit) Data Interface Bus Core10100 PHY MII Interface Receive RAM Address RAM Control Interface Bus Figure 2 * Typical Core10/100 Application Transmit Data RAM clkt clkdma TLSM TFIFO TC Transmit MII BD Data Interface DMA Receive MII RC RLSM External Address Filtering Interface RFIFO clkr Receive Data RAM MII Managment Interface clkcsr CSR (Control and Status Registers and Control Logic) csr Interface tps rps Serial ROM Interface int rst Address RAM RSTC Figure 3 * Core10/100 Architecture v3.1 3 Core10/100 Ethernet Media Access Controller Functional Block Descriptions BD - Backoff/Deferring Core10/100 architecture, shown in Figure 3 on page 3, consists of the functional blocks described in this section. The backoff/deferring controller implements the 802.3 half duplex operation. It monitors the status of the Ethernet bus and decides whether to perform a transmit or backoff/deferring of the data via the MII. It operates synchronously with the clkt clock from the MII interface. CSR - Control/Status Register Logic The CSR component is used to control Core10/100 operation by the host. It implements the CSR register set, the interrupt controller, and the power management functionality of Core10/100. It also provides a generic host interface supporting 8-, 16-, and 32-bit transfer. The CSR component operates synchronously with the clkcsr clock from the host CSR interface. The CSR also provides a Serial ROM interface and MII Management interface. The host can access these two interfaces via read/write CSR registers. The receive linked list state machine implements the descriptor/buffer architecture of Core10/100. It manages the receive descriptor list and moves the data from the receive FIFO into the data buffers. The receive linked list state machine controller operates synchronously with the clkdma clock from the host data interface. RFIFO - Receive FIFO DMA - Direct Memory Access Controller The direct memory access controller implements the host data interface. It services both the receive and the transmit channels. The TLSM and TFIFO have access to one DMA channel. The RLSM and RFIFO have access to the other DMA channel. The direct memory access controller operates synchronously with the clkdma clock from the host data interface. TLSM - Transmit Linked List State Machine The transmit linked list state machine implements the descriptor/buffer architecture of Core10/100. It manages the transmit descriptor list and fetches the data prepared for transmission from the data buffers into the transmit FIFO. The transmit linked list state machine controller operates synchronously with the clkdma clock from the host data interface. The receive FIFO is used for buffering data received by Core10/100. It provides an interface for the external RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core. The receive FIFO controller operates synchronously with the clkdma clock from the host data interface. RC - Receive Controller The receive controller implements the 802.3 receive operation. From the network side it uses the standard 802.3 MII interface for an external PHY device. The RC block transfers data received from the MII to the Receive Data RAM. It supports internal address filtering using an external Address RAM. It also supports an external address filtering interface. The receive controller operates synchronously with the clkr clock from the MII interface. RSTC - Reset Controller TFIFO - Transmit FIFO The transmit FIFO is used for buffering data prepared for transmission by Core10/100. It provides an interface for the external Transmit Data RAM working as FIFO memory. It fetches the transmit data from the host via the DMA interface. The FIFO size can be configured via the core parameters. The transmit FIFO controller operates synchronously with the clkdma clock from the host data interface. TC - Transmit Controller The transmit controller implements the 802.3 transmit operation. From the network side, it uses the standard 802.3 MII interface for an external PHY device. The TC unit reads transmit data from the external Transmit Data RAM, formats the frame, and transmits the framed data via the MII. The transmit controller operates synchronously with the clkt clock from the MII interface. 4 RLSM - Receive Linked List State Machine v3.1 The reset controller is used to reset all components for Core10/100. It generates a reset signal asynchronous to all clock domains in the design from the external reset line and a software reset. External Components There are three external components required for proper operation of Core10/100: * Receive Data RAM - Synchronous RAM working as receive FIFO. * Transmit Data RAM - Synchronous RAM working as transmit FIFO. * Address RAM - Synchronous RAM working as MAC addresses memory. Core10/100 Ethernet Media Access Controller Core10/100 Variations and Memory Requirements Core10/100 supports a generic host interface with an 8-, 16-, or 32-bit wide data bus. Core10/100 also supports different sizes of Transmit Data RAM and Receive Data RAM (Table 1). Table 1 * Core10/100 Configurable Parameters Name Value Descriptions CSRWIDTH 8, 16, 32 Data bus width of the CSR interface DATAWIDTH 8, 16, 32 Data bus width of the DATA interface DATADEPTH 321 up to TFIFODEPTH RFIFODEPTH Address bus width of the DATA interface 6-16 2 Address bus width of the Transmit Data RAM 6-16 2 Address bus width of the Receive Data RAM Notes: 1. The data depth is fixed to 16 kbytes for the netlist version. 2. The Transmit/Receive FIFO depth is fixed to 2 kbytes for the netlist version. For detailed information, refer to the following sections: * CSRWIDTH - "Control and Status Register (CSR) Interface" on page 1-8 * DATAWIDTH and DATADEPTH - "Data Interface" on page 1-22 * TFIFODEPTH and RFIFODEPTH - "Transmit Data / Receive Data /Address RAM Interface" on page 134 The size of the Transmit Data RAM is 2TFIFODEPTH * DATAWIDTH/8 in bytes. The size of the Receive Data RAM is 2RFIFODEPTH * DATAWIDTH/8 in bytes. Device Utilization and Performance Core10/100 can be implemented in the following Actel FPGA devices. Table 2 provides the typical utilization and performance data for the core implemented in these devices. Table 2 * Core10/100 Device Utilization and Performance Cells or Tiles Family Utilization Performance Combinatorial Sequential Total Device Total MHz 3,950 1,766 5,716 A3P400 62% 40 ProASIC 5,030 1,766 6,796 APA300 83% 25 Axcelerator 2,802 1,855 4,657 AX500 58% 70 RTAX 2,802 1,855 4,657 RTAX1000S 26% 49 ProASIC3/E PLUS Note: Data in this table was achieved using typical synthesis and layout settings using the following parameters: CSRWIDTH = 8, DATAWIDTH = 8, DATADEPTH = 16, TFIFODEPTH = 11, RFIFODEPTH = 11. Performance was achieved using the Core10/100 macro alone, and represents the system clock (clkdma) frequency; the clkr and clkt clock domains are capable of operating at 25 MHz or 2.5 MHz, depending on the link speed. The clkcsr clock domain is capable of operating in excess of the value listed. v3.1 5 Core10/100 Ethernet Media Access Controller I/O Signal Description Table 3 * I/O Signal Description Name Type Polarity/Bus Size Description General Host Interface Signals rstcsr In High Host side reset int Out High Interrupt rsttco Out High Transmit side reset rstrco Out High Receive side reset tps Out High Transmit process stopped rps Out High Receive process stopped Control and Status Register Interface clkcsr In Rise CSR clock csrreq In High CSR request csrrw In High CSR read/write selection csrbe In CSRWIDTH/8 CSR byte enable csrdatai In CSRWIDTH CSR data input csraddr In 8 csrack Out High csrdatao Out CSRWIDTH CSR address CSR acknowledge CSR data output Data Interface clkdma In Rise Data clock dataack In High Data acknowledge datai In DATAWIDTH Data output datareq Out High Data request datarw Out High Data read/write selection dataeob Out High Data end of burst datao Out DATAWIDTH Data input dataaddr Out DATADEPTH Data address Transmit RAM Interface trdata In DATAWIDTH Transmit RAM read data traddr Out TFIFODEPTH Transmit RAM read address twdata Out DATAWIDTH Transmit RAM write data twe Out High Transmit RAM write enable twaddr Out TFIFODEPTH Transmit RAM write address Receive RAM Interface rrdata In DATAWIDTH Receive RAM read data rraddr Out RFIFODEPTH Receive RAM read address rdatao Out DATAWIDTH Receive RAM data output rwe Out High Receive RAM write enable Note: Refer to Table 1 on page 5 for CSRWIDTH, DATAWIDTH, DATADEPTH, TFIFODEPTH, and RFIFODEPTH. 6 v3.1 Core10/100 Ethernet Media Access Controller Table 3 * I/O Signal Description (Continued) Name Type Polarity/Bus Size rwaddr Out RFIFODEPTH Description Receive RAM write address Address Filtering RAM Interface frdata In 16 Address filtering RAM read data fraddr Out 6 Address filtering RAM read address fwe Out High Address filtering RAM write enable fwaddr Out 6 Address filtering RAM write address fwdata Out 16 Address filtering RAM write data Serial ROM Interface sdi In 1 Serial data scs Out 1 Serial chip select sclk Out 1 Serial clock output sdo Out 1 Serial data output External Address Filtering Interface match In High External address match matchval In High External address match valid matchen Out High External address match enable matchdata Out 48 Match data MII PHY Interface clkt In rise Transmit clock clkr In rise Receive clock rxer In High MII Receive error rxdv In High MII Receive data valid col In High MII Collision detect crs In High MII Carrier sense mdi In 1 MII management data input rxd In 4 MII Receive data txen Out High MII Transmit enable txer Out High MII Transmit error mdc Out Rise MII management clock mdo Out 1 mden Out High txd Out 4 MII management data output MII management buffer control MII Transmit data Note: Refer to Table 1 on page 5 for CSRWIDTH, DATAWIDTH, DATADEPTH, TFIFODEPTH, and RFIFODEPTH. The number of Core10/100 I/O signals may vary from approximately 70 to 400, depending on parameter settings. To reduce the number of device I/O package pins, Actel recommends the use of FPGA on-chip RAM blocks for the Transmit FIFO, Receive FIFO, and Address RAMs. v3.1 7 Core10/100 Ethernet Media Access Controller Control and Status Register (CSR) Interface Control and Status Registers Addressing The Control and Status Register (CSR) interface is a slave interface that the host initiates for write or read transactions. The CSR interface operates synchronously with the clkcsr clock supplied by the host. The data width of the CSR interface is set with the CSRWIDTH parameter, defined in Table 1 on page 5. The CSR interface may be set to operate through an 8-, 16- or 32-bit bus interface. The Control and Status Registers are located physically inside Core10/100 and can be accessed directly by a host via an 8-, 16- or 32-bit interface. All the CSRs are 32 bits long and quad word-aligned. The address bus of the CSR interface is eight bits wide, and only bit 6 to bit 0 of the location code shown in Table 4 may be used to decode the CSR register address. Refer to csraddr in Table 5 on page 9 for details about the address decoding. Table 4 * CSR Locations Register Address Reset value CSR0 00H FE000000H CSR1 08H FFFFFFFFH Transmit poll demand CSR2 10H FFFFFFFFH Receive poll demand CSR3 18H FFFFFFFFH Receive list base address CSR4 20H FFFFFFFFH Transmit list base address CSR5 28H F0000000H Status CSR6 30H 32000040H Operation mode CSR7 38H F3FE0000H Interrupt enable CSR8 40H E0000000H Missed frames and overflow counters CSR9 48H FFF483FFH MII management CSR11 58H FFFE0000H Timer and interrupt mitigation control 8 v3.1 Description Bus mode Core10/100 Ethernet Media Access Controller CSR Interface Signals Table 5 * CSR Interface Signals Name Type Polarity/Bus Size Description csrreq In High This signal is set by a host in order to put a "request" for a data transfer on the CSR interface. It may be a read or a write request depending on the value of the csrrw signal. csrrw In 1 This signal indicates the type of request on the CSR interface. Setting the csrwr indicates a read operation, and clearing it indicates a write operation. csrbe In CSRWIDTH/8 This signal is the data byte enable to indicate which byte lanes of the csrdatai or csrdatao are the "valid" data bytes. Each bit of the csrbe controls a single byte lane. All the csrbe signal combinations are allowed. csraddr In 8 The csraddr inputs address an individual CSR data transaction. The meaning of csraddr depends on the CSRWIDTH parameter. For the CSRWIDTH = 32 (32-bit interface), only the csraddr bits 6 down to 2 are significant. The addresses are longword (32-bit) aligned in this mode. For the CSRWIDTH = 16 (16-bit interface), the csraddr bits 6 down to 1 are significant. The addresses are word (16-bit) aligned in this mode. For the CSRWIDTH = 8 (8-bit interface), all bits of the csraddr are significant. The addresses are byte (8-bit) aligned in this mode. csrdatai In CSRWIDTH csrack Out High csrdatao Out CSRWIDTH The write data is provided on the csrdatai inputs by the system during the write request. The csrack signal indicates that either valid data is present on the csrdatao outputs during a read request, or that the csrdatai inputs have been sampled during a write request. The current version of Core10/100 has the csrack signal statically tied to logic 1, i.e., Core10/ 100 responds to reads and writes immediately. The csrdatao signal provides the read data in response to a read request. CSR Read/Write Operation The CSR read and write operations are synchronous to the positive edge of the clkcsr signal and are illustrated in Figure 4. Read operations require the data is read in the same clock cycle in which the csrreq signal is set to logic 1. Read Write Read clk csrreq csrrw csrbe csraddr be be be addr addr addr csrdatai csrdatao data data data Figure 4 * CSR Read/Write Operation v3.1 9 Core10/100 Ethernet Media Access Controller CSR Definitions Table 6 * Bus Mode Register (CSR0) Bits 31:24 Bits 23:16 DBO TAP PBL Bits 15:8 Bits 7:0 BLE DSL BAR SWR Note: The CSR0 register has unimplemented bits (shaded). If these bits are read, they will return a predefined value. Writing these bits has no effect. Table 7 * Bus Mode Register Bit Functions Bit CSR0.20 Symbol DBO Function Descriptor byte ordering mode 1 - big endian mode used for data descriptors 0 - little endian mode used for data descriptors CSR0.(19..17) TAP Transmit automatic polling If the TAP is written with a nonzero value, Core10/100 performs an automatic transmit descriptor polling when operating in suspended state. When the descriptor is available, the transmit process goes into the running state. When the descriptor is marked as owned by the host, the transmit process remains suspended. The poll is always performed at the current transmit descriptor list position. The time interval between two consecutive polls is shown in Table 8 on page 11. CSR0.(13..8) PBL Programmable burst length Specifies the maximum number of words that can be transferred within one DMA transaction. Values permissible are 0, 1, 2, 4, 8, 16, and 32. When a '0' value is written, the bursts are limited only by the internal FIFO's threshold levels. The width of the single word is equal to the CSRWIDTH generic parameter, i.e.. all data transfers always use the maximum data bus width. Note that the PBL is valid only for the data buffers. The data descriptors burst length depends on a DATAWIDTH parameter. The rule is that every descriptor field (32-bit) is accessed with a single burst cycle. For the DATAWIDTH = 32, the descriptors are accessed with a single 32-bit word transaction; for the DATAWIDTH = 16, a burst of two 16-bit words; and for the DATAWIDTH = 8, a burst of four 8-bit words. CSR0.7 BLE Big/little endian Selects the byte-ordering mode used by the data buffers 1 - big endian mode used for the data buffers 0 - little endian mode used for the data buffers CSR0.(6..2) DSL Descriptor skip length Specifies the number of longwords between two consecutive descriptors in a ring structure. CSR0.1 BAR Bus arbitration scheme 1 - transmit and receive processes have equal priority to access the bus 0 - intelligent arbitration where the receive process has priority over the transmit process CSR0.0 SWR Software reset Setting this bit resets all internal flip-flops 10 v3.1 Core10/100 Ethernet Media Access Controller Table 8 * Transmit Automatic Polling Intervals CSR0(19..17) 10 Mb/s 100 Mb/s 000 TAP disabled TAP disabled 001 819 s 81.9 s 010 2450 s 245 s 011 5730 s 573 s 100 51.2 s 5.12 s 101 102.4 s 10.24 s 110 153.6 s 15.36 s 111 358.4 s 35.84 s Table 9 * Transmit Poll Demand Register (CSR1) Bits 31:24 TPD(31..24) Bits 23:16 TPD(23..16) Bits 15:8 TPD(15..8) Bits 7:0 TPD(7..0) Table 10 * Transmit Poll Demand Bit Functions Bit CSR1.(31..0) Symbol Function TPD Writing this field with any value instructs Core10/100 to check for frames to be transmitted. This operation is valid only when the transmit process is suspended. If no descriptor is available, the transmit process remains suspended. When the descriptor is available, the transmit process goes into the running state. Table 11 * Receive Poll Demand Register (CSR2) Bits 31:24 RPD(31..24) Bits 23:16 RPD(23..16) Bits 15:8 RPD(15..8) Bits 7:0 RPD(7..0) Table 12 * Receive Poll Demand Bit Functions Bit CSR2.(31..0) Symbol Function RPD Writing this field with any value instructs Core10/100 to check for receive descriptors to be acquired. This operation is valid only when the receive process is suspended. If no descriptor is available, the receive process remains suspended. When the descriptor is available, the receive process goes into the running state. Table 13 * Receive Descriptor List Base Address Register (CSR3) Bits 31:24 RLA(31..24) Bits 23:16 RLA(23..16) Bits 15:8 RLA(15..8) Bits 7:0 RLA(7..0) v3.1 11 Core10/100 Ethernet Media Access Controller Table 14 * Receive Descriptor List Base Address Register Bit Functions Bit CSR 3.(31..0) Symbol RLA Function Start of the receive list address Contains the address of the first descriptor in a receive descriptor list. This address should be longword aligned (RLA(1..0)=00). Table 15 * Transmit Descriptor List Base Address Register (CSR4) Bits 31:24 TLA(31..24) Bits 23:16 TLA(23..16) Bits 15:8 TLA(15..8) Bits 7:0 TLA(7..0) Table 16 * Transmit Descriptor List Base Address Register Bit Functions Bit CSR 4.(31..0) Symbol TLA Function Start of the transmit list address Contains the address of the first descriptor in a transmit descriptor list. This address should be longword aligned (TLA(1..0)=00). Table 17 * Status Register (CSR5) Bits 31:24 Bits 23:16 TS Bits 15:8 AIS ERI Bits 7:0 RU RI GTE RS NIS ETI RPS TU UNF TPS TI Note: The CSR5 register has unimplemented bits (shaded). If these bits are read they will return a predefined value. Writing these bits has no effect. 12 v3.1 Core10/100 Ethernet Media Access Controller Table 18 * Status Register Bit Functions Bit CSR5.(22..20) Symbol TS Function Transmit process state (Read only) Indicates the current state of a transmit process: 000 - Stopped, RESET, or STOP TRANSMIT command issued 001 - Running, fetching transmit descriptor 010 - Running, waiting for end of transmission 011 - Running, transferring data buffer from host memory to FIFO 100 - Reserved 101 - Running, setup packet 110 - Suspended, FIFO underflow or unavailable descriptor 111 - Running, closing transmit descriptor CSR5.(19..17) RS Receive process state (Read only) Indicates the current state of a receive process: 000 - Stopped, RESET, or STOP RECEIVE command issued 001 - Running, fetching receive descriptor 010 - Running, waiting for the end of receive packet before prefetch of next descriptor 011 - Running, waiting for receive packet 100 - Suspended, unavailable receive buffer 101 - Running, closing receive descriptor 110 - Reserved 111 - Running, transferring data from FIFO to host memory CSR5.16 NIS Normal interrupt summary This bit is logical or on the following bits: CSR5.0 - Transmit interrupt CSR5.2 - Transmit buffer unavailable CSR5.6 - Receive interrupt CSR5.11 - General purpose timer overflow CSR5.14 - Early receive interrupt Only the unmasked bits affect the normal interrupt summary bit. The user can clear this bit by writing a '1'. Writing a '0' has no effect. CSR5.15 AIS Abnormal interrupt summary This bit is logical or on the following bits: CSR5.1 - Transmit process stopped CSR5.5 - Transmit underflow CSR5.7 - Receive buffer unavailable CSR5.8 - Receive process stopped CSR5.10 - Early transmit interrupt Only the unmasked bits affect the abnormal interrupt summary bit. The user can clear this bit by writing a '1'. Writing a '0' has no effect. CSR5.14 ERI Early receive interrupt Set when Core10/100 fills the data buffers of the first descriptor The user can clear this bit by writing a '1'. Writing a '0' has no effect. v3.1 13 Core10/100 Ethernet Media Access Controller Table 18 * Status Register Bit Functions (Continued) Bit CSR5.11 Symbol GTE Function General-purpose timer expiration Gets set when the general-purpose timer reaches zero value The user can clear this bit by writing a '1'. Writing a '0' has no effect. CSR5.10 ETI Early transmit interrupt Indicates that the packet to be transmitted was fully transferred into the FIFO The user can clear this bit by writing a '1'. Writing a '0' has no effect. CSR5.8 RPS Receive process stopped RPS is set when a receive process enters a stopped state. The user can clear this bit by writing a '1'. Writing a '0' has no effect. CSR5.7 RU Receive buffer unavailable When set, indicates that the next receive descriptor is owned by the host and is unavailable for Core10/ 100. When the RU becomes set, Core10/100 enters a suspended state, and returns to receive descriptor processing when the host changes ownership of the descriptor and either a receive poll demand command is issued or a new frame is recognized by Core10/100. The user can clear this bit by writing a '1'. Writing a '0' has no effect. CSR5.6 RI Receive interrupt Indicates the end of a frame receive. The complete frame has been transferred into the receive buffers. Assertion of the RI bit can be delayed using receive interrupt mitigation counter/timer (CSR11.NRP/ CSR11.RT). The user can clear this bit by writing a '1'. Writing a '0' has no effect. CSR5.5 UNF Transmit underflow Indicates that the transmit FIFO was empty during a transmission. The transmit process goes into a suspended state. The user can clear this bit by writing a '1'. Writing a '0' has no effect. CSR5.2 TU Transmit buffer unavailable When set, TU indicates that the host owns the next descriptor on the transmit descriptor list; therefore, it cannot be used by Core10/100. When the TU is set, the transmit process goes into a suspended state and can resume normal descriptor processing when the host changes ownership of the descriptor, and either a transmit poll demand command is issued or transmit automatic polling is enabled. The user can clear this bit by writing a '1'. Writing a '0' has no effect. CSR5.1 TPS Transmit process stopped TPS is set when the transmit process goes into a stopped state. The user can clear this bit by writing a '1'. Writing a '0' has no effect. CSR5.0 TI Transmit interrupt Indicates the end of a frame transmission process. Assertion of the TI bit can be delayed using the transmit interrupt mitigation counter/timer (CSR11.NTP/CSR11.TT). The user can clear this bit by writing a '1'. Writing a '0' has no effect. 14 v3.1 Core10/100 Ethernet Media Access Controller Table 19 * Operation Mode Register (CSR6) Bits 31:24 RA Bits 23:16 TTM Bits 15:8 Bits 7:0 TR PM SF ST PR FD IF PB HO SR HP Note: The CSR6 register has unimplemented bits (shaded). If these bits are read they will return a predefined value. Writing these bits has no effect. Table 20 * Operation Mode Register Bit Functions Bit CSR6.30 Symbol RA Function Receive all When set, all incoming frames are received regardless of their destination address. An address check is performed and the result of the check is written into the receive descriptor (RDES0.30). CSR6.22 TTM Transmit threshold mode 1 - transmit the FIFO threshold set for 100 Mb/s mode 0 - transmit the FIFO threshold set for 10 Mb/s mode. This bit can be changed only when a transmit process is in a stopped state. CSR6.21 SF Store and forward When set, the transmission starts after a full packet is written into the transmit FIFO, regardless of the current FIFO threshold level. This bit can be changed only when the transmit process is in the stopped state. CSR6.(15..14) TR Threshold control bit This bit, together with the TTM, the SF and the PS, control the threshold level for the transmit FIFO. CSR6.13 ST Start/stop transmit command Setting this bit when the transmit process is in a stopped state causes a transition into a running state. In the running state Core10/100 checks the transmit descriptor at a current descriptor list position. If Core10/100 owns the descriptor, then the data starts to transfer from memory into the internal transmit FIFO. If the host owns the descriptor, Core10/100 enters a suspended state. Clearing this bit when the transmit process is in a running or a suspended state instructs Core10/100 to enter the stopped state. Core10/100 does not go into the stopped state immediately after clearing the ST bit. Core10/100 will finish all pending transmit operations before going into the stopped state. The status bits of the CSR5 register should be read to check the actual transmit operation state. CSR6.9 FD Full duplex mode 0 - half duplex mode 1 - forcing full duplex mode Changing of this bit is allowed only when both the transmitter and receiver processes are in the stopped state. CSR6.7 PM Pass all multicast When set, all the frames with the multicast destination addresses will be received regardless of the address check result. CSR6.6 PR Promiscuous mode When set all the frames will be received regardless of the address check result. An address check is not performed. v3.1 15 Core10/100 Ethernet Media Access Controller Table 20 * Operation Mode Register Bit Functions (Continued) Bit Symbol CSR6.4 IF Function Inverse filtering (Read only) If this bit is set when working in a perfect filtering mode, the receiver performs an inverse filtering during the address check process. The "filtering type" bits of the setup frame determine a state of this bit. CSR6.3 PB Pass bad frames When set, Core10/100 transfers all frames into the data buffers, regardless of the receive errors. This allows the runt frames, collided fragments, and truncated frames to be received. CSR6.2 HO Hash-only filtering mode (Read only) When set, Core10/100 performs an imperfect filtering over both the multicast and the physical addresses. The "filtering type" bits of the setup frame determine the state of this bit. CSR6.1 SR Start/stop receive command Setting this bit when the receive process is in a stopped state causes the transition into a running state. In the running state Core10/100 checks the receive descriptor at the current descriptor list position. If Core10/100 owns the descriptor, then it can process an incoming frame. When the host owns the descriptor, the receiver enters a suspended state and also sets the CSR5.7 (receive buffer unavailable) bit. Clearing this bit when the receive process is in running or suspended state instructs Core10/100 to enter a stopped state after receiving the current frame. Core10/100 does not go into the stopped state immediately after clearing the SR bit. Core10/100 will finish all pending receive operations before going into the stopped state. The status bits of CSR5 register should be read to check the actual receive operation state. CSR6.0 HP Hash/perfect receive filtering mode (Read only) 0 - perfect filtering of the incoming frames is performed according to the physical addresses specified in a setup frame. 1 - imperfect filtering over the frames with the multicast addresses is performed according to the hash table specified in a setup frame. A physical addresses check is performed according to the CSR6.2 (HO - Hash-only) bit. When the HO and HP are both set, an imperfect filtering is performed on all of the addresses. The "filtering type" bits of the setup frame determine the state of this bit. Table 21 lists all the possible combinations of the address filtering bits. The actual values of the IF, HO, and HP bits are determined by the filtering type (FT1:FT0) bits in the setup frame, as shown in Table 42 on page 32. The IF, HO, and HP bits are read-only. Table 21 * Receive Address Filtering Modes Summary PM CSR6.7 PR CSR6.6 IF CSR6.4 HO CSR6.2 HP CSR6.0 0 0 0 0 0 16 physical addresses - perfect filtering mode 0 0 0 0 1 1 physical address for physical addresses and 512-bit hash table for multicast addresses 0 0 0 1 1 512-bit hash table for both physical and multicast addresses 0 0 1 0 0 Inverse filtering x 1 0 0 x Promiscuous mode 0 1 0 1 1 Promiscuous mode 1 0 0 0 x Pass all multicast frames 1 0 0 1 1 Pass all multicast frames 16 v3.1 Current Filtering Mode Core10/100 Ethernet Media Access Controller Table 22 lists the transmit FIFO threshold levels. These levels are specified in bytes. Table 22 * Transmit Fifo Threshold Levels (Bytes) CSR6.21 CSR6.15..14 CSR6.22=1 CSR6.22=0 0 00 64 128 0 01 128 256 0 10 128 512 0 11 256 1024 1 xx Store and Forward Store and Forward Table 23 * Interrupt Enable Register (CSR7) Bits 31:24 Bits 23:16 NIE Bits 15:8 AIE ERE Bits 7:0 RUE RIE GTE ETE TUE UNE RSE TSE TIE Note: The CSR7 register has unimplemented bits (shaded). If these bits are read they will return a predefined value. Writing these bits has no effect. Table 24 * Interrupt Enable Register Bit Function Bit CSR7.16 Symbol NIE Function Normal interrupt summary enable When set, normal interrupts are enabled Normal interrupts are listed below: CSR5.0 - Transmit interrupt CSR5.2 - Transmit buffer unavailable CSR5.6 - Receive interrupt CSR5.11 - General-purpose timer expired CSR5.14 - Early receive interrupt CSR7.15 AIE Abnormal interrupt summary enable When set, abnormal interrupts are enabled Abnormal interrupts are listed below: CSR5.1 - Transmit process stopped CSR5.5 - Transmit underflow CSR5.7 - Receive buffer unavailable CSR5.8 - Receive process stopped CSR5.10 - Early transmit interrupt CSR7.14 ERE Early receive interrupt enable When both the ERE and normal interrupt enable bits are set, early receive interrupt is enabled. CSR7.11 GTE General-purpose timer overflow enable When both the GTE and normal interrupt summary enable bits are set, the general-purpose timer overflow interrupt is enabled. CSR7.10 ETE Early transmit interrupt enable When both the ETE and abnormal interrupt summary enable bits are set, the early transmit interrupt is enabled. v3.1 17 Core10/100 Ethernet Media Access Controller Table 24 * Interrupt Enable Register Bit Function (Continued) Bit Symbol CSR7.8 RSE Function Receive stopped enable When both the RSE and abnormal interrupt summary enable bits are set, the receive stopped interrupt is enabled. CSR7.7 RUE Receive buffer unavailable enable When both the RUE and abnormal interrupt summary enable bits are set, the receive buffer unavailable is enabled. CSR7.6 RIE Receive interrupt enable When both the RIE and normal interrupt summary enable bits are set, the receive interrupt is enabled. CSR7.5 UNE Underflow interrupt enable When both the UNE and abnormal interrupt summary enable bits are set, the transmit underflow interrupt is enabled. CSR7.2 TUE Transmit buffer unavailable enable When both the TUE and normal interrupt summary enable bits are set, the transmit buffer unavailable interrupt is enabled. CSR7.1 TSE Transmit stopped enable When both the TSE and abnormal interrupt summary enable bits are set, the transmit process stopped interrupt is enabled. CSR7.0 TIE Transmit interrupt enable When both the TIE and normal interrupt summary enable bits are set, the transmit interrupt is enabled. Table 25 * Missed Frames and Overflow Counter Register (CSR8) Bits 31:24 OCO Bits 23:16 FOC(6..0) FOC(10..7) MFO Bits 15:8 MFC(15..8) Bits 7:0 MFC(7..0) Note: The CSR8 register has unimplemented bits (shaded). If these bits are read they will return a predefined value. Writing these bits has no effect. Table 26 * Missed Frames and Overflow Counter Bit Functions Bit CSR8.28 Symbol OCO Function Overflow counter overflow (read only) Gets set when the FIFO overflow counter overflows Resets when read the high byte (bits 31:24). CSR8.(27..17) FOC FIFO overflow counter (read only) Counts the number of frames not accepted due to the receive FIFO overflow. The counter resets when the high byte (bits 31:24) is read. CSR8.16 MFO Missed frame overflow Set when a missed frame counter overflows The counter resets when the high byte (bits 31:24) is read. CSR8.(15..0) MFC Missed frame counter (read only) Counts the number of frames not accepted due to the unavailability of the receive descriptor. The counter resets when the high byte (bits 31:24) is read. 18 v3.1 Core10/100 Ethernet Media Access Controller Table 27 * MII Management and Serial ROM Interface Register (CSR9) Bits 31:24 Bits 23:16 MDI MII MDO MDC SDO SDI SCLK SCS Bits 15:8 Bits 7:0 Note: The CSR9 register has unimplemented bits (shaded). If these bits are read they will return a predefined value. Writing these bits has no effect. Table 28 * MII Management and Serial ROM Register Bit Functions Bit CSR9.19 Symbol MDI Function MII management data in signal (read only) This bit reflects the sample on the mdi port during the read operation on the MII management interface. CSR9.18 MII MII management operation mode 1 - indicates that Core10/100 reads the MII PHY registers 0 - indicates that Core10/100 writes to the MII PHY registers CSR9.17 MDO MII management write data The value of this bit drives the mdo port when a write operation is performed. CSR9.16 MDC MII management clock The value of this bit drives the mdc port. CSR9.3 SDO Serial ROM data output The value of this bit drives the sdo port of Core10/100. CSR9.2 SDI Serial ROM data input This bit reflects the sdi port of Core10/100. CSR9.1 SCLK Serial ROM clock The value of this bit drives the sclk port of Core10/100. CSR9.0 SCS Serial ROM chip select The value of this bit drives the scs port of Core10/100. v3.1 19 Core10/100 Ethernet Media Access Controller The MII management interface can be used to control the external PHY device from the host side. It allows access to all of the internal PHY registers via a simple two-wire interface. There are two signals on the MII management interface: the MDC (Management Data Clock) and the MDIO (Management Data Input/Output). The IEEE 802.3 indirection tristate signal defines the MDIO. Core10/100 uses four unidirectional external signals to control the management interface. For proper operation of the interface, the user must connect a tristate buffer (inside or outside the FPGA), as shown in Core10/100 Figure 5. The Serial ROM interface can be used to access an external Serial ROM device via the CSR register CSR9. The user can supply an external Serial ROM device, as shown in Figure 6. The Serial ROM can be used for storing the user data, such as Ethernet addresses. Note that all access sequences and timing of the Serial ROM interface are handled by the software. If the Serial ROM interface is not used, the sdi input port should be connected to logic 0 and the output ports (scs, sclk, and sdo) should be left unconnected. MII Man ag emen t MDC mdc mden mdo MDIO mdi Figure 5 * External Tristate Buffer Connections Core10/100 Serial ROM sdi Data Output scs Chip Select sclk Clock sdo Data Input Figure 6 * External Serial ROM Connections Table 29 * General-Purpose Timer and Interrupt Mitigation Control Register (CSR11) Bits 31:24 Bits 23:16 CS TT NTP RT NRP Bits 15:8 TIM(15..8) Bits 7:0 TIM(7..0) 20 v3.1 CON Core10/100 Ethernet Media Access Controller Table 30 * General-Purpose Timer and Interrupt Mitigation Control Bit Functions Bit CSR11.31 Symbol CS Function Cycle size Controls the time units for the transmit and receive timers according to the following: 1- MII 100 Mb mode - 5.12 s MII 10 Mb mode - 51.2 s 0- MII 100 Mb mode - 81.92 s MII 10 Mb mode - 819.2 s CSR11.(30..27) TT Transmit timer Controls the maximum time that must elapse between the end of a transmit operation and setting the CSR5.TI (Transmit Interrupt) bit This time is equal to TT * (16*CS) The transmit timer is enabled when written with a nonzero value. After each frame transmission the timer starts to count down if it has not already started. It is reloaded after every transmitted frame. Writing '0' to this field disables the timer effect on the transmit interrupt mitigation mechanism. Reading this field gives the actual count value of the timer. CSR11.(26..24) NTP Number of transmit packets Controls the maximum number of the frames transmitted before setting the CSR5.TI (Transmit Interrupt) bit The transmit counter is enabled when written with a nonzero value. It is decremented after every transmitted frame. It is reloaded after setting the CSR5.TI (Transmit Interrupt) bit. Writing '0' to this field disables the counter effect on the transmit interrupt mitigation mechanism. Reading this field gives the actual count value of the counter. CSR11.(23..20) RT Receive timer Controls the maximum time that must elapse between the end of a receive operation and setting the CSR5.RI (Receive Interrupt) bit This time is equal to RT * CS. The receive timer is enabled when written with a nonzero value. After each frame reception the timer starts to count down if it has not already started. It is reloaded after every received frame. Writing '0' to this field disables the timer effect on the receive interrupt mitigation mechanism. Reading this field gives the actual count value of the timer. CSR11.(19..17) NRP Number of receive packets Controls the maximum number of received frames before setting the CSR5.RI (Receive Interrupt) bit. The receive counter is enabled when written with a nonzero value. It is decremented after every received frame. It is reloaded after setting the CSR5.RI (Receive Interrupt) bit. Writing '0' to this field disables the timer effect on the receive interrupt mitigation mechanism. Reading this field gives the actual count value of the counter. CSR11.16 CON Continuous mode 1 - general-purpose timer works in continuous mode 0 - general-purpose timer works in one-shot mode CSR11.(15..0) TIM Timer value Contains the number of iterations of the general-purpose timer. Each iteration duration is MII 100 Mb mode - 81.92s MII 10 Mb mode - 819.2s v3.1 21 Core10/100 Ethernet Media Access Controller Data Interface The data interface is used for data transfers between Core10/100 and external shared system memory. It is a master via the DMA interface, i.e., Core10/100 operates as an initiator on this data interface. The interface operates synchronously with the clkdma clock supplied by the system. The data width of the interface can be changed using the core parameter DATAWIDTH. Possible DATAWIDTH values are: 8, 16, or 32. There are two data exchange types that can be initiated and performed by Core10/100 via the DMA interface. The first data type is the transmit and receive descriptors, which are setup by the host and are fetched by the DMA interface to instruct Core10/100 to exchange the Ethernet frame data on specified locations of shared RAM. The second is the Ethernet data type. Data Interface Signal Definitions Table 31 * Data Interface Signals Name Type Polarity/Bus Size Description datareq Out High This signal is set by Core10/100 to put a "request" for the data transfer on the interface. While datareq remains active, the datarw signal is stable, i.e., there is no transition on the datarw. datarw Out 1 The datarw output indicates the type of request on the data interface. When set, it indicates a read operation; when cleared, it indicates a write operation. dataeob Out High The dataeob output is an "end-of-burst" signal used for the burst transactions. When set, it indicates the last data transfer for a current burst; when cleared, it indicates that there will be more data transfers. dataack In High The dataack input is an acknowledge signal supplied by the host in response to the MACs request. In the case of a read operation, dataack indicates valid data is on the datai input. The datai input should be stable while the dataack is set. In case of a write operation, setting the dataack indicates that the host is ready to fetch the data supplied by Core10/100 on the datao output. Regardless of the current transaction type (write or read), a data transfer occurs on every rising edge of the clkdma on which both the datareq and the dataack are set. The dataack can be asserted or de-asserted at any clock cycle, even in the middle of a burst transfer. dataaddr Out DATADEPTH This signal addresses the external memory space for a data transaction. The meaning of the dataaddr bits depends on the DATAWIDTH parameter. For the DATAWIDTH = 32 (32-bit interface), only the dataaddr bits DATADEPTH1 down to 2 are significant. The addresses are longword (32-bit) aligned in this mode. For the DATAWIDTH = 16 (16-bit interface), the dataaddr bits DATADEPTH-1 down to 1 are significant. The addresses are word (16-bit) aligned in this mode. For the DATAWIDTH = 8 (8-bit interface), all bits of the dataaddr are significant. The addresses are byte (8-bit) aligned in this mode. datai In DATAWIDTH The read data should be provided on the datai by the system in response to a read request. datao Out DATAWIDTH Data to be written is provided by Core10/100 on datao during a write request. 22 v3.1 Core10/100 Ethernet Media Access Controller Data Interface Write Operation The data interface supports single or burst data transfer. The writes are operated on the positive edge of the clock clkdma. The write operation starts when the data interface sets datareq to high, and then the data interface waits until dataack from the host interface is set to high (which indicates the host is ready to receive the writes). A byte enable signal databe indicates the valid bytes on each write. The signal dataob indicates to the hosts it is the end of a burst transfer. dataack can be asserted or deasserted at any clock cycle, even in the middle of a burst transfer. Write Write clk datareq datar dataeob End of dataack databe dataaddr b a b a+ a+ a datai datao data[a] data[a+1] data[a+2] data[a] Figure 7 * Core10/100 Host Data Write Operation Data Interface Read Operation The data interface supports single or burst data transfer. The reads are operated on the positive edge of the clock clkdma. The read operation starts when the data interface sets datareq to high, and then the data interface waits until dataack from the host interface is set to high (that indicates the data is ready to be received by the data interface). A byte enable signal databe indicates the valid bytes on each read request. The signal dataob indicates to the hosts it is the end of a burst transfer. dataack can be asserted or deasserted at any clock cycle, even in the middle of a burst transfer. Read Read clk datareq datar End of dataeob dataack databe dataaddr datai b a b a+ data[a] a+ data[a+1] data[a+2] a data[a] datao Figure 8 * Host Data Read Operation v3.1 23 Core10/100 Ethernet Media Access Controller Frame Data and Frame Descriptors Descriptors/Data Buffers Architecture Overview A data exchange between the host and Core10/100 is performed via the descriptor lists and data buffers, which reside in the system shared RAM. The buffers hold the host data to be transmitted or received by Core10/100. The descriptors act as pointers to these buffers. Each descriptor list should be constructed by the host in a shared memory area, and can be of an arbitrary size. There is a separate list of the descriptors for both the transmit and receive processes. The position of the first descriptor in the descriptor list is described by CSR3 for the receive list and by CSR4 for the transmit list. The descriptors can be arranged in either a "chained" or "ring" structure. In a chained structure, every descriptor contains a pointer to the next descriptor in the list. In the ring structure, the address of the next descriptor is determined by the CSR0.6..2 (DSL-- Descriptor Skip Length). Every descriptor can point to up to two data buffers. When using descriptor chaining, the address of the second buffer is used as a pointer to the next descriptor, thus only one buffer is available. A frame can occupy one or more data descriptors and buffers, but one descriptor cannot exceed a single frame. In a ring structure, the descriptor operation may be corrupted if only one descriptor is used. Additionally, in the ring 24 v3.1 structure, at least two descriptors should be set up by the host. In a transmit process, the host can give the ownership of the first descriptor to Core10/100 and causes the data specified by the first descriptor to be transmitted. At the same time, the host holds the ownership of the second or last descriptor to itself to prevent Core10/100 from fetching the next frame until the host is ready to transmit the data specified in the second descriptor. In a receive process, the ownership of all available descriptors, unless it is pending to be processed by the host, should be given to Core10/100. Core10/100 can store a maximum of two frames in the Transmit Data FIFO, including the frame waiting inside the Transmit Data FIFO, the frame being transferred from the data interface into the Transmit Data FIFO, and the frame being transmitted out via the MII interface from the Transmit Data FIFO. Core10/100 can store a maximum of four frames in the Receive Data FIFO, including the frame waiting inside the Receive Data FIFO, the frame being transferred to data interface from the Receive Data FIFO, and the frame being received via the MII interface into the Receive Data FIFO. Core10/100 Ethernet Media Access Controller CSR Shared CSR3/CSR4 - Descriptor List Base OWN CSR RIN DSL - Descriptor Skip Buffer 1 Buffer 2 OWN RIN Buffer 1 Buffer 2 OWN RIN Buffer 1 Buffer 2 Data Data Data Figure 9 * Descriptors in "Ring Structure" v3.1 25 Core10/100 Ethernet Media Access Controller Shared CSR CSR3/CSR4 - Descriptor List Base OWN RIN Buffer 1 Buffer 2 OWN RIN Buffer 1 Buffer 2 OWN RIN Buffer 1 Buffer 2 Data Data Data Figure 10 * Descriptors in "Chained Structure" Table 32 * Receive Descriptors Bits 31:24 Bits 23:16 OWN CONTROL STATUS RBS2 RBS1 Bits 15:8 RBA1 Bits 7:0 RBA2 26 v3.1 Core10/100 Ethernet Media Access Controller Table 33 * STATUS (RDES0) Bit Functions Bit RDES0.31 Symbol OWN Function Ownership bit 1 - Core10/100 owns the descriptor 0 - the host owns the descriptor Core10/100 will clear this bit when it completes a current frame reception, or when the data buffers associated with a given descriptor are already full. RDES0.30 FF Filtering fail When set, indicates that a received frame did not pass the address recognition process This bit is valid only for the last descriptor of the frame (RDES0.8 set), when the CSR6.30 (receive all) bit is set, and the frame is at least 64 bytes long. RDES0.(29..16) FL Frame length Indicates the length, in bytes, of the data transferred into a host memory for a given frame This bit is valid only when the RDES0.8 (last descriptor) is set and RDES0.14 (descriptor error) is cleared. RDES0.15 ES Error summary This bit is logical or over the following bits: RDES0.1 - CRC error RDES0.6 - Collision seen RDES0.7 - Frame too long RDES0.11 - Runt frame RDES0.14 - Descriptor error This bit is valid only when the RDES0.8 (last descriptor) is set. RDES0.14 DE Descriptor error Set by Core10/100 when no receive buffer was available when trying to store the received data This bit is valid only when the RDES0.8 (last descriptor) is set. RDES0.11 RF Runt frame When set, indicates that the frame is damaged by a collision or by a premature termination before the end of a collision window This bit is valid only when the RDES0.8 (last descriptor) is set. RDES0.10 MF Multicast frame When set, indicates that the frame has a multicast address This bit is valid only when the RDES0.8 (last descriptor) is set. RDES0.9 FS First descriptor When set, indicates that this is the first descriptor of a frame RDES0.8 LS Last descriptor When set, indicates that this is the last descriptor of a frame RDES0.7 TL Frame too long When set, indicates that a current frame is longer than maximum size of 1518 bytes, as specified by 802.3 TL (frame too long) in the receive descriptor has been set when the received frame is longer than 1,518 bytes. This flag is valid in all receive descriptors when multiple descriptors are used for one frame. v3.1 27 Core10/100 Ethernet Media Access Controller Table 33 * STATUS (RDES0) Bit Functions (Continued) Bit RDES0.6 Symbol CS Function Collision seen When set, indicates that a late collision was seen (collision after 64 bytes following SFD) This bit is valid only when the RDES0.8 (last descriptor) is set. RDES0.5 FT Frame type When set, indicates that the frame has the length field greater then 1500 (Ethernet type frame). When cleared, indicates the 802.3 type frame This bit is valid only when the RDES0.8 (last descriptor) is set. Additionally, the FT is invalid for the runt frames of the length shorter then 14 bytes. RDES0.3 RE Report on MII error When set, indicates that an error has been detected by a physical layer chip connected through the MII interface This bit is valid only when the RDES0.8 (last descriptor) is set. RDES0.2 DB Dribbling bit When set, indicates that the frame was not byte aligned This bit is valid only when the RDES0.8 (last descriptor) is set. RDES0.1 CE CRC error When set, indicates that the CRC error has occurred in the received frame This bit is valid only when the RDES0.8 (last descriptor) is set. Additionally, the CE is not valid when the received frame is a runt frame. RDES0.0 ZERO This bit is reset for the frames with the legal length. Table 34 * CONTROL and COUNT (RDES1) Bit Bit RDES1.25 Symbol RER Function Receive end of ring When set, indicates that this is the last descriptor in the receive descriptor ring. Core10/100 returns to the first descriptor in the ring, as specified by the CSR3 (start of receive list address). RDES1.24 RCH Second address chained When set, indicates that the second buffer's address points to the next descriptor and not to the data buffer Note that the RER takes precedence over the RCH. RDES1.(21..11) RBS2 Buffer 2 size Indicates size, in bytes, of memory space used by the second data buffer. This number must be a multiple of four. If it is 0, then Core10/100 ignores the second data buffer and fetches the next data descriptor. This number is valid only when the RDES1.24 (second address chained) is cleared. RDES1.(10..0) RBS1 Buffer 1 size Indicates the size, in bytes, of memory space used by the first data buffer. This number must be a multiple of four. If it is 0, then Core10/100 ignores the first data buffer and uses the second data buffer. 28 v3.1 Core10/100 Ethernet Media Access Controller Table 35 * RBA1 (RDES2) Bit Functions Bit Symbol RDES2.(31..0) RBA1 Function Receive buffer 1 address Indicates the length, in bytes, of memory allocated for the first receive buffer. This number must be longword aligned (RDES2.1..0 = 00). Table 36 * RBA2 (RDES3) Bit Functions Bit Symbol RDES3.(31..0) RBA2 Function Receive buffer 2 address Indicates the length, in bytes, of memory allocated for the second receive buffer. This number must be longword aligned (RDES3.1..0 = 00). Table 37 * Transmit Descriptors Bits 31:24 Bits 23:16 OWN STATUS CONTROL TBS2 TBS1 Bits 15:8 TBA1 Bits 7:0 TBA2 Table 38 * STATUS (TDES0) Bit Functions Bit TDES0.31 Symbol OWN Function Ownership bit 1 - Core10/100 owns the descriptor 0 - the host owns the descriptor Core10/100 will clear this bit when it completes a current frame transmission or when the data buffers associated with a given descriptor are empty. TDES0.15 ES Error summary This bit is logical or over the following bits: TDES0.1 - Underflow error TDES0.8 - Excessive collision error TDES0.9 - Late collision TDES0.10 - No carrier TDES0.11 - Loss of carrier This bit is valid only when the TDES1.30 (last descriptor) is set. TDES0.11 LO Loss of carrier When set, indicates a loss of the carrier during a transmission This bit is valid only when the TDES1.30 (last descriptor) is set. TDES0.10 NC No carrier When set, indicates that the carrier was not asserted by an external transceiver during the transmission This bit is valid only when the TDES1.30 (last descriptor) is set. TDES0.9 LC Late collision When set, indicates that a collision was detected after transmitting 64 bytes This bit is not valid when the TDES0.1 (underflow error) is set. This bit is valid only when the TDES1.30 (last descriptor) is set. v3.1 29 Core10/100 Ethernet Media Access Controller Table 38 * STATUS (TDES0) Bit Functions (Continued) Bit TDES0.8 Symbol EC Function Excessive collisions When set, indicates that the transmission was aborted after 16 retries This bit is valid only when the TDES1.30 (last descriptor) is set. TDES0.(6..3) CC Collision count This field indicates the number of collisions that occurred before the end of a frame transmission. This value is not valid when the TDES0.8 (excessive collisions bit) is set. This bit is valid only when the TDES1.30 (last descriptor) is set. TDES0.1 UF Underflow error When set, indicates that the FIFO was empty during the frame transmission This bit is valid only when the TDES1.30 (last descriptor) is set. TDES0.0 DE Deferred When set, indicates that the frame was deferred before transmission. Deferring occurs if the carrier is detected when the transmission is ready to start. This bit is valid only when the TDES1.30 (last descriptor) is set. Table 39 * CONTROL (TDES1) Bit Functions Bit TDES1.31 Symbol IC Function Interrupt on completion Setting this flag instructs Core10/100 to set the CSR5.0 (transmit interrupt) immediately after processing a current frame. This bit is valid when the TDES1.30 (last descriptor) is set or for a setup packet. TDES1.30 LS Last descriptor When set, indicates the last descriptor of the frame TDES1.29 FS First descriptor When set, indicates the first descriptor of the frame TDES1.28 FT1 Filtering type This bit, together with the TDES0.22 (FT0), controls a current filtering mode. This bit is valid only for the setup frames. TDES1.27 SET Setup packet When set, indicates that this is a setup frame descriptor TDES1.26 AC Add CRC disable When set, Core10/100 does not append the CRC value at the end of the frame. The exception is when the frame is shorter then 64 bytes and automatic byte padding is enabled. In that case the CRC field is added despite the state of the AC flag. TDES1.25 TER Transmit end of ring When set, indicates the last descriptor in the descriptors ring TDES1.24 TCH Second address chained When set, indicates that the second descriptor's address points to the next descriptor and not to the data buffer This bit is valid only when the TDES1.25 (transmit end of ring) is reset. 30 v3.1 Core10/100 Ethernet Media Access Controller Table 39 * CONTROL (TDES1) Bit Functions (Continued) Bit Symbol TDES1.23 DPD Function Disabled padding When set, the automatic byte padding is disabled. Core10/100 normally appends the PAD field after the INFO field when the size of an actual frame is less than 64 bytes. After padding bytes, the CRC field is also inserted despite the state of the AC flag. When the DPD is set, no padding bytes are appended. TDES1.22 FT0 Filtering type This bit, together with the TDES0.28 (FT1), controls the current filtering mode. This bit is valid only when the TDES1.27 (SET) bit is set. TDES1.(21..11) TBS2 Buffer 2 size Indicates the size, in bytes, of memory space used by the second data buffer. If it is zero, Core10/ 100 ignores the second data buffer and fetches the next data descriptor. This bit is valid only when the TDES1.24 (second address chained) is cleared. TDES1.(10..0) TBS1 Buffer 1 size Indicates the size, in bytes, of memory space used by the first data buffer. If it is 0, Core10/100 ignores the first data buffer and uses the second data buffer. Table 40 * TBA1 (TDES2) Bit Functions Bit Symbol TDES2.(31..0) TBA1 Function Transmit buffer 1 address Contains the address of the first data buffer. For the setup frame this address must be longword aligned (TDES3.1..0 = 00). In all other cases there are no restrictions on buffer alignment. Table 41 * TBA2 (TDES3) Bit Functions Bit Symbol TDES3(31..0) TBA2 Function Transmit buffer 2 address Contains the address of the second data buffer. There are no restrictions on buffer alignment. v3.1 31 Core10/100 Ethernet Media Access Controller MAC Address and Setup Frames The setup frames define addresses that are used for the receive address filtering process. These frames are never transmitted on the Ethernet connection. They are used to fill the address-filtering RAM. A valid setup frame must be exactly 192 bytes long, and must be allocated in a single buffer that is longword aligned. The TDESI.27 (set up frame indicator) must be set. Both the TDES1.29 (first descriptor) and the TDES1.30 (last descriptor) must be cleared for the setup frame. The FT1 and FT0 bits of the setup frame define the current filtering mode. Table 42 lists all possible combinations. Table 43 shows the setup frame buffer format for perfect filtering modes and Table 44 on page 33 for imperfect filtering modes. The setup should be sent to Core10/100 when Core 10/100 is in stop mode. When a RAM with more than 192 bytes is used for the address filtering RAM, a setup frame with more than 192 bytes can be written into this memory to initialize its contents, but only the first 192 bytes constitute the address filtering operation. Table 42 * Filtering Type Selection FT1 0 FT0 0 Description Perfect filtering mode Setup frame buffer is interpreted as a set of 16 48-bit physical addresses. 0 1 Hash filtering mode Setup frame buffer contains 512-bit hash table plus a single 48-bit physical address. 1 0 Inverse filtering mode Setup frame buffer is interpreted as a set of 16 48-bit physical addresses. 1 1 Hash only filtering mode Setup frame buffer is interpreted as a 512-bit hash table. Table 43 * Perfect Filtering Setup Frame Buffer Byte Number Data Bits 31:16 Data Bits 15:0 3:0 xxxxxxxxxxxxxxxx Physical Address 0 (15:00) 7:4 xxxxxxxxxxxxxxxx Physical Address 0 (31:16) 11:8 xxxxxxxxxxxxxxxx Physical Address 0 (47:32) 15:12 xxxxxxxxxxxxxxxx Physical Address 1 (15:00) 19:16 xxxxxxxxxxxxxxxx Physical Address 1 (31:16) 23:20 xxxxxxxxxxxxxxxx Physical Address 1 (47:32) * * * * * * * * * 171:168 xxxxxxxxxxxxxxxx Physical Address 14 (15:00) 175:172 xxxxxxxxxxxxxxxx Physical Address 14 (31:16) 179:176 xxxxxxxxxxxxxxxx Physical Address 14 (47:32) 183:180 xxxxxxxxxxxxxxxx Physical Address 15 (15:00) 187:184 xxxxxxxxxxxxxxxx Physical Address 15 (31:16) 191:188 xxxxxxxxxxxxxxxx Physical Address 15 (47:32) 32 v3.1 Core10/100 Ethernet Media Access Controller Table 44 * Hash Table Setup Frame Buffer Format Byte Number Data Bits 31:16 Data Bits 15:0 3:0 xxxxxxxxxxxxxxxx Hash filter (015:000) 7:4 xxxxxxxxxxxxxxxx Hash filter (031:016) 11:8 xxxxxxxxxxxxxxxx Hash filter (047:032) 123:121 xxxxxxxxxxxxxxxx Hash filter (495:480) 127:124 xxxxxxxxxxxxxxxx Hash filter (511:496) * * * 131:128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 135:132 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx * * * 159:156 xxxxxxxxxxxxxxxx Physical Address (15:00) 163:160 xxxxxxxxxxxxxxxx Physical Address (31:16) 167:164 xxxxxxxxxxxxxxxx Physical Address (47:32) 171:168 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 175:172 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx * * * 183:180 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 187:184 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 191:188 xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx v3.1 33 Core10/100 Ethernet Media Access Controller Transmit Data / Receive Data / Address RAM Interface Read/Write of the External RAM Interface For proper operation of the core, the system designer should supply synchronous RAM memories. The writes to the external RAM operate on the positive clock edge of the write clock wclk. The reads from the external RAM operate on the positive clock edge of the read clock rclk. The read data is available one read clock cycle after the read address is read into the RAM. Core10/100 provides three external RAM interfaces: the first for the transmit data, the second for the receive data, and the third for the receive-address filtering block. Write Points wclk we datai data data data waddr addr addr addr Read Points rclk data[a1] datao raddr a1 a2 data[a2] data[a3] a3 Figure 11 * Dual Port RAM Write and Read Operations External RAM Interface Signals Table 45 * External RAM Interface Signals RAM Pin Name Pin Function Transmit Data RAM Receive Data RAM Address RAM write clock clkdma clkr clkdma write enable twe rwe fwe rdata read data trdata rrdata frdata waddr write address twaddr rwaddr fwaddr read clock clkt clkdma clkr raddr read address traddr rraddr fraddr wdata write data twdata rwdata fwdata wclk we rclk External Address RAM Interface Parameters Table 46 * External RAM Interface Parameters Parameter Receive Data RAM Transmit Data RAM Address RAM DATAWIDTH DATAWIDTH 16 Min. 6 6 6 Typ. 9 (2kB/32bit) 9 (2kB/32bit) 6 Max 16 16 6 data bus width address bus width 34 v3.1 Core10/100 Ethernet Media Access Controller The address bus width of the Receive/Transmit Data RAMs can be customized via the core parameters RFIFODEPTH/TFIFODEPTH (Table 1 on page 5). Those memories should be at least as big as the longest frame used on a given network. Core10/100 stops to request new frame data when there are two frames already in the Transmit Data RAM. It resumes the request for new frame data when there is either one or no frame in the Transmit Data RAM. At any given time, the Receive Data RAM can hold no more than four frames, including frames under transfers. and for the DATAWIDTH = 8, the descriptors are accessed with a burst of four eight-bit words. In case of data buffers, the burst length is defined by the CSR0(13..8) (programmable burst length) and can be set to 0, 1, 2, 4, 8, 16, or 32. When set to 0, no maximum burst size is defined, and the transfer ends when the transmit FIFOs are full or the receive FIFOs are empty. Transmit Process The transmit process can operate in one of three modes: running, stopped, or suspended. After a software or hardware reset, or after a stop transmit command, the transmit process is in a stopped state. The transmit process can leave a stopped state only after the start transmit command. When in a running state, the transmit process performs descriptor/buffer processing. When operating in a suspended or stopped state, the transmit process retains the position of the next descriptor, i.e., the address of the descriptor following the last descriptor being closed. After entering a running state, that position is used for the next descriptor fetch. The only exception is when the host writes the transmit descriptor base address register (CSR4). In that case, the descriptor address is reset and the fetch is directed to the first position in the list. When operating in a stopped state, the transmit process stopped (tps) output is high. This output may be used to optionally disable the clkt clock signal external to Core10/100. When both the tps and receive process stopped (rps) outputs are high, all clock signals except clkcsr may be optionally disabled external to Core10/100. The transmit process remains running until one of the following events occurs: * The hardware or software reset is issued. Setting the CSR0.0 (SWR) bit can perform the software reset. After the reset, all the internal registers return to their default states. The current descriptor's position in the transmit descriptors list is lost. * A stop transmit command is issued by the host. This can be performed by writing 0 to the CSR6.13 (ST) bit. The current descriptor's position is retained. * The descriptor owned by the host is found. A current descriptor's position is retained. * The transmit FIFO underflow error is detected. An underflow error is generated when the transmit FIFO is empty during the transmission of the frame. When it occurs, the transmit process enters a suspended state. Transmit automatic polling is internally disabled, even if it is enabled by the host by writing the TAP bits. A current descriptor's position is retained. DMA Controller The Direct Memory Access (DMA) is used to control a data flow between the host and Core10/100. The DMA services the following types of requests from the Core10/100's transmit and receive processes: * Transmit request: - Descriptor fetch - Descriptor closing - Setup packet processing - Data transfer from host buffer to transmit the FIFO * Receive request: - Descriptor fetch - Descriptor closing - Data transfer from receive the FIFO to the host buffer The key task for the DMA is to perform an arbitration between the receive and transmit processes. Two arbitration schemes are possible according to the CSR0.1 bit: * 1 - Round-robin arbitration scheme in which receive and transmit processes have equal priorities. * 0 - The receive process has priority over the transmit process unless transmission is in progress. In this case, the following rules apply: - The transmit process request should be serviced by the DMA between two consecutive receive transfers. - The receive process request should be serviced by the DMA between two consecutive transmit transfers. Transfers between the host and Core10/100 performed by the DMA component are either single data transfers or "burst" transfers. For the data descriptors the data transfer size depends on the core parameter DATAWIDTH. The rule is that every descriptor field (32bit) is accessed with a single burst. For the DATAWIDTH = 32, the descriptors are accessed with a single transaction; for the DATAWIDTH = 16, the descriptors are accessed with a burst of two 16-bit words, v3.1 35 Core10/100 Ethernet Media Access Controller Leaving a suspended state is possible in one of the following situations: * * A transmit poll demand command is issued. This can be performed by writing the CSR1 with a nonzero value. The transmit poll demand command can also be generated automatically when transmit automatic polling is enabled. Transmit automatic polling is enabled only if the CSR0(19..17) (TAP) bits are written with a nonzero value, and when there was no underflow error prior to entering the suspended state. A stop transmit command is issued by the host. This can be performed by writing 0 to the CSR6.13 (ST) bit. The current descriptor's position is retained. Start Transmit Command A typical data flow for the transmit process is illustrated in Figure 13. The events for the transmit process typically happen in the following order: * The host sets up CSR registers for the operational mode, interrupts, etc. * The host sets up transmit descriptors/data in the shared RAM * The host sends the transmit start command * Core10/100 starts to fetch the transmit descriptors * Core10/100 transfers the transmit data to Transmit Data RAM from the shared RAM * Core10/100 starts to transmit data on MII Transmit Stopped Stop Transmit Command Stop Transmit Command Reset Command Transmit Running Reset Command Pull Demand Command Transmit Suspended Descriptor Unavailable Underflow Error Figure 12 * Transmit Process Transitions Host-SharedRAM CSR_Interface Data_Interface-SharedRAM Data_Interface-TxFIFO_RAM Transmit_Controller-MII TxFIFO_RAM-Transmit_Controller Des+Data CSRs CSR6 Tx Des Tx Data Tx Data Preamble Note: Refer to the Core10/100 User's Guide for an example of transmit data timing. Figure 13 * Transmit Data Flow 36 v3.1 Tx Data Tx Data CRC Core10/100 Ethernet Media Access Controller Receive Process The receive process can operate in one of three modes: running, stopped, or suspended. After a software or hardware reset, or after a stop receive command, the receive process is in the stopped state. The receive process can leave a stopped state only after a start receive command. switching the receive clock clkr off externally. When both rps and tps outputs are high, all clocks except clkcsr can be externally switched off. The receive process runs until one of the following events occurs: In the running state, the receiver performs descriptor/ buffer processing. In the running state, the receiver fetches from the receive descriptor list. It performs this fetch regardless of whether there is any frame on the link. When there is no frame pending, the receive process reads the descriptor and simply waits for the frames. When a valid frame is recognized, the receive process starts to fill the memory buffers pointed to by the current descriptor. When the frame ends, or when the memory buffers are completely filled, the current frame descriptor is closed (ownership bit cleared). Immediately, the next descriptor on the list is fetched in the same manner, and so on. * A hardware or software reset is issued by the host. A software reset can be performed by setting the CSR0.0 (SWR) bit. After reset, all the internal registers return to their default states. The current descriptor's position in the receive descriptors list is lost. * A stop receive command is issued by the host. This can be performed by writing 0 to the CSR6.1 (SR) bit. The current descriptor's position is retained. * The descriptor owned by the host is found by Core10/100 during the descriptor fetch. The current descriptor's position is retained. Leaving a suspended state is possible in one of the following situations: When operating in a suspended or stopped state, the receive process retains the position of the next descriptor (the address of the descriptor following the last descriptor that was closed). After entering a running state, the retained position is used for the next descriptor fetch. The only exception is when the host writes the receive descriptor base address register (CSR3). In that case, the descriptor address is reset and the fetch is pointed to the first position in the list. * A receive poll command is issued by the host. This can be performed by writing CSR2 with a nonzero value. * A new frame is detected by Core10/100 on a receive link. * A stop receive command is issued by the host. This can be performed by writing 0 to the CSR6.1 (SR) bit. The current descriptor's position is retained. When operating in a stopped state, the receive process stopped (rps) output is high. This output allows for Start Receive Command Receive Stopped Stop Receive Command Reset Command Stop Receive Command Frame Recognized Pull Demand Command Receive Running Reset Command Receive Suspended Descriptor Unavailable Note: Refer to the Core10/100 User's Guide for an example of receive timing. Figure 14 * Receive Process Transitions v3.1 37 Core10/100 Ethernet Media Access Controller A typical data flow in a receive process is illustrated in Figure 15. The events for the receive process typically happen in the following order: 1. The host sets up CSR registers for the operational mode, interrupts, etc. 2. The host sets up receive descriptors in the shared RAM. Host-SharedRAM CSR_Interface Data_Interface-SharedRAM Data_Interface-RxFIFO_RAM RxFIFO_RAM-Receive_Controller Receive_Controller-MII 3. The host sends the receive start command. 4. Core10/100 starts to fetch the transmit descriptors. 5. Core10/100 waits for receive data on MII. 6. Core10/100 transfers received data to the Receive Data RAM. 7. Core10/100 transfers Rx data to shared RAM from Receive data RAM. Rx Des CSRs CSR6 Rx Des Rx Data Rx Data Preamble Rx Data Rx Data CRC CRC Figure 15 * Receive Dataflow Interrupt Controller The interrupt controller uses three internal Control and Status Registers: CSR5, CSR7, and CSR11. The CSR5 contains the Core10/100's status information. It has 10 bits that can trigger an interrupt. These bits are collected in two groups: normal interrupts and abnormal interrupts. Each group has its own summary bit, the NIS and AIS, respectively. The NIS and AIS bits directly control the int output port of Core10/100. Every status bit in the CSR5 that can source an interrupt can be individually masked by writing an appropriate value into the CSR7 - Interrupt Enable Register. Additionally, an interrupt mitigation mechanism is provided for reducing the CPU usage in servicing interrupts. The interrupt mitigation is controlled via the CSR11. There are separate interrupt mitigation control blocks for the transmit and receive interrupts. Both of these blocks consist of a four-bit frame counter and a four-bit timer. The operation of these blocks is similar for 38 v3.1 the receive and transmit processes. After the end of a successful receive or transmission operation, an appropriate counter is decremented and the timer starts to count down, if it has not already started. An interrupt is triggered when either the counter or timer reaches a zero value. This allows Core10/100 to generate a single interrupt for a few received/transmitted frames, or after a specified time since the last successful receive/transmit operation. It is possible to omit the transmit interrupt mitigation for one particular frame by setting the Interrupt on Completion (IC) bit in the last descriptor of the frame. If the IC bit is set, Core10/100 sets the transmit interrupt immediately after the frame has been transmitted. The int port remains low for a single clock cycle on every write to CSR5. This enables the use of both level and edge triggered external interrupt controllers. Core10/100 Ethernet Media Access Controller CSR11 Mitigation Control TT=0 CSR5 Status CSR7 Interrupt Enable TIE TI NTP=0 RT=0 RIE RI NRP=0 TUE TU ERE ERI GTE GTE NIS NIE Int AIE AIS TSE TPS RSE RPS UNE UNF RUE TU ETE ETI Figure 16 * Interrupt Scheme v3.1 39 Core10/100 Ethernet Media Access Controller General Purpose Timer Core10/100 includes a 16-bit general-purpose timer to simplify time interval calculation by an external host. The timer operates synchronously with the transmit clock clkt generated by the PHY device. This gives the host the possibility of measuring the time intervals based on actual Ethernet bit time. CSR11(15..0), the data is stored in the internal reload register. The timer is immediately reloaded and starts to count down. The timer can operate in "one shot" mode or continuous mode. In "one shot" mode, the timer stops after reaching a zero value; in continuous mode, it is automatically reloaded and continues counting down after reaching a zero value. MII Interface The actual count value can be tested with an accuracy of 1 bit by reading the CSR11(15..0). When writing the Data Link Layer Operation Core10/100 uses a standard MII interface as defined in the 802.3 standard. This interface can be used for connecting Core10/100 to an external Ethernet 10/100 PHY device. MII Interface Signals Table 47 * External PHY Interface Signals IEEE 802.3 Signal Name RX_CLK Core10/100 Signal Name clkr Description Clock for receive operation This should be a 25 MHz clock for a 100 Mb/s operation or a 2.5 MHz clock for a 10 Mbit/s operation. RX_DV rxdv Receive data valid signal The PHY device should assert the rxdv when a valid data nibble is provided on the rxd signal. The rxdv must be synchronous to the clkr receive clock. RX_ER rxer Receive error Core10/100 ends a reception when this bit is asserted during a receive operation. The rxer must be synchronous to the clkr receive clock. RXD rxd Receive data recovered and decoded by PHY The rxd(0) is the least significant bit. The rxd must be synchronous to the clkr receive clock. TX_CLK clkt Clock for transmit operation This should be a 25 MHz clock for a 100 Mb/s operation or 2.5 MHz clock for a 10 Mbit/s operation. TX_EN txen Transmit enable When asserted, indicates a valid data for the PHY on the txd The txen is synchronous to the clkt transmit clock. TXD txd Transmit data The txd(0) is the least significant bit. The txd is synchronous to the clkt transmit clock. COL col Collision detected This signal should be asserted by the PHY when a collision is detected on the medium. It is valid only when operating in a half duplex mode. When operating in a full duplex mode, this signal is ignored by Core10/100. The col is not required to be synchronous to either the clkr or clkt. The col is sampled internally by the clkt clock. 40 v3.1 Core10/100 Ethernet Media Access Controller Table 47 * External PHY Interface Signals (Continued) IEEE 802.3 Signal Name Core10/100 Signal Name CRS crs Description Carrier sense This signal should be asserted by the PHY when either a receive or transmit medium is non-idle. The CSR is not required to be synchronous to either the clkr or clkt. TX_ER txer Transmit error The current version of Core10/100 has the txer signal statically tied to logic 0 (no transmit errors). MDC mdc MII management clock This signal is driven by the CSR9.16-bit. MDIO mdi MII management data input The state of this signal can be checked by reading the CSR9.19-bit. mdo MII management data output This signal is driven by the CSR9.18-bit. MII Receive Operation Read Points Error detected clkr rxdv rxer rxd[3..0] data data data data Figure 17 * MII Receive Operation MII Transmit Operation Write Points Collis ion Detected clkt txen col txd[3..0] data data data data crs Deferring Figure 18 * MII Transmit Operation v3.1 41 Core10/100 Ethernet Media Access Controller Frame Format Core10/100 supports the Ethernet frame format shown in Figure 19 (B indicates bytes). The standard Ethernet frames (DIX Ethernet), as well as the IEEE 802.3 frames, are accepted. Core10/100 processes the individual frame fields according to Table 46 on page 34. 46B - 1500B 7B 1B 6B 6B PREAMBLE SFD DA SA 2B 4B LENGTH / TYPE DATA PAD FCS Figure 19 * Frame Format Table 48 * Frame Field Usage Field PREAMBLE Width (Bytes) 7 Transmit Operation Generated by Core10/100 Receive Operation Stripped from received data Not required for proper operation SFD 1 Generated by Core10/100 Stripped from received data DA 6 Supplied by host Checked by Core10/100 according to current address filtering mode and passed to host SA 6 Supplied by host Passed to host LENGTH/ TYPE 6 Supplied by host Passed to host DATA 0-1500 Supplied by host Passed to host PAD 0-46 FCS 4 Generated by Core10/100 when CSR.23 Passed to host (DPD) bit is cleared and data supplied by host is less than 64 bytes Generated by Core10/100 when CSR.26 bit is Checked by Core10/100 and passed to host cleared Collision Handling Collision detection is performed via the col input port. If a collision is detected before the end of the PREAMBLE/ SFD, then Core10/100 completes the PREAMBLE/SFD, transmits the JAM sequence, and initiates a backoff computation. If a collision is detected after the transmission of the PREAMBLE and SFD, but prior to 512 bits being transmitted, Core10/100 immediately aborts the transmission, transmits the JAM sequence, and then initiates a backoff. If a collision is detected after 512 bits have been transmitted, the collision is termed a late collision. Core10/100 aborts the transmission and appends the JAM sequence. The transmit message is flushed from 42 v3.1 the FIFO. Core10/100 does not initiate a backoff and does not attempt to retransmit the frame when a late collision is detected. Core10/100 uses a "truncated binary exponential backoff" algorithm for backoff computing, as defined in the IEEE 802.3 standard, and outlined in Figure 20 on page 43. Backoff processing is performed only in half-duplex mode. In full-duplex mode, collision detection is disabled. Core10/100 Ethernet Media Access Controller Reset Attempt No Transmission Ready Yes Wait for End of Transmission Normal Collision? No Yes Late Collision? Set TDES0.9 (LC) Late Collision No Yes Increment Attempt No Attempt < 16 set TDES0.8 (EC) Excessive Collision Yes Yes No Attempt < 10 ran = Random(0..2 10 -1) ran = Random(0..2 attempt -1) Wait for ran*Slot Time Next Transmission Attempt Figure 20 * Backoff Process Algorithms v3.1 43 Core10/100 Ethernet Media Access Controller Deferring The deference algorithm is implemented per the 802.3 specification and outlined in Figure 21. The InterFrame Gap (IFG) timer starts to count whenever the link is not idle. If the activity on the link is detected during the first 60-bit times of the IFG timer, the timer is reset and restarted once activity has stopped. During the final 36 bit times of the IFG timer, the link activity is ignored. Carrier sensing is performed only when operating in half-duplex mode. In full-duplex mode, the state of the crs input is ignored. Res et IFG Timer No crs=0 ? Yes No IFG Timer = 60 Bit Times ? Yes No IFG Timer = 96 Bit Times ? Yes No Transmit Ready and Not in Backoff? Yes crs=0? Transmit Frame No Figure 21 * Deference Process Algorithm 44 v3.1 Yes Core10/100 Ethernet Media Access Controller Receive Address Filtering There are three kinds of addresses on the LAN: the unicast addresses, the multicast addresses, and the broadcast addresses. If the first bit of the address (IG bit) is 0, the frame is unicast, i.e., dedicated to a single station. If the first bit is 1, the frame is multicast, i.e., destined for a group of stations. If the address field contains all 1s, the frame is broadcast and is received by all the stations on the LAN. When Core10/100 operates in the imperfect filtering mode, the frames with the unicast addresses are checked against a single physical address. The multicast frames are checked using the 512-bit hash table. Core10/100 applies the standard Ethernet CRC function to the first six bytes of the frame that contains a destination address. The least significant nine bits of the CRC value are used to index the table. If the indexed bit is set, the frame is accepted. If this bit is cleared, the frame is rejected. The algorithm is shown in Figure 22. When Core10/100 operates in perfect filtering mode, all frames are checked against the addresses in the address filtering RAM. The unicast, multicast, and broadcast frames are treated in the same manner. 802.3 Frame Destination Address 47 0 IG CRC Generator 47 9 8 0 DA Multicast Address? Yes 512-Bit Hash Table Hash Table Index No One Physical Address Figure 22 * Filtering with One Physical Address and the Hash Table It is important that one bit in the hash table corresponds to many Ethernet addresses. Therefore, it is possible that some frames may be accepted by Core10/100, even if they are not intended to be received. This is because some frames that should not have been received have addresses that hash to the same bit in the table as one of the proper addresses. The software should perform additional address filtering to reject all such frames. v3.1 45 Core10/100 Ethernet Media Access Controller External Address Filtering Interface An external address filtering interface is provided to extend the internal filtering capabilities of Core10/100. The interface allows connection of an external user-supplied address checking logic. All signals from the interface are synchronous to the clkr clock. If the external address filtering is not used, all input ports of the interface should be grounded and all output ports should be left floating. Table 49 * External Address Interface Description Core10/100 Signal Name match Type In Description External address match When high, indicates that the destination address on the matchdata port is recognized by the external address checking logic and the current frame should be received by Core10/100. When low, indicates that the destination address on the matchdata port is not recognized and the current frame should be discarded. Note that the match signal should be valid only when the matchval signal is high. matchval In External address match valid When high, indicates that the match signal is valid matchen Out External match enable When high, indicates that the matchdata signal is valid. The matchen output should be used as an enable signal for the external address checking logic. It is high for at least four clkr clock periods to allow for latency of an external address checking logic. matchdata Out External address match data The matchdata signal represents 48-bit destination address of the received frame. Note that the matchdata signal is valid only when matchen signal is high. 46 v3.1 Core10/100 Ethernet Media Access Controller Clock and Reset Control * The RC operates synchronously with the clkr clock supplied by the MII PHY device. This is a 2.5 MHz clock for 10 Mb operation or a 25 MHz for 100 Mb operation. * The TFIFO, RFIFO, TLSM, RLSM, and DMA components operate synchronously with the clkdma global clock supplied by the system. * The CSR operates synchronously with clkcsr clock supplied by the system. Clock Controls As shown in Figure 23, there are four clock domains in the design: * The TC, and BD components operate synchronously with the clkt clock supplied by the MII PHY device. This is a 2.5 MHz clock for 10 Mb operation or a 25 MHz for 100 Mb operation. clkdma clkcsr TFIFO RFIFO TLSM RLSM DMA TC BD clkt RC clkr CSR RSTC Figure 23 * Clock Domains and Reset Reset Control All clock signals are independent and can be asynchronous one to another. If needed, the clkcsr and clkdma clock domains can be connected together with the same system clock signal in the user's system to consolidate global clock resources, or they can be from independent clock sources. Hardware Reset The Core10/100 core contains a single input rstcsr signal. This signal is sampled in the RSTC component by clock clkcsr. The RSTC component generates an internal asynchronous reset for every clock domain in Core10/100. The internal reset is generated by the input rstcsr and software reset. The internal reset remains active until the circuitry of all clock domains are reset. A minimum frequency of clock clkcsr is required for proper operation of the transmit, the receive, and the general-purpose timers. The minimum frequency for the clkcsr must be at least the clkt frequency divided by 64. For a proper operation of the receive timer, the clkcsr frequency should be at least the clkr frequency divided by 64. If the clock frequency conditions described above are not met, do not use the transmit interrupt mitigation control, the receive interrupt mitigation control, or the general purpose timer. Appropriate clocks should be also supplied when the hardware reset operation is performed. The external reset signal must be active (high level) for at least one period of clock clkcsr in the user's design. The minimum recovery time for a software reset is two clkcsr periods plus one maximum clock period among clkdma, clkt, and clkr. Software Reset Software reset can be performed by setting the CSR0(0) (SWR) bit. The software reset will reset all internal flipflops. v3.1 47 Core10/100 Ethernet Media Access Controller Ordering Information Order Core10/100 through your local Actel sales representative. Use the following number convention when ordering: Core10/100-XX, where XX is listed in Table 50. Table 50 * Ordering Information XX Description EV Evaluation Version SN Netlist for single-use on Actel devices AN Netlist for unlimited use on Actel devices SR RTL for single-use on Actel devices AR RTL for unlimited use on Actel devices UR RTL for unlimited use and not restricted to Actel devices List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v 3 .1 ) v3.0 v2.0 Page Table 2 was updated. 5 The "CSR Read/Write Operation" section was updated. 9 Table 42 was updated. 32 The "Supported Families" section was updated to include ProASIC3/E. 1 The "Descriptors/Data Buffers Architecture Overview" section was updated. 24 Table 33 * STATUS (RDES0) Bit Functions was updated. 27 The "MAC Address and Setup Frames" section was updated. 32 Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. 48 v3.1 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation Actel Europe Ltd. Actel Japan www.jp.actel.com Actel Hong Kong www.actel.com.cn 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) 1276 401 450 Fax +44 (0) 1276 401 490 EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 51700023-3/5.05