1
®HI5762
Dual 10-Bit, 60MSPS A/D Converter with
Internal Voltage Reference
The HI5762 is a monolithic, dual 10-bit, 60 MSPS
analog-to-digital converter fabricated in an advanced CMOS
process. It is designed for high speed applications where
integrat io n , ba ndwid th an d ac curacy are essenti a l . Bui l t by
combining two cores of the HI5767 single channel 10-bit
60MSPS analog-to-digital converter, the HI5762 reaches a
new level of multi-channel integrati on. The fully pipeline
architecture and an innovative input stage enable the
HI5762 to accept a variety of input configurations, single-
ended or fully differential. Only one external clock is
necessary to drive both converters and an internal band-gap
voltage reference is provided. This allows the system
designer to realize an increased level of system integration
resulting in decreased cost and power dissipation.
The HI5762 has excellent dyna mic performance while
consuming only 650mW of power at 60MSPS. The A/D only
requires a single +5V power supply and encode clock. Data
output latches are provided which present valid data to the
output bus with a latency of 6 clock cycles.
For those customers needing dual channel 8-bit resolution,
please refer to the HI5662. For single channel 10-bit
applications, please refer to the HI5767.
Features
Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .60MSPS
8.8 Bits at fIN = 10MHz
Low Power at 60MSPS . . . . . . . . . . . . . . . . . . . . 650mW
Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz
Excellent Channel-to-Channel Isolation. . . . . . . . . .>75dB
On-Chip Sample and Hold Amplifiers
Internal Band-Gap Voltage Reference. . . . . . . . . . . . 2.5V
Fully Differential or Single-Ended Analog Inputs
Single Supply Voltage Operation . . . . . . . . . . . . . . . . .+ 5V
TTL/CMOS Compatible Sampling Clock Input
CMOS Compatible Digital Outputs. . . . . . . . . . . 3.0V/5.0V
Offset Binary Digital Data Output Format
Dual 10-Bit A/D Converters on a Monolithic Chi p
Applications
Wireless Local Loop
PSK and QAM I&Q Demodulators
Medical Imag ing
High Speed Data Acquisition
Ordering Information
PART
NUMBER PART
MARKING
TEMP.
RANGE
(°C) PACKAGE PKG.
DWG. #
HI5762/6IN HI5762/6IN -40 to +85 44 Ld MQFP Q44.10x10
HI5762/6INZ
(Notes 1, 2) HI5762 /6INZ -40 to +85 44 Ld MQFP
(Pb-free) Q44.10x10
HI5762EVAL2 25 Evaluation Platform
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device
information page for HI5762. F or more information on MSL
please see techbrief TB363.
Data Sheet January 22, 2010 FN4318.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN4318.3
January 22, 2010
Pinout HI5762
(44 LD MQFP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
28
27
26
25
24
23
2221201918
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
AGND
AVCC2
ID8
ID7
ID6
ID5
DVCC3
DGND
ID4
ID3
ID9
AGND
AVCC2
QD8
QD7
QD6
QD5
DVCC3
DGND
QD4
QD3
QD9
ID2
ID1
ID0
DGND
DVCC1
CLK
DVCC2
DGND
QD0
QD1
QD2
IVDC
IIN-
IIN+
AGND
VRIN
NC
VROUT
AVCC1
QIN+
QIN-
QVDC
HI5762
3FN4318.3
January 22, 2010
Functional Block Diagram
DVCC3
+
-
STAGE 1
STAGE 8
CLOCK
BIAS I/QVDC
I/QIN-
I/QIN+
I/QD0 (LSB)
I/QD1
I/QD2
I/QD3
I/QD4
I/QD5
I/QD6
I/QD7
I/QD8
I/QD9 (MSB)
CLK
AVCC1,2 AGND DVCC1,2 DGND
STAGE 9
X2
S/H
2-BIT
FLASH
2-BIT
DAC
+
-
X2
2-BIT
FLASH
2-BIT
DAC
2-BIT
FLASH
DIGITAL DELAY
AND
DIGITAL ERROR
CORRECTION
REFERENCE
VREFOUT
VREFIN
I or Q CHANNEL
HI5762
4FN4318.3
January 22, 2010
Typical Application Schematic
ARE PLACED AS CLOSE
10µF AND 0.1µF CAPS
QD9
QD8
QD7
QD6
QD5
QD4
QD3
QD2
QD1
QD0
BNC
CLOCK
10µF0.1µF10µF
++
DGND
AGND
(38) VROUT
(40) VRIN
CLK (17)
DGND (9,15,19,25)
(1,33,41) AGND
(LSB) QD0 (20)
QD1 (21)
QD2 (22)
QD3 (23)
QD4 (24)
QD5 (27)
QD6 (28)
QD7 (29)
QD8 (30)
(MSB) QD9 (31)
(2,32) AVCC2
(37) AVCC1
DVCC1 (16)
TO PART AS POSSIBLE
0.1µF
+5V
+5V
0.1µF
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
(LSB) ID0 (14)
ID1 (13)
ID2 (12)
ID3 (11)
ID4 (10)
ID5 (7)
ID6 (6)
ID7 (5)
ID8 (4)
(MSB) ID9 (3)
IIN+
IIN-(43) IIN-
(42) IIN+
(44) IVDC
0.1µF10µF
+
DVCC3 (8,26) +5V or +3V
DVCC2 (18)
(39) NC
QIN+
QIN-(35) QIN-
(36) QIN+
(34) QVDC
HI5762
HI5762
5FN4318.3
January 22, 2010
Pin Descriptions
PIN NO. NAME DESCRIPTION
1A
GND Analog Ground
2AV
CC2 Analog Supply (+5.0V)
3 ID9 I-Channel, Data Bit 9 Output (MSB)
4 ID8 I-Channel, Data Bit 8 Output
5 ID7 I-Channel, Data Bit 7 Output
6 ID6 I-Channel Data Bit 6 Output
7 ID5 I-Channel, Data Bit 5 Output
8DV
CC3 Digital Output Supply
(+3.0V or +5.0V)
9D
GND Digital Ground
10 ID4 I-Channel, Data Bit 4 Output
11 ID3 I-Channel, Data Bit 3 Output
12 ID2 I-Channel, Data Bit 2 Output
13 ID1 I-Channel, Data Bit 1 Output
14 ID0 I-Channel, Data Bit 0 Output (LSB)
15 DGND Digital Ground
16 DVCC1 Digital Supply (+5.0V)
17 CLK Sample Clock Input
18 DVCC2 Digital Supply (+5.0V)
19 DGND Digital Ground
20 QD0 Q-Channel, Data Bit 0 Output (LSB)
21 QD1 Q-Channel, Data Bit 1 Output
22 QD2 Q-Channel, Data Bit 2 Output
23 QD3 Q-Channel, Data Bit 3 Output
24 QD4 Q-Channel, Data Bit 4 Output
25 DGND Digital Ground
26 DVCC3 Digital Output Supply
(+3.0V or +5.0V)
27 QD5 Q-Channel, Data Bit 5 Output
28 QD6 Q-Channel, Data Bit 6 Output
29 QD7 Q-Channel, Data Bit 7 Output
30 QD8 Q-Channel, Data Bit 8 Output
31 QD9 Q-Channel, Data Bit 9 Output (MSB)
32 AVCC2 Analog Supply (+5.0V)
33 AGND Analog Ground
34 QVDC Q-Channel DC Bias Voltage Output
35 QIN- Q-Channel Negative Analog Input
36 QIN+ Q-Channel Positive Analog Input
37 AVCC1 Analog Supply (+5.0V)
38 VROUT +2.5V Reference Voltage Output
39 NC No Connect
40 VRIN +2.5V Reference Voltage Input
41 AGND Analog Ground
42 IIN+ I-Channel Positive Analog Input
43 IIN- I-Channel Negative Analog Input
44 IVDC I-Channel DC Bias Voltage Output
PIN NO. NAME DESCRIPTION
HI5762
6FN4318.3
January 22, 2010
Absolute Maximum Ratings TA= +25°C Thermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V
DGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Typical, Note 3) θJA (°C/W)
44 Ld MQFP Package . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = +25°C; Differential Analog Input; Unless Otherwise Specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ACCURACY
Resolution 10 - - Bits
Integral Linearity Error, INL fIN = 10MHz - ±2 - LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes) fIN = 10MHz - ±0.4 ±1.0 LSB
Offset Error, VOS fIN = DC -40 - +40 LSB
Full Scale Error, FSE fIN = DC - 4 - LSB
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate No Missing Codes - 1 - MSPS
Maximum Conversion Rate No Missing Codes 60 - - MSPS
Effective Number of Bits, ENOB fIN = 10MHz 8.4 8.8 - Bits
Signal to Noise and Distortion Ratio, SINAD fIN = 10MHz - 54.7 - dB
Signal to Noise Ratio, SNR fIN = 10MHz - 54.7 - dB
Total Harmonic Distortion, THD fIN = 10MHz - -68 - dBc
2nd Harmonic Distortion fIN = 10MHz - -70 - dBc
3rd Harmonic Distortion fIN = 10MHz - -73 - dBc
Spurious Free Dynamic Range, SFDR fIN = 10MHz - 70 - dBc
Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - 64 - dBc
I/Q Channel Crosstalk --75- dBc
I/Q Channel Offset Match -10-LSB
I/Q Channel Full Scale Error Match - 10 - LSB
Transient Response (Note 4) - 1 - Cycle
Overvoltage Recovery 0.2V Overdrive (Note 4) - 1 - Cycle
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input
Range (VIN+ - VIN-) -±0.5 - V
Maximum Peak-to-Peak Single-Ended
Analog Input Range -1.0- V
Analog Input Resistance, RIN+ or RIN- VIN+, VIN- = VREF, DC - 1 - MΩ
RMS Signal
RMS Noise + Distortion
--------------------------------------------------------------
=
RMS Signal
RMS Noise
-------------------------------
=
HI5762
7FN4318.3
January 22, 2010
Analog Input Capacitance, CIN+ or CIN- VIN+, VIN- = 2.5V, DC - 10 - pF
Analog Input Bias Current, IB+ or IB-V
IN+, VIN- = VREF-, VREF+,DC
(Note 4, 5) -10 - 10 µA
Differential Analog Input Bias Current
IBDIFF = (IB+ - IB-) (Notes 4, 5) -0.5 - +0.5 µA
Full Power Input Bandwidth, FPBW (Note 4) - 250 - MHz
Analog Input Common Mode Voltage Range
(VIN+ + VIN-)/2 Differential Mode (Note 4) 0.25 - 4.75 V
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, VROUT (Loaded) 2.35 2.5 2.65 V
Reference Output Current, IROUT -24mA
Reference Temperature Coefficient - -400 - ppm/oC
REFERENCE VOLTAGE INPUT
Reference Voltage Input, VRIN -2.5- V
Total Reference Resistance, RRIN with VRIN = 2.5V - 1.25 - kΩ
Reference Current, IRIN with VRIN = 2.5V - 2 - mA
DC BIAS VOLTAGE
DC Bias Voltage Output, VDC -3.0- V
Maximum Output Current --0.4mA
SAMPLING CLOCK INPUT
Input Logic High Voltage, VIH CLK 2.0 - - V
Input Logic Low Voltage, VIL CLK - - 0.8 V
Input Logic High Current, IIH CLK, VIH = 5V -10.0 - +10.0 µA
Input Logic Low Current, IIL CLK, VIL = 0V -10.0 - +10.0 µA
Input Capacitance, CIN CLK - 7 - pF
DIGITAL OUTPUTS
Output Logic High Voltage, VOH IOH = 100µA; DVCC3 = 5V 4.0 - - V
Output Logic Low Voltage, VOL IOL = 100µA; DVCC3 = 5V - - 0.8 V
Output Logic High Voltage, VOH IOH = 100µA; DVCC3 = 3V 2.4 - - V
Output Logic Low Voltage, VOL IOL = 100µA; DVCC3 = 3V - - 0.5 V
Output Capacitance, COUT -7- pF
TIMING CHARACTERISTICS
Aperture Delay, tAP -5- ns
Aperture Jitter, tAJ -5-ps
RMS
Data Output Hold, tH- 10.7 - ns
Data Output Delay, tOD - 11.7 - ns
Data Latency, tLAT For a Valid Sample (Note 4) 6 6 6 Cycles
Power-Up Initialization Data Invalid Time (Note 4) - - 20 Cycles
Sample Clock Pulse Width (Low) (Note 4) 7.5 8.3 - ns
Sample Clock Pulse Width (High) (Note 4) 7.5 8.3 - ns
Sample Clock Duty Cycle Variation - ±5- %
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVCC (Note 4) 4.75 5.0 5.25 V
Electrical Specifications AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = +25°C; Differential Analog Input; Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
HI5762
8FN4318.3
January 22, 2010
Digital Supply Voltage, DVCC1 and DVCC2 (Note 4) 4.75 5.0 5.25 V
Digital Output Supply Voltage, DVCC3 At 3.0V (Note 4) 2.7 3.0 3.3 V
At 5.0V (Note 4) 4.75 5.0 5.25 V
Supply Current, ICC fS = 60MSPS - 130 - mA
Power Dissipation - 650 670 mW
Offset Error Sensitivity, ΔVOS AVCC or DVCC = 5V ±5% - ±0.5 - LSB
Gain Error Sensitivity, ΔFSE AVCC or DVCC = 5V ±5% - ±0.6 - LSB
NOTES:
4. Limits established by characterization and are not production tested.
5. With the clock low and DC input.
Electrical Specifications AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = +25°C; Differential Analog Input; Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Timing Waveforms
NOTES:
6. SN: N-th sampling period.
7. HN: N-th holding period.
8. BM, N: M-th stage digital output corresponding to N-th sampled input.
9. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. HI5762 INTERNAL CIRCUIT TIMING
DN - 6 DN - 5 DN - 1 DNDN + 1 DN + 2
ANALOG
INPUT
CLOCK
INPUT
INPUT
S/H
1ST
STAGE
2ND
STAGE
9TH
STAGE
DATA
OUTPUT
SN - 1 HN - 1 SNHNSN + 1 HN + 1 SN + 2 SN + 5 HN + 5 SN + 6 HN + 6 SN + 7 HN + 7 SN + 8 HN + 8
B1, N - 1 B1, N B1, N + 1 B1, N + 4 B1, N + 5 B1, N + 6 B1, N + 7
B2, N - 2 B2, N - 1 B2, N B2, N + 4 B2, N + 5 B2, N + 6
B9, N - 5 B9, N - 4 B9, N B9, N + 1 B9, N + 2 B9, N + 3
tLAT
HI5762
9FN4318.3
January 22, 2010
FIGURE 2. HI5762 INPUT-TO OUTPUT TIMING
Timing Waveforms (Continued)
tOD
tH
DATA N-1 DATA N
CLOCK
INPUT
DATA
OUTPUT
1.5V
tAP
ANALOG
INPUT
tAJ
1.5V
2.4V
0.5V
Typical Performance Curves
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) AND
SINAD vs INPUT FREQUENCY FIGURE 4. SNR vs INPUT FREQUENCY
FIGURE 5. -THD, -2HD AND -3HD vs INPUT FREQUENCY FIGURE 6. SINAD, SNR AND -THD vs INPUT AMPLITUDE
ENOB (BITS)
SINAD (dB)
9
8
7
6
1M 10M 100M
INPUT FREQUENCY (Hz)
fS = 60MSPS
TA = +25°C
56
50
44
38
SNR (dB)
56
50
44
38
1M 10M 100M
INPUT FREQUENCY (MHz)
fS = 60MSPS
TA = +25°C
dBc
90
1M 10M 100M
INPUT FREQUENCY (Hz)
fS = 60MSPS
TA = +25°C
85
80
75
70
65
60
55
50
-3HD
-2HD
-THD
dB
70
-40
INPUT LEVEL (dBFS)
60
50
40
30
-20 0
SINAD (dB)
SNR (dB)
-THD (dBc)
20 -30 -10
fS = 60MSPS
fIN = 10MHz
TA = +25°C
HI5762
10 FN4318.3
January 22, 2010
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs
SAMPLE CLOCK DUTY CYCLE FIGURE 8. SUPPL Y CURRENT vs SAMPLE CLOCK
FREQUENCY
FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs
TEMPERATURE FIGURE 10. INTERNAL REFERENCE VOL TAGE (VROUT) vs
TEMPERATURE
FIGURE 11. DC BIAS VOLTAGE (I/QVDC) vs TEMPERATURE FIGURE 12. DATA OUTPUT DELAY (tOD) vs TEMPERATURE
Typical Performance Curves (Continued)
ENOB (BITS)
9
40
DUTY CYCLE (%, tHI/tCLK)
42 44 46 48 50 52 54 56 58 60
5
6
7
8
fS = 60MSPS
TA = +25°C
1MHz < fIN < 15MHz
SUPPLY CURRENT (mA)
10
fS (MSPS)
20 30 50 60 70
0
TA = +25°C
1MHz < fIN < 15MHz
40
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
ICC
AICC
DICC2
DICC1
DICC3
ENOB (BITS)
9.0
TEMPERATURE (°C)
020406080
7.0
7.5
8.0
8.5
fS = 60MSPS
fIN = 10MHz
I CHANNEL
Q CHANNEL
-20-40
INTERNAL REFERENCE VOLTAGE
2.50
TEMPERATURE (°C)
020406080
VROUT
-20-40
2.49
2.48
2.47
2.46
2.45
2.44
2.43
2.42
2.41
2.40
VROUT (V)
DC BIAS VOLTAGE, I/QVDC (V)
3.10
TEMPERATURE (°C)
0 20406080
QVDC
-20-40
3.05
3.00
2.95
2.90
2.85
IVDC
tOD (ns)
13.0
TEMPERATURE (°C)
0 20406080-20-40
12.5
12.0
11.5
11.0
tOD
HI5762
11 FN4318.3
January 22, 2010
Detailed Description
Theory of Operation
The HI5762 is a dual 10-bit fully di f ferentia l sampling pi peline
A/D converter with digital error correction logic. Figure 15
depicts the circuit for the front-end differential-in-differential-
out sample-and-hold (S/H ) amplifiers. The switches are
controlled by an internal sampling clock which is a
non-overlapping tw o phase signal, Φ1 and Φ2, derived from
the master sampling clock. During the sampling ph ase, Φ1,
the input signal is applied to th e sampl ing cap a citors, CS. At
the same time the holding capaci tors, C H, are discha rged to
analog ground. At the falling ed ge of Φ1 the input signal is
sampled on the bottom plates of the sampling cap acitors. In
the next clock phase, Φ2, the two bottom plates of the
sampling capacitors are connected toge ther and the hol ding
capacitors are switched to th e op amp output n odes. The
charge then redistribute s between CS and CH completing one
sample-and-hold cycle. The front end sample-and-hold output
is a fully-diff erential, sampled -dat a rep resent ation of the
analog input. The circuit not only perfo rms the sample-a nd-
hold function but will also convert a sin gle-end ed input to a
fully-differe ntial o utput for the converter core. During the
sampling phase, the I/Q IN pins see only the on -resistance of a
switch and CS. The relatively small values of these
components result in a typ ical full power inpu t bandwi d th of
250MHz for the converter.
FIGURE 13. SUPPLY CURRENT vs TEMPERATURE FIGURE 14. 2048 POINT FFT PLOT
Typical Performance Curves (Continued)
SUPPLY CURRENT (mA)
0
140
120
100
80
60
40
20
TEMPERATURE (°C)
020406080-20-40
fS = 60MSPS
1MHz < fIN < 15MHz
AICC
ICC
DICC1
DICC2
DICC3
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-1000 100 200 300 400 500 600 700 800 900 1023
FREQUENCY (BIN)
dB
fS = 60MSPS
fIN = 10MHz
TA = +25°C
TABLE 1. A/D CODE TABLE
CODE CENTER
DESCRIPTION
DIFFERENTIAL INPUT
VOLTAGE
(I/QIN+ - I/QIN-)
OFFSET BINARY OUTPUT CODE
MSB LSB
I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0
+Full Scale (+FS) -1/4LSB 0.499756V 1 1 1 1 1 1 1 1 1 1
+FS - 11/4LSB 0.498779V 1 1 1 1 1 1 1 1 1 0
+3/4LSB 732.422μV 1000000000
-1/4LSB -244.141μV 0111111111
-FS + 13/4LSB -0.498291V 0 0 0 0 0 0 0 0 0 1
-Full Scale (-FS) + 3/4LSB -0.499268V 0 0 0 0 0 0 0 0 0 0
NOTE:
10. The voltages listed above represent the ideal center of each output code shown with VREFIN =+2.5V.
-
+
+
-
CH
CS
CS
CH
I/QIN+ VOUT+
VOUT-
I/QIN-
Φ1
Φ1
Φ1
Φ2
Φ1
Φ1
Φ1
FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD
HI5762
12 FN4318.3
January 22, 2010
As illustrated in the “Functional Block Diagram” on page 3
and the timing diagram in Figure 1 on page 8, eight identical
pipeline subconverter stages, each containing a two-bit flash
converter and a two-bit multiplying digital-to-analog
converter, follow the S/H circuit with the ninth stage being a
two bit flash converter. Each converter stage in the pipeline
will be sampling in one phase and amplifying in the other
clock phase. Each individual subconverter clock signal is
offset by 180° from the previous stage clock signal resulting
in alternate stages in the pipeline performing the same
operation.
The output of each of the eight identical two-bit sub conve rter
stages is a two-bit digit al w ord cont ai ning a supplementary bit
to be used by the digit al error correcti on logic. The o utput of
each subconverter st age is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the di git al o utput s of the eight
identical two-bit subconverter st age s with the corresp onding
output of the ninth st age fla sh converter before applying the
eighteen bit result to the digit al error correction logi c. The
digital error correctio n logic uses th e supplemen t ary bits to
correct any error that may exist before generating the final ten
bit digital dat a outp ut of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the
analog sample is taken (see the timing diagram in Figure 1
on page 8). This time delay is specified as the data latency.
After the data latency time, the digital data representing each
succeeding analog sample is output durin g the following
clock cycle. The digital output data is provided in offset
binary format (see Table 1, A/D Code Table).
Internal Reference Voltage Output, VREFOUT
The HI5762 is equipped with an in ternal reference voltage
generator, therefore, no external reference voltage is
required. VROUT must be connected to VRIN when using the
internal reference voltage.
An internal band-gap reference voltage followed by an
amplifier/buffer generates the precision +2.5V reference
voltage used by the converter. A band-gap reference circuit is
used to generate a precision +1.25V internal reference voltage.
This voltage is then amplified by a wide-band uncompensated
operational amplifier connected in a gain-of-two configuration.
An external, user-supplied, 0.1µF capacitor connected from the
VROUT output pin to analog ground is used to set the dominant
pole and to maintain the stability of the operational amplifier .
Reference Voltage Input, VREFIN
The HI5762 is designed to accept a +2.5V reference voltage
source at the VRIN input pin. Typical operation of the
converter requires VRIN to be set at +2.5V. The HI5762 is
tested with VRIN connected to VROUT yielding a fully
differential analog input voltage range of ±0.5V.
The user does have the option of supplying an external +2.5V
reference voltage. As a result of the high input impedance
presented at the VRIN input pin, 1.25kΩ typically, the external
reference voltage being used is onl y required to source 2mA
of reference input current. In the situation whe re an external
reference voltage will be used an exte rnal 0.1µF cap acitor
must be connected from the VROUT output pin to analog
ground in order to maint ain the st ab ility of the internal
operational amplifier.
In order to minimize overall converter noise it is
recommended that ad equate high frequency decoup ling be
provided at the reference voltage input pin, VRIN.
Analog Input, Differential Connection
The analog input of the HI5762 is a differential input that can
be configured in various ways depending on the signal
source and the require d level of performance. A fully
differential connection (Figure 16 and Figure 17) will deliver
the best performance from the converter.
Since the HI5762 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V.
The performance of the ADC does not change significantly
with the value of the analog input common mode voltage.
A DC voltage source, I/QVDC, equal to 3.0V (typical), is
made available to the user to help simplify circuit design
when using an AC-coupled differential input. This low output
impedance voltage source is not designed to be a reference
but makes an excellent DC bias source and stays well within
the analog input common mode voltage range over
temperature.
For the AC-coupled dif ferentia l input (se e Figure 16 ) and with
VRIN connected to VROUT, full scale is achieved when th e
VIN a nd -VIN input signals are 0.5VP-P, with -VIN being 180°
out-of-phase with VIN. The converter will be at positive full
scale when the I/QIN+ in put is at VDC + 0.25V and the I/QIN-
input is at VDC - 0.25V (I/QIN+-I/Q
IN- = +0.5V). Conversely,
the converter will be at negative full scale when the I/Q IN+
input is equal to VDC - 0.25V and I/QIN- is at
VDC + 0.25V (I/QIN+ - I/QIN-=-0.5V).
I/QIN+
I/QVDC
I/QIN-
HI5762
VIN
-VIN
R
R
FIGURE 16. AC-COUPLED DIFFERENTIAL INPUT
HI5762
13 FN4318.3
January 22, 2010
The analog input can be DC coupled (see Figure 17) as long
as the inputs are within the analog input common mode
voltage range (0.25V VDC 4.75V).
The resistors, R, in Figure 17 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from I/QIN+ to I/QIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on
AC-coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Fig ure 18 may be used with a
single-ended AC-coupled input.
Again, with VRIN connected to VROUT, if VIN is a 1VP-P
sinewave, then I/QIN+ is a 1.0VP-P sinewave riding on a
positive voltage equal to VDC. The converter will be at positive
full scale when I/QIN+ is at VDC + 0.5V (I/QIN+ - I/QIN-=+0.5V)
and will be at negative full scale when I/QIN+ is equal to
VDC - 0.5V (I/QIN+-I/Q
IN- = -0.5V). Sufficient headroom must
be provided such that the input voltage never goes above +5V
or below AGND. In this case, VDC could range between 0.5V
and 4.5V without a significant change in ADC performance.
The simplest way to produce VDC is to use the DC bias source,
I/QVDC, output of the HI5762.
The single ended analog input can be DC-coupled (see
Figure 19) as long as the input is within the analog input
common mode voltage range.
The resistor, R, in Figure 19 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from I/QIN+ to I/QIN- will help filter any high
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on
AC-coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of th e analog input signal.
A single-ended source may give better overall system
performance if it is first converted to differential before
driving the HI5762.
Sampling Clock Requirements
The HI5762 sampling clock input provides a standard
high-speed interface to external TTL/CMOS logic families.
In order to ensure rated performance of the HI5762, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL/CMOS levels.
Performance of the HI5762 will only be guaranteed at
conversion rates above 1MSPS (Typ). This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of
20 cycles at a sample rate above 1MSPS must be
performed before valid data is available.
Supply and Ground Considerations
The HI5762 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The digital data outputs also have a separate supply
pin, DVCC3, which can be powered from a 3.0V or 5.0V
supply. This allows the o utputs to interface with 3.0V logic if
so desired.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performan c e, the
supplies to the HI5762 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply can be isolated by a ferrite
bead from the digital supply.
Refer to the application note “Using Intersil High-Speed A/D
Converters” (AN9214) for additional considerations when
using high-speed converters.
I/QIN+
I/QVDC
I/QIN-
HI5762
VIN
-VIN R
RC
VDC
VDC
FIGURE 17. DC COUPLED DIFFERENTIAL INPUT
I/QIN+
I/QIN-
HI5762
VIN
VDC
R
FIGURE 18. AC COUPLED SINGLE-ENDED INPUT
I/QIN+
I/QIN-
HI5762
VDC
R
C
VIN
VDC
FIGURE 19. DC COUPLED SINGLE ENDED INPUT
HI5762
14 FN4318.3
January 22, 2010
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4LSB
above half-scale. Offset is defined as the devi ation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input
that is 3/4LSB below Positive Full Scale (+FS) with the
offset error removed. Full scale error is defined as the
deviation of the actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and full scale error (in LSBs) is
noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5762. A low
distortion sine wave is applied to the input, it is coherently
sampled, and the output i s stored in RAM. The d ata is then
transformed into the frequency domain with an FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine w ave in put to the part is typically -0. 5dB down
from full scale for all these tests.
SNR and SINAD are quoted in dB. The distortion numbers
are quoted in dBc (decibels with respect to carrier) a nd DO
NOT include any correction factors for normalizing to full
scale.
The Effective Number of Bits (ENOB) is calculated from the
SINAD data by Equation 1:
where: VCORR = 0.5dB (Typ).
VCORR adjusts the SINAD, and hence the ENOB, for the
amount the analog input signa l is backed off from full scale.
Signal To Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the measured RMS signal to RMS
sum of all the other spectral components below the Nyqui st
frequency, fS/2, excluding DC.
Signal To Noise Ratio (SNR)
SNR is the r at i o o f th e measured RMS signal to RMS noise at
a specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components below fS/2
excluding the fundamental, the first five harmonics and DC.
Total Harmonic Distortion (THD)
THD is the ra tio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input
signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable
harmonic component to the RMS value of the fundamental
input sign a l.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitud e to the
RMS amplitude of the next largest spectral component in the
spectrum below fS/2.
Intermodulation Disto r tion (IMD)
Nonlinearities in the signal p ath will tend to ge nerate
intermodulation products w hen two tones, f 1 and f2, are
present at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2),
(f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB below
full scale.
Transient Response
Transient response is measured by providing a full-scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the o utput code to settle within
10-bit accuracy.
Over-Voltage Recovery
Over-V oltage Recovery is measured by providing a full-scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has an amplitude which swings from
-FS to +FS. The bandwidth given is measured at the
specified sampling frequency.
ENOB SINAD 1.76VCORR
+()6.02=(EQ. 1)
HI5762
15 FN4318.3
January 22, 2010
I/Q Channel Crosstalk
I/Q Channel Crosstalk is a measure of the amount of
channel separation or isolation between the two A/D
converter cores contained within the dual converter
package. The measurement consists of stimulating one
channel of the converter with a fullscale input signal and
then measuring the am ount that signal is below, in dBc, a
fullscale signal on the opposite channel.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This del ay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is take n, the digital data representing
an analog input sample is output to the digital data bus
following the 6th cycle of the clock after the analog sample is
taken. This is due to the pipeline na ture of the converter
where the analog samp le has to ri pple through th e internal
subconverter stages. This d elay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding ana log sample is output
during the following clock cycle. The digital data lags the
analog input sample by 6 sample clock cycles.
Power-Up Initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize th e dynamic
circuits within the converter.
HI5762
16
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN4318.3
January 22, 2010
HI5762
Metric Plastic Quad Flatpack Packages (MQFP)
D
D1
EE1
-A-
PIN 1
A2 A1
A
12o-16o
12o-16o
0o-7o
0.40
0.016 MIN
L
0o MIN
PLANE
b
0.005/0.009
0.13/0.23
WITH PLATING
BASE METAL
SEATING
0.005/0.007
0.13/0.17
b1
-B-
e
0.008
0.20 A-B SD SCM
0.076
0.003
-C-
-D-
-H-
Q44.10x10 (JEDEC MS-022AB ISSUE B)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.096 - 2.45 -
A1 0.004 0.010 0.10 0.25 -
A2 0.077 0.083 1.95 2.10 -
b 0.012 0.018 0.30 0.45 6
b1 0.012 0.016 0.30 0.40 -
D 0.515 0.524 13.08 13.32 3
D1 0.389 0.399 9.88 10.12 4, 5
E 0.516 0.523 13.10 13.30 3
E1 0.390 0.398 9.90 10.10 4, 5
L 0.029 0.040 0.73 1.03 -
N44 447
e 0.032 BSC 0.80 BSC -
Rev. 2 4/99
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane .
4. Dimensions D1 and E1 to be determined at datum plane
.
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
-C-
-H-