ADC12H030/ADC12H032/ADC12H034/ADC12H038,
ADC12030/ADC12032/ADC12034/ADC12038
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold
General Description
The ADC12030, and ADC12H030 families are 12-bit plus
sign successive approximationA/D converters with serial I/O
and configurable input multiplexers. The ADC12032/
ADC12H032, ADC12034/ADC12H034 and ADC12038/
ADC12H038 have 2, 4 and 8 channel multiplexers, respec-
tively. The differential multiplexer outputs and A/D inputs are
available on the MUXOUT1, MUXOUT2,A/DIN1 andA/DIN2
pins. The ADC12030/ADC12H030 has a two channel multi-
plexer with the multiplexer outputs and A/D inputs internally
connected. The ADC12030 family is tested witha5MHz
clock, while the ADC12H030 family is tested with an 8 MHz
clock. On request, these A/Ds go through a self calibration
process that adjusts linearity, zero and full-scale errors to
less than ±1 LSB each.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes.Afully differential unipolar analog
input range (0V to +5V) can be accommodated with a single
+5V supply. In the differential modes, valid outputs are ob-
tained even when the negative inputs are greater than the
positive because of the 12-bit plus sign output data format.
The serial I/O is configured to comply with the
NSC MICROWIRE™. For voltage references see the
LM4040 or LM4041.
Features
nSerial I/O (MICROWIRE Compatible)
n2, 4, or 8 channel differential or single-ended multiplexer
nAnalog input sample/hold function
nPower down mode
nVariable resolution and conversion rate
nProgrammable acquisition time
nVariable digital output word length and format
nNo zero or full scale adjustment required
nFully tested and guaranteed with a 4.096V reference
n0V to 5V analog input range with single 5V power
supply
nNo Missing Codes over temperature
Key Specifications
nResolution 12-bit plus sign
n12-bit plus sign conversion time
— ADC12H030 family 5.5 µs (max)
— ADC12030 family 8.8 µs (max)
n12-bit plus sign throughput time
— ADC12H030 family 8.6 µs (max)
— ADC12030 family 14 µs (max)
nIntegral linearity error ±1 LSB (max)
nSingle supply 5V ±10%
nPower dissipation 33 mW (max)
— Power down 100 µW (typ)
Applications
nMedical instruments
nProcess control systems
nTest equipment
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
COPS™microcontrollers, HPC™and MICROWIRE™are trademarks of National Semiconductor Corporation.
July 1999
ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
© 1999 National Semiconductor Corporation DS011354 www.national.com
ADC12038 Simplified Block Diagram
Connection Diagrams
DS011354-1
16-Pin Wide Body
SO Packages
DS011354-6
Top View
20-Pin Wide Body
SO Packages
DS011354-7
Top View
www.national.com 2
Connection Diagrams (Continued)
Ordering Information
Industrial Temperature Range Package
−40˚C ≤T
A
≤+85˚C
ADC12H030CIWM, ADC12030CIWM M16B
ADC12H032CIWM, ADC12032CIWM M20B
ADC12H034CIN, ADC12034CIN N24C
ADC12H034CIWM, ADC12034CIWM M24B
ADC12H038CIWM, ADC12038CIWM M28B
Pin Descriptions
CCLK The clock applied to this input controls the
sucessive approximation conversion time
interval and the acquisition time. The rise
and fall times of the clock edges should not
exceed 1 µs.
SCLK This is the serial data clock input. The clock
applied to this input controls the rate at
which the serial data exchange occurs. The
rising edge loads the information on the DI
pin into the multiplexer address and mode
select shift register. This address controls
which channel of the analog input multi-
plexer (MUX) is selected and the mode of
operation for the A/D. With CS low the fall-
ing edge of SCLK shifts the data resulting
from the previous ADC conversion out on
DO, with the exception of the first bit of data.
When CS is low continously, the first bit of
the data is clocked out on the rising edge of
EOC (end of conversion). When CS is
toggled the falling edge of CS always clocks
out the first bit of data. CS should be
brought low when SCLK is low. The rise and
fall times of the clock edges should not ex-
ceed 1 µs.
DI This is the serial data input pin. The data ap-
plied to this pin is shifted by the rising edge
of SCLK into the multiplexer address and
mode select register.
Table 2
through
Table
5
show the assignment of the multiplexer
address and the mode select data.
DO The data output pin. This pin is an active
push/pull output when CS is low. When CS
is high, this output is TRI-STATE. The A/D
conversion result (D0–D12) and converter
status data are clocked out by the falling
edge of SCLK on this pin. The word length
and format of this result can vary (see
Table
1
). The word length and format are con-
trolled by the data shifted into the multi-
plexer address and mode select register
(see
Table 5
).
EOC This pin is an active push/pull output and in-
dicates the status of the ADC12030/2/4/8.
When low, it signals that theA/D is busy with
a conversion, auto-calibration, auto-zero or
power down cycle. The rising edge of EOC
signals the end of one of these cycles.
CS This is the chip select pin. When a logic low
is applied to this pin, the rising edge of
SCLK shifts the data on DI into the address
register. This low also brings DO out of
TRI-STATE. With CS low the falling edge of
SCLK shifts the data resulting from the pre-
vious ADC conversion out on DO, with the
24-Pin Wide Body
SO Packages
DS011354-8
Top View
28-Pin Wide Body
SO Packages
DS011354-9
Top View
www.national.com3
Pin Descriptions (Continued)
exception of the first bit of data. When CS is
low continously, the first bit of the data is
clocked out on the rising edge of EOC (end
of conversion). When CS is toggled the fall-
ing edge of CS always clocks out the first bit
of data. CS should be brought low when
SCLK is low. The falling edge of CS resets a
conversion in progress and starts the se-
quence for a new conversion. When CS is
brought back low during a conversion, that
conversion is prematurely terminated. The
data in the output latches may be corrupted.
Therefore, when CS is brought back low
during a conversion in progress the data
output at that time should be ignored. CS
may also be left continuously low. In this
case it is imperative that the correct number
of SCLK pulses be applied to theADC in or-
der to remain synchronous. After the ADC
supply power is applied it expects to see 13
clock pulses for each I/O sequence. The
number of clock pulses the ADC expects is
the same as the digital output word length.
This word length can be modified by the
data shifted in on the DO pin.
Table 5
details
the data required.
DOR This is the data output ready pin. This pin is
an active push/pull output. It is low when the
conversion result is being shifted out and
goes high to signal that all the data has
been shifted out.
CONV Alogic low is required on this pin to program
any mode or change the ADC’s configura-
tion as listed in the Mode Programming
Table 5
such as 12-bit conversion, 8-bit con-
version, Auto Cal, Auto Zero etc. When this
pin is high the ADC is placed in the read
data only mode. While in the read data only
mode, bringing CS low and pulsing SCLK
will only clock out on DO any data stored in
the ADCs output shift register. The data on
DI will be neglected. A new conversion will
not be started and the ADC will remain in
the mode and/or configuration previously
programmed. Read data only cannot be
performed while a conversion, Auto-Cal or
Auto-Zero are in progress.
PD This is the power down pin. When PD is
high the A/D is powered down; when PD is
low the A/D is powered up. The A/D takes a
maximum of 250 µs to power up after the
command is given.
CH0–CH7 These are the analog inputs of the MUX. A
channel input is selected by the address in-
formation at the DI pin, which is loaded on
the rising edge of SCLK into the address
register (See
Tables 2, 3, 4
).
The voltage applied to these inputs should
not exceed V
A
+ or go below GND. Exceed-
ing this range on an unselected channel will
corrupt the reading of a selected channel.
COM This pin is another analog input pin. It is
used as a pseudo ground when the analog
multiplexer is single-ended.
MUXOUT1,
MUXOUT2 These are the multiplexer output
pins.
A/DIN1, /DIN2 These are the converter input pins. MUX-
OUT1 is usually tied to A/DIN1. MUXOUT2
is usually tied to A/DIN2. If external circuitry
is placed between MUXOUT1 and A/DIN1,
or MUXOUT2 and A/DIN2 it may be neces-
sary to protect these pins. The voltage at
these pins should not exceed V
A+
or go be-
low AGND (see
Figure 5
).
V
REF
+ This is the positive analog voltage reference
input. In order to maintain accuracy, the
voltage range of V
REF
(V
REF
=V
REF
+−
V
REF
−) is 1 V
DC
to 5.0 V
DC
and the voltage
at V
REF
+ cannot exceed V
A
+. See
Figure 6
for recommended bypassing.
V
REF
− The negative voltage reference input. In or-
der to maintain accuracy, the voltage at this
pin must not go below GND or exceed V
A
+.
(See
Figure 6
).
V
A
+, V
D
+ These are the analog and digital power sup-
ply pins. V
A+
and V
D+
are not connected to-
gether on the chip. These pins should be
tied to the same power supply and by-
passed separately (see
Figure 6
). The oper-
ating voltage range of V
A
+ and V
D
+is
4.5 V
DC
to 5.5 V
DC
.
DGND This is the digital ground pin (see
Figure 6
).
AGND This is the analog ground pin (see
Figure 6
).
www.national.com 4
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage
(V
+
=V
A
+=V
D
+) 6.5V
Voltage at Inputs and Outputs
except CH0–CH7 and COM −0.3V to V
+
+0.3V
Voltage at Analog Inputs
CH0–CH7 and COM GND −5V to V
+
+5V
|V
A
+−V
D
+| 300 mV
Input Current at Any Pin (Note 3) ±30 mA
Package Input Current (Note 3) ±120 mA
Package Dissipation at
T
A
=25˚C (Note 4) 500 mW
ESD Susceptability (Note 5)
Human Body Model 1500V
Soldering Information
N Packages (10 seconds) 260˚C
SO Package (Note 6):
Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C
Storage Temperature −65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Operating Temperature Range T
MIN
≤T
A
≤T
MAX
ADC12030CIWM,
ADC12H030CIWM,
ADC12032CIWM,
ADC12H032CIWM,
ADC12034CIN, ADC12034CIWM,
ADC12H034CIN,
ADC12H034CIWM,
ADC12038CIWM,
ADC12H038CIWM −40˚C ≤T
A
≤+85˚C
Supply Voltage (V
+
=V
A
+=V
D
+) +4.5V to +5.5V
|V
A
+−V
D
+| ≤100 mV
V
REF
+ 0VtoV
A
+
V
REF
− 0VtoV
REF
+
V
REF
(V
REF
+−V
REF
−) 1V to V
A
+
V
REF
Common Mode Voltage Range
0.1 V
A
+ to 0.6 V
A
+
A/DIN1, A/DIN2, MUXOUT1
and MUXOUT2 Voltage Range 0V to V
A
+
A/D IN Common Mode
Voltage Range
0V to V
A
+
Converter Electrical Characteristics
The following specifications apply for V
+
=V
A
+=V
D
+=+5.0 V
DC
,V
REF
+=+4.096 V
DC
,V
REF
−=0V
DC
, 12-bit + sign conver-
sion mode, f
CK
=f
SK
=8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
=f
SK
=5 MHz for the
ADC12030, ADC12032, ADC12034 and ADC12038, R
S
=25Ω, source impedance for V
REF
+ and V
REF
−≤25Ω, fully-differential
input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Boldface limits apply
for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
=25˚C. (Notes 7, 8, 9)
Symbol Parameter Conditions Typical
(Note 10) Limits
(Note 11) Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No
Missing Codes 12 + sign Bits (min)
+ILE Positive Integral Linearity Error After Auto-Cal (Notes 12, 18) ±1/2 ±1LSB (max)
−ILE Negative Integral Linearity Error After Auto-Cal (Notes 12, 18) ±1/2 ±1LSB (max)
DNL Differential Non-Linearity After Auto-Cal ±1LSB (max)
Positive Full-Scale Error After Auto-Cal (Notes 12, 18) ±1/2 ±3.0 LSB (max)
Negative Full-Scale Error After Auto-Cal (Notes 12, 18) ±1/2 ±3.0 LSB (max)
Offset Error After Auto-Cal (Notes 5, 18) ±1/2 ±2LSB (max)
V
IN
(+) =V
IN
(−) =2.048V
DC Common Mode Error After Auto-Cal (Note 15) ±2±3.5 LSB (max)
TUE Total Unadjusted Error After Auto-Cal ±1 LSB
(Notes 12, 13, 14)
Resolution with No
Missing Codes 8-bit + sign mode 8 + sign Bits (min)
+INL Positive Integral Linearity Error 8-bit + sign mode (Note 12) ±1/2 LSB (max)
−INL Negative Integral Linearity Error 8-bit + sign mode (Note 12) ±1/2 LSB (max)
DNL Differential Non-Linearity 8-bit + sign mode ±3/4 LSB (max)
Positive Full-Scale Error 8-bit + sign mode (Note 12) ±1/2 LSB (max)
Negative Full-Scale Error 8-bit + sign mode (Note 12) ±1/2 LSB (max)
www.national.com5
Converter Electrical Characteristics (Continued)
The following specifications apply for V
+
=V
A
+=V
D
+=+5.0 V
DC
,V
REF
+=+4.096 V
DC
,V
REF
−=0V
DC
, 12-bit + sign conver-
sion mode, f
CK
=f
SK
=8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
=f
SK
=5 MHz for the
ADC12030, ADC12032, ADC12034 and ADC12038, R
S
=25Ω, source impedance for V
REF
+ and V
REF
−≤25Ω, fully-differential
input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Boldface limits apply
for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
=25˚C. (Notes 7, 8, 9)
Symbol Parameter Conditions Typical
(Note 10) Limits
(Note 11) Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Offset Error 8-bit + sign mode,
after Auto-Zero (Note 13) ±1/2 LSB (max)
V
IN
(+) =V
IN
(−) =+ 2.048V
TUE Total Unadjusted Error 8-bit + sign mode
after Auto-Zero ±3/4 LSB (max)
(Notes 12, 13, 14)
Multiplexer Channel
to Channel Matching ±0.05 LSB
Power Supply Sensitivity V
+
=+5V ±10%
V
REF
=+4.096V
Offset Error ±0.5 ±1LSB (max)
+ Full-Scale Error ±0.5 ±1.5 LSB (max)
− Full-Scale Error ±0.5 ±1.5 LSB (max)
+ Integral Linearity Error ±0.5 LSB
− Integral Linearity Error ±0.5 LSB
Output Data from (Note 20) +10 LSB (max)
“12-Bit Conversion of Offset” −10 LSB (min)
(see
Table 5
)
Output Data from (Note 20) 4095 LSB (max)
“12-Bit Conversion of Full-Scale” 4093 LSB (min)
(see
Table 5
)
UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plus f
IN
=1 kHz, V
IN
=5V
PP
,V
REF+
=5.0V 69.4 dB
Distortion Ratio f
IN
=20 kHz, V
IN
=5V
PP
,V
REF+
=5.0V 68.3 dB
f
IN
=40 kHz, V
IN
=5V
PP
,V
REF
+=5.0V 65.7 dB
−3 dB Full Power Bandwidth V
IN
=5V
PP
, where S/(N+D) drops 3 dB 31 kHz
DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
S/(N+D) Signal-to-Noise Plus f
IN
=1 kHz, V
IN
=±5V, V
REF+
=5.0V 77.0 dB
Distortion Ratio f
IN
=20 kHz, V
IN
=±5V, V
REF+
=5.0V 73.9 dB
f
IN
=40 kHz, V
IN
=±5V, V
REF+
=5.0V 67.0 dB
−3 dB Full Power Bandwidth V
IN
=±5V, where S/(N+D) drops 3 dB 40 kHz
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
C
REF
Reference Input Capacitance 85 pF
C
A/D
A/DIN1 and A/DIN2 Analog 75 pF
Input Capacitance
A/DIN1 and A/DIN2 Analog V
IN
=+5.0V or ±0.1 ±1.0 µA (max)
Input Leakage Current V
IN
=0V
CH0–CH7 and COM GND − 0.05 V (min)
Input Voltage V
A
+ + 0.05 V (max)
C
CH
CH0–CH7 and COM
Input Capacitance 10 pF
C
MUXOUT
MUX Output Capacitance 20 pF
www.national.com 6
Converter Electrical Characteristics (Continued)
The following specifications apply for V
+
=V
A
+=V
D
+=+5.0 V
DC
,V
REF
+=+4.096 V
DC
,V
REF
−=0V
DC
, 12-bit + sign conver-
sion mode, f
CK
=f
SK
=8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
=f
SK
=5 MHz for the
ADC12030, ADC12032, ADC12034 and ADC12038, R
S
=25Ω, source impedance for V
REF
+ and V
REF
−≤25Ω, fully-differential
input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Boldface limits apply
for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
=25˚C. (Notes 7, 8, 9)
Symbol Parameter Conditions Typical
(Note 10) Limits
(Note 11) Units
(Limits)
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
Off Channel Leakage (Note 16) On Channel =5V and −0.01 −0.3 µA (min)
CH0–CH7 and COM Pins Off Channel =0V
On Channel =0V and 0.01 0.3 µA (max)
Off Channel =5V
On Channel Leakage (Note 16) On Channel =5V and 0.01 0.3 µA (max)
CH0–CH7 and COM Pins Off Channel =0V
On Channel =0V and −0.01 −0.3 µA (min)
Off Channel =5V
MUXOUT1 and MUXOUT2 V
MUXOUT
=5.0V or 0.01 0.3 µA (max)
Leakage Current V
MUXOUT
=0V
R
ON
MUX On Resistance V
IN
=2.5V and 850 1150 Ω(max)
V
MUXOUT
=2.4V
R
ON
Matching Channel V
IN
=2.5V and 5 %
to Channel V
MUXOUT
=2.4V
Channel to Channel Crosstalk V
IN
=5V
PP
,f
IN
=40 kHz −72 dB
MUX Bandwidth 90 kHz
DC and Logic Electrical Characteristics
The following specifications apply for V
+
=V
A
+=V
D
+=+5.0 V
DC
,V
REF
+=+4.096 V
DC
,V
REF
−=0V
DC
, 12-bit + sign conver-
sion mode, f
CK
=f
SK
=8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
=f
SK
=5 MHz for the
ADC12030, ADC12032, ADC12034 and ADC12038, R
S
=25Ω, source impedance for V
REF
+ and V
REF
−≤25Ω, fully-differential
input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Boldface limits apply
for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
=25˚C. (Notes 7, 8, 9)
Symbol Parameter Conditions Typical Limits Units
(Note 10) (Note 11) (Limits)
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
V
IN(1)
Logical “1” Input Voltage V
+
=5.5V 2.0 V (min)
V
IN(0)
Logical “0” Input Voltage V
+
=4.5V 0.8 V (max)
I
IN(1)
Logical “1” Input Current V
IN
=5.0V 0.005 1.0 µA (max)
I
IN(0)
Logical “0” Input Current V
IN
=0V −0.005 −1.0 µA (min)
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
V
OUT(1)
Logical “1” Output Voltage V
+
=4.5V, I
OUT
=−360 µA 2.4 V (min)
V
+
=4.5V, I
OUT
=−10µA 4.25 V (min)
V
OUT(0)
Logical “0” Output Voltage V
+
=4.5V, I
OUT
=1.6 mA 0.4 V (max)
I
OUT
TRI-STATE®Output Current V
OUT
=0V −0.1 −3.0 µA (max)
V
OUT
=5V 0.1 3.0 µA (max)
+I
SC
Output Short Circuit Source Current V
OUT
=0V 14 6.5 mA (min)
−I
SC
Output Short Circuit Sink Current V
OUT
=V
D
+168.0 mA (min)
POWER SUPPLY CHARACTERISTICS
I
D
+ Digital Supply Current Awake 1.6 2.5 mA (max)
ADC12030, ADC12032, ADC12034 CS =HIGH, Powered Down, CCLK on 600 µA
and ADC12038 CS =HIGH, Powered Down, CCLK off 20 µA
Digital Supply Current Awake 2.3 3.2 mA
ADC12H030, ADC12H032, CS =HIGH, Powered Down, CCLK on 0.9 mA
ADC12H034 and ADC12H038 CS =HIGH, Powered Down, CCLK off 20 µA
www.national.com7
DC and Logic Electrical Characteristics (Continued)
The following specifications apply for V
+
=V
A
+=V
D
+=+5.0 V
DC
,V
REF
+=+4.096 V
DC
,V
REF
−=0V
DC
, 12-bit + sign conver-
sion mode, f
CK
=f
SK
=8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
=f
SK
=5 MHz for the
ADC12030, ADC12032, ADC12034 and ADC12038, R
S
=25Ω, source impedance for V
REF
+ and V
REF
−≤25Ω, fully-differential
input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Boldface limits apply
for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
=25˚C. (Notes 7, 8, 9)
Symbol Parameter Conditions Typical Limits Units
(Note 10) (Note 11) (Limits)
POWER SUPPLY CHARACTERISTICS
I
A
+ Positive Analog Supply Current Awake 2.7 4.0 mA (max)
CS =HIGH, Powered Down, CCLK on 10 µA
CS =HIGH, Powered Down, CCLK off 0.1 µA
I
REF
Reference Input Current Awake 70 µA
CS =HIGH, Powered Down 0.1 µA
AC Electrical Characteristics
The following specifications apply for V
+
=V
A
+=V
D
+=+5.0 V
DC
,V
REF
+=+4.096 V
DC
,V
REF
−=0V
DC
, 12-bit + sign conver-
sion mode, t
r
=t
f
=3 ns, f
CK
=f
SK
=8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
=f
SK
=5
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
S
=25Ω, source impedance for V
REF
+ and V
REF
−≤25Ω,
fully-differential input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Bold-
face limits apply for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
=25˚C. (Note 17)
Symbol Parameter Conditions Typical
(Note 10) ADC12H030/2/4/8 ADC12030/2/4/8 Units
(Limits)
Limits Limits
(Note 11) (Note 11)
f
CK
Conversion Clock 10 85MHz (max)
(CCLK) Frequency 1 MHz (min)
f
SK
Serial Data Clock 10 85MHz (max)
SCLK Frequency 0 Hz (min)
Conversion Clock 40 40 %(min)
Duty Cycle 60 60 %(max)
Serial Data Clock 40 40 %(min)
Duty Cycle 60 60 %(max)
t
C
Conversion Time 12-Bit + Sign or 12-Bit 44(t
CK
)44(t
CK
) 44(t
CK
)(max)
5.5 8.8 µs (max)
8-Bit + Sign or 8-Bit 21(t
CK
)21(t
CK
) 21(t
CK
)(max)
2.625 4.2 µs (max)
t
A
Acquisition Time 6 Cycles Programmed 6(t
CK
)6(t
CK
) 6(t
CK
)(min)
(Note 19) 7(t
CK
) 7(t
CK
)(max)
0.75 1.2 µs (min)
0.875 1.4 µs (max)
10 Cycles Programmed 10(t
CK
)10(t
CK
) 10(t
CK
)(min)
11(t
CK
) 11(t
CK
)(max)
1.25 2.0 µs (min)
1.375 2.2 µs (max)
18 Cycles Programmed 18(t
CK
)18(t
CK
) 18(t
CK
)(min)
19(t
CK
) 19(t
CK
)(max)
2.25 3.6 µs (min)
2.375 3.8 µs (max)
34 Cycles Programmed 34(t
CK
)34(t
CK
) 34(t
CK
)(min)
35(t
CK
) 35(t
CK
)(max)
4.25 6.8 µs (min)
4.375 7.0 µs (max)
www.national.com 8
AC Electrical Characteristics (Continued)
The following specifications apply for V
+
=V
A
+=V
D
+=+5.0 V
DC
,V
REF
+=+4.096 V
DC
,V
REF
−=0V
DC
, 12-bit + sign conver-
sion mode, t
r
=t
f
=3 ns, f
CK
=f
SK
=8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
=f
SK
=5
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
S
=25Ω, source impedance for V
REF
+ and V
REF
−≤25Ω,
fully-differential input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Bold-
face limits apply for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
=25˚C. (Note 17)
Symbol Parameter Conditions Typical
(Note 10) ADC12H030/2/4/8 ADC12030/2/4/8 Units
(Limits)
Limits Limits
(Note 11) (Note 11)
t
CKAL
Self-Calibration Time 4944(t
CK
)4944(t
CK
) 4944(t
CK
)(max)
618.0 988.8 µs (max)
t
AZ
Auto-Zero Time 76(t
CK
)76(t
CK
) 76(t
CK
)(max)
9.5 15.2 µs (max)
t
SYNC
Self-Calibration 2(t
CK
)2(t
CK
) 2(t
CK
)(min)
or Auto-Zero 3(t
CK
) 3(t
CK
)(max)
Synchronization Time 0.250 0.40 µs (min)
from DOR 0.375 0.60 µs (max)
t
DOR
DOR High Time 9(t
SK
)9(t
SK
) 9(t
SK
)(max)
when CS is Low 1.125 1.8 µs (max)
Continuously for Read
Data and Software
Power Up/Down
t
CONV
CONV Valid Data Time 8(t
SK
)8(t
SK
) 8(t
SK
)(max)
1.0 1.6 µs (max)
AC Electrical Characteristics
The following specifications apply for V
+
=V
A
+=V
D
+=+5.0 V
DC
,V
REF
+=+4.096 V
DC
,V
REF
−=0V
DC
, 12-bit + sign conver-
sion mode, t
r
=t
f
=3 ns, f
CK
=f
SK
=8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
=f
SK
=5
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
S
=25Ω, source impedance for V
REF
+ and V
REF
−≤25Ω,
fully-differential input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Bold-
face limits apply for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
=25˚C. (Note 17)
Symbol Parameter Conditions Typical
(Note 10) Limits
(Note 11) Units
(Limits)
t
HPU
Hardware Power-Up Time, Time from 140 250 µs (max)
PD Falling Edge to EOC Rising Edge
t
SPU
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to 140 250 µs (max)
EOC Rising Edge
t
ACC
Access Time Delay from 20 50 ns (max)
CS Falling Edge to DO Data Valid
t
SET-UP
Set-Up Time of CS Falling Edge to 30 ns (min)
Serial Data Clock Rising Edge
t
DELAY
Delay from SCLK Falling 0 5ns (min)
Edge to CS Falling Edge
t
1H
,t
0H
Delay from CS Rising Edge to R
L
=3k, C
L
=100 pF 40 100 ns (max)
DO TRI-STATE
t
HDI
DI Hold Time from Serial Data 5 15 ns (min)
Clock Rising Edge
t
SDI
DI Set-Up Time from Serial Data 5 10 ns (min)
Clock Rising Edge
t
HDO
DO Hold Time from Serial Data R
L
=3k, C
L
=100 pF 25 50 ns (max)
Clock Falling Edge 5ns (min)
t
DDO
Delay from Serial Data Clock 35 50 ns (max)
Falling Edge to DO Data Valid
www.national.com9
AC Electrical Characteristics (Continued)
The following specifications apply for V
+
=V
A
+=V
D
+=+5.0 V
DC
,V
REF
+=+4.096 V
DC
,V
REF
−=0V
DC
, 12-bit + sign conver-
sion mode, t
r
=t
f
=3 ns, f
CK
=f
SK
=8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
=f
SK
=5
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
S
=25Ω, source impedance for V
REF
+ and V
REF
−≤25Ω,
fully-differential input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Bold-
face limits apply for T
A
=T
J
=T
MIN
to T
MAX
;all other limits T
A
=T
J
=25˚C. (Note 17)
Symbol Parameter Conditions Typical
(Note 10) Limits
(Note 11) Units
(Limits)
t
RDO
DO Rise Time, TRI-STATE to High R
L
=3k, C
L
=100 pF 10 30 ns (max)
DO Rise Time, Low to High 10 30 ns (max)
t
FDO
DO Fall Time, TRI-STATE to Low R
L
=3k, C
L
=100 pF 12 30 ns (max)
DO Fall Time, High to Low 12 30 ns (max)
t
CD
Delay from CS Falling Edge 25 45 ns (max)
to DOR Falling Edge
t
SD
Delay from Serial Data Clock Falling 25 45 ns (max)
Edge to DOR Rising Edge
C
IN
Capacitance of Logic Inputs 10 pF
C
OUT
Capacitance of Logic Outputs 20 pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN <GND or VIN >VA+orV
D
+), the current at that pin should be limited to 30 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD=(TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
TJmax =150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow:
Thermal
Part Number Resistance
θ
JA
ADC12H030CIWM, ADC12030CIWM 70˚C/W
ADC12H032CIWM, ADC12032CIWM 64˚C/W
ADC12H034CIN, ADC12034CIN 42˚C/W
ADC12H034CIWM, ADC12034CIWM 57˚C/W
ADC12H038CIWM, ADC12038CIWM 50˚C/W
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semi-
conductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND
will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55
VDC to ensure accurate conversions.
Note 8: To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V+
pin.
DS011354-2
www.national.com 10
AC Electrical Characteristics (Continued)
Note 9: With the test condition for VREF (VREF+−V
REF−) given as +4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV.
Note 10: Typicals are at TJ=TA=25˚C and represent most likely parametric norm.
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see
Figures 2, 3
).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between 1 to 0 and 0 to +1 (see
Figure 4
).
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTLlogic levels, VIL =0.4V for a falling edge and VIH =2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
Note 18: The ADC12030 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will re-
sult in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then tAis 6, 10, 18 or 34 clock periods minimum and maximum.
Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
DS011354-10
FIGURE 1. Transfer Characteristic
DS011354-11
FIGURE 2. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
www.national.com11
AC Electrical Characteristics (Continued)
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9)
DS011354-12
FIGURE 3. Simplified Error Curve vs Output Code after Auto-Calibration Cycle
DS011354-13
FIGURE 4. Offset or Zero Error Voltage
Linearity Error Change
vs Clock Frequency
DS011354-53
Linearity Error Change
vs Temperature
DS011354-54
Linearity Error Change
vs Reference Voltage
DS011354-55
www.national.com 12
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note
9) (Continued)
Linearity Error Change
vs Supply Voltage
DS011354-56
Full-Scale Error Change
vs Clock Frequency
DS011354-57
Full-Scale Error Change
vs Temperature
DS011354-58
Full-Scale Error Change
vs Reference Voltage
DS011354-59
Full-Scale Error Change
vs Supply Voltage
DS011354-60
Zero Error Change
vs Clock Frequency
DS011354-61
Zero Error Change
vs Temperature
DS011354-62
Zero Error Change
vs Reference Voltage
DS011354-63
Zero Error Change
vs Supply Voltage
DS011354-64
www.national.com13
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note
9) (Continued)
Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign
mode after auto-calibration unless otherwise specified.
Analog Supply Current
vs Temperature
DS011354-65
Digital Supply Current
vs Clock Frequency
DS011354-66
Digital Supply Current
vs Temperature
DS011354-67
Bipolar Spectral Response
with 1 kHz Sine Wave Input
DS011354-68
Bipolar Spectral Response
with 10 kHz Sine Wave Input
DS011354-69
Bipolar Spectral Response
with 20 kHz Sine Wave Input
DS011354-70
Bipolar Spectral Response
with 30 kHz Sine Wave Input
DS011354-71
Bipolar Spectral Response
with 40 kHz Sine Wave Input
DS011354-72
Bipolar Spectral Response
with 50 kHz Sine Wave Input
DS011354-73
www.national.com 14
Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign
mode after auto-calibration unless otherwise specified. (Continued)
Bipolar Spurious Free
Dynamic Range
DS011354-74
Unipolar Signal-to-Noise Ratio
vs Input Frequency
DS011354-75
Unipolar Signal-to-Noise
+ Distortion Ratio
vs Input Frequency
DS011354-76
Unipolar Signal-to-Noise
+ Distortion Ratio
vs Input Signal Level
DS011354-77
Unipolar Spectral Response
with 1 kHz Sine Wave Input
DS011354-78
Unipolar Spectral Response
with 10 kHz Sine Wave Input
DS011354-79
Unipolar Spectral Response
with 20 kHz Sine Wave Input
DS011354-80
Unipolar Spectral Response
with 30 kHz Sine Wave Input
DS011354-81
Unipolar Spectral Response
with 40 kHz Sine Wave Input
DS011354-82
www.national.com15
Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign
mode after auto-calibration unless otherwise specified. (Continued)
Test Circuits
Timing Diagrams
Unipolar Spectral Response
with 50 kHz Sine Wave Input
DS011354-83
DO “TRI-STATE” (t
1H
,t
OH
)
DS011354-3
DO except “TRI-STATE”
DS011354-4
Leakage Current
DS011354-5
DO Falling and Rising Edge
DS011354-18
DO “TRI-STATE” Falling and Rising Edge
DS011354-19
www.national.com 16
Timing Diagrams (Continued)
DI Data Input Timing
DS011354-20
DO Data Output Timing Using CS
DS011354-21
DO Data Output Timing with CS Continuously Low
DS011354-22
www.national.com17
Timing Diagrams (Continued)
ADC12038 Auto Cal or Auto Zero
DS011354-23
Note: DO output data is not valid during this cycle.
ADC12038 Read Data without Starting a Conversion Using CS
DS011354-24
www.national.com 18
Timing Diagrams (Continued)
ADC12038 Read Data without Starting a Conversion with CS Continuously Low
DS011354-25
ADC12038 Conversion Using CS with 8-Bit Digital Output Format
DS011354-26
www.national.com19
Timing Diagrams (Continued)
ADC12038 Conversion Using CS with 16-Bit Digital Output Format
DS011354-51
ADC12038 Conversion with CS Continuously Low and 8-Bit Digital Output Format
DS011354-28
www.national.com 20
Timing Diagrams (Continued)
ADC12038 Conversion with CS Continuously Low and 16-Bit Digital Output Format
DS011354-29
ADC12038 Software Power Up/Down Using CS with 16-Bit Digital Output Format
DS011354-52
www.national.com21
Timing Diagrams (Continued)
ADC12038 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format
DS011354-31
ADC12038 Hardware Power Up/Down
DS011354-32
Note: Hardware power up/down may occur at any time. If PD is high while a conversion is in progress that conversion will be corrupted and erroneous data will
be stored in the output shift register.
www.national.com 22
Timing Diagrams (Continued)
ADC12038 Configuration Modification— Example of a Status Read
DS011354-33
Note: In order for all 9 bits of Status Information to be accessible, the last conversion programmed before Cycle N needs to have a resolution of 8 bits plus
sign, 12 bits, 12 bits plus sign, or greater.
DS011354-34
FIGURE 5. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins
www.national.com23
Timing Diagrams (Continued)
Tables
TABLE 1. Data Out Formats
DO Formats DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16
with
Sign 17 X X X X Sign MSB 10 9 8 7 654321LSB
Bits
MSB 13 Sign MSB 10 9 8 7 6 5 4 3 2 1 LSB
First Bits
9 Sign MSB 6 5 4 3 2 1 LSB
Bits
17 LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign XXXX
Bits
LSB 13 LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign
First Bits
9 LSB 1 2 3 4 5 6 MSB Sign
Bits
DS011354-35
*Tantalum
**Monolithic Ceramic or better
FIGURE 6. Recommended Power Supply Bypassing and Grounding
www.national.com 24
Tables (Continued)
TABLE 1. Data Out Formats (Continued)
DO Formats DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16
without
Sign 160000MSB10987654321LSB
Bits
MSB 12 MSB 10 9 8 7 6 5 4 3 2 1 LSB
First Bits
8MSB654321LSB
Bits
16LSB12345678910MSB0000
Bits
LSB 12 LSB 1 2 3 4 5 6 7 8 9 10 MSB
First Bits
8LSB123456MSB
Bits
X=High or Low state.
TABLE 2. ADC12038 Multiplexer Addressing
Analog Channel Addressed A/D Input Multiplexer Mode
MUX and Assignment Polarity Output
Address with A/DIN1 tied to MUXOUT1 Assignment Channel
and A/DIN2 tied to MUXOUT2 Assignment
DI0 DI1 DI2 DI3 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2
LLLL + − + − CH0 CH1
L L L H + − + − CH2 CH3
L L H L + − + − CH4 CH5
L L H H + − + − CH6 CH7 Differential
L H L L − + − + CH0 CH1
LHLH − + − + CH2 CH3
L H H L − + − + CH4 CH5
L H H H − + − + CH6 CH7
H L L L + − + − CH0 COM
H L L H + − + − CH2 COM
HLHL + − + − CH4 COM
H L H H + − + − CH6 COM Single-Ended
H H L L + − + − CH1 COM
H H L H + − + − CH3 COM
H H H L + − + − CH5 COM
HHHH + − + − CH7 COM
www.national.com25
Tables (Continued)
TABLE 3. ADC12034 Multiplexer Addressing
Analog Channel Addressed A/D Input Multiplexer Mode
MUX and Assignment Polarity Output
Address with A/DIN1 tied to MUXOUT1 Assignment Channel
and A/DIN2 tied to MUXOUT2 Assignment
DI0 DI1 DI2 CH0 CH1 CH2 CH3 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2
L L L + − + − CH0 CH1
L L H + − + − CH2 CH3 Differential
L H L − + − + CH0 CH1
L H H − + − + CH2 CH3
H L L + − + − CH0 COM
H L H + − + − CH2 COM Single-Ended
H H L + − + − CH1 COM
H H H + − + − CH3 COM
TABLE 4. ADC12032 and ADC12030 Multiplexer Addressing
Analog Channel Addressed A/D Input Multiplexer Mode
MUX and Assignment Polarity Output
Address with A/DIN1 tied to MUXOUT1 Assignment Channel
and A/DIN2 tied to MUXOUT2 Assignment
DI0 DI1 CH0 CH1 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2
L L + − + − CH0 CH1 Differential
L H − + − + CH0 CH1
H L + − + − CH0 COM Single-Ended
H H + − + − CH1 COM
Note: ADC12030 and ADC12H030 do not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins.
TABLE 5. Mode Programming
ADC12038 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 Mode Selected
(Current) DO Format
(next Conversion
Cycle)
ADC12034 DI0 DI1 DI2 DI3 DI4 DI5 DI6
ADC12030
and DI0 DI1 DI2 DI3 DI4 DI5
ADC12032 See
Tables 2, 3
or
Table 4
LLLL 12BitConversion 12 or 13 Bit MSB First
See
Tables 2, 3
or
Table 4
L L L H 12 Bit Conversion 16 or 17 Bit MSB First
See
Tables 2, 3
or
Table 4
L L H L 8 Bit Conversion 8 or 9 Bit MSB First
L L L L L L H H 12 Bit Conversion of Full-Scale 12 or 13 Bit MSB First
See
Tables 2, 3
or
Table 4
L H L L 12 Bit Conversion 12 or 13 Bit LSB First
See
Tables 2, 3
or
Table 4
LHLH 12BitConversion 16 or 17 Bit LSB First
See
Tables 2, 3
or
Table 4
L H H L 8 Bit Conversion 8 or 9 Bit LSB First
L L L L L H H H 12 Bit Conversion of Offset 12 or 13 Bit LSB First
L L L L H L L L Auto Cal No Change
L L L L H L L H Auto Zero No Change
L L L L HLHL Power Up No Change
L L L L H L H H Power Down No Change
L L L L H H L L Read Status Register No Change
L L L L H H L H Data Out without Sign No Change
H L L L H H L H Data Out with Sign No Change
www.national.com 26
Tables (Continued)
TABLE 5. Mode Programming (Continued)
ADC12038 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 Mode Selected
(Current) DO Format
(next Conversion
Cycle)
ADC12034 DI0 DI1 DI2 DI3 DI4 DI5 DI6
ADC12030
and DI0 DI1 DI2 DI3 DI4 DI5
ADC12032 L L L L H H H L Acquisition Time—6 CCLK Cycles No Change
L H L L H H H L Acquisition Time—10 CCLK
Cycles No Change
H L L L H H H L Acquisition Time— 18 CCLK
Cycles No Change
H H L L H H H L Acquisition Time— 34 CCLK
Cycles No Change
L L L L HHHH User Mode No Change
H X X X HHHH Test Mode No Change
(CH1–CH7 become Active
Outputs)
Note: The A/D powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB first, and user mode.
X=Don’t Care
TABLE 6. Conversion/Read Data Only Mode Programming
CS CONV PD Mode
LLL See
Table 5
for Mode
L H L Read Only (Previous DO Format). No Conversion.
H X L Idle
X X H Power Down
X=Don’t Care
www.national.com27
Tables (Continued)
TABLE 7. Status Register
Status Bit DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8
Location
Status Bit PU PD Cal 8 or 9 12 or 13 16 or 17 Sign Justification Test Mode
Device Status DO Output Format Status
Function
“High”
indicates
a Power
Up
Sequence
is in
progress
“High”
indicates
a Power
Down
Sequence
is in
progress
“High”
indicates
an
Auto-Cal
Sequence
is in
progress
“High”
indicates
an8or9
bit format
“High”
indicates
a12or
13 bit
format
“High”
indicates
a16or
17 bit
format
“High”
indicates
that the
sign bit is
included.
When
“Low” the
sign bit is
not
included.
When
“High” the
conversion
result will
be output
MSB first.
When
“Low” the
result will
be output
LSB first.
When
“High” the
device is in
test mode.
When
“Low” the
device is in
user mode.
Application Hints
1.0 DIGITAL INTERFACE
1.1 Interface Concepts
The example in
Figure 7
shows a typical sequence of events
after the power is applied to the ADC12030/2/4/8:
The first instruction input to the A/D via DI initiates Auto Cal.
The data output on DO at that time is meaningless and is
completely random. To determine whether the Auto Cal has
been completed, a read status instruction is issued to the
A/D. Again the data output at that time has no significance
since the Auto Cal procedure modifies the data in the output
shift register. To retrieve the status information, an additional
read status instruction is issued to the A/D. At this time the
status data is available on DO. If the Cal signal in the status
word, is low Auto Cal has been completed. Therefore, the
next instruction issued can start a conversion. The data out-
put at this time is again status information. To keep noise
from corrupting the A/D conversion, status can not be read
during a conversion. If CS is strobed and is brought low dur-
ing a conversion, that conversion is prematurely ended.
EOC can be used to determine the end of a conversion or
theA/D controller can keep track in software of when it would
be appropriate to comnmunicate to the A/D again. Once it
has been determined that the A/D has completed a conver-
sion, another instruction can be transmitted to the A/D. The
data from this conversion can be accessed when the next in-
struction is issued to the A/D.
Note, when CS is low continuously it is important to transmit
the exact number of SCLK cycles, as shown in the timing
diagrams. Not doing so will desynchronize the serial commu-
nication to the A/D. (See Section 1.3.)
1.2 Changing Configuration
The configuration of the ADC12030/2/4/8 on power up de-
faults to 12-bit plus sign resolution, 12- or 13-bit MSB First,
10 CCLK acquisition time, user mode, no Auto Cal, no Auto
Zero, and power up mode. Changing the aquisition time and
turning the sign bit on and off requires an 8-bit instruction to
be issued to the ADC. This instruction will not start a conver-
sion. The instructions that select a multiplexer address and
format the output data do start a conversion.
Figure 8
de-
scribes an example of changing the configuration of the
ADC12030/2/4/8.
During I/O sequence 1, the instruction on DI configures the
ADC12030/2/4/8 to do a conversion with 12-bit +sign resolu-
tion. Notice that when the 6 CCLK Acquisition and Data Out
without Sign instructions are issued to the ADC, I/O se-
quences 2 and 3, a new conversion is not started. The data
output during these instructions is from conversion N which
was started during I/O sequence 1. The Configuration Modi-
fication timing diagram describes in detail the sequence of
events necessary for a Data Out without Sign, Data Out with
Sign, or 6/10/18/34 CCLK Acquisition time mode selection.
Table 5
describes the actual data necessary to be input to
the ADC to accomplish this configuration modification. The
next instruction, shown in
Figure 8
, issued to the A/D starts
conversion N+1 with 8 bits of resolution formatted MSB first.
Again the data output during this I/O cycle is the data from
conversion N.
The number of SCLKs applied to the A/D during any conver-
sion I/O sequence should vary in accord with the data out
word format chosen during the previous conversion I/O se-
quence. The various formats and resolutions available are
shown in
Table 1
.In
Figure 8
, since 8-bit without sign MSB
first format was chosen during I/O sequence 4, the number
of SCLKs required during I/O sequence 5 is 8. In the follow-
ing I/O sequence the format changes to 12-bit without sign
MSB first; therefore the number of SCLKs required during
I/O sequence 6 changes accordingly to 12.
DS011354-36
FIGURE 7. Typical Power Supply Power Up Sequence
www.national.com 28
Application Hints (Continued)
1.3 CS Low Continuously Considerations
When CS is continuously low, it is important to transmit the
exact number of SCLK pulses that theADC expects. Not do-
ing so will desynchronize the serial communications to the
ADC. When the supply power is first applied to the ADC, it
will expect to see 13 SCLK pulses for each I/O transmission.
The number of SCLK pulses that the ADC expects to see is
the same as the digital output word length. The digital output
word length is controlled by the Data Out (DO) format. The
DO format maybe changed any time a conversion is started
or when the sign bit is turned on or off. The table below de-
tails out the number of clock periods required for different
DO formats:
Number of
DO Format SCLKs
Expected
8-Bit MSB or LSB First SIGN OFF 8
SIGN ON 9
12-Bit MSB or LSB First SIGN OFF 12
SIGN ON 13
16-Bit MSB or LSB first SIGN OFF 16
SIGN ON 17
If erroneous SCLK pulses desynchronize the communica-
tions, the simplest way to recover is by cycling the power
supply to the device. Not being able to easily resynchronize
the device is a shortcoming of leaving CS low continuously.
The number of clock pulses required for an I/O exchange
may be different for the case when CS is left low continu-
ously vs the case when CS is cycled. Take the I/O sequence
detailed in
Figure 7
(Typical Power Supply Sequence) as an
example. The table below lists the number of SCLK pulses
required for each instruction:
Instruction CS Low CS Strobed
Continuously
Auto Cal 13 SCLKs 8 SCLKs
Read Status 13 SCLKs 8 SCLKs
Read Status 13 SCLKs 8 SCLKs
12-Bit + Sign Conv 1 13 SCLKs 8 SCLKs
12-Bit + Sign Conv 2 13 SCLKs 13 SCLKs
1.4 Analog Input Channel Selection
The data input on DI also selects the channel configuration
for a particular A/D conversion (see
Tables 2, 3, 4
and
Table
5
). In
Figure 8
the only times when the channel configuration
could be modified would be during I/O sequences 1, 4, 5 and
6. Input channels are reselected before the start of each new
conversion. Shown below is the data bit stream required on
DI, during I/O sequence number 4 in
Figure 8
, to set CH1 as
the positive input and CH0 as the negative input for the dif-
ferent versions of ADCs:
Part DI Data
Number DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
ADC12H030 LHLLHLXX
ADC12030
ADC12H032 LHLLHLXX
ADC12032
ADC12H034 LHLLLHLX
ADC12034
ADC12H038 LHLLLLHL
ADC12038
Where X can be a logic high (H) or low (L).
1.5 Power Up/Down
The ADC may be powered down at any time by taking the
PD pin HIGH or by the instruction input on DI (see
Tables 5,
6
, and the Power Up/Down timing diagrams). When theADC
is powered down in this way, the circuitry necessary for an
A/D conversion is deactivated. The circuitry necessary for
digital I/O is kept active. Hardware power up/down is con-
trolled by the state of the PD pin. Software power-up/down is
controlled by the instruction issued to the ADC. If a software
power up instruction is issued to the ADC while a hardware
power down is in effect (PD pin high) the device will remain
in the power-down state. If a software power down instruc-
tion is issued to the ADC while a hardware power up is in ef-
fect (PD pin low), the device will power down. When the de-
vice is powered down by software, it may be powered up by
either issuing a software power up instruction or by taking
PD pin high and then low. If the power down command is is-
sued during an A/D conversion, that conversion is disrupted.
Therefore, the data output after power up cannot be relied
upon.
DS011354-37
FIGURE 8. Changing the ADC’s Conversion Configuration
www.national.com29
Application Hints (Continued)
1.6 User Mode and Test Mode
An instruction may be issued to the ADC to put it into test
mode. Test mode is used by the manufacturer to verify com-
plete functionality of the device. During test mode CH0–CH7
become active outputs. If the device is inadvertently put into
the test mode with CS continuously low, the serial communi-
cations may be desynchronized. Synchronization may be re-
gained by cycling the power supply voltage to the device.
Cycling the power supply voltage will also set the device into
user mode. If CS is used in the serial interface, theADC may
be queried to see what mode it is in. This is done by issuing
a “read STATUS register” instruction to the ADC. When bit 9
of the status register is high, the ADC is in test mode; when
bit 9 is low the ADC, is in user mode. As an alternative to cy-
cling the power supply, an instruction sequence may be used
to return the device to user mode. This instruction sequence
must be issued to theADC using CS. The following table lists
the instructions required to return the device to user mode:
Instruction DI Data
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
TEST
MODE HXXXHHHH
Reset
Test Mode
Instructions
LLLLHHHL
LLLLHLHL
LLLLHLHH
USER
MODE LLLLHHHH
Power Up LLLLHLHL
Set DO with H
or without or L L L H H L H
Sign L
Set H H
Acquisition or or L L H H H L
Time L L
Start HHHH HHH
a orororor Lororor
Conversion LLLL LLL
X
=
Don’t Care
After returning to user mode with the user mode instruction
the power up, data with or without sign, and acquisition time
instructions need to be resent to ensure that the ADC is in
the required state before a conversion is started.
1.7 Reading the Data Without Starting a Conversion
The data from a particular conversion may be accessed
without starting a new conversion by ensuring that the
CONV line is taken high during the I/O sequence. See the
Read Data timing diagrams.
Table 6
describes the operation
of the CONV pin.
2.0 DESCRIPTION OF THE ANALOG MULTIPLEXER
For the ADC12038, the analog input multiplexer can be con-
figured with 4 differential channels or 8 single ended chan-
nels with the COM input as the zero reference or any combi-
nation thereof (see
Figure 9
). The difference between the
voltages on the V
REF+
and V
REF−
pins determines the input
voltage span (V
REF
). The analog input voltage range is 0 to
V
A+
. Negative digital output codes result when V
IN−
>V
IN+
.
The actual voltage at V
IN−
or V
IN+
cannot go below AGND.
CH0, CH2, CH4, and CH6 can be assigned to the MUX-
OUT1 pin in the differential configuration, while CH1, CH3,
CH5, and CH7 can be assigned to the MUXOUT2 pin. In the
differential configuration, the analog inputs are paired as fol-
lows: CH0 with CH1, CH2 with CH3, CH4 with CH5 and CH6
with CH7. The A/DIN1 and A/DIN2 pins can be assigned
positive or negative polarity.
With the single-ended multiplexer configuration CH0 through
CH7 can be assigned to the MUXOUT1 pin. The COM pin is
always assigned to the MUXOUT2 pin. A/DIN1 is assigned
as the positve input; A/DIN2 is assigned as the negative in-
put. (See
Figure 10
).
4 Differential
Channels
DS011354-38
8 Single-Ended Channels
with COM
as Zero Reference
DS011354-39
FIGURE 9.
www.national.com 30
Application Hints (Continued)
The Multiplexer assignment tables for the ADC12030,2,4,8
(
Tables 2, 3, 4
) summarize the aforementioned functions for
the different versions of A/Ds.
2.1 Biasing for Various Multiplexer Configurations
Figure 11
is an example of biasing the device for
single-ended operation. The sign bit is always low. The digi-
tal output range is 0 0000 0000 0000 to 0 1111 1111 1111.
One LSB is equal to 1 mV (4.1V/4096 LSBs).
For pseudo-differential signed operation, the biasing circuit
shown in
Figure 12
shows a signal AC coupled to the ADC.
This gives a digital output range of −4096 to +4095. With a
2.5V reference, as shown, 1 LSB is equal to 610 µV. Al-
though, the ADC is not production tested with a 2.5V refer-
ence, linearity error typically will not change more than 0.1
LSB (see the curves in the Typical Electrical Characteristics
Section). With the ADC set to an acquisition time of 10 clock
periods, the input biasing resistor needs to be 600Ωor less.
Notice though that the input coupling capacitor needs to be
made fairly large to bring down the high pass corner. In-
creasing the acquisition time to 34 clock periods (with a
5 MHz CCLK frequency) would allow the 600Ωto increase to
6k, which with a 1 µF coupling capacitor would set the high
pass corner at 26 Hz. Increasing R, to 6k would allow R
2
to
be 2k.
Differential
Configuration
DS011354-40
A/DIN1 and A/DIN2 can be assigned as the + or − input
Single-Ended
Configuration
DS011354-41
A/DIN1 is + input
A/DIN2 is − input
FIGURE 10.
DS011354-46
FIGURE 11. Single-Ended Biasing
www.national.com31
Application Hints (Continued)
An alternative method for biasing pseudo-differential opera-
tion is to use the +2.5V from the LM4040 to bias any ampli-
fier circuits driving theADC as shown in
Figure 13
. The value
of the resistor pull-up biasing the LM4040-2.5 will depend
upon the current required by the op amp biasing circuitry.
In the circuit of
Figure 13
some voltage range is lost since
the amplifier will not be able to swing to +5V and GND with
a single +5V supply. Using an adjustable version of the
LM4041 to set the full scale voltage at exactly 2.048V and a
lower grade LM4040D-2.5 to bias up everything to 2.5V as
shown in
Figure 14
will allow the use of all the ADC’s digital
output range of −4096 to +4095 while leaving plenty of head
room for the amplifier.
Fully differential operation is shown in
Figure 15
. One LSB
for this case is equal to (4.1V/4096) =1mV.
DS011354-47
FIGURE 12. Pseudo-Differential Biasing with the Signal Source AC Coupled Directly into the ADC
DS011354-48
FIGURE 13. Alternative Pseudo-Differential Biasing
www.national.com 32
Application Hints (Continued)
3.0 REFERENCE VOLTAGE
The difference in the voltages applied to the V
REF+
and
V
REF−
defines the analog input span (the difference between
the voltage applied between two multiplexer inputs or the
voltage applied to one of the multiplexer inputs and analog
ground), over which 4095 positive and 4096 negative codes
exist. The voltage sources driving V
REF+
or V
REF−
must have
very low output impedance and noise. The circuit in
Figure
16
is an example of a very stable reference appropriate for
use with the device.
DS011354-49
FIGURE 14. Pseudo-Differential Biasing without the Loss of Digital Output Range
DS011354-50
FIGURE 15. Fully Differential Biasing
www.national.com33
Application Hints (Continued)
TheADC 12030/2/4/8 can be used in either ratiometric or ab-
solute reference applications. In ratiometric systems, the
analog input voltage is proportional to the voltage used for
the ADC’s reference voltage. When this voltage is the sys-
tem power supply, the V
REF+
pin is connected to V
A+
and
V
REF−
is connected to ground. This technique relaxes the
system reference stability requirements because the analog
input voltage and the ADC reference voltage move together.
This maintains the same output code for given input condi-
tions. For absolute accuracy, where the analog input voltage
varies between very specific voltage limits, a time and tem-
perature stable voltage source can be connected to the ref-
erence inputs. Typically, the reference voltage’s magnitude
will require an initial adjustment to null reference voltage in-
duced full-scale errors.
Below are recommended references along with some key
specifications.
Output Temperature
Part Number Voltage Coefficient
Tolerance
LM4041CI-Adj ±0.5%±100ppm/˚C
LM4040AI-4.1 ±0.1%±100ppm/˚C
Circuit of
Figure 16
Adjustable ±2ppm/˚C
The reference voltage inputs are not fully differential. The
ADC12030/2/4/8 will not generate correct conversions or
comparisons if V
REF+
is taken below V
REF−
. Correct conver-
sions result when V
REF+
and V
REF−
differ by 1V and remain,
at all times, between ground and V
A+
. The V
REF
common
mode range, (V
REF+
+V
REF−
)/2 is restricted to (0.1 x V
A+
)to
(0.6 x V
A+
). Therefore, with V
A+
=5V the center of the refer-
ence ladder should not go below 0.5V or above 3.0V.
Figure
17
is a graphic representation of the voltage restrictions on
V
REF+
and V
REF−
.
4.0 ANALOG INPUT VOLTAGE RANGE
The ADC12030/2/4/8’s fully differential ADC generate a
two’s complement output that is found by using the equa-
tions shown below:
for (12-bit) resolution the Output Code =
for (8-bit) resolution the Output Code =
Round off to the nearest integer value between −4096 to
4095 for 12-bit resolution and between −256 to 255 for 8-bit
resolution if the result of the above equation is not a whole
number.
Examples are shown in the table below:
Digital
V
REF+
V
REF−
V
IN+
V
IN−
Output
Code
+2.5V +1V +1.5V 0V 0,1111,1111,1111
+4.096V 0V +3V 0V 0,1011,1011,1000
+4.096V 0V +2.499V +2.500V 1,1111,1111,1111
+4.096V 0V 0V +4.096V 1,0000,0000,0000
5.0 INPUT CURRENT
At the start of the acquisition window (t
A
) a charging current
flows into or out of the analog input pins (A/DIN1 and
A/DIN2) depending on the input voltage polarity. The analog
input pins are CH0–CH7 and COM when A/DIN1 is tied to
MUXOUT1 andA/DIN2 is tied to MUXOUT2. The peak value
of this input current will depend on the actual input voltage
applied, the source impedance and the internal multiplexer
switch on resistance. With MUXOUT1 tied to A/DIN1 and
DS011354-42
*Tantalum
FIGURE 16. Low Drift Extremely
Stable Reference Circuit
DS011354-45
FIGURE 17. V
REF
Operating Range
www.national.com 34
Application Hints (Continued)
MUXOUT2 tied to A/DIN2 the internal multiplexer switch on
resistance is typically 1.6 kΩ. The A/DIN1 and A/DIN2 mux
on resistance is typically 750Ω.
6.0 INPUT SOURCE RESISTANCE
For low impedance voltage sources (<600Ω), the input
charging current will decay, before the end of the S/H’s ac-
quisition time of 2 µs (10 CCLK periods with f
C
=5 MHz), to
a value that will not introduce any conversion errors. For high
source impedances, the S/H’s acquisition time can be in-
creased to 18 or 34 CCLK periods. For less ADC resolution
and/or slower CCLK frequencies the S/H’s acquisition time
may be decreased to 6 CCLK periods. To determine the
number of clock periods (N
c
) required for the acquisition time
with a specific source impedance for the various resolutions
the following equations can be used:
12 Bit + Sign
N
C
=[
R
S
+ 2.3] x
f
C
x 0.824
8 Bit + Sign
N
C
=[
R
S
+ 2.3] x
f
C
x 0.57
Where f
C
is the conversion clock (CCLK) frequency in MHz
and R
S
is the external source resistance in kΩ.Asanex-
ample, operating with a resolution of 12 Bits+sign,a5MHz
clock frequency and maximum acquistion time of 34 conver-
sion clock periods the ADC’s analog inputs can handle a
source impedance as high as 6 kΩ. The acquisition time may
also be extended to compensate for the settling or response
time of external circuitry connected between the MUXOUT
and A/DIN pins.
The acquisition time t
A
is started by a falling edge of SCLK
and ended by a rising edge of CCLK (see timing diagrams).
If SCLK and CCLK are asynchronous one extra CCLK clock
period may be inserted into the programmed acquisition time
for synchronization. Therefore with asnychronous SCLK and
CCLKs the acquisition time will change from conversion to
conversion.
7.0 INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF–0.1 µF) can be connected be-
tween the analog input pins, CH0–CH7, and analog ground
to filter any noise caused by inductive pickup associated with
long input leads. These capacitors will not degrade the con-
version accuracy.
8.0 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion er-
rors. Input filtering can be used to reduce the effects of the
noise sources.
9.0 POWER SUPPLIES
Noise spikes on the V
A+
and V
D+
supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. The
minimum power supply bypassing capacitors recommended
are low inductance tantalum capacitors of 10 µF or greater
paralleled with 0.1 µF monolithic ceramic capacitors. More or
different bypassing may be necessary depending on the
overall system requirements. Separate bypass capacitors
should be used for the V
A+
and V
D+
supplies and placed as
close as possible to these pins.
10.0 GROUNDING
The ADC12030/2/4/8’s performance can be maximized
through proper grounding techniques. These include the use
of separate analog and digital ground planes. The digital
ground plane is placed under all components that handle
digital signals, while the analog ground plane is placed under
all components that handle analog signals. The digital and
analog ground planes are connected together at only one
point, either the power supply ground or at the pins of the
ADC. This greatly reduces the occurence of ground loops
and noise.
Shown in
Figure 18
is the ideal ground plane layout for the
ADC12038 along with ideal placement of the bypass capaci-
tors. The circuit board layout shown in
Figure 18
uses three
bypass capacitors: 0.01 µF (C1) and 0.1 µF (C2) surface
mount capacitors and 10 µF (C3) tantalum capacitor.
www.national.com35
Application Hints (Continued)
11.0 CLOCK SIGNAL LINE ISOLATION
The ADC12030/2/4/8’s performance is optimized by routing
the analog input/output and reference signal conductors as
far as possible from the conductors that carry the clock sig-
nals to the CCLK and SCLK pins. Ground traces parallel to
the clock signal traces can be used on printed circuit boards
to reduce clock signal interference on the analog input/
output pins.
12.0 THE CALIBRATION CYCLE
A calibration cycle needs to be started after the power sup-
plies, reference, and clock have been given enough time to
stabilize after initial turn-on. During the calibration cycle, cor-
rection values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall full-scale,
offset, and linearity errors down to the specified limits.
Full-scale error typically changes ±0.4 LSB over tempera-
ture and linearity error changes even less; therefore it should
be necessary to go through the calibration cycle only once
after power up if the Power Supply Voltage and the ambient
temperature do not change significantly (see the curves in
the Typical Performance Characteristics).
13.0 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of theA/D,
the auto-zero cycle can be used. It may be necessary to do
an auto-zero cycle whenever the ambient temperature or the
power supply voltage change significantly. (See the curves
titled “Zero Error Change vs Ambient Temperature” and
“Zero Error Change vs Supply Voltage” in the Typical Perfor-
mance Characteristics.)
14.0 DYNAMIC PERFORMANCE
Many applications require the A/D converter to digitize AC
signals, but the standard DC integral and differential nonlin-
earity specifications will not accurately predict the A/D con-
verter’s performance with AC input signals. The important
specifications for AC applications reflect the converter’s abil-
ity to digitize AC signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
characteristics such as signal-to-noise (S/N), signal-tonoise
+ distortion ratio (S/(N + D)), effective bits, full power band-
width, aperture time and aperture jitter are quantitative mea-
sures of the A/D converter’s capability.
An A/D converter’s AC performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal wave-
form is applied to the A/D converter’s input, and the trans-
form is then performed on the digitized waveform. S/(N + D)
and S/N are calculated from the resulting FFT data, and a
spectral plot may also be obtained. Typical values for S/N
are shown in the table of Electrical Characteristics, and
spectral plots of S/(N + D) are included in the typical perfor-
mance curves.
The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can be
seen in the S/(N + D) versus frequency curves. These curves
will also give an indication of the full power bandwidth (the
frequency at which the S/(N + D) or S/N drops 3 dB).
Effective number of bits can also be useful in describing the
A/D’s noise performance. An ideal A/D converter will have
some amount of quantization noise, determined by its reso-
lution, which will yield an optimum S/N ratio given by the fol-
lowing equation:S/N =(6.02xn+1.76) dB
where n is the A/D’s resolution in bits.
The effective bits of a real A/D converter, therefore, can be
found by:
As an example, this device with a differential signed 5V,
10 kHz sine wave input signal will typically have a S/N of
78 dB, which is equivalent to 12.6 effective bits.
DS011354-43
FIGURE 18. Ideal Ground Plane
www.national.com 36
Application Hints (Continued)
15.0 AN RS232 SERIAL INTERFACE
Shown on the following page is a schematic for an RS232 in-
terface to any IBM and compatible PCs. The DTR, RTS, and
CTS RS232 signal lines are buffered via level translators
and connected to the ADC12038’s DI, SCLK, and DO pins,
respectively. The D flip flop drives the CS control line.
The assignment of the RS232 port is shown below
B7 B6 B5 B4 B3 B2 B1 B0
COM1 Input Address 3FE X X X CTS X X X X
Output Address 3FC X X X 0 X X RTS DTR
Asample program, written in Microsoft QuickBasic, is shown
on the next page. The program prompts for data mode select
instruction to be sent to the A/D. This can be found from the
Mode Programming table shown earlier. The data should be
entered in “1”s and “0”s as shown in the table with DI0 first.
Next the program prompts for the number of SCLKs required
for the programmed mode select instruction. For instance, to
send all “0”s to the A/D, selects CH0 as the +input, CH1 as
the −input, 12-bit conversion, and 13-bit MSB first data out-
put format (if the sign bit was not turned off by a previous in-
struction). This would require 13 SCLK periods since the out-
put data format is 13 bits. The part powers up with No Auto
Cal, NoAuto Zero, 10 CCLK Acquisition Time, 12-bit conver-
sion, data out with sign, power up, 12- or 13-bit MSB first,
and user mode. Auto Cal, Auto Zero, Power Up and Power
Down instructions do not change these default settings. The
following power up sequence should be followed:
1. Run the program
2. Prior to responding to the prompt apply the power to the
ADC12038
3. Respond to the program prompts
It is recommended that the first instruction issued to the
ADC12038 be Auto Cal (see Section 1.1).
DS011354-44
Note: VA+,V
D
+
, and VREF+on the ADC12038 each have 0.01 µF and 0.1 µF chip caps, and 10 µF tantalum caps. All logic devices are bypassed with 0.1 µF
caps.
www.national.com37
Application Hints (Continued)
’variables DOL=Data Out word length, DI=Data string for A/D DI input,
’DO
=
A/D result string
’SET CS# HIGH
OUT <&amp>H3FC, (<&amp>H2 OR INP (<&amp>H3FC)) ’set RTS HIGH
OUT <&amp>H3FC, (<&amp>HFE AND INP(<&amp>H3FC)) ’set DTR LOW
OUT <&amp>H3FC, (<&amp>HFD AND INP(<&amp>H3FC)) ’set RTS LOW
OUT <&amp>H3FC, (<&amp>HEF AND INP(<&amp>H3FC)) ’set B4 low
10
LINE INPUT <&ldquo>DI data for ADC12038 (see Mode Table on data sheet)<&rdquo>; DI$
INPUT <&ldquo>ADC12038 output word length (8,9,12,13,16 or 17)<&rdquo>; DOL
20
’SET CS# HIGH
OUT <&amp>H3FC, (<&amp>H2 OR INP (<&amp>H3FC)) ’set RTS HIGH
OUT <&amp>H3FC, (<&amp>HFE AND INP(<&amp>H3FC)) ’set DTR LOW
OUT <&amp>H3FC, (<&amp>HFD AND INP(<&amp>H3FC)) ’set RTS LOW
’SET CS# LOW
OUT <&amp>H3FC, (<&amp>H2 OR INP (<&amp>H3FC)) ’set RTS HIGH
OUT <&amp>H3FC, (<&amp>H1 OR INP(<&amp>H3FC)) ’set DTR HIGH
OUT <&amp>H3FC, (<&amp>HFD AND INP(<&amp>H3FC)) ’set RTS LOW
DO$=<&ldquo> <&rdquo> ’reset DO variable
OUT <&amp>H3FC, (<&amp>H1 OR INP(<&amp>H3FC)) ’SET DTR HIGH
OUT <&amp>H3FC, (<&amp>HFD AND INP(<&amp>H3FC)) ’SCLK low
FOR N=1TO8
Temp$=MID$(DI$,N,1)
IF Temp$=<&ldquo>0<&rdquo> THEN
OUT <&amp>H3FC,(<&amp>H1 OR INP(<&amp>H3FC))
ELSE OUT <&amp>H3FC, (<&amp>HFE AND INP(<&amp>H3FC))
END IF ’out DI
OUT <&amp>H3FC, (<&amp>H2 OR INP(<&amp>H3FC)) ’SCLK high
IF (INP(<&amp>H3FE) AND 16)=16 THEN
DO$=DO$+<&ldquo>0<&rdquo>
ELSE
DO$=DO$+<&ldquo>1<&rdquo>
END IF ’input DO
OUT <&amp>H3FC, (<&amp>H1 OR INP(<&amp>H3FC)) ’SET DTR HIGH
OUT <&amp>H3FC, (<&amp>HFD AND INP(<&amp>H3FC)) ’SCLK low
NEXT N
IF DOL>8 THEN
FOR N=9TODOL
OUT <&amp>H3FC, (<&amp>H1 OR INP(<&amp>H3FC)) ’SET DTR HIGH
OUT <&amp>H3FC, (<&amp>HFD AND INP(<&amp>H3FC)) ’SCLK low
OUT <&amp>H3FC, (<&amp>H2 OR INP(<&amp>H3FC)) ’SCLK high
IF (INP(<&amp>H3FE) AND <&amp>H10)=<&amp>H10 THEN
DO$=DO$+<&ldquo>0<&rdquo>
ELSE
DO$=DO$+<&ldquo>1<&rdquo>
END IF
NEXT N
END IF
OUT <&amp>H3FC, (<&amp>HFA AND INP(<&amp>H3FC)) ’SCLK low and DI high
FOR N=1TO500
NEXT N
PRINT DO$
INPUT <&ldquo>Enter <&ldquo>C<&rdquo> to convert else <&ldquo>RETURN<&rdquo> to alter DI
data<&rdquo>; s$
IF s$=<&ldquo>C<&rdquo> OR s$=<&ldquo>c<&rdquo> THEN
GOTO 20
ELSE
GOTO 10
END IF
END
www.national.com 38
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number ADC12030CIWM or ADC12H030CIWM
NS Package Number M16B
Order Number ADC12032CIWM or ADC12H032CIWM
NS Package Number M20B
www.national.com39
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number ADC12034CIWM or ADC12H034CIWM
NS Package Number M24B
Order Number ADC12038CIWM or ADC12H038CIWM
NS Package Number M28B
www.national.com 40
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
www.national.com
Order Number ADC12034CIN or ADC12H034CIN
NS Package Number N24C
ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.