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19-5504; Rev 6/13
FEATURES
Integrated NV SRAM, Real-Time Clock
(RTC), Crystal, Power-Fail Control
Circuit, and Lithium Energy Source
Clock Registers are Accessed Identically to
the Static RAM. These Registers are
Resident in the Eight Top RAM Locations
Century Byte Register (Y2K Compliant)
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
Up to the Year 2100
Battery Voltage-Level Indicator Flag
Power-Fail Write Protection Allows for
±10% VCC Power-Supply Tolerance
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
DIP Module Only:
Standard JEDEC Byte-Wide 512k x 8 Static
RAM Pinout
PowerCap Module Board Only:
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
of DS174xP Timekeeping RAM
Also Available in Industrial Temperature
Range: -40°C to +85°C
PIN CONFIGURATIONS
DS1747/DS1747P
Y2K-
Compliant, Nonvolatile Timekeeping RAMs
A17
A18
13
1
2
3
4
5
6
7
8
9
10
11
12
14
31
Encapsulated DIP
(512k x 8)
VCC
A15
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
DQ2
15
16
18
17
DQ4
DQ3
Maxim
DS1747
1
N.C.
2
3
A15
A16
RST
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A17
A14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
A18
X1
GND
V
BAT
X2
PowerCap Module Board
(Uses DS9034PCX+ or DS9034I-PCX+ PowerCap)
Maxim
DS1747P
TOP VIEW
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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PIN DESCRIPTION
PIN
NAME FUNCTION
EDIP
PowerCap
1
34
A18
Address Input
2
3
A16
3
32
A14
4
30
A12
5
25
A7
6
24
A6
7
23
A5
8
22
A4
9
21
A3
10
20
A2
11
19
A1
12
18
A0
23
28
A10
25
29
A11
26
27
A9
27
26
A8
28
31
A13
30
33
A17
31
2
A15
13
16
DQ0
Data Input/Output
14
15
DQ1
15
14
DQ2
17
13
DQ3
18
12
DQ4
19
11
DQ5
20
10
DQ6
21
9
DQ7
16
17
GND
Ground
22
8
CE
Active-Low Chip-Enable Input
24
7
OE
Active-Low Output-Enable Input
29
6
WE
Active-Low Write-Enable Input
32
5
VCC
Power-Supply Input
—
1
N.C.
No Connection
—
4
RST
Active-Low Power-On Reset Output
—
(See Pin
Configuration)
X1, X2 Crystal Input, Output Connections
—
(See Pin
Configuration)
VBAT Battery Connection
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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ORDERING INFORMATION
PART
SUPPLY
VOLTAGE
(V)
TEMP RANGE PIN-PACKAGE TOP MARK†
DS1747-70+
5.0
0°C to +70°C
32 EDIP (0.740a)
DS1747-70+
DS1747-70IND+
5.0
-40°C to +85°C
32 EDIP (0.740a)
DS1747-70IND+
DS1747P-70+
5.0
0°C to +70°C
34 PowerCap*
DS1747P+70
DS1747P-70IND+
5.0
-40°C to +85°C
34 PowerCap*
DS1747P+70 IND
DS1747W-120+
3.3
0°C to +70°C
32 EDIP (0.740a)
DS1747W-120+
DS1747W-120IND+
3.3
-40°C to +85°C
32 EDIP (0.740a)
DS1747W-120IND+
DS1747WP-120+
3.3
0°C to +70°C
34 PowerCap*
DS1747WP+120
DS1747WP-120IND+
3.3
-40°C to +85°C
34 PowerCap*
DS1747WP+120 IND
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PCX+ or DS9034I-PCX+ required (must be ordered separately).
†A “+” indicates lead(Pb)-free. The top mark will include a “+” symbol on lead(Pb)-free devices.
DESCRIPTION
The DS1747 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and
512k x 8 nonvolatile static RAM. User access to all registers within the DS1747 is accomplished with a
byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight
uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes,
and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for the date of each month
and leap year are made automatically. The RTC clock registers are double buffered to avoid access of
incorrect data that can occur during clock update cycles. The double-buffered system also prevents time
loss as the timekeeping countdown continues unabated by access to time register data. The DS1747 also
contains its own power-fail circuitry that deselects the device when the VCC supply is in an out-of-
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on
by low VCC as errant access and update cycles are avoided.
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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Figure 1. Block Diagram
PACKAGES
The DS1747 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap
(DS9034PCX) that contains the crystal and battery. This design allows the Power-Cap to be mounted on
top of the DS1747P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to the high temperatures required
for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board
and PowerCap are ordered separately and shipped in separate containers.
TIME AND DATE OPERATIONS
The contents of the time and date registers are in BCD format. The day-of-week register increments at
midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined
operation.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal
updates to the DS1747 clock registers should be halted before clock data is read to prevent reading of
data in transition. However, halting the internal clock register updating process does not affect clock
accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register (see
Table 2). As long as a one remains in that position, updating is halted. After a halt is issued, the registers
reflect the count, that is day, date, and time that was current at the moment the halt command was
issued. However, the internal clock registers of the double-buffered system continue to update so that
the clock accuracy is not affected by the access of data. All the DS1747 registers are updated
simultaneously after the internal clock register updating process has been re-enabled. Updating is within
a second after the read bit is written to zero. The READ bit must be set to a zero for a minimum of
500µs to ensure the external registers will be updated.
Maxim
DS1747
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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Table 1. Truth Table
VCC
CE
OE
WE
MODE DQ POWER
VCC>VPF
VIH
X
X
Deselect
High-Z
Standby
VIL
X
VIL
Write
Data In
Active
VIL
VIL
VIH
Read
Data Out
Active
VIL
VIH
VIH
Read
High-Z
Active
VSO<VCC<VPF
X
X
X
Deselect
High-Z
CMOS Standby
VCC<VSO<VPF X X X Deselect High-Z
Data-Retention
Mode
SETTING THE CLOCK
As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates
to the device registers. The user can subsequently load correct date and time values into all eight registers,
followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new settings
into the clock, allowing timekeeping operations to resume from the new set point.
Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts
updates to the device registers. The user can subsequently read the date and time values from the eight
registers without those contents possibly changing during those I/O operations. A subsequent write cycle
of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the
previous set point.
The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a
write cycle to Control if either the W or R bits are being set to 1 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write
cycle to Control if the W bit is being cleared to 0 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by a write
cycle to Control if the R bit is being cleared to 0 in that write operation.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned
off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers,
see Table 2. Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1747 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The RTC is
calibrated at the factory by Maxim using nonvolatile tuning elements, and does not require additional
calibration. For this reason, methods of field clock calibration are not available and not necessary. The
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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electrical environment also affects the clock accuracy, and caution should be taken to place the RTC in
the lowest-level EMI section of the PC board layout. For additional information, refer to Application
Note 58.
CLOCK ACCURACY (PowerCap MODULE)
The DS1747 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module typically keeps time accuracy to within ±1.53 minutes per month (35 ppm) at +25°C. Clock
accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest-level EMI section of the PC board layout. For additional information, refer to Application
Note 58.
Table 2. Register Map
ADDRESS
DATA
FUNCTION RANGE
B7
B6
B5
B4
B3
B2
B1
B0
7FFFF
10 Year
Year
Year
00-99
7FFFE
X
X
X
10 Month
Month
Month
01-12
7FFFD
X
X
10 Date
Date
Date
01-31
7FFFC
BF
FT
X
X
X
Day
Day
01-07
7FFFB
X
X
10 Hour
Hour
Hour
00-23
7FFFA
X
10 Minutes
Minutes
Minutes
00-59
7FFF9
OSC
10 Seconds
Seconds
Seconds
00-59
7FFF8
W
R
10 Century
Century
Century
00-39
OSC
= Stop Bit
R = Read Bit
FT = Frequency Test
W = Write Bit
X = See Note
BF = Battery Flag
Note:
All indicated “X” bits are unused, but must be set to “0” during write cycles to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1747 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip-enable access (tCEA) or at output enable
access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the
outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1747 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE
will then disable the output tWEZ after WE goes active.
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power failing point, VPF, (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time the power fail reset output
signal (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned
to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is
greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. At
this time the power fail reset output signal (RST) is driven active and will remain active until VCC returns
to nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply
(VBAT) when VCC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to
the backup supply (VBAT) when VCC drops below VSO. RTC operation and SRAM data are maintained
from the battery until VCC is returned to nominal levels. The RST signal is an open drain output and
requires a pull up. Except for the RST, all control, data, and address signals must be powered down
when VCC is powered down.
BATTERY LONGEVITY
The DS1747 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1747 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running
in the absence of VCC power. Each DS1747 is shipped from Maxim with its lithium energy source
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the
lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1747 will
be much longer than 10 years since no lithium battery energy is consumed when VCC is present.
BATTERY MONITOR
The DS1747 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7)
of the day register is used to indicate the voltage level range of the battery. This bit is not writable and
should always be a one when read. If a zero is ever present, an exhausted lithium energy source is
indicated and both the contents of the RTC and RAM are questionable.
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
5.5V Version………………………………………………………………………………………….-0.3V to +6.0V
3.3V Version.…………………………………………………………………………………………-0.3V to +4.6V
Operating Temperature Range (Noncondensing)
Commercial...……………………………………….......................................................................0°C to +70°C
Industrial……………………………………………………..……………………………………….-40°C to +85°C
Storage Temperature Range
EDIP .......................………………………………………………………………………………...-40°C to +85°C
PowerCap ........................................................................................................................... -55°C to +125°C
Lead Temperature (soldering, 10s)..........................……………………….………….…………………………...+260°C
Note: EDIP is hand or wave-soldered only.
Soldering Temperature (reflow, PowerCap) .................................................................................................. +260°C
This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device
reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = Over the Operating Range)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 Voltage
All Inputs
V
CC
=
5V±10%
VIH 2.2
V
CC
+
0.3V
V 1
V
CC
=
3.3V±10%
VIH 2.0
V
CC
+
0.3V
V 1
Logic 0 Voltage
All Inputs
V
CC
=
5V±10%
VIL -0.3 +0.8 V 1
V
CC
=
3.3V±10%
VIL -0.3 +0.6 V 1
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current
Icc
85
mA
2, 3, 10
TTL Standby Current
(
CE
= VIH)
Icc1 6 mA 2, 3
CMOS Standby Current
(
CE
≥ VCC - 0.2V)
Icc2 4 mA 2, 3
Input Leakage Current
(Any Input)
IIL -1 +1 µA
Output Leakage Current
(Any Output)
IOL -1 +1 µA
Output Logic 1 Voltage
(IOUT = -1.0mA)
VOH 2.4 1
Output Logic 0 Voltage
(IOUT = +2.1mA)
VOL 0.4 1
Write Protection Voltage VPF 4.25 4.50 V 1
Battery Switchover Voltage VSO VBAT 1, 4
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Active Supply Current Icc 30 mA 2, 3, 10
TTL Standby Current
(
CE
= VIH)
Icc1 2 mA 2, 3
CMOS Standby Current
(
CE
≥ VCC - 0.2V)
Icc2 2 mA 2, 3
Input Leakage Current
(Any Input)
IIL -1 +1 µA
Output Leakage Current
(Any Output)
IOL -1 +1 µA
Output Logic 1 Voltage
(IOUT = -1.0mA)
VOH 2.4 1
Output Logic 0 Voltage
(IOUT = +2.1mA)
VOL 0.4 1
Write Protection Voltage VPF 2.80 2.97 V 1
Battery Switchover Voltage VSO
V
BAT
or
VPF
V 1, 4
AC CHARACTERISTICS—READ CYCLE (5V)
(VCC = 5.0V ±10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time
tRC 70 ns
Address Access Time
tAA 70 ns
CE
to DQ Low-Z
tCEL 5 ns
CE
Access Time
tCEA 70 ns
CE
Data Off Time
tCEZ 25 ns
OE
to DQ Low-Z
tOEL 5 ns
OE
Access Time
tOEA 35 ns
OE
Data Off Time
tOEZ 25 ns
Output Hold from Address
tOH 5 ns
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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AC CHARACTERISTICS—READ CYCLE (3.3V)
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 120 ns
Address Access Time tAA 120 ns
CE
to DQ Low-Z tCEL 5 ns
CE
Access Time tCEA 120 ns
CE
Data Off Time tCEZ 40 ns
OE
to DQ Low-Z tOEL 5 ns
OE
Access Time tOEA 100 ns
OE
Data Off Time tOEZ 35 ns
Output Hold from Address tOH 5 ns
READ CYCLE TIMING DIAGRAM
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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AC CHARACTERISTICS—WRITE CYCLE (5V)
(VCC = 5.0V ±10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Write Cycle Time tWC 70 ns
Address Setup Time tAS 0 ns
WE
Pulse Width tWEW 50 ns
CE
Pulse Width tCEW 60 ns
Data Setup Time tDS 30 ns
Data Hold Time tDH1 0 ns 8
Data Hold Time tDH2 0 ns 9
Address Hold Time tAH1 5 ns 8
Address Hold Time tAH2 5 ns 9
WE
Data Off Time tWEZ 25 ns
Write Recovery Time tWR 5 ns
AC CHARACTERISTICS—WRITE CYCLE (3.3V)
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Write Cycle Time tWC 120 ns
Address Setup Time tAS 0 120 ns
WE
Pulse Width tWEW 100 ns
CE
Pulse Width tCEW 110 ns
Data Setup Time tDS 80 ns
Data Hold Time tDH1 0 ns 8
Data Hold Time tDH2 0 ns 9
Address Hold Time tAH1 0 ns 8
Address Hold Time tAH2 10 ns 9
WE
Data Off Time tWEZ 40 ns
Write Recovery Time tWR 10 ns
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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POWER-UP/DOWN AC CHARACTERISTICS (5V)
(VCC = 5.0V ±10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE
or
WE
at VH
Before Power-Down
tPD 0 µs
VCC Fall Time: VPF(MAX) to
V
PF(MIN)
tF 300 µs
VCC Fall Time: VPF(MIN) to VSO tFB 10 µs
VCC Rise Time: VPF(MIN) to
V
PF
(
MAX)
tR 0 µs
Power-Up Recover Time
VPF to RST High (PowerCap
Only)
tREC 35 ms
Expected Data-Retention Time
(Oscillator ON)
tDR 10 years 5, 6
POWER-UP/DOWN TIMING (5V DEVICE)
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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POWER-UP/DOWN CHARACTERISTICS (3.3V)
(VCC = 3.3V ±10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE
or
WE
at VH, Before
Power-Down
tPD 0 µs
V
CC
Fall Time: V
PF(MAX)
to
VPF(MIN)
tF 300 µs
V
CC
Rise Time: V
PF(MIN)
to
VPF(MAX)
tR 0 µs
Power-Up Recover Time
VPF to
RST
High (PowerCap
Only)
tREC 35 ms
Expected Data-Retention Time
(Oscillator ON)
tDR 10 years 5, 6
POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE)
CAPACITANCE
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Capacitance on All Input Pins
C
IN
14
pF
Capacitance on All Output Pins
C
O
10
pF
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
15 of 16
AC TEST CONDITIONS
Output Load: 50 pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltages are referenced to ground.
2) Typical values are at +25°C and nominal supplies.
3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF.
5) Data-retention time is at +25°C.
6) Each DS1747 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined for DIP modules and assembled PowerCap modules as accumulative time
in the absence of VCC starting from the time power is first applied by the user.
7) RTC encapsulated DIP (EDIP) modules can be successfully processed through conventional wave-
soldering techniques as long as temperatures as long as temperature exposure to the lithium energy
source contained within does not exceed +85°C. Post-solder cleaning with water-washing techniques
is acceptable, provided that ultra-sonic vibration is not used.
See the PowerCap package outline drawing for details regarding the PowerCap package.
8) tAH1, tDH1 are measured from WE going high.
9) tAH2, tDH2 are measured from CE going high.
10) tWC = 200ns.
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
32 EDIP
MDT32+4
21-0245
—
34 PWRCP
PC2+1
21-0246
—
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
16 of 16
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
9/10
Updated the Ordering Information table top mark information and
removed leaded parts; updated the Absolute Maximum Ratings section
to include the storage temperature range and lead and soldering
temperatures for EDIP and PowerCap packages; added Note 10 to the
ICC parameter in the DC Electrical Characteristics tables (for 5.0V and
3.3V) and the Notes section; updated the Package Information table
3, 8, 9, 15
3/12
Updated the Absolute Maximum Ratings section to add the 5V and 3.3V
voltage range
8
6/13
Replaced the Setting the Clock section
5
Mouser Electronics
Authorized Distributor
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DS1747-70+ DS1747-70IND+ DS1747P-70+ DS1747P-70IND+ DS1747W-120IND+ DS1747WP-120IND+
DS1747WP-C03+ DS1747W-120+ DS1747WP-120+ DS1747-70IND-W