DS1339BU+T - Maxim Integrated

General Description

The DS1339B serial real-time clock (RTC) is a low-

power clock/date device with two programmable time-

of-day alarms and a programmable square-wave output.

Address and data are transferred serially through an I2C

bus. The clock/date provides seconds, minutes, hours,

day, date, month, and year information. The date at the

end of the month is automatically adjusted for months

with fewer than 31 days, including corrections for leap

year. The clock operates in either the 24-hour or 12-hour

format with AM/PM indicator. The device has a built-in

power-sense circuit that detects power failures and auto-

matically switches to the backup supply, maintaining time,

date, and alarm operation.

Applications

● Handhelds(GPS,POSTerminals)

● ConsumerElectronics(Set-TopBox,Digital

Recording, Network Appliance)

● OfceEquipment(Fax/Printers,Copier)

● Medical(Glucometer,MedicineDispenser)

● Telecommunications(Routers,Switches,Servers)

● Other(UtilityMeter,VendingMachine,

Thermostat, Modem)

Benets and Features

●Drop-In Replacement for DS1339

● SupportsHigh-ESRCrystalsUpto100kΩtoAllow

CrystalstobeOptimizedforCostandSpace

● CompletelyManagesAllTimekeepingFunctions

• Real-TimeClockCountsSeconds,Minutes,Hours,

Date of the Month, Month, Day of the Week, and

YearwithLeap-YearCompensationValidUpto

2200

• Two Time-of-Day Alarms

• ProgrammableSquare-WaveOutputSignal

●Low-PowerOperationExtendsBatteryBackupRunTime

• AutomaticPower-FailDetectandSwitchCircuitry

●Simple Serial Port Interfaces to Most Microcontrollers

• I2C Serial Interface

● UnderwritersLaboratories(UL®)Recognized

Ordering Information appears at end of data sheet.

UL is a registered trademark of Underwriters Laboratories Inc.

DS1339B

/4 /4096

CONTROL LOGIC

OSCILLATOR

AND

DIVIDER

ALARMS,

TRICKLE CHARGER, AND

CONTROL REGISTERS

CLOCK AND

CALENDAR REGISTERS

USER BUFFER

(7 BYTES)

/2 1Hz

SQW/INTB

4.096kHz

8.192kHz

32.768kHz

MUX/

BUFFER

SERIAL BUS

INTERFACE AND

ADDRESS

POWER

CONTROL

SCL

SDA

VCC

VBACKUP

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

19-6682; Rev 1; 4/15

Functional Diagram

EVALUATION KIT AVAILABLE

VoltageRangeonAnyPinRelativetoGround ....-0.3Vto+6.0V

OperatingTemperatureRange(noncondensing) ... -40°Cto+85°C

Storage Temperature Range ............................ -55°Cto+125°C

LeadTemperature(soldering,10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

µSOP

Junction-to-Ambient Thermal Resistance (θJA) ........ 206.3°C/W Junction-to- Case Thermal Resistance (θJC) ................. 42°C/W

(Note 1)

(TA=-40°Cto+85°C, unless otherwise noted.) (Note 2)

(VCC = MIN to MAX,VBACKUP = MIN to MAX, TA=-40°Cto+85°C.)(Note2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SupplyVoltage VCC 1.71 3.3 5.5 V

BackupSupplyVoltage VBACKUP 1.3 3.0 3.7 V

VBACKMIN 1.15 1.3

Logic 1 VIH 0.7x

VCC 5.5 V

Logic0 VIL -0.3 0.3x

VCC V

Power-FailVoltage VPF 1.51 1.61 1.71 V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage ILI (Note 3) -0.1 0.1 µA

I/OLeakage ILO (Note 4) -0.1 0.1 µA

Logic0Out(SDAorSQW/INT)

VOL=0.4V,

VCC≥VCCMIN

IOL (Note 4) 3 mA

Logic0Out(SQW/INT)

VOL=0.2V,VCC=0V,

VBAT≥VBATMIN

IOL (Note 4) 250 µA

VCC Active Current ICCA (Note5) 450 µA

VCC Standby Current ICCS (Note6) 200 µA

Trickle-Charger Resistor Register

10h=A5h,VCC = Typ,

VBACKUP=0V

R1 (Note 7) 200 Ω

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

www.maximintegrated.com MaximIntegrated

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Note 1: PackagethermalresistanceswereobtainedusingthemethoddescribedinJEDECspecificationJESD51-7,usingafour-layer

board.Fordetailedinformationonpackagethermalconsiderations,referto www.maximintegrated.com/thermal-tutorial.

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Thermal Characteristics

Recommended Operating Conditions

DC Electrical Characteristics

(VCC = MIN to MAX,VBACKUP = MIN to MAX, TA=-40°Cto+85°C,unlessotherwisenoted.)(Note2)

(VCC = 0V,VBACKUP = MIN to MAX, TA=-40°Cto+85°C,unlessotherwisenoted.)(Note2)

(VCC = MIN to MAX, TA=-40°Cto+85°C,unlessotherwisenoted.)(Note2,Figure1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Trickle-Charger Resistor Register

10h=A6h,VCC = Typ,

VBACKUP=0V

R2 2000 Ω

Trickle-Charger Resistor Register

10h=A7h,VCC = Typ,

VBACKUP=0V

R3 4000 Ω

VBACKUP Leakage Current IBKLKG -100 25 200 nA

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VBACKUPCurrentEOSC=0,

SQWOff IBKOSC (Note8) 300 600 nA

VBACKUPCurrentEOSC=0,

SQWOn IBKSQW (Note8) 500 1100 nA

VBACKUPCurrentEOSC=1 IBKDR 10 200 nA

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCLClockFrequency fSCL 0.03 400 kHz

BusFreeTimeBetweenaSTOP

and START Condition tBUF 1.3 µs

HoldTime(Repeated)START

Condition tHD:STA (Note 9) 0.6 µs

Low Period of SCL Clock tLOW 1.3 µs

HighPeriodofSCLClock tHIGH 0.6 µs

Setup Time for a Repeated

START Condition tSU:STA 0.6 µs

DataHoldTime tHD:DAT (Notes10,11) 0 0.9 µs

Data Setup Time tSU:DAT (Note 12) 100 ns

Rise Time of Both SDA and SCL

Signals tR(Note 13) 300 ns

FallTimeofBothSDAandSCL

Signals tF(Note 13) 300 ns

SetupTimeforSTOPCondition tSU:STO 0.6 µs

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

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│

DC Electrical Characteristics (continued)

DC Electrical Characteristics

AC Electrical Characteristics

WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup

mode.

Note 2: Limitsare100%productiontestedatTA=+25°CandTA=+85°C.Limitsovertheoperatingtemperaturerangeand

relevantsupplyvoltagerangeareguaranteedbydesignandcharacterization.Typicalvaluesarenotguaranteed.

Note 3: SCL only.

Note 4: SDAandSQW/INT.

Note 5: ICCA—SCL at fSCLmax,VIL=0.0V,VIH=VCC, trickle charger disabled.

Note 6: Specified with the I2Cbusinactive,VIL=0.0V,VIH=VCC, trickle charger disabled.

Note 7:V

CCmustbelessthan3.63Vifthe200Ωresistorisselected.

Note 8: UsingrecommendedcrystalonX1andX2.

Note 9: After this period, the first clock pulse is generated.

Note 10:Adevicemustinternallyprovideaholdtimeofatleast300nsfortheSDAsignal(referredtotheVIHMIN of the SCL signal)

to bridge the undefined region of the falling edge of SCL.

Note 11:ThemaximumtHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal.

Note 12: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT≥to250nsmustthenbemet.

This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch

thelowperiodoftheSCLsignal,itmustoutputthenextdatabittotheSDAlinetR(MAX)+tSU:DAT=1000+250=1250ns

before the SCL line is released.

Note 13: CB—totalcapacitanceofonebuslineinpF.

Note 14:Guaranteedbydesign;notproductiontested.

Note 15: The parameter tOSFistheperiodoftimetheoscillatormustbestoppedfortheOSFflagtobeset.

Note 16: The device can detect any single SCL clock held low longer than tTIMEOUTMIN. The device’s I2C interface is in reset state

and can receive a new START condition when SCL is held low for at least tTIMEOUTMAX.Oncethedevicedetectsthiscon-

dition, the SDA output is released. The oscillator must be running for this function to work.

Note 17: This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.

(VCC = MIN to MAX, TA=-40°Cto+85°C,unlessotherwisenoted.)(Note2,Figure1)

(TA=-40°Cto+85°C,unlessotherwisenoted.)(Note2,Figure2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CapacitiveLoadforEachBus

Line CB(Note 13) 400 pF

I/OCapacitance(SDA,SCL) CI/O (Note 14) 10 pF

OscillatorStopFlag(OSF)Delay tOSF (Note15) 100 ms

Timeout Interval tTIMEOUT (Note16) 25 35 ms

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

RecoveryatPower-Up tREC (Note 17) 1 2 ms

VCCSlewRate;VPFto0V tVCCF 1/50 V/µs

VCCSlewRate;0VtoVPF tVCCR 1/1 V/µs

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

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AC Electrical Characteristics (continued)

Power-Up/Down Characteristics

Figure 1. I2C Timing

Figure 2. Power-Up/Down Timing

SCL

NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

SDA

STOP START REPEATED

START

tBUF

tHD:STA

tHD:DAT tSU:DAT

tSU:STO

tHD:STA tSP

tSU:STA

tHIGH

tLOW

RECOGNIZED DON’T CARE RECOGNIZED

SCL

VALID VALID

SDA

HIGH IMPEDANCE

tREC

tVCCR

tVCCF

VPF

VCC

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

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(VCC=3.3V,TA=+25°C,unlessotherwisenoted.)

POWER SUPPLY CURRENT

vs. POWER SUPPLY VOLTAGE

DS1339B toc01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

4.73.72.7

100

120

140

160

180

1.7 5.7

VCC = SCL = SDA,

VBACKUP = 3V

TA = +85°C

TA = +25°C

TA = -40°C

POWER SUPPLY CURRENT

vs. SCL FREQUENCY

DS1339B toc02

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

4.73.72.7

100

150

200

250

300

350

400

450

1.7 5.7

VCC = SDA,

VBACKUP = 3V

fSCL = 400kHz

fSCL = 100kHz

fSCL = 1kHz

BACKUP SUPPLY CURRENT

vs. BACKUP VOLTAGE

DS1339B toc03

BACKUP VOLTAGE (V)

BACKUP CURRENT (nA)

3.32.3

150

200

250

300

350

400

450

500

100

1.3 4.3

VCC = 0V,

SQW OFF

TA = +85°C

TA = +25°C

TA = -40°C

BACKUP SUPPLY CURRENT

vs. BACKUP VOLTAGE

DS1339B toc04

BACKUP VOLTAGE (V)

BACKUP CURRENT (nA)

3.32.3

300

350

400

450

500

550

600

650

250

1.3 4.3

VCC = 0V,

SQW ON,

IOUT = 0mA

TA = +85°C

TA = +25°C

TA = -40°C

INT/SQW OUTPUT CURRENT

vs. OUTPUT VOLTAGE

DS1339B toc05

OUTPUT CURRENT (mA)

OUTPUT VOLTAGE (V)

862 4

0.1

0.2

0.3

0.4

0.6

0.5

0.7

0.8

0 10

VCC = 1.71V,

TA = +25°C

INT/SQW OUTPUT CURRENT

vs. OUTPUT VOLTAGE

DS1339B toc06

OUTPUT CURRENT (mA)

OUTPUT VOLTAGE (V)

1.51.00.5

0.1

0.2

0.3

0.4

0 2.0

VBACKUP = 1.3V,

VCC = 0V,

TA = +25°C

TRICKLE CHARGER RESISTORS

vs. POWER SUPPLY VOLTAGE

DS1339B toc07

POWER SUPPLY VOLTAGE (V)

RESISTANCE (Ω)

4.73.72.7

500

1000

1500

2000

2500

3000

3500

4000

1.7 5.7

TA = +25°C

4kΩ SELECTED

2kΩ SELECTED

200Ω SELECTED

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

MaximIntegrated

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Typical Operating Characteristics

µSOP

2 7 SQW/INTX2

1 8 VCC

SCLVBACKUP 3 6

SDAGND

TOP VIEW

4 5

DS1339B

PIN NAME FUNCTION

1 X1 ConnectionsforStandard32.768kHzQuartzCrystal.Theinternaloscillatorcircuitryisdesignedfor

operationwithacrystalhavingaspeciedloadcapacitance(CL)of6pF.

Formoreinformationaboutcrystalselectionandcrystallayoutconsiderations,seetheApplications

InformationsectionandrefertoApplicationNote58:Crystal Considerations with Dallas Real-Time Clocks.

2 X2

3VBACKUP

SecondaryPowerSupply.Supplyvoltagemustbeheldbetween1.3Vand3.7Vforproperoperation.

This pin can be connected to a primary cell, such as a lithium coin cell. Additionally, this pin can be

connected to a rechargeable cell or a super cap when used in conjunction with the trickle-charge

feature.DiodesshouldnotbeplacedinseriesbetweenthebackupsourceandtheVBACKUP input,

orimproperoperationwillresult.Ifabackupsupplyisnotrequired,VBACKUPmustbegrounded.UL

recognizedtoensureagainstreversechargingcurrentwhenusedwithaprimarylithiumcell.Formore

information, visit www.maximintegrated.com/qa/info/ul.

4GND Ground

5SDA

SerialDataInput/Output.SDAistheinput/outputpinfortheI2C serial interface. The SDA pin is an open-

drainoutputandrequiresanexternalpullupresistor.Thepullupvoltagemaybeupto5.5Vregardlessof

thevoltageonVCC.

6SCL SerialClockInput.SCLisusedtosynchronizedatamovementontheI2C serial interface. The pull up

voltagemaybeupto5.5VregardlessofthevoltageonVCC.

7SQW/INT

Square-Wave/InterruptOutput.Programmablesquare-waveorinterruptoutputsignal.TheSQW/INT pin

isanopen-drainoutputandrequiresanexternalpullupresistor.Thepullupvoltagemaybeupto5.5V

regardlessofthevoltageonVCC. If not used, this pin may be left unconnected.

8 VCC

Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data

canbewrittenandread.WhenabackupsupplyisconnectedandVCCisbelowVPF, reads and writes are

inhibited.ThetimekeepingandalarmfunctionsoperatewhenthedeviceispoweredbyVCCorVBACKUP.

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

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Pin Description

Pin Conguration

Detailed Description

The DS1339B serial real-time clock (RTC) is a low-

power clock/date device with two programmable time-

of-day alarms and a programmable square-wave output.

Address and data are transferred serially through an I2C

bus. The clock/date provides seconds, minutes, hours,

day, date, month, and year information. The date at the

end of the month is automatically adjusted for months

with fewer than 31 days, including corrections for leap

year. The clock operates in either the 24-hour or 12-hour

format with AM/PM indicator. The device has a built-in

power-sense circuit that detects power failures and auto-

matically switches to the backup supply, maintaining time,

date, and alarm operation.

Operation

The device operates as a slave device on the serial bus.

Access is obtained by implementing a START condition

and providing a device identification code followed by

data. Subsequent registers can be accessed sequentially

until a STOP condition is executed. The device is fully

accessibleanddatacanbewrittenandreadwhenVCC

is greater than VPF. However, when VCC falls below

VPF, the internal clock registers are blocked from any

access.IfVPFislessthanVBACKUP, the device power is

switchedfromVCCtoVBACKUPwhenVCC drops below

VPF.IfVPFisgreaterthanVBACKUP, the device power

is switched from VCC to VBACKUP when VCC drops

belowVBACKUP. The registers are maintained from the

VBACKUPsourceuntilVCC is returned to nominal levels.

The Functional Diagram shows the main elements of the

serial real-time clock.

Power Control

The power-control function is provided by a precise,

temperature-compensated voltage reference and a com-

paratorcircuitthatmonitorstheVCC level. The device is

fully accessible and data can be written and read when

VCCisgreaterthanVPF.However,whenVCC falls below

VPF, the internal clock registers are blocked from any

access.IfVPFislessthanVBACKUP, the device power is

switchedfromVCCtoVBACKUPwhenVCC drops below

VPF.IfVPFisgreaterthanVBACKUP, the device power

is switched from VCC to VBACKUP when VCC drops

belowVBACKUP. The registers are maintained from the

VBACKUPsourceuntilVCC is returned to nominal levels

(Table 1).AfterVCC returnsabove VPF, read and write

access is allowed after tREC (Figure2).Onthefirstappli-

cation of power to the device the time and date registers

are reset to 01/01/00 01 00:00:00 (DD/MM/YY DOW

HH:MM:SS).

Oscillator Circuit

The device uses an external 32.768kHz crystal. The

oscillator circuit does not require any external resistors

or capacitors to operate. Table 2 specifies several crys-

tal parameters for the external crystal. The Functional

Diagram shows a basic schematic of the oscillator circuit.

The startup time is usually less than 1 second when using

a crystal with the specified characteristics.

Table 1. Power Control

Table 2. Crystal Specifications*

*The crystal, traces, and crystal input pins should be isolated

from RF generating signals. Refer to ApplicationNote58:

Crystal Considerations for Dallas Real-Time Clocks for additional

specifications.

SUPPLY CONDITION

READ/

WRITE

ACCESS

POWERED

VCC<VPF,VCC<VBACKUP No VBACKUP

VCC<VPF,VCC>VBACKUP No VCC

VCC>VPF,VCC<VBACKUP Yes VCC

VCC>VPF,VCC>VBACKUP Yes VCC

PARAMETER SYMBOL MIN TYP MAX UNITS

Nominal

Frequency fO32.768 kHz

Series Resistance ESR 100 kΩ

Load

Capacitance CL6 pF

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Clock Accuracy

The accuracy of the clock is dependent upon the accuracy

of the crystal and the accuracy of the match between the

capacitive load of the oscillator circuit and the capacitive

load for which the crystal was trimmed. Additional error is

added by crystal frequency drift caused by temperature

shifts. External circuit noise coupled into the oscillator

circuit may result in the clock running fast. Figure6 shows

a typical PC board layout for isolating the crystal and

oscillator from noise. Refer to ApplicationNote58:Crystal

Considerations with Dallas Real-Time Clocks for detailed

information

RTC Address Map

Table 3 shows the address map for the device registers.

During a multibyte access, when the address pointer

reaches the end of the register space (10h), it wraps

around to location 00h. On an I2C START or address

pointerincrementingtolocation00h,thecurrent timeis

transferred to a second set of registers. The time infor-

mation is read from these secondary registers, while the

clock may continue to run. This eliminates the need to

re-read the registers in case of an update of the main

registers during a read.

Time and Date Operation

The time and date information is obtained by reading the

appropriate register bytes. Table 3 shows the RTC reg-

isters.Thetimeanddatearesetorinitializedbywriting

the appropriate register bytes. The contents of the time

and date registers are in the BCD format. The device can

be run in either 12-hour or 24-hour mode. Bit 6 of the

HOURSregisterisdefinedasthe12-or24-hourmode-

select bit. When high, the 12-hour mode is selected. In the

12-hourmode,bit5istheAM/PM bit with logic high being

PM.Inthe24-hourmode,bit5isthe20-hourbit(20to

23 hours). All hours values, including the alarms, must be

re-entered whenever the 12/24-hour mode bit is changed.

TheCenturybit(bit7oftheMONTHregister)istoggled

whentheYEARregisteroverflowsfrom99to 00.Ifthe

Century bit is logic 0, the year will be designated as a

LeapYearandFebruarywillcontain29days.

If the Century bit is logic 1, the year will not be designated

asaLeapYearandFebruarywillcontain28days.

TheDay-Of-Weekregisterincrementsatmidnight.Values

that correspond to the day of week are user-defined, but

must be sequential (i.e., if 1 equals Sunday, then 2 equals

Monday and so on). Illogical time and date entries result

in undefined operation.

When reading or writing the time and date registers,

secondary (user) buffers are used to prevent errors when

the internal registers update. When reading the time and

dateregisters, theuser buffersare synchronizedto the

internal registers on a START or when the address pointer

rollsoverto00h.Thecountdownchainisresetwhenever

the seconds register is written. Write transfers occurs on

the acknowledge pulse from the device. To avoid rollover

issues, once the countdown chain is reset, the remaining

time and date registers must be written within one sec-

ond.Ifenabled,the1Hzsquare-waveoutputtransitions

high500msafterthesecondsdatatransfer,providedthe

oscillator is already running.

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Table 3. Timekeeping Register Map

“0” - reads as Logic 0.

Note: Unless otherwise specified, the state of the registers are not defined when power is first applied or when VCC and VBACKUP

fall below the VBACKUP(MIN).

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE

00h 0 10Seconds Seconds Seconds 00-59

01h 0 10Minutes Minutes Minutes 00-59

02h 0 12/24

AM/PM 10

Hour Hours Hours

01-12

+AM/PM

00-23

20Hour

03h 0 0 0 0 0 Day Day 01-07

04h 0 0 10Date Date 01-31

05h Century 0 0 10

Month Month Month 01-12

+Century

06h 10Year Year Year 00-99

07h A1M1 10Seconds Seconds Alarm 1

Seconds 00-59

08h A1M2 10Minutes Minutes Alarm 1

Minutes 00-59

09h A1M3 12/24

AM/PM 10

Hour Hours Alarm 1

Hours

01-12

+AM/PM

00-23

20Hour

0Ah A1M4 DY/DT 10Date Day, Date

Alarm 1

Day, Alarm

1 Date

01-07,

01-31

0Bh A2M2 10Minutes Minutes Alarm 2

Minutes 00-59

0Ch A2M3 12/24

AM/PM 10

Hour Hours Alarm 2

Hours

01-12

+AM/PM

00-23

20Hour

0Dh A2M4 DY/DT 10Date Day, Date

Alarm 2

Day, Alarm

2 Date

01-07,

01-31

0Eh EOSC 0 BBSQI RS2 RS1 INTCN A2IE A1IE Control -

0Fh OSF 0 0 0 0 0 A2F A1F Status -

10h TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 Trickle

Charger -

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Alarms

The device contains two time of day/date alarms. Alarm 1

canbesetbywritingtoregisters07hto0Ah.Alarm2can

besetbywritingtoregisters0Bhto0Dh.Thealarmscan

beprogrammed(bytheAlarmEnableandINTCNbitsof

theControlRegister)toactivatetheSQW/INT output on

an alarm match condition. Bit 7 of each of the time of day/

date alarm registers are mask bits (Table 4). When all the

maskbitsforeachalarmarelogic0,analarmonlyoccurs

whenthevaluesinthetimekeepingregisters00hto06h

match the values stored in the time of day/date alarm

registers. The alarms can also be programmed to repeat

every second, minute, hour, day, or date. Table 4 shows

the possible settings. Configurations not listed in the table

result in illogical operation.

The DY/DT bits (bit 6 of the alarm day/date registers)

controlwhether thealarm valuestored inbits 0to 5of

that register reflects the day of the week or the date of

the month. If DY/DTiswrittentoalogic0,thealarmis

the result of a match with date of the month. If DY/DT is

written to a logic 1, the alarm is the result of a match with

day of the week.

The device checks for an alarm match once per second.

When the RTC register values match alarm register

settings,thecorrespondingAlarmFlag‘A1F’or‘A2F’bitis

settologic1.IfthecorrespondingAlarmInterruptEnable

‘A1IE’or‘A2IE’isalsosettologic1andtheINTCNbitis

settologic1,thealarmconditionactivatestheSQW/INT

signal.IftheBBSQIbitissetto1,theINT output activates

whilethepartisbeingpoweredbyVBACKUP. The alarm

output remains active until the alarm flag is cleared by

the user.

Table 4. Alarm Mask Bits

DY/DT ALARM1 REGISTER MASK BITS (BIT 7) ALARM RATE

A1M4 A1M3 A1M2 A1M1

X 1 1 1 1 Alarm once per second

X 1 1 1 0Alarm when seconds match

X 110 0 Alarm when minutes and seconds match

X 1 0 0 0 Alarm when hours, minutes, and seconds match

0 0 0 0 0 Alarm when date, hours, minutes, and seconds match

10 0 0 0 Alarm when day, hours, minutes, and seconds match

DY/DT ALARM2 REGISTER MASK BITS (BIT 7) ALARM RATE

A2M4 A2M3 A2M2

X 1 1 1 Alarmonceperminute(00sec.ofeveryminute)

X 1 1 0Alarm when minutes match

X 1 0 0 Alarm when hours and minutes match

0 0 0 0 Alarm when date, hours, and minutes match

10 0 0 Alarm when day, hours, and minutes match

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Control Register (0Eh)

ThecontrolregistercontrolstheoperationoftheSQW/INT pin and provides oscillator status.

Bit 7: Enable Oscillator (EOSC). When the EOSCbitis0,theoscillatorisenabled.Whenthisbitisa1,theoscillator

isdisabled.Thisbitiscleared(0)whenpowerisfirstapplied.

Bit 5: Battery-Backed Square-Wave Interrupt (BBSQI).When setto logic1, thisbitenables theSQW/INT output

functionalitywhilethepartispoweredbyVBACKUP.Whensettologic0,thisbitdisablestheSQW/INT output while the

partispoweredbyVBACKUP.

Bits 4 and 3: Rate Select (RS2 and RS1).ThesebitscontrolthefrequencyoftheSQW/INT output when the square-

wavehasbeenenabled(INTCN=0).Table5 lists the square-wave frequencies that can be selected with the RS bits.

Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output pin.

When the INTCN bit is set to logic 1, a match between the timekeeping registers and the Alarm 1 or Alarm 2 registers

activatetheSQW/INTpin(providedthatthealarmisenabled).WhentheINTCNbitissettologic0,asquarewaveis

outputontheSQW/INTpin.Thisbitissettologic0whenpowerisfirstapplied.

Bit 1: Alarm 2 Interrupt Enable (A2IE).Whensettoalogic1,thisbitpermitstheAlarm2Flag(A2F)bitinthestatus

registertoassertSQW/INT(whenINTCN=1).WhentheA2IEbitissettologic0orINTCNissettologic0,theA2Fbit

doesnotinitiateaninterruptsignal.TheA2IEbitisdisabled(logic0)whenpowerisfirstapplied.

Bit 0: Alarm 1 Interrupt Enable (A1IE).Whensettologic1,thisbitpermitstheAlarm1Flag(A1F)bitinthestatus

registertoassertSQW/INT(whenINTCN=1).WhentheA1IEbitissettologic0orINTCNissettologic0,theA1Fbit

doesnotinitiateaninterruptsignal.TheA1IEbitisdisabled(logic0)whenpowerisfirstapplied.

Table 5. SQW/INT Output

Bit # BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

Name EOSC 0 BBSQI RS2 RS1 INTCN A2IE A1IE

POR 0 0 0 11000

INTCN RS2 RS1 SQW/INT OUTPUT A2IE A1IE

0 0 0 1Hz X X

0014.096kHz X X

010 8.192kHz X X

01 1 32.768kHz X X

1 X X A1F 01

1 X X A2F 10

1 X X A2F+A1F 1 1

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Status Register (0Fh)

ThecontrolregistercontrolstheoperationoftheSQW/INT pin and provides oscillator status.

Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some

time period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered, and is set to

logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a stopped condition.

ThefollowingareexamplesofconditionsthatmaycausetheOSFbittobeset:

The first time power is applied.

 ThevoltagepresentonVCCandVBAT are insufficient to support oscillation.

The EOSC bit is set to 1, disabling the oscillator.

 Externalinfluencesonthecrystal(i.e.,noise,leakage,etc.).

Thisbitremainsatlogic1untilwrittentologic0.Thisbitcanonlybewrittentologic0.AttemptingtowriteOSFtologic

1 leaves the value unchanged.

Bit 1: Alarm 2 Flag (A2F).Alogic1intheAlarm2FlagbitindicatesthatthetimematchedtheAlarm2registers.Ifthe

A2IEbitisalogic1andtheINTCNbitissettoalogic1,theSQW/INTpinisalsoasserted.A2Fisclearedwhenwritten

tologic0.Thisbitcanonlybewrittentologic0.Attemptingtowritetologic1leavesthevalueunchanged.

Bit 0: Alarm 1 Flag (A1F).Alogic1intheAlarm1FlagbitindicatesthatthetimematchedtheAlarm1registers.Ifthe

A1IEbitisalogic1andtheINTCNbitissettoalogic1,theSQW/INTpinisalsoasserted.A1Fisclearedwhenwritten

tologic0.Thisbitcanonlybewrittentologic0.Attemptingtowritetologic1leavesthevalueunchanged.

Bit # BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

Name OSF 0 0 0 0 0 A2F A1F

POR 10000000

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Trickle Charger (10h)

The simplified schematic in Figure3 shows the basic components of the trickle charger. The trickle-charge select bits

(TCS[3:0])controltheselectionofthetricklecharger.Topreventaccidentalenabling,onlyapatternon1010enablesthe

trickle charger. All other patterns disable the trickle charger. The trickle charger is disabled when power is first applied.

Thediode-select(DS[1:0])bitsselectwhetherornotadiodeisconnectedbetweenVCCandVBACKUP.TheROUT[1:0]

bitsselectthevalueoftheresistorconnectedbetweenVCCandVBACKUP. Table6 shows the register settings.

Warning: The ROUT value of 200Ω must not be selected whenever VCC is greater than 3.63V.

Theuserdeterminesdiodeandresistorselectionaccordingtothemaximumcurrentdesiredforbatteryorsupercap

charging.Themaximumchargingcurrentcanbecalculatedasillustratedinthefollowingexample.Assumethata3.3V

systempowersupplyisappliedtoVCCandasupercapisconnectedtoVBACKUP. Also assume that the trickle charger

hasbeenenabledwithadiodeandresistorR2betweenVCCandVBACKUP.ThemaximumcurrentIMAX would therefore

becalculatedasfollows:

IMAX=(3.3V-diodedrop)/R2≈(3.3V-0.7V)/2kΩ≈1.3mA

Asthesupercaporbatterycharges,thevoltagedropbetweenVCCandVBACKUP decreases and therefore the charge

current decreases.

Table 6. Trickle Charger Register (10h)

Figure 3. Trickle Charger

200Ω

2kΩ

4kΩ

VCC VBACKUP

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0

TRICKLE-

CHARGE

1 0F 16 SELECT

NOTE: ONLY 1010 CODE ENABLES CHARGER

1 OF 2

SELECT

1 OF 3

SELECT

TCS[3:0] = TRICKLE-CHARGE SELECT

DS[1:0] = DIODE SELECT

ROUT[1:0] = RESISTOR SELECT

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION

TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0

X X X X 0 0 X X Disabled

X X X X 1 1 X X Disabled

XXXXXX 0 0 Disabled

10100101Nodiode,200Ωresistor

101010 0 1Onediode,200Ωresistor

101001 1 0 Nodiode,2kΩresistor

10101010 Onediode,2kΩresistor

101001 1 1 Nodiode,4kΩresistor

1010101 1 Onediode,4kΩresistor

0 0 0 0 0 0 0 0 Initial power-up values

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I2C Serial Port Operation

I2C Slave Address

The device’s slave address byte is D0h. The first byte

sent to the device includes the device identifier and the

R/W bit (Figure4). The device address sent by the I2C

master must match the address assigned to the device.

I2C Denitions

The following terminology is commonly used to describe

I2C data transfers.

Master Device: The master device controls the slave

devices on the bus. The master device generates SCL

clockpulsesandSTARTandSTOPconditions.

Slave Devices: Slave devices send and receive data at

the master’s request.

Bus Idle or Not Busy: Time between STOP and

START conditions when both SDA and SCL are inac-

tive and in their logic-high states. When the bus is idle

it often initiates a low-power mode for slave devices.

START Condition: A START condition is generated by

the master to initiate a new data transfer with a slave.

Transitioning SDA from high to low while SCL remains

high generates a START condition. See Figure 1 for

applicable timing.

STOP Condition:ASTOPconditionisgeneratedbythe

master to end a data transfer with a slave. Transitioning

SDA from low to high while SCL remains high generates

aSTOPcondition.SeeFigure1 for applicable timing.

Repeated START Condition: The master can use a

repeated START condition at the end of one data trans-

fer to indicate that it immediately initiates a new data

transfer following the current one. Repeated STARTs

are commonly used during read operations to identify

a specific memory address to begin a data transfer.

A repeated START condition is issued identically to a

normal START condition. See Figure 1 for applicable

timing.

Bit Write: Transitions of SDA must occur during the low

state of SCL. The data on SDA must remain valid and

unchanged during the entire high pulse of SCL plus the

setup and hold time requirements (see Figure1). Data is

shifted into the device during the rising edge of the SCL.

Bit Read: At the end a write operation, the master must

release the SDA bus line for the proper amount of setup

time (see Figure1)beforethenextrisingedgeofSCL

during a bit read. The device shifts out each bit of data

on SDA at the falling edge of the previous SCL pulse

and the data bit is valid at the rising edge of the current

SCL pulse. Remember that the master generates all

SCL clock pulses including when it is reading bits from

the slave.

Acknowledge (ACK and NACK): An Acknowledge

(ACK) or Not Acknowledge (NACK) is always the 9th

bit transmitted during a byte transfer. The device receiv-

ing data (the master during a read or the slave during

a write operation) performs an ACK by transmitting a

zeroduringthe9thbit.AdeviceperformsaNACKby

transmitting a one during the 9th bit. Timing for the ACK

and NACK is identical to all other bit writes. An ACK is

the acknowledgment that the device is properly receiv-

ing data. A NACK is used to terminate a read sequence

or as an indication that the device is not receiving data.

Byte Write:Abytewriteconsistsof8bitsofinforma-

tion transferred from the master to the slave (most sig-

nificant bit first) plus a 1-bit acknowledgment from the

slavetothemaster.The8bitstransmittedbythemas-

ter are done according to the bit write definition and the

acknowledgment is read using the bit read definition.

Byte Read:Abytereadisan8-bitinformationtransfer

from the slave to the master plus a 1-bit ACK or NACK

fromthemastertotheslave.The8bitsofinformation

that are transferred (most significant bit first) from the

slave to the master are read by the master using the bit

read definition, and the master transmits an ACK using

the bit write definition to receive additional data bytes.

The master must NACK the last byte read to terminate

communication so the slave returns control of SDA to

the master.

Figure 4. Slave Address Byte

1 1 10 R/W000

MSB LSB

READ/

WRITE BIT

DEVICE

IDENTIFIER

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

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Slave Address Byte: Each slave on the I2C bus

responds to a slave address byte sent immediately fol-

lowing a START condition. The slave address byte con-

tains the slave address in the most significant 7 bits and

the R/W bit in the least significant bit. The whatever’s

slave address is D0h and cannot be modified by the

user. When the R/Wbitis0(suchasinD0h),themaster

is indicating it writes data to the slave. If R/W = 1, (D1h

in this case), the master is indicating it wants to read

from the slave. If an incorrect slave address is written,

the device assumes the master is communicating with

another I2C device and ignores the communication until

thenextSTARTconditionissent.

Memory Address: During an I2C write operation, the

master must transmit a memory address to identify

the memory location where the slave is to store the

data. The memory address is always the second byte

transmitted during a write operation following the slave

address byte.

I2C Communication

Writing a Single Byte to a Slave: The master must

generate a START condition, write the slave address

byte (R/W=0),writethememoryaddress,writethebyte

ofdata,andgenerateaSTOPcondition.Rememberthe

master must read the slave’s acknowledgment during

all byte write operations.

Writing Multiple Bytes to a Slave: To write multiple

bytes to a slave, the master generates a START condi-

tion, writes the slave address byte (R/W=0),writesthe

starting memory address, writes multiple data bytes,

andgeneratesaSTOPcondition.

Reading a Single Byte from a Slave:Unlikethewrite

operation that uses the specified memory address byte

to define where the data is to be written, the read opera-

tion occurs at the present value of the memory address

counter. To read a single byte from the slave, the master

generates a START condition, writes the slave address

byte with R/W = 1, reads the data byte with a NACK to

indicatetheendofthetransfer,andgeneratesaSTOP

condition.However,sincerequiringthemastertokeep

track of the memory address counter is impractical, the

following method should be used to perform reads from

a specified memory location.

Figure 5. I2C Transactions

SLAVE

ADDRESS

START

1 1 0 1 0 0 0 SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

R/W

MSB LSB MSB LSB MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

READ/

WRITE

b7 b6 b5 b4 b3 b2 b1 b0

DATA

STOP

SINGLE BYTE WRITE

-WRITE CONTROL REGISTER

TO B8h

MULTIBYTE WRITE

-WRITE DATE REGISTER TO "02"

AND MONTH REGISTER TO "11"

SINGLE BYTE READ

-READ CONTROL REGISTER

MULTIBYTE READ

-READ HOURS AND DAY

START REPEATED

START

D1h

MASTER

NACK STOP11010000 00001110

0Eh

11010001

1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0

D0h 0Eh

STOP

VALUE

START 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0

D0h 04h

DATA

MASTER

NACK STOPVALUE

DATA

02h

B8h

EXAMPLE I2C TRANSACTIONS

TYPICAL I2C WRITE TRANSACTION

10111000

00000010

D0h

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

REPEATED

START

D1h

MASTER

ACK

11010001 VALUE

DATA

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

START 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0

D0h 02h

SLAVE

ACK

SLAVE

ACK

STOP

11h

00010001 SLAVE

ACK

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

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Manipulating the Address Counter for Reads: A

dummy write cycle can be used to force the address

counter to a particular value. To do this the master

generates a START condition, writes the slave address

byte (R/W = 0), writes the memory address where it

desires to read, generates a repeated START condi-

tion, writes the slave address byte (R/W = 1), reads

data with ACK or NACK as applicable, and generates a

STOPcondition.SeeFigure5forareadexampleusing

the repeated START condition to specify the starting

memory location.

Reading Multiple Bytes From a Slave: The read

operation can be used to read multiple bytes with a

single transfer. When reading bytes from the slave, the

master simply ACKs the data byte if it desires to read

another byte before terminating the transaction. After

the master reads the last byte it must NACK to indicate

theendofthetransferandthenitgeneratesaSTOP

condition.

Applications Information

Power-Supply Decoupling

To achieve the best results when using the device,

decouple the VCC power supply with a 0.01µF and/or

0.1µF capacitor. Use a high-quality, ceramic, surface-

mount capacitor if possible. Surface-mount components

minimizeleadinductance,whichimprovesperformance,

and ceramic capacitors tend to have adequate high-

frequency response for decoupling applications.

Using an Open-Drain Output

TheSQW/INT output is open-drain and therefore requires

anexternal pullupresistor torealize alogic-high output

level.

SDA and SCL Pullup Resistors

SDAisanopen-drainoutputandrequiresanexternalpul-

lupresistortorealizealogic-highoutputlevel.

Because the device does not use clock cycle stretching,

a master using either an open-drain output with a pullup

resistororCMOSoutputdriver(push-pull)couldbeused

for SCL.

Battery Charge Protection

The device contains Maxim’s redundant battery-charge

protectioncircuittopreventany chargingof anexternal

battery.TheDS1339BisrecognizedbytheUnderwriters

Laboratories(UL)underfileE141114.

Handling, PCB Layout, and Assembly

Avoid running signal traces under the package, unless a

ground plane is placed between the package and the sig-

nalline.Donotuseexternalcomponentstocompensate

for improper crystal selection.

Moisture-sensitive packages are shipped from the factory

dry-packed.Handling instructionslisted onthe package

label must be followed to prevent damage during reflow.

Refer to the IPC/JEDEC J-STD-020 standard for mois-

ture-sensitive device (MSD) classifications.

Figure 6. Typical PCB Layout for Crystal

CRYSTAL X1

LOCAL GROUND PLANE (LAYER 2)

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

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+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

*Future product—contact factory for availability.

PART TEMP RANGE PIN-PACKAGE

DS1339BU+ -40°Cto+85°C 8µSOP

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

8µSOP U8+1 21-0036 90-0092

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

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Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

thata“+”,“#”,or“-”inthepackagecodeindicatesRoHSstatus

only.Packagedrawingsmayshowadifferentsuffixcharacter,but

thedrawingpertainstothepackageregardlessofRoHSstatus.

Chip Information

PROCESS:CMOS

SUBSTRATECONNECTEDTOGROUND

Ordering Information

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 5/13 Initial release —

14/15 Revised Benets and Features section 1

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

DS1339B Low-Current, I2C, Serial Real-Time Clock

for High-ESR Crystals

│

Revision History

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.