2003 Microchip Technology Inc. DS80165A-page 1
PIC16F73/74/76/77
The PIC16F73/74/76/77 parts you have received con-
form functionally to the Device Data Sheet
(DS30325B), except for the anomalies described
below.
None.
Date Codes that pertain to Rev. C0 Silicon:
PIC16F7 3/7 4 0220 and later
PIC16F7 6/7 7 0304 and later
Clarifications/Corrections to the Data
Sheet:
In the Device Data Sheet (DS30325B), the following
clarifications and corrections should be noted.
1. Module: Core
The t ypica l and maxi mum suppl y curre nts (p aram-
eter D010A) specified for extended voltage
devices have been changed.
The IDD specifi cat ion s differ from the D evice Da ta
Sheet only for devices operating at a VDD of 3.0V
and a FOSC of 32 kHz with the WDT disabled.
The changes in the specification are shown in
bold in Table 1.
TABLE 1: DC SPECIFICATION CHANGES FROM DATA SHEET
Param
No. Sym. Characteristic/
Device
New Specification Data Sheet
Specification Units Notes
Min Typ Max Min Typ Max
D010A IDD Supply Current
PIC16LF73/74/76/77 —25 48 — 20 48 µA LP osc configuration,
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
PIC16F73/74/76/77 (Rev. C0 Silicon) Data Sheet Errata
PIC16F73/74/76/77
DS80165A-page 2 2003 Microchip Technology Inc.
2. Module: Pinout Correction
The MLF (now known as QFN) package pinout
locations for pins RA4 and RA5 were incorrectly
stated in Table 1-2 of the Device Data Sheet.
The correct pinout locations are indicated in bold
in Table 2.
TABLE 2: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION
Pin Name
DIP
SSOP
SOIC
Pin#
MLF
Pin# I/O/P
Type Buffer
Type Description
.
.
.
RA4/T0CKI
RA4
T0CKI
63I/O
I
ST Digital I/O – Open drain when configured as output.
Timer0 external clock input.
RA5/SS/AN4
RA5
SS
AN4
74I/O
I
I
TTL Digital I/O.
SPI slave select input.
Analog input 4.
.
.
.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt T r igger input
2003 Microchip Technology Inc. DS80165A-page 3
PIC16F73/74/76/77
3. Module: Pinout Correction
The PIC16F73/74/76/77 device family does not
offer low-voltage programming. The Device Data
Sheet incorrectly lists RB3 as providing the PGM
function required for low-voltage programming.
References to the PGM function in Tables 1-2 and
Table 1-3 of the Device Data Sheet have been
removed. Table 3 and Table 4 show the correc-
tions for the PIC16F73/76 and PIC16F74/77
devices respectively, The text shown in bold has
been removed.
References to the PGM function in the Pin
Diagrams on pages 2 and 3, and Figures 1-1 and
1-2 (pages 6 and 7) in the Data Sheet have also
been removed.
A reference to the PGM function listed in the Data
Sheet Index has also been removed.
TABLE 3: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION
TABLE 4: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION
Pin Name
DIP
SSOP
SOIC
Pin#
MLF
Pin# I/O/P
Type Buffer
Type Description
.
.
.
RB3/PGM
RB3
PGM
.
.
.
24 21 I/O
I/O
TTL Digital I/O.
Low voltage ICSP programming enable pin.
Pin Name DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
.
.
.
RB3/PGM
RB3
PGM
.
.
.
36 39 11 I/O
I/O
TTL Digita l I/O.
Low voltage ICSP programming enable pin.
PIC16F73/74/76/77
DS80165A-page 4 2003 Microchip Technology Inc.
4. Module: Packaging (Pinout and Product
Identification)
PIC16F74 and PIC16F77 devices are now offered
in a 44-pin, micro lead frame package (commonly
known as “QFN”). This provides near chip scale
package s ize. This option is in addition to the 28-pin
QFN packages already available for the PIC16F73
and PIC16F76 devices. The 44-pin QFN package
has been added to the product line since the
original publication of the Device D at a Sheet.
The addition of this option requires the following
additions to the Device Data Sheet (DS30325B).
Referenced figures and tables follow this text.
1. The “Pin Diagrams” on pages 2-3 of the Data
Sheet are amended with the addition of the
44-pin QFN pinout shown in Figure 1.
2. Table 1.3 of Secti on 1.0 (“D evice O vervi ew”) is
replace d with an upd ated version wh ich adds a
column for QFN pin assignments. All new
information is indicated in bold.
3. Section 17.1 (“Package Marking Information”)
is amend ed to inc lu de a marking template and
example for 44-pin QFN devices. These are
shown in Figure 2.
4. Section 17.2 (“Package Details”) is amended
to incl ude the mechan ical drawing o f the 44-pin
QFN package, follow in g th e e xi sti ng draw i ngs .
This is shown in Figure 3.
5. In the “PIC16F7X Product Identification
System” (page 171), the “ML” line item in the
“Package” options section should now read
(change in bold):
ML = QFN
For th e sake of comp letene ss, i t is als o noted
that the package designation “MLF” is now
replaced by “QFN” in all occurrences through-
out the Device Data Sheet. “MLF” should be
considered an obsoleted term.
FIGURE 1: PINOUT DIAGRAM FOR PIC16F74/77, 44-PIN QFN PACKAGE
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC16F74
37
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
MCLR/VPP
RB3
RB7/PGD
RB6/PGC
RB5
RB4
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
RC0/T1CKI
OSC2/CLKO
OSC1/CLKI
VSS
VSS
VDD
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
VDD
RB0/INT0
RB1
RB2
44-Pin QFN
PIC16F77
2003 Microchip Technology Inc. DS80165A-page 5
PIC16F73/74/76/77
FIGURE 2: PACKAGE MARKING TEMPLATE FOR PIC16F74/77, 44-PIN QFN
44-Lead QFN Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F77
-I/ML
0310017
PIC16F73/74/76/77
DS80165A-page 6 2003 Microchip Technology Inc.
TABLE 1-3: PIC16F74/77 PINOUT DESCRIPTION
Pin Nam e DIP
Pin# PLCC
Pin# QFN
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKI
OSC1
CLKI
13 14 32 30 I ST/CMOS(4) Oscillator crystal or external clock input.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode.
Otherwise CMOS.
External clock source input. Always associated
with pin function OSC1 (see OSC1/CLKI,
OSC2/CLKO pins).
OSC2/CLKO
OSC2
CLKO
14 15 33 31 O — Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal
Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
MCLR/VPP
MCLR
VPP
1218 18 I/P ST Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active low
RESET to the device.
Programming voltage input.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2319 19 I/O
I
TTL Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3420 20 I/O
I
TTL Digital I/O.
Analog input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
4521 21 I/O
I
I
TTL Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
5622 22 I/O
I
I
TTL Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
RA4/T0CKI
RA4
T0CKI
6723 23 I/O
I
ST Digital I/O – Ope n drain when configured as output.
Timer0 external clock input.
RA5/SS/AN4
RA5
SS
AN4
7824 24 I/O
I
I
TTL Digital I/O.
SPI slave select input.
Analog input 4.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor b us).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2003 Microchip Technology Inc. DS80165A-page 7
PIC16F73/74/76/77
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT
RB0
INT
33 36 98I/O
I
TTL/ST(1)
Digital I/O.
External interrupt.
RB1 34 37 10 9I/O TTL Digital I/O.
RB2 35 38 11 10 I/O TTL Digit a l I/O.
RB3 36 39 12 11 I/O TTL Digital I/O.
RB4 37 41 14 14 I/O TTL Digital I/O.
RB5 38 42 15 15 I/O TTL Digital I/O.
RB6/PGC
RB6
PGC
39 43 16 16 I/O
I/O
TTL/ST(2)
Digital I/O.
In-circuit debugger and ICSP™ programming clock.
RB7/PGD
RB7
PGD
40 44 17 17 I/O
I/O
TTL/ST(2)
Digital I/O.
In-circuit debugger and ICSP™ programming data.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15 16 34 32 I/O
O
I
ST Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
16 18 35 35 I/O
I
I/O
ST Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
17 19 36 36 I/O
I/O
ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
18 20 37 37 I/O
I/O
I/O
ST Digital I/O.
Synchronous seria l clock input /output for SPI™ mode.
Synchronous se rial clo ck inp ut/out put for I 2C™ mode.
RC4/SDI/SDA
RC4
SDI
SDA
23 25 42 42 I/O
I
I/O
ST Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
24 26 43 43 I/O
O
ST Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
25 27 44 44 I/O
O
I/O
ST Digital I/O.
USART asynchronous tr ansmit .
USART 1 synchronous clock.
RC7/RX/DT
RC7
RX
DT
26 29 11I/O
I
I/O
ST Digital I/O.
USART asynchronous receiv e.
USART synchronous data.
TABLE 1-3: PIC16F74/77 PINOUT DESCRIPTION (CONTINUED)
Pin Nam e DIP
Pin# PLCC
Pin# QFN
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode .
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor b us).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
PIC16F73/74/76/77
DS80165A-page 8 2003 Microchip Technology Inc.
PORTD is a bidirectional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0
RD0
PSP0
19 21 38 38 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD1/PSP1
RD1
PSP1
20 22 39 39 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD2/PSP2
RD2
PSP2
21 23 40 40 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD3/PSP3
RD3
PSP3
22 24 41 41 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD4/PSP4
RD4
PSP4
27 30 22I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD5/PSP5
RD5
PSP5
28 31 33I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD6/PSP6
RD6
PSP6
29 32 44I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD7/PSP7
RD7
PSP7
30 33 55I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
RD
AN5
8925 25 I/O
I
I
ST/TTL(3)
Digital I/O.
Read control for parallel slave port.
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
91026 26 I/O
I
I
ST/TTL(3)
Digital I/O.
Write control for parallel slave port.
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10 11 27 27 I/O
I
I
ST/TTL(3)
Digital I/O.
Chip select control for parallel slave port.
Analog input 7.
VSS 12,31 13,34 6, 30,
31 6,29 P — Ground reference for logic and I/O pins.
VDD 11,32 12,35 7, 8,
28, 29 7,28 P — Positive supply for logic and I/O pins.
NC — 1,17,
28,40 13 12,13,
33,34 — — These pins are not internally connected. These pins
should be left unconnected.
TABLE 1-3: PIC16F74/77 PINOUT DESCRIPTION (CONTINUED)
Pin Nam e DIP
Pin# PLCC
Pin# QFN
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor b us).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2003 Microchip Technology Inc. DS80165A-page 9
PIC16F73/74/76/77
FIGURE 3: 44-PIN QFN PACKAGE (DRAWING 1, PACKAGING)
44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
Lead Width
*Controlling Parameter
Drawing No. C04-103
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
B .012 .013 .013 0.30 0.33 0.35
Pitch
Number of Pins
Overall Width
Standoff
Overall Length
Overall Height
MAX
Units
Dimension Limits
A1
D
E
n
p
A
.315 BSC
.000
INCHES
.026 BSC
MIN
44
NOM MAX
.002 0
8.00 BSC
MILLIMETERS*
.039
MIN
44
0.65 BSC
NOM
0.05
1.00
.010 REFBase Thickness A3 0.25 REF
JEDEC equivalent: M0-220
0.90.035
.001 0.02
.315 BSC 8.00 BSC
Lead Length L .014 .016 .018 0.35 0.40 0.45
E2
D2
Exposed Pad Width
Exposed Pad Length .262 .268 .274 6.65 6.80 6.95
.262 .268 .274 6.65 6.80 6.95
D2
D
A1
A3
A
TOP VIEW
n
1
L
E2
BOTTOM VIEW
B
E
2
PAD
METAL
EXPOSED
p
PIN 1
INDEX ON
EXPOSED PAD
TOP MARKING
INDEX ON
OPTIONAL PIN 1
.031 0.80
PIC16F73/74/76/77
DS80165A-page 10 2003 Microchip Technology Inc.
REVISION HISTORY
Rev A Document (8/2003)
First revision of this document. Device Data Sheet
Clarification issues 1 (Core), 2 (Pinout Correction),
3 (Pinout Correction) and 4 (Packaging).
2003 Microchip Technology Inc. DS80165A-page 11
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, MPLAB, PIC, PICmicro, PICST ART, PRO MA TE and
PowerSmart are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-
Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB , MPLINK , MPSI M,
PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, Powe rTool, rfLAB , rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartT el and T ot al Endurance are
trademarks of Microchip Technology Incorporat ed in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrit y of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code prot ection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such a ct s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS80165A-page 12 2003 Microchip Technology Inc.
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Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel : 81- 45 -47 1- 616 6 Fax: 81-45-471 -61 22
Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK- 2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
France
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - l er Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany
Steinheilstras se 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
Fax: 31-416- 690340
United Kingdom
505 Eskdale Road
Winnersh T riangle
Wokingham
Berk shi re, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
07/28/03
WORLDWIDE SALES AND SERVICE
