MC100EPT26DR2G - ON Semiconductor L.L.C.

December, 2009 − Rev. 16

1Publication Order Number:

MC100EPT26/D

MC100EPT26

3.3V 1:2 Fanout Differential

LVPECL/LVDS to LVTTL

Translator

Description

The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to

LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are

used only +3.3 V and ground are required. The small outline 8−lead

package and the 1:2 fanout design of the EPT26 makes it ideal for

applications which require the low skew duplication of a signal in a

tightly packed PC board.

The VBB output allows the EPT26 to be used in a single−ended input

mode. In this mode the VBB output is tied to the D0 input for a

non−inverting buffer or the D0 input for an inverting buffer. If used,

the VBB pin should be bypassed to ground with > 0.01 mF capacitor.

For a single−ended direct connection, use an external voltage

reference source such as a resistor divider. Do not use VBB for a

single−ended direct connection or port to another device.

Features

•1.4 ns Typical Propagation Delay

•Maximum Frequency > 275 MHz Typical

•The 100 Series Contains Temperature Compensation

•Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V

•24 mA TTL outputs

•Q Outputs Will Default LOW with Inputs Open or at VEE

•VBB Output

•Pb−Free Packages are Available

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAMS*

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

M = Date Code

G= Pb−Free Package

ALYWG

KA26

SO−8

D SUFFIX

CASE 751

TSSOP−8

DT SUFFIX

CASE 948R

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

KPT26

ALYW

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DFN8

MN SUFFIX

CASE 506AA

3W MG

(Note: Microdot may be in either location)

MC100EPT26

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GND

VCC

Figure 1. 8−Lead Pinout and Logic Diagram

Q1D

VBB

LVTTL

LVPECL

(Top View)

Table 1. PIN DESCRIPTION

Pin Function

Q0, Q1 LVTTL Outputs

D0**, D1** Differential LVPECL Inputs Pair

VCC Positive Supply

VBB Output Reference Voltage

GND Ground

NC No Connect

EP (DFN8 only) Thermal exposed pad must be con-

nected to a sufficient thermal conduit. Electric-

ally connect to the most negative supply (GND)

or leave unconnected, floating open.

** Pins will default to VCC/2 when left open.

Table 2. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 50 kW

Internal Input Pullup Resistor 50 kW

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 1.5 kV

> 100 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

SO−8

TSSOP−8

DFN8

Level 1

Level 3

Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 117 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

MC100EPT26

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Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC Positive Power Supply GND = 0 V 3.8 V

VIN Input Voltage GND = 0 V VI  VCC 0 to 3.8 V

IBB VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SOIC−8

190

130

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−841 to 44 °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

TSSOP−8

185

140

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−841 to 44 °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

DFN8

129

°C/W

Tsol Wave Solder Pb

Pb−Free

265

°C

qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

Table 4. PECL INPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 3)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV

VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV

VBB Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 4)

1.2 3.3 1.2 3.3 1.2 3.3 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current D

−150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. Input parameters vary 1:1 with VCC.

4. VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the

differential input signal.

MC100EPT26

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Table 5. TTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V; TA = −40°C to 85°C

Symbol Characteristic Condition Min Typ Max Unit

VOH Output HIGH Voltage IOH = −3.0 mA 2.4 V

VOL Output LOW Voltage IOL = 24 mA 0.5 V

ICCH Power Supply Current 10 25 35 mA

ICCL Power Supply Current 15 34 40 mA

IOS Output Short Circuit Current −50 −150 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; GND = 0.0 V (Note 5)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fmax Maximum Frequency (Figure 2) 275 350 275 350 275 350 MHz

tPLH,

tPHL

Propagation Delay to

Output Differential (Note 6)

1.2

1.5

2.0

1.8

1.2

1.5

2.0

1.8

1.3

1.2

1.7

1.5

2.2

1.8

tSK+ +

tSK−−

tSKPP

Within Device Skew++

Within Device Skew− −

Device−to−Device Skew (Note 7)

100

500

100

500

100

500

tJITTER Random Clock Jitter (RMS) (Figure 2)

@ v 200 MHz

@ > 200 MHz

275

170

275

VPP Input Voltage Swing (Differential Configuration) 150 800 1200 150 800 1200 150 800 1200 mV

Output Rise/Fall Times

(0.8V − 2.0V) Q, Q 330 600 950 330 600 950 330 650 950

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5. Measured with a 750 mV 50% duty−cycle clock source. RL = 500 W to GND and CL = 20 pF to GND. Refer to Figure 3.

6. Reference (VCC = 3.3 V ± 5%; GND = 0 V)

7. Skews are measured between outputs under identical transitions.

Figure 2. Typical VOH / Jitter versus Frequency (255C)

FREQUENCY (MHz)

VOH (V)

0.0

1.0

2.0

3.0

VOH

VOL  0.5 V

JITTER

RANDOM CLOCK JITTER (ps RMS)

0 100 200 300

MC100EPT26

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Figure 3. TTL Output Loading Used for Device Evaluation

CHARACTERISTIC TEST

CL*R

AC TEST LOAD

GND

*CL includes

fixture

capacitance

APPLICATION

TTL RECEIVER

ORDERING INFORMATION

Device Package Shipping†

MC100EPT26D SOIC−898 Units / Rail

MC100EPT26DG SOIC−8

(Pb−Free)

98 Units / Rail

MC100EPT26DR2 SOIC−82500 / Tape & Reel

MC100EPT26DR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

MC100EPT26DT TSSOP−8100 Units / Rail

MC100EPT26DTG TSSOP−8

(Pb−Free)

100 Units / Rail

MC100EPT26DTR2 TSSOP−82500 / Tape & Reel

MC100EPT26DTR2G TSSOP−8

(Pb−Free)

2500 / Tape & Reel

MC100EPT26MNR4 DFN8 1000 / Tape & Reel

MC100EPT26MNR4G DFN8

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC100EPT26

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Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC100EPT26

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC100EPT26

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PACKAGE DIMENSIONS

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.80 1.10 0.031 0.043

D0.05 0.15 0.002 0.006

F0.40 0.70 0.016 0.028

G0.65 BSC 0.026 BSC

L4.90 BSC 0.193 BSC

M0 6 0 6

____

SEATING

PLANE

PIN 1

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

8x REFK

IDENT

K0.25 0.40 0.010 0.016

TSSOP−8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R−02

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

MC100EPT26

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PACKAGE DIMENSIONS

DFN8

CASE 506AA−01

ISSUE D

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

ÇÇÇ

C0.10

PIN ONE

2 X

REFERENCE

2 X

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(A3)

C0.10

C0.08

8 X

SEATING

PLANE

e/2 e

8 X

NOTE 3

8 X 0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

D2.00 BSC

D2 1.10 1.30

E2.00 BSC

E2 0.70 0.90

e0.50 BSC

K0.20 −−−

L0.25 0.35

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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Japan Customer Focus Center

Phone: 81−3−5773−3850

MC100EPT26/D

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For additional information, please contact your local

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ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).