PBM 39705/3LQ Preliminary Extended Line Driver for DSLAM applications Key Features * Using standard CMOS technologies * Seven power modes (0.4 W - 1 W) enables optimized line card power dissipation * Typically 0.8 W (VBAT = 10 V) power dissipation during full rate COoperation and 0.2 W when the device is operating in idle mode 6-11V VDD1 OTPO OTPR PD SUBH VDD2 VBAT DR1 GND TVP SA1 750k 680 nF Line transformer SB1 IREF AD/DA 45.3 2.7 OTPR R REF VSS3 VSS3 PBM 397 05/3 POTS Splitter 6.8 nF Line TVN SB2 RP * Analog echo cancellation (better than 20 dB) relaxes the requirements of the DSP and the AD/DA converter * A high integration level requires minimum external components and a more robust design 5V 5V SA2 2.7 680 nF 2:1 RN Receive 45.3 RVREF2.2 VSS1 DR2 DIN DEN DCLK RS VSS2 VBAT 6-11V To DSP or P * 32 pin LQFP package (0C - 85C) Figure 1. Line driver application. Description The Ericsson Analog Receive/Transmit Interface Circuit (ARTIC) for DSLAM applications is an analog line driver and receiver circuit providing the driving and terminating functions needed for implementation of an ADSL transceiver. The DSL interface circuit includes line driver, receiver, echo cancellation, termination and programmable gain controllers. The ARTIC line driver serve both full rate ADSL and ADSL Lite, according to the ITU recommendations G.dmt and G.Lite respectively, it supports annex A (ADSL over POTS) and annex B (ADSL over ISDN). The ARTIC line driver is designed for CO-applications. Power consumption is minimized by the line driver architecture and by a design optimized for ADSL. The optimized design of the ARTIC line driver also ensures a compact board design with minimum area and wiring. On a CO-application, a dual power supply is used to provide full line drive capability. The applied supply voltage on the driver output can be varied between 6 V and 11 V, depending on the required output swing (up to 16.5 Vpp differential). Further, the design of the ARTIC line driver relaxes the requirements on the mixed signal and DSP part of the ADSL transceiver, with an integrated analog echo cancellation, which cancel more than 20 dB of the transmitted signal, and an intelligent programmable feedback loop providing an optimal line termination. To further reduce power dissipation, seven power modes are introduced, which can be used on shorter lines to reduce power dissipation or when bitrate demands are lower. PBM 397 05/3 Absolute Maximum Ratings Parameter Symbol Min Storage Temperature Range Operating Junction Temperature Range Operating Ambient Temperature Range Thermal Resistance, junction to ambient, LQFP-32 Condition TStg TJ TAmb QJA -60 0 0 Typ Max Unit +150 +120 +85 C C C C/W Supply Voltages VDD1, VDD2, with respect to VSS1 Supply Voltages VBAT, with respect to VSS1 Analog Voltage Input Range, with respect to VSS1 Digital Voltage Input Range, with respect to VSS1 Continuous Power Dissipation 0C< TAmb <+85C VDDx -0.3 +6.5 V 0C< TAmb <+85C VBAT -0.3 +11.5 V 0C< TAmb <+85C VAnalog -0.3 VDD1+0.3 V 0C< TAmb <+85C VDigital -0.3 VDD1+0.3 V TAmb = +85C PDmax 1.2 W Typ Max Unit Comment 0 4.75 5 4.75 5 VDD1 + 1 10.5 +85 5.25 5.25 11.0 C V V V See figure 2 42.1 Comment On Multilayer card @ 1m/s flow Recommended Operating Conditions Parameter Condition Symbol Operating Ambient Temperature Range Supply Voltage With respect to VSS1 With respect to VSS2 With respect to VSS3 TAmb VDD1 VDD2 VBAT Min Maximum Ambient Temperature Maximum power dissipation in LQFP 32 when transmitting multitone, assumed that maximum junction temperature is 120 C, and maximum ambient temperature is 85 C. Rthja = 47.9 C/W with airflow of 0 liters/min Rthja = 42.1 C/W with airflow of 200 liters/min Rthja = 39.4 C/W with airflow of 500 liters/min 1400 Pdmax 1300 Flow (l/min) Temp. 1200 1100 0 200 500 TA = 85 C 730 830 890 TA = 80 C 840 850 1020 800 TA = 75 C 940 1070 1140 700 TA = 70 C 1040 1190 1270 600 1000 900 500 0 50 100 150 200 250 TA = 70 C TA = 75 C 300 350 400 450 500 TA = 80 C TA = 85 C Figure 2. Ambient temperature. Default Conditions Unless otherwise noted the specification applies for the default general conditions using the default external components and default device programming. General Conditions Condition Symbol Power Supplies except VBAT Power Supply Receive bias voltage Ambient Temperature VDD1, VDD2 VDD3 VRRef TAmb 2 Value Unit 5 10 2.2 25 V V V C Comment EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 PBM 397 05/3 External Components in application Component Symbol Line Transformer T1* Value 2:1 Unit Tol. Line Capacitors CLA, CLB 68 nF 10% ZS series resistors ZS shunt resistors ZS series capacitors RSA, RSB RSHA, RSHB CSA, CSB 2.7 45.3 680 W W nF 1% 1% 5% Bias Current Setting Resistor COB out of band Filter Capacitor Receive Path DC Capacitor CVDD Decoupling Capacitor for VDD1 CVDD Decoupling Capacitors VDD2, Transmit Input Coupling Capacitor Receive Output Coupling Capacitor RREF 24.3 COB 6.8 CRX 68 CVDD1 220 VBAT, CVDD2, CVBAT 220 CTP, CTN 22 CRP, CRN 22 kW nF nF nF nF nF nF 1% 10% 10% 10% 10% 10% 10% Comment At least 45dB balance 5% for better echo cancellation 0.25W 0.25W 63V, tan d < 0.03 @80kHz 0.1W * For example Schott 32828 or Bel Fuse S560-6600-AB: The CLA and CLB values are given for an application where this Schott transformer is used. External components in application DEN n Common for all lines 0V DSP PD DIN DEN RS DCLK VSS2 VBAT VBAT CLA CSA T1 VBAT 0V 0V VSS1 SB2 RN NC DR2 P2 0V P1 P2 SA2 COB VBAT ADC CRP RP IREF R REF VSS3 CLB CPB R SB 39705 VSS3 0V CRN DR1 NC SB1 VREF2.2 SA1 VDD1 0V CRX CPA 0V R SHA R SA LINE 0V VBAT 0V DEN 1 CODEC DAC +5V 0V CSB 0V R SHB TVN OTPO OTPR ROTP CTN CTP 0V +5V 0V 0V TVP VBAT SUBH VBAT VDD2 VBAT 0V Figure 3. External components in application. External components during test 0V 0V VBAT 0V PD DIN DEN DCLK RS VSS2 VBAT VBAT 0V R SA SA2 VSS1 SB2 RN NC DR2 0V RL 39705/3 VSS3 0V RP IREF R REF VSS3 DR1 NC SB1 VREF2.2 SA1 VDD1 0V +5V 0V R SB TVN OTPO OTPR TVP SUBH VDD2 VBAT VBAT 0V CTP CTN 0V 0V 0V ROTP +5V VBAT Figure 4. External components during setup. EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 3 PBM 397 05/3 External Components During Test Component Symbol Value Line Load RS series resistors Bias Current Setting Resistor CVDD Decoupling Capacitor for VDD1 CVDD Decoupling Capacitors VDD2, VBAT Transmit Input Coupling Capacitor RL RSA, RSB RREF CVDD1 CVDD2, CVBAT CTP , CTN 25 2.7 24.3 220 220 47 Unit Tol. Comment W W kW nF nF nF 1% 1% 1% 10% 10% 10% 0.25W 0.25W 0.1W Electrical Characteristics Power Dissipation & Supply Currents Parameter Condition Symbol Supply Currents VBAT = 10.0V or 6.0V Power Down mode (PD=5V), no ADSL signal RL = 25W On-chip Power Consumption Supply Currents On-chip Power Consumption Supply Currents On-chip Power Consumption Supply Currents On-chip Power Dissipation Min Typ Max Unit IDD1 IDD2 IBAT 2.7 4.0 0 5.0 10.0 10.0 mA mA mA P = S(IDDxVDD+IBATxVBAT) Pd 32 VBAT = 10.0V Power mode 7 (PD=0V), no ADSL Tx signal P2P1P0 = "111" IDD1 IDD2 IBAT 11.5 11.5 10.0 P = S(IDDxVDD+IBATxVBAT) Pd7 210 VBAT = 10.0V Power mode 0 (PD=0V), no ADSL signal IDD1 IDD2 IBAT 24.0 23.0 69.0 P = S(IDDxVDD+IBATxVBAT) Pd0 922 mW VBAT = 10.0V Power mode 2, transmitting ADSL signal PSD = -40dBm/Hz, 0.15-1.1MHz, PAR = 3.8 TX-PGC = +16.5dB P = S(IDDxVDD+IBATxVBAT) - IL2 x ZL (1) IDD1 IDD2 IBAT 20.0 25.0 72.0 mArms mArms mArms Pd2 845 mW mW 12.5 12.5 15 mA mA mA mW 25.0 24.5 73.0 mA mA mA Note 1: The power dissipated in the external ZS impedances are included in the On-Chip power, since this power is dissipated on the board. Power Supply Rejection Ratio Parameter Tx PSRR (to Line) Rx PSRR (to Receive output) 4 Fig Condition Symbol Min Typ Max Unit Comment VPSRR=0.1VPP, f=550kHz RX-PGC="00000"=+25.2dB, TX-PGC="00000"=+21.5dB from VDD from VBAT PSRRTDD PSRRTBAT 35 100 dB dB GBD GBD VPSRR=0.1VPP, 25kHz < f <138kHz, RX-PGC="00000"=+25.2dB, TX-PGC="00000"=+21.5dB from VDD PSRRRDD from VBAT PSRRRBAT 54 >80 dB dB GBD GBD EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 PBM 397 05/3 Digital Interface, levels Parameter Fig Condition Input Voltage Low Input Voltage High Input Current Input Capacitance Output Voltage Low OutputVoltage High Symbol Min Typ Max Unit 0.8 V VIL VDD1 = 5 V VIH 2.4 IIL (@VIL), IIH(@VIH) IIL, IIH CI -10 @ IOL = 3.2 mA VOL @ IOL = 3.2mA VOH Comment V 10 10 mA pF GBD 0.4 V GBD V GBD 2.8 Digital Interface, timing Parameter Condition Symbol Min Data clock frequency Applicable range with rise and fall times <10ns Of digital input waveforms fMCLK 0.1 t r, t f TBD Rise and fall times Typ Max Unit Comment 35 MHz GBD ps GBD Reference Voltages and Currents Parameter Condition VREF2.2 voltage IREF voltage Symbol VVRef2.2 VIRef Min Typ 0.429xVDD1 1.20 Max Unit 0.440xVDD1 0.447xVDD1 1.25 1.30 V V Line Driver DC Characteristics Parameter Condition Symbol Min Typ Max Unit Differential Output Offset Voltage* No input signal, Input offset VVTXIN-VVTXINB = 0 TX-PGC="00000"=21.5dB Output Offset voltage, VSB1-VSB2, open circuit load No input signal, Input offset VVTXIN-VVTXINB = 0, Relative VBAT/2, TX-PGC="00000"=21.5dB VLong = (VSB1 + VSB2)/2 VLIN -1000 240 1000 mV VOLine -150 0 150 mV VTXINO -15 0 15 mV VTXInLong -15 0 15 mV Longitudinal Output Offset Voltage Differential Input Offset Voltage at TXIN Common Mode input Offset Voltage at TXIN Relative VREF2.2 Comment Note : In above table 'LINE' refers to currents or voltages on primary (25W) side of 1:2 line output transformer. * The DC current flowing through the transformer can easily be calculated from the open circuit DC offset by using the Equation below. UO = Open circuit offset voltage UO Ik = RSH = Shunt Resistor in the complex impedance network ZS 11.5 x RSH + RL RL = Resistance in the transformer winding Receive Path DC Characteristics Parameter Condition Symbol Min RP-RN Differential Output Voltage RP, RN Longitudinal Output Voltage No Input signal, RX-PGC = "00000" (+25.2dB), Measured with RLoad = 0W VRXDiff No input signal, Relative VRREF, RX-PGC = "00000" (+25.2dB) VRXLong EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 Typ Max Unit -200 0 200 mV -50 0 +50 mV Commemt 5 PBM 397 05/3 Line Driver Termination Impedance Parameter Condition Differential output impedance Measured differentially across load pins (SB1, SB2) with RAB=2.2W and f=25kHz Symbol Control word = "10000" (default) Control word = "00000" (min) Control word = "11111" (max) Min Typ ZTLINE(10000) 25 ZTLINE(00000) 17 ZTLINE(11111) 32 27 18 36 DZTLINE Max Unit Comment W W W GBD 0.5 W GBD 29 19 40 Output impedance step size Measured differentially across load pins (SB1, SB2) with RSX=2.2W and f=500kHz Default control word ="10000" Termination impedance frequency response Impedance @ 1.1MHz relative impedance @ 25kHz Default control word ="10000" ZTf1.1M 2.4 W GBD Termination impedance phase shift Impedance phase @ 1.1MHz relative impedance @ 25kHz Default control word ="10000" FZTf1.1M 21 GBD Over Temperature Protection Parameter Condition ON Temperature OFF Temperature Symbol Min Typ Max Unit TON TOFF 140 125 145 130 150 135 C C Symbol Min Typ Max Line Driver Transmission Characteristics Parameter Comment Fig Condition Unit Driver output Clip voltage Max VTXIN, TX-PGC = "00000" (+21.5dB), VDD1=VDD2=5.0V, VBAT = 10.0V, measure VSB1-VSB2 VOLCLIP 15.1 15.2 V GBD Slew rate 2Vpp input square wave, Output measured differentially at SB1, SB2 . Slew rate measured for rising and falling edges between 10% and 90% levels. SRLINE 40 150 V/ms GBD Absolute differential voltage gain, TXIN to LINE V in =0.1Vrms fsine = 25kHz, Max PGC = "00000" (21.5dB) fsine = 1.1MHz, Max PGC = "00000" (21.5dB) fsine = 25kHz, Nom PGC = "01110" (7.5dB) fsine = 1.1MHz, Nom PGC = "01110" (7.5dB) fsine = 25kHz, Min PGC = "10101" (0.5dB) fsine = 1.1MHz, Min PGC = "10101" (0.5dB) Signal TXIN to LINE GTX25 GTX1.1M GTX25 GTX1.1M GTX25 GTX1.1M 21.4 21.6 7.4 7.2 0.4 0.2 21.8 22.0 7.8 7.6 0.8 0.6 Vin=0.1Vrms, fsine=1.1MHz DGTX=GTX(25kHz) - GTX (1100kHz) Signal TXIN/TXINB to SB1/SB2 DGTX -0.15 dB GBD TXSTP 1.0 dB GBD fTXD -6 GBD fTXDE 2.5 GBD Frequency response TX-PGC step size Phase response Vin=0.1Vrms, fsine=1.1MHz DfTXD=fTX(25kHz) - fTX(1100kHz) Signal TXIN/TXINB to SB1/SB2 Differential phase error* Vin=0.1Vrms, fsine=1100kHz, phase at VOLDC=40%of VOLCLIP rel. phaseatVOLDC=0V 6 22.2 22.4 8.2 8.0 1.2 1.0 dB dB dB dB dB dB GBD GBD GBD GBD EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 PBM 397 05/3 Line Driver Transmission Characteristics continued ... Parameter SFDR, sine at output, single tone Fig Condition fsine fsine fsine fsine =25kHz, 8.0Vpp on output =138kHz, 8.0Vpp on output =250kHz, 8.0Vpp on output =400kHz, 8.0Vpp on output fsine =400kHz, 14.0Vpp on output fsine =400kHz, 1.0Vpp on output MTPR transmit multitone Symbol Min Typ Max Unit SFDR25k SFDR138k SFDR250k SFDR400k 53 51 47 44 58 70 dB dB dB dB GBD GBD SFDR14 SFDR1 42 57 dB dB GBD fmultitone=150kHz - 1.1MHz, MTPR measured relative notches, Power Mode=2 TX-Band : 150kHz-1.1MHz MTPR5.0TX @bin37=160kHz, bin57=245kHz, bin117=504kHz bin174=750kHz, bin234=1MHz, PAR=5.0 bin37=160kHz, bin57=245kHz, bin117=504kHz, MTPR3.8TX bin174=750kHz,bin234=1MHz, PAR=3.8 PAR=3.8, PSD=-40dBm/Hz (11.7Vpp), TX-PGC=15.5dB PAR=5.0, PSD=-40dBm/Hz (15.4Vpp), TX-PGC=17.5dB MTPR transmit multitone -into Rx band fmultitone=150kHz - 1.1MHz, MTPR measured relative Rx-band, Power Mode=2 300Hz-4.3kHz, PAR=5.0 (Speech Band) MTPR 5SP 25-138kHz, PAR=5.0 (RX Band) MTPR5RX 300Hz-4.3kHz, PAR=3.8 (Speech Band) MTPR 3SP 25-138kHz, PAR=3.8 (RX Band) MTPR3RX on driver output PAR=3.8, PSD=-40dBm/Hz (11.7Vpp), TX-PGC=15.5dB PAR=5.0, PSD=-40dBm/Hz (15.4Vpp), TX-PGC=17.5dB MTPR transmit multitone -into "out of band" band fmultitone=150kHz - 1.1MHz, MTPR measured relative Out Of-band: > 1.1MHz on driver output Power Mode=2 MTPR5.0OB PAR=3.8, PSD=-40dBm/Hz (11.7Vpp) MTPR3.8OB PAR=5.0, PSD=-40dBm/Hz (15.4Vpp) Idle noise floor at output No input signal. TXP, TXN connected to VREF2.2. Noise floor measured across SB1, SB2, TX-PGC= "00111" (+14.5dB) 300Hz-4.3kHz 25kHz-138kHz 150kHz-1.1MHz 1.1MHz-11.04MHz Unbalance_TL 6 Vin=1Vrms, RL = 2x12.5W, measured at load midpoint, ratio (dB) to Differential signal across load. 25kHz 500kHz 1.1MHz Unbalance_LT 6 Vin load mid = 1Vrms, RL = 2x12.5W, measure VSB1-VSB2, ratio (dB) to Differential signal across load. 25kHz 500kHz 1.1MHz TX input impedance Comment TX-PGC= "00111" (+14.5dB) f < 1.1 MHz EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 NFLINEidle 44 47 dB 47 50 dB 49 31 51.5 41.0 55 42 59.0 51.5 dB dB dB dB 39 36.0 42 39.0 dB dB -92.0 -104.0 -107.5 -109.0 UNBTL UNBLT ZinTX 4.9 -87.0 dBm/Hz into 25W -101.0 -106.0 -107.5 GBD -34.5 -34.5 -31.0 dB dB dB GBD -30 -28 -23 dB dB dB GBD GBD GBD kW GBD GBD 7 PBM 397 05/3 Receive Path Transmission Characteristics Parameter Fig Condition Symbol Min VRXOCLIP 5 Typ Max Unit Comment Vpp GBD V/ms GBD Receive output clip voltage VLINE=2Vpp, fsine=25kHz, RxPGC = "00000" (25.2dB), measured differentially at ROUTP/ROUTN, *)VBAT = 10V. Receive output slew rate 2Vpp input square wave, Output measured SRRO differentially at ROUTP/ROUTN. Slew rate measured for rising and falling edges between 10% and 90% levels, RX-PGC="10100" (6.2dB) 20 50 Absolute differential voltage gain VLINE=0.2Vpp (input to SB1/SB2), fsine=25kHz, RX-PGC="10111" (3.2dB), measure LINE to Receive output ROUTP/ROUTN, TX-PGC = "00111" (+14.5dB) RX-PGC = "00000" (+25.2dB), @25kHz GRX 1.3 1.7 2.1 dB GRX 23.2 23.6 24.0 dB GBD Frequency response VLINE=0.2Vpp, fsine=138kHz, RX-PGC="00110" (20.2dB) DGRX=GRX (25kHz) - GRX (138kHz) measure gain LINE to ROUTP/ROUTN DG RX 0.3 0.0 -0.3 dB GBD Phase response Vin=0.2Vpp, fsine=138kHz, RX-PGC="10001" DfRX (+9.2dB) DfRX = fRX(25kHz) - fRX (138kHz) measure phase LINE to ROUTP/ROUTN -3 TBD GBD Differential phase error* 0.2Vpp sine wave at f=138kHz, RXPGC="10001" (+9.2dB), phase at VRXOUTDC = 40% of VRXOCLIP relative phase at VRXOUTDC = 0V RxPGC step size Rx SFDR, sine Rx MTPR-into Rx band, multitone Rx idle noise floor 8 fRXE 0.25 GBD RxPGC_stp 1.0 dB GBD 54 54 dB dB GBD GBD 68.0 68.0 68.0 dB dB dB GBD GBD dB GBD TX-PGC = "00111" (+14.5dB) a) RX-PGC="00000" (+25.2dB) fsine = 25kHz, ULINE = 0.11Vpp, URX = 2.0Vpp fsine =138kHz, ULINE = 0.11Vpp, URX = 2.0Vpp SFDRRA25k SFDRRA138k c) RX-PGC="00000" (+25.2dB) fsine = 138kHz, ULINE = 0.22Vpp, URX = 4.0Vpp fsine =138kHz, ULINE =0.165Vpp, URX =3.0Vpp fsine =138kHz, ULINE =0.055Vpp, URX =1.0Vpp SFDRRC4 SFDRRC3 SFDRRC1 VinLINE = 0.39Vpp, PAR = 3.8, RX-PGC="00110" (+20.2dB) fmultitone = 25kHz - 138kHz MTPR measured relative notches @bin13=56063kHz and MTPRR6 @bin24=103.5kHz No input signal, RxPGC= "00000" (+25.2dB) Noise Floor transformed to LINE 300Hz - 4.3kHz 25kHz - 138kHz 150kHz - 1.1MHz 1.1MHz - 11.0MHz NFidleRX 71.5 53 55 -122.0 dBm/ GBD -121.0 Hz into -125.0 25W -128.0 GBD EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 PBM 397 05/3 Transmit to Receive Path AC Characteristics (Echo Cancellation) Parameter Echo cancellation multitone MTPR transmit multitone -into Rx band Fig Condition Symbol Min Typ Max Unit Comment TX: multitone = 150kHz-1.1MHz applied to TXP/TXN, Uin = 2.0Vpp, PAR=5.0, PSDLINE = -40dBm/Hz, TX-PGC="00100" (+16.5dB), RxPGC= "00000" (+25.2dB) Power Mode = 2 Echo_cancellation = spectrum(LINE)-spectrum(RXOUT) Echo Canc, @f=150kHz, Echo Canc, @f=500kHz, Echo Canc, @f=1.1MHz, EC150k EC500k EC1.1M 24 14 8 dB dB dB GBD GBD GBD fmultitone=150kHz-1.1MHz, MTPR measured relative Rx-band: Power Mode=2 25kHz, PAR=5.0 138kHz, PAR=5.0 25kHz, PAR=3.8 138kHz, PAR=3.8 MTPR 5RA1 MTPR 5RA2 MTPR 3RA1 MTPR 3RA2 TBD TBD TBD TBD dB dB dB dB GBD GBD GBD GBD on RX Output, RX-PGC="00000" (+25.2dB) PAR=3.8, PSD=-40dBm/Hz (11.7Vpp), TX-PGC=+15.5dB PAR=5.0, PSD=-40dBm/Hz (15.4Vpp), TX-PGC=+17.5dB Echo cancellation singletone TX:single tone with fs applied to TXP/TXN, Uin = 1.5Vpp, TX-PGC = "00111"(+14.5dB), RxPGC = "00000" (+25.2dB) Echo_cancellation at RXOUT, transformed to LINE Echo Canc, @fs = 150kHz, fundamental, fs first spurious, 2xfs second spurious, 3xfs EC150k0 EC150k1 EC150k2 25.5 19.5 30.5 30.0 31.0 33.0 dB dB dB Echo Canc, @fs = 400kHz, fundamental, fs first spurious, 2xfs second spurious, 3xfs EC40k0 EC400k1 EC400k2 28.0 26.0 35.0 34.0 40.0 41.0 dB dB dB 1. Apply the multitone at TX, measure the fundamental levels on LINE 2. Transform this fundamental level to RXOUT by adding the RX-PGC factor 3. Measure the spectrum at RXOUT and calculate MTPR from the fundamental level calculated in 2. Transmitter Output Spectral Mask The required spectral mask from the standard is met, provided that the driver is connected to the line via the proposed hybrid (transformer and LINE capacitor combination) and provided that the driver is driven from a DAC with at least 6dB lower distortion and noise floor than the PBM 39705/3 TX path. See figure 5. Balance Longitudinal - Transversal A TXP PBM 39705/3 12.5 uT PSD (dBm/Hz) uLONG 12.5 -36.5dBm/Hz peak TXN uin 36dB/oct 21dB/oct B Transmit Band MTPR > 38dB Balance LT = 20log(uT/uL) Max transmitted total power :+19.8dBm Balance Transversal - Longitudinal A -110dBm/Hz -97.5dBm/Hz TXP PBM 39705/3 12.5 4 25.875 1104 4545 f (kHz) uT uin uLONG 12.5 TXN B Balance TL = 20log(u L/uT) Figure 5. Transmitted spectral mask. EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 Figure 6. Longitudinal balance measurement. 9 PBM 397 05/3 VBAT VBAT VDD2 SUBH TVP OTPR OTPO TVN Pin Description VDD1 SA1 VREF2.2 SB1 DR1 NC IREF VSS3 PBM 39705 RP VSS3 DR2 NC RN SB2 VSS1 VBAT VBAT VSS2 RS DCLK DEN PD DIN SA2 Pin Name Description 1 SA2 1 of 2 current sense input pins for B-wire to define current gain. Supply/GND A/in x A/out D/in Misc 2 SB2 Current and voltage sense input for B-wire to define current gain and impedance. x 3 DR2 Drive output to line, B-wire. 4 VSS3 Ground For Driver High Current Output Stage. x 5 VSS3 Ground For Driver High Current Output Stage. x 6 DR1 Drive output to line, A-wire. 7 SB1 Current and voltage sense input for A-wire to define current gain and impedance. x 8 SA1 1 of 2 current sense input pins for A-wire to define current gain. x 9 VBAT Battery sourcing drive output current (VBAT). x High Cur 10 VBAT Battery for setting half supply voltage level on drive output pins 3 & 6. This is normal connected to the same supply as VBAT. x High Cur 11 VDD2 Main positive supply input for signal currents, except for drive output currents. x High Cur 12 SUBH Connection to substrate used to isolate high voltage and high current output transistors from low voltage side to reduce crosstalk via the substrate. x 13 TVP Transmit input voltage, ~2.4kW to internal 2.2V reference 14 OTPR Over temperature protection resistor 15 OTPO Over temperature protection output indicator, active high, can be used directly to power down the chip or to indicate high chip temperature. 16 TVN Transmit input voltage, ~2.4kW to internal 2.2V reference. 17 VDD1 5V supply for bias network and for digital serial bus and register. Sensitive Sensitive x High Cur High Cur High Cur x High Cur Sensitive Sensitive Sensitive x Sensitive x x x Sensitive x 18 VREF2.2 Buffered output of internal 2.2Volt reference, used to bias tx input circuit via package bond-out arrangement and also to provide receive reference voltage, to pin22, for the receive output. High Cur x Sensitive Current bias generation. A resistor to ground, pin 24, sets the bias current for all the internal circuits. Nominal resistor value used is 25kW, but could be nearest preferred value. (x) Sensitive 21 RP Receive output signal, differential with signal from pin 23. The receive signal appearing at pins 21 and 23 is echo cancelled to ~>20dB from the transmit signal for frequencies up to 300KHz. x 22 NC Do not use. 19 NC Do not use. 20 IREF 23 RN Receive output signal differential to that on pin 21. 24 VSS1 Ground for all dc chip biasing and for connection to substrate on the low voltage side of the chip. It is also the ground for the digital and the main ESD ground for the chip. 25 PD Active high, 3.3V or 5V compatible input to power down the chip except for the bandgap, on-chip temperature monitor and a few other low current circuits. x 26 DIN Serial DATA signal input. 3.3V and 5V compatible x 27 DEN Active pulsed low DATA ENABLE input. 3.3V and 5V compatible. All settings are updated on the falling edge of this signal. x 28 DCLK DATA CLOCK input. 3.3V and 5V compatible. x 29 RS Active high RESET input. 3.3V and 5V compatible. Resets defaults values for Transmit gain, Receive gain, Impedance and Standby on the negative edge. DEN must be pulsed low during reset. 30 VSS2 Main signal ground for chip, except for drive output currents. x High Cur 31 VBAT Battery sourcing drive output current (VBAT). x High Cur 32 VBAT Battery sourcing drive output current (VBAT). x High Cur 10 x x High Cur x EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 PBM 397 05/3 LQFP package outline e Common dimensions Typ Max 1.40 1.50 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 - 0.20 e 0.8 BSC D 9.00 BSC D1 7.00 BSC E 9.00 BSC E1 7.00 BSC L 0.45 L1 O2 0.60 A2 A1 b C D D1 02 E1 A A A E Min A N 0.75 L L1 1.00 Ref 11 12 13 1 2 3 Functional Description The PBM 397 05/3LQ is a complete ADSL line interface circuit, optimized to be used at the Central Office (CO) side. different output voltages is given in the table 1. The drive outputs are centred on VBAT/2 DC level using a longitudal loop. See figure 7. Standard Requirements The PBM 397 05/3LQ is a complete integrated Analog line driver and receiver for ADSL (Assymetrical Digital Subscriber Line). The device handles both full-rate ADSL (G.DMT as standardized in ITU G.992.1 and ANSI T1.413 Issue 2) and ADSL-Lite (G.Lite as standardized in ITU G.992.2) . Serial digital control interface The driver is programmable in order to maximize the performance and minimize the Power consumption. The programmability is controlled via a serial control interface. The interface has a chip select signal (DEN), that enables the same digital bus to be used for all line drivers on a line card, reducing board area. The digital interface can be programmed from either 3.3V or 5V circuits. See Figure 8. 2.2V VBAT(+10V) VDD(+5V) Two Power Supplies The PBM 397 05/3LQ requires two power supplies: VBAT (6-11V) for the final drive output stage, and VDD (5V) for the rest of the device. VDD shall always be set to 5.0V. For applications with long lines , it is recommended to use a typical supply voltage VBAT of 10.5V, but as the line gets shorter, the power supply (and thus the power consumption) can be reduced. The recommended power supply voltage for TXIN Line Length (AWG 26) VBAT/2 2.2V 2.2V 2.2V VBAT/2 GROUND RXOUT The following functions can be programmed : * Transmit gain (-1.7db to +21.3dB in 1dB steps). In order to be able to perform Power Cut Back in 1dB steps between -38dBm/Hz to -52dBm/Hz, according to the ADSL standard. * Receive gain (-4.7dB to +25.3dB in 1dB steps) in order to give a high SNR (Signal to Noise Ratio) before the AD converter for all line lengths. Figure 7. Power supplies and DC levels for the PBM 397 05/3LQ. EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 LINE > 800m 600m 500m 400m < 300m Uout tot (Vpp) VBATmin (V) 16.4 13.3 10.7 8.8 7.4 10.5 8.7 7.2 6.0 6.0 Table 1. Line length. 11 PBM 397 05/3 Active Drive/Termination Impedance The circuit is able to deliver 15.5Vpp into a 25W load, enough to transmit ADSL signals between 150kHz and 1.1MHz with a Power Spectral Density (PSD) of -40dBm/ Hz into 100W via a 2:1 transformer or a total power of 19.8dBm (3.08Vrms) with a PAR (Peak to Average Ratio) value up to 5.2, while receiving an upstream band between 25kHz and 138kHz, according to the ANSI (T1.413 Issue 2) and ETSI ADSL standards. The line driver manages to meet this performance with an output stage fed between 0 and 10.5V and a total power consumption of 850mW. This is possible by the use of Ericsson Microelectronics patented active termination/ drive impedance scheme for ADSL. See figure 11. The active drive/termination impedance principle. The active termination concept means that no high ohmic series resistors are needed in series with the driver output, which reduces the power suppy voltage needed to transmit a given power to the line. All that is needed is a low-ohmic (in the ADSL band) sense impedance in series with the output. Power Down PBM 397 05/3LQ has a power down function (through the PD pin), that completely shuts down the circuit. This pin can be directly connected to the OTPO pin (the Over Temperature detection Output), so that the circuit is automatically shut down during error conditions. Programmable transmit gain Programmable transmit gain enables power cut-back according to standard and easy implementation of extended power cut-back. ANSI T1.413 requires that the Transmitted Power Spectral Density (PSD) to the line should be reduced in 2dB steps from -40dBm/Hz down to -52dBm/Hz when the line length (and the line damping) is reduced. Integrated Over Temperature Protection In order to protect the circuit from damage during error conditions, such as short circuit, there is an on-chip over temperature detection circuit (OTP). During overtemperature conditions the digital over temperature detector output (OTPO) is set high and can either be monitored by the system processor or connected directly to the Power Down pin of the PBM 397 05/3LQ. The OTP has 15 degrees centigrade built-in hysteresis to avoid thermal oscillation effects. See figure 9. +5V C VBAT C TP C TN ROTP VDD C VDD2 TVN OTPO OTPRTVP SUBH VDD2 VDD +5V Drive Tx VDD1 VBAT VBAT PBM 39705/3 OTP C VDD1 VBAT 6-11V DR1 SA1 DA IMP Tx gain TX-PGC SB1 VREF2.2 RREF -5- +25dB B RP SB2 PGC RX-PGC RN VSS1 SA2 Drive DIN DEN DSP DR2 IMP Control PD LINE C LB RSHB CRN T1 C LA C OB VSS3 RSB C SB AD STBY IREF IMP CRP Ref & Bias A VSS3 EC RSHA * Termination impedance (17-32.5W in 0.5W steps) in case the user wants to be able to tune the impedance without changing any external components. However, it is recommended, to achieve the best performance to set the programmable impedance to 25W and use the complex termination impedance described in the application drawing. Power mode : The device can be set in either power mode 0-2 for full ADSL transmission. In the remaining power modes (3-7), ADSL transmission is also possible, but with limited performance (could be used for example on short lines or lines which are very noisy or when no data is sent). See figure 10. RSA C SA * DCLK RS VSS2 VBAT VBAT C VBAT VBAT 6-11V Overview. 12 EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 PBM 397 05/3 The PBM 397 05/3LQ has been designed to meet this requirement when connected to DA converters (or amplifiers) with a max output swing between 1.5Vpp and 4.0Vpp. It is also possible to adjust the transmit power, since the TX-PGC step is 1dB. The TX-PGC is controlled through the serial control interface. The principle for calculating the internal Transmit Gain is shown in figure 12. Differential Input- and Output Interfaces The transmit input interface is a differential voltage interface. The driver should be connected to the output from the DAC via AC coupling capacitors. The maximum transmit input swing is 4Vpp, and the TX inputs have a common-mode level of 2.2V. See figure 13. The Receive output interface is also differential and of voltage type. The RX outputs should be connected via external AC-coupling capacitors to the AD converter input. The maximum output swing is 4Vpp. The RX outputs have a common mode level of 2.2V. See figure 14. Integrated echo cancellation circuit In an ADSL system, the key performance parameter is the MTPR (Multi Tone Power Ratio) of the receive signal. In order to maximize the MTPR, the PBM 397 05/3LQ has an integrated echo canceller that removes around 25dB of the transmitted signal from the Receive Path. In order to further reduce the transmitted echo signal to the receiver, a first order low pass filter with a corner frequency of 300kHz has been integrated. A 10kHz high pass filter is also integrated in the receive path to reduce POTS signals. It is important to note that it is not only the fundamental transmitted tones that are echocancelled, but also noise and distortion from the driver will be cancelled to the receive path. This enables higher transmit distortion and noise in the transmit path without sacrificing bitrate. See figure 15 and 16. How to choose ZS A good echo cancellation is achieved when the drive/ termination impedance of PBM 39705 matches the load impedance (the line seen through the transformer and the high-pass filter LINE capacitors). The expression for the termination impedance is given by: ZOut = 11.5 ZS The PD signal can either be tied to ground, or connected to OTPO for each LINE The RS (reset) signal can be tied to Ground. PBM39705/3 LINE1 PBM39705/3 LINE2 DIN/DCLK (Common) DEN1 DSP/ 3.3 or 5V digital levels Control OTPO DEN2 High LINE3 PBM39705/3 DEN3 Hyst LINE#N PBM39705/3 Low DEN#N T OFF =130 C Figure 8. Digital control routing on a multiline board. T T ON =145 C Figure 9. Over Temperature Protection (OTP). Dynamic Static 1200 1200 PM0 1000 PM0 1000 PM1 PM1 800 PM2 PM3 PM4 PM5 PM6 PM7 800 PM2 PM3 600 600 PM4 PM5 400 400 PM6 PM7 200 0 200 6 7 8 9 10 11 0 6 7 8 9 10 11 Figure 10. Static and dynamic power consumption in active mode vs VBAT (VDD=5.0V). EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 13 PBM 397 05/3 To get the optimum performance, ZS must be chosen for a specific transformer and line capacitor combination. The proposed solution from Ericsson Microelectronics is to use the Schott transformer 32828 in combination with two 150nF LINE high pass filter capacitors. Ericsson Microelectronics can also provide ZS for other transformer/LINE capacitor combinations on request. The propsed ZS is optimized to give the best impedance matching in the ADSL-band for the AWG26 (0.4mm) cable, but the proposed ZS will work fine for the AWG24 (0.5mm) cable as well. See figure 17 and 21. The termination/drive impedance of the PBM 39705/3LQ is obtained by using: ZOut = 11.5 x Rsh x (1+2pf x Cs x Rs) 1 + 2pf x Cs x (Rs + Rsh) The factor 11.5 is valid for the nominal impedance setting: "10000" and can be varied between 7.8 and 15.0. The impedance in equation above shall now be matched with the load impedance of the driver, ie the terminated transmission line seen through the transformer and the LINE high-pass filter capacitors. High range Receive Programmable Gain (PGC) The signal levels after echo cancellation is very low. In order to get a maximal MTPR at the AD converter input, the signal level must be boosted up to match the optimal input swing for the AD converter. This is achieved by using a Programmabe Receive Gain (PGC). The RX gain from the line driver output to the Receive outputs can be varied via the serial digital interface in 1dB steps between -4.7dB and +25.3dB. Normally the lower PGC values are used for shorter lines and higher PGC's are used for longer lines. The PGC to be used will be set from the DSP during the training sequence of the ADSL connection. Equivalent Circuit PSD RX PSD TXIN Zin LINE Spectrum on LINE TX MTPR Low Ohmic Sense Impedance, ZS ZT=ZL/2 ZL ZL RX Noise & Dist PSD Low Ohmic Sense Impedance, ZS ZT=ZL/2 Noise & Dist Floor MTPR 4.3kHz f Figure 11. Drive impedance. uin SA1 DRIVE1 SB1 TXIN Figure 15. The spectrum on the LINE. Spectrum on RXOUT TX-PGC=20log(uo/uin) PSD ZSA Echo Cancellation uo PBM 397 05/3 LINE TX RX ZSB MTPR Noise & Dist Floor Figure 12. Calculating the transmit gain (TX-PGC). Common Mode = 2.2V Zin = 4.8k For Schott 32828 or BelFuse S560-6600_AB and 2x68nF R SHA , R SHB SA1,2 TXP Max 4.0Vpp TXN R SA , R SB CSA , CSB Figure 13. The differential transmit input interface. f Figure 16. The spectrum on the receive output. ZS CTP CTP Dist Cancellation SB1,2 SB2 DRIVE2 SA2 RXOUT R SHA , R SHB = 45.3 R SA , R SB = 2.7 CSA , CSB = 680nF Zs = Rsh (1 + 2f Cs Rs) 1 + 2f Cs (Rs + Rsh) Figure 17. Proposed ZS. Max 4.0Vpp RXP Common Mode = 2.2V PBM 397 05/3 Secondary Protection Primary Protection RXN Figure 14. The differential receive output interface. 14 Figure 18. Over Voltage Protection. EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 PBM 397 05/3 Resetting the device There is a default programming for the device. This default word is automatically loaded into the register when the device is reset. See figure 20. There are two ways of resetting the device without sending any serial data : 1. Power -On Reset : Once the power supply VDD is applied to the device, the PBM 397 05/3LQ will be reset automatically. 2. Reset via the RS pin : Provided that DEN is held low, the PBM 397 05/3LQ is reset once the RS pin is set high. Once the reset has been made, the RS pin must be brought low again, to ensure proper function of the programming. Over Voltage Protection In a Central Office protection, it is recommended to use a primary protection outside the transformer and a secondary protection inside the transformer, see fig 18. At the moment, Ericsson Microelectronics has a proposal for an OVP scheme for the PBM 39705/3LQ, but this scheme need to be verified practically. Programming The Device The device is programmed by using the Serial Data Control Interface (DIN, DCLK & DEN). The Serial Control Word is 18 bits wide. Bit 17 is sent first and Bit 0 is sent last. Data is clocked in on each clock cycle, positive edge. After all bits have been read in, the DEN signal should be pulsed low for the new settings to take effect. See figure 19. Important! On a board with many lines : All DEN must be set high, before a new serial data word could be sent. Transmit Gain (5 bits) 17 16 15 14 13 Receive Gain (5 bits) 12 11 10 9 8 Term. Impedance (5 bits) 7 6 5 4 3 Power (3 bits) 2 1 0 T4 T0 R4 R0 I4 P2 T3 T2 T1 R3 R2 R1 I3 I2 I1 I0 P1 P0 fmax = 35MHz fmin = 100kHz DCLK DEN DIN B17 B16 B2 B1 B0 Programming Settings Take Effect Figure 19. The function of the serial control interface. 110 100 90 fmax = 35MHz fmin = 100kHz 80 DEN 70 60 RS Driver 50 Line Through Hybrid Reset taking effect 40 30 20 10k Figure 20. Resetting the device. EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 100k frequency (Hz) 1M 10M Figure 21. Impedance matching between line driver and the line (AWG 26 cable) seen through the transformer and high pass filter capacitors. 15 PBM 397 05/3 Transmit Gain Control (TX-PGC) Supporting Full Power Cut Back [T4 .. T0 ] TxPGC (res Zs) TxPGC (complex Zs) Comments 00000 21.5 dB 21.3 dB @ 150kHz 00001 20.5 dB 20.3 dB 00010 19.5 dB 19.3 dB 00011 18.5 dB 18.3 dB 00100 17.5 dB 17.3 dB 00101 16.5 dB 16.3 dB 00110 15.5 dB 15.3 dB 00111 14.5 dB 14.3 dB 01000 13.5 dB 13.3 dB 01001 12.5 dB 12.3 dB 01010 11.5 dB 11.3 dB 01011 10.5 dB 10.3 dB 01100 9.5 dB 9.3 dB 01101 8.5 dB 8.3 dB 01110 7.5 dB 7.3 dB 01111 6.5 dB 6.3 dB 10000 5.5 dB 5.3 dB 10001 4.5 dB 4.3 dB 10010 3.5 dB 3.3 dB 10011 2.5 dB 2.3 dB 10100 1.5 dB 1.3 dB 10101 0.5 dB 0.3 dB 10110 -0.5 dB -0.7 dB 10111 -1.5 dB -1.7dB 11000 - 11001 - - -"- 11010 - - -"- 11011 - - -"- 11100 - - -"- 11101 - - -"- 11110 - - -"- 11111 - - -"- 16 - Use when transmitting 150 kHz - 1.1 MHz with -40 dBm/Hz and PAR = 5.3x from a 2.0 Vpp DAC Default when reset Use when transmitting 150 kHz - 1.1 MHz with -40 dBm/Hz and PAR = 5.3x from a 4.0 Vpp DAC Use when transmitting 150 kHz - 1.1 MHz with -52 dBm/Hz and PAR = 5.3x from a 2.0 Vpp DAC Use when transmitting 150 kHz - 1.1 MHz with -52 dBm/Hz and PAR = 5.3x from a 4.0 Vpp DAC Not Valid EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 PBM 397 05/3 Receive Gain Control (RX-PGC) [ R4 .. R0 ] Rx PGC (res Zs) Rx PGC (complex Zs) Comments 00000 +25.2 dB +25.3 dB @ 80kHz (fc for the upstream Receive Band) 00001 +25.2 dB +25.3 dB To be used on long lines 00010 +24.2 dB +24.3 dB 00011 +23.2 dB +23.3 dB 00100 +22.2 dB +22.3 dB 00101 +21.2 dB +21.3 dB 00110 +20.2 dB +20.3 dB 00111 +19.2 dB +19.3 dB 01000 +18.2 dB +18.3 dB 01001 +17.2 dB +17.3 dB 01010 +16.2 dB +16.3 dB 01011 +15.2 dB +15.3 dB 01100 +14.2 dB +14.3 dB 01101 +13.2 dB +13.3 dB 01110 +12.2 dB +12.3 dB 01111 +11.2 dB +11.3 dB 10000 +10.2 dB +10.3 dB 10001 +9.2 dB +9.3 dB 10010 +8.2 dB +8.3 dB 10011 +7.2 dB +7.3 dB 10100 +6.2 dB +6.3 dB 10101 +5.2 dB +5.3 dB 10110 +4.2 dB +4.3 dB 10111 +3.2 dB +3.3 dB 11000 +2.2 dB +2.3 dB 11010 +0.2 dB +0.3 dB 11011 -0.8 dB -0.7 dB 11100 -1.8 dB -1.7 dB 11101 -2.8 dB -2.7 dB 11110 -3.8 dB -3.7 dB 11111 -4.8 dB -4.7 dB Default when reset To be used on a 0m line when using a ADC with Uinmax = 4.0Vpp To be used on a 0m line when using a ADC with Uinmax = 3.0Vpp A high Receive PGC is needed to take full advantage of the built-in echo cancellation and echo filtering of the PBM 39705. The Receive PGC to be used should be decided by the DSP during the ADSL training sequence. The total signal on the line is dominated by the transmitted downstream signal compared to the received upstream signal, except for very short lines. The fully integrated echo cancellation circuitry effectively removes around 30dB of the transmitted signal from the EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 receiver, which means an improved dynamic range for the upstream receive signal at the AD convertor, relaxing the requirements on the AD converter linearity and resolution. The lowest PGC shall ensure that the ADSL connection can run at a 0m line without clipping the RX output signal. 17 PBM 397 05/3 Termination Impedance Control (ZT) [ I4 .. I0 ] ZT after 2:1 transformer. ZT, no transformer. 00000 68.0W 17.0W 00001 70.0W 17.5W 00010 72.0W 18.0W 00011 74.0W 18.5W 00100 76.0W 19.0W 00101 78.0W 19.5W 00110 80.0W 20.0W 00111 82.0W 20.5W 01000 84.0W 21.0W 01001 86.0W 21.5W 01010 88.0W 22.0W 01011 90.0W 22.5W 01100 92.0W 23.0W 01101 94.0W 23.5W 01110 96.0W 24.0W 01111 98.0W 24.5W 10000 100.0W 25.0W 10001 102.0W 25.5W 10010 104.0W 26.0W 10011 106.0W 26.5W 10100 108.0W 27.0W 10101 110.0W 27.5W 10110 112.0W 28.0W 10111 114.0W 28.5W 11000 116.0W 29.0W 11001 118.0W 29.5W 11010 120.0W 30.0W 11011 122.0W 30.5W 11100 124.0W 31.0W 11101 126.0W 31.5W 11110 128.0W 32.0W 11111 130.0W 32.5W The impedances given in the table are achieved when using a pure resistive ZSA and ZSB of 2.2W. In order to achieve higher upstream bitrate, it is recommended to use a complex termination impedance by making ZSA and ZSB complex (as in figure 1). By doing so, the echo cancellation is improved considerably, enabling a higher RX-PGC and increasing the MTPR at the AD converter, relaxing the AD converter resolution requirements. When using a complex termination impedance scheme, the target should be to make the output impedance equal 18 Comment Default when reset to the impedance of the line seen through the transformer and LINE capacitors. The proposed values from figure 1 is set to give the best impedance matching for an AWG 26 cable in the ADSL band and the values used are assumed that the programmable impedance code is set to "10000" (or 25W). When using a complex termination impedance, the value of a programmable impedance is less. EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 PBM 397 05/3 Power modes [ S2 ..S0 ] IBATqui* IDDqui** Function Comment 000 76mA 40mA Power 0 Allowing full transmission in both directions 001 67mA 36mA Power 1 Full transmission 010 58mA 32mA Power 2 Recommended for high end applications (lines with low noice), Default when reset 011 49mA 29mA Power 3 Full transmission 100 40mA 25mA Power 4 Good enough for 400kbit/s, 4Mbit/s on 3 km AWG 26 with ETSI noise 101 31mA 22mA Power 5 Slight degradation in bitrate 110 21mA 18mA Power 6 Only recommended as "sleep mode" 111 13mA 14mA Power 7 Tx-path disabled, Rx-path active, Should not be used * Standing Current in high voltage part ** Standing Current in low voltage part In order to save power in sleep mode, the "100" code is recommended : The power consumption is then reduced to 525mW. In this mode, it is still possible to receive a wake-up signal from the CPE. Terminology Ordering Information ADDA: Analogue to Digital, Digital to Analogue converter circuit ADSL: Assymetric Digital Subscriber Line CO: Central Office CPE: Customer Premises Equipment EC: Echo Cancellation FDM: Frequency Division Multiplex GBD: Guaranteed by Design MTPR: Multi-Tone Power Ratio OTP: Over-Temperature Protection OVP: Over Voltage Protection PAR: Peak-to-Average Ratio PGC: Programmable Gain Control POTS: Plain Old Telephony System RX: Receive Direction SFDR: Spurious Free Dynamic Range SNR: Signal to Noise Ratio TBD: To Be Defined Package 32-pin LQFP EN/LZT 146 83R1A (c)Ericsson Microelectronics, November 2001 temp range 0 - 85 C part no PBM 397 05/3LQ 19 Ericsson Microelectronics SE-164 81 Kista, Sweden Telephone: +46 8 757 5000 Internet: www.ericsson.com/microelectronics For local sales contacts, please refer to our website or call: Int + 46 8 757 4700, Fax: +46 8 757 4776 Preliminary Data Sheet EN/LZT 146 83 R1A (c) Ericsson Microelectronics AB, January 2002