01/2013
ARA2017
Programmable Gain Amplier
DATA SHEET - Rev 2.2
FEATURES
• High Linearity, High Output Power Integrated
Amplier with Programmable Gain Control
• Attenuation Range: 0-58 dB, Adjustable in
2 dB Increments via a 3-wire Serial Control
• 33 dB Gain (at Minimum Attenuation)
• Low Distortion Products at Output Power Levels
up to +64 dBmV
• Low Noise Figure and Output Noise
• Frequency range: 5-85 MHz
• 5 V Operation
• Materials set consistent with RoHS Directives.
Surface Mount Package
APPLICATIONS
• DOCSIS 3.0 Data Cable Modems and E-MTAs
• CATV Set Top Boxes
PRODUCT DESCRIPTION
The ARA2017 is a highly linear, high output power,
programmable gain amplier optimized for DOCSIS
3.0 cable modem and E-MTA applications. Using a
low noise input amplication stage and an ultra linear
output driver amplier, the device generates extremely
low distortion products at the high output power levels
required by DOCSIS 3.0 signals. Its balanced circuit
design provides superior harmonic performance
and an integrated digitally-controlled, multiple-stage
precision step attenuator enables system solutions to
meet DOCSIS power step accuracy requirements.
S29 Package
28-Pin QFN
5 mm x 5 mm x 1 mm
Figure 1: Functional Block Diagram
The ARA2017 supports output power levels of +64
dBmV while minimizing harmonic, distortion, and
output noise levels. Its precision attenuator provides
up to 58 dB of attenuation in 2 dB increments, which
is set by programming the register via a 3-wire serial
interface. The output stage current, a feature which
allows the device to be operated in reduced power
modes for extended backup battery life, is also
programmed through the 3-wire serial interface. The
ARA2017 is offered in a 28-pin 5 mm x 5 mm x 1 mm
QFN package.
2DATA SHEET - Rev 2.2
01/2013
ARA2017
Table 1: Pin Description
Figure 2: Pinout (X-Ray Top View)
PIN NAME DESCRIPTION PIN NAME DESCRIPTION
1A1
IN+
Amplifier A1 (+) Input 28 A1
OUT+
Amplifier A1 (+) Output and
Supply
2GND Ground 27 ATTN
IN+
Attentuator Input (+)
3A1
IN-
Amplifier A1 (-) Input 26 GND Ground
4GND Ground 25 V
ATTN
Attenuator Supply
5A1
OUT-
Amplifier A1 (-) Output and Supply 24 GND Ground
6ATTN
IN-
Attentuator Input (-) 23 ATTN
OUT+
Attentuator Output (+)
7N/C No Connection 22 A2
IN+
Amplifier A2 (+) Input
8GND Ground 21 A2
OUT+
Amplifier A2 (+) Output and
Supply
9CLOCK Clock 20 GND Ground
10 D ATA Data 19 A2
OUT-
Amplifier A2 (-) Output and Supply
11 ENBL Enable 18 GND Ground
12 N/C No Connection (Reserved for
future use - leave floating) 17 A2
IN-
Amplifier A2 (-) Input
13 TX_EN Transmit Enable 16 ATTN
OUT-
Attentuator Output (-)
14 V
DD
Supply 15 N/C No Connection
3DATA SHEET - Rev 2.2
01/2013
ARA2017
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
Table 3: Operating Ranges
Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under
these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability.
The device may be operated safely over these conditions; however, parametric performance is
guaranteed only over the conditions dened in the electrical specications.
Table 4: Digital Interface Specications
(VDD = +5.0 V)
Note:
(1) Logic control levels apply to the 3-wire programming bus (pins 9, 10, 11) and the transmit
enable control (pin 13).
PARAMETER MIN MAX UNIT COMMENTS
Supply: V
DD
(pins 5, 14, 19, 21, 28),
V
ATTN
(pin 25) 0+6 V
RF Power at Inputs (pins 1, 3) -+40 dBmV differential into 200
Digital Interface (pins 9, 10, 11, 13) -0.5 V
DD
+0.5 V
Storage Temperature -55 +150 °C
PARAMETER MIN TYP MAX UNIT
Logic High Input Voltage: VIN,HIGH +2.0 - VDD V
Logic Low Input Voltage: VIN,LOW 0 - +0.8 V
PARAMETERMINTYPMAXUNIT
Operating Frequency (f)5-8
5M
Hz
Supply: V
DD
(pins 5, 14, 19, 21, 28) +4.5 +5 +5.5 V
Digital Interface (pins 9, 10, 11, 13)0-V
DD
V
Case Te mperature (T
C
)-40 +25+95 °C
4DATA SHEET - Rev 2.2
01/2013
ARA2017
Table 5: Electrical Specications
(VDD = +5.0 V, TX Enabled (unless otherwise noted), TC = 25 8C)
Notes:
(1) As measured in ANADIGICS test xture.
(2) Measured using the maximum current setting-see Application Information section.
PARAMETER MIN TYP MAX UNIT COMMENTS
Gain (1) 34 36 37 dB 0 dB attenuation setting
Gain Flatness (1) -
-
0.5
1.0
-
-dB 5 to 42 MHz
5 to 85 MHz
Gain Variation over Temperature --0.02 -dB/°C
Gain Range with Attenuator 58 - - dB
Incremental Attenuator Step Size 1.5 22.5 dB
2nd Harmonic Distortion Level (1) (2) --67 -55 dBc +64 dBmV into 75
3rd Harmonic Distortion Level (1) (2) --72 -55 dBc +64 dBmV into 75
3rd Order Output Intercept (1) (2) +88 +93 -dBmV 2 tone, +61 dBmV/tone
1 dB Gain Compression (1) (2) -+73 -dBmV
Noise Figure (1) (2) -2.5 -dB
Full gain @ 0 dB attenuator
setting; Includes input balun
loss
Output Noise Power
Active / No Signal / Min. Atten. Set.
Active / No Signal / Max. Atten. Set.
-
-
-38.5
-53.8
-
-dBmV Any 160 kHz bandwidth
from 5 to 85 MHz
Isolation (85 MHz) in Tx disable mode -60 -dB
Differential Input Impedance -200 -between pins 1 and 3
(Tx enabled)
Differential Output Impedance -75 -between pins 19 and 21
Output Impedance -75 -with transformer
Output Return Loss
(75 Ohm characteristic impedance)
-
-
-15
-12
-
-dB Tx enabled
Tx disabled
Output Voltage Transient
Tx enable / Tx disable
-
-
50
7
-
-mVp-p 0 dB attenuator setting
24 dB attenuator setting
Total Supply Current (1) (2)
(pins 5, 14, 19, 21, 25, 28)
-
-
340
10.5
400
-mA Tx enabled (TX_EN high)
Tx disabled (TX_EN low)
Total Power Consumption -
-
1.7
52.5
-
-
W
mW
Tx enabled (TX_EN high)
Tx disabled (TX_EN low)
Thermal Resistance (JC) - 30 -8C/W
5DATA SHEET - Rev 2.2
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ARA2017
DATA PLOTS
Figure 3: Gain vs. Frequency over Voltage
(TC = 25 8C)
Figure 4: Noise Figure vs. Frequency over Voltage
(TC = 25 8C)
1.5
2
2.5
3
3.5
4
020 40 60 80 100 120
NF(dB)
Frequency (MHz)
+5V
+5.25V
+5.5V
+4.75V
+4.5V
VDD
=
33
33.5
34
34.5
35
35.5
36
020 40 60 80 100 120
Gain (dB)
Frequency (MHz)
Figure ?: Gain vs Frequency over Voltage
+5V
+5.25V
+5.5V
+4.75V
+4.5V
V
DD
=
6DATA SHEET - Rev 2.2
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ARA2017
Figure 5: Gain & Noise Figure vs. Temperature
(Vdd = +5V, F1 = 10 MHz)
Figure 6: 1dB Gain Compression (P1dB) vs. Voltage
(Tc = 25 8C, F1 = 10 MHz)
1
2
3
4
5
6
7
30
31
32
33
34
35
36
020 40 60 80 100 120
NF(dB)
Gain(dB)
Case Temperature (TC) -
o
C
Figure ?: Gain & Noise Figure vs. Temperature
( V
DD
= + 5V, F1 = 10MHz )
Gain dB
NF dB
73
73.5
74
74.5
75
75.5
76
76.5
77
4.4 4.6 4.8 55.2 5.4 5.6
P1dB (dBmV)
Voltage (Vdc)
Figure ?: 1dB Gain Compression (P1dB) vs Voltage
( T
C
= 25
o
C, F1 = 10MHz )
7DATA SHEET - Rev 2.2
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ARA2017
Figure 7: 1dB Gain Compression (P1dB) vs. Temperature
(VDD = +5 V, F1 = 10 MHz)
Figure 8: Output Third Order Intercept Point (OIP3) vs. Voltage
(Tc = 25 8C, F1 = 10 MHz, F2 = 11 MHz)
73
73.5
74
74.5
75
75.5
76
76.5
77
020 40 60 80 100 120
P1dB(dBmV)
Case Temperature (
o
C)
Figure ?: 1dB Gain Compression (P1dB)
vs. Case Temperature
( VDD = +5V, F1 = 10MHz )
82
83
84
85
86
87
88
89
90
91
92
4.4 4.6 4.8 55.2 5.4 5.6
OIP3 (dBmV)
Voltage (Vdc)
Figure ?: Output Third Order Intercept Point (OIP3)
vs Voltage
8DATA SHEET - Rev 2.2
01/2013
ARA2017
Figure 7: Output Third Order Intercept Point (OIP3) vs Temperature
(Vdd = +5 Vdc, F1 = 10 MHz, f2 = 11 MHz)
Figure 10: Attenuator Accuracy over Frequency
(TC = 25 8C, VDC = +5V)
0
5
10
15
20
25
30
35
10 20 30 40 50 60 70 80 90 100
Measured Attenuation (dB)
Frequency (MHz)
Figure ?: Attenuator Accuracy over Frequency
2dB
4dB
8dB
16dB
32dB
Tc = 25
o
C, Vdc = +5V
ATTENUATOR SETTING =
85
86
87
88
89
90
91
92
93
94
95
020 40 60 80 100 120
OIP3(dBmV)
Case Temperature(
o
C)
Figure ?: Output Third Order Intercept Point (OIP3)
vs. Case Temperature
9DATA SHEET - Rev 2.2
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ARA2017
Figure 11:Attenuator Accuracy over Voltage
(TC = +25 8C, F1 = 10 MHz)
Figure 12: Attenuator Accuracy over Temperature
(VDC = +5V, F1 = 10 MHz)
0
5
10
15
20
25
30
35
25 35 45 55 65 75 85 95
Measured Attenuation(dB)
Case Temperature (oC)
Figure ?: Attenuator Accuracy over Temperature
2dB
4dB
8dB
16dB
32dB
( V= +5V, F1 = 10mHz )
ATTENUATOR
SETTING =
0
5
10
15
20
25
30
35
4.5 4.6 4.7 4.8 4.9 55.1 5.2 5.3 5.4 5.5
Measured Attenuation(dB)
Supply Voltage, Vdd (Vdc)
Figure ?: Attenuator accuracy over Voltage
2dB
4dB
8dB
16dB
32dB
( Tc = +25
o
C, F1 = 10mHz )
ATTENUATOR SETTING =
10 DATA SHEET - Rev 2.2
01/2013
ARA2017
Figure 13: Gain & Idd vs. Power Control Setting
Figure 14: POUT & Harmonics vs. Power Control Setting
28.00
30.00
32.00
34.00
36.00
38.00
40.00
42.00
44.00
0.00
50.00
100.00
150.00
200.00
250.00
300.00
350.00
400.00
024 6 8
Gain (dB)
Current (mA)
Power Control Setting
(1)
Figure 13: Gain & Idd vs Pcontrol Setting
Current
Gain
-70.00
-65.00
-60.00
-55.00
-50.00
-45.00
-40.00
-35.00
0.00
10.00
20.00
30.00
40.00
50.00
60.00
70.00
0 1 2345678
Harmonics (-dBc)
Pout (dBmV)
Power Control Setting
(1)
Figure ??: Pout & Harmonics vs Pcontrol Setting
Pout
2nd
3rd
11 DATA SHEET - Rev 2.2
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ARA2017
Figure 15: P1dB vs. Power Control Setting
Figure 16: OIP3 & POUT vs. Power Control Setting
Notes (Figures 13-16):
(1) Power control setting refers to the programming register bits 7, 8, and 9 (see Table 6). The power control can be set
using ANADIGICS Tuner Control Software, version 1.2.3, in the “Advanced settings” window. The software is used in
conjunction with the ANADIGICS ARA2017 evaluation board.
40
50
60
70
80
90
0123 4 5 6 7 8
P1dB (dBmV)
Power Control Setting
(1)
Figure 15: P1dB vs Pcontrol
25
35
45
55
65
75
85
95
105
0123 4 5 6 7 8
OIP3 or Pout (dBmV)
Power Control Setting
(1)
Figure 16: OIP3 & Pout vs Pcontrol
OIP3
Pout
12 DATA SHEET - Rev 2.2
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ARA2017
Figure 17: Test Circuit
Notes:
(1) Pin 12 is reserved for future use. Do not connect (leave oating).
(2) Input balun is used for evaluation test purposes only in 75 system. Actual application does not require a 4:1 balun on
the input.
13 DATA SHEET - Rev 2.2
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ARA2017
Table 6: Programming Register
LOGIC PROGRAMMING
Figure 18: Serial Data Input Timing
Programming Instructions
The programming word is set through a 10 bit shift
register via the data, clock and enable lines. The
data is entered in order with the most signicant bit
(MSB) rst and the least signicant bit (LSB) last. The
enable line must be low for the duration of the data
entry, then set high to latch the shift register. The
rising edge of the clock pulse shifts each data value
into the register.
Notes:
(1) Refer to Application Information section for Current and Gain bit settings.
(2) Data bit 0 should always be set to “1”.
(3) Data bit 1 is reserved for future use, and should be set to “0”.
DATA BIT 98 7 6 5 4 3 21 0
FUNCTION Current Gain 0 1
14 DATA SHEET - Rev 2.2
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ARA2017
APPLICATION INFORMATION
Transmit Enable / Disable
The ARA2017 can be switched on (TX enable) and off
(TX disable) via an asynchronous input TX_EN (pin
13). A logic high will turn the amplier on. The gain
and current settings are retained during Tx disable
and do not need to be reloaded.
Gain/Attenuator Setting
The gain of the ARA2017 can be controlled via the
3-wire bus. Data bits D2 through D6 set the gain/
attenuator level, with 00000 being the min gain setting,
and 11111 being the max gain setting. A new gain/
attenuator setting can be loaded while the PGA is on
(TX enable), but will not take effect until TX_EN has
been cycled off /on.
Output Stage Current Setting
The ARA2017 consists of 2 gain stages. The input
stage operates at a constant xed current when TX
is enabled. The current in the output stage can be
controlled via the 3-wire bus. Data bits D7 – D9 set
the current. 111 will set the output stage to maximum
current for maximum linearity. The current can be
lowered for improved efficiency at lower output
power levels, or lower linearity requirements. 000 will
turn both stages off, the same as TX disable. A new
current setting can be loaded while the PGA is on (TX
Enable), but will not take effect until TX_EN has been
cycled off /on.
Output Transformer
Matching the balanced output of the ARA2017 to a
single-ended 75 load is accomplished using a 1:1
turns ratio transformer. In addition to the balanced to
single-ended conversion, this transformer provides the
bias to the output amplier stage via the center tap.
The transformer also cancels even mode distortion
products and common mode signals, such as the
voltage transients that occur while enabling and
disabling the ampliers. As a result, care must be
taken when selecting the transformer to be used at
the output. It must be capable of handling the RF and
DC power requirements without saturating the core,
and it must have adequate isolation and good phase
and amplitude balance. It also must operate over
the desired frequency and temperature range for the
intended application.
15 DATA SHEET - Rev 2.2
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ARA2017
Figure 19: S29 Package Outline - 28 Pin 5 mm x 5 mm x 1 mm QFN
PACKAGE OUTLINE
Figure 20: Branding Specication
ARA2017R
LLLLLNN
YYWWCC
Pin 1 Identifier
Country Code(CC)
Part Number
Lot Number
Date Code
YY=Year WW=Work Week
16 DATA SHEET - Rev 2.2
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ARA2017
Figure 21: Land Pattern
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product
in any such application without written consent is prohibited.
IMPORTANT NOTICE
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice.
The product specications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to
change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed
to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers
to verify that the information they are using is current before placing orders.
DATA SHEET - Rev 2.2
01/2013
17
ARA2017
ORDERING INFORMATION
ORDER
NUMBER
TEMPERAT URE
RANGE
PACKAGE
DESCRIPTIONCOMPONENT PACKAGING
ARA2017RS29P8-40 oC to +95 oC28 Pin QFN Package
5 mm x 5 mm x 1 mm Ta pe and Reel, 2500 pieces per Reel