SN74LVC1G02-EP SINGLE 2-INPUT POSITIVE-NOR GATE www.ti.com SGLS370 - AUGUST 2006 * * * * * * FEATURES * * * * * * (1) Controlled Baseline - One Assembly - One Test Site - One Fabrication Site Extended Temperature Performance of -55C to 125C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Available in the Texas Instruments NanoStarTM and NanoFreeTM Packages * * Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 3.6 ns at 3.3 V Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. (A) (A) DBV PACKAGE (TOP VIEW) 1 A 5 2 GND 3 A VCC GND 4 DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) B B (A) 1 5 VCC B 2 3 A 4 GND 1 5 VCC GND 2 3 4 (A) (A) YEA , YEP , YZA , (A) OR YZP PACKAGE (BOTTOM VIEW) Y 3 4 B 2 A 1 5 Y VCC Y Y See mechanical drawings for dimensions. A. Product Preview DESCRIPTION/ORDERING INFORMATION This single 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G02 performs the Boolean function Y = A + B or Y = A x B in positive logic. NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006, Texas Instruments Incorporated SN74LVC1G02-EP SINGLE 2-INPUT POSITIVE-NOR GATE www.ti.com SGLS370 - AUGUST 2006 ORDERING INFORMATION PACKAGE (1) TA ORDERABLE PART NUMBER NanoStarTM - WCSP (DSBGA) 0,17-mm Small Bump - YEA SN74LVC1G02NYEAREP (3) NanoFreeTM - WCSP (DSBGA) 0,17-mm Small Bump - YZA (Pb-free) -55C to 125C NanoStarTM - WCSP (DSBGA) 0,23-mm Large Bump - YEP SN74LVC1G02NYZAREP (3) Reel of 3000 _ _ _CB_ SN74LVC1G02MYEPREP (3) NanoFreeTM - WCSP (DSBGA) 0,23-mm Large Bump - YZP (Pb-free) (2) (3) SN74LVC1G02MYZPREP (3) SOT (SOT-23) - DBV Reel of 3000 SN74LVC1G02MDBVREP (3) C02_ SOT (SC-70) - DCK Reel of 3000 SN74LVC1G02MDCKREP BUF Reel of 4000 SN74LVC1G02MDRLREP (3) CB_ SOT (SOT-553) - DRL (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition(1 = SnPb, * = Pb-free). Product Preview FUNCTION TABLE INPUTS B OUTPUT Y H X L X H L L L H A LOGIC DIAGRAM (POSITIVE LOGIC) 1 A B 2 TOP-SIDE MARKING (2) 4 2 Submit Documentation Feedback Y SN74LVC1G02-EP SINGLE 2-INPUT POSITIVE-NOR GATE www.ti.com SGLS370 - AUGUST 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range -0.5 6.5 V VI Input voltage range (2) -0.5 6.5 V -0.5 6.5 V -0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current 50 mA 100 mA Continuous current through VCC or GND JA Package thermal impedance (4) DBV package 206 DCK package 252 DRL package 142 YEA/YZA package 154 YEP/YZP package Tstg (1) (2) (3) (4) Storage temperature range V C/W 132 -65 150 C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback 3 SN74LVC1G02-EP SINGLE 2-INPUT POSITIVE-NOR GATE www.ti.com SGLS370 - AUGUST 2006 Recommended Operating Conditions (1) VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VIH High-level input voltage VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 1.5 Low-level input voltage 1.7 V 2 0.7 x VCC 0.35 x VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 V 0.3 x VCC VCC = 4.5 V to 5.5 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 1.65 V -4 VCC = 2.3 V IOH High-level output current -8 -16 VCC = 3 V -32 VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current t/v Input transition rise or fall rate 8 16 VCC = 3 V 32 VCC = 1.8 V 0.15 V, 2.5 V 0.2 V 20 VCC = 3.3 V 0.3 V 10 (1) Operating free-air temperature ns/V 5 -55 125 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback mA 24 VCC = 4.5 V VCC = 5 V 0.5 V TA mA -24 VCC = 4.5 V 4 V 0.65 x VCC VCC = 1.65 V to 1.95 V VIL UNIT C SN74LVC1G02-EP SINGLE 2-INPUT POSITIVE-NOR GATE www.ti.com SGLS370 - AUGUST 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -100 A VOH 1.65 V to 5.5 V MAX 1.65 V 1.2 IOH = -8 mA 2.3 V 1.9 IOH = -16 mA 3V 2.4 V 2.3 IOH = -32 mA 4.5 V IOL = 100 A 1.65 V to 5.5 V 3.8 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 16 mA 3V 0.4 IOL = 24 mA A or B inputs 4.5 V VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ICC One input at VCC - 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND 0.6 0 to 5.5 V 5 A 0 10 A 1.65 V to 5.5 V 10 A 500 A VI = 5.5 V or GND Ioff (1) V 0.55 IOL = 32 mA II UNIT VCC - 0.1 IOH = -4 mA IOH = -24 mA VOL TYP (1) MIN 3 V to 5.5 V 3.3 V 4 pF All typical values are at VCC 3.3 V, TA = 25C. Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.8 10.7 1.2 7.3 1 6 1 5 ns Operating Characteristics TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 23 23 23 25 Submit Documentation Feedback UNIT pF 5 SN74LVC1G02-EP SINGLE 2-INPUT POSITIVE-NOR GATE www.ti.com SGLS370 - AUGUST 2006 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 15 pF 15 pF 15 pF 15 pF 1 M 1 M 1 M 1 M 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators have the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback SN74LVC1G02-EP SINGLE 2-INPUT POSITIVE-NOR GATE www.ti.com SGLS370 - AUGUST 2006 PARAMETER MEASUREMENT INFORMATION (continued) VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators have the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) SN74LVC1G02MDCKREP ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 BUF V62/06631-01XE ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 BUF (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC1G02-EP : * Catalog: SN74LVC1G02 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC1G02MDCKREP Package Package Pins Type Drawing SC70 DCK 5 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 180.0 8.4 Pack Materials-Page 1 2.41 B0 (mm) K0 (mm) P1 (mm) 2.41 1.2 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G02MDCKREP SC70 DCK 5 3000 202.0 201.0 28.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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