0<BL Blue> XA Spartan-3 Automotive FPGA Family: Introduction and Ordering Information R DS314 (v1.3) June 18, 2009 0 Product Specification 0 Summary The Xilinx(R) Automotive (XA) Spartan(R)-3 family of Field-Programmable Gate Arrays meets the needs of high-volume, cost-sensitive automotive electronic applications. The five-member family offers densities ranging from 50,000 to 1.5 million system gates, as shown in Table 1. Introduction Features XA devices are available in both extended-temperature Q-grade (-40C to +125C TJ) and I-grade (-40C to +100C TJ) and are qualified to the industry-recognized AEC-Q100 standard. * AEC-Q100 device qualification and full PPAP documentation support available in both extended temperature Q-grade and I-grade * Guaranteed to meet full electrical specification over the TJ = -40C to +125C temperature range * Revolutionary 90-nanometer process technology * Low cost, high-performance logic solution for high-volume, automotive applications The XA Spartan-3 family builds on the success of the earlier XA Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. These Spartan-3 enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. * Three power rails: for core (1.2V), I/Os (1.2V to 3.3V), and auxiliary purposes (2.5V) SelectIOTM interface signaling Up to 487 I/O pins Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of advanced automotive electronics modules and systems ranging from the latest driver assistance and infotainment systems to instrument clusters and gateways. 622 Mb/s data transfer rate per I/O Eighteen single-ended signal standards Eight differential signal standards including LVDS Termination by Digitally Controlled Impedance The Spartan-3 family is a flexible alternative to ASICs, ASSPs, and microcontrollers. FPGAs avoid the high initial NREs, the lengthy development cycles, and problems with obsolescence. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary. Signal swing ranging from 1.14V to 3.45V Double Data Rate (DDR) support * Logic resources Abundant logic cells with shift register capability Wide multiplexers Table 1: Summary of Spartan-3 FPGA Attributes CLB Array (One CLB = Four Slices) System Gates Logic Cells Rows XA3S50 50K 1,728 16 12 XA3S200 200K 4,320 24 XA3S400 400K 8,064 32 XA3S1000 1M 17,280 XA3S1500 1.5M 29,952 Device DCMs Maximum User I/O Maximum Differential I/O Pairs 2 124 56 12 4 173 76 16 4 264 116 432K 24 4 333 149 576K 32 4 487 221 Distributed RAM (bits1) Block RAM (bits1) Dedicated Multipliers 192 12K 72K 4 20 480 30K 216K 28 896 56K 288K 48 40 1,920 120K 64 52 3,328 208K Columns Total CLBs Notes: 1. By convention, one Kb is equivalent to 1,024 bits. (c) 2004-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium in the U.S. and other jurisdictions. All other trademarks are the property of their respective owners. DS314 (v1.3) June 18, 2009 Product Specification www.xilinx.com 1 R * * * Fast look-ahead carry logic Dedicated 18 x 18 multipliers JTAG logic compatible with IEEE 1149.1/1532 Introduction and Ordering Information elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical functions as well as to store data. * Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Twenty-six different signal standards, including eight high-performance differential standards, are available as shown in Table 2. Double Data-Rate (DDR) registers are included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying board designs. * Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Fully supported by Xilinx ISE(R) software development system * Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. * Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. SelectRAMTM hierarchical memory Up to 576 Kbits of total block RAM Up to 208 Kbits of total distributed RAM Digital Clock Manager (up to four DCMs) Clock skew elimination Frequency synthesis High-resolution phase shifting Maximum clock frequency 125 MHz Synthesis, mapping, placement and routing * MicroBlazeTM processor, CAN, LIN, MOST, and other cores * Pb-free packaging options * Xilinx and all of our production partners are qualified to ISO-TS16949 Please refer to the Spartan-3 complete data sheet (DS099) for a full product description, AC and DC specifications, and package pinout descriptions Architectural Overview The Spartan-3 family architecture consists of five fundamental programmable functional elements: * Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage DS314 (v1.3) June 18, 2009 Product Specification These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. The XA3S50 has a single column of block RAM embedded in the array. Those devices ranging from the XA3S200 to the XA3S1500 have two columns of block RAM. Each column is made up of several 18 Kbit RAM blocks; each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of the block RAM columns. The Spartan-3 family features a rich network of traces and switches that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. www.xilinx.com 2 R Introduction and Ordering Information DS314-1_01_100808 Notes: 1. The XA3S50 has only the block RAM column on the far left. Figure 1: Spartan-3 Family Architecture Configuration I/O Capabilities Spartan-3 FPGAs are programmed by loading configuration data into robust static memory cells that collectively control all functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master Serial, Slave Serial and Boundary Scan (JTAG). The Master and Slave Parallel modes use an 8-bit-wide SelectMAP port. The SelectIO feature of Spartan-3 devices supports 18 single-ended standards and eight differential standards as listed in Table 2. Many standards support the DCI feature, which uses integrated terminations to eliminate unwanted signal reflections. Table 3 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. . DS314 (v1.3) June 18, 2009 Product Specification www.xilinx.com 3 R Introduction and Ordering Information Table 2: Signal Standards Supported by the Spartan-3 Family Standard Category Description VCCO (V) Class Symbol DCI Option N/A Terminated GTL Yes Plus GTLP Yes I HSTL_I Yes III HSTL_III Yes I HSTL_I_18 Yes II HSTL_II_18 Yes III HSTL_III_18 Yes 1.2 N/A LVCMOS12 No 1.5 N/A LVCMOS15 Yes 1.8 N/A LVCMOS18 Yes 2.5 N/A LVCMOS25 Yes 3.3 N/A LVCMOS33 Yes Single-Ended GTL HSTL Gunning Transceiver Logic High-Speed Transceiver Logic 1.5 1.8 LVCMOS Low-Voltage CMOS LVTTL Low-Voltage Transistor-Transistor Logic 3.3 N/A LVTTL No PCI Peripheral Component Interconnect 3.0 33 MHz PCI33_3 No SSTL Stub Series Terminated Logic 1.8 N/A (6.7 mA) SSTL18_I Yes N/A (13.4 mA) SSTL18_II No I SSTL2_I Yes II SSTL2_II Yes N/A LDT_25 No Standard LVDS_25 Yes Bus BLVDS_25 No Extended Mode LVDSEXT_25 Yes 2.5 Differential LDT (ULVDS) Lightning Data Transport (HyperTransportTM) LVDS Low-Voltage Differential Signaling 2.5 LVPECL Low-Voltage Positive Emitter-Coupled Logic 2.5 N/A RSDS Reduced-Swing Differential Signaling 2.5 N/A RSDS_25 No HSTL Differential High-Speed Transceiver Logic 1.8 II DIFF_HSTL_II_18 Yes SSTL Differential Stub Series Terminated Logic 2.5 II DIFF_SSTL2_II Yes DS314 (v1.3) June 18, 2009 Product Specification LVPECL_25 No www.xilinx.com 4 R Introduction and Ordering Information Table 3: Spartan-3 XA I/O Chart Available User I/Os and Differential (Diff) I/O Pairs VQG100 Device TQG144 PQG208 FTG256 FGG456 FGG676 Grade User Diff User Diff User Diff User Diff User Diff User Diff XA3S50 I,Q 63 29 - - 124 56 - - - - - - XA3S200 I,Q 63 29 97 46 141 62 173 76 - - - - XA3S400 I,Q - - - - 141 62 173 76 264 116 - - XA3S1000 I,Q - - - - - - 173 76 333 149 - - XA3S1500 I - - - - - - - - 333 149 487 221 Notes: 1. All device options listed in a given package column are pin-compatible. DC Specifications Table 4: General Recommended Operating Conditions Symbol TJ Description Junction temperature Min Nom Max Units I-Grade -40 25 100 C Q-Grade -40 25 125 C VCCINT Internal supply voltage 1.140 1.200 1.260 V VCCO(1) Output driver supply voltage 1.140 - 3.450 V VCCAUX Auxiliary supply voltage 2.375 2.500 2.625 V - - 10 mV/ms VCCO = 3.3V -0.3 - 3.75 V VCCO < 2.5V -0.3 - VCCO+0.3 V -0.3 - VCCAUX+0.3 V VCCAUX VIN (2) Voltage variance on VCCAUX when using a DCM Voltage applied to all User I/O pins and Dual-Purpose pins relative to GND Voltage applied to all Dedicated pins relative to GND Notes: 1. The VCCO range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended VCCO range specific to each of the single-ended I/O standards is given in Table 34 of DS099, and that specific to the differential standards is given in Table 36 of DS099. 2. Only during DCM operation is it recommended that the rate of change of VCCAUX not exceed 10 mV/ms. DS314 (v1.3) June 18, 2009 Product Specification www.xilinx.com 5 R Introduction and Ordering Information Table 5: Quiescent Supply Current Characteristics Symbol ICCINTQ ICCOQ ICCAUXQ Description Quiescent VCCINT supply current Quiescent VCCO supply current Quiescent VCCAUX supply current I-Grade Maximum Device Q-Grade Maximum Units XA3S50 50 100 mA XA3S200 125 200 mA XA3S400 180 250 mA XA3S1000 315 400 mA XA3S1500 410 - mA XA3S50 12 12 mA XA3S200 12 12 mA XA3S400 14 14 mA XA3S1000 14 14 mA XA3S1500 16 - mA XA3S50 22 25 mA XA3S200 33 35 mA XA3S400 44 50 mA XA3S1000 55 60 mA XA3S1500 85 - mA Notes: 1. The numbers in this table are based on the conditions set forth in Table 31 of DS099. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using devices with typical processing at ambient room temperature (TA of 25C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX = 2.5V). Maximum values are the production test limits measured for each device at the maximum specified junction temperature and at maximum voltage limits with VCCINT = 1.26V, VCCO = 3.45V, and VCCAUX = 2.625V. The FPGA is programmed with a "blank" configuration data file (i.e., a design with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements, the use of DCI standards, etc.), measured quiescent current levels may be different than the values in the table. Use the XPower Power Estimator for more accurate estimates. See Note 2. 2. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The XPower Power Estimator at http://www.xilinx.com/ise/power_tools provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower, part of the Xilinx ISE development software, uses the FPGA netlist as input to provide more accurate maximum and typical estimates. 3. The maximum numbers in this table also indicate the minimum current each power rail requires in order for the FPGA to power-on successfully, once all three rails are supplied. If VCCINT is applied before VCCAUX, there may be temporary additional ICCINT current until VCCAUX is applied. See Surplus ICCINT if VCCINT Applied before VCCAUX, page 51 of DS099. Ordering Information Mask Revision Code BGA Ball A1 R SPARTAN Device Type Package R XA3S1000TM FTG256EGQ0525 D1234567A 4Q Fabrication Code Process Code Date Code Lot Code Speed Grade Temperature Range DS314-1_02_100808 Figure 2: Spartan-3 BGA Package Marking Example for Part Number XA3S1000-4 FTG256Q Spartan-3 FPGAs are available in Pb-free packaging options for all device/package combinations. The Pb-free packages include a special "G" character in the ordering code. DS314 (v1.3) June 18, 2009 Product Specification www.xilinx.com 6 R Introduction and Ordering Information Pb-Free Packaging For additional information on Pb-free packaging, see XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free Packages. Example: XA3S50 -4 PQ G 208 Q Device Type Temperature Range: Q-Grade = Automotive Extended (TJ = -40C to +125C) I-Grade = Automotive Industrial (TJ = -40C to +100C) Speed Grade Number of Pins Pb-free Package Type DS314-1_03_100808 Table 6: Package Types and Number of Pins Device XA3S50 Speed Grade -4 Standard Performance Package Type / Number of Pins Temperature Range ( TJ ) VQG100 100-pin Very Thin Quad Flat Pack (VQFP) I I-Grade (- 40C to +100C) XA3S200 TQG144 144-pin Thin Quad Flat Pack (TQFP) Q Q-Grade (- 40C to +125C) XA3S400 PQG208 208-pin Plastic Quad Flat Pack (PQFP) XA3S1000 FTG256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) XA3S1500 FGG456 456-ball Fine-Pitch Ball Grid Array (FBGA) FGG676 676-ball Fine-Pitch Ball Grid Array (FBGA) Additional Resources * DS099, Spartan-3 FPGA Family Data Sheet * UG331, Spartan-3 Generation FPGA User Guide * UG332, Spartan-3 Generation Configuration User Guide Revision History The following table shows the revision history for this document: Date Version 10/18/04 1.0 Initial Xilinx release. 12/20/04 1.1 Multiple text edits throughout. 10/27/06 1.2 Updated IO standards (Table 2), and link to Spartan-3 Data Sheet, added XA3S1500, TQG144, FGG676, Table 4, and Table 5. 11/28/06 1.2.1 Changed order of explanations in Table 6 for TQG144 and PQG208. 11/12/07 1.2.2 Changed all values for the Block RAM (bits) column and two values for the XA3S1000 row in Table 1. 01/25/08 1.2.3 Changed XA3S1500 Q-Grade Maximum in Table 5. 06/18/09 1.3 DS314 (v1.3) June 18, 2009 Product Specification Description Added UG331 and UG332 to "Additional Resources" section. www.xilinx.com 7 R Introduction and Ordering Information Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS314 (v1.3) June 18, 2009 Product Specification www.xilinx.com 8