IRFI9634G
PRELIMINARY HEXFET® Power MOSFET
PD - 9.1488
Third Generation HEXFETs from International Rectifier
provide the designer with the best combination of fast
switching, ruggedized device design, low on-resistance
and cost-effectiveness.Third Generation HEXFETs from
International Rectifier provide the designer with the
best combination of fast switching, ruggedized device
design, low on-resistance and cost-effectiveness.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial applications.
The moulding compound used provides a high isolation
capability and a low thermal resistance between the tab
and external heatsink. This isolation is equivalent to using
a 100 micron mica barrier with standard TO-220 product.
The Fullpak is mounted to a heatsink using a single clip or
by a single screw fixing.
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ -10V -4.1
ID @ TC = 100°C Continuous Drain Current, VGS @ -10V -2.6 A
IDM Pulsed Drain Current -16
PD @TC = 25°C Power Dissipation 35 W
Linear Derating Factor 0.28 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy520 mJ
IAR Avalanche Current-4.1 A
EAR Repetitive Avalanche Energy3.5 mJ
dv/dt Peak Diode Recovery dv/dt -5.0 V/ns
TJOperating Junction and -55 to + 150
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Mounting torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Absolute Maximum Ratings
VDSS = -250V
RDS(on) = 1.0Ω
ID = -4.1A
lAdvanced Process Technology
lDynamic dv/dt Rating
l150°C Operating Temperature
lFast Switching
lP-Channel
lFully Avalanche Rated
Description
8/8/96
S
D
G
TO-220 FULLPAK
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 3.6
RθJA Junction-to-Ambient ––– 65
Thermal Resistance
°C/W
IRFI9634G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– -6.5 V TJ = 25°C, IS = -4.1A, VGS = 0V
trr Reverse Recovery Time ––– 190 290 ns TJ = 25°C, IF = -4.1A
Qrr Reverse RecoveryCharge ––– 1.5 2.2 µ C di/dt = -100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage -250 ––– ––– V VGS = 0V, ID = -250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– -0.27 ––– V/°C Reference to 25°C, ID = -1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 1.0 ΩVGS = -10V, ID = -2.5A
VGS(th) Gate Threshold Voltage -2.0 ––– -4.0 V VDS = VGS, ID = -250µA
gfs Forward Transconductance 2.2 ––– ––– S VDS = -50V, ID = -4.1A
––– ––– -25 µA VDS = -250V, VGS = 0V
––– ––– -250 VDS = -200V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -20V
QgTotal Gate Charge –– – –– – 38 ID = -4.1A
Qgs Gate-to-Source Charge ––– ––– 8 .0 nC VDS = -200V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 18 VGS = -10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 12 ––– VDD = -130V
trRise Time ––– 23 ––– ID = -4.1A
td(off) Turn-Off Delay Time ––– 34 – –– RG = 12Ω
tfFall Time ––– 21 ––– RD = 31Ω, See Fig. 10
Between lead,
––– ––– 6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 680 ––– VGS = 0V
Coss Output Capacitance ––– 170 ––– pF VDS = -25V
Crss Reverse Transfer Capacitance ––– 40 ––– ƒ = 1.0MHz, See Fig. 5
C Drain to Sink Capacitance ––– 12 ––– ƒ = 1.0MHz
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance ––– –––
IGSS
ns
4.5
7.5
IDSS Drain-to-Source Leakage Current
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 ) ISD ≤ -4.1A, di/dt ≤ -640A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
Notes:
Starting TJ = 25°C, L = 62mH
RG = 25Ω, IAS = -4.1A. (See Figure 12)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
S
D
G
Source-Drain Ratings and Characteristics
A
S
D
G
-4.1
-16
IRFI9634G
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics,
TJ = 150oC
Fig 1. Typical Output Characteristics,
TJ = 25oC
Fig 3. Typical Transfer Characteristics
1
10
100
1 10 100
D
DS
20µs PULSE WIDTH
T = 2 5 °C
c
A
-I , D rain -to -S ou rce C urre nt (A )
-V , D rain-to-Source Voltage (V )
VGS
T OP - 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTTOM - 4.5V
-4 .5V
1
10
100
1 10 100
D
DS
20
µ
s PU LSE WIDTH
T = 150°C
C
A
-I , Drain-to-Source Current (A)
-V , D ra in -to -S o urc e V o lta
g
e
(
V
)
VGS
T OP - 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTTOM - 4.5V
-4.5V
1
10
100
45678910
T = 25°C
T = 150°C
J
J
GS
D
A
-I , D rain -to -S o urc e Curre nt (A )
-V , Ga te -to-Source Voltage (V)
V = -50V
20µs PU LSE WID TH
DS
0.0
0.5
1.0
1.5
2.0
2.5
-60 -40 -20 0 20 40 60 80 100 120 140 160
J
T , Junction Tem perature (°C )
R , D ra in-to -S o u rc e O n R e s is ta nc e
DS(on)
(Normalized)
A
V = -1 0V
GS
I = -4.1 A
D
IRFI9634G
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
4
8
12
16
20
0 10203040
G
GS
A
-V , G a te-to -Sou rc e V o ltag e (V )
Q , To ta l Ga te Ch a r
g
e
(
nC
)
FO R TEST CIRCU IT
S E E FIGU R E 1 3
I = -4 .1 A V = -20 0 V
V = -12 5 V
V = -50 V
DDS
DS
DS
0.1
1
10
100
1.0 2.0 3.0 4.0 5.0
T = 25°C
T = 150°C
J
J
V = 0V
GS
SD
SD
A
-I , R ev ers e D ra in C urre nt (A )
-V , Source-to-Drain Voltage (V )
0.1
1
10
100
10 100 1000
O P ER A T IO N IN T H IS A R E A L IM IT E D
B Y R
DS(on)
T = 25 °C
T = 15 0 °C
Sin
g
le P u ls e
C
J
10ms
A
-I , D ra in C urre nt (A )
-V , Dr a in -to -So ur c e V o lta
g
e
(
V
)
DS
D
100µs
1ms
0
200
400
600
800
1000
1200
1 10 100
C , Capacitance (pF)
A
DS
-V , D ra in -to -S o u rce V o lta
g
e
(
V
)
V = 0 V , f = 1MH z
C = C + C , C SH O RT E D
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss d s gd
C
iss
C
oss
C
rss
IRFI9634G
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
VDS
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
VDD
RGD.U.T.
+
-
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
0.0
1.0
2.0
3.0
4.0
5.0
25 50 75 100 125 150
C
T , C as e Tem perature (°C)
A
-I , D rain C urren t (A m ps)
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1 10
t , Rectangular Pulse Duration (sec)
1
thJC
D = 0.50
0.01
0.02
0.05
0.10
0.20
S INGL E P ULS E
(THERM AL RES PONSE)
A
T h er ma l Re sp onse (Z )
P
t
2
1
t
DM
N ote s:
1. D uty f act or D = t / t
2. P ea k T = P x Z + T
12
JDM thJC C
IRFI9634G
Fig 13b. Gate Charge Test CircuitFig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Q
G
Q
GS
Q
GD
V
G
Charge
-10V
D.U.T. V
DS
I
D
I
G
-3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tpV
(
BR
)
DSS
I
AS
R
G
IAS
0.01
Ω
t
p
D.U.T
L
V
DS
VDD
DRIVER A
15V
-20V
0
100
200
300
400
500
600
25 50 75 100 125 150
J
E , S in gle Pu lse Avalanc he E n ergy (m J )
AS
A
Startin
g
T , J unc tion Temperature
(
°C
)
I
TOP -4 .1 A
-5 .2 A
B O T T O M -8 .2A
D
IRFI9634G
Peak Diode Recovery dv/dt Test Circuit
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T*Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
* Reverse Polarity of D.U.T for P-Channel
VGS
[ ]
[ ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
[ ] ***
Fig 14. For P-Channel HEXFETS
IRFI9634G
PART NU MB ER
INTERNATIONAL
RE CTIF IER
LOGO
EXA MPLE : THIS IS AN IR F1010
W ITH A SS EMBLY
LOT CODE 9B1M
ASSEMBLY
LOT CODE
DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
9246
IRF1010
9 B 1 M
A
Part Marking Information
TO-220 Fullpak
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
LEAD ASSIGNMENTS
1 - GATE
2 - DRA IN
3 - SOUR CE
NOTES:
1 DIMENSIONING & TOLERANCING
P ER AN S I Y14.5M , 1982
2 CONTROLLING DIMENSION: INCH.
D
C
AB
MINIMUM CREEPAGE
DISTANCE BETWEEN
A -B-C -D = 4.80 (.189)
3X
2.85 (.112)
2.65 (.104)
2.80 (.110)
2.60 (.102)
4.80 (.189)
4.60 (.181)
7.10 (.280)
6.70 (.263)
3.40 (.133)
3.10 (.123)
ø
- A -
3.70 (.145)
3.20 (.126)
1.15 (.045)
MIN .
3.30 (.130)
3.10 (.122)
- B -
0.90 (.035)
0.70 (.028)
3X
0.25 (.010) MA M B
2.54 (.100)
2 X
3X
13.70 (.540)
13.50 (.530)
16.00 (.630)
15.80 (.622)
1 2 3
10.60 (.417)
10.40 (.409)
1.40 (.055)
1.05 (.042)
0.48 (.019)
0.44 (.017)
PART NUMBER
INTERNATIONAL
R E CT IF IER
L O GO
DAT E COD E
(YYWW)
YY = YEA R
WW = WEEK
ASSEM BL Y
L O T C OD E
E401 9245
IRFI840G
EXAMPLE : TH IS IS AN IRFI840G
WITH ASSEMBLY
L OT C OD E E 4 0 1
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http://www.irf.com/ Data and specifications subject to change without notice. 8/96