DS91M040TSQX/NOPB - NATIONAL SEMICONDUCTOR

DS91M040

DS91M040 125 MHz Quad M-LVDS Transceiver

Literature Number: SNLS283L

DS91M040

November 9, 2009

125 MHz Quad M-LVDS Transceiver

General Description

The DS91M040 is a quad M-LVDS transceiver designed for

driving / receiving clock or data signals to / from up to four

multipoint networks.

M-LVDS (Multipoint LVDS) is a new family of bus interface

devices based on LVDS technology specifically designed for

multipoint and multidrop cable and backplane applications. It

differs from standard LVDS in providing increased drive cur-

rent to handle double terminations that are required in multi-

point applications. Controlled transition times minimize re-

flections that are common in multipoint configurations due to

unterminated stubs. M-LVDS devices also have a very large

input common mode voltage range for additional noise margin

in heavily loaded and noisy backplane environments.

A single DS91M040 channel is a half-duplex transceiver that

accepts LVTTL/LVCMOS signals at the driver inputs and con-

verts them to differential M-LVDS signal levels. The receiver

inputs accept low voltage differential signals (LVDS, BLVDS,

M-LVDS, LVPECL and CML) and convert them to

3V LVCMOS signals. The DS91M040 supports both M-LVDS

type 1 and type 2 receiver inputs.

Features

■DC - 125 MHz / 250 Mbps low jitter, low skew, low power

operation

■Wide Input Common Mode Voltage Range allows up to

±1V of GND noise

■Conforms to TIA/EIA-899 M-LVDS Standard

■Pin selectable M-LVDS receiver type (1 or 2)

■Controlled transition times (2.0 ns typ) minimize reflections

■8 kV ESD on M-LVDS I/O pins protects adjoining

components

■Flow-through pinout simplifies PCB layout

■Small 5 mm x 5 mm LLP-32 space saving package

Applications

■Multidrop / Multipoint clock and data distribution

■High-Speed, Low Power, Short-Reach alternative to

TIA/EIA-485/422

■Clock distribution in AdvancedTCA (ATCA) and

MicroTCA (μTCA, uTCA) backplanes

Typical Application

30042202

DS91M040 125 MHz Quad M-LVDS Transceiver

Ordering Information

Order Number Receiver Input Function Package Type

DS91M040TSQ Type 1 or 2 Quad M-LVDS Transciever LLP-32

Connection Diagram

30042201

Logic Diagram

30042203

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DS91M040

Pin Descriptions

Number Name I/O, Type Description

1, 3, 5, 7 RO O, LVCMOS Receiver output pin.

26, 28, 13, 15 RE I, LVCMOS Receiver enable pin: When RE is high, the receiver is disabled.

When RE is low, the receiver is enabled. There is a 300 kΩ pullup

resistor on this pin.

25, 27, 14, 16 DE I, LVCMOS Driver enable pin: When DE is low, the driver is disabled. When

DE is high, the driver is enabled. There is a 300 kΩ pulldown

resistor on this pin.

2, 4, 6, 8 DI I, LVCMOS Driver input pin.

31, DAP GND Power Ground pin and pad.

17, 19, 21, 23 A I/O, M-LVDS Non-inverting driver output pin/Non-inverting receiver input pin

18, 20, 22, 24 B I/O, M-LVDS Inverting driver output pin/Inverting receiver input pin

11, 12, 29, 30 VDD Power Power supply pin, +3.3V ± 0.3V

32 FSEN1 I, LVCMOS Failsafe enable pin with a 300 kΩ pullup resistor. This pin

enables Type 2 receiver on inputs 0 and 2.

FSEN1 = L --> Type 1 receiver inputs

FSEN1 = H --> Type 2 receiver inputs

9 FSEN2 I, LVCMOS Failsafe enable pin with a 300 kΩ pullup resistor. This pin

enables Type 2 receiver on inputs 1 and 3.

FSEN2 = L --> Type 1 receiver inputs

FSEN2 = H --> Type 2 receiver inputs

10 MDE I, LVCMOS Master enable pin. When MDE is H, the device is powered up.

When MDE is L, the device overrides all other control and powers

down.

M-LVDS Receiver Types

The EIA/TIA-899 M-LVDS standard specifies two different

types of receiver input stages. A type 1 receiver has a con-

ventional threshold that is centered at the midpoint of the input

amplitude, VID/2. A type 2 receiver has a built in offset that is

100mV greater then VID/2. The type 2 receiver offset acts as

a failsafe circuit where open or short circuits at the input will

always result in the output stage being driven to a low logic

state.

30042240

FIGURE 1. M-LVDS Receiver Input Thresholds

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DS91M040

Absolute Maximum Ratings (Note 4)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Power Supply Voltage −0.3V to +4V

LVCMOS Input Voltage −0.3V to (VDD + 0.3V)

LVCMOS Output Voltage −0.3V to (VDD + 0.3V)

M-LVDS I/O Voltage −1.9V to +5.5V

M-LVDS Output Short Circuit

Current Duration Continuous

Junction Temperature +140°C

Storage Temperature Range −65°C to +150°C

Lead Temperature Range

Soldering (4 sec.) +260°C

Maximum Package Power Dissipation @ +25°C

SQ Package 3.91W

Derate SQ Package 34 mW/°C above +25°C

Package Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)

θJA +29.4°C/W

θJC +2.8°C/W

ESD Susceptibility

HBM (Note 1)≥8 kV

MM (Note 2)≥250V

CDM (Note 3)≥1250V

Note 1: Human Body Model, applicable std. JESD22-A114C

Note 2: Machine Model, applicable std. JESD22-A115-A

Note 3: Field Induced Charge Device Model, applicable std.

JESD22-C101-C

Recommended Operating

Conditions

Min Typ Max Units

Supply Voltage, VDD 3.0 3.3 3.6 V

Voltage at Any Bus Terminal −1.4 +3.8 V

(Separate or Common-Mode)

Differential Input Voltage VID 2.4 V

LVTTL Input Voltage High VIH 2.0 VDD V

LVTTL Input Voltage Low VIL 0 0.8 V

Operating Free Air

Temperature TA−40 +25 +85 °C

DC Electrical Characteristics (Note 5, Note 6, Note 7, Note 9)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

M-LVDS Driver

|VAB| Differential output voltage magnitude RL = 50Ω, CL = 5 pF 480 650 mV

ΔVAB Change in differential output voltage magnitude

between logic states

Figures 2, 4 −50 0 +50 mV

VOS(SS) Steady-state common-mode output voltage RL = 50Ω, CL = 5 pF 0.3 1.6 2.1 V

|ΔVOS(SS)|Change in steady-state common-mode output

voltage between logic states

Figures 2, 3 0 +50 mV

VA(OC) Maximum steady-state open-circuit output voltage Figure 5 0 2.4 V

VB(OC) Maximum steady-state open-circuit output voltage 0 2.4 V

VP(H) Voltage overshoot, low-to-high level output

(Note 12)

RL = 50Ω, CL = 5pF, CD = 0.5 pF

Figures 7, 8 1.2VSS V

VP(L) Voltage overshoot, high-to-low level output

(Note 12)

−0.2VS

IIH High-level input current (LVTTL inputs) VIH = 3.6V -15 15 μA

IIL Low-level input current (LVTTL inputs) VIL = 0.0V -15 15 μA

VCL Input Clamp Voltage (LVTTL inputs) IIN = -18 mA -1.5 V

IOS Differential short-circuit output current (Note 8)Figure 6 -43 43 mA

M-LVDS Receiver

VIT+ Positive-going differential input voltage threshold See Function Tables Type 1 16 50 mV

Type 2 100 150 mV

VIT− Negative-going differential input voltage threshold See Function Tables Type 1 −50 20 mV

Type 2 50 94 mV

VOH High-level output voltage (LVTTL output) IOH = −8mA 2.4 2.7 V

VOL Low-level output voltage (LVTTL output) IOL = 8mA 0.28 0.4 V

IOZ TRI-STATE output current VO = 0V or 3.6V −10 10 μA

IOSR Short-circuit receiver output current (LVTTL output) VO = 0V -50 -90 mA

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DS91M040

Symbol Parameter Conditions Min Typ Max Units

M-LVDS Bus (Input and Output) Pins

IATransceiver input/output current VA = 3.8V, VB = 1.2V 32 µA

VA = 0V or 2.4V, VB = 1.2V −20 +20 µA

VA = −1.4V, VB = 1.2V −32 µA

IBTransceiver input/output current VB = 3.8V, VA = 1.2V 32 µA

VB = 0V or 2.4V, VA = 1.2V −20 +20 µA

VB = −1.4V, VA = 1.2V −32 µA

IAB Transceiver input/output differential current (IA − IB)VA = VB, −1.4V ≤ V ≤ 3.8V −4 +4 µA

IA(OFF) Transceiver input/output power-off current VA = 3.8V, VB = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

32 µA

VA = 0V or 2.4V, VB = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

−20 +20 µA

VA = −1.4V, VB = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

−32 µA

IB(OFF) Transceiver input/output power-off current VB = 3.8V, VA = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

32 µA

VB = 0V or 2.4V, VA = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

−20 +20 µA

VB = −1.4V, VA = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

−32 µA

IAB(OFF) Transceiver input/output power-off differential

current (IA(OFF) − IB(OFF))

VA = VB, −1.4V ≤ V ≤ 3.8V,

DE = 0V

0V ≤ VDD ≤ 1.5V

−4 +4 µA

CATransceiver input/output capacitance VDD = OPEN 7.8 pF

CBTransceiver input/output capacitance 7.8 pF

CAB Transceiver input/output differential capacitance 3 pF

CA/B Transceiver input/output capacitance balance

(CA/CB) 1

SUPPLY CURRENT (VCC)

ICCD Driver Supply Current RL = 50Ω, DE = H, RE = H 67 75 mA

ICCZ TRI-STATE Supply Current DE = L, RE = H 22 26 mA

ICCR Receiver Supply Current DE = L, RE = L 32 38 mA

ICCPD Power Down Supply Current MDE = L 3 5 mA

Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the

device should not be operated beyond such conditions.

Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and

ΔVOD.

Note 7: Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.

Note 9: CL includes fixture capacitance and CD includes probe capacitance.

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DS91M040

Switching Characteristics (Note 10, Note 11, Note 17)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

DRIVER AC SPECIFICATIONS

tPLH Differential Propagation Delay Low to High RL = 50Ω, CL = 5 pF, 1.5 3.3 5.5 ns

tPHL Differential Propagation Delay High to Low CD = 0.5 pF 1.5 3.3 5.5 ns

tSKD1 Pulse Skew (Note 12, Note 13)Figures 7, 8 30 125 ps

tSKD2 Channel-to-Channel Skew (Note 12, Note

14)

100 200 ps

tSKD3 Part-to-Part Skew (Note 12, Note 15) 0.8 1.6 ns

tSKD4 Part-to-Part Skew (Note 12, Note 16) 4 ns

tTLH Rise Time (Note 12) 1.2 2.0 3.0 ns

tTHL Fall Time (Note 12) 1.2 2.0 3.0 ns

tPZH Enable Time (Z to Active High) RL = 50Ω, CL = 5 pF, 7.5 11.5 ns

tPZL Enable Time (Z to Active Low ) CD = 0.5 pF 8.0 11.5 ns

tPLZ Disable Time (Active Low to Z) Figures 9, 10 7.0 11.5 ns

tPHZ Disable Time (Active High to Z) 7.0 11.5 ns

RECEIVER AC SPECIFICATIONS

tPLH Propagation Delay Low to High CL = 15 pF 1.5 3.0 4.5 ns

tPHL Propagation Delay High to Low Figures 11, 12, 13 1.5 3.1 4.5 ns

tSKD1A Pulse Skew (Receiver Type 1)

(Note 12, Note 13)

55 325 ps

tSKD1B Pulse Skew (Receiver Type 2)

(Note 12, Note 13)

475 800 ps

tSKD2 Channel-to-Channel Skew (Note 12, Note

14)

60 300 ps

tSKD3 Part-to-Part Skew (Note 12, Note 15) 0.6 1.2 ns

tSKD4 Part-to-Part Skew (Note 16) 3 ns

tTLH Rise Time (Note 12) 0.3 1.1 1.6 ns

tTHL Fall Time (Note 12) 0.3 0.65 1.6 ns

tPZH Enable Time (Z to Active High) RL = 500Ω, CL = 15 pF 3 5.5 ns

tPZL Enable Time (Z to Active Low) Figures 14, 15 3 5.5 ns

tPLZ Disable Time (Active Low to Z) 3.5 5.5 ns

tPHZ Disable Time (Active High to Z) 3.5 5.5 ns

GENERIC AC SPECIFICATIONS

tWKUP Wake Up Time (Note 12)

(Master Device Enable (MDE) time)

500 ms

fMAX Maximum Operating Frequency (Note 12) 125 MHz

Note 10: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 11: Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 12: Specification is guaranteed by characterization and is not tested in production.

Note 13: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative

going edge of the same channel.

Note 14: tSKD2, Channel-to-Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels.

Note 15: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to

devices at the same VDD and within 5°C of each other within the operating temperature range.

Note 16: tSKD4, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over

recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.

Note 17: CL includes fixture capacitance and CD includes probe capacitance.

Note 18: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subracted geometrically.

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DS91M040

Test Circuits and Waveforms

30042214

FIGURE 2. Differential Driver Test Circuit

30042244

FIGURE 3. Differential Driver Waveforms

30042222

FIGURE 4. Differential Driver Full Load Test Circuit

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DS91M040

30042212

FIGURE 5. Differential Driver DC Open Test Circuit

30042225

FIGURE 6. Differential Driver Short-Circuit Test Circuit

30042216

FIGURE 7. Driver Propagation Delay and Transition Time Test Circuit

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DS91M040

30042218

FIGURE 8. Driver Propagation Delays and Transition Time Waveforms

30042219

FIGURE 9. Driver TRI-STATE Delay Test Circuit

30042221

FIGURE 10. Driver TRI-STATE Delay Waveforms

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DS91M040

30042215

FIGURE 11. Receiver Propagation Delay and Transition Time Test Circuit

30042217

FIGURE 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms

30042223

FIGURE 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms

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DS91M040

30042213

FIGURE 14. Receiver TRI-STATE Delay Test Circuit

30042220

FIGURE 15. Receiver TRI-STATE Delay Waveforms

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DS91M040

Truth Tables

DS91M040 Transmitting

Inputs Outputs

RE DE DI B A

X H H L H

X H L H L

X L X Z Z

X — Don't care condition

Z — High impedance state

DS91M040 as Type 1 Receiving

Inputs Output

FSEN RE DE A − B RO

L L X ≥ +0.05V H

L L X ≤ −0.05V L

L L X −0.05V

≤ A-B ≤

+0.05V

Undefined

L H X X Z

X — Don't care condition

Z — High impedance state

DS91M040 as Type 2 Receiving

Inputs Output

FSEN RE DE A − B RO

H L X ≥ +0.15V H

H L X ≤ +0.05V L

H L X +0.05V

≤ A-B ≤

+0.15V

Undefined

H H X X Z

X — Don't care condition

Z — High impedance state

DS91M040 Type 1 Receiver Input Threshold Test Voltages

Applied Voltages Resulting Differential Input

Voltage

Resulting Common-Mode

Input Voltage

Receiver

Output

VIA VIB VID VICM R

2.400V 0.000V 2.400V 1.200V H

0.000V 2.400V −2.400V 1.200V L

3.800V 3.750V 0.050V 3.775V H

3.750V 3.800V −0.050V 3.775V L

−1.350V −1.400V 0.050V −1.375V H

−1.400V −1.350V −0.050V −1.375V L

H — High Level

L — Low Level

Output state assumes that the receiver is enabled (RE = L)

DS91M040 Type 2 Receiver Input Threshold Test Voltages

Applied Voltages Resulting Differential Input

Voltage

Resulting Common-Mode

Input Voltage

Receiver

Output

VIA VIB VID VIC R

2.400V 0.000V 2.400V 1.200V H

0.000V 2.400V −2.400V 1.200V L

3.800V 3.650V 0.150V 3.725V H

3.800V 3.750V 0.050V 3.775V L

−1.250V −1.400V 0.150V −1.325V H

−1.350V −1.400V 0.050V −1.375V L

H — High Level

L — Low Level

Output state assumes that the receiver is enabled (RE = L)

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DS91M040

Typical Performance Characteristics

30042250

Driver Rise Time as a Function of Temperature

30042251

Driver Fall Time as a Function of Temperature

30042258

Driver Output Signal Amplitude as a Function of

Resistive Load

30042252

Driver Propagation Delay (tPLHD) as a Function of

Temperature

30042253

Driver Propagation Delay (tPHLD) as a Function of

Temperature

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DS91M040

30042254

Driver Power Supply Current as a Function of Frequency

30042255

Receiver Power Supply Current as a Function of

Frequency

30042256

Receiver Propagation Delay (tPLHD) as a Function of

Input Common Mode Voltage

30042257

Receiver Propagation Delay (tPHLD) as a Function of

Input Common Mode Voltage

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DS91M040

Physical Dimensions inches (millimeters) unless otherwise noted

Order Number DS91M040TSQ

See NS package Number SQA32A

(See AN-1187 for PCB Design and Assembly Recommendations)

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DS91M040

Notes

DS91M040 125 MHz Quad M-LVDS Transceiver

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Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265