In-System Programming by On-chip Boot Program

True Read-While-Write Operation

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Programmable Serial USART

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– 2.7V - 5.5V for ATmega32L

– 4.5V - 5.5V for ATmega32

– 0 - 16MHz for ATmega32

ATmega32L

Pin

Overview The Atmel®AVR®ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR

ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to

Resources A comprehensive set of development tools, application notes and datasheets are available for

Examples

compilation. Be aware that not all C Compiler vendors include bit definitions in the header files

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The ALU supports arithmetic and logic operations between registers or between a constant and

• Bits 15..10 – Reserved Bits

• Bits 7..0 – EEDR7.0: EEPROM Data

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

by the IN and OUT instructions, transferring data between the 32 general purpose working regis-

ters and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-

System Clock

and Clock

the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table

Table 3. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

Power

Management

Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the

ing (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the

This improves the noise environment for the ADC, enabling higher resolution measurements. If

Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface

address match interrupt, an External level interrupt on INT0 or INT1, or an External interrupt on

INT2 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing oper-

ation of asynchronous modules only.

for details.

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 201

independent of sleep mode. Refer to “Analog Comparator” on page 198 for details on how to

device will be disabled. This ensures that no power is consumed by the input logic when not

details on which pins are enabled. If the input buffer is enabled and the input signal is left floating

• Disable JTAGEN Fuse.

power consumption will increase. Note that the TDI pin for the next device in the scan chain con-

and Reset

threshold (VPOT).

(BODEN programmed), and VCC decreases to a value below the trigger level (VBOT- in Figure

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

The voltage reference has a start-up time that may influence the way it should be used. The

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be fol-

ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as

capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-

vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP,

and PUD are common to all ports.

Description for I/O Ports” on page 64, the DDxn bits are accessed at the DDRx I/O address, the

PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

the edge of the internal clock, but it also introduces a delay. Figure 24 shows a timing diagram of

the synchronization when reading an externally applied pin value. The maximum and minimum

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

1 1 X Output No Output High (Source)

The simplest method to ensure a defined level of an unused pin, is to enable the internal pullup.