1
®
FN7105.3
EL8200, EL8201, EL8401
200MHz Rail-to-Rail Amplifiers
The EL8200, EL8201, and EL8401 represent rail-to-rail
amplifiers with a -3dB bandwidth of 200MHz and slew rate of
200V/µs. Running off a very low supply current of 2mA per
channel, the EL8200, EL8201, and EL8401 also feature
inputs that go to 0.1 5V be l o w th e VS- rail. The EL8200 and
EL8201 are dual channel amplifi ers. The EL8401 is a quad
channel amplifier.
The EL8200 includes a fast-acting disable/power-down
circuit. With a 25ns disable and a 200ns enable, the EL8200
is ideal for multiplexing appl ications.
The EL8200, EL8201, and EL8401 are designed for a
number of general purpose video, communication,
instrumentation, and industrial applications. The EL8200 is
available in a 10 Ld MSOP package, the EL8201 in an 8 Ld
SO and 8 Ld MSOP package, and the EL8401 in a 14 Ld SO
and 16 Ld QSOP packages. All are specified for operation
over the -40°C to +85°C temperature range.
Features
200MHz -3dB bandwidth
200V/µs slew rate
Low supply current = 2mA per channel
Supplies from 3V to 5.5V
Rail-to-rail output
Input to 0.15V below VS-
Fast 25ns disable (EL8200 only)
•Low cost
Pb-free available (RoHS co mpliant)
Applications
Video amplifiers
Portable/hand-held products
Communications devices
Pinouts
EL8201
(8 LD SO, 8 LD MSOP)
TOP VIEW
EL8200
(10 LD MSOP)
TOP VIEW
EL8401
(14 LD SO)
TOP VIEW
EL8401
(16 LD QSOP)
TOP VIEW
-
+
-
+
OUTA
INA-
INA+
VS-
VS+
OUTB
INB-
INB+
1
2
3
4
8
7
6
5
-
+
-
+
INA+
CEA
VS-
CEB
INA-
OUTA
VS+
OUTB
INB+ INB-
1
2
3
4
10
9
8
7
5 6
1
2
3
4
14
13
12
11
5
6
7
10
9
8
OUTA
INA-
INA+
VS+
INB+
INB-
OUTB
OUTD
IND-
IND+
VS-
INC+
INC-
OUTC
-+ -+
-+ -+
AD
BC
1
2
3
4
16
15
14
13
5
6
7
12
11
10
8 9
OUTA
INA-
INA+
VS+
INB+
INB-
OUTB
OUTD
IND-
IND+
VS-
INC+
INC-
OUTC
NC NC
-+ -+
-+ -+
Data Sheet August 29, 2007
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2006, 2007. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
2FN7105.3
August 29, 2007
Ordering Information
PART NUMBER PART MARKING PACKAGE PKG. DWG. #
EL8200IY j 10 Ld MSOP MDP0043
EL8200IY-T7* j 10 Ld MSOP MDP0043
EL8200IY-T13* j 10 Ld MSOP MDP0043
EL8200IYZ (See Note) BAMAA 10 Ld MSOP (Pb-free) MDP0043
EL8200IYZ-T7* (See Note) BAMAA 10 Ld MSOP (Pb-free) MDP0043
EL8200IYZ-T13* (See Note) BAMAA 10 Ld MSOP (Pb-free) MDP0043
EL8201IS 8201IS 8 Ld SO MDP0027
EL8201IS-T7* 8201IS 8 Ld SO MDP0027
EL8201IS-T13* 8201IS 8 Ld SO MDP0027
EL8201ISZ (See Note) 8201ISZ 8 Ld SO (Pb-free) MDP0027
EL8201ISZ-T7* (See Note) 8201ISZ 8 Ld SO (Pb-free) MDP0027
EL8201ISZ-T13* (See Note) 8201ISZ 8 Ld SO (Pb-free) MDP0027
Coming Soon
EL8201IYZ (See Note) 8 Ld MSOP (Pb-free) MDP0043
Coming Soon
EL8201IYZ-T7* (See Note) 8 Ld MSOP (Pb-free) MDP0043
Coming Soon
EL8201IYZ-T13* (See Note) 8 Ld MSOP (Pb-free) MDP0043
EL8401IS 8401IS 14 Ld SO MDP0027
EL8401IS-T7* 8401IS 14 Ld SO MDP0027
EL8401IS-T13* 8401IS 14 Ld SO MDP0027
EL8401ISZ (See Note) 8401ISZ 14 Ld SO (Pb-free) MDP0027
EL8401ISZ-T7* (See Note) 8401ISZ 14 Ld SO (Pb-free) MDP0027
EL8401ISZ-T13* (See Note) 8401ISZ 14 Ld SO (Pb-free) MDP0027
EL8401IU 8401IU 16 Ld QSOP MDP0040
EL8401IU-T7* 8401IU 16 Ld QSOP MDP0040
EL8401IU-T13* 8401IU 16 Ld QSOP MDP0040
EL8401IUZ (See Note) 8401IUZ 16 Ld QSOP (Pb-free) MDP0040
EL8401IUZ-T7* (See Note) 8401IUZ 16 Ld QSOP (Pb-free) MDP0040
EL8401IUZ-T13* (See Note) 8401IUZ 16 Ld QSOP (Pb-free) MDP0040
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
EL8200, EL8201, EL8401
3FN7105.3
August 29, 2007
IMPORTANT NOTE: All parameters having Min/Max specifica tio ns are guaranteed. Typ va lues are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T J = TC = TA
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
St orage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified
PARAMETER DESCRIPTION CONDITIONS MIN
(Note 1) TYP MAX
(Note 1) UNIT
INPUT CHARACTERISTICS
VOS Offset Voltage -6 -0.8 +6 mV
TCVOS Offset Voltage Temperature Coefficient Measured from TMIN to TMAX V/°C
IB Input Bias Current VIN = 0V -2.5 -1.6 µA
IOS Input Offset Current VIN = 0V 0.2 0.55 µA
TCIOS Input Bias Current Temperature
Coefficient Measured from TMIN to TMAX 2nA/°C
CMRR Common Mode Rejection Ratio VCM = -0.15V to +3.5V (EL8200,EL8201) 70 90 dB
VCM = -0.15V to +3.5V (EL8401) 65 90 dB
CMIR Common Mode Input Range VS- -0.15 VS+ -1.5 V
RIN Input Resistance Common Mode 16 MΩ
CIN Input Capacitance 0.5 pF
AVOL Open Loop Gain VOUT = +1.5V to +3.5V, RL = 1kΩ to GND 75 90 dB
VOUT = +1.5V to +3.5V , RL = 150Ω to GND 80 dB
OUTPUT CHARACTERISTICS
ROUT Output Resistance AV = +1 30 mΩ
VOP Positive Output Voltage Swing RL = 1kΩ 4.85 4.9 V
RL = 150Ω 4.6 4.7 V
VON Negative Output Voltage Swing RL = 150Ω100 150 mV
RL = 1kΩ35 50 mV
IOUT Linear Output Current 65 mA
ISC (source) Short Circuit Current RL = 10Ω60 70 mA
ISC (sink) Short Circuit Current RL = 10Ω100 130 mA
POWER SUPPLY
PSRR Power Supply Rejection Ratio VS+ = 4.5V to 5.5V 70 100 dB
IS-ON Supply Current 22.4mA
IS-OFF Supply Current - Disabled per Amplifier EL8200 only 40 90 µA
ENABLE (EL8200 ONLY)
tEN Enable Time 200 ns
tDS Disable Time 25 ns
VIH-ENB ENABLE Pin Voltage for Power-up 0.8 V
EL8200, EL8201, EL8401
4FN7105.3
August 29, 2007
VIL-ENB ENABLE Pin Voltage for Shut-down 2 V
IIH-ENB ENABLE Pin Input Current High 8.6 µA
IIL-ENB ENABLE Pin Input for Current Low 0.01 µA
AC PERFORMANCE
BW -3dB Bandwidth AV = +1, RF = 0Ω, CL = 1.5pF 200 MHz
AV = -1, RF = 1kΩ, CL = 1.5pF 90 MHz
AV = +2, RF = 1kΩ, CL = 1.5pF 90 MHz
AV = +10, RF = 1kΩ, CL = 1.5pF 10 MHz
BW ±0.1dB Bandwidth AV = +1, RF = 0Ω, CL = 1.5pF 20 MHz
Peak Peaking AV = +1, RF = 1kΩ, CL = 1.5pF 1 dB
GBWP Gain Bandwidth Product 100 MHz
PM Phase Margin RL = 1kΩ, CL = 1.5pF 55 °
SR Slew Rate AV = 2, RL = 100Ω, VOUT = 0.5V to 4.5V 160 200 V/µs
tRRise Time 2.5VSTEP, 20% - 80% 8 ns
tFFall Time 2.5VSTEP, 20% - 80% 7 ns
OS Overshoot 200mV step 10 %
tPD Propagation Delay 200mV step 2 ns
tS0.1% Settling Time 200mV step 20 ns
dG Differential Gain AV = +2, RF = 1kΩ, RL = 150Ω0.035 %
dP Differential Phase AV = +2, RF = 1kΩ, RL = 150Ω0.05 °
eNInput Noise Voltage f = 10kHz 10 nV/Hz
iN+ Positive Input Noise Current f = 10kHz 1 pA/Hz
iN- Negative Input Noise Current f = 10kHz 0.8 pA/Hz
eSChannel Separation f = 100kHz 95 dB
NOTE:
1. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
Electrical Specifications VS+ = 5V, VS- = GND, TA = 25°C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN
(Note 1) TYP MAX
(Note 1) UNIT
Pin Descriptions
EL8200
(10 Ld SO) EL8201
(8 Ld SO, 8 Ld MSOP) EL8401
(14 Ld SO) EL8401
(16 Ld QSOP) NAME FUNCTION
1, 5 3, 5 3, 5, 10, 12 3, 5, 12, 14 IN+ Non-inverting input for each channel
2, 4 CE Enable and disable input for each channel
3 4 11 13 VS- Negative power supply
6, 10 2, 6 2, 6, 9, 13 2, 6, 11, 15 IN- Inverting input for each channel
7, 9 1, 7 1, 7, 8, 14 1, 7, 10, 16 OUT Amplifier output for each channel
8 8 4 4 VS+ Positive power supply
EL8200, EL8201, EL8401
5FN7105.3
August 29, 2007
Typical Performance Curves
FIGURE 1. FREQUENCY RESPONSE FOR V ARIOUS OUTPUT
VOLTAGE LEVELS FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS RLOAD
FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS NON-INVERTING GAINS FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS INVERTING GAINS
FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS CL
FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS CL
4
2
0
-2
-4
-6
100K 1M 10M 100M 1G
FREQUENCY (Hz)
GAIN (dB)
VS=5V
AV=1
RL=1kΩ
CL=1.5pF VOP-P=200mV
VOP-P=2V
VOP-P=1V
4
2
0
-2
-4
-6
100K 1M 10M 100M 1G
FREQUENCY (Hz)
GAIN (dB)
VS=5V
AV=1
CL=1.5pF RL=330Ω
RL=1kΩ
RL=100Ω
4
2
0
-2
-4
-6
100K 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
VS=5V
RL=1kΩ
CL=1.5pF AV=1
AV=10
AV=5
AV=2
4
2
0
-2
-4
-6
100K 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
VS=5V
RL=1kΩ
CL=1.5pF
RF=1kΩ
AV=-10
AV=-2
AV=-5
5
3
1
-1
-3
-5
100K 1M 10M 100M 1G
FREQUENCY (Hz)
GAIN (dB)
VS=5V
AV=1
RL=1kΩ
VOP-P=200mV
CL=10pF
CL=7pF
CL=5pF
CL=1.5pF
14
10
6
2
-2
-6
100K 1M 10M 100M 1G
FREQUENCY (Hz)
GAIN (dB)
CL=15pF
CL=1.5pF
CL=56pF
CL=35pF
VS=5V
AV=2
RL=1kΩ
RF=RG=1kΩ
12
8
4
0
-4
EL8200, EL8201, EL8401
6FN7105.3
August 29, 2007
FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE FOR
VARIOUS RF AND RG
FIGURE 8. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 9. COMMON-MODE REJECTION RA TIO vs
FREQUENCY FIGURE 10. SMALL SIGNAL BANDWIDTH vs SUPPLY
VOLTAGE
FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 12. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE
Typical Performance Curves (Continued)
10
8
6
4
2
0
100K 1M 10M 100M 1G
FREQUENCY (Hz)
GAIN (dB)
VS=5V
AV=2
RL=1kΩ
CL=1.5pF
RF=RG=2kΩ
RF=RG=500Ω
RF=RG=1kΩ
110
70
30
-10
-50
-90
1K 10K 1M 100M 1G
FREQUENCY (Hz)
GAIN (dB)
RL=1kΩ
PHASE (°)
-45
405
315
225
135
45
100K 10M
RL=150Ω
RL=150Ω
RL=1kΩ
-10
-30
-50
-70
-90
-110
100K 1M 10M 100M
FREQUENCY (Hz)
CMRR (dB)
230
170
130
210
70
50
3 3.5 4.5 5 5.5
VS (V)
BANDWIDTH (MHz)
RL=1kΩ
CL=1.5pF
AV=1
AV=2
190
110
90
150
4
100
10
1
0.1
0.01
10K 100K 1M 10M
FREQUENCY (Hz)
IMPEDANCE (Ω)
100M
2.5
1
2
0
3 3.5 4.5 5 5.5
VS (V)
PEAKING (dB)
AV=1
RL=1kΩ
CL=1.5pF
1.5
0.5
4
EL8200, EL8201, EL8401
7FN7105.3
August 29, 2007
FIGURE 13. POWER SUPPLY REJECTION RA TIO vs
FREQUENCY FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FIGURE 15. DISABLED OUTPUT ISOLA TION FREQUENCY
RESPONSE FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
FIGURE 17. HARMONIC DISTORTION vs LOAD RESISTANCE FIGURE 18. VOLTAGE AND CURRENT NOISE vs FREQUENCY
Typical Performance Curves (Continued)
-10
-30
-50
-70
-90
-110
1K 10K 10M 100M
FREQUENCY (Hz)
PSRR (dB)
100K 1M
PSRR-
PSRR+
-45
-65
-75
-55
-95
15
VOP-P (V)
DISTORTION (dBc)
VS=5V
RL=1kΩ
CL=1.5pF
AV=2
-85
342
HD2@10MHz
HD3@10MHz
HD3@5MHz
HD2@5MHz
HD2@1MHz
HD3@1MHz
-10
-30
-50
-70
-90
-110
1K 10K 1M 100M 1G
FREQUENCY (Hz)
GAIN (dB)
VS=5V
AV=1
RL=1kΩ
CL=1.5pF
10M100K
-30
-50
-80
-40
-100
140
FREQUENCY (MHz)
DISTORTION (dBc)
VS=5V
RL=1kΩ
VO=1VP-P for AV=1
VO=2VP-P for AV=2
-90
10
HD2@A
V
=2
-70
-60
HD2@AV=1
HD3@A
V
=2
HD3@A
V
=1
-60
-75
-90
-65
-100
100 2K
RLOAD (Ω)
DISTORTION (dBc)
-95
1K
VS=5V
VO=1VP-P for AV=1
VO=2VP-P for AV=2
-70
-85
-80
HD2@A
V
=2
HD2@AV=1
HD3@AV=2
HD3@A
V
=1
1K
1
100
0.1
10 100 10K 100K 10M
FREQUENCY (Hz)
VOLTAGE NOISE (nV/Hz)
CURRENT NOISE (pA/Hz)
eN
10
1K 1M
IN+
IN-
EL8200, EL8201, EL8401
8FN7105.3
August 29, 2007
FIGURE 19. CHANNEL SEPARATION vs FREQUENCY (EL8200
AND EL8201) FIGURE 20. CHANNEL SEP ARA TION vs FREQUENCY
(EL8401)
FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 22. OUTPUT SWING
FIGURE 23. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 24. OUTPUT SWING
Typical Performance Curves (Continued)
0
-20
-40
-60
-80
-100
100K 1M 10M 100M 1G
FREQUENCY (Hz)
CHANNEL SEPARATION (dB)
CH1 <=> CH2
-10
-30
-50
-70
-90
0
-20
-40
-60
-80
-100
100K 1M 10M 100M 1G
FREQUENCY (Hz)
CHANNEL SEPARATION (dB)
CH1 <=> CH2
-10
-30
-50
-70
-90
CH3 <=> CH4
CH1 <=> CH3, CH4
CH2 <=> CH3, CH4
VS=5V, AV=1, RL=1kΩ to 2.5V
10ns/DIV
0
5
2.5
VS=5V, AV=5, RL=1kΩ to 2.5V
2µs/DIV
0
5
2.5
VS=5V, AV=1, RL=1kΩ to 2.5V CL=1.5pF
10ns/DIV
2.4
2.5
2.6
VS=5V, AV=5, RL=1kΩ to 2.5V
2µs/DIV
0
5
2.5
EL8200, EL8201, EL8401
9FN7105.3
August 29, 2007
Simplified Schematic Diagram
FIGURE 25. DISABLED RESPONSE (EL8200) FIGURE 26. ENABLED RESPONSE (EL8200)
FIGURE 27. P ACKAGE POWER DISSIPA TION vs AMBIENT
TEMPERATURE
FIGURE 28. P ACKAGE POWER DISSIPA TION vs AMBIENT
TEMPERATURE
Typical Performance Curves (Continued)
VS=±2.5V, AV=1, RL=1kΩ
CH1, CH2, 0.5V/DIV, M=20ns
CH2
CH1
ENABLE
INPUT
OUTPUT
VS=±2.5V, AV=1, RL=1kΩ
CH1, CH2, 1V/DIV, M=100ns
CH2
CH1
ENABLE
INPUT
VOUT
909mW
1.4
1.2
1
0.8
0.6
0.2
00 25 50 75 100 150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
12585
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD
0.4
θ
JA
=88°C/W
SO14
θJA=110°C/W
SO8
893mW
870mW
θJA=115°C/W
MSOP10
θJA=112°C/W
QSOP16
1.136W
486mW
θJA=206°C/W
MSOP10
625mW
1
0.9
0.8
0.6
0.4
0.1
00 25 50 75 100 150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
12585
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.2
0.7
0.3
0.5
833mW
θ
JA
=120°C/W
SO14
633mW
θ
JA
=158°C/W
θJA=160°C/W
SO8
QSOP16
IN+ IN-
I1I2R6
R3
R1R2
Q1Q2
R7
VBIAS1
Q5Q6
R8
Q7
Q8
R9
Q3Q4
R4R5
VS-
OUT
VBIAS2
VS+
DIFFERENTIAL TO
DRIVE
GENERATOR
SINGLE ENDED
EL8200, EL8201, EL8401
10 FN7105.3
August 29, 2007
Description of Operation and Application
Information
Product Descr iption
The EL8200, EL8201 and EL8401 are wide bandwidth,
single supply, low power and rail-to-rail output voltage
feedback operational amplifiers. The amplifiers are internally
compensated for closed loop gain of +1 of greater.
Connected in voltage follower mode and driving a 1kΩ load,
they have a -3dB bandwidth of 200MHz. Driving a 150Ω
load, the bandwidth is about 130MHz while maintaining a
200V/us slew rate. The EL8200 is available with a pow er
down pin to reduce power to 30µA typically while the
amplifier is disabled.
Input, Output and Supply Voltage Range
The EL8200, EL8201 and EL8401 have been designed to
operate with a single supply voltage from 3V to 5.0V. Split
supplies can also be used as long as their total voltage is
within 3V to 5.0V. The amplifiers have an input commo n
mode voltage range from 0.15V below the negative supply
(VS- pin) to within 1.5V of the positive supply (VS+ pin). If the
input signal is outside the above specified range, it will cause
the output signal to be distorted.
The output of the EL8200, EL8201 and EL8401 can swing
rail to rail. As the load resistance becomes lower, the ability
to drive close to each rail is reduced. For the load resistor
1kΩ, the output swing is about 4.9V at a 5V supply. For the
load resistor 150Ω, the output swing is about 4.6V.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications th at require a gain of +1, no feedback
resistor is required. Just short the output pin to the inverting
input pin. For gains greater than +1, the feedback resistor
forms a pole with the parasitic capacitance at the inverting
input. As this pole becomes smaller, the ampli fie r’s phase
margin is reduced. This causes ringing in the time domain
and peaking in the frequency domain. Therefore, RF has
some maximum value that should not be exceeded for
optimum performance. If a large value of RF must be used, a
small capacitor in the few Pico farad range in parallel with RF
can help to reduce the ringing and peaking at the expense of
reducing the bandwidth.
As far as the output stage of the amplifier is concerned, the
output stage is also a gain stage with the load. RF and RG
appear in parallel with RL for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
Consequently, RF also has a minimum value that should not
be exceeded for optimum performance. For gain of +1, RF=0
is optimum. For the gains other than +1, optimum response
is obtained with RF between 300Ω to 1kΩ.
The EL8200, EL8201 and EL8401 have a gain bandwidth
product of 100MHz. For gains 5, its bandwidth can be
predicted by the following equation:
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency response as DC levels are changed at the output.
This is especially difficult when driving a standard video load
of 150Ω, because the change in output current with DC level.
Special circuitry has been incorporated in the EL8200,
EL8201 and EL8401 to reduce the variation of the output
impedance with the current output. This results in dG and dP
specifications of 0.03% and 0.05°, while driving 150Ω at a
gain of 2. Driving high impedance loads would give a similar
or better dG and dP performance.
Driving Capacitive Loads and Cables
The EL8200, EL8201 and EL8401 can drive 10pF loads in
parallel with 1kΩ with less than 5dB of peaking at gain of +1.
If less peaking is desired in applications, a small series
resistor (usually between 5Ω to 50Ω) can be placed in series
with the output to eliminate most peaking. However, this will
reduce the gain slightly. If the gain setting is greater than 1,
the gain resistor RG can then be chosen to make up for any
gain loss which may be created by the additional series
resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier’s output will isolate the amplifier from the cable and
allow extensive capacitive drive. However , other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL8200 can be disabled and placed its output in a high
impedance state. The turn off time for each channel is about
25ns and the turn on time is about 200ns. When disabled,
the amplifier’s supply current is reduced to 30µA typically,
thereby effectively eliminating the power consumption. The
amplifier’s power down can be controlled by standard TTL or
CMOS signal levels at the ENABLE pin. The applied logic
signal is relative to VS- pin. Letting the ENABLE pin float or
applying a signal that is less than 0.8V above VS- will enable
the amplifier. Th e amplifier will be disabled when the signal
at ENABLE pin is 2V above VS-.
Output Drive Capability
The EL8200, EL8201 and EL8401 do not have internal short
circuit protection circuitry. They have a typical short circuit
current of 70mA sourcing and 140mA sinking for the output
is connected to half way between the rails with a 10Ω
resistor. If the output is shorted indefinitely, the powe r
Gain BW×100MHz=
EL8200, EL8201, EL8401
11 FN7105.3
August 29, 2007
dissipation could easily increase such that the part will be
destroyed. Maximum reliability is maintained if the output
current never exceeds ±40mA. This limit is set by the design
of the internal metal interconnections.
Power Dissipation
With the high output drive capability of the EL8200, EL8201
and EL8401, it is possi b l e to exce ed th e 125°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to:
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
For sourcing:
For sinking:
Where:
VS = Total supply voltage
ISMAX = Maximum quiescent supply current
VOUTi = Maximum output voltage of the application for
each channel
RLOADi = Load resistance tied to ground for each channel
ILOADi = Load current for each channel
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOADi to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillati on. For
normal single supply operation, where the VS- pin is
connected to the ground plane, a sing le 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire wound resistors should be
avoided because of their additi onal series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier’s inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. S trip line design techniques are
recommended for the signal traces.
Typical Applications
VIDEO SYNC PULSE REMOVER
Many CMOS analog to digital converters have a parasitic
latch up problem when subjected to negative input voltage
levels. Since the sync tip contains no useful video
information and it is a negative going pulse, we can chop it
off. Figure 29 shows a gain of 2 connections. Figure 30
shows the complete input video signal applied at the input,
as well as the output signal with the negative going sync
pulse removed.
MULTIPLEXER
Besides the normal power down usage, the ENABLE pin of
the EL8200 can be used for multiplexing applications.
Figure 31 shows two channels with the outputs tied together ,
driving a back terminated 75 Ω video load. A 2VP-P 2MHz
sine wave is applied to Amp A and a 1VP-P 2MHz sine wave
is applied to Amp B. Figure 32 shows the ENABLE signal
and the resulting output waveform at VOUT. Observe the
break-before-make operation of the mu ltiplexing. Amp A is
on and VIN1 is passed through to the output when the
ENABLE signal is low and turns off in about 25ns when the
ENABLE signal is high. About 200ns later, Amp B turns on
and VIN2 is passed through to the output. The break-before-
make operation ensures that more than one amplifier isn’t
trying to drive the bus at the same time.
PDMAX TJMAX TAMAX
θJA
---------------------------------------------
=
PDMAX VSISMAX ΣVSVOUTi
()
VOUTi
RLi
-----------------
×+×=
PDMAX VSISMAX ΣVOUTi VS-()ILOADi
×+×=
FIGURE 29. SYNC PULSE REMOVER
5V
1K
VOUT
VIN 75Ω
+
-
75Ω
1K
75Ω
VS+
VS-
EL8200, EL8201, EL8401
12 FN7105.3
August 29, 2007
SINGLE SUPPLY VIDEO LINE DRIVER
The EL8200, EL8201 and EL8401 are wideband rail-to-rail
output op amplifiers with large output current, excellent dG,
dP, and low distortion that allow them to drive video signals
in low supply applications. Figure 33 is the single supply
non-inverting video line driver configuration and Figure 34 is
the inverting video ling driver configuration. The signal is AC
coupled by C1. R1 and R2 are used to level shift the input
and output to provide the largest output swing. RF and RG
set the AC gain. C2 isolates the virtual ground potential. RT
and R3 are the termination resi sto rs fo r the lin e. C1, C2 and
C3 are selected big enough to minimize the droop of the
luminance signal.
FIGURE 30. VIDEO SIGNAL
1V
0.5V
0V
1V
0.5V
0V
M = 10µs/DIV
VOUT
VIN
FIGURE 31. TWO TO ONE MULTIPLEXER
+2.5V
1K
2MHz
75W
+
-
1K
75W -2.5V
VOUT
75W
1VP-P
B
+2.5V
1K
2MHz +
-
1K
75W -2.5V
2VP-P
A
ENABLE
FIGURE 32. ENABLE SIGNAL
0V
-0.5V
-1.5V
-2.5V
1V
0V
M = 50ns/DIV
A
ENABLE
B-1V
FIGURE 33. 5V SINGLE SUPPL Y NON INVERTING VIDEO LINE
DRIVER
5V
RF
VOUT
VIN 75W
+
-
75W
1kW
75W
C3
470µF R3
C1
47µF
RT
10K
10K
R2
R1
1kW
RG
C2
220µF
FIGURE 34. 5V SINGLE SUPPLY INVERTING VIDEO LINE
DRIVER
5V
RF
VOUT
VIN 75Ω
-
+
75Ω
500Ω
75Ω
C3
470µF R3
C1
47µF
RT
10K
10K
R2
R1
1kΩ
RG
C2
220µF
5V
FIGURE 35. VIDEO LINE DRIVER FREQUENCY RESPONSE
5
4
3
2
1
0
-1
-2
-3
-4
-5
NORMALIZED GAIN (dB)
100K 1M 10M 100M 200M
FREQUENCY (Hz)
AV = -2
AV = 2
EL8200, EL8201, EL8401
13 FN7105.3
August 29, 2007
EL8200, EL8201, EL8401
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1 L
L1
DETAIL X 4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
INCHES
TOLERANCE NOTESSO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
14 FN7105.3
August 29, 2007
EL8200, EL8201, EL8401
Quarter Size Outline Plastic Packages Family (QSOP)
0.010 CAB
SEATING
PLANE
DETAIL X
EE1
1(N/2)
(N/2)+1
N
PIN #1
I.D. MARK
b
0.004 C
c
A
SEE DETAIL "X"
A2
4°±4°
GAUGE
PLANE
0.010
L
A1
D
B
H
C
e
A
0.007 CAB
L1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
SYMBOL
INCHES
TOLERANCE NOTESQSOP16 QSOP24 QSOP28
A 0.068 0.068 0.068 Max. -
A1 0.006 0.006 0.006 ±0.002 -
A2 0.056 0.056 0.056 ±0.004 -
b 0.010 0.010 0.010 ±0.002 -
c 0.008 0.008 0.008 ±0.001 -
D 0.193 0.341 0.390 ±0.004 1, 3
E 0.236 0.236 0.236 ±0.008 -
E1 0.154 0.154 0.154 ±0.004 2, 3
e 0.025 0.025 0.025 Basic -
L 0.025 0.025 0.025 ±0.009 -
L1 0.041 0.041 0.041 Basic -
N 16 24 28 Reference -
Rev. F 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
3. Dimensions “D” and “E1” are measur ed at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7105.3
August 29, 2007
EL8200, EL8201, EL8401
Mini SO Package Family (MSOP)
1(N/2)
(N/2)+1
N
PLANE
SEATING
N LEADS
0.10 C
PIN #1
I.D.
E1E
b
DETAIL X
3° ±3°
GAUGE
PLANE
SEE DETAIL "X"
c
A
0.25
A2
A1 L
0.25 C A B
D
A
M
B
e
C
0.08 C A B
M
H
L1
MDP0043
MINI SO PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE NOTESMSOP8 MSOP10
A 1.10 1.10 Max. -
A1 0.10 0.10 ±0.05 -
A2 0.86 0.86 ±0.09 -
b 0.33 0.23 +0.07/-0.08 -
c 0.18 0.18 ±0.05 -
D 3.00 3.00 ±0.10 1, 3
E 4.90 4.90 ±0.15 -
E1 3.00 3.00 ±0.10 2, 3
e 0.65 0.50 Basic -
L 0.55 0.55 ±0.15 -
L1 0.95 0.95 Basic -
N 8 10 Reference -
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.