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FEATURES
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Directly replaces 2k x 8 volatile static RAM
or EEPROM
Unlimited write cycles
Low-power CMOS
JEDEC standard 24-pin DIP package
Read and write access times as fast as 100 ns
Lithium energy source is electrically
disconnected to retain freshness until power
is applied for the first time
Full ±10% VCC operating range (DS1220AD)
Optional ±5% VCC operating range
(DS1220AB)
Optional industrial temperature range of
-40°C to +85°C, designated IND
PIN ASSIGNMENT
24-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A10 - Address Inputs
DQ0-DQ7 - Data In/Data Out
CE - Chip Enable
WE - Write Ena ble
OE - Output Enable
VCC - Power (+5V)
GND - Ground
DESCRIPTION
The DS1220AB and DS1220AD 16k Nonvolatile SRAMs are 16,384-bit, fully static, nonvolatile SRAMs
organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs
directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of
the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance.
There is no limit on the number of write c ycles that can be executed and no additional support ci rcuitry is
required for microprocessor interfacing.
DS1220AB/AD
16k Nonvolatile SRAM
www.dalsemi.com
14
VCC
WE
1
2
3
4
5
6
7
8
9
10
11
12 13
24
15
23
22
21
20
19
18
17
16
A7
A5
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
A6
A4
A
8
A
9
OE
A
10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
DS1220AB/AD
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READ MODE
The DS1220AB and DS1220AD execute a read c ycle when ever WE (Write Enable) is inactive (high) and
CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 11
address inputs (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be
available to the eight data output drivers within tACC (Access Time) after the last address input signal is
stable, providing that the CEand OE access times are also satisfied. If CEand OE access times are not
satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is
either tCO for CEor tOE for OE rather than address access.
WRITE MODE
The DS1220AB and DS1220AD execute a write cycle wh enev er the WE and CE signals are act ive (low)
after address inputs are stable. The latter occurring falling edge of CEorWEwill determine the start of
the write c ycle. The write cycle is terminated by the earlier rising edge of CEorWE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recover y
time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled ( CEandOE
active) thenWE will disable the outputs in tODW from its fa lling edge.
DATA RETENTION MODE
The DS1220AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5V. The DS1220AD provides full functional capability for VCC greater than 4.5 volts and write protects
by 4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The
nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resum e after VCC exceeds 4.75 volts for the DS1220AB and 4.5 volts for the
DS1220AD.
FRESHNESS SEAL
Each DS1220 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level of greater than VTP, the lithium
energy source is enabled for battery backup operation.
DS1220AB/AD
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ABSOLUTE MAXIMUM RA TINGS*
Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C; -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C; -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds
∗ This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for e xtended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS 1220AB Power Supply Voltage VCC 4.75 5.0 5.25 V
DS 1220AD Power Supply Voltage VCC 4.50 5.0 5.50 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 +0.8 V
(VCC =5V ± 5% for DS1220AB)
(TA: See Note 10)
DC ELECTRICAL CHARACTERISTICS (VCC =5V ± 10% for DS1220AD)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current IIL -1.0 +1.0 µA
I/O Leakage Curr ent
CE ≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.4V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
Standby Current CE = 2.2V ICCS1 5.0 10.0 mA
Standby Current CE = VCC-0.5V ICCS2 3.0 5.0 mA
Operating Current tCYC=200 ns
(Commercial) ICC01 75 mA
Operating Current tCYC=200ns
(Industrial) ICCO1 85 mA
Write Protection Voltage
(DS1220AB) VTP 4.5 4.62 4.75 V
Write Protection Voltage
(DS1220AD) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA =25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 510 pF
Input/Output Capacitance CI/O 512 pF
DS1220AB/AD
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(VCC =5.0V ± 5% for DS1220AB)
(TA: See Note 10)
AC ELEC TRICAL CHARACTERISTICS (VCC =5.0V ± 10% for DS1220AD)
DS1220AB-100
DS1220AD-100 DS1220AB-120
DS1220AD-120
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time tRC 100 120 ns
Access Time tACC 100 120 ns
OE to Output Valid tOE 50 60 ns
CE to Output Valid tCO 100 120 ns
OE or CE to Output Active tCOE 55ns5
Output High Z from
Deselection tOD 35 35 ns 5
Output Hold from Address
Change tOH 55ns
Write Cycle Time tWC 100 120 ns
Write Pulse Width tWP 75 90 ns 3
Address Setup Time tAW 00ns
Write Rec overy Time tWR1
tWR2
0
10 0
10 ns
ns 12
13
Output High from WE tODW 35 35 ns 5
Output Active from WE tOEW 55ns4
Data Setup Time tDS 40 50 ns 4
Data Hold Time tDH1
tDH2
0
10 0
10 ns
ns 12
13
DS1220AB/AD
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AC ELECTRICAL CHARACTERISTICS (cont’d)
DS1220AB-150
DS1220AD-150 DS1220AB-200
DS1220AD-200
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time tRC 150 200 ns
Access Time tACC 150 200 ns
OE to Output Valid tOE 70 100 ns
CE to Output Valid tCO 150 200 ns
OE or CE to Output Active tCOE 55ns5
Output High Z from
Deselection tOD 35 35 ns 5
Output Hold from Address
Change tOH 55ns
Write Cycle Time tWC 150 200 ns
Write Pulse Width tWP 100 150 ns 3
Address Setup Time tAW 00ns
Write Rec overy Time tWR1
tWR2
0
10 0
10 ns
ns 12
13
Output High Z from WE tODW 35 35 ns 5
Output Active from WE tOEW 55ns4
Data Setup Time tDS 60 50 ns 4
Data Hold Time tDH1
tDH2
0
10 0
10 ns
ns 12
13
DS1220AB/AD
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1220AB/AD
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POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE at VIH before Power-Down tPD 0µs11
VCC slew from VTP to 0v tF300 µs
VCC slew from 0V to VTP tR300 µs
CE at VIH after Power-Up tREC 2125 ms
(TA =25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time tDR 10 years 9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the
battery backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CEand WE . tWP is measured from the latter of CE or CE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output
buffers remain in a high-impedance state during this period.
DS1220AB/AD
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7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1220AB and each DS1220AD has a built-in switch that disconnects the lithium source until
VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of
VCC starting from the time power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power down condition the voltage on any pin may not exceed the voltage on VCC .
12. tWR1 , tDH1 are measured from WE going high.
13. tWR2 , tDH2 are measured from CEgoing high.
14. DS1220AB and DS1220AD modules are recognized by Underwriters Laboratory (U.L.) under file
E99151.
DC TEST CONDITIONS
Outputs Open
All Voltages Are Referenced to Ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1220AB/AD
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DS1220AB/AD NONVOLATILE SRAM, 24-PIN 720-MIL EXTENDED MODULE
PKG 24-PIN
DIM MIN MAX
A IN.
MM 1.320
33.53 1.340
34.04
B IN.
MM 0.695
17.65 0.720
18.29
C IN.
MM 0.390
9.91 0.415
10.54
D IN.
MM 0.100
2.54 0.130
3.30
E IN.
MM 0.017
0.43 0.030
0.76
F IN.
MM 0.120
3.05 0.160
4.06
G IN.
MM 0.090
2.29 0.110
2.79
H IN
MM 0.590
14.99 0.630
16.00
J IN.
MM 0.008
0.20 0.012
0.30
K IN.
MM 0.015
0.38 0.021
0.53
