AT24C01A/02/04/08/16
7
Device Addressing
The 1K, 2K, 4K, 8K and 16K EEPROM devices all require
an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure
1).
The device address word consists of a mandatory one,
zero sequence for the first four most significant bits as
shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits
for the 1K/2K EEPROM. These 3 bits must compare to
their corresponding hard-wired input pins.
The 4K E EP RO M onl y uses th e A 2 and A 1 d ev ic e add ress
bits with the third bit being a memory page address bit. The
two devic e addre ss bits m ust co mpa re to the ir corres pond-
ing hard-wired input pins. The A0 pin is no connect.
The 8K EEP ROM on ly us es the A2 device add ress bi t with
the ne xt 2 b its b eing for me mory page add ress ing. The A2
bit must compare to its c or re spon din g h ard- wir ed in put pin .
The A1 and A0 pins are no connect.
The 16K does not use any device address bits but instead
the 3 b its are us ed for m emory page addressi ng. These
page addressing bits on the 4K, 8K, and 16K devices
should be co nsidered the mo st significa nt bits of the data
word address which follows. The A0, A1 and A2 pins are no
connect.
The eighth bit of the device address is the read/write opera-
tion select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will
output a zer o. If a co mpa re is not made, the c hip wi ll r et urn
to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data
word address following the device address word and
acknowledgment. Upon receipt of this address, the
EEPROM will again respond with a zero and then clock in
the first 8-bit data word. Following rec eipt of the 8-bit data
word, the E EPROM will output a zer o and the a ddressing
devic e, s uch as a m icr oc ontrol ler , mu st t erm inat e the w rit e
sequence with a stop condition. At this time the EEPROM
enters an internally-timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and
the EEPROM will not respond until the write is complete
(refer to Figure 2).
PAGE WRITE: The 1K/2K EEPROM is capable of an 8-
byte page write, and the 4K, 8K and 16K devices are capa-
ble of 16-byte page writes.
A page write is ini tiated the sam e as a byte wr ite, b ut the
microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcon-
troller can transmit up to seven (1K/2K) or fifteen (4K, 8K,
16K) mo re data words . The EEPROM w ill respond with a
zero after each data word received. The microcontroller
must te rmin ate the page wri te se quence with a stop cond i-
tion (refer to Figure 3).
The data word address lower three (1K/2K) or four (4K, 8K,
16K) bit s are inter nall y incre mented followi ng the r eceip t of
each data word. The higher data word a ddress bits are n ot
incremented, retaining the memory page row location.
When the word address, internally generated, reaches the
page boundary, the following byte is placed at the begin-
ning of the same page. If more than eight (1K/2K) or six-
teen (4K, 8K, 16K) data words are transmitted to the
EEPROM, the data word address will “roll over” and previ-
ous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed
write cycle has started and the EEPROM inpu ts are dis-
abled, ackno wledge polling can be initi ated. This invol ves
sending a start condition followed by the devic e address
word. The rea d/write bit is repres entative of the operation
desired. O nly if the internal write cycle has completed wil l
the EEPROM respond with a zero allowing the read or
write sequence to continue.
Read Operations
Read operations are initiated the same way as write opera-
tions with the exception that the read/write select bit in the
device add ress word is set to one. There are thr ee read
operations: current address read, random address read
and sequential read.
CURRENT ADDRESS READ: The internal data word
address counter maintains the last addres s accessed dur-
ing the last read or write operation, incremented by one.
This address stays valid between operations as long as the
chip p ower is maintained. T he address “roll ov er” during
read is from the last byte of the last memory page to the
first byte of the first page. The address “roll ov er” during
write is from the las t byte of the cur rent page to the first
byte of the same page.
Once the de vice addre ss with the r ead/write select b it set
to one is clocked in and acknowledged by the EEPROM,
the current addr ess data word i s serially clo cked out. The
microcontroller does not respond with an input zero but
does generate a following stop condition (refer to Figure 4).
RANDOM READ: A ra ndom read r equire s a “du mmy” byte
write s equence to loa d in t he data word addr ess. O nce th e
device address word and data word address are clocked in
and ack nowledged by the EEPRO M, the mi crocontroller
must generate another start condition. The microcontroller
now initiates a current address read by sending a device
addres s with t he read/wr ite selec t bit high. The E EPROM
acknowledges the device address and serially clocks out