AS3400 AS3410 AS3430 L o w P o w e r A m b i e n t N o i s e - C an c e l l i n g S p e a k e r D r i v e r 1 General Description Line Input Volume control via serial interface or volume pin The AS3400/10/30 are speaker driver with Ambient Noise Cancelling function for handsets, headphones or ear pieces. It is intended to improve quality of e.g. music listening, a phone conversation etc. by reducing background ambient noise. The fully analog implementation allows the lowest power consumption, lowest system BOM cost and most natural received voice enhancement otherwise difficult to achieve with DSP implementations. The device is designed to be easily applied to existing architectures. 64 steps @ 0.75dB and MUTE, pop-free gain setting Single ended stereo or mono differential mode ANC processing Feed-forward cancellation Feed-back cancellation with filter loop transfer function definable via simple RC components Simple in production SW calibration An internal OTP-ROM can be optionally used to store the microphones gain calibration settings. 12-30dB noise reduction (headset dependent) 10-2000Hz wide frequency active noise attenuation (headset dependent) The AS3400/10/30 can be used in different configurations for best trade-off of noise cancellation, required filtering functions and mechanical designs. The simpler feed-forward topology is used to effectively reduce low frequency background noise. The feed-back topology with either 1 or 2 filtering stages can be used to reduce noise for a larger frequency range, and to even implement transfer functions like speaker equalization, Baxandall equalization, high/low shelving filter and to set a predefined loop bandwidth. The filter loop is optimized by the user for specific handset electrical and mechanical designs by dimensioning simple R, C components. Most handset implementations will make use of a single noise detecting microphone. Two microphones could be used to allow for increased flexibility of their location in the handset mechanical design. Using the bridged mode allows to even drive high impedance headsets. Monitor Function For assisted hearing, i.e. to monitor announcements Fixed (OTP prog.) ambient sound amplification to compensate headphone passive attenuation Volume controlled ambient sound amplification mixed with fixed (OTP prog.) attenuation of LineIn Incremental Functions ANC with or without music on the receiving path Improved dynamic range playback OTP ROM for automatic trimming during production (4 times programbable) Performance Parameter 2 Key Features Microphone Input 128 gain steps @ 0.375dB and MUTE with AGC Differential, low noise microphone amplifier Single ended or differential mode Improved supply for electret microphone MIC gain OTP programmable High Efficiency Headphone Amplifier 2x34mW, 0.1% THD @ 16, 1.5V supply, 100dB SNR Bridged mode for e.g. 300 loads Click and pop less start-up and mode switching www.austriamicrosystems.com 5/3.8mA @ 1.5V stereo/mono ANC; <1A quiescent Extended PSRR for 217Hz Interfaces 2-wire serial control mode & volume inputs Calibration via Line-In or 2-wire serial interface (patent pending) Single cell or fixed 1.0-1.8V supply with internal CP Package AS3400, AS3410 QFN24 [4x4mm] 0.5mm pitch AS3430 QFN32 [5.x5mm] 0.5mm pitch 3 Applications The devices are ideal for Ear pieces, Headsets, Hands-Free Kits, Mobile Phones, and Voice Communicating Devices. Revision 1.02 1 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - A p p l i c a t i o n s Figure 1. AS3410 Feed Forward ANC Block Diagram Figure 2. AS3430 Feed-Back Block Diagram www.austriamicrosystems.com Revision 1.02 2 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - A p p l i c a t i o n s Figure 3. AS3400 Feed-Back Block Diagram Figure 4. AS3400 Feed Forward Block Diagram www.austriamicrosystems.com Revision 1.02 3 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - C o n t e n t s Contents 1 General Description .................................................................................................................................................................. 1 2 Key Features............................................................................................................................................................................. 1 3 Applications............................................................................................................................................................................... 1 4 Pin Assignments ....................................................................................................................................................................... 4 4.1 Pin Descriptions.................................................................................................................................................................................... 5 5 Absolute Maximum Ratings ...................................................................................................................................................... 7 6 Electrical Characteristics........................................................................................................................................................... 8 7 Typical Operating Characteristics ............................................................................................................................................. 9 8 Detailed Description................................................................................................................................................................ 12 8.1 Audio Line Input.................................................................................................................................................................................. 12 8.1.1 Gain Stage................................................................................................................................................................................. 12 8.1.2 Parameter .................................................................................................................................................................................. 12 8.2 Microphone Input................................................................................................................................................................................ 13 8.2.1 Gain Stage & Limiter.................................................................................................................................................................. 13 8.2.2 Supply........................................................................................................................................................................................ 13 8.2.3 Parameter .................................................................................................................................................................................. 14 8.3 Headphone Output ............................................................................................................................................................................. 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 Input Multiplexer ........................................................................................................................................................................ No-Pop Function........................................................................................................................................................................ No-Clip Function ........................................................................................................................................................................ Over-Current Protection............................................................................................................................................................. Parameter .................................................................................................................................................................................. 8.4 Operational Amplifier .......................................................................................................................................................................... 15 15 15 15 15 16 16 8.4.1 Parameter .................................................................................................................................................................................. 16 8.5 SYSTEM............................................................................................................................................................................................. 8.5.1 8.5.2 8.5.3 8.5.4 Power Up/Down Conditions....................................................................................................................................................... Start-up Sequence..................................................................................................................................................................... Mode Switching ......................................................................................................................................................................... Status Indication ........................................................................................................................................................................ 8.6 VNEG Charge Pump .......................................................................................................................................................................... 17 17 17 18 19 19 8.6.1 Parameter .................................................................................................................................................................................. 19 8.7 OTP Memory & Internal Registers...................................................................................................................................................... 19 8.7.1 Register & OTP Memory Configuration ..................................................................................................................................... 19 8.7.2 OTP Fuse Burning ..................................................................................................................................................................... 20 8.8 2-Wire-Serial Control Interface ........................................................................................................................................................... 21 8.8.1 Protocol...................................................................................................................................................................................... 21 8.8.2 Parameter .................................................................................................................................................................................. 24 9 Register Description................................................................................................................................................................ 25 10 Application Information ......................................................................................................................................................... 38 11 Package Drawings and Markings.......................................................................................................................................... 43 12 Ordering Information............................................................................................................................................................. 47 www.austriamicrosystems.com Revision 1.02 4 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - P i n A s s i g n m e n t s 4 Pin Assignments Note: Pin assignment may change in preliminary data sheets. 19 CPP 20 GND 17 HPR AGND 2 17 HPVDD AS3400 16 HPL LINL 3 AS3410 16 HPR QFN 24pin 15 VSS LINR 4 QFN 24pin 15 HPL 14 QOP2R 24 VBAT QLINL 2 23 HPVDD QMICL 3 22 HPR AS3430 LINL 5 IOP1R 12 QMICR 11 MICR 10 25 n.c. 26 CPP 27 GND 28 CPN 29 VNEG 30 QOP2L 31 IOP2L MICL 7 13 QOP1R IOP1L 1 AGND 4 14 VSS 25 VNEG or open MODE_CSCL 6 QOP1R 12 32 QOP1L IOP1R 11 QLINR 10 QMICR 9 13 IOP2R MICR 8 MICL 6 VOL_CSDA 5 MICS 9 25 VNEG or open MICS 7 21 CPN 18 VBAT VOL_CSDA 4 21 HPVSS 20 HPL QFN 32pin LINR 6 19 VSS 33 Exposed Pad: VNEG or open VOL_CSDA 7 18 QOP2R Revision 1.02 QOP1R 16 IOP1R 15 QLINR 14 QMICR 13 MICR 12 MICS 11 ILED 10 17 IOP2R MICL 9 MODE_CSCL 8 www.austriamicrosystems.com 22 VNEG QMICL 1 LINL 2 MODE_CSCL 5 23 QOP1L 18 HPVDD ILED 8 AGND 1 LINR 3 24 IOP1L 19 VBAT 20 CPP 21 GND 22 CPN 23 VNEG 24 QMICL Figure 5. Pin Assignments (Top View) 5 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - P i n A s s i g n m e n t s 4.1 Pin Descriptions Note: Pin description may change in preliminary data sheets. Table 1. Pin Description for AS3400 AS3410 AS3430 Pin Name Pin Number Type Description AS3400 AS3410 AS3430 IOP1L - 24 1 ANA IN QLINL - - 2 ANA OUT Line In GainStage Output Left Channel QMICL 24 1 3 ANA OUT MIC GainStage Output Right Channel AGND 1 2 4 ANA IN Analog Reference Filter OpAmp1 Input Left Channel LINL 2 3 5 ANA IN DIG IN Line In Left Channel During Appl Trim Mode Write - CSDA During Appl Trim Mode Burn - VNEG LINR 3 4 6 ANA IN DIG IO LineIn Right Channel During Appl Trim Mode Write - CSCL During Appl Trim Mode Burn - Clock VOL_CSDA 4 5 7 MIXED IO Serial Interface Data ADC Input for volume regulation MODE_CSCL 5 6 8 DIG IN Mode Pin (PowerUp/Dn, Monitor) Serial Interface Clock MICL 6 7 9 ANA IN Microphone In Left Channel ILED - 8 10 ANA OUT Current Output for on-indication LED MICS 7 9 11 ANA OUT Microphone Supply MICR 8 10 12 ANA IN QMICR 9 11 13 ANA OUT MIC GainStage Output Right Channel QLINR 10 - 14 ANA OUT Line In GainStage Output Right Channel IOP1R 11 12 15 ANA IN FilterOpAmp1 Input Right Channel QOP1R 12 13 16 ANA IN Filter OpAmp1 Output Right Channel IOP2R 13 - 17 ANA IN Filter OpAmp2 Input Right Channel QOP2R 14 - 18 ANA OUT VSS 15 14 19 SUP IN HPL 16 15 20 ANA OUT HPVSS - - 21 SUP IN HPR 17 16 22 ANA OUT HPVDD 18 17 23 SUP IN Headphone VDD Supply VBAT 19 18 24 SUP IN VNEG ChargePump Positive Supply n.c. - - 25 - CPP 20 19 26 ANA OUT GND 21 20 27 GND CPN 22 21 28 ANA OUT VNEG 23 22 29 SUP IO www.austriamicrosystems.com Revision 1.02 Microphone Input Right Channel Filter OpAmp2 Output Right Channel Core and Periphery Circuit VSS Supply Headphone Output Left Channel Headphone VSS Supply Headphone Output Right Channel VNEG ChargePump Flying Capacitor Positive Terminal VNEG ChargePump Negative Supply VNEG ChargePump Flying Capacitor Negative Terminal VNEG ChargePump Output 6 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - P i n A s s i g n m e n t s Table 1. Pin Description for AS3400 AS3410 AS3430 Pin Name Pin Number Type AS3400 AS3410 AS3430 QOP2L - - 30 ANA OUT IOP2L - - 31 ANA IN QOP1L - 23 32 ANA OUT 25 25 33 www.austriamicrosystems.com Description Filter OpAmp2 Output Left Channel Filter OpAmp2 Input Left Channel Filter OpAmp1 Output Right Channel Exposed Pad: connect to VNEG or leave it unconnected Revision 1.02 7 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 9 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating conditions. Table 2. Absolute Maximum Ratings Parameter Min Max Units Comments Reference Ground Defined as in GND Supply terminals -0.5 2.0 V Applicable for pin VBAT, HPVDD Ground terminals -0.5 0.5 V Applicable for pins AGND Negative terminals -2.0 0.5 V Applicable for pins VNEG, VSS, HPVSS Voltage difference at VSS terminals -0.5 0.5 V Applicable for pins VSS, HPVSS Pins with protection to VBAT VNEG -0.5 5.0 VBAT+0.5 V Applicable for pins CPP, CPN Pins with protection to HPVDD VSS -0.5 5.0 HPVDD+0.5 V Applicable for pins LINL/R, MICL/R, ILED, HPR, HPL, QMICL/R, QLINL/R, IOPx, QOPx other pins VSS -0.5 5 Input Current (latch-up immunity) -100 100 mA Norm: JEDEC 17 - 200 mW PT for QFN16/24/32 package +/-2 kV Norm: JEDEC JESD22-A114C Applicable for pins MICS, VOL_CSDA, MODE_CSCL Continuous Power Dissipation (TA = +70C) Continuous Power Dissipation 1 Electrostatic Discharge Electrostatic Discharge HBM Temperature Ranges and Storage Conditions Junction Temperature +110 C Storage Temperature Range -55 +125 C Humidity non-condensing 5 85 % Moisture Sensitive Level Package Body Temperature 3 Represents a max. floor life time of 168h 260 C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020"Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". 1. Depending on actual PCB layout and PCB used www.austriamicrosystems.com Revision 1.02 8 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics VBAT = 1.0V to 1.8V, TA = -20C to +85C. Typical values are at VBAT = 1.5V, TA = +25C, unless otherwise specified. Table 3. Electrical Characteristics Symbol Parameter TA Condition Min Max Unit Ambient Temperature Range -20 +85 C GND Reference Ground 0 0 V VBAT, HPVDD Battery Supply Voltage normal operation with MODE pin high 1.0 1.8 V Two wire interface operation 1.4 1.8 V VNEG ChargePump Voltage -1.8 -0.7 V VSS Analog neg. Supply Voltages HPVSS, VSS, VNEG -1.8 -0.7 V VDELTA- Difference of Ground Supplies GND, AGND To achieve good performance, the negative supply terminals should be connected to low impedance ground plane. -0.1 0.1 V VDELTA-- Difference of Negative Supplies VSS, VNEG, HPVSS Charge pump output or external supply -0.1 0.1 V VDELTA+ Difference of Positive Supplies VBAT-HPVDD -0.25 0.25 V VMICS Microphone Supply Voltage MICS 0 3.6 V VHPVDD Pins with diode to HPVDD MICL/R, ILED, HPR, HPL, QMICL/R, QLINL/ R, IOPx, QOPx VSS 3.6 V VVBAT Pins with diode to VBAT CPP, CPN VNEG VBAT V VCONTROL Control Pins VSS 3.7 V VTRIM Line Input & Application Trim Pins LINL, LINR VNEG -0.5 or -1.8 HPVDD +0.5 or 1.8 V Symbol Parameter Condition Ileak Leakage current Supply Voltages Other pins MODE_CSCL, VOL_CSDA Min Typ Max Unit VBAT<0.8V 20 A VBAT<0.6V 10 A Block Power Requirements @ 1.5V VBAT ISYS Reference supply current Bias generation, oscillator, ILED current sink, ADC6 0.25 mA ILIN LineIn gain stage current no signal, stereo 0.64 mA IMIC Mic gain stage current no signal, stereo 2.10 mA IHP Headphone stage current no signal 1.70 mA IVNEG VNEG charge pump current no load 0.25 mA IMICS MICS charge pump current no load 0.06 mA IMIN Minimal supply current Sum of all above blocks 5.00 mA IOP1 OP1 supply current no load 0.64 mA IOP2 OP2 supply current no load 0.64 mA IILED ILED current sink current 100% duty cycle 2.50 mA IMICB Microphone bias current 200A per microphone via charge pump 1.30 mA www.austriamicrosystems.com Revision 1.02 9 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics VBAT = +1.5V, TA = +25C, unless otherwise specified. Figure 6. LIN to HPH: THD+N vs. Output Power THD+N vs POUT - 16 - single ended stereo THD+N vs POUT - 32 - stereo single ended 1 1 VBAT=1.8V VBAT=1.5V VBAT=1.0V THD+N [%] THD+N [%] VBAT=1.8V VBAT=1.5V VBAT=1.0V 0,1 0,1 0,01 0,01 0 10 20 30 40 50 0 60 5 10 15 THD+N vs POUT - 32 - bridged-tied load 25 30 35 40 THD+N vs POUT - 64 - bridged-tied load 1 1 VBAT=1.8V VBAT=1.8V VBAT=1.5V VBAT=1.5V VBAT=1.0V VABT=1.0V THD+N [%] THD+N [%] 20 Pout [mW] Pout [mW] 0,1 0,1 0,01 0,01 0 10 20 30 40 50 60 70 80 90 100 110 120 0 130 10 20 30 40 50 60 70 80 90 Pout [mW] Pout [mW] Figure 7. VNEG Charge Pump VNEG CP Voltage vs Load Current VNEG CP Efficiency 0,0 100 -0,2 95 VBAT=1.0V -0,4 90 VBAT=1.5V VBAT=1.8V 85 80 -0,8 Eff [%] V_VNEG [V] -0,6 -1,0 75 70 -1,2 65 -1,4 VBAT=1.0V VBAT=1.5V 60 -1,6 VBAT=1.8V 55 -1,8 50 0 50 100 150 200 I_VNEG [mA] www.austriamicrosystems.com 0 20 40 60 80 100 120 140 160 180 200 I_VNEG [mA] Revision 1.02 10 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 8. Microphone Supply Generation I_MICS vs dI_VBAT 7000 3 6000 2,5 5000 dI_VBAT [uA] V_MICS [V] MICS Charge Pump 3,5 2 1,5 VBAT=1.8V VBAT=1.5V VABT=1.0V 1 4000 VBAT=1.8V VBAT=1.5V VBAT=1.0V 3000 2000 1000 0,5 0 0 0 500 1000 1500 0 2000 500 1000 V_MICS vs V_VBAT 140 3,3 130 R_MICS_Switch [] V_MICS [V] 120 I_MCS = 0.0uA I_MICS = 600uA 2,9 2000 R_MICS_Switch vs V_VBAT 3,5 3,1 1500 I_MICS [uA] I_MICS [uA] 2,7 2,5 2,3 2,1 110 100 90 80 70 1,9 60 1,7 50 40 1,5 0,9 1,0 1,1 1,2 1,3 1,4 1,5 1,6 1,7 0,9 1,8 1,0 1,1 1,2 VBAT [V] 1,3 1,4 1,5 1,6 1,7 1,8 VBAT [V] Figure 9. ILED Current Sink (100% PWM setting) ILED Current ILED Current 120,0 120,0 100,0 100,0 ILED (Vbat=1.5V) ILED (Vbat=1.0V) 60,0 ILED (Vbat=1.8V) 80,0 ILED (Vbat=1.8V) I (ILED) [%] I (ILED) [%] 80,0 ILED (Vbat=1.5V) ILED (Vbat=1.0V) 60,0 40,0 40,0 20,0 20,0 0,0 0,0 0,0 0,1 0,2 0,3 0,4 0,5 www.austriamicrosystems.com 0,0 0,5 1,0 1,5 2,0 2,5 3,0 V (ILED-VNEG) [V] V (ILED-VNEG) [V] Revision 1.02 11 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 10. THD vs. Frequency @ 1.5V, 16, 25mW Figure 11. Typical Performance Data, FF Configuration www.austriamicrosystems.com Revision 1.02 12 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n 8 Detailed Description This section provides a detailed description of the device related components. 8.1 Audio Line Input The chip features one line input. The blocks can work in mono differential or in stereo single ended mode. In addition to the 12.5-25k input impedance, LineIn has a termination resistor of 10k which is also effective during MUTE to charge eventually given input capacitors. 8.1.1 Gain Stage The Line In gain stage is designed to have 63 gain steps of 0.75dB with a max gain of 0dB plus MUTE. In default, the gain will be ramped up from MUTE to 0dB during startup. There is a possibility to make the playback volume user controlled by the VOL pin with an ADC converted VOL voltage or UP/DN buttons. In monitor mode, the gain stage can be set to an fixed default attenuation level for reducing the loudness of the music. Figure 12. Line Inputs 12.5k LINR k 12.5k LINR mute QLINR 10k mute QLINR 10k AGND AGND 10k 10k QLINL mute QLINL mute LINL LINL 12.5k k AGND 12.5k stereo mode 8.1.2 k k mono differential mode Parameter VBAT=1.5V, TA= 25C, unless otherwise specified. Table 4. Line Input Parameter Symbol Parameter VLIN Input Signal Level Condition Min Typ Max Unit 0.6* VBAT VBAT VPEAK 0dB gain (12.5k // 10k) 5.6 k -46.5dB gain (25k // 10k) 7.2 k MUTE RLIN Input Impedance 10 k RLIN Input Impedance Tolerance 30 % CLIN Input Capacitance 5 pF ALIN Programmable Gain Gain Steps ALINMUTE -46.5 dB 0.75 dB Gain Step Accuracy 0.5 dB Mute Attenuation 100 dB www.austriamicrosystems.com Discrete logarithmic gain steps +0 Revision 1.02 13 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 4. Line Input Parameter (Continued) Symbol ALIN Parameter Condition Gain Ramp Rate Min Typ PotiMode, Tinit=100ms 20 ButtonMode, Tinit=400ms 80 MonitorMode 8 VATTACK Limiter Activation Level HPL/R start of neg. clipping VDECAY Limiter Release Level HPL/R tATTACK tDECAY Max Unit ms/step VPEAK VNEG +0.3 VPEAK Limiter Attack Time 4 s Limiter Decay Time 8 ms 8.2 Microphone Input The AFE offers two microphone inputs and one low noise microphone voltage supply (microphone bias). The inputs can be switched to single ended or differential mode. Figure 13. Microphone Input MICR MICR QMICR AGND QMICR AGND QMICL MICL QMICL MICL AGND stereo mode 8.2.1 mono differential mode Gain Stage & Limiter The Mic GainStage has programmable Gain within -6dB...+41.625dB in 128 steps of 0.375dB. As soft-start function is implemented for an automatic gain ramping implemented with steps of 4ms to fade in the audio at the end of the start-up sequence. A limiter automatically attenuates high input signals. The AGC has 127 steps with 0.375dB with a dynamic range of the full gain stage. In monitor mode, the gain stage can be set to an fixed (normally higher) gain level or be controlled by the VOL pin. 8.2.2 Supply The MICS charge pump is providing a proper microphone supply voltage for the AAA supply. Since AAA batteries are operating down to 1.0V, the direct battery voltage cannot be used for mic-supply. There are 2 modes. The first mode SWITCH-MODE for 1.8V supply is to have just a switch from VBAT to MICS. With this switch, the microphone current is switched off in idle mode. The second mode CHAREGPUMP_MODE for AAA batteries is the real charge pump mode, in this mode a positive voltage is generated of about 2* VBAT. It is also possible to switch off the microphone supply if not needed (e.g. playback without ANC) www.austriamicrosystems.com Revision 1.02 14 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.2.3 Parameter VBAT=1.5V, TA= 25C unless otherwise specified. Table 5. Microphone Input Parameter Symbol Parameter Condition VMICIN0 Input Signal Level AMIC = 30dB Min Typ Max 20 mVP Unit VMICIN1 AMIC = 36dB 10 mVP VMICIN2 AMIC = 42dB 5 mVP MICP to AGND 7.5 k RMICIN Input Impedance MICIN Input Impedance Tolerance -7 +33 % CMICIN Input Capacitance 5 pF AMIC Programmable Gain Gain Steps -6 Discrete logarithmic gain steps Gain Step Precision +41.6 dB 0.375 dB 0.15 dB 4 ms/step 0.67 1 0.4 1 41.625 dB AMIC Gain Ramp Rate VATTACK Limiter Activation Level VDECAY Limiter Release Level AMICLIMIT Limiter Gain Overdrive tATTACK Limiter Attack Time 5 s/step tDECAY-DEB Limiter Decay Debouncing Time 64 ms tDECAY Limiter Decay Time 4 ms/step VMICS Microphone Supply Voltage VBAT*2240mV V IMICSMIN Min. Microphone Supply Current 650 A ROUT_CP CP Output Resistance 1300 www.austriamicrosystems.com Tinit=64ms VPEAK related to VBAT or VNEG 127 @ 0.375dB VBAT=+1.0V VNEG=-0.7V MICS=+1.75V Revision 1.02 15 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.3 Headphone Output The headphone output is a true ground output using VNEG as negative supply, designed to provide the audio signal with 2x12mW @ 16-64, which are typical values for headphones. It is also capable to operate in bridged mode for higher impedance (e.g. 300) headphone. In this mode the left output is carrying the inverted signal of the right output shown in Figure 15. Figure 14. Headphone Output Single Ended Mode HPVDD MUX QMicR QOP1R QOP2R open LineInR HPR AGND HPL LineInL MUX open QOP2L QOP1L QMicL Pop Click Control LineIn gain stage HPVSS Figure 15. Headphone Output Differential Mode 8.3.1 Input Multiplexer The signal from the line-input gain stage gets summed at the input of the headphone stage with the microphone gain stage output, the first filter opamp output or the second filter opamp output. The microphone gain stage output is used per default. It is also possible to playback without ANC by only using the line-input gain stage with no other signal on the multiplexer. For the monitor mode, the setting of this input multiplexer can be changed to another source, normally to the microphone. 8.3.2 No-Pop Function The No-Pop startup of the headphone stage takes 60ms to 120ms dependent on the supply voltage. 8.3.3 No-Clip Function The headphone output stage gets monitored by comparator stages which detect if the output signal starts to clip. This signal is used to reduce the LineIn gain to avoid distortion of the output signal. A hystereses avoids jumping between 2 gain steps for a signal with constant amplitude. www.austriamicrosystems.com Revision 1.02 16 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.3.4 Over-Current Protection The over-current protection has a threshold of 150-200mA and a debouncing time of 8s. The stage is forced to OFF mode in an over-current situation. After this, the headphone stage tries to power up again every 8ms as long as the over-current situation still exists or the stage is turned off manually. 8.3.5 Parameter VBAT=1.5V, TA= 25C, unless otherwise specified. Table 6. Headphone Output Parameter Symbol Parameter Condition Min RL_HP Load Impedance Stereo mode 16 CL_HP Load Capacitance Stereo mode PHP Nominal Output Power PSRRHP Power Supply Rejection Ratio Typ Max Unit 100 pF RL=64 12 mW RL=32 24 mW RL=16 34 mW 200Hz-20kHz, 720mVpp, RL=16 90 dB 8.4 Operational Amplifier While AS3410 offers only one operational amplifier for feed-forward ANC, AS3400 and AS3430 feature an additional second operational amplifier stage to perform feed-back ANC or any other additional needed filtering. Both operational amplifiers stages can be activated and used individually. While OP1 stage is always configured as inverting amplifier, OP2 stage can be also switched to a non-inverting mode with an adjustable gain of 0...+10.5dB. Figure 16. Operational Amplifiers 0..10.5dB IOP1R IOP2R QOP1R AGND QOP2R AGND QOP2R IOP2R AGND QOP1L IOP1L QOP2L IOP2L QOP2L IOP2L AGND OP1 www.austriamicrosystems.com OP2 inverting mode Revision 1.02 0..10.5dB OP2 non-inverting mode 17 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.4.1 Parameter VBAT=1.5V, TA= 25C, unless otherwise specified. Table 7. Headphone Output Parameter Symbol Parameter Condition Min RL_OP Load Impedance Single ended 1 CL_OP Load Capacitance Single ended GBWOP Gain Band Width VOS_OP Offset Voltage VEIN_HP Equivalent Input Noise www.austriamicrosystems.com Typ Max k 100 4.3 Revision 1.02 2.6 pF MHz 6 200Hz-20kHz Unit mV V 18 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.5 SYSTEM The system block handles the power up and power down sequencing, as well as, the mode switching. 8.5.1 Power Up/Down Conditions The chip powers up when one of the following conditions is true: Table 8. Power UP Conditions # Source 1 MODE pin 2 I2C start Description In stand-alone mode, MODE pin has to be driven high to turn on the device In I2C mode, a I2C start condition turns on the device The chip automatically shuts off if one of the following conditions arises: Table 9. Power DOWN Conditions # Source 1 MODE pin 2 SERIF 3 Low Battery 4 VNEG CP OVC 8.5.2 Description Power down by driving MODE pin to low Power down by SERIF writing 0h to register 20h bit <0> Power down if VBAT is lower than the supervisor off-threshold Power down if VNEG is higher than the VNEG off-threshold Start-up Sequence The start-up sequence depends on the used mode. In stand-alone mode the sequence runs automatically, in I2C mode the sequence runs till a defined state and waits then for an I2C command. Either the automatic sequence is started by setting the CONT_PWRUP bit in addition to the PWR_HOLD bit. If only the PWR_HOLD is set all enable bits for headphone, microphone, etc have to be set manually. Figure 17. Stand-Alone Mode Start-Up Sequence www.austriamicrosystems.com Revision 1.02 19 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 18. I2C Mode Start-Up Sequence The total start-up time (inlcuding fade-in of the gain stages) can be reduced from 900ms to 600ms by OTP setting. 8.5.3 Mode Switching When the chip is in stand-alone mode (no I2C control), the mode can be switched with different levels on the MODE pin. Table 10. Operation Modes MODE MODE pin OFF LOW (VSS) ANC HIGH (VBAT) MONITOR VBAT/2 Description Chip is turned off Chip is turned on and active noise cancellation is active Chip is turned on and monitor mode is active In Monitor mode, a different (normally higher) microphone preamplifier gain can be chosen to get an amplification of the surrounding noise. This volume can be either fixed or be controlled by the VOL input. To get rid of the low pass filtering needed for the noise cancellation, the headphone input multiplexer can be set to a different (normally to MIC) source. In addition, the LineIn gain can be lowered to reduce the loudness of the music currently played back. In I2C mode, the monitor mode can be activated be setting the corresponding bit in the system register. www.austriamicrosystems.com Revision 1.02 20 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.5.4 Status Indication AS3410and AS3430 features a on-status information via the current output pin ILED. The current can be controlled in 3 steps and be switched off, by setting the PWM to 0%, 25%, 50% or 100% duty cycle of a 50kHz signal. If LOW_BAT is active, ILED switches to blinking with 1Hz, 50% duty cycle and 50% current setting. 8.6 VNEG Charge Pump The VNEG charge pump uses one external 1uF capacitor to generate a negative supply voltage out of the battery input voltage to supply all audio related blocks. This allows a true-ground headphone output with no more need of external dc-decoupling capacitors. 8.6.1 Parameter VBAT=1.5V, TA= 25C, unless otherwise specified. Table 11. Headphone Output Parameter Symbol Parameter Condition Min Typ Max Unit VIN Input voltage VBAT 1.0 1.5 1.8 V VOUT Output voltage VNEG -0.7 -1.5 -1.8 V CEXT External flying capacitor 1 F 8.7 OTP Memory & Internal Registers The OTP memory consists of OTP register and the OTP fuses.The OTP register can be written as often as wanted but will lose the content on power off. The OTP fuses are intended to store basic chip configurations as well as the microphone gain settings to optimize the ANC performance and get rid of sensitivity variations of different microphones. Burning the fuses can only be done once and is a permanent change, which means the fuses keep the content even if the chip is powered down. This AS3400/10/30 offers 4 register set for storing the microphone gain making it possible to change the gain 3 times for re-calibration or other purposes. When the chip is controlled by a microcontroller via I2C, the OTP memory don't has to be used. 8.7.1 Register & OTP Memory Configuration Figure 19 is showing the principal register interaction. Figure 19. Register Access OTP WRITE BURN OTP Register I2C IF OTP READ normal I2C write normal I2C read 10h...16h; 30h...35h LOAD OTP Fuses Register Register 0x8,0x9,0xA 8h...21h 0xB, 0xC, 0x21 OTP path is default but can be switched by register setting www.austriamicrosystems.com Revision 1.02 21 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n Registers 0x8, 0x9, 0xA, 0xB, 0xC and 0x21 have only effect when the corresponding "REG_ON" bit is set, otherwise the chip operates with the OTP Register settings which are loaded from the OTP fuses at every start-up. All registers settings can be changed several times, but will loose the content on power off. When using the I2C mode, the chip configuration has to be loaded from the microcontroller after every start-up. In stand alone mode the OTP fuses have to be programmed for a permanent change of the chip configuration. A single OTP cell can be programmed only once. Per default, the cell is "0"; a programmed cell will contain a "1". While it is not possible to reset a programmed bit from "1" to "0", multiple OTP writes are possible, but only additional unprogrammed "0"-bits can be programmed to "1". Independent of the OTP programming, it is possible to overwrite the OTP register temporarily with an OTP write command at any time. This setting will be cleared and overwritten with the hard programmed OTP settings at each power-up sequence or by a LOAD operation. The OTP memory can be accessed in the following ways: LOAD Operation. The LOAD operation reads the OTP fuses and loads the contents into the OTP register. A LOAD operation is automatically executed after each power-on-reset. WRITE Operation. The WRITE operation allows a temporary modification of the OTP register. It does not program the OTP. This operation can be invoked multiple times and will remain set while the chip is supplied with power and while the OTP register is not modified with another WRITE or LOAD operation. READ Operation. The READ operation reads the contents of the OTP register, for example to verify a WRITE command or to read the OTP memory after a LOAD command. BURN Operation. The BURN operation programs the contents of the OTP register permanently into the OTP fuses. Don't use old or nearly empty batteries for burning the fuses. Attention: If you once burn the OTP_LOCK bit, no further programming, e.g. setting additional "0" to "1", of the OTP can be done. For production, the OTP_LOCK bit must be set to avoid an unwanted change of the OTP content during the livetime of the product. 8.7.2 OTP Fuse Burning In most stand alone applications, the I2C pins are not accessible. Burning the fuses can be done by switching the line inputs into a special mode to access the chip by I2C over the line input connections. This allows trimming of the microphone gain with no openings in the final housing and so no influence to the acoustic of the headset. This mode is called "Application Trimm" mode, or short "APT". (Patent Pending) During the application trimm mode LINR has to provide the clock, while LINL has to provide the data for the I2C communication. Please note that the OTP register cannot be accessed directly but have to be enabled before a read or write access. This is independent whether you access the OTP register via the normal I2C pins or in application trimm mode via LINL and LINR. Please refer to the detailed register description to get more information on how the registers can be accessed. To achieve a proper burning of the fuses, the negative supply has to be buffered by applying an external negative supply during burning. This voltage can also be applied to the LINL terminal. An internal switch is connecting LINL and VNEG during the fuse burning. LINR has to provide the clock for burning the fuses. The below flow chart shows the principle steps of the OTP burning process. The application trimm mode can only be entered at a specific timing during the start-up sequence. The device offers the possibility to change microphone gain settings 3 times by using alternative registers. The selection which register set is being used to set the microphone gain is done by the "lock" bits of the corresponding registers. A more detailed description of the individual steps is available in an application note. www.austriamicrosystems.com Revision 1.02 22 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 20. OTP Burning Process enter "Application Trimm" mode ANC pre burning measurements MAIN_LOCK set? Y Y ALT1_LOCK set? N N write, burn OTP fuses 30-35h, 16-17h Set MAIN_LOCK and SEQ_LOCK Y ALT2_LOCK set? N MIC trimm #2 write, burn OTP fuses 10-11h Set ALT1_LOCK ALT3_LOCK set? Y N MIC trimm #3 write, burn OTP fuses 12-13h Set ALT2_LOCK MIC trimm #4 write, burn OTP fuses 14-15h Set ALT3_LOCK leave "Application Trimm" mode No further MIC trimming possible trimm verification verification OK? N leave "Application Trimm" mode N Device trimming failed Y leave "Application Trim" mode ANC post burning measurements verification OK? Y Device trimming succeeded 8.8 2-Wire-Serial Control Interface There is an I2C slave block implemented to have access to 64 byte of setting information. The I2C address is: Adr_Group8 - audio processors 8Eh_write 8Fh_read 8.8.1 Protocol Table 12. 2-Wire Serial Symbol Definition Symbol Definition RW Note S Start condition after stop R 1 bit Sr Repeated start R 1 bit DW Device address for write R 1000 1110b (8Eh) DR Device address for read R 1000 1111b (8Fh) WA Word address R 8 bit www.austriamicrosystems.com Revision 1.02 23 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 12. 2-Wire Serial Symbol Definition Symbol Definition RW Note A Acknowledge W 1 bit N No Acknowledge R 1 bit reg_data Register data/write R 8 bit data (n) Register data/read W 8 bit P Stop condition R 1 bit WA++ Increment word address internally R during acknowledge AS3400 AS3410 AS3430 (=slave) receives data AS3400 AS3410 AS3430 (=slave) transmits data Figure 21. Byte Write S DW A WA A reg_data A P write register WA++ Figure 22. Page Write S DW A WA A reg_data 1 A reg_data 2 write register WA++ A write register WA++ ... reg_data n A P write register WA++ Byte Write and Page Write formats are used to write data to the slave. The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The devicewrite address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally. www.austriamicrosystems.com Revision 1.02 24 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 23. Random Read S DW A WA A Sr DR A data N P read register WA++ Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master. The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address. In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus. Figure 24. Sequential Read S DW A WA A Sr DR A data read register WA++ A reg_data 2 read register WA++ A ... reg_data n N P read register WA++ Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently. Figure 25. Current Address Read S DR A read register WA++ data A reg_data 2 read register WA++ A ... reg_data n N P read register WA++ To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition. www.austriamicrosystems.com Revision 1.02 25 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - D e t a i l e d D e s c r i p t i o n 8.8.2 Parameter Figure 26. 2-Wire Serial Timing TS TSU TH THD TL TPD CSDA CSCL 1-7 Start Address Condition 8 9 1-7 R/W ACK 8 Data 9 ACK 1-7 8 9 Data ACK Stop Condition 1 VBAT >=1.4V , TA=25C, unless otherwise specified. Table 13. 2-Wire Serial Parameter Symbol Parameter Condition Min Typ Max Unit VCSL CSCL, CSDA Low Input Level (max 30%DVDD) 0 - 0.87 V VCSH CSCL, CSDA High Input Level CSCL, CSDA (min 70%DVDD) 2.03 - 5.5 V HYST CSCL, CSDA Input Hysteresis 200 450 800 mV VOL CSDA Low Output Level - - 0.4 V Tsp Spike insensitivity 50 100 - ns TH Clock high time TL Clock low time at 3mA max. 400kHz clock speed 500 ns ns max. 400kHz clock speed 500 TSU CSDA has to change Tsetup before rising edge of CSCL 250 - - ns THD No hold time needed for CSDA relative to rising edge of CSCL 0 - - ns TS CSDA H hold time relative to CSDA edge for start/stop/rep_start 200 - - ns TPD CSDA prop delay relative to lowgoing edge of CSCL 50 ns 1. Serial interface operates down to VBAT = 1.0V but with 100kHz clock speed and degraded parameters. www.austriamicrosystems.com Revision 1.02 26 - 51 Addr Name b7 b6 b5 b4 b3 b2 08h MIC_L 09h MIC_R 0Ah LINE_IN 0Bh GP_OP_L 0Ch GP_OP_R 0Dh-0Fh 18h-1Fh reserved reserved MIC_MODE 0: StereoSingleEnd 1: MonoDiff MIC_REG_ON 0: use reg 30h & 31h 1: use reg 08h & 09h LIN_REG_ON Revision 1.02 b1 b0 OP2L_ON OP1L_ON OP2R_ON OP1R_ON Audio Registers 00-07h reserved System Register 20h SYSTEM 21h PWR_SET 0: use reg 33h and VOL pin 1: use reg 0Ah MICL_VOL<6:0> Gain from MICL to QMICL or Mixer = -6dB...+41.6dB; 127 steps of 0.375dB MICR_VOL<6:0> Gain from MICR to QMICR or Mixer = -6dB...+41.6dB; 127 steps of 0.375dB LIN_MODE LIN_VOL<5:0> 0: StereoSingleEnd 1: MonoDiff 0: MUTE; 0x01..0x3F: Gain from LINR/L to QLINR/L or Mixer = -46.5dB...+0dB; 63 steps of 0.75dB HP_MUX<1:0> OP2L<3:0> 0: MIC; 1: OP1; 2: OP2; 3: open 0: OP2L inverting mode; 0x1..0xF: OP2L non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB OP_REG_ON HP_MODE OP2R<3:0> 0: use reg 34h 1: use reg 0Bh & 0Ch 0: StereoSingleEnd 1: MonoDiff 0: OP2R inverting mode; 0x1..0xF: OP2R non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB Design_Version<3:0> 0100 ILED<1:0> PWR_REG_ON 0: 1: use reg 21h LOW_BAT 22h-2Fh reserved HP_ON 0: OFF; 1: 25%; 2: 50%; 3: 100% PWRUP_ COMPLETE REG3F_ON MONITOR_ON CONT_PWRUP PWR_HOLD MIC_ON LIN_ON MICS_CP_ON MICS_ON Data Sheet - R e g i s t e r D e s c r i p t i o n Table 14. I2C Register Overview AS3400 AS3410 AS3430 1v0 www.austriamicrosystems.com 9 Register Description 27 - 51 Name b7 b6 b5 b4 b3 b2 b1 b0 Revision 1.02 10h ANC_L2 TEST_BIT_5 11h ANC_R2 ALT1_LOCK 12h ANC_L3 TEST_BIT_6 13h ANC_R3 ALT2_LOCK 14h ANC_L4 TEST_BIT_7 15h ANC_R4 ALT3_LOCK 16h MICS_CNTR 17h PWRUP SEQ_LOCK 30h ANC_L TEST_BIT_1 31h ANC_R TEST_BIT_2 32h MIC_MON 33h AUDIO_SET 34h GP_OP 35h OTP_SYS 3Eh CONFIG_1 3Fh CONFIG_2 MON_MODE 0: fixed volume 1: adj. volume VOL_PIN_OFF MICL_VOL_OTP2<6:0> Gain from MICL to QMICL or Mixer = MUTE, -5.625dB...+41.6dB; 127 steps of 0.375dB MICR_VOL_OTP2<6:0> Gain from MICR to QMICR or Mixer = MUTE, -5.625dB...+41.6dB; 127 steps of 0.375dB MICL_VOL_OTP3<6:0> Gain from MICL to QMICL or Mixer = MUTE, -5.625dB...+41.6dB; 127 steps of 0.375dB MICR_VOL_OTP3<6:0> Gain from MICR to QMICR or Mixer = MUTE, -5.625dB...+41.6dB; 127 steps of 0.375dB MICL_VOL_OTP4<6:0> Gain from MICL to QMICL or Mixer = MUTE, -5.625dB...+41.6dB; 127 steps of 0.375dB MICR_VOL_OTP4<6:0> Gain from MICR to QMICR or Mixer = MUTE, -5.625dB...+41.6dB; 127 steps of 0.375dB LowBat + 100mV FAST_START<4:0> 0: ~900ms; 0Eh: ~600ms 0: potentiometer 1: up/down button 0: StereoSingleEnd 1: MonoDiff 0: StereoSingleEnd 1: MonoDiff 0: StereoSingleEnd 1: MonoDiff OP2_OTP<3:0> 0: MIC; 1: OP1; 2: OP2; 3: - 0: OP2 inverting mode; 0x1..0xF: OP2 non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB 0: write reg 30h.. 35h 1: lock reg 30h..35h MIC_AGC_OFF MICL_VOL_OTP<6:0> Gain from MICL to QMICL or Mixer = MUTE, -5.625dB...+41.6dB; 127 steps of 0.375dB MICR_VOL_OTP<6:0> Gain from MICR to QMICR or Mixer =MUTE, -5.625dB...+41.6dB; 127 steps of 0.375dB MIC_MON_OTP<6:0> Gain from MICl/R to QMICL/R or Mixer = MUTE, -5.625dB...+41.6dB; 0.375dB steps, if MON_MODE is set to 0 Gain from MICl/R to QMICL/R or Mixer = MUTE, -5.625dB...+41.6dB; 0.375dB steps, adjustable by VOL pin if MON_MODE is set to 1 VOL_PIN_ LIN_MODE_ MIC_MODE_ HP_MODE_ LIN_MON_ATTEN<2:0> MODE OTP OTP OTP 0: no attenuation; HP_MUX_OTP<1:0> MAIN_LOCK LIN_AGC_OFF TEST_BIT_3 MON_HP_MUX<1:0> ILED_OTP<1:0> 0: MIC; 1: OP1; 2: OP2; 3: - 0: OFF; 1: 25%; 2: 50%; 3: 100% 1..6: LIN_VOL<6:0> shift by -6dB...-36dB 7: MUTE OP2_ON_OTP OP1_ON_OTP MICS_CP_OFF I2C_MODE EXTBURNCLK TM34 BURNSW TM_REG34-35 TM_REG30-33 OTP_MODE<1:0> 28 - 51 0: READ; 1: LOAD; 2: WRITE; 3: BURN Data Sheet - R e g i s t e r D e s c r i p t i o n Addr OTP Register AS3400 AS3410 AS3430 1v0 www.austriamicrosystems.com Table 14. I2C Register Overview AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 15. MIC_L Register Name Base Default MIC_L 2-wire serial 00h Left Microphone Input Register Offset: 08h Configures the gain for the left microphone input and defines the microphone operation mode. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 MIC_MODE 0 R/W Selects the microphone input mode 0: single ended stereo mode 1: mono differential mode 6:0 MICL_VOL<6:0> 000 0000 R/W Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain Table 16. MIC_R Register Name Base Default MIC_R 2-wire serial 00h Right Microphone Input Register Offset: 09h Configures the gain for the right microphone input and enables register 08h & 09h. This register is reset at POR. Bit Bit Name Default Access 7 MIC_REG_ON 0 R/W Defines which registers are used for the microphone settings. 0: settings of register 30h and 31h are used 1: settings of register 08h and 09h are used 6:0 MICR_VOL<6:0> 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain www.austriamicrosystems.com Bit Description Revision 1.02 29 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 17. LINE_IN Register Name Base Default LINE_IN 2-wire serial 00h Line Input Register Offset: 0Ah Configures the attenuation for the line input, defines the line input operation mode and enables register 0Ah. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 LIN_REG_ON 0 R/W Defines which source is used for the line input settings. 0: settings of register 33h and VOL pin are used 1: register 0Ah is used 6 LIN_MODE 0 R/W Selects the line input mode 0: single ended stereo mode 1: mono differential mode 5:0 LIN_VOL<5:0> 00 0000 R/W Volume settings for line input, adjustable in 63 steps of 0.75dB 00 0000: MUTE 00 0001:-46.5dB gain 00 0010:-45.75dB gain .. 11 1110:-0.75dB gain 11 1111:.0 dB gain Table 18. GP_OP_L Register Name Base Default GP_OP_L 2-wire serial 00h Left General Purpose Operational Amplifier Register Offset: 0Bh Enables the left opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This register is reset at POR. Bit Bit Name Default Access 7:6 HP_MUX<1:0> 00 R/W Multiplexes the analog audio signal to HP amp 00: MIC: selects QMICL/R output 01: OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 5:2 OP2L<3:0> 0000 R/W Mode and volume settings for left OP2, adjustable in 15 steps of 0.75dB 0000: OP2L in inverting mode 0001: 0 dB gain, OP2L in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting 1 OP2L_ON 0 R/W Enables left OP 2 0: left OP2 is switched off 1: left OP2 is enabled 0 OP1L_ON 0 R/W Enables left OP 1 0: left OP1 is switched off 1: left OP1 is enabled www.austriamicrosystems.com Bit Description Revision 1.02 30 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 19. GP_OP_R Register Name Base Default GP_OP_R 2-wire serial 00h Right General Purpose Operational Amplifier Register Offset: 0Ch Enables the right opamp stages, defines opamp 2 mode and gain and sets the HP mode. This register is reset at POR. Bit Bit Name Default Access 7 OP_REG_ON 0 R/W Defines which register is used for the opamp and HP settings. 0: settings of register 33h and 34h are used 1: register 0B and 0Ch are used Bit Description 6 HP_MODE 0 R/W Selects the line input mode 0: single ended stereo mode 1: mono differential mode 5:2 OP2R<3:0> 0000 R/W Mode and volume settings for right OP2, adjustable in 15 steps of 0.75dB 0000: OP2R in inverting mode 0001: 0 dB gain, OP2R in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting 1 OP2R_ON 0 R/W Enables right OP 2 0: right OP2 is switched off 1: right OP2 is enabled 0 OP1R_ON 0 R/W Enables right OP 1 0: right OP1 is switched off 1: right OP1 is enabled Table 20. SYSTEM Register Name Base Default SYSTEM 2-wire serial 31h Offset: 20h SYSTEM Register This register is reset at a POR. Bit Bit Name Default Access 7:4 Design_Version<3:0> 0100 R 3 TESTREG_ON 0 R/W 0: normal operation 1: enables writing to test register 3Eh & 3Fh to configure the OTP and set the access mode. 2 MONITOR_ON 0 R/W Enables the monitor mode 0: normal operation 1: monitor mode enabled 1 CONT_PWRUP 0 R/W Continues the automatic power-up sequence when using the I2C mode 0: chip stops the power-up sequence after the supplies are stable, switching on individual blocks has to be done via I2C commands 1: automatic power-up sequence is continued 0 PWR_HOLD 1 R/W 0: power up hold is cleared and AFE will power down 1: is automatically set to on after power on www.austriamicrosystems.com Bit Description AFE number to identify the design version 0100: for chip version 1v0 Revision 1.02 31 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 21. PWR_SET Register Name PWR_SET Base Default 2-wire serial 0x11 1111b (stand alone mode) 0x00 0000b (I2C mode) Power Setting Register Offset: 21h Please be aware that writing to this register will enable/disable the corresponding blocks, while reading gets the actual status. It is not possible to read back e.g ILED settings. This register is reset at POR. Bit Bit Name Default Access 7 PWR_REG_ON 0 R/W 6:5 ILED<1:0> 00 W Sets the current sunk into ILED 00: current sink switched OFF 01: 25% 10: 50% 11: 100% 6 LOW_BAT x R VBAT supervisor status 0: VBAT is above brown out level 1: BVDD has reached brown out level 5 PWRUP_COMPLETE x R Power-Up sequencer status 0: power-up sequence incomplete 1: power-up sequence completed 4 HP_ON 0 W 0: switches HP stage off 1: switches HP stage on x R 0: HP stage not powered 1: normal operation 0 W 0: switches microphone stage off 1: switches microphone stage on x R 0: microphone stage not powered 1: normal operation 0 W 0: switches line input stage off 1: switches line input stage on x R 0: line input stage not powered 1: normal operation 0 W 0: switches microphone supply charge pump off 1: switches microphone supply charge pump on x R 0: microphone supply charge pump not powered 1: normal operation 0 W 0: switches microphone supply off 1: switches microphone supply on x R 0: microphone supply not enabled 1: normal operation 3 2 1 0 MIC_ON LIN_ON MICS_CP_ON MICS_ON www.austriamicrosystems.com Bit Description Defines which register is used for the power settings. 0: all blocks stay on as defined in the start-up sequence 1: register 21h is used Revision 1.02 32 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 22. ANC_L2 Register Name ANC_L2 Base Default 2-wire serial 80h (OTP) Left OTP Microphone Input Register (2nd OTP option) Offset: 10h Bit Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Name Default Access 7 TEST_BIT_5 1 R 6:0 MICL_VOL_OTP2 <6:0> 000 0000 R/W Bit Description for testing purpose only Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain Table 23. ANC_R2 Register Name Base Default ANC_R2 2-wire serial 00h (OTP) Right OTP Microphone Input Register (2nd OTP option) Offset: 11h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7 ALT1_LOCK 0 R/W 0: additional bits can be fused inside register 10h & 11h 1: OTP fusing for register 10h & 11h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP2 <6:0> 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain www.austriamicrosystems.com Bit Description Revision 1.02 33 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 24. ANC_L3 Register Name Base Default ANC_L3 2-wire serial 80h (OTP) Left OTP Microphone Input Register (3rd OTP option) Offset: 12h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7 TEST_BIT_6 1 R 6:0 MICL_VOL_OTP3 <6:0> 000 0000 R/W Bit Description for testing purpose only Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain Table 25. ANC_R3 Register Name Base Default ANC_R3 2-wire serial 00h (OTP) Right OTP Microphone Input Register (3rd OTP option) Offset: 13h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 ALT2_LOCK 0 R/W 0: additional bits can be fused inside register 12h & 13h 1: OTP fusing for register 12h & 13h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP3 <6:0> 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain www.austriamicrosystems.com Revision 1.02 34 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 26. ANC_L4 Register Name Base Default ANC_L4 2-wire serial 80h (OTP) Left OTP Microphone Input Register (4th OTP option) Offset: 14h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7 TEST_BIT_7 1 R 6:0 MICL_VOL_OTP4 <6:0> 000 0000 R/W Bit Description for testing purpose only Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain Table 27. ANC_R4 Register Name ANC_R4 Base Default 2-wire serial 00h (OTP) Right OTP Microphone Input Register (4th OTP option) Offset: 15h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 ALT3_LOCK 0 R/W 0: additional bits can be fused inside register 14h & 15h 1: OTP fusing for register 14h & 15h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP4 <6:0> 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain Table 28. MICS_CNTR Register Name Base Default MICS_CNTR 2-wire serial 00h (OTP) Offset: 16h Microphone Supply Regsiter Configures the low battery trehshold value Bit Bit Name Default Access 3 LowBat 0 R/W www.austriamicrosystems.com Bit Description 0: default LowBat value 1: 100mV increase of LowBat threshold Revision 1.02 35 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 29. PWRUP_CNTR Register Name Base Default PWRUP_CNTR 2-wire serial 00h (OTP) PowerUp Control Register Offset: 17h Configures chip start-up speed. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7 SEQ_LOCK 0 R/W 0: additional bits can be fused inside register 16h & 17h 1: OTP fusing for register 16h & 17h gets locked, no more changes can be done. 6:2 FAST_START <4:0> 0 0000 R/W 0h: ~900ms start-up time 0Eh: ~600ms start-up time 1 LIN_AGC_OFF 0 R/W 0: Line Input AGC enabled 1: Line Input AGC switched off 0 MIC_AGC_OFF 0 R/W 0:Microphone Input AGC enabled 1: Microphone Input AGC switched off www.austriamicrosystems.com Bit Description Revision 1.02 36 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 30. ANC_L Register Name Base Default ANC_L 2-wire serial 80h (OTP) Left OTP Microphone Input Register Offset: 30h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7 TEST_BIT_1 1 R 6:0 MICL_VOL_OTP <6:0> 000 0000 R/W Bit Description for testing purpose only Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain Table 31. ANC_R Register Name Base Default ANC_R 2-wire serial 80h (OTP) Right OTP Microphone Input Register Offset: 31h Bit Bit Name Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Default Access 7 TEST_BIT_2 1 R 6:0 MICR_VOL_OTP <6:0> 000 0000 R/W www.austriamicrosystems.com Bit Description for testing purpose only Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain Revision 1.02 37 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n vvvvvvvvvv Table 32. MIC_MON Register Name Base Default MIC_MON 2-wire serial 00h (OTP) OPT Microphone Monitor Mode Register Configures the gain for the microphone input in monitor mode. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Offset: 32h Bit Bit Name Default Access Bit Description 7 MON_MODE 0 R/W 0: monitor mode is working with fixed microphone gain 1: monitor mode uses adjustable gain via the VOL pin 6:0 MIC_MON_OTP <6:0> 000 0000 R/W Volume settings for microphone input during monitor mode, adjustable in 127 steps of 0.375dB. If MON_MODE bit is set to 1 the gain can be further adjusted via the VOL pin. 00 0000: MUTE 00 0001: -5.625dB gain 00 0010: -5.25 dB gain .. 11 1110: 41.250dB gain 11 1111: 41.625 dB gain Table 33. AUDIO_SET Register Name Base Default AUDIO_SET 2-wire serial 00h (OTP) OPT Audio Setting Register Offset: 33h Configures the audio settings. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 VOL_PIN_OFF 0 R/W 0: VOL pin is enabled 1: line in volume settings can only be done via I2C. VOL_PIN_MODE has to be set to 1 in this mode. 6 VOL_PIN_MODE 0 R/W 0: VOL pin is in potentiometer mode 1: VOL pin is in up/down button mode 5 LIN_MODE_OTP 0 R/W 0: line input stage operating in single ended mode 1: line input operating in mono balanced 4 MIC_MODE_OTP 0 R/W 0: microphone input stage operating in single ended mode 1: normal operating in mono balanced 3 HP_MODE_OTP 0 R/W 0: headphone stage operating in single ended mode 1: normal operating in mono balanced 2:0 LIN_MON_ATTEN <6:0> 000 R/W Volume settings for line input during monitor mode, adjustable in 7 steps of 6dB and mute. 000: 0dB gain 001: -6dB gain .. 110: -36dB gain 111: MUTE www.austriamicrosystems.com Revision 1.02 38 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 34. GP_OP Register Name Base Default GP_OP 2-wire serial 00h (OTP) OTP General Purpose Operational Amplifier Register Enables the opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Offset: 34h Bit Bit Name Default Access Bit Description 7:6 HP_MUX_OTP<1:0> 00 R/W Multiplexes the analog audio signal to HP amp 00: MIC: selects QMICL/R output 01:OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 5:2 OP2_OTP<3:0> 0000 R/W Mode and volume settings for OP2, adjustable in 15 steps of 0.75dB 0000: OP2L in inverting mode 0001: 0 dB gain, OP2L in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting 1 OP2_ON 0 R/W 0: OP2 is switched off 1: left OP2 is enabled 0 OPL_ON 0 R/W 0: OP1 is switched off 1: OP1 is enabled Table 35. OTP_SYS Register Name Base Default OTP_SYS 2-wire serial 40h (OTP) OTP System Settings Register Offset: 35h Defines several system settings for OTP operation. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7 MAIN_LOCK 0 R/W 6 TEST_BIT_3 1 R 5:4 MON_HP_MUX <1:0> 00 R/W 3:2 ILED_OTP<1:0> 00 W 1 MICS_CP_OFF 0 R/W 0: MICS charge pump is enabled 1: MICS charge pump is switched off 0 I2C 0 R/W 0: I2C and stand alone mode start-up possible 1: chip starts-up in I2C mode only www.austriamicrosystems.com Bit Description 0: additional bits can be fused inside the OTP 1: OTP fusing gets locked, no more changes can be done for testing purpose only Multiplexes the analog audio signal to HP amp in monitor mode 00: MIC: selects QMICL/R output 01: OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal Sets the current sunk into ILED 00: current sink switched OFF 01: 25% 10: 50% 11: 100% Revision 1.02 39 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e g i s t e r D e s c r i p t i o n Table 36. CONFIG_1 Register Name Base Default CONFIG_1 2-wire serial 00h OTP Configuration Register Offset: 3Eh Controls the clock configuration. This is a special register, writing needs to be enabled by writing 9h to Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7:4 - 0000 n/a 3 EXTBURNCLK 0 n/a 2:0 - 000 n/a Bit Description 0: ext. clock for OTP burning disabled 1: ext. clock for OTP burning enabled Table 37. CONFIG_2 Register Name Base Default CONFIG_2 2-wire serial 00h OTP Access Configuration Register Offset: 3Fh Bit Controls the OTP access. This is a special register, writing needs to be enabled by writing 9h to Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Name Default Access 7:6 - 000 n/a 5 TM34 0 n/a This Register defines the Register bank selection for Register TM_REG34-35 and TMREG30-33. Depending on TM34 you can select either between Register bank 14h-17h and 10h-13h enabled or 30h-33h and 34h-37h enabled. 0: test mode Registers 14h-17h and 10h-13h disabled test mode Registers 30h-33h and 34h-37h enabled 1: test mode Registers 14h-17h and 10h-13h enabled test mode Registers 30h-33h and 34h-37h disabled 4 BURNSW 0 n/a 0: BURN switch from LINL to VNEG is disabled 1: BURN switch from LINL to VNEG is enabled 3 TM_REG34-35 0 n/a 0: test mode for Register 34h-35h disabled test mode for Register 14h-17h disabled 1: test mode for Register 34h-35h enabled test mode for Register 14h-17h enabled 2 TM_REG30-33 0 n/a 0: test mode for Register 30h-33h disabled test mode for Register 10h-13h disabled 1: test mode for Register 30h-33h enabled test mode for Register 10h-13h enabled 1:0 OTP_MODE<1:0> 00 R/W Controls the OTP access 00: READ 01: LOAD 10: WRITE 11: BURN www.austriamicrosystems.com Bit Description Revision 1.02 40 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 10 Application Information Figure 27. AS3410 High Performance Application in Bridged Mode for High Impedance Headsets For high impedance headphones two AS3410 can be used in a bridged mode each one driving one side of the headphone load as differential output to get 24mW output power per channel. Also the microphone inputs can be used in differential mode to reduce the noise level. Figure 28. AS3400 Feed-Forward ANC Block Diagram www.austriamicrosystems.com Revision 1.02 41 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Figure 29. AS3430 on Music Player with ANC www.austriamicrosystems.com Revision 1.02 42 - 51 D C B 1 R GND 2 1 50k P1A MICS Volume Control Vpos AAA Batterie U3 Battery Socket R18 10k Monitor Button 2 R17 10k R20 150R Vpos R19 150R Vneg 2 3 ON/OFF Bypass slider 3 1 3 Alternative Volume Control MICS Line Input 4 3 1 2 4.7uF C15 MICS C3 10u Values dep. on headphone characteristics, also other topologies possible 1 L 3 U2 1 Revision 1.02 2 2 2 Vneg LED 220R 3 2 1 C6 2 QOP1R VSS HPL HPR C? 13 14 15 16 17 18 GND 22nF GND 22nF Mic LPF cap dep. on headphone characteristics 2 1 C8 R? con_mic - + J4 10u C10 - + Right Speaker J? HEADPHONE for open loop noise cancelation - R? VBAT HVDD U? AS3410 Vpos C13 Values dep. on 2.2uF headphone characteristics, also other topologies possible 1 C7 Left Speaker - + J? con_mic + C12 2.2uF C1 2.2uF J1 R13 2k2 20 AS3410 MODE_CSCL VOL_CSDA LINR LINL AGND QMICL C? R1 R14 2k2 VCC 6 5 4 3 2 1 R? R? 3 23 QOP1L 24 IOP1L MICL 7 MICS 9 ILED 8 22 VNEG 21 1uF CPN MICR 10 19 CPP IOP1R GND QMICR 11 www.austriamicrosystems.com 12 A 1 2 1 Vneg 4 4 D C B A AS3400 AS3410 AS3430 1v0 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Figure 30. AS3410 Feed-Forward Application Example 43 - 51 D C B 1 Line Input U2 2 1 3 Vpos 2 Battery Socket AAA Batterie U3 R19 150R R20 150R 50k P1A MICS 3 Monitor Button Volume Control Alternative Volume Control MICS R GND L 4 3 1 2 10k R18 R17 10k 4 D1 LED 8 7 6 5 4 3 2 1 Vpos R14 2k2 220R ON/OFF Bypass slider R13 2k2 MODE/CSCL VOL/CSDA LINR LINL AGND QMICL QLINL IOP1L U1 AS3430 R25 Vpos R3 R2 R1 Mic Supply resistors depend on Mic Spec C15 4.7uF MICS Power Led R6 R5 R4 C5 C4 C2 C20 2.2uF 5 1u C6 C1 3 LPF and NOTCH-Filter to avoid oscillation by acustic (Headphone-Speaker <=> Mic) 1 MICL 9 C3 10u AS3430 2.2u 1 C12 3 4 3 C9 30 2 3 2 32 QOP1L 31 IOP2L ILED 10 QOP2L 1 MICR 12 2.2u C13 5 Vneg R15 C7 Mic LPF cap dep. on Headphone Characteris tics QMICR 13 MICS 11 29 VNEG 28 CPN 27 GND QLINR 14 R9 25 VSS HPL HVSS HPR HVDD VBAT R16 3 4 5 2 IOP2R QOP2R NC 26 CPP IOP1R 15 QOP1R 16 2 2 Revision 1.02 C17 R11 10u C10 6 C14 R12 Vneg - + 6 - + HEADPHONE for closed loop noise cancelation LPF and NOTCH-Filter to avoid oscillation by acustic (Headphone-Speaker <=> Mic) R10 C11 Vpos C16 17 18 19 20 21 22 23 24 LINE www.austriamicrosystems.com LINE A 1 3 4 5 2 C18 C8 7 7 Mic LPF cap dep. on Headphone Characteristics 8 8 D C B A AS3400 AS3410 AS3430 1v0 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Figure 31. AS3430 Feed-back Application Example 44 - 51 Revision 1.02 D C B A 1 CPU for I2C control e.g. bluetooth, audio codec differential audio output R? 2k2 Vpos C? C? R? 2k2 Vpos 470nF 470nF Vneg 220 R3 MICL 2 AGND 4.7uF C6 MICS_F AGND PGND 6 5 4 3 2 1 Vneg 2.2uF C7 MICS MICL MODE/CSCL VOL/CSDA LINR LINL AGND PGND 10uF 100nF PGND C3 C2 MICS 7 1uF C1 CPP 20 2 24 QMICL 23 VNEG CPN 22 AS3400 CPN QMICR 9 MICR 8 MICR 21 GND QLINR 10 Vpos 19 13 14 15 16 HPL HPR Vpos Vneg U1 AS3400 3 3 RC filter network IOP2R QOP2R VSS HPL HPR 17 18 PGND HPVDD VBAT QOP1R CPP IOP1R 11 www.austriamicrosystems.com 12 1 PGND 10uF 100nF PGND C5 C4 Vpos 2.2uF C? 2.2uF C? Mic LPF cap dep. on Headphone Characteristics 2 1 R? 2k2 AGND AGND C? 2 1 R4 2k2 MICS_F 1V - 1.8V 4 T-a m1 - + - + s1 PGND supply from power management unit 4 D C B A AS3400 AS3410 AS3430 1v0 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Figure 32. AS3400 Mode Differential Feed Forward Application Example 45 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g 11 Package Drawings and Marking Figure 33. QFN Marking Table 38. Package Code AYWWZZZ YY WW I ZZ last two digits of the year manufacturing week plant identifier free choice / traceability code www.austriamicrosystems.com Revision 1.02 46 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g Figure 34. AS3400, AS3410, 24-pin QFN 0.5mm Pitch www.austriamicrosystems.com Revision 1.02 47 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g Figure 35. AS3430 32-pin QFN 0.5mm Pitch www.austriamicrosystems.com Revision 1.02 48 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - R e v i s i o n H i s t o r y Revision History Revision Date Owner Description 0.1 19.1.2010 pkm initial release 0.2 29.1.2010 pkm updated block diagrams and application schematics 1.0 27.10.2010 hgt update to new datasheet template 1.01 11.11.2010 hgt updated package drawings, QFN markings and operating temperature range 1.02 24.11.2010 hgt inserted register description for MIC_R and updated register table overview Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com Revision 1.02 49 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - O r d e r i n g I n f o r m a t i o n 12 Ordering Information The devices are available as the standard products shown in Table 39. Table 39. Ordering Information Ordering Code Description Delivery Form Package AS3400-EQFP Low Power Ambient Noise-Cancelling Speaker Driver Tape & Reel dry pack QFN 24 [4.0x4.0x0.85mm] 0.5mm pitch AS3410-EQFP Low Power Ambient Noise-Cancelling Speaker Driver Tape & Reel dry pack QFN 24 [4.0x4.0x0.85mm] 0.5mm pitch AS3430-EQFP Low Power Ambient Noise-Cancelling Speaker Driver Tape & Reel dry pack QFN 32 [5.0x5.0x0.85mm] 0.5mm pitch Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect For further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com Revision 1.02 50 - 51 AS3400 AS3410 AS3430 1v0 Data Sheet - C o p y r i g h t s Copyrights Copyright (c) 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.02 51 - 51