1. General description
The TJA1048 is a dual high-speed CAN transceiver that provides an interface between a
Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus.
The transceiver is design ed for high-speed CAN applications in the automo tive industry,
providing the differenti al transmit and receive capa bility to (a microcontroller with) a CAN
protocol cont ro ller.
The TJA1048 belongs to the third generation of high- speed CAN transceivers from NXP
Semiconductors, offering significant improvements over first- and second-generation
devices such as the TJA1040. It offers improved Electro Magnetic Compatibility (EMC)
and ElectroStatic Discharge (ESD) performance, and also features:
•Ideal passive behavior to the CAN bus when the supply voltage is off
•A very low-current Standby mode with bus wake-up capability on both channels
•Can be interfaced directly to microcontrollers with supply voltages from 3 V to 5 V
The TJA1048 imple m ents the CAN physic al laye r as def ine d in th e cur re n t ISO11898
standard (ISO11898-2:2003, ISO11898-5:2007) and the pending updated version of
ISO 11898-2:2016. Pending the release of the updated version of ISO11898-2:2016
including CAN FD and SAE J2284-4/5, additional timing parameters defining loo p delay
symmetry are specified. This implementation enable s r eliable communication in the CAN
FD fast phase at data rates up to 5 Mbit/s.
These features make the TJA1048 an excellent choice for all types of HS-CAN networks
containing mor e than one HS-CAN interf ace that require a low-p ower mode with wake-up
capability via the CAN bus, especially for Body Control and Gateway units.
2. Features and benefits
2.1 General
Two TJA1042/3 HS-CAN transceivers combined monolithically in a single package
Fully ISO 11898-2:2003 and ISO 11898-5:2007 compliant
Timing guaranteed for data rates up to 5 Mbit/s in the CAN FD fast phase
Suitable for 12 V and 24 V systems
Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)
VIO input allows for direct interfacing with 3 V to 5 V microcontrollers
Available in SO14 and HVSON14 packages
Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability
TJA1048
Dual high-speed CAN transceiver with Standby mode
Rev. 5 — 23 May 2016 Product data sheet
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Product data sheet Rev. 5 — 23 May 2016 2 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
Dark green product (halogen free and Restriction of Hazardous Subst ances (RoHS)
compliant)
AEC-Q100 qualified
2.2 Low-power management
Very low-current Standby mode with host and bus wake-up capability
Functional behavior predictable under all supply conditions
Transceiver disengages from the bus when not powered up (zero load)
Wake-up receiver powered by VIO; allows shut down of VCC
2.3 Protection
High ESD handling capability on the bus pins
Bus pins protected against transients in automotive environments
Transmit Data (TXD) dominant time-out function
Undervolt age detection on pins VCC and VIO
Thermally protected
3. Quick reference data
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.5 - 5.5 V
VIO supply voltage on pin VIO 2.8 - 5.5 V
Vuvd(VCC) undervoltage detection voltage on
pin VCC
3.5 - 4.5 V
Vuvd(VIO) undervoltage detection voltage on
pin VIO
1.3 2.0 2.7 V
ICC supply current Standby mode - 0.5 2 A
Normal mode
both channels recessive - - 20 mA
one channel dominant - - 80 mA
both channels dominant - 90 140 mA
IIO supply current on pin VIO Standby mode; VTXD =V
IO -16.526A
Normal mode
both channels recessive - - 35 A
one channel dominant - - 300 A
both channels dominant - - 550 A
VESD electrostatic discharge voltage IEC 61000-4-2 at pins CANHx and CANLx 6- +6kV
VCANH voltage on pin CANH pins CANH1 and CANH2 58 - +58 V
VCANL voltage on pin CANL pins CANL1 and CANL2 58 - +58 V
Tvj virtual junction temperature 40 - +150 C
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Product data sheet Rev. 5 — 23 May 2016 3 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
4. Ordering information
Table 2. Or dering information
Type number Package
Name Description Version
TJA1048T SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
TJA1048TK HVSON14 plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 4.5 0.85 mm SOT1086-2
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Product data sheet Rev. 5 — 23 May 2016 4 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
5. Block diagram
Fig 1. Block diagram
WAKE-UP
FILTER
CANH1
CANL1
13
12
SLOPE CONTROL
AND DRIVER
NORMAL
RECEIVER
LOW-POWER
RECEIVER
VCC
VIO
WAKE-UP
FILTER
CANH2
CANL2
10
9
SLOPE CONTROL
AND DRIVER
NORMAL
RECEIVER
LOW-POWER
RECEIVER
VCC
VIO
VCC
VCC/VIO
UNDERVOLTAGE
DETECTION
TEMPERATURE
PROTECTION
MODE
CONTROL
VCC
MUX and
DRIVER
TIME-OUT
TXD1 1
VIO
14
STBN1
RXD1 4
MUX and
DRIVER
TIME-OUT
TXD2 6
VIO
8
STBN2
RXD2 7
11 3
2
GNDA 5GNDB
015aaa146
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Product data sheet Rev. 5 — 23 May 2016 5 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
6. Pinning information
6.1 Pinning
6.2 Pin description
[1] Pins 2 and 5 must be connected together externally in the application. HVSON14 package die supply
ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to
board ground. For enhanced thermal and electrical performance, it is recommended that the exposed
center pad also be soldered to board ground.
Fig 2. Pin configuration diagram: SO14 Fig 3. Pin configuration diagram: HVSON14
TJA1048T
TXD1 STBN1
GNDA CANH1
V
CC
CANL1
RXD1 V
IO
GNDB CANH2
TXD2 CANL2
RXD2 STBN2
015aaa144
1
2
3
4
5
6
7 8
10
9
12
11
14
13
terminal 1
index area
TJA1048TK
015aaa207
TXD1 1
GNDA 2
RXD1 4
GNDB 5
TXD2 6
RXD2 7
STBN114
CANH113
CANL112
VIO
11
CANH210
CANL29
STBN28
3
VCC
Tabl e 3. Pin descripti on
Symbol Pin Description
TXD1 1 transmit data input 1
GNDA 2[1] transceiver groun d
VCC 3 transceiver supply voltage
RXD1 4 receive data output 1; reads out data from bus line1
GNDB 5[1] transceiver groun d
TXD2 6 transmit data input 2
RXD2 7 receive data output 2; reads out data from bus line 2
STBN2 8 standby control input 2 (HIGH = Normal mode, LOW = Standby mode)
CANL2 9 LOW-level CAN bus line 2
CANH2 10 HIGH-level CAN bus line 2
VIO 11 supply voltage for I/O level adapter
CANL1 12 LOW-level CAN bus line 1
CANH1 13 HIGH-level CAN bus line 1
STBN1 14 standby control input 1 (HIGH = Normal mode, LOW = Standby mode)
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Product data sheet Rev. 5 — 23 May 2016 6 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
7. Functional description
The TJA1048 is a dual HS-CAN stand- alone transceiver with Standby mode and robust
ESD handling capability. It combines the functionality of two TJA1042/3 transceivers with
improved EMC and quiescent current performance. Improved slope control and high DC
handling capability on the bus pins provide additional application flexibility.
7.1 Operating modes
The TJA1048 supports two operating modes per transceiver, Normal and Standby. The
operating mode can be selected independently for each transceiver via pins STBN1 and
STBN2 (see Table 4).
7.1.1 Normal mode
A HIGH level on pin STBN1/STBN2 selects Normal mode. In this mode, the transceiver
can transmit and receive data via the bus lines CANH1/CANL1 and CANH2/CANL2 (see
Figure 1 for the block diagram). The differential receiver converts the analog data on the
bus lines into digital data which is output on pin RXD1/RXD2. The slopes of the output
signals on the bus lines are controlled interna lly and are optimized in a way that
guarantees the lowest possible EME.
7.1.2 Standby mode
A LOW level on pin STBN1/STBN2 selects Standby mode. In Standby mode, the
transceiver is not able to transmit or correctly receive data via the bus lines. The
transmitter and Normal-mod e receiver blocks are switched off to reduce supply current,
and only a low-powe r differential receiver monitors the bus lines for activity.
In Standby mode, the bus lines are biased to ground to minimize the system supply
current. The low-power receiver is supplied by VIO, and is capable of detecting CAN bus
activity even if VIO is the only supply voltage available. When pin RXD1/RXD2 goes LOW
to signal a wake-up request, a transition to Normal mode will not be triggered until
STBN1/STBN2 is forced HIGH.
7.1.3 Remote wake-up (via the CAN bus)
A dedicated wake-up sequence (specified in ISO11898-5:2007) must be received to
wake-up the TJA1048 from a low-power mode. This filtering is necessary to avoid
spurious wake-up events due to a dominant clamped CAN bus or dominant phases
caused by noise or spikes on the bus.
A valid wake-up pattern consists of:
•A dominant phase of at least twake(busdom) followed by
•A recessive phase of at least twake(busrec) followed by
•A dominant phase of at least twake(busdom)
Table 4. Operating modes
Mode Pin STBN1/STBN2 Pin RXD1/RXD2
LOW HIGH
Normal HIGH bus dominant bus recessive
Standby LOW wake-up request detected no wake-up request detected
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Product data sheet Rev. 5 — 23 May 2016 7 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
The complete dominant-recessive -domin ant pattern must be received within tto(wake)bus to
be recognized as a valid wake-up pattern (see Figure 4). Pin RXD1/RXD2 will remain
recessive until the wake-up event has been triggered.
After a wake-up sequence has been detected, the TJA1048 will remain in Standby mode
with the bus signals reflected on RXD1/RXD2. Note that dominant or recessive phases
lasting less than tfltr(wake)bus will not be detected by the low-power differential receiver and
will not be reflected on RXD1/RXD2 in Standby mode.
A wake-up event will not be registered if any of the following events occurs while a
wake-up sequence is being transmitted:
•The TJA1048 switches to Normal mode
•The complete wake-up pattern was not received within tto(wake)bus
•A VIO undervoltage is detected (VIO < Vuvd(VIO); see Section 7.2.3)
If any of these events occurs while a wake-up sequence is being received, the internal
wake-up logic will be reset and the complete wake-up sequence will have to be
re-transmitted to trigger a wake-up event.
7.2 Fail-safe features
7.2.1 TXD dominant time-out function
A 'TXD dominant time-out' timer is started when pin TXD1/TXD2 is set LOW. If the LOW
state on this pin persists for longer than tto(dom)TXD, the transmitter is disabled, releasing
the bus lines to recessive state. This function pre vents a hardware and/or software
application failure from driving the bus lines to a permanent do minant state (blocking all
network communications). The TXD dominant time-out timer is reset when pin
TXD1/TXD2 is set HIGH. The TXD dominant time-out time also defines the minimum
possible bit rate of 40 kbit/s. The TJA104 8 has two TXD dominant time-out timers that
operate independently of each other.
Fig 4. Wake-up timing
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5;'
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WZDNHEXVGRP WZDNHEXVUHF WIOWUZDNHEXV
WIOWUZDNHEXV
WIOWUZDNHEXV WWIOWUZDNHEXV
WZDNHEXVGRP
W
WRZDNHEXV
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Product data sheet Rev. 5 — 23 May 2016 8 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
7.2.2 Internal biasing of TXD1, TXD2, STBN1 and STBN2 input pins
Pins TXD1 and TXD2 have internal pull-ups to VIO and pins STBN1 and STBN2 have
internal pull-downs to GNDA and GNDB. This ensures a safe, d efined state if any of these
pins is left floating. Pins GNDA and GNDB must be connected together in the application.
Pull-up/pull-down current s flow in these pins in all states. Pins TXD1 and TXD2 should be
held HIGH in Standby mode to minimize the supply current; pins STBN1 and STBN2
should be held LOW.
7.2.3 Undervoltage detection on pins VCC and VIO
Should VCC drop below the VCC undervolt age detection le vel, Vuvd(VCC), both transceiver s
will switch to Standby mode. The logic state of pins STBN1 and STBN2 will be ignored
until VCC has recovered.
Should VIO drop below the VIO undervoltage d etection level, V uvd(VIO), the transceivers will
switch off and disengage from the bus (zero load) until VIO has recovered.
7.2.4 Overtemperature protection
The output dri vers are protecte d against over temperature cond itions. If the virtual ju nction
temperature exceed s the shut down junction temperature , Tj(sd), both output drivers will be
disabled. When the virtual junction temperature drops below Tj(sd) again, the output
drivers will recover independently once TXD1/TXD2 has been reset to HIGH. Including
the TXD1/TXD2 condition prevents output driver oscillation due to small variations in
temperature.
7.3 VIO supply pin
Pin VIO should be connecte d to the microcontrolle r supply volta ge (see Figure 7). This will
adjust the signal levels of pins TXD1, TXD2, RXD1, RXD2, STBN1 and STBN2 to the I/O
levels of the microcontroller. Pin VIO also provides the internal supply voltage for the
transceiver’s low-power differential receiver. For applications ru nning in low-power mode,
this allows the bus lines to be monito re d fo r act ivity ev en if ther e is no supp ly voltage on
pin VCC.
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Product data sheet Rev. 5 — 23 May 2016 9 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
8. Limiting values
[1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients)
never exceed these values.
[2] According to IEC TS 62228 (2007), Section 4.2.4; parameters for standard pulses defined in ISO7637 part 2: 2004-06.
[3] According to IEC TS 62228 (2007), Section 4.3; DIN EN 61000-4-2.
[4] According to AEC-Q100-002.
[5] According to AEC-Q100-003.
[6] According to AEC-Q100-011 Rev-C1. The classification level is C4B.
[7] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj =T
amb +PRth(vj-a), where Rth(vj-a) is a
fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
9. Thermal characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol Parameter Conditions Min Max Unit
Vxvoltage on pin x[1] on pins CANH1, CANL1, CANH2 and CANL2 58 +58 V
on any other pin 0.3 +7 V
V(CANH-CANL) voltage between pin CANH
and pin CANL 27 +27 V
Vtrt transient voltage on pins CANH1, CANL1, CANH2 and CANL2 [2]
pulse 1 100 - V
pulse 2a - 75 V
pulse 3a 150 - V
pulse 3b - 100 V
VESD electrostatic discharge voltage IEC 61000-4-2 (150 pF, 330 )[3]
on pins CANH1, CANL1, CANH2 and CANL2 6+6 kV
Human Body Model (HBM); 100 pF, 1.5 k[4]
on pins CANH1, CANL1, CANH2 and CANL2 6+6 kV
at any other pin 4+4 kV
Machine Model (MM); 200 pF, 0.75 H, 10 [5]
at any pin 300 +300 V
Charged Device Model (CDM); field Induced
charge; 4 pF [6]
at corner pins 750 +750 V
at any pin 500 +500 V
Tvj virtual junction temperature [7] 40 +150 C
Tstg storage temperature 55 +150 C
Table 6. Thermal characteris tics
Va lues determined for free convection conditions on a JESD51-7 board.
Symbol Parameter Conditions Value Unit
Rth(vj-a) thermal resist ance from virtual junction to
ambient SO14 65 K/W
HVSON14 42 K/W
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Product data sheet Rev. 5 — 23 May 2016 10 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
10. Static characteristics
Table 7. Static characteristics
Tvj =
40
C to + 150
C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V; RL=60
unless specified otherwise; all voltages are
defined with respec t to gr ound; positive curre nts flow into the device[1].
Symbol Parameter Conditions Min Typ Max Unit
Supply; pin VCC
VCC supply voltage 4.5 - 5.5 V
ICC supply current Standby mode; VTXD =V
IO [2] -0.52A
Normal mode
both channels recessive - - 20 mA
one channel dominant - - 80 mA
both channels dominant - 90 140 mA
Vuvd(VCC) undervoltage detection
voltage on pin VCC
3.5 - 4.5 V
I/O level adapter supply; pin VIO
VIO supply voltage on pin VIO 2.8 - 5.5 V
IIO supply current on pin VIO Standby mode; VTXD =V
IO [2] - 16.5 26 A
Normal mode
both channels recessive - - 35 A
one channel dominant - - 300 A
both channels dominant - - 550 A
Vuvd(VIO) undervoltage detection
voltage on pin VIO
1.3 2.0 2.7 V
Standby mode control input; pins STBN1 and STBN2
VIH HIGH-level input voltage 0.7VIO -V
IO + 0.3 V
VIL LOW-level input voltage 0.3 - 0.3VIO V
IIH HIGH-level input current VSTBN[3] =V
IO 1-10A
IIL LOW-level input current VSTBN =0V 1- +1A
CAN transmit data input; pins TXD1 and TXD2
VIH HIGH-level input voltage 0.7VIO -V
IO + 0.3 V
VIL LOW-level input voltage 0.3 - 0.3VIO V
IIH HIGH-level input current VTXD[4] =V
IO 5- +5A
IIL LOW-level input current VTXD =0V 260 150 30 A
Ciinput capacitance [5] - 5 10 pF
CAN receive data output; pins RXD1 and RXD2
IOH HIGH-level output current VRXD[6] =V
IO 0.4 V; VIO =V
CC 831mA
IOL LOW-level output current VRXD = 0.4 V; bus dominant 2 5 12 mA
Bus lines; pins CANH1, CANL1, CANH2 and CANL2
VO(dom) dominant output voltage VTXD =0V; t<t
to(dom)TXD
pin CANH1/CANH2; RL=50 to 60 2.75 3.5 4.5 V
pin CANL1/CANL2; RL=50 to 60 0.5 1.5 2.25 V
Vdom(TX)sym transmitter dominant
voltage symmetry Vdom(TX)sym = VCC VCANH[7] VCANL[8] 300 - +300 mV
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Product data sheet Rev. 5 — 23 May 2016 11 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
VTXsym transmitter voltage
symmetry VTXsym = VCANH[7] +V
CANL[8];
fTXD = 250 kHz; CSPLIT =4.7nF [5]
[9] 0.9VCC -1.1V
CC V
VO(dif) diff erential output voltage dominant: Normal mode
VTXD =0V; t<t
to(dom)TXD;
VCC = 4.75 V to 5.2 5 V
RL=50to 65
1.5 - 3 V
VTXD =0V; t<t
to(dom)TXD;
VCC = 4.75 V to 5.2 5 V
RL=45to 70
1.4 - 3.3 V
VTXD =0V; t<t
to(dom)TXD;
VCC = 4.75 V to 5.2 5 V
RL=2240
1.5 - 5 V
recessive
Normal mode: VTXD =V
IO; no load 50 - +50 mV
Standby mode 0.2 - +0.2 V
VO(rec) recessive output voltage Normal mode; VTXD =V
IO; no load 2 0.5VCC 3V
Standby mode; no load 0.1 - +0.1 V
Vth(RX)dif dif f erential receiver
threshold voltage Normal mode:
30 V VCANL +30 V;
30 V VCANH +30 V
0.5 0.7 0.9 V
Standby mode;
12 V VCANL +12 V;
12 V VCANH +12 V
0.4 0.7 1.15 V
Vrec(RX) receiver recessive
voltage Normal mode;
12 V VCANL +12 V;
12 V VCANH +12 V
3- 0.5V
Vdom(RX) receiver dominant voltage Normal mode;
12 V VCANL +12 V;
12 V v VCANH +12 V
0.9 - 8.0 V
Vhys(RX)dif differential receiver
hysteresis voltage Normal mode:
30 V VCANL +30 V;
30 V VCANH +30 V
50 120 200 mV
IO(sc)dom dominant short-circuit
output current VTXD =0V; t<t
to(dom)TXD; VCC =5 V
pin CANH1/CANH2; VCANH =3V to
+40 V 100 70 40 mA
pin CANL1/CANL2; VCANL =3V to
+40 V 40 70 100 mA
IO(sc)rec recessive short-circuit
output current Normal mode; VTXD =V
IO;
VCANH =V
CANL = 40 V to +40 V 5- +5mA
ILleakage current VCC =V
IO =0V or V
CC =V
IO = shorted to
ground via 47 k; VCANH =V
CANL =5V 5- +5A
Riinput resistance 9 15 28 k
Riinput resistance deviation between pin CANH1/CANH2 and pin;
CANL1/CANL2 1- +1%
Table 7. Static characteristics …continued
Tvj =
40
C to + 150
C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V; RL=60
unless specified otherwise; all voltages are
defined with respec t to gr ound; positive curre nts flow into the device[1].
Symbol Parameter Conditions Min Typ Max Unit
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NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2] Total supply current (ICC +I
IO) in Standby mode is typically 17 A, with a maximum value of 26 A.
[3] STBN refers to the input signal on pin STBN1 o r pin STBN2.
[4] TXD refers to the input signal on pin TXD1 or pin TXD2.
[5] Not tested in production; guaranteed by design.
[6] RXD refers to the output signal on pin RXD1 or pin RXD2.
[7] CANH refers to the input/output signal on pin CANH1 or pin CANH2.
[8] CANL refers to the input/output signal on pin CANL1 or pin CANL2.
[9] The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 9.
Ri(dif) differential input
resistance 19 30 52 k
Ci(cm) common-mode input
capacitance [5] - - 20 pF
Ci(dif) differential input
capacitance [5] - - 10 pF
Temperature detection
Tj(sd) shutdown junction
temperature [5] - 190 - C
Table 7. Static characteristics …continued
Tvj =
40
C to + 150
C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V; RL=60
unless specified otherwise; all voltages are
defined with respec t to gr ound; positive curre nts flow into the device[1].
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 5 — 23 May 2016 13 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
11. Dynamic characteristics
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2] See Figure 6.
Table 8. Dynamic character istics
Tvj =
40
C to + 150
C; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to 5.5 V; RL=60
unless specified otherwise; all voltages are
defined with respec t to gr ound; positive curre nts flow into the device[1].
Symbol Parameter Conditions Min Typ Max Unit
Transceiver tim ing; pins CANH1, CANH2, CANL1, CANL2, TXD1, TXD2, RXD1 and RXD2; see Figure 8 and Figure 5
td(TXD-busdom) delay time from TXD to bus dominant Normal mode - 65 - ns
td(TXD-busrec) delay time from TXD to bus recessive Normal mode - 90 - ns
td(busdom-RXD) delay time from bus dominan t to RX D Normal mode - 60 - ns
td(busrec-RXD) delay time from bus recessive to RXD Normal mode - 65 - ns
td(TXDL-RXDL) delay time from TXD LOW to RXD LOW Normal mode 60 - 250 ns
td(TXDH-RXDH) delay time from TXD HIGH to RXD HIGH Normal mode 60 - 250 ns
tbit(bus) transmitted recessive bit width tbit(TXD) = 500 ns [2] 435 - 530 ns
tbit(TXD) = 200 ns [2] 155 - 210 ns
tbit(RXD) bit time on pin RXD tbit(TXD) = 500 ns [2] 400 - 550 ns
tbit(TXD) = 200 ns [2] 120 - 220 ns
trec receiver timing symme try tbit(TXD) = 500 ns 65 - +40 ns
tbit(TXD) = 200 ns 45 - +15 ns
tto(dom)TXD TXD dominant time-out time VTXD = 0 V; Normal mode 0.5 2 5 ms
td(stb-norm) standby to normal mode delay time 7 25 4 7 s
twake(busdom) bus dominant wake-up time Standby mode 0.5 - 5 s
twake(busrec) bus recessive wake-up time Standby mode 0.5 - 5 s
tto(wake)bus bus wake-up time-out time 0.5 2 5 ms
tfltr(wake)bus bus wake-up filter time Standby m ode 0.5 1.5 5 s
TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 14 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
Fig 5. CAN transceiver timing diagram
Fig 6. Loop delay symmetry timing diagram
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TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 15 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
12. Application information
12.1 Application diagram
12.2 Application hints
Further information on the application of the TJA1048 can be found in NXP application
hints AH1014 Application Hints - Standalone high speed CAN transceiver
TJA1042/TJA1043/TJA1048/TJA1051.
Optionally, the 5 V supply can be switched off in Standby mode.
Fig 7. Typical application with 3 V microcontroller
TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 16 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
13. Test information
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive app licat ion s.
Fig 8. Timing test circuit for CAN transceiver
Fig 9. Test circuit for measur ing transceiver driver symmetry
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TJA1048
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TJA1048
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CSPLIT
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TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 17 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
14. Package outline
Fig 10. Package outline SOT108 (SO14)
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TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 18 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
Fig 11. Package outline SOT1086 (HVSON14)
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TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 19 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate prec a u tio ns ar e taken as
described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when thro ugh-hole and
Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
W ave soldering is a joining te chnology in which the joints are m ade by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solde r lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orientation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering ve rsus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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Product data sheet Rev. 5 — 23 May 2016 20 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
•Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are :
•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 12) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting th e process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) an d cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low en ough that the
packages and/or boards are not damaged. Th e peak temperature of the package
depends on p ackage thickness and volume and is classified in accordance with
Table 9 and 10
Moisture sensitivity precautions, as indicated on the packing, must be respe cted at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 12.
Table 9. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 10. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
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Product data sheet Rev. 5 — 23 May 2016 21 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
For further informa tion on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering of HVSON packages
Section 17 contains a brief intr oduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
•AN10365 ‘Surface mount reflow soldering description”
•AN10366 “HVQFN application information”Section 16
MSL: Moisture Sensitivity Level
Fig 12. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 22 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
18. Appendix: ISO 11898-2:2016 parameter cross-reference list
Table 11. ISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016 NXP data sheet
Parameter Notation Symbol Parameter
HS-PMA dominant output characteristics
Single ended voltage on CAN_H VCAN_H VO(dom) dominant output voltage
Single ended voltage on CAN_L VCAN_L
Differential voltage on normal bus load VDiff VO(dif) differential output voltage
Differential voltage on effective resistance during arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
Driver symmetry VSYM VTXsym transmitter voltage symmetry
Maximum HS-PMA driver output current
Absolute current on CAN_H ICAN_H IO(sc)dom dominant short-circuit output
current
Absolute current on CAN_L ICAN_L
HS-PMA recessive ou tput characteristics, bus biasing active/inactive
Single ended output voltage on CAN_H VCAN_H VO(rec) recessive output voltage
Single ended output voltage on CAN_L VCAN_L
Differential output voltage VDiff VO(dif) diff erential output voltage
Optional HS-PMA transmit dominant timeout
Tr ansmit dominant timeout, long tdom tto(dom)TXD TXD dominant time-out time
Tr ansmit dominant timeout, short
HS-PMA static receiver input characteristics, bus biasing active/in active
Recessive state differential input voltage range
Dominant state differential input voltage range VDiff Vth(RX)dif differential receiver threshold
voltage
Vrec(RX) receiver recessive voltage
Vdom(RX) receiver dominant voltage
HS-PMA receiver input resistance (matching)
Differential internal resistance RDiff Ri(dif) differential input resistance
Single ended internal resistance RCAN_H
RCAN_L
Riinput resistance
Matching of internal resistance MR Riinput resista nce deviation
HS-PMA implementation loop delay requirement
Loop delay tLoop td(TXDH-RXDH) delay time from TXD HIGH to
RXD HIGH
td(TXDL-RXDL) delay time from TXD LOW to RXD
LOW
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to
2 Mbit/s and above 2 Mbit/s up to 5 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,
intended tBit(Bus) tbit(bus) transmitted recessive bit width
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s tBit(RXD) tbit(RXD) bit time on pin RXD
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s tRec trec receiver timing symmetry
TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 23 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
[1] tfltr(wake)bus - bus wake-up filter time, in devices with basic wake-up functionality
HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff
Maximum rating VDiff VDiff V(CANH-CANL) voltage between pin CANH and
pin CANL
General maximum rating VCAN_H and VCAN_L VCAN_H
VCAN_L
Vxvoltage on pin x
Optional: Extended maximum rating VCAN_H and VCAN_L
HS-PMA maximum leakage curre nts on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L ICAN_H
ICAN_L
ILleakage current
HS-PMA bus biasing control timing s
CAN activity filter time, long tFilter twake(busdom)[1] bus dominant wake-up time
CAN activity filter time, short twake(busrec)[1] bus recessive wake-up time
Wake-up timeout, short tWake tto(wake)bus bus wake-up time-out time
Wake-up timeout, long
Timeout for bus inactivity tSilence tto(silence) bus silence time-out time
Bus Bias reaction time tBias td(busact-bias) delay time from bus active to bias
Table 11. ISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016 NXP data sheet
Parameter Notation Symbol Parameter
TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 24 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
19. Revision history
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TJA1048 v.5 20160523 Product data sheet - TJA1048 v.4
Modifications •Table 3: Table note 1: text revised
•Section 7.1.3 added
•Figure 4 changed
•Table 5:
–Table note 1 added for parameter Vx
–new parameter added: (V(CANH-CANL))
–parameter Vtrt reformatted
•Section 12.1: Figure 7 modified
•ISO 11898-2:201 6 compliance
–Section 1: text revised (3rd paragraph)
–Section 2.1 third list item revised
–Table 5: Table no te 1 added for parameter Vx
–Table 7: Parameter VTX(sym) added; Table note 9 added
–Table 7: Parameters for VO(dom) modified
–Table 7: Parameter VO(dif)bus changed to VO(dif); Conditions revised
–Table 7: Parameter Vth(RX)dif Conditions revised
–Table 7: Parameter Vrec(RX) added
–Table 7: Parameter Vdom(RX) added
–Table 7: Parameter Vhys(RX)dif Conditions revised
–Table 7: Parameter IO(sc)dom Conditions revised
–Table 7: Parameter IL conditions revised
–Table 7: Previous note 9 deleted
–Section 11: Figure 5 and Figure 6 replaced
–Table 8: parameters tbit(bus) and trec added
–Table 8: parameter tPD(RDX-RXD) replaced by td(TXDL-RXDL) and td(TXDH-RXDH)
–Table 8: additional condition and spec ification values added to parameter tbit(RXD)
–Section 13: Figure 9 “Test circuit for measuring transceiver driver symmetry” added
–Section 18 “ Appendix: ISO 11898-2:2016 parameter cross-reference list” added
TJA1048 v.4 20150115 Product data sheet - TJA1048 v.3
TJA1048 v.3 20130424 Product data sheet - TJA1048 v.2
TJA1048 v.2 20110325 Product data sheet - TJA1048 v.1
TJA1048 v.1 20101103 Product data sheet - -
TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 25 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
20. Legal information
20.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict wit h the short data sheet, th e
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and t her efo re su ch inclu si on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for t he customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
TJA1048 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 5 — 23 May 2016 26 of 27
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to se ll product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
20.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors TJA1048
Dual high-speed CAN transceiver with Standby mode
© NXP Semiconductors N.V. 2016. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 May 2016
Document identifier: TJA1048
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
22. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Low-power management . . . . . . . . . . . . . . . . . 2
2.3 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 6
7.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.2 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.3 Remote wake-up (via the CAN bus). . . . . . . . . 6
7.2 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 7
7.2.1 TXD dominant time-out function. . . . . . . . . . . . 7
7.2.2 Internal biasing of TXD1, TXD2, STBN1 and
STBN2 input pins . . . . . . . . . . . . . . . . . . . . . . . 8
7.2.3 Undervoltage detection on pins VCC and VIO . . 8
7.2.4 Overtemperature protection . . . . . . . . . . . . . . . 8
7.3 VIO supply pin. . . . . . . . . . . . . . . . . . . . . . . . . . 8
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
9 Thermal characteristics . . . . . . . . . . . . . . . . . . 9
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 10
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13
12 Application information. . . . . . . . . . . . . . . . . . 15
12.1 Application diagram . . . . . . . . . . . . . . . . . . . . 15
12.2 Application hints . . . . . . . . . . . . . . . . . . . . . . . 15
13 Test information. . . . . . . . . . . . . . . . . . . . . . . . 16
13.1 Quality information . . . . . . . . . . . . . . . . . . . . . 16
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
15 Handling information. . . . . . . . . . . . . . . . . . . . 19
16 Soldering of SMD packages . . . . . . . . . . . . . . 19
16.1 Introduction to soldering . . . . . . . . . . . . . . . . . 19
16.2 Wave and reflow soldering . . . . . . . . . . . . . . . 19
16.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 19
16.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 20
17 Soldering of HVSON packages. . . . . . . . . . . . 21
18 Appendix: ISO 11898-2:2016 parameter
cross-reference list . . . . . . . . . . . . . . . . . . . . . 22
19 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
20.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 25
20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 25
20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26
21 Contact information . . . . . . . . . . . . . . . . . . . . 26
22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27