TDA4863GGEG - Infineon Technologies

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 1

Power Factor Controller

IC for High Power Factor and

low THD

· IC for sinusoidal line -current consumption

· Power fa ctor achieves nearly 1

· Controls boost converter as active harmonic

filter for low THD

· St art up with low current consumption

· Zero current detector for discontinuous oper-

ation mode

· Output overvoltage protection

· Output undervoltage lockout

· Internal start up timer

· Totem pole output wit h active shut down

· Internal leading edge blanking LEB

Improvements referred to TDA 4862

· Suitable for universal input applications with

low THD at low load conditions

· Very low start up current

· Accurate OVR and VISENSEmax threshold

· Competiton compatibel VCC thresholds

· Enable threshold referred to VVSENSE

Boost Contro ller

P-DIP-8-4

The TDA4863 IC controls a boost converter in

a way that sinusoidal current is taken from the

single phase line supply and stabilized DC

voltage is available at the output. This active

harmonic filter limits the harmonic currents

resulting from the capacitor pulsed charge cur-

rents during rectification. The power factor

which descibes the ratio between active and

apparent power is almost one. Line voltage

fluctuations can be compensated very effi-

ciently

Type Ordering Code Package

TDA 4863 Q67040-S4452 P-DIP-8-4

TDA 4863G Q67040-S4451 P-DSO-8-3

AC line DC Output

Volage

GND

TDA4863

RF-Filter

and

Rectifier

P-DSO-8-3

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 2

Pin Connections

Pin Description

Pin1 VSENSE (voltage amplifier inverting input)

VSENSE is connected via a resistive divider to the boost converter output. With a capacitor connected to

VAOUT the internal error amplifier acts as an integrator.

Pin2 VAOUT (voltage amplifier output)

VAOUT is connected internally to the first multiplier input. To prevent overshoot the input voltage will be

clamped internally at 5V. Input voltage less then 2.2V inhibits the gate driver.If the current flowing into this pin

is exceeding an internal threshold the multiplier output voltage is rdeuced to prevent the MOSFET from

overvoltage damage.

Pin 3 MULTIN (multipier input)

MULTIN is the second multiplier input and is connected via a resistive divider to the rectifier output voltage.

Pin 4 ISENSE (current sense input)

ISENSE is connected to a sense resistor controlling the MOSFET source current. The input is internally

clamped at -0.3V to prevent negative input voltage interaction. A leading edge blanking circuitry suppresses

voltage spik s when turning the MO SF E T on.

Pin 5 DETIN (Zero current detector input)

DETIN is connected to an auxiliary winding monitoring the zero crossing of the inductor current.

Pin 6 GND (Ground)

Pin 7 GTDRV (Gate driver output)

GTDRV is the output of a totem-pole circuitry for direct driving a MOSFET. An active shutdown circuitry

ensures that GTDRV is low if the IC is switched off.

Pin 8 Vcc (Positive voltage supply)

If Vcc exceeds the turn-on threshold the IC is switched on. When Vcc falls below the turn-off threshold it is

switched off and power consumption is very low. An auxilliary winding is charging a capacitor which provides

the supply current. A second 100nF ceramic capacitor should be added to Vcc to absorbe supply current

spikes required to charge the MOSFET gate capacitance.

Pin Symbol Function

1 VSENSE Voltage amplifier inverting input

2 VAOUT Voltage amplifier output

3 MULTIN Mult iplie r inp ut

4 ISENSE Current sense input

5 DETIN Zero current detector input

6 GND Ground

7 GTDRV Gate driver output

8 VCC Positive voltage supply

1 VSENSE

2 VAOUT

3 MULTIN

4 ISENSE

8 VCC

7 GTDRV

6 GND

5 DETIN

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 3

Block Diagram

Functional Description

Introduction

Conventional electronic ballasts and switching power supplies are designed with a bridge rectifier

and a bulk capacitor. Their disadvantage is that the circuit draws power from the line when the

instantaneous AC voltage exceeds the capacitors voltage. This occurs near the line voltage peak

and causes a high charge cur rent spike with foll owing character istics: The app arent power is higher

than the real power that means low power factor condition, the current spikes are non sinusoidal

with a high content of harmonics causing line noise, the rectified voltage depends on load condition

and requires a large bulk capacitor, special efforts in noise suppression are necessary.

With the TDA4863 preconverter a sinusoidal current is achieved which varies in direct instantane-

ous proportional to the input voltage half sine wave and so provides a power factor near 1. This is

due to the appearence of almost any complex load like a resistive one at the AC line. The harmoni c

distortions are reduced and comply with the IEC555 standard requirements.

GTDRV

Reference

Voltage

Vref

Gate

Drive

Voltage

Amp

Multiplier

Flip-Flop

UVLO

Restart

Timer

Detector

VSENSE VAOUT MULTIN ISENSE

DETINVCC GND

Current

Comp

multout

Inhibit

time delay

2.2V

0.2V

2.5V

uvlo

active

shu t down

1.5V

1.0V

12.5V

10V

dVA

=2us

res

=150us

dsd

=70ns

20V

Inhibit

Enable

OVR

0.5V

3.5V

Vref

Clamp

Current

5.4V

LEB

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 4

IC Description

The TDA4863 contains a wide bandwidth voltage amplifier used in a feedback loop, an overvoltage

regulator, an one quadrant multi plier wit h a wide linear operating ra nge, a curr ent sense comp arator,

a zero curr ent detect or, a PWM and l ogic circ uitr y, a totem-p ole MOSFET dri ver, an internal t rimmed

voltage reference, a restart timer and an undervoltage lockout circuitry.

Voltage Amplif ier

With an external capacitor between VSENSE and VAOUT the voltage amplifier forms an integrator.

The integrat or moni tors t he av erage out put voltage over several li ne c ycles. Typical ly t he int egrator s

bandwidt h is set below 20 Hz in order to suppress the 100 Hz ripple of the recti fied li ne volt ag e. The

voltage amplifier is internally compensated and has a gain bandwidth of 3 MHz and a phase margin

of 80 degrees. The non-inverting input is biased internally at 2.5V. The output is directly connected

to the multiplier input.

The gate drive is disabled when VSENSE vol tage is less than 0.2 V or VVAOUT voltage is less than

2.2 V.

If the MOSFET i s placed n earby the con troller switching inteferences have to be taken into account.

The output of the voltage amplifier is designed in a way to minimiz e these inteferen ces.

Overvoltage Reg ulator

Because of the integrators low bandwidth fast changes of the output voltage can’t be regulated

whithin an adequate time. Fast output changes occure during initial start-up, sudden load removal,

or output arcing. While the integrators differential input voltage remains zero during this fast

changes a peak current is flowing through the external capacitor into pin VAOUT. If this current

exceeds an internal defined margin the overvoltage regulator circuitry reduces the multiplier output

volt age. As a result the on time of the MOSFET is reduced.

Multiplier

The one quadrant multiplier regulates the gate driver with respect of the DC output voltage and the

AC half wave rectified input voltage. Both inputs are designed to achieve good linearity over a wide

dynamic range to represent an AC line free from distortion. Special efforts are made to assure uni-

versal line applications with respect to a 90 to 270 V AC range.

The multiplier output is internally clamped at 1.3V. So the MOSFET is protected against critical

operating during start up.

Current sense comparator, LEB and RS Flip-Flop

An external sense resistor transferes the source current of the MOSFET into a sense voltage.The

multipli er output volt age is compared with this sense voltage.

To protect the current comparator input from negative pulses a current source is inserted which

sends current out of the ISENSE pin every time when ISENSE is falling below ground potential..

The switch-on current peak of the MOSFET is blanked out via an leading edge blanking circuit with

a blanking time of ty ically 200ns.

The RS Flip-Flop ensures that only one single switch-on and switch-off pulse appears at the gate

drive output dur ing a given cycle (double puls e suppression).

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 5

Zero Current Detector

The zero current detector senses the inductor current via an auxiliary winding and ensures that the

next on-time of the MOSFET is initiated immediately when the inductor current has reached zero.

This diminishes the revers recovery losses of the boost converter diode. The MOSFET is switched

off when the voltage drop of the shunt resistor reaches the voltage level of the multipler output. So

the boost current waveform has a triangular shape and there are no deadtime gaps between the

cycles. This leads to a continuous AC line current limiting the peak current to twice of the average

current.

To prevent false tri pping the zero current detector is designed as a Schmitt-Trigger with a hysteresi s

of 0.5V. An internal 5V clamp protects the input from overvoltage breadkdown, a 0.6V clamp pre-

vents substrate injection. An external resistor has to be used in series with the auxiliary winding to

limit the cur rent through the clamps.

Restart Timer

The restart timer function eliminates the need of an oscillator when. The timer starts or restarts the

TDA4863 when the driver output has been off for more than 150us after the inductor current

reaches zero .

Undervoltage Lockout

An undervoltage lockout circuitry switches the IC on when Vcc reaches the upper threshold VCCH

and switches the IC off when Vcc is falling below the lower threshold VCCL. During start up the sup-

ply current is less then 100uA.

An internal voltage clamp has been added to protect the IC from Vcc overvoltage condition. When

using this clamp special care must be t a ken on power dissipation.

Start up current is provided by an external start up resistor which is connected from the AC line to

the input supply voltage Vcc and a storage capacitor which is connected from Vcc to ground. Be

aware that this capacitor is discharged befor the IC is plugged into the application board. Otherwise

the IC can be destroyed due to the high capacitor voltage.

Bootstrap power supply is created with the previous mentioned auxiliary winding and a diode (see

application circuit).

Gate Drive

The TDA4863 totem pole output stage is MOSFET compat ible. An internal protection ciruitry is acti-

vated when Vcc is within the start up phase and ensures that the MOSFET is turned off. The totem

pole output has been optimized to minimize cross conduction current during high speed operation.

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 6

Signal Diagrams

DETIN

GTDRV

LEB

VISENSE multout

IVAOUT

Icoil

OVR

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 7

Absolute maximum ratings

Parameter Symbol Min Max Unit Remark

Supply + Zener Current ICCH+Iz - 20 mA

Supply Voltage VCC -0.3 Vz V V z=Z ene r Voltage

Icc+Iz=20mA

Voltage at Pin 1,3,4 -0.3 6.5 V

Current into Pin 2 IVAOUT -10 30 mA

mA VAOUT=4V,VSENSE=2.8V

VAOUT=0V,VSENSE=2.3V

t<1ms

Current into Pin 5 IDETIN -10 10 mA

mA DETIN > 6V

DETIN< 0.4V

t<1ms

Current into Pin 7 IGTDRV -500 500 mA t<1ms

ESD Protection 2000 V MIL STD 883C method

3015.6, 100pF,15009

Storage Temperature Tstg -50 150 °C

Operating Junction Temper-

ature TJ-40 150 °C

Thermal Resistance

Junction-Ambient RthJA 100

180 K/W

K/W P-DIP-8

P-DSO-8

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 8

Characteristics

Unless otherwise stated, -40°C<Tj <150 °C, VCC = 14.5V

Parameter Symbol min. typ. max. Unit Test Condition

Start-Up ci rcuit

Zener Voltage Vz 18 20 22 V Icc+Iz=20mA

Start-up supply current ICCL 20 100 uA Vcc=VCCON - 0.5V

Oper ating supply curr ent ICCH 4 6 mA Output low

Vcc Turn-ON threshold VCCON 12 12.5 13 V

Vcc Turn-OFF threshold VCCOFF 9.5 10 10. 5 V

Vcc Hyst eresi s VCCHY 2.5

Voltage Amplif ier

Voltage feedback Input

Threshold VFB 2.45 2.5 2.55 V

Line regulation VFBLR 5mVV

CC=12V to 16V

Open Loop V oltage Gain1) GV100 dB

Unity Gain Bandwidth1)B

W5MHz

Phase Margin1) M 80 Degr

Bias current VSENSE IBVSENSE -1.0 -0.3 uA

Enable T hres hol d VVSENSE 0.2 V

Inhibit Th reshold Voltage VVAOUTI 2.2 V VISENSE= -0.1V

Inhibit Time Delay tdVA 3usV

ISENSE= -0.1V

Output Current Source IVAOUTH -6 mA VAOUT=0V

VSENSE=2.3V, t<1ms

Output Current Sink IVAOUTL 30 mA VAOUT=4V

VSENSE=2.8V,t<1ms

Upper Clamp Voltage VVAOUTH 5.4 V VSENSE=2.3V, I= -0.2mA

Lower Clamp Voltage VVAOUTL 1.1 V VSENSE=2.8V, I=0.5mA

Overvoltage Reg ulator

Threshold Current IOVR 35 40 45 uA Tj=25°C

1) guaranteed by design, not tested

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 9

Current Comparator

Input Bias Current IBISENSE -1 -0.2 1 uA VISENSE=0V

Input Offset Volta ge VISENSEO 25 mV VAOUT=2.7V

Max Threshold Voltage VISENSEM 0.95 1.0 1.05 V

Threshold at OVR VISENOVR 0.05 V IOVR=50uA

Leading Edge Blanking tLEB 200 ns

Shut Down Delay tdISG 80 ns

Detector

Upper threshold voltage VDETINU 1.5 V

Lower threshold voltage VDETINL 1V

Hysteresis VDETINHY 0.5 V

Input curr en t IBDETIN -1 -0.2 1 uA VDETIN=2V

Input clamp volta ge

High state

Low state VDETINHC

VDETINLC

0.5 IDETIN=5mA

IDETIN=-5mA

Multiplier

Input bias cur ren t IBMULTIN -1 -0.2 1 uA VMULTIN=0V

Dynamic voltage range

MULTIN VMULTIN 0 to 4 V VVAOUT=2.75V

Dynamic voltage range

VAOUT VVAOUT

VFB to

VFB+1.

5VMULTIN=1V

Mult ipl ier Gain Klow

Khigh 0.3

0.7 VVAOUT<3V, VMULTIN=1V

VVAOUT>3.5V,VMULTIN=1V

K=delta VVISENSE/deltaVVAOUT at VMULTIN=constant

Restart Timer

restart time tRES 100 160 250 us

Parameter Symbol min. typ. max. Unit Test Condition

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 10

Gate Drive

Output voltage low state

VGTL

1.0

1.7

2.2

IGT= 2mA

IGT= 20mA

IGT=200mA

Output voltage high state

VGTH

10.9

10.7

9.6

IGT=-20mA

IGT=-200mA

IGT=-2mA, VCC=11V

see Diagram 14

Output voltage active shut

down VGTSD 1VI

GT=20mA, VCC=9V

Rise time

Fall time trise

tfall 80

55 180

120 ns

ns CGT= 4.7nF Vout=2...8V

CGT= 4.7nF Vout=2...8V

Parameter Symbol min. typ. max. Unit Test Condition

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 11

Electric al Diagrams

Diagram 2: VCCON/OFF versus

Temperature

-40 0 40 80 120 160

Tj / °C

Vcc / V

VCC ON

VCC OFF

Diagram 1: Icc versus Vcc

0,5

1,5

2,5

3,5

4,5

0 5 10 15 20

Vcc/V

Icc / mA

VCC ON

VCC OFF

Diagram 3: Iccl ver sus Vcc

0246810121416

Vcc / V

Iccl / uA

Diagram 4: ICCL versus

Temp eratu re, VCC=10V

-40 0 40 80 120 160

Tj / °C

ICCL / uA

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 12

Diagr am 6: Open loop gain and

Phase versus frequency

100

120

0,01 0,1 1 10 100 1000 10000

f/kHz

100

120

140

160

180

Phi/deg

GV/dB

Phi

Diagr am 7: Overvolt age R egulat or

VISENSE vers. Threshold Volt age

0,2

0,4

0,6

0,8

1,2

35 37 39 41 43 45

Iovp / uA

VISENSE / V

VVAOUT = 3. 5V

VMULTIN = 3. 0V

Diagram 5: VFB vers. Temperature

(pin1 connecte d to pin2)

2,45

2,46

2,47

2,48

2,49

2,5

2,51

2,52

2,53

2,54

2,55

-40 0 40 80 120 160

Tj / °C

VFB / V

Di agra m 8: Leading edge

bl anki ng ve rs. Tem p.

100

150

200

250

300

-40 0 40 80 120 160

Tj / °C

LEB / ns

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 13

Diagr am 9: Current Sense

Threshold VISENSE versus VMULTIN

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

01234

VMULTIN / V

VISENSE

/ V

VAOUT=2.75V

3.0V

3.5V

4.0V

4.5V

3.25V

Diagr am 10: C urrent sense

threshold VISENSE versus VVAOUT

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

2,5 3 3,5 4 4,5

VVAOUT / V

VISENSE / V

1.0

1.5

2.0

3.0

Vmultin=4.0

0.5

0.25

Diagram 11: Restart time versus

temperature

100

120

140

160

180

200

220

-40 0 40 80 120 160

Tj / °C

trst / us

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 14

Diag r am 12 : G ate Dr i v e Ri se

Tim e a nd Fal l Tim e ve rs.

temperature

100

120

140

-40 0 40 80 120 160

Tj / °C

rise time / ns

rise

time

fall

time

Diagram 13: Gate drive voltage

hi gh sta te versus Vcc

8,5

9,5

10,5

11,5

11 13 15

Vcc / V

GTH

/ V

IGT=-2mA

IGT=-20mA

IGT=-200mA

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 15

Vin

90-270V AC

220n

33k

9.1k

R6B

470k

C10

47uF

25V

47uF

450V

R11

0.5

R4A

820k

10k

TDA4863

R10

R4B

820k

MR856

R12

470

R8A

120k R8B

120k

R6A

470k

10n

9.1k

C13

3.3n

400V

CoolMOS

SPP04N60S5

0.95 Ohm

1234

5678

Vout

410V DC

Application circuit: Pout=110W, universal Input Vin=90-270V AC

GND

L1=750uH

E36/11,N27; gap=2mm

W1=85 turns,d=40x0.1

W2=17 turns, d=0.3

RF filter

and

rectifier

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 16

Results of THD measurements with application board Pout=110W

Diagram:THD Class C: Pmax=110W, Vinac=90V, Iout=250mA, Vout=420, PF=0.998

Diagramm: THD ClassC: Pmax=110W, Vinac=220V, Iout=250mA, Vaout=420V, PF=0.992

Diagramm: THD ClassC: Pmax=110W, Vinac=270V, Iout=250mA, Vaout=420V, PF=0.978

0,00

0,05

0,10

0,15

0,20

0,25

0,30

Current RMS(Amps)

Harmonic #

4 8 12 16 20 24 28 32 36 40

0,000

0,025

0,050

0,075

0,100

0,125

0,150

0,175

0,200

0,225

Current RMS(Amps)

Harmonic

4 8 12 16 20 24 28 32 36 40

0,000

0,025

0,050

0,075

0,100

0,125

0,150

0,175

Current RMS(Amps)

Harmonic #

4 8 12 16 20 24 28 32 36 40

preliminary TDA4863

Infineon Tech PCI Group 14.02.02 17

Diagramm: THD ClassC: Pmax=110W, Vinac=90V, Iout=140mA, Vaout=420V, PF=0.999

Diagramm: THD ClassC: Pmax=110W, Vinac=270V, Iout=140mA, Vaout=420V, PF=0.975

Diagramm: THD ClassC: Pmax=110W, Vinac=270V, Iout=140mA, Vaout=420V, PF=0.883

0,00

0,05

0,10

0,15

0,20

0,25

0,30

Current RMS(Amps)

Harmonic #

4 8 12 16 20 24 28 32 36 40

0,000

0,025

0,050

0,075

0,100

0,125

Current RMS(Amps)

Harmonic

4 8 12 16 20 24 28 32 36 40

0,00

0,01

0,02

0,03

0,04

0,05

0,06

0,07

0,08

0,09

0,10

Current RMS(Amps)

Harmonic #

4 8 12 16 20 24 28 32 36 40